iMX6: Disable the L2 before chaning the PL310 latency

The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ac84a1fbfb6517a737557418fc253bf2ad7aebbe..be4bf24020f1d6b294f7d6ff5171b4e5be9feb82 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -430,6 +430,9 @@ void v7_outer_cache_enable(void)
        }
 #endif
 
+       /* Must disable the L2 before changing the latency parameters */
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
        writel(0x132, &pl310->pl310_tag_latency_ctrl);
        writel(0x132, &pl310->pl310_data_latency_ctrl);