--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_common_tables.h\r
+ * Description: Extern declaration for common tables\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef _ARM_COMMON_TABLES_H\r
+#define _ARM_COMMON_TABLES_H\r
+\r
+#include "arm_math.h"\r
+\r
+extern const uint16_t armBitRevTable[1024];\r
+extern const q15_t armRecipTableQ15[64];\r
+extern const q31_t armRecipTableQ31[64];\r
+extern const float32_t twiddleCoef_16[32];\r
+extern const float32_t twiddleCoef_32[64];\r
+extern const float32_t twiddleCoef_64[128];\r
+extern const float32_t twiddleCoef_128[256];\r
+extern const float32_t twiddleCoef_256[512];\r
+extern const float32_t twiddleCoef_512[1024];\r
+extern const float32_t twiddleCoef_1024[2048];\r
+extern const float32_t twiddleCoef_2048[4096];\r
+extern const float32_t twiddleCoef_4096[8192];\r
+#define twiddleCoef twiddleCoef_4096\r
+extern const q31_t twiddleCoef_16_q31[24];\r
+extern const q31_t twiddleCoef_32_q31[48];\r
+extern const q31_t twiddleCoef_64_q31[96];\r
+extern const q31_t twiddleCoef_128_q31[192];\r
+extern const q31_t twiddleCoef_256_q31[384];\r
+extern const q31_t twiddleCoef_512_q31[768];\r
+extern const q31_t twiddleCoef_1024_q31[1536];\r
+extern const q31_t twiddleCoef_2048_q31[3072];\r
+extern const q31_t twiddleCoef_4096_q31[6144];\r
+extern const q15_t twiddleCoef_16_q15[24];\r
+extern const q15_t twiddleCoef_32_q15[48];\r
+extern const q15_t twiddleCoef_64_q15[96];\r
+extern const q15_t twiddleCoef_128_q15[192];\r
+extern const q15_t twiddleCoef_256_q15[384];\r
+extern const q15_t twiddleCoef_512_q15[768];\r
+extern const q15_t twiddleCoef_1024_q15[1536];\r
+extern const q15_t twiddleCoef_2048_q15[3072];\r
+extern const q15_t twiddleCoef_4096_q15[6144];\r
+extern const float32_t twiddleCoef_rfft_32[32];\r
+extern const float32_t twiddleCoef_rfft_64[64];\r
+extern const float32_t twiddleCoef_rfft_128[128];\r
+extern const float32_t twiddleCoef_rfft_256[256];\r
+extern const float32_t twiddleCoef_rfft_512[512];\r
+extern const float32_t twiddleCoef_rfft_1024[1024];\r
+extern const float32_t twiddleCoef_rfft_2048[2048];\r
+extern const float32_t twiddleCoef_rfft_4096[4096];\r
+\r
+/* floating-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)\r
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)\r
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)\r
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)\r
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)\r
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)\r
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)\r
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)\r
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];\r
+\r
+/* fixed-point bit reversal tables */\r
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)\r
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)\r
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)\r
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)\r
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)\r
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)\r
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)\r
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\r
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\r
+\r
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\r
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\r
+\r
+/* Tables for Fast Math Sine and Cosine */\r
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\r
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\r
+\r
+#endif /* ARM_COMMON_TABLES_H */\r
--- /dev/null
+/* ----------------------------------------------------------------------\r
+ * Project: CMSIS DSP Library\r
+ * Title: arm_const_structs.h\r
+ * Description: Constant structs that are initialized for user convenience.\r
+ * For example, some can be given as arguments to the arm_cfft_f32() function.\r
+ *\r
+ * $Date: 27. January 2017\r
+ * $Revision: V.1.5.1\r
+ *\r
+ * Target Processor: Cortex-M cores\r
+ * -------------------------------------------------------------------- */\r
+/*\r
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef _ARM_CONST_STRUCTS_H\r
+#define _ARM_CONST_STRUCTS_H\r
+\r
+#include "arm_math.h"\r
+#include "arm_common_tables.h"\r
+\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\r
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\r
+\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\r
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\r
+\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\r
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file arm_math.h\r
+ * @brief Public header file for CMSIS DSP LibraryU\r
+ * @version V1.5.3\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/**\r
+ \mainpage CMSIS DSP Software Library\r
+ *\r
+ * Introduction\r
+ * ------------\r
+ *\r
+ * This user manual describes the CMSIS DSP software library,\r
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.\r
+ *\r
+ * The library is divided into a number of functions each covering a specific category:\r
+ * - Basic math functions\r
+ * - Fast math functions\r
+ * - Complex math functions\r
+ * - Filters\r
+ * - Matrix functions\r
+ * - Transforms\r
+ * - Motor control functions\r
+ * - Statistical functions\r
+ * - Support functions\r
+ * - Interpolation functions\r
+ *\r
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,\r
+ * 32-bit integer and 32-bit floating-point values.\r
+ *\r
+ * Using the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\r
+ * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)\r
+ * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)\r
+ * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)\r
+ * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)\r
+ * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)\r
+ * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)\r
+ * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)\r
+ * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)\r
+ * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)\r
+ * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)\r
+ * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)\r
+ * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)\r
+ * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)\r
+ * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)\r
+ * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)\r
+ * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)\r
+ * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)\r
+ * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)\r
+ * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)\r
+ *\r
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\r
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\r
+ * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\r
+ * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\r
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\r
+ * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.\r
+ * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.\r
+ * \r
+ *\r
+ * Examples\r
+ * --------\r
+ *\r
+ * The library ships with a number of examples which demonstrate how to use the library functions.\r
+ *\r
+ * Toolchain Support\r
+ * ------------\r
+ *\r
+ * The library has been developed and tested with MDK version 5.14.0.0\r
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\r
+ *\r
+ * Building the Library\r
+ * ------------\r
+ *\r
+ * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.\r
+ * - arm_cortexM_math.uvprojx\r
+ *\r
+ *\r
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.\r
+ *\r
+ * Preprocessor Macros\r
+ * ------------\r
+ *\r
+ * Each library project have different preprocessor macros.\r
+ *\r
+ * - UNALIGNED_SUPPORT_DISABLE:\r
+ *\r
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\r
+ *\r
+ * - ARM_MATH_BIG_ENDIAN:\r
+ *\r
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\r
+ *\r
+ * - ARM_MATH_MATRIX_CHECK:\r
+ *\r
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\r
+ *\r
+ * - ARM_MATH_ROUNDING:\r
+ *\r
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions\r
+ *\r
+ * - ARM_MATH_CMx:\r
+ *\r
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\r
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\r
+ * ARM_MATH_CM7 for building the library on cortex-M7.\r
+ *\r
+ * - ARM_MATH_ARMV8MxL:\r
+ *\r
+ * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library\r
+ * on Armv8-M Mainline target.\r
+ *\r
+ * - __FPU_PRESENT:\r
+ *\r
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.\r
+ *\r
+ * - __DSP_PRESENT:\r
+ *\r
+ * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.\r
+ *\r
+ * <hr>\r
+ * CMSIS-DSP in ARM::CMSIS Pack\r
+ * -----------------------------\r
+ *\r
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\r
+ * |File/Folder |Content |\r
+ * |------------------------------|------------------------------------------------------------------------|\r
+ * |\b CMSIS\\Documentation\\DSP | This documentation |\r
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |\r
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |\r
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |\r
+ *\r
+ * <hr>\r
+ * Revision History of CMSIS-DSP\r
+ * ------------\r
+ * Please refer to \ref ChangeLog_pg.\r
+ *\r
+ * Copyright Notice\r
+ * ------------\r
+ *\r
+ * Copyright (C) 2010-2015 Arm Limited. All rights reserved.\r
+ */\r
+\r
+\r
+/**\r
+ * @defgroup groupMath Basic Math Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFastMath Fast Math Functions\r
+ * This set of functions provides a fast approximation to sine, cosine, and square root.\r
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions\r
+ * operate on individual values and not arrays.\r
+ * There are separate functions for Q15, Q31, and floating-point data.\r
+ *\r
+ */\r
+\r
+/**\r
+ * @defgroup groupCmplxMath Complex Math Functions\r
+ * This set of functions operates on complex data vectors.\r
+ * The data in the complex arrays is stored in an interleaved fashion\r
+ * (real, imag, real, imag, ...).\r
+ * In the API functions, the number of samples in a complex array refers\r
+ * to the number of complex values; the array contains twice this number of\r
+ * real values.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupFilters Filtering Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupMatrix Matrix Functions\r
+ *\r
+ * This set of functions provides basic matrix math operations.\r
+ * The functions operate on matrix data structures. For example,\r
+ * the type\r
+ * definition for the floating-point matrix structure is shown\r
+ * below:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows; // number of rows of the matrix.\r
+ * uint16_t numCols; // number of columns of the matrix.\r
+ * float32_t *pData; // points to the data of the matrix.\r
+ * } arm_matrix_instance_f32;\r
+ * </pre>\r
+ * There are similar definitions for Q15 and Q31 data types.\r
+ *\r
+ * The structure specifies the size of the matrix and then points to\r
+ * an array of data. The array is of size <code>numRows X numCols</code>\r
+ * and the values are arranged in row order. That is, the\r
+ * matrix element (i, j) is stored at:\r
+ * <pre>\r
+ * pData[i*numCols + j]\r
+ * </pre>\r
+ *\r
+ * \par Init Functions\r
+ * There is an associated initialization function for each type of matrix\r
+ * data structure.\r
+ * The initialization function sets the values of the internal structure fields.\r
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\r
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.\r
+ *\r
+ * \par\r
+ * Use of the initialization function is optional. However, if initialization function is used\r
+ * then the instance structure cannot be placed into a const data section.\r
+ * To place the instance structure in a const data\r
+ * section, manually initialize the data structure. For example:\r
+ * <pre>\r
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\r
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\r
+ * </pre>\r
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\r
+ * specifies the number of columns, and <code>pData</code> points to the\r
+ * data array.\r
+ *\r
+ * \par Size Checking\r
+ * By default all of the matrix functions perform size checking on the input and\r
+ * output matrices. For example, the matrix addition function verifies that the\r
+ * two input matrices and the output matrix all have the same number of rows and\r
+ * columns. If the size check fails the functions return:\r
+ * <pre>\r
+ * ARM_MATH_SIZE_MISMATCH\r
+ * </pre>\r
+ * Otherwise the functions return\r
+ * <pre>\r
+ * ARM_MATH_SUCCESS\r
+ * </pre>\r
+ * There is some overhead associated with this matrix size checking.\r
+ * The matrix size checking is enabled via the \#define\r
+ * <pre>\r
+ * ARM_MATH_MATRIX_CHECK\r
+ * </pre>\r
+ * within the library project settings. By default this macro is defined\r
+ * and size checking is enabled. By changing the project settings and\r
+ * undefining this macro size checking is eliminated and the functions\r
+ * run a bit faster. With size checking disabled the functions always\r
+ * return <code>ARM_MATH_SUCCESS</code>.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupTransforms Transform Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupController Controller Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupStats Statistics Functions\r
+ */\r
+/**\r
+ * @defgroup groupSupport Support Functions\r
+ */\r
+\r
+/**\r
+ * @defgroup groupInterpolation Interpolation Functions\r
+ * These functions perform 1- and 2-dimensional interpolation of data.\r
+ * Linear interpolation is used for 1-dimensional data and\r
+ * bilinear interpolation is used for 2-dimensional data.\r
+ */\r
+\r
+/**\r
+ * @defgroup groupExamples Examples\r
+ */\r
+#ifndef _ARM_MATH_H\r
+#define _ARM_MATH_H\r
+\r
+/* Compiler specific diagnostic adjustment */\r
+#if defined ( __CC_ARM )\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+\r
+#elif defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+#elif defined ( __ICCARM__ )\r
+\r
+#elif defined ( __TI_ARM__ )\r
+\r
+#elif defined ( __CSMC__ )\r
+\r
+#elif defined ( __TASKING__ )\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+\r
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */\r
+\r
+#if defined(ARM_MATH_CM7)\r
+ #include "core_cm7.h"\r
+ #define ARM_MATH_DSP\r
+#elif defined (ARM_MATH_CM4)\r
+ #include "core_cm4.h"\r
+ #define ARM_MATH_DSP\r
+#elif defined (ARM_MATH_CM33)\r
+ #include "core_cm33.h"\r
+ #define ARM_MATH_DSP\r
+#elif defined (ARM_MATH_CM3)\r
+ #include "core_cm3.h"\r
+#elif defined (ARM_MATH_CM0)\r
+ #include "core_cm0.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_CM0PLUS)\r
+ #include "core_cm0plus.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_ARMV8MBL)\r
+ #include "core_armv8mbl.h"\r
+ #define ARM_MATH_CM0_FAMILY\r
+#elif defined (ARM_MATH_ARMV8MML)\r
+ #include "core_armv8mml.h"\r
+ #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))\r
+ #define ARM_MATH_DSP\r
+ #endif\r
+#else\r
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"\r
+#endif\r
+\r
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */\r
+#include "string.h"\r
+#include "math.h"\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Macros required for reciprocal calculation in Normalized LMS\r
+ */\r
+\r
+#define DELTA_Q31 (0x100)\r
+#define DELTA_Q15 0x5\r
+#define INDEX_MASK 0x0000003F\r
+#ifndef PI\r
+ #define PI 3.14159265358979f\r
+#endif\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Fast math approximations\r
+ */\r
+\r
+#define FAST_MATH_TABLE_SIZE 512\r
+#define FAST_MATH_Q31_SHIFT (32 - 10)\r
+#define FAST_MATH_Q15_SHIFT (16 - 10)\r
+#define CONTROLLER_Q31_SHIFT (32 - 9)\r
+#define TABLE_SPACING_Q31 0x400000\r
+#define TABLE_SPACING_Q15 0x80\r
+\r
+ /**\r
+ * @brief Macros required for SINE and COSINE Controller functions\r
+ */\r
+ /* 1.31(q31) Fixed value of 2/360 */\r
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\r
+#define INPUT_SPACING 0xB60B61\r
+\r
+ /**\r
+ * @brief Macro for Unaligned Support\r
+ */\r
+#ifndef UNALIGNED_SUPPORT_DISABLE\r
+ #define ALIGN4\r
+#else\r
+ #if defined (__GNUC__)\r
+ #define ALIGN4 __attribute__((aligned(4)))\r
+ #else\r
+ #define ALIGN4 __align(4)\r
+ #endif\r
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */\r
+\r
+ /**\r
+ * @brief Error status returned by some functions in the library.\r
+ */\r
+\r
+ typedef enum\r
+ {\r
+ ARM_MATH_SUCCESS = 0, /**< No error */\r
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */\r
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */\r
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */\r
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */\r
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\r
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */\r
+ } arm_status;\r
+\r
+ /**\r
+ * @brief 8-bit fractional data type in 1.7 format.\r
+ */\r
+ typedef int8_t q7_t;\r
+\r
+ /**\r
+ * @brief 16-bit fractional data type in 1.15 format.\r
+ */\r
+ typedef int16_t q15_t;\r
+\r
+ /**\r
+ * @brief 32-bit fractional data type in 1.31 format.\r
+ */\r
+ typedef int32_t q31_t;\r
+\r
+ /**\r
+ * @brief 64-bit fractional data type in 1.63 format.\r
+ */\r
+ typedef int64_t q63_t;\r
+\r
+ /**\r
+ * @brief 32-bit floating-point type definition.\r
+ */\r
+ typedef float float32_t;\r
+\r
+ /**\r
+ * @brief 64-bit floating-point type definition.\r
+ */\r
+ typedef double float64_t;\r
+\r
+ /**\r
+ * @brief definition to read/write two 16 bit values.\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #define __SIMD32_TYPE int32_t __packed\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE __attribute__((always_inline))\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE __attribute__((always_inline))\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE __attribute__((always_inline))\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __SIMD32_TYPE int32_t __packed\r
+ #define CMSIS_UNUSED\r
+ #define CMSIS_INLINE\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED __attribute__((unused))\r
+ #define CMSIS_INLINE\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __SIMD32_TYPE int32_t\r
+ #define CMSIS_UNUSED\r
+ #define CMSIS_INLINE\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __SIMD32_TYPE __unaligned int32_t\r
+ #define CMSIS_UNUSED\r
+ #define CMSIS_INLINE\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))\r
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))\r
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))\r
+#define __SIMD64(addr) (*(int64_t **) & (addr))\r
+\r
+#if !defined (ARM_MATH_DSP)\r
+ /**\r
+ * @brief definition to pack two 16 bit values.\r
+ */\r
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \\r
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )\r
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \\r
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )\r
+\r
+#endif /* !defined (ARM_MATH_DSP) */\r
+\r
+ /**\r
+ * @brief definition to pack four 8 bit values.\r
+ */\r
+#ifndef ARM_MATH_BIG_ENDIAN\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )\r
+#else\r
+\r
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \\r
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \\r
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\r
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )\r
+\r
+#endif\r
+\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q31 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q63 to Q15 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(\r
+ q63_t x)\r
+ {\r
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q7 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\r
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Clips Q31 to Q15 values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(\r
+ q31_t x)\r
+ {\r
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\r
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\r
+ }\r
+\r
+ /**\r
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\r
+ */\r
+\r
+ CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(\r
+ q63_t x,\r
+ q31_t y)\r
+ {\r
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\r
+ (((q63_t) (x >> 32) * y)));\r
+ }\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\r
+ */\r
+\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(\r
+ q31_t in,\r
+ q31_t * dst,\r
+ q31_t * pRecipTable)\r
+ {\r
+ q31_t out;\r
+ uint32_t tempVal;\r
+ uint32_t index, i;\r
+ uint32_t signBits;\r
+\r
+ if (in > 0)\r
+ {\r
+ signBits = ((uint32_t) (__CLZ( in) - 1));\r
+ }\r
+ else\r
+ {\r
+ signBits = ((uint32_t) (__CLZ(-in) - 1));\r
+ }\r
+\r
+ /* Convert input sample to 1.31 format */\r
+ in = (in << signBits);\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t)(in >> 24);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.31 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);\r
+ tempVal = 0x7FFFFFFFu - tempVal;\r
+ /* 1.31 with exp 1 */\r
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\r
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1U);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(\r
+ q15_t in,\r
+ q15_t * dst,\r
+ q15_t * pRecipTable)\r
+ {\r
+ q15_t out = 0;\r
+ uint32_t tempVal = 0;\r
+ uint32_t index = 0, i = 0;\r
+ uint32_t signBits = 0;\r
+\r
+ if (in > 0)\r
+ {\r
+ signBits = ((uint32_t)(__CLZ( in) - 17));\r
+ }\r
+ else\r
+ {\r
+ signBits = ((uint32_t)(__CLZ(-in) - 17));\r
+ }\r
+\r
+ /* Convert input sample to 1.15 format */\r
+ in = (in << signBits);\r
+\r
+ /* calculation of index for initial approximated Val */\r
+ index = (uint32_t)(in >> 8);\r
+ index = (index & INDEX_MASK);\r
+\r
+ /* 1.15 with exp 1 */\r
+ out = pRecipTable[index];\r
+\r
+ /* calculation of reciprocal value */\r
+ /* running approximation for two iterations */\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);\r
+ tempVal = 0x7FFFu - tempVal;\r
+ /* 1.15 with exp 1 */\r
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);\r
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\r
+ }\r
+\r
+ /* write output */\r
+ *dst = out;\r
+\r
+ /* return num of signbits of out = 1/in value */\r
+ return (signBits + 1);\r
+ }\r
+\r
+\r
+/*\r
+ * @brief C custom defined intrinsic function for M3 and M0 processors\r
+ */\r
+#if !defined (ARM_MATH_DSP)\r
+\r
+ /*\r
+ * @brief C custom defined QADD8 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s, t, u;\r
+\r
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
+\r
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB8 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s, t, u;\r
+\r
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\r
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\r
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;\r
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;\r
+\r
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QADD16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */\r
+ q31_t r = 0, s = 0;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHADD16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHSUB16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QASX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHASX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSAX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SHSAX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ q31_t r, s;\r
+\r
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\r
+\r
+ return ((uint32_t)((s << 16) | (r )));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUSDX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMUADX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QADD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE int32_t __QADD(\r
+ int32_t x,\r
+ int32_t y)\r
+ {\r
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined QSUB for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(\r
+ int32_t x,\r
+ int32_t y)\r
+ {\r
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLAD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLADX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLSDX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint32_t sum)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q31_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLALD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint64_t sum)\r
+ {\r
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\r
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ( ((q63_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMLALDX for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(\r
+ uint32_t x,\r
+ uint32_t y,\r
+ uint64_t sum)\r
+ {\r
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\r
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ( ((q63_t)sum ) ) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUAD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SMUSD for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(\r
+ uint32_t x,\r
+ uint32_t y)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\r
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));\r
+ }\r
+\r
+\r
+ /*\r
+ * @brief C custom defined SXTB16 for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(\r
+ uint32_t x)\r
+ {\r
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\r
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));\r
+ }\r
+\r
+ /*\r
+ * @brief C custom defined SMMLA for M3 and M0 processors\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(\r
+ int32_t x,\r
+ int32_t y,\r
+ int32_t sum)\r
+ {\r
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));\r
+ }\r
+\r
+#endif /* !defined (ARM_MATH_DSP) */\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q7;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ } arm_fir_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ } arm_fir_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 FIR filter.\r
+ * @param[in] S points to an instance of the Q7 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q7(\r
+ const arm_fir_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q7 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed.\r
+ */\r
+ void arm_fir_init_q7(\r
+ arm_fir_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR filter.\r
+ * @param[in] S points to an instance of the Q15 FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_fast_q15(\r
+ const arm_fir_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>numTaps</code> is not a supported value.\r
+ */\r
+ arm_status arm_fir_init_q15(\r
+ arm_fir_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR filter.\r
+ * @param[in] S points to an instance of the Q31 FIR filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_fast_q31(\r
+ const arm_fir_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR filter.\r
+ * @param[in,out] S points to an instance of the Q31 FIR structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ */\r
+ void arm_fir_init_q31(\r
+ arm_fir_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR filter.\r
+ * @param[in] S points to an instance of the floating-point FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_f32(\r
+ const arm_fir_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR filter.\r
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.\r
+ * @param[in] numTaps Number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of samples that are processed at a time.\r
+ */\r
+ void arm_fir_init_f32(\r
+ arm_fir_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_casd_df1_inst_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_casd_df1_inst_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_casd_df1_inst_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 Biquad cascade filter.\r
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cascade_df1_init_q15(\r
+ arm_biquad_casd_df1_inst_q15 * S,\r
+ uint8_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_fast_q15(\r
+ const arm_biquad_casd_df1_inst_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 Biquad cascade filter\r
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_fast_q31(\r
+ const arm_biquad_casd_df1_inst_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cascade_df1_init_q31(\r
+ arm_biquad_casd_df1_inst_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point Biquad cascade filter.\r
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df1_f32(\r
+ const arm_biquad_casd_df1_inst_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df1_init_f32(\r
+ arm_biquad_casd_df1_inst_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float32_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ float64_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_f64;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q15_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 matrix structure.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows of the matrix. */\r
+ uint16_t numCols; /**< number of columns of the matrix. */\r
+ q31_t *pData; /**< points to the data of the matrix. */\r
+ } arm_matrix_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_add_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_add_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix addition.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_add_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_cmplx_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_cmplx_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Q31, complex, matrix multiplication.\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_cmplx_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_trans_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_trans_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix transpose.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>\r
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_trans_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @param[in] pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @param[in] pState points to the array for storing intermediate results\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_fast_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_mult_fast_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_sub_f32(\r
+ const arm_matrix_instance_f32 * pSrcA,\r
+ const arm_matrix_instance_f32 * pSrcB,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_sub_q15(\r
+ const arm_matrix_instance_q15 * pSrcA,\r
+ const arm_matrix_instance_q15 * pSrcB,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix subtraction\r
+ * @param[in] pSrcA points to the first input matrix structure\r
+ * @param[in] pSrcB points to the second input matrix structure\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_sub_q31(\r
+ const arm_matrix_instance_q31 * pSrcA,\r
+ const arm_matrix_instance_q31 * pSrcB,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix scaling.\r
+ * @param[in] pSrc points to the input matrix\r
+ * @param[in] scale scale factor\r
+ * @param[out] pDst points to the output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_scale_f32(\r
+ const arm_matrix_instance_f32 * pSrc,\r
+ float32_t scale,\r
+ arm_matrix_instance_f32 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix scaling.\r
+ * @param[in] pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to output matrix\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_scale_q15(\r
+ const arm_matrix_instance_q15 * pSrc,\r
+ q15_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q15 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix scaling.\r
+ * @param[in] pSrc points to input matrix\r
+ * @param[in] scaleFract fractional portion of the scale factor\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to output matrix structure\r
+ * @return The function returns either\r
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\r
+ */\r
+ arm_status arm_mat_scale_q31(\r
+ const arm_matrix_instance_q31 * pSrc,\r
+ q31_t scaleFract,\r
+ int32_t shift,\r
+ arm_matrix_instance_q31 * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Q31 matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+ void arm_mat_init_q31(\r
+ arm_matrix_instance_q31 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q31_t * pData);\r
+\r
+\r
+ /**\r
+ * @brief Q15 matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+ void arm_mat_init_q15(\r
+ arm_matrix_instance_q15 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ q15_t * pData);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix initialization.\r
+ * @param[in,out] S points to an instance of the floating-point matrix structure.\r
+ * @param[in] nRows number of rows in the matrix.\r
+ * @param[in] nColumns number of columns in the matrix.\r
+ * @param[in] pData points to the matrix data array.\r
+ */\r
+ void arm_mat_init_f32(\r
+ arm_matrix_instance_f32 * S,\r
+ uint16_t nRows,\r
+ uint16_t nColumns,\r
+ float32_t * pData);\r
+\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+#if !defined (ARM_MATH_DSP)\r
+ q15_t A1;\r
+ q15_t A2;\r
+#else\r
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\r
+#endif\r
+ q15_t state[3]; /**< The state array of length 3. */\r
+ q15_t Kp; /**< The proportional gain. */\r
+ q15_t Ki; /**< The integral gain. */\r
+ q15_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ q31_t A2; /**< The derived gain, A2 = Kd . */\r
+ q31_t state[3]; /**< The state array of length 3. */\r
+ q31_t Kp; /**< The proportional gain. */\r
+ q31_t Ki; /**< The integral gain. */\r
+ q31_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point PID Control.\r
+ */\r
+ typedef struct\r
+ {\r
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */\r
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */\r
+ float32_t A2; /**< The derived gain, A2 = Kd . */\r
+ float32_t state[3]; /**< The state array of length 3. */\r
+ float32_t Kp; /**< The proportional gain. */\r
+ float32_t Ki; /**< The integral gain. */\r
+ float32_t Kd; /**< The derivative gain. */\r
+ } arm_pid_instance_f32;\r
+\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point PID Control.\r
+ * @param[in,out] S points to an instance of the PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_f32(\r
+ arm_pid_instance_f32 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the floating-point PID Control.\r
+ * @param[in,out] S is an instance of the floating-point PID Control structure\r
+ */\r
+ void arm_pid_reset_f32(\r
+ arm_pid_instance_f32 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_q31(\r
+ arm_pid_instance_q31 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q31 PID Control structure\r
+ */\r
+\r
+ void arm_pid_reset_q31(\r
+ arm_pid_instance_q31 * S);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID structure.\r
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.\r
+ */\r
+ void arm_pid_init_q15(\r
+ arm_pid_instance_q15 * S,\r
+ int32_t resetStateFlag);\r
+\r
+\r
+ /**\r
+ * @brief Reset function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the q15 PID Control structure\r
+ */\r
+ void arm_pid_reset_q15(\r
+ arm_pid_instance_q15 * S);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point Linear Interpolate function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t nValues; /**< nValues */\r
+ float32_t x1; /**< x1 */\r
+ float32_t xSpacing; /**< xSpacing */\r
+ float32_t *pYData; /**< pointer to the table of Y values */\r
+ } arm_linear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ float32_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q31_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q15_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 bilinear interpolation function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numRows; /**< number of rows in the data table. */\r
+ uint16_t numCols; /**< number of columns in the data table. */\r
+ q7_t *pData; /**< points to the data table. */\r
+ } arm_bilinear_interp_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector multiplication.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_mult_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q15(\r
+ arm_cfft_radix2_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q15(\r
+ const arm_cfft_radix2_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q15;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q15(\r
+ arm_cfft_radix4_instance_q15 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q15(\r
+ const arm_cfft_radix4_instance_q15 * S,\r
+ q15_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix2_instance_q31;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_q31(\r
+ arm_cfft_radix2_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_q31(\r
+ const arm_cfft_radix2_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ } arm_cfft_radix4_instance_q31;\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_q31(\r
+ const arm_cfft_radix4_instance_q31 * S,\r
+ q31_t * pSrc);\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_q31(\r
+ arm_cfft_radix4_instance_q31 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix2_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix2_init_f32(\r
+ arm_cfft_radix2_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix2_f32(\r
+ const arm_cfft_radix2_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\r
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\r
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\r
+ float32_t onebyfftLen; /**< value of 1/fftLen. */\r
+ } arm_cfft_radix4_instance_f32;\r
+\r
+/* Deprecated */\r
+ arm_status arm_cfft_radix4_init_f32(\r
+ arm_cfft_radix4_instance_f32 * S,\r
+ uint16_t fftLen,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+/* Deprecated */\r
+ void arm_cfft_radix4_f32(\r
+ const arm_cfft_radix4_instance_f32 * S,\r
+ float32_t * pSrc);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q15;\r
+\r
+void arm_cfft_q15(\r
+ const arm_cfft_instance_q15 * S,\r
+ q15_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_q31;\r
+\r
+void arm_cfft_q31(\r
+ const arm_cfft_instance_q31 * S,\r
+ q31_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t fftLen; /**< length of the FFT. */\r
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */\r
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */\r
+ uint16_t bitRevLength; /**< bit reversal table length. */\r
+ } arm_cfft_instance_f32;\r
+\r
+ void arm_cfft_f32(\r
+ const arm_cfft_instance_f32 * S,\r
+ float32_t * p1,\r
+ uint8_t ifftFlag,\r
+ uint8_t bitReverseFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q15;\r
+\r
+ arm_status arm_rfft_init_q15(\r
+ arm_rfft_instance_q15 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q15(\r
+ const arm_rfft_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_q31;\r
+\r
+ arm_status arm_rfft_init_q31(\r
+ arm_rfft_instance_q31 * S,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_q31(\r
+ const arm_rfft_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint32_t fftLenReal; /**< length of the real FFT. */\r
+ uint16_t fftLenBy2; /**< length of the complex FFT. */\r
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\r
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\r
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\r
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */\r
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_rfft_instance_f32;\r
+\r
+ arm_status arm_rfft_init_f32(\r
+ arm_rfft_instance_f32 * S,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint32_t fftLenReal,\r
+ uint32_t ifftFlagR,\r
+ uint32_t bitReverseFlag);\r
+\r
+ void arm_rfft_f32(\r
+ const arm_rfft_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.\r
+ */\r
+typedef struct\r
+ {\r
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */\r
+ uint16_t fftLenRFFT; /**< length of the real sequence */\r
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */\r
+ } arm_rfft_fast_instance_f32 ;\r
+\r
+arm_status arm_rfft_fast_init_f32 (\r
+ arm_rfft_fast_instance_f32 * S,\r
+ uint16_t fftLen);\r
+\r
+void arm_rfft_fast_f32(\r
+ arm_rfft_fast_instance_f32 * S,\r
+ float32_t * p, float32_t * pOut,\r
+ uint8_t ifftFlag);\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ float32_t normalize; /**< normalizing factor. */\r
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ float32_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.\r
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_f32(\r
+ arm_dct4_instance_f32 * S,\r
+ arm_rfft_instance_f32 * S_RFFT,\r
+ arm_cfft_radix4_instance_f32 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ float32_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_f32(\r
+ const arm_dct4_instance_f32 * S,\r
+ float32_t * pState,\r
+ float32_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q31_t normalize; /**< normalizing factor. */\r
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q31_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure\r
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_q31(\r
+ arm_dct4_instance_q31 * S,\r
+ arm_rfft_instance_q31 * S_RFFT,\r
+ arm_cfft_radix4_instance_q31 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q31_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the Q31 DCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_q31(\r
+ const arm_dct4_instance_q31 * S,\r
+ q31_t * pState,\r
+ q31_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t N; /**< length of the DCT4. */\r
+ uint16_t Nby2; /**< half of the length of the DCT4. */\r
+ q15_t normalize; /**< normalizing factor. */\r
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */\r
+ q15_t *pCosFactor; /**< points to the cosFactor table. */\r
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */\r
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\r
+ } arm_dct4_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 DCT4/IDCT4.\r
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.\r
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.\r
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.\r
+ * @param[in] N length of the DCT4.\r
+ * @param[in] Nby2 half of the length of the DCT4.\r
+ * @param[in] normalize normalizing factor.\r
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\r
+ */\r
+ arm_status arm_dct4_init_q15(\r
+ arm_dct4_instance_q15 * S,\r
+ arm_rfft_instance_q15 * S_RFFT,\r
+ arm_cfft_radix4_instance_q15 * S_CFFT,\r
+ uint16_t N,\r
+ uint16_t Nby2,\r
+ q15_t normalize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 DCT4/IDCT4.\r
+ * @param[in] S points to an instance of the Q15 DCT4 structure.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.\r
+ */\r
+ void arm_dct4_q15(\r
+ const arm_dct4_instance_q15 * S,\r
+ q15_t * pState,\r
+ q15_t * pInlineBuffer);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector addition.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_add_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector subtraction.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_sub_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a floating-point vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scale scale factor to be applied\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_f32(\r
+ float32_t * pSrc,\r
+ float32_t scale,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q7 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q7(\r
+ q7_t * pSrc,\r
+ q7_t scaleFract,\r
+ int8_t shift,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q15 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q15(\r
+ q15_t * pSrc,\r
+ q15_t scaleFract,\r
+ int8_t shift,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Multiplies a Q31 vector by a scalar.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] scaleFract fractional portion of the scale value\r
+ * @param[in] shift number of bits to shift the result by\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_scale_q31(\r
+ q31_t * pSrc,\r
+ q31_t scaleFract,\r
+ int8_t shift,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q7 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q15 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Q31 vector absolute value.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[out] pDst points to the output buffer\r
+ * @param[in] blockSize number of samples in each vector\r
+ */\r
+ void arm_abs_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of floating-point vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t blockSize,\r
+ float32_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q7 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q7(\r
+ q7_t * pSrcA,\r
+ q7_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q31_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q15 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Dot product of Q31 vectors.\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] blockSize number of samples in each vector\r
+ * @param[out] result output result returned here\r
+ */\r
+ void arm_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t blockSize,\r
+ q63_t * result);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q7(\r
+ q7_t * pSrc,\r
+ int8_t shiftBits,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q15(\r
+ q15_t * pSrc,\r
+ int8_t shiftBits,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_shift_q31(\r
+ q31_t * pSrc,\r
+ int8_t shiftBits,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a floating-point vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_f32(\r
+ float32_t * pSrc,\r
+ float32_t offset,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q7 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q7(\r
+ q7_t * pSrc,\r
+ q7_t offset,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q15 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q15(\r
+ q15_t * pSrc,\r
+ q15_t offset,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Adds a constant offset to a Q31 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[in] offset is the offset to be added\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_offset_q31(\r
+ q31_t * pSrc,\r
+ q31_t offset,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a floating-point vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q7 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q15 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Negates the elements of a Q31 vector.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] blockSize number of samples in the vector\r
+ */\r
+ void arm_negate_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a floating-point vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q7 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q7(\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q15 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Copies the elements of a Q31 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_copy_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a floating-point vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_f32(\r
+ float32_t value,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q7 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q7(\r
+ q7_t value,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q15 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q15(\r
+ q15_t value,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Fills a constant value into a Q31 vector.\r
+ * @param[in] value input value to be filled\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_fill_q31(\r
+ q31_t value,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Convolution of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_conv_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.\r
+ */\r
+ void arm_conv_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Partial convolution of Q7 sequences\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+/**\r
+ * @brief Partial convolution of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] firstIndex is the first output sample to start with.\r
+ * @param[in] numPoints is the number of output points to be computed.\r
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\r
+ */\r
+ arm_status arm_conv_partial_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ uint32_t firstIndex,\r
+ uint32_t numPoints);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR decimator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t M; /**< decimation factor. */\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ } arm_fir_decimate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR decimator.\r
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_f32(\r
+ const arm_fir_decimate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR decimator.\r
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_f32(\r
+ arm_fir_decimate_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator.\r
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_fast_q15(\r
+ const arm_fir_decimate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR decimator.\r
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_q15(\r
+ arm_fir_decimate_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator.\r
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_q31(\r
+ const arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_decimate_fast_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR decimator.\r
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.\r
+ * @param[in] numTaps number of coefficients in the filter.\r
+ * @param[in] M decimation factor.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * <code>blockSize</code> is not a multiple of <code>M</code>.\r
+ */\r
+ arm_status arm_fir_decimate_init_q31(\r
+ arm_fir_decimate_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ uint8_t M,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\r
+ } arm_fir_interpolate_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR interpolator.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t L; /**< upsample factor. */\r
+ uint16_t phaseLength; /**< length of each polyphase filter component. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\r
+ } arm_fir_interpolate_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR interpolator.\r
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_q15(\r
+ const arm_fir_interpolate_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR interpolator.\r
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_q15(\r
+ arm_fir_interpolate_instance_q15 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR interpolator.\r
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_q31(\r
+ const arm_fir_interpolate_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR interpolator.\r
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_q31(\r
+ arm_fir_interpolate_instance_q31 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR interpolator.\r
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_interpolate_f32(\r
+ const arm_fir_interpolate_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point FIR interpolator.\r
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.\r
+ * @param[in] L upsample factor.\r
+ * @param[in] numTaps number of filter coefficients in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\r
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\r
+ */\r
+ arm_status arm_fir_interpolate_init_f32(\r
+ arm_fir_interpolate_instance_f32 * S,\r
+ uint8_t L,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */\r
+ } arm_biquad_cas_df1_32x64_ins_q31;\r
+\r
+\r
+ /**\r
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cas_df1_32x64_q31(\r
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format\r
+ */\r
+ void arm_biquad_cas_df1_32x64_init_q31(\r
+ arm_biquad_cas_df1_32x64_ins_q31 * S,\r
+ uint8_t numStages,\r
+ q31_t * pCoeffs,\r
+ q63_t * pState,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */\r
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_stereo_df2T_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */\r
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */\r
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */\r
+ } arm_biquad_cascade_df2T_instance_f64;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df2T_f32(\r
+ const arm_biquad_cascade_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_stereo_df2T_f32(\r
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in] S points to an instance of the filter data structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_biquad_cascade_df2T_f64(\r
+ const arm_biquad_cascade_df2T_instance_f64 * S,\r
+ float64_t * pSrc,\r
+ float64_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df2T_init_f32(\r
+ arm_biquad_cascade_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_stereo_df2T_init_f32(\r
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,\r
+ uint8_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.\r
+ * @param[in,out] S points to an instance of the filter data structure.\r
+ * @param[in] numStages number of 2nd order stages in the filter.\r
+ * @param[in] pCoeffs points to the filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ */\r
+ void arm_biquad_cascade_df2T_init_f64(\r
+ arm_biquad_cascade_df2T_instance_f64 * S,\r
+ uint8_t numStages,\r
+ float64_t * pCoeffs,\r
+ float64_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point FIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of filter stages. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */\r
+ } arm_fir_lattice_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_q15(\r
+ arm_fir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_q15(\r
+ const arm_fir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_q31(\r
+ arm_fir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 FIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_q31(\r
+ const arm_fir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the floating-point FIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] numStages number of filter stages.\r
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages.\r
+ */\r
+ void arm_fir_lattice_init_f32(\r
+ arm_fir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point FIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_fir_lattice_f32(\r
+ const arm_fir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point IIR lattice filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numStages; /**< number of stages in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */\r
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */\r
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */\r
+ } arm_iir_lattice_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point IIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_f32(\r
+ const arm_iir_lattice_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point IIR lattice filter.\r
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_init_f32(\r
+ arm_iir_lattice_instance_f32 * S,\r
+ uint16_t numStages,\r
+ float32_t * pkCoeffs,\r
+ float32_t * pvCoeffs,\r
+ float32_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_q31(\r
+ const arm_iir_lattice_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_init_q31(\r
+ arm_iir_lattice_instance_q31 * S,\r
+ uint16_t numStages,\r
+ q31_t * pkCoeffs,\r
+ q31_t * pvCoeffs,\r
+ q31_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 IIR lattice filter.\r
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_iir_lattice_q15(\r
+ const arm_iir_lattice_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+/**\r
+ * @brief Initialization function for the Q15 IIR lattice filter.\r
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.\r
+ * @param[in] numStages number of stages in the filter.\r
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.\r
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.\r
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.\r
+ * @param[in] blockSize number of samples to process per call.\r
+ */\r
+ void arm_iir_lattice_init_q15(\r
+ arm_iir_lattice_instance_q15 * S,\r
+ uint16_t numStages,\r
+ q15_t * pkCoeffs,\r
+ q15_t * pvCoeffs,\r
+ q15_t * pState,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that controls filter coefficient updates. */\r
+ } arm_lms_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for floating-point LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_f32(\r
+ const arm_lms_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to the coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_init_f32(\r
+ arm_lms_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to the coefficient buffer.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_init_q15(\r
+ arm_lms_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q15 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_q15(\r
+ const arm_lms_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint32_t postShift; /**< bit shift applied to coefficients. */\r
+ } arm_lms_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q31 LMS filter.\r
+ * @param[in] S points to an instance of the Q15 LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_q31(\r
+ const arm_lms_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 LMS filter.\r
+ * @param[in] S points to an instance of the Q31 LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_init_q31(\r
+ arm_lms_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint32_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ float32_t mu; /**< step size that control filter coefficient updates. */\r
+ float32_t energy; /**< saves previous frame energy. */\r
+ float32_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_f32;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for floating-point normalized LMS filter.\r
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pRef,\r
+ float32_t * pOut,\r
+ float32_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for floating-point normalized LMS filter.\r
+ * @param[in] S points to an instance of the floating-point LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_init_f32(\r
+ arm_lms_norm_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ float32_t mu,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q31_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */\r
+ q31_t energy; /**< saves previous frame energy. */\r
+ q31_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q31;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q31 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pRef,\r
+ q31_t * pOut,\r
+ q31_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q31 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_norm_init_q31(\r
+ arm_lms_norm_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ q31_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 normalized LMS filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< Number of coefficients in the filter. */\r
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */\r
+ q15_t mu; /**< step size that controls filter coefficient updates. */\r
+ uint8_t postShift; /**< bit shift applied to coefficients. */\r
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */\r
+ q15_t energy; /**< saves previous frame energy. */\r
+ q15_t x0; /**< saves previous input sample. */\r
+ } arm_lms_norm_instance_q15;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for Q15 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[in] pRef points to the block of reference data.\r
+ * @param[out] pOut points to the block of output data.\r
+ * @param[out] pErr points to the block of error data.\r
+ * @param[in] blockSize number of samples to process.\r
+ */\r
+ void arm_lms_norm_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pRef,\r
+ q15_t * pOut,\r
+ q15_t * pErr,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for Q15 normalized LMS filter.\r
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.\r
+ * @param[in] numTaps number of filter coefficients.\r
+ * @param[in] pCoeffs points to coefficient buffer.\r
+ * @param[in] pState points to state buffer.\r
+ * @param[in] mu step size that controls filter coefficient updates.\r
+ * @param[in] blockSize number of samples to process.\r
+ * @param[in] postShift bit shift applied to coefficients.\r
+ */\r
+ void arm_lms_norm_init_q15(\r
+ arm_lms_norm_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ q15_t mu,\r
+ uint32_t blockSize,\r
+ uint8_t postShift);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of floating-point sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_f32(\r
+ float32_t * pSrcA,\r
+ uint32_t srcALen,\r
+ float32_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ float32_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ */\r
+ void arm_correlate_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+\r
+ void arm_correlate_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+\r
+ void arm_correlate_fast_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ */\r
+ void arm_correlate_fast_opt_q15(\r
+ q15_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q15_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q15_t * pDst,\r
+ q15_t * pScratch);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_fast_q31(\r
+ q31_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q31_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q31_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\r
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\r
+ */\r
+ void arm_correlate_opt_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst,\r
+ q15_t * pScratch1,\r
+ q15_t * pScratch2);\r
+\r
+\r
+ /**\r
+ * @brief Correlation of Q7 sequences.\r
+ * @param[in] pSrcA points to the first input sequence.\r
+ * @param[in] srcALen length of the first input sequence.\r
+ * @param[in] pSrcB points to the second input sequence.\r
+ * @param[in] srcBLen length of the second input sequence.\r
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.\r
+ */\r
+ void arm_correlate_q7(\r
+ q7_t * pSrcA,\r
+ uint32_t srcALen,\r
+ q7_t * pSrcB,\r
+ uint32_t srcBLen,\r
+ q7_t * pDst);\r
+\r
+\r
+ /**\r
+ * @brief Instance structure for the floating-point sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_f32;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q31 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q31;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q15 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q15;\r
+\r
+ /**\r
+ * @brief Instance structure for the Q7 sparse FIR filter.\r
+ */\r
+ typedef struct\r
+ {\r
+ uint16_t numTaps; /**< number of coefficients in the filter. */\r
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */\r
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\r
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/\r
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */\r
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */\r
+ } arm_fir_sparse_instance_q7;\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the floating-point sparse FIR filter.\r
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ float32_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the floating-point sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_f32(\r
+ arm_fir_sparse_instance_f32 * S,\r
+ uint16_t numTaps,\r
+ float32_t * pCoeffs,\r
+ float32_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q31 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ q31_t * pScratchIn,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q31 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q31(\r
+ arm_fir_sparse_instance_q31 * S,\r
+ uint16_t numTaps,\r
+ q31_t * pCoeffs,\r
+ q31_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q15 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ q15_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q15 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q15(\r
+ arm_fir_sparse_instance_q15 * S,\r
+ uint16_t numTaps,\r
+ q15_t * pCoeffs,\r
+ q15_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Processing function for the Q7 sparse FIR filter.\r
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] pSrc points to the block of input data.\r
+ * @param[out] pDst points to the block of output data\r
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.\r
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.\r
+ * @param[in] blockSize number of input samples to process per call.\r
+ */\r
+ void arm_fir_sparse_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ q7_t * pSrc,\r
+ q7_t * pDst,\r
+ q7_t * pScratchIn,\r
+ q31_t * pScratchOut,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Initialization function for the Q7 sparse FIR filter.\r
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.\r
+ * @param[in] numTaps number of nonzero coefficients in the filter.\r
+ * @param[in] pCoeffs points to the array of filter coefficients.\r
+ * @param[in] pState points to the state buffer.\r
+ * @param[in] pTapDelay points to the array of offset times.\r
+ * @param[in] maxDelay maximum offset time supported.\r
+ * @param[in] blockSize number of samples that will be processed per block.\r
+ */\r
+ void arm_fir_sparse_init_q7(\r
+ arm_fir_sparse_instance_q7 * S,\r
+ uint16_t numTaps,\r
+ q7_t * pCoeffs,\r
+ q7_t * pState,\r
+ int32_t * pTapDelay,\r
+ uint16_t maxDelay,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point sin_cos function.\r
+ * @param[in] theta input value in degrees\r
+ * @param[out] pSinVal points to the processed sine output.\r
+ * @param[out] pCosVal points to the processed cos output.\r
+ */\r
+ void arm_sin_cos_f32(\r
+ float32_t theta,\r
+ float32_t * pSinVal,\r
+ float32_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Q31 sin_cos function.\r
+ * @param[in] theta scaled input value in degrees\r
+ * @param[out] pSinVal points to the processed sine output.\r
+ * @param[out] pCosVal points to the processed cosine output.\r
+ */\r
+ void arm_sin_cos_q31(\r
+ q31_t theta,\r
+ q31_t * pSinVal,\r
+ q31_t * pCosVal);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+ /**\r
+ * @brief Q31 complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex conjugate.\r
+ * @param[in] pSrc points to the input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_conj_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude squared\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_squared_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup PID PID Motor Control\r
+ *\r
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control\r
+ * loop mechanism widely used in industrial control systems.\r
+ * A PID controller is the most commonly used type of feedback controller.\r
+ *\r
+ * This set of functions implements (PID) controllers\r
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample\r
+ * of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>\r
+ * is the input sample value. The functions return the output value.\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\r
+ * A0 = Kp + Ki + Kd\r
+ * A1 = (-Kp ) - (2 * Kd )\r
+ * A2 = Kd </pre>\r
+ *\r
+ * \par\r
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant\r
+ *\r
+ * \par\r
+ * \image html PID.gif "Proportional Integral Derivative Controller"\r
+ *\r
+ * \par\r
+ * The PID controller calculates an "error" value as the difference between\r
+ * the measured output and the reference input.\r
+ * The controller attempts to minimize the error by adjusting the process control inputs.\r
+ * The proportional value determines the reaction to the current error,\r
+ * the integral value determines the reaction based on the sum of recent errors,\r
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.\r
+ *\r
+ * \par Instance Structure\r
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\r
+ * A separate instance structure must be defined for each PID Controller.\r
+ * There are separate instance structure declarations for each of the 3 supported data types.\r
+ *\r
+ * \par Reset Functions\r
+ * There is also an associated reset function for each data type which clears the state array.\r
+ *\r
+ * \par Initialization Functions\r
+ * There is also an associated initialization function for each data type.\r
+ * The initialization function performs the following operations:\r
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\r
+ * - Zeros out the values in the state buffer.\r
+ *\r
+ * \par\r
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\r
+ *\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.\r
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup PID\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point PID Control.\r
+ * @param[in,out] S is an instance of the floating-point PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(\r
+ arm_pid_instance_f32 * S,\r
+ float32_t in)\r
+ {\r
+ float32_t out;\r
+\r
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */\r
+ out = (S->A0 * in) +\r
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+\r
+ }\r
+\r
+ /**\r
+ * @brief Process function for the Q31 PID Control.\r
+ * @param[in,out] S points to an instance of the Q31 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 64-bit accumulator.\r
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\r
+ * Thus, if the accumulator result overflows it wraps around rather than clip.\r
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\r
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(\r
+ arm_pid_instance_q31 * S,\r
+ q31_t in)\r
+ {\r
+ q63_t acc;\r
+ q31_t out;\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q63_t) S->A0 * in;\r
+\r
+ /* acc += A1 * x[n-1] */\r
+ acc += (q63_t) S->A1 * S->state[0];\r
+\r
+ /* acc += A2 * x[n-2] */\r
+ acc += (q63_t) S->A2 * S->state[1];\r
+\r
+ /* convert output to 1.31 format to add y[n-1] */\r
+ out = (q31_t) (acc >> 31U);\r
+\r
+ /* out += y[n-1] */\r
+ out += S->state[2];\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Process function for the Q15 PID Control.\r
+ * @param[in,out] S points to an instance of the Q15 PID Control structure\r
+ * @param[in] in input sample to process\r
+ * @return out processed output sample.\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using a 64-bit internal accumulator.\r
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\r
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\r
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\r
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\r
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(\r
+ arm_pid_instance_q15 * S,\r
+ q15_t in)\r
+ {\r
+ q63_t acc;\r
+ q15_t out;\r
+\r
+#if defined (ARM_MATH_DSP)\r
+ __SIMD32_TYPE *vstate;\r
+\r
+ /* Implementation of PID controller */\r
+\r
+ /* acc = A0 * x[n] */\r
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ vstate = __SIMD32_CONST(S->state);\r
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\r
+#else\r
+ /* acc = A0 * x[n] */\r
+ acc = ((q31_t) S->A0) * in;\r
+\r
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */\r
+ acc += (q31_t) S->A1 * S->state[0];\r
+ acc += (q31_t) S->A2 * S->state[1];\r
+#endif\r
+\r
+ /* acc += y[n-1] */\r
+ acc += (q31_t) S->state[2] << 15;\r
+\r
+ /* saturate the output */\r
+ out = (q15_t) (__SSAT((acc >> 15), 16));\r
+\r
+ /* Update state */\r
+ S->state[1] = S->state[0];\r
+ S->state[0] = in;\r
+ S->state[2] = out;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+ /**\r
+ * @} end of PID group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+ arm_status arm_mat_inverse_f32(\r
+ const arm_matrix_instance_f32 * src,\r
+ arm_matrix_instance_f32 * dst);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point matrix inverse.\r
+ * @param[in] src points to the instance of the input floating-point matrix structure.\r
+ * @param[out] dst points to the instance of the output floating-point matrix structure.\r
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\r
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\r
+ */\r
+ arm_status arm_mat_inverse_f64(\r
+ const arm_matrix_instance_f64 * src,\r
+ arm_matrix_instance_f64 * dst);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup clarke Vector Clarke Transform\r
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\r
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\r
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\r
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\r
+ * \image html clarke.gif Stator current space vector and its components in (a,b).\r
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\r
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeFormula.gif\r
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\r
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point Clarke transform\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(\r
+ float32_t Ia,\r
+ float32_t Ib,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\r
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Clarke transform for Q31 version\r
+ * @param[in] Ia input three-phase coordinate <code>a</code>\r
+ * @param[in] Ib input three-phase coordinate <code>b</code>\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(\r
+ q31_t Ia,\r
+ q31_t Ib,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */\r
+ *pIalpha = Ia;\r
+\r
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\r
+\r
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\r
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\r
+\r
+ /* pIbeta is calculated by adding the intermediate products */\r
+ *pIbeta = __QADD(product1, product2);\r
+ }\r
+\r
+ /**\r
+ * @} end of clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q31 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_q7_to_q31(\r
+ q7_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_clarke Vector Inverse Clarke Transform\r
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html clarkeInvFormula.gif\r
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\r
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Clarke transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_clarke\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Clarke transform\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pIa,\r
+ float32_t * pIb)\r
+ {\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\r
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Clarke transform for Q31 version\r
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha\r
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta\r
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>\r
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the subtraction, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pIa,\r
+ q31_t * pIb)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */\r
+ *pIa = Ialpha;\r
+\r
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\r
+\r
+ /* pIb is calculated by subtracting the products */\r
+ *pIb = __QSUB(product2, product1);\r
+ }\r
+\r
+ /**\r
+ * @} end of inv_clarke group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to Q15 vector.\r
+ * @param[in] pSrc input pointer\r
+ * @param[out] pDst output pointer\r
+ * @param[in] blockSize number of samples to process\r
+ */\r
+ void arm_q7_to_q15(\r
+ q7_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup park Vector Park Transform\r
+ *\r
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.\r
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\r
+ * from the stationary to the moving reference frame and control the spatial relationship between\r
+ * the stator vector current and rotor flux vector.\r
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the\r
+ * current vector and the relationship from the two reference frames:\r
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkFormula.gif\r
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\r
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Park transform\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] pId points to output rotor reference frame d\r
+ * @param[out] pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ *\r
+ * The function implements the forward Park transform.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_park_f32(\r
+ float32_t Ialpha,\r
+ float32_t Ibeta,\r
+ float32_t * pId,\r
+ float32_t * pIq,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\r
+ *pId = Ialpha * cosVal + Ibeta * sinVal;\r
+\r
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\r
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Park transform for Q31 version\r
+ * @param[in] Ialpha input two-phase vector coordinate alpha\r
+ * @param[in] Ibeta input two-phase vector coordinate beta\r
+ * @param[out] pId points to output rotor reference frame d\r
+ * @param[out] pIq points to output rotor reference frame q\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_park_q31(\r
+ q31_t Ialpha,\r
+ q31_t Ibeta,\r
+ q31_t * pId,\r
+ q31_t * pIq,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Ialpha * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Ialpha * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Ibeta * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pId by adding the two intermediate products 1 and 2 */\r
+ *pId = __QADD(product1, product2);\r
+\r
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\r
+ *pIq = __QSUB(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of park group\r
+ */\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q7 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q7_to_float(\r
+ q7_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupController\r
+ */\r
+\r
+ /**\r
+ * @defgroup inv_park Vector Inverse Park transform\r
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\r
+ *\r
+ * The function operates on a single sample of data and each call to the function returns the processed output.\r
+ * The library provides separate functions for Q31 and floating-point data types.\r
+ * \par Algorithm\r
+ * \image html parkInvFormula.gif\r
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\r
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\r
+ * cosine and sine values of theta (rotor flux position).\r
+ * \par Fixed-Point Behavior\r
+ * Care must be taken when using the Q31 version of the Park transform.\r
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.\r
+ * Refer to the function specific documentation below for usage guidelines.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup inv_park\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point Inverse Park transform\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(\r
+ float32_t Id,\r
+ float32_t Iq,\r
+ float32_t * pIalpha,\r
+ float32_t * pIbeta,\r
+ float32_t sinVal,\r
+ float32_t cosVal)\r
+ {\r
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\r
+ *pIalpha = Id * cosVal - Iq * sinVal;\r
+\r
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\r
+ *pIbeta = Id * sinVal + Iq * cosVal;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Inverse Park transform for Q31 version\r
+ * @param[in] Id input coordinate of rotor reference frame d\r
+ * @param[in] Iq input coordinate of rotor reference frame q\r
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha\r
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta\r
+ * @param[in] sinVal sine value of rotation angle theta\r
+ * @param[in] cosVal cosine value of rotation angle theta\r
+ *\r
+ * <b>Scaling and Overflow Behavior:</b>\r
+ * \par\r
+ * The function is implemented using an internal 32-bit accumulator.\r
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\r
+ * There is saturation on the addition, hence there is no risk of overflow.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(\r
+ q31_t Id,\r
+ q31_t Iq,\r
+ q31_t * pIalpha,\r
+ q31_t * pIbeta,\r
+ q31_t sinVal,\r
+ q31_t cosVal)\r
+ {\r
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */\r
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */\r
+\r
+ /* Intermediate product is calculated by (Id * cosVal) */\r
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * sinVal) */\r
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\r
+\r
+\r
+ /* Intermediate product is calculated by (Id * sinVal) */\r
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\r
+\r
+ /* Intermediate product is calculated by (Iq * cosVal) */\r
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\r
+\r
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */\r
+ *pIalpha = __QSUB(product1, product2);\r
+\r
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */\r
+ *pIbeta = __QADD(product4, product3);\r
+ }\r
+\r
+ /**\r
+ * @} end of Inverse park group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_float(\r
+ q31_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup LinearInterpolate Linear Interpolation\r
+ *\r
+ * Linear interpolation is a method of curve fitting using linear polynomials.\r
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\r
+ *\r
+ * \par\r
+ * \image html LinearInterp.gif "Linear interpolation"\r
+ *\r
+ * \par\r
+ * A Linear Interpolate function calculates an output value(y), for the input(x)\r
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\r
+ *\r
+ * \par Algorithm:\r
+ * <pre>\r
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\r
+ * where x0, x1 are nearest values of input x\r
+ * y0, y1 are nearest values to output y\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * This set of functions implements Linear interpolation process\r
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single\r
+ * sample of data and each call to the function returns a single processed value.\r
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.\r
+ * <code>x</code> is the input sample value. The functions returns the output value.\r
+ *\r
+ * \par\r
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table\r
+ * if x is below input range and returns last value of table if x is above range.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup LinearInterpolate\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Process function for the floating-point Linear Interpolation Function.\r
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure\r
+ * @param[in] x input sample to process\r
+ * @return y processed output sample.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(\r
+ arm_linear_interp_instance_f32 * S,\r
+ float32_t x)\r
+ {\r
+ float32_t y;\r
+ float32_t x0, x1; /* Nearest input values */\r
+ float32_t y0, y1; /* Nearest output values */\r
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */\r
+ int32_t i; /* Index variable */\r
+ float32_t *pYData = S->pYData; /* pointer to output table */\r
+\r
+ /* Calculation of index */\r
+ i = (int32_t) ((x - S->x1) / xSpacing);\r
+\r
+ if (i < 0)\r
+ {\r
+ /* Iniatilize output for below specified range as least output value of table */\r
+ y = pYData[0];\r
+ }\r
+ else if ((uint32_t)i >= S->nValues)\r
+ {\r
+ /* Iniatilize output for above specified range as last output value of table */\r
+ y = pYData[S->nValues - 1];\r
+ }\r
+ else\r
+ {\r
+ /* Calculation of nearest input values */\r
+ x0 = S->x1 + i * xSpacing;\r
+ x1 = S->x1 + (i + 1) * xSpacing;\r
+\r
+ /* Read of nearest output values */\r
+ y0 = pYData[i];\r
+ y1 = pYData[i + 1];\r
+\r
+ /* Calculation of output */\r
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\r
+\r
+ }\r
+\r
+ /* returns output value */\r
+ return (y);\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q31 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q31 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(\r
+ q31_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q31_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & (q31_t)0xFFF00000) >> 20);\r
+\r
+ if (index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if (index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* shift left by 11 to keep fract in 1.31 format */\r
+ fract = (x & 0x000FFFFF) << 11;\r
+\r
+ /* Read two nearest output values from the index in 1.31(q31) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */\r
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\r
+\r
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\r
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));\r
+\r
+ /* Convert y to 1.31 format */\r
+ return (y << 1U);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q15 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q15 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ *\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(\r
+ q15_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q63_t y; /* output */\r
+ q15_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ int32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ index = ((x & (int32_t)0xFFF00000) >> 20);\r
+\r
+ if (index >= (int32_t)(nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else if (index < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */\r
+ y = ((q63_t) y0 * (0xFFFFF - fract));\r
+\r
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\r
+ y += ((q63_t) y1 * (fract));\r
+\r
+ /* convert y to 1.15 format */\r
+ return (q15_t) (y >> 20);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Process function for the Q7 Linear Interpolation Function.\r
+ * @param[in] pYData pointer to Q7 Linear Interpolation table\r
+ * @param[in] x input sample to process\r
+ * @param[in] nValues number of table values\r
+ * @return y processed output sample.\r
+ *\r
+ * \par\r
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\r
+ * This function can support maximum of table size 2^12.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(\r
+ q7_t * pYData,\r
+ q31_t x,\r
+ uint32_t nValues)\r
+ {\r
+ q31_t y; /* output */\r
+ q7_t y0, y1; /* Nearest output values */\r
+ q31_t fract; /* fractional part */\r
+ uint32_t index; /* Index to read nearest output values */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ if (x < 0)\r
+ {\r
+ return (pYData[0]);\r
+ }\r
+ index = (x >> 20) & 0xfff;\r
+\r
+ if (index >= (nValues - 1))\r
+ {\r
+ return (pYData[nValues - 1]);\r
+ }\r
+ else\r
+ {\r
+ /* 20 bits for the fractional part */\r
+ /* fract is in 12.20 format */\r
+ fract = (x & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index and are in 1.7(q7) format */\r
+ y0 = pYData[index];\r
+ y1 = pYData[index + 1];\r
+\r
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\r
+ y = ((y0 * (0xFFFFF - fract)));\r
+\r
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\r
+ y += (y1 * fract);\r
+\r
+ /* convert y to 1.7(q7) format */\r
+ return (q7_t) (y >> 20);\r
+ }\r
+ }\r
+\r
+ /**\r
+ * @} end of LinearInterpolate group\r
+ */\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ float32_t arm_sin_f32(\r
+ float32_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ q31_t arm_sin_q31(\r
+ q31_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return sin(x).\r
+ */\r
+ q15_t arm_sin_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.\r
+ * @param[in] x input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ float32_t arm_cos_f32(\r
+ float32_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ q31_t arm_cos_q31(\r
+ q31_t x);\r
+\r
+\r
+ /**\r
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.\r
+ * @param[in] x Scaled input value in radians.\r
+ * @return cos(x).\r
+ */\r
+ q15_t arm_cos_q15(\r
+ q15_t x);\r
+\r
+\r
+ /**\r
+ * @ingroup groupFastMath\r
+ */\r
+\r
+\r
+ /**\r
+ * @defgroup SQRT Square Root\r
+ *\r
+ * Computes the square root of a number.\r
+ * There are separate functions for Q15, Q31, and floating-point data types.\r
+ * The square root function is computed using the Newton-Raphson algorithm.\r
+ * This is an iterative algorithm of the form:\r
+ * <pre>\r
+ * x1 = x0 - f(x0)/f'(x0)\r
+ * </pre>\r
+ * where <code>x1</code> is the current estimate,\r
+ * <code>x0</code> is the previous estimate, and\r
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\r
+ * For the square root function, the algorithm reduces to:\r
+ * <pre>\r
+ * x0 = in/2 [initial guess]\r
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]\r
+ * </pre>\r
+ */\r
+\r
+\r
+ /**\r
+ * @addtogroup SQRT\r
+ * @{\r
+ */\r
+\r
+ /**\r
+ * @brief Floating-point square root function.\r
+ * @param[in] in input value.\r
+ * @param[out] pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(\r
+ float32_t in,\r
+ float32_t * pOut)\r
+ {\r
+ if (in >= 0.0f)\r
+ {\r
+\r
+#if (__FPU_USED == 1) && defined ( __CC_ARM )\r
+ *pOut = __sqrtf(in);\r
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\r
+ *pOut = __builtin_sqrtf(in);\r
+#elif (__FPU_USED == 1) && defined(__GNUC__)\r
+ *pOut = __builtin_sqrtf(in);\r
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\r
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));\r
+#else\r
+ *pOut = sqrtf(in);\r
+#endif\r
+\r
+ return (ARM_MATH_SUCCESS);\r
+ }\r
+ else\r
+ {\r
+ *pOut = 0.0f;\r
+ return (ARM_MATH_ARGUMENT_ERROR);\r
+ }\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q31 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\r
+ * @param[out] pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q31(\r
+ q31_t in,\r
+ q31_t * pOut);\r
+\r
+\r
+ /**\r
+ * @brief Q15 square root function.\r
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\r
+ * @param[out] pOut square root of input value.\r
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\r
+ * <code>in</code> is negative value and returns zero output for negative values.\r
+ */\r
+ arm_status arm_sqrt_q15(\r
+ q15_t in,\r
+ q15_t * pOut);\r
+\r
+ /**\r
+ * @} end of SQRT group\r
+ */\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular write function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const int32_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+\r
+ /**\r
+ * @brief floating-point Circular Read function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(\r
+ int32_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ int32_t * dst,\r
+ int32_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == (int32_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular write function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q15_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 Circular Read function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(\r
+ q15_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q15_t * dst,\r
+ q15_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == (q15_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular write function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ uint16_t * writeOffset,\r
+ int32_t bufferInc,\r
+ const q7_t * src,\r
+ int32_t srcInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0U;\r
+ int32_t wOffset;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location where the input samples to be copied */\r
+ wOffset = *writeOffset;\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the input sample to the circular buffer */\r
+ circBuffer[wOffset] = *src;\r
+\r
+ /* Update the input pointer */\r
+ src += srcInc;\r
+\r
+ /* Circularly update wOffset. Watch out for positive and negative value */\r
+ wOffset += bufferInc;\r
+ if (wOffset >= L)\r
+ wOffset -= L;\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *writeOffset = (uint16_t)wOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 Circular Read function.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(\r
+ q7_t * circBuffer,\r
+ int32_t L,\r
+ int32_t * readOffset,\r
+ int32_t bufferInc,\r
+ q7_t * dst,\r
+ q7_t * dst_base,\r
+ int32_t dst_length,\r
+ int32_t dstInc,\r
+ uint32_t blockSize)\r
+ {\r
+ uint32_t i = 0;\r
+ int32_t rOffset, dst_end;\r
+\r
+ /* Copy the value of Index pointer that points\r
+ * to the current location from where the input samples to be read */\r
+ rOffset = *readOffset;\r
+\r
+ dst_end = (int32_t) (dst_base + dst_length);\r
+\r
+ /* Loop over the blockSize */\r
+ i = blockSize;\r
+\r
+ while (i > 0U)\r
+ {\r
+ /* copy the sample from the circular buffer to the destination buffer */\r
+ *dst = circBuffer[rOffset];\r
+\r
+ /* Update the input pointer */\r
+ dst += dstInc;\r
+\r
+ if (dst == (q7_t *) dst_end)\r
+ {\r
+ dst = dst_base;\r
+ }\r
+\r
+ /* Circularly update rOffset. Watch out for positive and negative value */\r
+ rOffset += bufferInc;\r
+\r
+ if (rOffset >= L)\r
+ {\r
+ rOffset -= L;\r
+ }\r
+\r
+ /* Decrement the loop counter */\r
+ i--;\r
+ }\r
+\r
+ /* Update the index pointer */\r
+ *readOffset = rOffset;\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q63_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Sum of the squares of the elements of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_power_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Mean value of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_mean_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Variance of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_var_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Root Mean Square of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_rms_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Standard deviation of the elements of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output value.\r
+ */\r
+ void arm_std_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_f32(\r
+ float32_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_q31(\r
+ q31_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex magnitude\r
+ * @param[in] pSrc points to the complex input vector\r
+ * @param[out] pDst points to the real output vector\r
+ * @param[in] numSamples number of complex samples in the input vector\r
+ */\r
+ void arm_cmplx_mag_q15(\r
+ q15_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q31_t * realResult,\r
+ q31_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ uint32_t numSamples,\r
+ q63_t * realResult,\r
+ q63_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex dot product\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ * @param[out] realResult real part of the result returned here\r
+ * @param[out] imagResult imaginary part of the result returned here\r
+ */\r
+ void arm_cmplx_dot_prod_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ uint32_t numSamples,\r
+ float32_t * realResult,\r
+ float32_t * imagResult);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_q15(\r
+ q15_t * pSrcCmplx,\r
+ q15_t * pSrcReal,\r
+ q15_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_q31(\r
+ q31_t * pSrcCmplx,\r
+ q31_t * pSrcReal,\r
+ q31_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-real multiplication\r
+ * @param[in] pSrcCmplx points to the complex input vector\r
+ * @param[in] pSrcReal points to the real input vector\r
+ * @param[out] pCmplxDst points to the complex output vector\r
+ * @param[in] numSamples number of samples in each vector\r
+ */\r
+ void arm_cmplx_mult_real_f32(\r
+ float32_t * pSrcCmplx,\r
+ float32_t * pSrcReal,\r
+ float32_t * pCmplxDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] result is output pointer\r
+ * @param[in] index is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * result,\r
+ uint32_t * index);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Minimum value of a floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ * @param[out] pResult is output pointer\r
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.\r
+ */\r
+ void arm_min_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q7 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q7(\r
+ q7_t * pSrc,\r
+ uint32_t blockSize,\r
+ q7_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q15 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q15(\r
+ q15_t * pSrc,\r
+ uint32_t blockSize,\r
+ q15_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a Q31 vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_q31(\r
+ q31_t * pSrc,\r
+ uint32_t blockSize,\r
+ q31_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+/**\r
+ * @brief Maximum value of a floating-point vector.\r
+ * @param[in] pSrc points to the input buffer\r
+ * @param[in] blockSize length of the input vector\r
+ * @param[out] pResult maximum value returned here\r
+ * @param[out] pIndex index of maximum value returned here\r
+ */\r
+ void arm_max_f32(\r
+ float32_t * pSrc,\r
+ uint32_t blockSize,\r
+ float32_t * pResult,\r
+ uint32_t * pIndex);\r
+\r
+\r
+ /**\r
+ * @brief Q15 complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_q15(\r
+ q15_t * pSrcA,\r
+ q15_t * pSrcB,\r
+ q15_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Q31 complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_q31(\r
+ q31_t * pSrcA,\r
+ q31_t * pSrcB,\r
+ q31_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Floating-point complex-by-complex multiplication\r
+ * @param[in] pSrcA points to the first input vector\r
+ * @param[in] pSrcB points to the second input vector\r
+ * @param[out] pDst points to the output vector\r
+ * @param[in] numSamples number of complex samples in each vector\r
+ */\r
+ void arm_cmplx_mult_cmplx_f32(\r
+ float32_t * pSrcA,\r
+ float32_t * pSrcB,\r
+ float32_t * pDst,\r
+ uint32_t numSamples);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q31 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q31 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q31(\r
+ float32_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q15 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q15 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q15(\r
+ float32_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the floating-point vector to Q7 vector.\r
+ * @param[in] pSrc points to the floating-point input vector\r
+ * @param[out] pDst points to the Q7 output vector\r
+ * @param[in] blockSize length of the input vector\r
+ */\r
+ void arm_float_to_q7(\r
+ float32_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q15 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_q15(\r
+ q31_t * pSrc,\r
+ q15_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q31 vector to Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q31_to_q7(\r
+ q31_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to floating-point vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_float(\r
+ q15_t * pSrc,\r
+ float32_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q31 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_q31(\r
+ q15_t * pSrc,\r
+ q31_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @brief Converts the elements of the Q15 vector to Q7 vector.\r
+ * @param[in] pSrc is input pointer\r
+ * @param[out] pDst is output pointer\r
+ * @param[in] blockSize is the number of samples to process\r
+ */\r
+ void arm_q15_to_q7(\r
+ q15_t * pSrc,\r
+ q7_t * pDst,\r
+ uint32_t blockSize);\r
+\r
+\r
+ /**\r
+ * @ingroup groupInterpolation\r
+ */\r
+\r
+ /**\r
+ * @defgroup BilinearInterpolate Bilinear Interpolation\r
+ *\r
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\r
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\r
+ * determines values between the grid points.\r
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\r
+ * Bilinear interpolation is often used in image processing to rescale images.\r
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\r
+ *\r
+ * <b>Algorithm</b>\r
+ * \par\r
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\r
+ * For floating-point, the instance structure is defined as:\r
+ * <pre>\r
+ * typedef struct\r
+ * {\r
+ * uint16_t numRows;\r
+ * uint16_t numCols;\r
+ * float32_t *pData;\r
+ * } arm_bilinear_interp_instance_f32;\r
+ * </pre>\r
+ *\r
+ * \par\r
+ * where <code>numRows</code> specifies the number of rows in the table;\r
+ * <code>numCols</code> specifies the number of columns in the table;\r
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\r
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\r
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\r
+ *\r
+ * \par\r
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:\r
+ * <pre>\r
+ * XF = floor(x)\r
+ * YF = floor(y)\r
+ * </pre>\r
+ * \par\r
+ * The interpolated output point is computed as:\r
+ * <pre>\r
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\r
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))\r
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)\r
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)\r
+ * </pre>\r
+ * Note that the coordinates (x, y) contain integer and fractional components.\r
+ * The integer components specify which portion of the table to use while the\r
+ * fractional components control the interpolation processor.\r
+ *\r
+ * \par\r
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\r
+ */\r
+\r
+ /**\r
+ * @addtogroup BilinearInterpolate\r
+ * @{\r
+ */\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Floating-point bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate.\r
+ * @param[in] Y interpolation coordinate.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(\r
+ const arm_bilinear_interp_instance_f32 * S,\r
+ float32_t X,\r
+ float32_t Y)\r
+ {\r
+ float32_t out;\r
+ float32_t f00, f01, f10, f11;\r
+ float32_t *pData = S->pData;\r
+ int32_t xIndex, yIndex, index;\r
+ float32_t xdiff, ydiff;\r
+ float32_t b1, b2, b3, b4;\r
+\r
+ xIndex = (int32_t) X;\r
+ yIndex = (int32_t) Y;\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* Calculation of index for two nearest points in X-direction */\r
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in X-direction */\r
+ f00 = pData[index];\r
+ f01 = pData[index + 1];\r
+\r
+ /* Calculation of index for two nearest points in Y-direction */\r
+ index = (xIndex - 1) + (yIndex) * S->numCols;\r
+\r
+\r
+ /* Read two nearest points in Y-direction */\r
+ f10 = pData[index];\r
+ f11 = pData[index + 1];\r
+\r
+ /* Calculation of intermediate values */\r
+ b1 = f00;\r
+ b2 = f01 - f00;\r
+ b3 = f10 - f00;\r
+ b4 = f00 - f01 - f10 + f11;\r
+\r
+ /* Calculation of fractional part in X */\r
+ xdiff = X - xIndex;\r
+\r
+ /* Calculation of fractional part in Y */\r
+ ydiff = Y - yIndex;\r
+\r
+ /* Calculation of bi-linear interpolated output */\r
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\r
+\r
+ /* return to application */\r
+ return (out);\r
+ }\r
+\r
+\r
+ /**\r
+ *\r
+ * @brief Q31 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(\r
+ arm_bilinear_interp_instance_q31 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q31_t out; /* Temporary output */\r
+ q31_t acc = 0; /* output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q31_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q31_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left xfract by 11 to keep 1.31 format */\r
+ xfract = (X & 0x000FFFFF) << 11U;\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];\r
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* shift left yfract by 11 to keep 1.31 format */\r
+ yfract = (Y & 0x000FFFFF) << 11U;\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];\r
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\r
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));\r
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */\r
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\r
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\r
+\r
+ /* Convert acc to 1.31(q31) format */\r
+ return ((q31_t)(acc << 2));\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q15 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(\r
+ arm_bilinear_interp_instance_q15 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q15_t x1, x2, y1, y2; /* Nearest output values */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q15_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & 0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\r
+\r
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\r
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */\r
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);\r
+ acc = ((q63_t) out * (0xFFFFF - yfract));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);\r
+ acc += ((q63_t) out * (xfract));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */\r
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);\r
+ acc += ((q63_t) out * (yfract));\r
+\r
+ /* acc is in 13.51 format and down shift acc by 36 times */\r
+ /* Convert out to 1.15 format */\r
+ return ((q15_t)(acc >> 36));\r
+ }\r
+\r
+\r
+ /**\r
+ * @brief Q7 bilinear interpolation.\r
+ * @param[in,out] S points to an instance of the interpolation structure.\r
+ * @param[in] X interpolation coordinate in 12.20 format.\r
+ * @param[in] Y interpolation coordinate in 12.20 format.\r
+ * @return out interpolated value.\r
+ */\r
+ CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(\r
+ arm_bilinear_interp_instance_q7 * S,\r
+ q31_t X,\r
+ q31_t Y)\r
+ {\r
+ q63_t acc = 0; /* output */\r
+ q31_t out; /* Temporary output */\r
+ q31_t xfract, yfract; /* X, Y fractional parts */\r
+ q7_t x1, x2, y1, y2; /* Nearest output values */\r
+ int32_t rI, cI; /* Row and column indices */\r
+ q7_t *pYData = S->pData; /* pointer to output table values */\r
+ uint32_t nCols = S->numCols; /* num of rows */\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ rI = ((X & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Input is in 12.20 format */\r
+ /* 12 bits for the table index */\r
+ /* Index value calculation */\r
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);\r
+\r
+ /* Care taken for table outside boundary */\r
+ /* Returns zero output when values are outside table boundary */\r
+ if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\r
+ {\r
+ return (0);\r
+ }\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* xfract should be in 12.20 format */\r
+ xfract = (X & (q31_t)0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];\r
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\r
+\r
+ /* 20 bits for the fractional part */\r
+ /* yfract should be in 12.20 format */\r
+ yfract = (Y & (q31_t)0x000FFFFF);\r
+\r
+ /* Read two nearest output values from the index */\r
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];\r
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\r
+\r
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\r
+ out = ((x1 * (0xFFFFF - xfract)));\r
+ acc = (((q63_t) out * (0xFFFFF - yfract)));\r
+\r
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */\r
+ out = ((x2 * (0xFFFFF - yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y1 * (0xFFFFF - xfract)));\r
+ acc += (((q63_t) out * (yfract)));\r
+\r
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */\r
+ out = ((y2 * (yfract)));\r
+ acc += (((q63_t) out * (xfract)));\r
+\r
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\r
+ return ((q7_t)(acc >> 40));\r
+ }\r
+\r
+ /**\r
+ * @} end of BilinearInterpolate group\r
+ */\r
+\r
+\r
+/* SMMLAR */\r
+#define multAcc_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+/* SMMLSR */\r
+#define multSub_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\r
+\r
+/* SMMULR */\r
+#define mult_32x32_keep32_R(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\r
+\r
+/* SMMLA */\r
+#define multAcc_32x32_keep32(a, x, y) \\r
+ a += (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+/* SMMLS */\r
+#define multSub_32x32_keep32(a, x, y) \\r
+ a -= (q31_t) (((q63_t) x * y) >> 32)\r
+\r
+/* SMMUL */\r
+#define mult_32x32_keep32(a, x, y) \\r
+ a = (q31_t) (((q63_t) x * y ) >> 32)\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("push") \\r
+ _Pragma ("O1")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
+ #define LOW_OPTIMIZATION_EXIT \\r
+ _Pragma ("pop")\r
+ #else\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #endif\r
+\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ __attribute__(( optimize("-O1") ))\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __ICCARM__ )\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
+ #define LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define LOW_OPTIMIZATION_EXIT\r
+\r
+ /* Enter low optimization region - place directly above function definition */\r
+ #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\r
+ _Pragma ("optimize=low")\r
+ #else\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #endif\r
+\r
+ /* Exit low optimization region - place directly after end of function definition */\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define LOW_OPTIMIZATION_ENTER\r
+ #define LOW_OPTIMIZATION_EXIT\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\r
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\r
+\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/* Compiler specific diagnostic adjustment */\r
+#if defined ( __CC_ARM )\r
+\r
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\r
+\r
+#elif defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+\r
+#elif defined ( __ICCARM__ )\r
+\r
+#elif defined ( __TI_ARM__ )\r
+\r
+#elif defined ( __CSMC__ )\r
+\r
+#elif defined ( __TASKING__ )\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+#endif /* _ARM_MATH_H */\r
+\r
+/**\r
+ *\r
+ * End of file.\r
+ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armcc.h\r
+ * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_ARMCC_H\r
+#define __CMSIS_ARMCC_H\r
+\r
+\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\r
+ #error "Please use Arm Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* CMSIS compiler control architecture macros */\r
+#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \\r
+ (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )\r
+ #define __ARM_ARCH_6M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))\r
+ #define __ARM_ARCH_7M__ 1\r
+#endif\r
+\r
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\r
+ #define __ARM_ARCH_7EM__ 1\r
+#endif\r
+\r
+ /* __ARM_ARCH_8M_BASE__ not applicable */\r
+ /* __ARM_ARCH_8M_MAIN__ not applicable */\r
+\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE static __forceinline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __declspec(noreturn)\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT __packed struct\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION __packed union\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePriMax __ASM("basepri_max");\r
+ __regBasePriMax = (basePri & 0xFFU);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1U);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() do {\\r
+ __schedule_barrier();\\r
+ __isb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() do {\\r
+ __schedule_barrier();\\r
+ __dsb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() do {\\r
+ __schedule_barrier();\\r
+ __dmb(0xF);\\r
+ __schedule_barrier();\\r
+ } while (0U)\r
+\r
+ \r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+ #define __RBIT __rbit\r
+#else\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+ return result;\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+#else\r
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+#else\r
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXB(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXH(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\r
+ #define __STREXW(value, ptr) __strex(value, ptr)\r
+#else\r
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\r
+{\r
+ rrx r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRBT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRHT(value, ptr) __strt(value, ptr)\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+#define __STRT(value, ptr) __strt(value, ptr)\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )\r
+\r
+#define __SADD8 __sadd8\r
+#define __QADD8 __qadd8\r
+#define __SHADD8 __shadd8\r
+#define __UADD8 __uadd8\r
+#define __UQADD8 __uqadd8\r
+#define __UHADD8 __uhadd8\r
+#define __SSUB8 __ssub8\r
+#define __QSUB8 __qsub8\r
+#define __SHSUB8 __shsub8\r
+#define __USUB8 __usub8\r
+#define __UQSUB8 __uqsub8\r
+#define __UHSUB8 __uhsub8\r
+#define __SADD16 __sadd16\r
+#define __QADD16 __qadd16\r
+#define __SHADD16 __shadd16\r
+#define __UADD16 __uadd16\r
+#define __UQADD16 __uqadd16\r
+#define __UHADD16 __uhadd16\r
+#define __SSUB16 __ssub16\r
+#define __QSUB16 __qsub16\r
+#define __SHSUB16 __shsub16\r
+#define __USUB16 __usub16\r
+#define __UQSUB16 __uqsub16\r
+#define __UHSUB16 __uhsub16\r
+#define __SASX __sasx\r
+#define __QASX __qasx\r
+#define __SHASX __shasx\r
+#define __UASX __uasx\r
+#define __UQASX __uqasx\r
+#define __UHASX __uhasx\r
+#define __SSAX __ssax\r
+#define __QSAX __qsax\r
+#define __SHSAX __shsax\r
+#define __USAX __usax\r
+#define __UQSAX __uqsax\r
+#define __UHSAX __uhsax\r
+#define __USAD8 __usad8\r
+#define __USADA8 __usada8\r
+#define __SSAT16 __ssat16\r
+#define __USAT16 __usat16\r
+#define __UXTB16 __uxtb16\r
+#define __UXTAB16 __uxtab16\r
+#define __SXTB16 __sxtb16\r
+#define __SXTAB16 __sxtab16\r
+#define __SMUAD __smuad\r
+#define __SMUADX __smuadx\r
+#define __SMLAD __smlad\r
+#define __SMLADX __smladx\r
+#define __SMLALD __smlald\r
+#define __SMLALDX __smlaldx\r
+#define __SMUSD __smusd\r
+#define __SMUSDX __smusdx\r
+#define __SMLSD __smlsd\r
+#define __SMLSDX __smlsdx\r
+#define __SMLSLD __smlsld\r
+#define __SMLSLDX __smlsldx\r
+#define __SEL __sel\r
+#define __QADD __qadd\r
+#define __QSUB __qsub\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\r
+ ((int64_t)(ARG3) << 32U) ) >> 32U))\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_armclang.h\r
+ * @brief CMSIS compiler armclang (Arm Compiler 6) header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\r
+\r
+#ifndef __CMSIS_ARMCLANG_H\r
+#define __CMSIS_ARMCLANG_H\r
+\r
+#pragma clang system_header /* treat file as system include file */\r
+\r
+#ifndef __ARM_COMPAT_H\r
+#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE __inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static __inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma clang diagnostic push\r
+ #pragma clang diagnostic ignored "-Wpacked"\r
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma clang diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __enable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+/* intrinsic void __disable_irq(); see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq /* see arm_compat.h */\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr\r
+#else\r
+#define __get_FPSCR() ((uint32_t)0U)\r
+#endif\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#define __set_FPSCR __builtin_arm_set_fpscr\r
+#else\r
+#define __set_FPSCR(x) ((void)(x))\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __builtin_arm_nop\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI __builtin_arm_wfi\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __builtin_arm_wfe\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __builtin_arm_sev\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+#define __ISB() __builtin_arm_isb(0xF);\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __builtin_arm_dsb(0xF);\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __builtin_arm_dmb(0xF);\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV(value) __builtin_bswap32(value)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV16(value) __ROR(__REV(value), 16)\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __builtin_arm_rbit\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB (uint8_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH (uint16_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW (uint32_t)__builtin_arm_ldrex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW (uint32_t)__builtin_arm_strex\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+#define __CLREX __builtin_arm_clrex\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __builtin_arm_ssat\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __builtin_arm_usat\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDAEX (uint32_t)__builtin_arm_ldaex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXB (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEXH (uint32_t)__builtin_arm_stlex\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STLEX (uint32_t)__builtin_arm_stlex\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#endif /* __CMSIS_ARMCLANG_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_compiler.h\r
+ * @brief CMSIS compiler generic header file\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_COMPILER_H\r
+#define __CMSIS_COMPILER_H\r
+\r
+#include <stdint.h>\r
+\r
+/*\r
+ * Arm Compiler 4/5\r
+ */\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+\r
+/*\r
+ * Arm Compiler 6 (armclang)\r
+ */\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armclang.h"\r
+\r
+\r
+/*\r
+ * GNU Compiler\r
+ */\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+\r
+/*\r
+ * IAR Compiler\r
+ */\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iccarm.h>\r
+\r
+\r
+/*\r
+ * TI Arm Compiler\r
+ */\r
+#elif defined ( __TI_ARM__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed))\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * TASKING Compiler\r
+ */\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+ #ifndef __ASM\r
+ #define __ASM __asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((noreturn))\r
+ #endif\r
+ #ifndef __USED\r
+ #define __USED __attribute__((used))\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED __packed__\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __packed__\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __packed__\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ struct __packed__ T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #define __ALIGNED(x) __align(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+/*\r
+ * COSMIC Compiler\r
+ */\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+ #ifndef __ASM\r
+ #define __ASM _asm\r
+ #endif\r
+ #ifndef __INLINE\r
+ #define __INLINE inline\r
+ #endif\r
+ #ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+ #endif\r
+ #ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __STATIC_INLINE\r
+ #endif\r
+ #ifndef __NO_RETURN\r
+ // NO RETURN is automatically detected hence no warning here\r
+ #define __NO_RETURN\r
+ #endif\r
+ #ifndef __USED\r
+ #warning No compiler specific solution for __USED. __USED is ignored.\r
+ #define __USED\r
+ #endif\r
+ #ifndef __WEAK\r
+ #define __WEAK __weak\r
+ #endif\r
+ #ifndef __PACKED\r
+ #define __PACKED @packed\r
+ #endif\r
+ #ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT @packed struct\r
+ #endif\r
+ #ifndef __PACKED_UNION\r
+ #define __PACKED_UNION @packed union\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ @packed struct T_UINT32 { uint32_t v; };\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_WRITE\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT16_READ\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_WRITE\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+ #endif\r
+ #ifndef __UNALIGNED_UINT32_READ\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+ #endif\r
+ #ifndef __ALIGNED\r
+ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+ #ifndef __RESTRICT\r
+ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\r
+ #define __RESTRICT\r
+ #endif\r
+\r
+\r
+#else\r
+ #error Unknown compiler.\r
+#endif\r
+\r
+\r
+#endif /* __CMSIS_COMPILER_H */\r
+\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS compiler GCC header file\r
+ * @version V5.0.3\r
+ * @date 16. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+\r
+/* Fallback for __has_builtin */\r
+#ifndef __has_builtin\r
+ #define __has_builtin(x) (0)\r
+#endif\r
+\r
+/* CMSIS compiler specific defines */\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+#ifndef __STATIC_FORCEINLINE \r
+ #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline\r
+#endif \r
+#ifndef __NO_RETURN\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+#endif\r
+#ifndef __USED\r
+ #define __USED __attribute__((used))\r
+#endif\r
+#ifndef __WEAK\r
+ #define __WEAK __attribute__((weak))\r
+#endif\r
+#ifndef __PACKED\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_STRUCT\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __PACKED_UNION\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ struct __attribute__((packed)) T_UINT32 { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT16_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\r
+#endif\r
+#ifndef __UNALIGNED_UINT32_READ\r
+ #pragma GCC diagnostic push\r
+ #pragma GCC diagnostic ignored "-Wpacked"\r
+ #pragma GCC diagnostic ignored "-Wattributes"\r
+ __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\r
+ #pragma GCC diagnostic pop\r
+ #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)\r
+#endif\r
+#ifndef __ALIGNED\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+#endif\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT __restrict\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Control Register (non-secure)\r
+ \details Returns the content of the non-secure Control Register when in secure mode.\r
+ \return non-secure Control Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Control Register (non-secure)\r
+ \details Writes the given value to the non-secure Control Register when in secure state.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \return PSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \return MSP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );\r
+}\r
+#endif\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Stack Pointer (non-secure)\r
+ \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\r
+ \return SP Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Stack Pointer (non-secure)\r
+ \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\r
+ \param [in] topOfStack Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\r
+{\r
+ __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Priority Mask (non-secure)\r
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Priority Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__STATIC_FORCEINLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Base Priority (non-secure)\r
+ \details Returns the current value of the non-secure Base Priority register when in secure state.\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Base Priority (non-secure)\r
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Fault Mask (non-secure)\r
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );\r
+ return(result);\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Fault Mask (non-secure)\r
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+/**\r
+ \brief Get Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+ \r
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Process Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \return PSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+ \r
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Process Stack Pointer (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\r
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)ProcStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always in non-secure\r
+ mode.\r
+\r
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Get Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence zero is returned always.\r
+\r
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\r
+ \return MSPLIM Register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ return 0U;\r
+#else\r
+ register uint32_t result;\r
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );\r
+ return result;\r
+#endif\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer Limit\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored in non-secure\r
+ mode.\r
+\r
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\r
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+\r
+\r
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\r
+/**\r
+ \brief Set Main Stack Pointer Limit (non-secure)\r
+ Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\r
+ Stack Pointer Limit register hence the write is silently ignored.\r
+\r
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\r
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set\r
+ */\r
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\r
+{\r
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)MainStackPtrLimit;\r
+#else\r
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ return __builtin_arm_get_fpscr();\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ return(result);\r
+#endif\r
+#else\r
+ return(0U);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\r
+ /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\r
+ __builtin_arm_set_fpscr(fpscr);\r
+#else\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");\r
+#endif\r
+#else\r
+ (void)fpscr;\r
+#endif\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP() __ASM volatile ("nop")\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+#define __WFI() __ASM volatile ("wfi")\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE() __ASM volatile ("wfe")\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV() __ASM volatile ("sev")\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__STATIC_FORCEINLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__STATIC_FORCEINLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__STATIC_FORCEINLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (int16_t)__builtin_bswap16(value);\r
+#else\r
+ int16_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return result;\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] op1 Value to rotate\r
+ \param [in] op2 Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ op2 %= 32U;\r
+ if (op2 == 0U)\r
+ {\r
+ return op1;\r
+ }\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value != 0U; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return result;\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ (uint8_t)__builtin_clz\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__STATIC_FORCEINLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+__extension__ \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] ARG1 Value to be saturated\r
+ \param [in] ARG2 Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+ __extension__ \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );\r
+}\r
+\r
+#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+{\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+}\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+{\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \\r
+ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */\r
+\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+/**\r
+ \brief Load-Acquire (8 bit)\r
+ \details Executes a LDAB instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (16 bit)\r
+ \details Executes a LDAH instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire (32 bit)\r
+ \details Executes a LDA instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (8 bit)\r
+ \details Executes a STLB instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (16 bit)\r
+ \details Executes a STLH instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release (32 bit)\r
+ \details Executes a STL instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (8 bit)\r
+ \details Executes a LDAB exclusive instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint8_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (16 bit)\r
+ \details Executes a LDAH exclusive instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return ((uint16_t) result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Load-Acquire Exclusive (32 bit)\r
+ \details Executes a LDA exclusive instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (8 bit)\r
+ \details Executes a STLB exclusive instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (16 bit)\r
+ \details Executes a STLH exclusive instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Store-Release Exclusive (32 bit)\r
+ \details Executes a STL exclusive instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#if 0\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+#endif\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \\r
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \\r
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )\r
+\r
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__ARM_FEATURE_DSP == 1) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#pragma GCC diagnostic pop\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_iccarm.h\r
+ * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file\r
+ * @version V5.0.5\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+\r
+//------------------------------------------------------------------------------\r
+//\r
+// Copyright (c) 2017-2018 IAR Systems\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License")\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+// http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+\r
+#ifndef __CMSIS_ICCARM_H__\r
+#define __CMSIS_ICCARM_H__\r
+\r
+#ifndef __ICCARM__\r
+ #error This file should only be compiled by ICCARM\r
+#endif\r
+\r
+#pragma system_include\r
+\r
+#define __IAR_FT _Pragma("inline=forced") __intrinsic\r
+\r
+#if (__VER__ >= 8000000)\r
+ #define __ICCARM_V8 1\r
+#else\r
+ #define __ICCARM_V8 0\r
+#endif\r
+\r
+#ifndef __ALIGNED\r
+ #if __ICCARM_V8\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #elif (__VER__ >= 7080000)\r
+ /* Needs IAR language extensions */\r
+ #define __ALIGNED(x) __attribute__((aligned(x)))\r
+ #else\r
+ #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\r
+ #define __ALIGNED(x)\r
+ #endif\r
+#endif\r
+\r
+\r
+/* Define compiler macros for CPU architecture, used in CMSIS 5.\r
+ */\r
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\r
+/* Macros already defined */\r
+#else\r
+ #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\r
+ #if __ARM_ARCH == 6\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif __ARM_ARCH == 7\r
+ #if __ARM_FEATURE_DSP\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #else\r
+ #define __ARM_ARCH_7M__ 1\r
+ #endif\r
+ #endif /* __ARM_ARCH */\r
+ #endif /* __ARM_ARCH_PROFILE == 'M' */\r
+#endif\r
+\r
+/* Alternativ core deduction for older ICCARM's */\r
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\r
+ !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\r
+ #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\r
+ #define __ARM_ARCH_6M__ 1\r
+ #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\r
+ #define __ARM_ARCH_7M__ 1\r
+ #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\r
+ #define __ARM_ARCH_7EM__ 1\r
+ #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\r
+ #define __ARM_ARCH_8M_BASE__ 1\r
+ #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\r
+ #define __ARM_ARCH_8M_MAIN__ 1\r
+ #else\r
+ #error "Unknown target."\r
+ #endif\r
+#endif\r
+\r
+\r
+\r
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\r
+ #define __IAR_M0_FAMILY 1\r
+#else\r
+ #define __IAR_M0_FAMILY 0\r
+#endif\r
+\r
+\r
+#ifndef __ASM\r
+ #define __ASM __asm\r
+#endif\r
+\r
+#ifndef __INLINE\r
+ #define __INLINE inline\r
+#endif\r
+\r
+#ifndef __NO_RETURN\r
+ #if __ICCARM_V8\r
+ #define __NO_RETURN __attribute__((__noreturn__))\r
+ #else\r
+ #define __NO_RETURN _Pragma("object_attribute=__noreturn")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED\r
+ #if __ICCARM_V8\r
+ #define __PACKED __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED __packed\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_STRUCT\r
+ #if __ICCARM_V8\r
+ #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_STRUCT __packed struct\r
+ #endif\r
+#endif\r
+\r
+#ifndef __PACKED_UNION\r
+ #if __ICCARM_V8\r
+ #define __PACKED_UNION union __attribute__((packed, aligned(1)))\r
+ #else\r
+ /* Needs IAR language extensions */\r
+ #define __PACKED_UNION __packed union\r
+ #endif\r
+#endif\r
+\r
+#ifndef __RESTRICT\r
+ #define __RESTRICT restrict\r
+#endif\r
+\r
+#ifndef __STATIC_INLINE\r
+ #define __STATIC_INLINE static inline\r
+#endif\r
+\r
+#ifndef __FORCEINLINE\r
+ #define __FORCEINLINE _Pragma("inline=forced")\r
+#endif\r
+\r
+#ifndef __STATIC_FORCEINLINE\r
+ #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT16_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\r
+{\r
+ return *(__packed uint16_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\r
+#endif\r
+\r
+\r
+#ifndef __UNALIGNED_UINT16_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\r
+{\r
+ *(__packed uint16_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_READ\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\r
+{\r
+ return *(__packed uint32_t*)(ptr);\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32_WRITE\r
+#pragma language=save\r
+#pragma language=extended\r
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\r
+{\r
+ *(__packed uint32_t*)(ptr) = val;;\r
+}\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\r
+#endif\r
+\r
+#ifndef __UNALIGNED_UINT32 /* deprecated */\r
+#pragma language=save\r
+#pragma language=extended\r
+__packed struct __iar_u32 { uint32_t v; };\r
+#pragma language=restore\r
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\r
+#endif\r
+\r
+#ifndef __USED\r
+ #if __ICCARM_V8\r
+ #define __USED __attribute__((used))\r
+ #else\r
+ #define __USED _Pragma("__root")\r
+ #endif\r
+#endif\r
+\r
+#ifndef __WEAK\r
+ #if __ICCARM_V8\r
+ #define __WEAK __attribute__((weak))\r
+ #else\r
+ #define __WEAK _Pragma("__weak")\r
+ #endif\r
+#endif\r
+\r
+\r
+#ifndef __ICCARM_INTRINSICS_VERSION__\r
+ #define __ICCARM_INTRINSICS_VERSION__ 0\r
+#endif\r
+\r
+#if __ICCARM_INTRINSICS_VERSION__ == 2\r
+\r
+ #if defined(__CLZ)\r
+ #undef __CLZ\r
+ #endif\r
+ #if defined(__REVSH)\r
+ #undef __REVSH\r
+ #endif\r
+ #if defined(__RBIT)\r
+ #undef __RBIT\r
+ #endif\r
+ #if defined(__SSAT)\r
+ #undef __SSAT\r
+ #endif\r
+ #if defined(__USAT)\r
+ #undef __USAT\r
+ #endif\r
+\r
+ #include "iccarm_builtin.h"\r
+\r
+ #define __disable_fault_irq __iar_builtin_disable_fiq\r
+ #define __disable_irq __iar_builtin_disable_interrupt\r
+ #define __enable_fault_irq __iar_builtin_enable_fiq\r
+ #define __enable_irq __iar_builtin_enable_interrupt\r
+ #define __arm_rsr __iar_builtin_rsr\r
+ #define __arm_wsr __iar_builtin_wsr\r
+\r
+\r
+ #define __get_APSR() (__arm_rsr("APSR"))\r
+ #define __get_BASEPRI() (__arm_rsr("BASEPRI"))\r
+ #define __get_CONTROL() (__arm_rsr("CONTROL"))\r
+ #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))\r
+\r
+ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) )\r
+ #define __get_FPSCR() (__arm_rsr("FPSCR"))\r
+ #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))\r
+ #else\r
+ #define __get_FPSCR() ( 0 )\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #define __get_IPSR() (__arm_rsr("IPSR"))\r
+ #define __get_MSP() (__arm_rsr("MSP"))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __get_MSPLIM() (0U)\r
+ #else\r
+ #define __get_MSPLIM() (__arm_rsr("MSPLIM"))\r
+ #endif\r
+ #define __get_PRIMASK() (__arm_rsr("PRIMASK"))\r
+ #define __get_PSP() (__arm_rsr("PSP"))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __get_PSPLIM() (0U)\r
+ #else\r
+ #define __get_PSPLIM() (__arm_rsr("PSPLIM"))\r
+ #endif\r
+\r
+ #define __get_xPSR() (__arm_rsr("xPSR"))\r
+\r
+ #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))\r
+ #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))\r
+ #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))\r
+ #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))\r
+ #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))\r
+\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ #define __set_MSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))\r
+ #endif\r
+ #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))\r
+ #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ #define __set_PSPLIM(VALUE) ((void)(VALUE))\r
+ #else\r
+ #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))\r
+ #endif\r
+\r
+ #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))\r
+ #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))\r
+ #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))\r
+ #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))\r
+ #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))\r
+ #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))\r
+ #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))\r
+ #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))\r
+ #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))\r
+ #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))\r
+ #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))\r
+ #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))\r
+ #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))\r
+ #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))\r
+ #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))\r
+ #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))\r
+ #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))\r
+ #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))\r
+\r
+ #define __NOP __iar_builtin_no_operation\r
+\r
+ #define __CLZ __iar_builtin_CLZ\r
+ #define __CLREX __iar_builtin_CLREX\r
+\r
+ #define __DMB __iar_builtin_DMB\r
+ #define __DSB __iar_builtin_DSB\r
+ #define __ISB __iar_builtin_ISB\r
+\r
+ #define __LDREXB __iar_builtin_LDREXB\r
+ #define __LDREXH __iar_builtin_LDREXH\r
+ #define __LDREXW __iar_builtin_LDREX\r
+\r
+ #define __RBIT __iar_builtin_RBIT\r
+ #define __REV __iar_builtin_REV\r
+ #define __REV16 __iar_builtin_REV16\r
+\r
+ __IAR_FT int16_t __REVSH(int16_t val)\r
+ {\r
+ return (int16_t) __iar_builtin_REVSH(val);\r
+ }\r
+\r
+ #define __ROR __iar_builtin_ROR\r
+ #define __RRX __iar_builtin_RRX\r
+\r
+ #define __SEV __iar_builtin_SEV\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __SSAT __iar_builtin_SSAT\r
+ #endif\r
+\r
+ #define __STREXB __iar_builtin_STREXB\r
+ #define __STREXH __iar_builtin_STREXH\r
+ #define __STREXW __iar_builtin_STREX\r
+\r
+ #if !__IAR_M0_FAMILY\r
+ #define __USAT __iar_builtin_USAT\r
+ #endif\r
+\r
+ #define __WFE __iar_builtin_WFE\r
+ #define __WFI __iar_builtin_WFI\r
+\r
+ #if __ARM_MEDIA__\r
+ #define __SADD8 __iar_builtin_SADD8\r
+ #define __QADD8 __iar_builtin_QADD8\r
+ #define __SHADD8 __iar_builtin_SHADD8\r
+ #define __UADD8 __iar_builtin_UADD8\r
+ #define __UQADD8 __iar_builtin_UQADD8\r
+ #define __UHADD8 __iar_builtin_UHADD8\r
+ #define __SSUB8 __iar_builtin_SSUB8\r
+ #define __QSUB8 __iar_builtin_QSUB8\r
+ #define __SHSUB8 __iar_builtin_SHSUB8\r
+ #define __USUB8 __iar_builtin_USUB8\r
+ #define __UQSUB8 __iar_builtin_UQSUB8\r
+ #define __UHSUB8 __iar_builtin_UHSUB8\r
+ #define __SADD16 __iar_builtin_SADD16\r
+ #define __QADD16 __iar_builtin_QADD16\r
+ #define __SHADD16 __iar_builtin_SHADD16\r
+ #define __UADD16 __iar_builtin_UADD16\r
+ #define __UQADD16 __iar_builtin_UQADD16\r
+ #define __UHADD16 __iar_builtin_UHADD16\r
+ #define __SSUB16 __iar_builtin_SSUB16\r
+ #define __QSUB16 __iar_builtin_QSUB16\r
+ #define __SHSUB16 __iar_builtin_SHSUB16\r
+ #define __USUB16 __iar_builtin_USUB16\r
+ #define __UQSUB16 __iar_builtin_UQSUB16\r
+ #define __UHSUB16 __iar_builtin_UHSUB16\r
+ #define __SASX __iar_builtin_SASX\r
+ #define __QASX __iar_builtin_QASX\r
+ #define __SHASX __iar_builtin_SHASX\r
+ #define __UASX __iar_builtin_UASX\r
+ #define __UQASX __iar_builtin_UQASX\r
+ #define __UHASX __iar_builtin_UHASX\r
+ #define __SSAX __iar_builtin_SSAX\r
+ #define __QSAX __iar_builtin_QSAX\r
+ #define __SHSAX __iar_builtin_SHSAX\r
+ #define __USAX __iar_builtin_USAX\r
+ #define __UQSAX __iar_builtin_UQSAX\r
+ #define __UHSAX __iar_builtin_UHSAX\r
+ #define __USAD8 __iar_builtin_USAD8\r
+ #define __USADA8 __iar_builtin_USADA8\r
+ #define __SSAT16 __iar_builtin_SSAT16\r
+ #define __USAT16 __iar_builtin_USAT16\r
+ #define __UXTB16 __iar_builtin_UXTB16\r
+ #define __UXTAB16 __iar_builtin_UXTAB16\r
+ #define __SXTB16 __iar_builtin_SXTB16\r
+ #define __SXTAB16 __iar_builtin_SXTAB16\r
+ #define __SMUAD __iar_builtin_SMUAD\r
+ #define __SMUADX __iar_builtin_SMUADX\r
+ #define __SMMLA __iar_builtin_SMMLA\r
+ #define __SMLAD __iar_builtin_SMLAD\r
+ #define __SMLADX __iar_builtin_SMLADX\r
+ #define __SMLALD __iar_builtin_SMLALD\r
+ #define __SMLALDX __iar_builtin_SMLALDX\r
+ #define __SMUSD __iar_builtin_SMUSD\r
+ #define __SMUSDX __iar_builtin_SMUSDX\r
+ #define __SMLSD __iar_builtin_SMLSD\r
+ #define __SMLSDX __iar_builtin_SMLSDX\r
+ #define __SMLSLD __iar_builtin_SMLSLD\r
+ #define __SMLSLDX __iar_builtin_SMLSLDX\r
+ #define __SEL __iar_builtin_SEL\r
+ #define __QADD __iar_builtin_QADD\r
+ #define __QSUB __iar_builtin_QSUB\r
+ #define __PKHBT __iar_builtin_PKHBT\r
+ #define __PKHTB __iar_builtin_PKHTB\r
+ #endif\r
+\r
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #define __CLZ __cmsis_iar_clz_not_active\r
+ #define __SSAT __cmsis_iar_ssat_not_active\r
+ #define __USAT __cmsis_iar_usat_not_active\r
+ #define __RBIT __cmsis_iar_rbit_not_active\r
+ #define __get_APSR __cmsis_iar_get_APSR_not_active\r
+ #endif\r
+\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\r
+ #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\r
+ #endif\r
+\r
+ #ifdef __INTRINSICS_INCLUDED\r
+ #error intrinsics.h is already included previously!\r
+ #endif\r
+\r
+ #include <intrinsics.h>\r
+\r
+ #if __IAR_M0_FAMILY\r
+ /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\r
+ #undef __CLZ\r
+ #undef __SSAT\r
+ #undef __USAT\r
+ #undef __RBIT\r
+ #undef __get_APSR\r
+\r
+ __STATIC_INLINE uint8_t __CLZ(uint32_t data)\r
+ {\r
+ if (data == 0U) { return 32U; }\r
+\r
+ uint32_t count = 0U;\r
+ uint32_t mask = 0x80000000U;\r
+\r
+ while ((data & mask) == 0U)\r
+ {\r
+ count += 1U;\r
+ mask = mask >> 1U;\r
+ }\r
+ return count;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __RBIT(uint32_t v)\r
+ {\r
+ uint8_t sc = 31U;\r
+ uint32_t r = v;\r
+ for (v >>= 1U; v; v >>= 1U)\r
+ {\r
+ r <<= 1U;\r
+ r |= v & 1U;\r
+ sc--;\r
+ }\r
+ return (r << sc);\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __get_APSR(void)\r
+ {\r
+ uint32_t res;\r
+ __asm("MRS %0,APSR" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ #endif\r
+\r
+ #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\r
+ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))\r
+ #undef __get_FPSCR\r
+ #undef __set_FPSCR\r
+ #define __get_FPSCR() (0)\r
+ #define __set_FPSCR(VALUE) ((void)VALUE)\r
+ #endif\r
+\r
+ #pragma diag_suppress=Pe940\r
+ #pragma diag_suppress=Pe177\r
+\r
+ #define __enable_irq __enable_interrupt\r
+ #define __disable_irq __disable_interrupt\r
+ #define __NOP __no_operation\r
+\r
+ #define __get_xPSR __get_PSR\r
+\r
+ #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\r
+\r
+ __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\r
+ {\r
+ return __LDREX((unsigned long *)ptr);\r
+ }\r
+\r
+ __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\r
+ {\r
+ return __STREX(value, (unsigned long *)ptr);\r
+ }\r
+ #endif\r
+\r
+\r
+ /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+ #if (__CORTEX_M >= 0x03)\r
+\r
+ __IAR_FT uint32_t __RRX(uint32_t value)\r
+ {\r
+ uint32_t result;\r
+ __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");\r
+ return(result);\r
+ }\r
+\r
+ __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));\r
+ }\r
+\r
+\r
+ #define __enable_fault_irq __enable_fiq\r
+ #define __disable_fault_irq __disable_fiq\r
+\r
+\r
+ #endif /* (__CORTEX_M >= 0x03) */\r
+\r
+ __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+ {\r
+ return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\r
+ }\r
+\r
+ #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+ __IAR_FT uint32_t __get_MSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,MSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_MSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure MSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR MSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __get_PSPLIM(void)\r
+ {\r
+ uint32_t res;\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ res = 0U;\r
+ #else\r
+ __asm volatile("MRS %0,PSPLIM" : "=r" (res));\r
+ #endif\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __set_PSPLIM(uint32_t value)\r
+ {\r
+ #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\r
+ (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))\r
+ // without main extensions, the non-secure PSPLIM is RAZ/WI\r
+ (void)value;\r
+ #else\r
+ __asm volatile("MSR PSPLIM,%0" :: "r" (value));\r
+ #endif\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_SP_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,SP_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+ __IAR_FT void __TZ_set_SP_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR SP_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+ __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)\r
+ {\r
+ uint32_t res;\r
+ __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)\r
+ {\r
+ __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));\r
+ }\r
+\r
+ #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */\r
+\r
+#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))\r
+\r
+#if __IAR_M0_FAMILY\r
+ __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\r
+ {\r
+ if ((sat >= 1U) && (sat <= 32U))\r
+ {\r
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\r
+ const int32_t min = -1 - max ;\r
+ if (val > max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < min)\r
+ {\r
+ return min;\r
+ }\r
+ }\r
+ return val;\r
+ }\r
+\r
+ __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\r
+ {\r
+ if (sat <= 31U)\r
+ {\r
+ const uint32_t max = ((1U << sat) - 1U);\r
+ if (val > (int32_t)max)\r
+ {\r
+ return max;\r
+ }\r
+ else if (val < 0)\r
+ {\r
+ return 0U;\r
+ }\r
+ }\r
+ return (uint32_t)val;\r
+ }\r
+#endif\r
+\r
+#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\r
+\r
+ __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\r
+ {\r
+ uint32_t res;\r
+ __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+ {\r
+ __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+ {\r
+ __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\r
+ {\r
+ __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");\r
+ }\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\r
+ (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )\r
+\r
+\r
+ __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");\r
+ }\r
+\r
+ __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+ return ((uint8_t)res);\r
+ }\r
+\r
+ __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+ return ((uint16_t)res);\r
+ }\r
+\r
+ __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+ __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\r
+ {\r
+ uint32_t res;\r
+ __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");\r
+ return res;\r
+ }\r
+\r
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\r
+\r
+#undef __IAR_FT\r
+#undef __IAR_M0_FAMILY\r
+#undef __ICCARM_V8\r
+\r
+#pragma diag_default=Pe940\r
+#pragma diag_default=Pe177\r
+\r
+#endif /* __CMSIS_ICCARM_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_version.h\r
+ * @brief CMSIS Core(M) Version definitions\r
+ * @version V5.0.2\r
+ * @date 19. April 2017\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CMSIS_VERSION_H\r
+#define __CMSIS_VERSION_H\r
+\r
+/* CMSIS Version definitions */\r
+#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */\r
+#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */\r
+#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mbl.h\r
+ * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MBL_H_GENERIC\r
+#define __CORE_ARMV8MBL_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MBL\r
+ @{\r
+ */\r
+ \r
+#include "cmsis_version.h"\r
+\r
+/* CMSIS definitions */\r
+#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M ( 2U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0U\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT\r
+#define __CORE_ARMV8MBL_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MBL_REV\r
+ #define __ARMv8MBL_REV 0x0000U\r
+ #warning "__ARMv8MBL_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __VTOR_PRESENT\r
+ #define __VTOR_PRESENT 0U\r
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ETM_PRESENT\r
+ #define __ETM_PRESENT 0U\r
+ #warning "__ETM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MTB_PRESENT\r
+ #define __MTB_PRESENT 0U\r
+ #warning "__MTB_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MBL */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+#else\r
+ uint32_t RESERVED0;\r
+#endif\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ uint32_t RESERVED0[6U];\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ uint32_t RESERVED0[7U];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 1U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#endif\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */\r
+#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */\r
+/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+/* Interrupt Priorities are WORD accessible only under Armv6-M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)\r
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )\r
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ If VTOR is not present address 0 must be mapped to SRAM.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+#else\r
+ uint32_t *vectors = (uint32_t *)0x0U;\r
+#endif\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ return 0U; /* No FPU */\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_armv8mml.h\r
+ * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_ARMV8MML_H_GENERIC\r
+#define __CORE_ARMV8MML_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_ARMv8MML\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS Armv8MML definitions */\r
+#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\r
+ __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (81U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ \r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ \r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ \r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined(__ARM_FEATURE_DSP)\r
+ #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+ \r
+#elif defined ( __TI_ARM__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_ARMV8MML_H_DEPENDANT\r
+#define __CORE_ARMV8MML_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __ARMv8MML_REV\r
+ #define __ARMv8MML_REV 0x0000U\r
+ #warning "__ARMv8MML_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group ARMv8MML */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm33.h\r
+ * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File\r
+ * @version V5.0.5\r
+ * @date 08. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM33_H_GENERIC\r
+#define __CORE_CM33_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M33\r
+ @{\r
+ */\r
+\r
+#include "cmsis_version.h"\r
+ \r
+/* CMSIS CM33 definitions */\r
+#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */\r
+#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */\r
+#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (33U) /*!< Cortex-M Core */\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined (__TARGET_FPU_VFP)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined (__ARM_PCS_VFP)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined (__ARMVFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\r
+ #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\r
+ #define __DSP_USED 1U\r
+ #else\r
+ #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"\r
+ #define __DSP_USED 0U \r
+ #endif\r
+ #else\r
+ #define __DSP_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TI_ARM__ )\r
+ #if defined (__TI_VFP_SUPPORT__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined (__FPU_VFP__)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM33_H_DEPENDANT\r
+#define __CORE_CM33_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM33_REV\r
+ #define __CM33_REV 0x0000U\r
+ #warning "__CM33_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __SAUREGION_PRESENT\r
+ #define __SAUREGION_PRESENT 0U\r
+ #warning "__SAUREGION_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DSP_PRESENT\r
+ #define __DSP_PRESENT 0U\r
+ #warning "__DSP_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M33 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core SAU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */\r
+ uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */\r
+ uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */\r
+ uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */\r
+#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */\r
+\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[16U];\r
+ __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[16U];\r
+ __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[16U];\r
+ __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[16U];\r
+ __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[16U];\r
+ __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */\r
+ uint32_t RESERVED5[16U];\r
+ __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED6[580U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */\r
+ uint32_t RESERVED3[92U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */\r
+#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */\r
+\r
+#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */\r
+#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */\r
+#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */\r
+#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */\r
+\r
+#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */\r
+#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */\r
+#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */\r
+#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */\r
+\r
+#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */\r
+#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */\r
+#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */\r
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */\r
+#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */\r
+#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */\r
+\r
+#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */\r
+#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */\r
+#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */\r
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */\r
+\r
+#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */\r
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */\r
+\r
+#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */\r
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */\r
+\r
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\r
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\r
+\r
+#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */\r
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\r
+\r
+#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */\r
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\r
+\r
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */\r
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */\r
+\r
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */\r
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */\r
+\r
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */\r
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */\r
+\r
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */\r
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */\r
+\r
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */\r
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\r
+\r
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */\r
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */\r
+\r
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */\r
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */\r
+\r
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\r
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */\r
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\r
+\r
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */\r
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */\r
+\r
+#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */\r
+#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */\r
+\r
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */\r
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */\r
+\r
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */\r
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */\r
+\r
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */\r
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */\r
+\r
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\r
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Non-Secure Access Control Register Definitions */\r
+#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */\r
+#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */\r
+\r
+#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */\r
+#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */\r
+\r
+#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */\r
+#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */\r
+ uint32_t RESERVED6[4U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Stimulus Port Register Definitions */\r
+#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */\r
+#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */\r
+\r
+#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */\r
+#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */\r
+#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */\r
+\r
+#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */\r
+#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ uint32_t RESERVED3[1U];\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ uint32_t RESERVED5[1U];\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED6[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ uint32_t RESERVED7[1U];\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */\r
+ uint32_t RESERVED9[1U];\r
+ __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */\r
+ uint32_t RESERVED10[1U];\r
+ __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */\r
+ uint32_t RESERVED11[1U];\r
+ __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */\r
+ uint32_t RESERVED12[1U];\r
+ __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */\r
+ uint32_t RESERVED13[1U];\r
+ __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */\r
+ uint32_t RESERVED14[1U];\r
+ __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */\r
+ uint32_t RESERVED15[1U];\r
+ __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */\r
+ uint32_t RESERVED16[1U];\r
+ __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */\r
+ uint32_t RESERVED17[1U];\r
+ __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */\r
+ uint32_t RESERVED18[1U];\r
+ __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */\r
+ uint32_t RESERVED19[1U];\r
+ __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */\r
+ uint32_t RESERVED20[1U];\r
+ __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */\r
+ uint32_t RESERVED21[1U];\r
+ __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */\r
+ uint32_t RESERVED22[1U];\r
+ __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */\r
+ uint32_t RESERVED23[1U];\r
+ __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */\r
+ uint32_t RESERVED24[1U];\r
+ __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */\r
+ uint32_t RESERVED25[1U];\r
+ __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */\r
+ uint32_t RESERVED26[1U];\r
+ __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */\r
+ uint32_t RESERVED27[1U];\r
+ __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */\r
+ uint32_t RESERVED28[1U];\r
+ __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */\r
+ uint32_t RESERVED29[1U];\r
+ __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */\r
+ uint32_t RESERVED30[1U];\r
+ __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */\r
+ uint32_t RESERVED31[1U];\r
+ __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */\r
+ uint32_t RESERVED32[934U];\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+ uint32_t RESERVED33[1U];\r
+ __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */\r
+#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */\r
+#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */\r
+\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */\r
+#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */\r
+\r
+#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */\r
+#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */\r
+\r
+#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */\r
+#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */\r
+ __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */\r
+ __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */\r
+ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */\r
+ uint32_t RESERVED0[1];\r
+ union {\r
+ __IOM uint32_t MAIR[2];\r
+ struct {\r
+ __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */\r
+ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */\r
+ };\r
+ };\r
+} MPU_Type;\r
+\r
+#define MPU_TYPE_RALIASES 4U\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */\r
+#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */\r
+\r
+#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */\r
+#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */\r
+\r
+#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */\r
+#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */\r
+\r
+/* MPU Region Limit Address Register Definitions */\r
+#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */\r
+#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */\r
+\r
+#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */\r
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */\r
+\r
+#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */\r
+#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 0 Definitions */\r
+#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */\r
+#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */\r
+\r
+#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */\r
+#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */\r
+\r
+#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */\r
+#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */\r
+\r
+#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */\r
+#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */\r
+\r
+/* MPU Memory Attribute Indirection Register 1 Definitions */\r
+#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */\r
+#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */\r
+\r
+#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */\r
+#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */\r
+\r
+#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */\r
+#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */\r
+\r
+#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */\r
+#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SAU Security Attribution Unit (SAU)\r
+ \brief Type definitions for the Security Attribution Unit (SAU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Security Attribution Unit (SAU).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */\r
+ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */\r
+#else\r
+ uint32_t RESERVED0[3];\r
+#endif\r
+ __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */\r
+ __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */\r
+} SAU_Type;\r
+\r
+/* SAU Control Register Definitions */\r
+#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */\r
+#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */\r
+\r
+#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */\r
+#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */\r
+\r
+/* SAU Type Register Definitions */\r
+#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */\r
+#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */\r
+\r
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\r
+/* SAU Region Number Register Definitions */\r
+#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */\r
+#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */\r
+\r
+/* SAU Region Base Address Register Definitions */\r
+#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */\r
+#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */\r
+\r
+/* SAU Region Limit Address Register Definitions */\r
+#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */\r
+#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */\r
+\r
+#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */\r
+#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */\r
+\r
+#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */\r
+#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */\r
+\r
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\r
+\r
+/* Secure Fault Status Register Definitions */\r
+#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */\r
+#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */\r
+\r
+#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */\r
+#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */\r
+\r
+#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */\r
+#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */\r
+\r
+#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */\r
+#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */\r
+\r
+#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */\r
+#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */\r
+\r
+#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */\r
+#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */\r
+\r
+#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */\r
+#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */\r
+\r
+#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */\r
+#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */\r
+\r
+/*@} end of group CMSIS_SAU */\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */\r
+#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */\r
+#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */\r
+\r
+#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */\r
+#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */\r
+\r
+#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */\r
+#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */\r
+\r
+#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */\r
+#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */\r
+#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */\r
+#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */\r
+#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ uint32_t RESERVED4[1U];\r
+ __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */\r
+ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */\r
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/* Debug Authentication Control Register Definitions */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\r
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\r
+\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\r
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\r
+\r
+/* Debug Security Control and Status Register Definitions */\r
+#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */\r
+#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */\r
+#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */\r
+\r
+#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */\r
+#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Core Hardware */\r
+ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+ #endif\r
+\r
+ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */\r
+ #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */\r
+ #endif\r
+\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+ #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */\r
+ #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */\r
+ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */\r
+ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */\r
+ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */\r
+\r
+ #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */\r
+ #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */\r
+ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */\r
+ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */\r
+ #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */\r
+\r
+ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */\r
+ #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */\r
+ #endif\r
+\r
+ #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */\r
+ #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+#ifdef CMSIS_NVIC_VIRTUAL\r
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"\r
+ #endif\r
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping\r
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping\r
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ\r
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ\r
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ\r
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ\r
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ\r
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ\r
+ #define NVIC_GetActive __NVIC_GetActive\r
+ #define NVIC_SetPriority __NVIC_SetPriority\r
+ #define NVIC_GetPriority __NVIC_GetPriority\r
+ #define NVIC_SystemReset __NVIC_SystemReset\r
+#endif /* CMSIS_NVIC_VIRTUAL */\r
+\r
+#ifdef CMSIS_VECTAB_VIRTUAL\r
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"\r
+ #endif\r
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\r
+#else\r
+ #define NVIC_SetVector __NVIC_SetVector\r
+ #define NVIC_GetVector __NVIC_GetVector\r
+#endif /* (CMSIS_VECTAB_VIRTUAL) */\r
+\r
+#define NVIC_USER_IRQ_OFFSET 16\r
+\r
+\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt\r
+ \details Enables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status\r
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt\r
+ \details Disables a device specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ __DSB();\r
+ __ISB();\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Get Interrupt Target State\r
+ \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ \return 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Target State\r
+ \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Interrupt Target State\r
+ \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 if interrupt is assigned to Secure\r
+ 1 if interrupt is assigned to Non Secure\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\r
+ return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every processor exception.\r
+ */\r
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of a device specific interrupt or a processor exception.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Vector\r
+ \details Sets an interrupt vector in SRAM based interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ VTOR must been relocated to SRAM before.\r
+ \param [in] IRQn Interrupt number\r
+ \param [in] vector Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Vector\r
+ \details Reads an interrupt vector from interrupt vector table.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Address of interrupt handler function\r
+ */\r
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\r
+{\r
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;\r
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void __NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief Set Priority Grouping (non-secure)\r
+ \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB_NS->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */\r
+ SCB_NS->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping (non-secure)\r
+ \details Reads the priority grouping field from the non-secure NVIC when in secure state.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\r
+{\r
+ return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable Interrupt (non-secure)\r
+ \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Enable status (non-secure)\r
+ \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt is not enabled.\r
+ \return 1 Interrupt is enabled.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable Interrupt (non-secure)\r
+ \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt (non-secure)\r
+ \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt (non-secure)\r
+ \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt (non-secure)\r
+ \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt (non-secure)\r
+ \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\r
+ \param [in] IRQn Device specific interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ \note IRQn must not be negative.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+ }\r
+ else\r
+ {\r
+ return(0U);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority (non-secure)\r
+ \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ \note The priority cannot be set for every non-secure processor exception.\r
+ */\r
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority (non-secure)\r
+ \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\r
+ The interrupt number can be positive to specify a device specific interrupt,\r
+ or negative to specify a processor exception.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) >= 0)\r
+ {\r
+ return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+/* ########################## MPU functions #################################### */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\r
+\r
+#include "mpu_armv8.h"\r
+\r
+#endif\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = FPU->MVFR0;\r
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\r
+ {\r
+ return 2U; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\r
+ {\r
+ return 1U; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0U; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## SAU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SAUFunctions SAU Functions\r
+ \brief Functions that configure the SAU.\r
+ @{\r
+ */\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+\r
+/**\r
+ \brief Enable SAU\r
+ \details Enables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Enable(void)\r
+{\r
+ SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+\r
+\r
+/**\r
+ \brief Disable SAU\r
+ \details Disables the Security Attribution Unit (SAU).\r
+ */\r
+__STATIC_INLINE void TZ_SAU_Disable(void)\r
+{\r
+ SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\r
+}\r
+\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+/*@} end of CMSIS_Core_SAUFunctions */\r
+\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\r
+/**\r
+ \brief System Tick Configuration (non-secure)\r
+ \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM33_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv7.h\r
+ * @brief CMSIS MPU API for Armv7-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+ \r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+ \r
+#ifndef ARM_MPU_ARMV7_H\r
+#define ARM_MPU_ARMV7_H\r
+\r
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)\r
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)\r
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)\r
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)\r
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)\r
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)\r
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)\r
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)\r
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)\r
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)\r
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)\r
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)\r
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)\r
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)\r
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)\r
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)\r
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)\r
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)\r
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)\r
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)\r
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)\r
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)\r
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)\r
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)\r
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)\r
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)\r
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)\r
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)\r
+\r
+#define ARM_MPU_AP_NONE 0U \r
+#define ARM_MPU_AP_PRIV 1U\r
+#define ARM_MPU_AP_URO 2U\r
+#define ARM_MPU_AP_FULL 3U\r
+#define ARM_MPU_AP_PRO 5U\r
+#define ARM_MPU_AP_RO 6U\r
+\r
+/** MPU Region Base Address Register Value\r
+*\r
+* \param Region The region to be configured, number 0 to 15.\r
+* \param BaseAddress The base address for the region.\r
+*/\r
+#define ARM_MPU_RBAR(Region, BaseAddress) \\r
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \\r
+ ((Region) & MPU_RBAR_REGION_Msk) | \\r
+ (MPU_RBAR_VALID_Msk))\r
+\r
+/**\r
+* MPU Region Attribute and Size Register Value\r
+* \r
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.\r
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.\r
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\r
+* \param IsShareable Region is shareable between multiple bus masters.\r
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.\r
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\r
+* \param SubRegionDisable Sub-region disable field.\r
+* \param Size Region size of the region to be configured, for example 4K, 8K.\r
+*/ \r
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\r
+ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \\r
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \\r
+ (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \\r
+ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \\r
+ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \\r
+ (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \\r
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \\r
+ (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \\r
+ (MPU_RASR_ENABLE_Msk))\r
+\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; //!< The region base address register value (RBAR)\r
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RASR = 0U;\r
+}\r
+\r
+/** Configure an MPU region.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rsar Value for RSAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\r
+{\r
+ MPU->RNR = rnr;\r
+ MPU->RBAR = rbar;\r
+ MPU->RASR = rasr;\r
+}\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ while (cnt > MPU_TYPE_RALIASES) {\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\r
+ table += MPU_TYPE_RALIASES;\r
+ cnt -= MPU_TYPE_RALIASES;\r
+ }\r
+ orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\r
+}\r
+\r
+#endif\r
--- /dev/null
+/******************************************************************************\r
+ * @file mpu_armv8.h\r
+ * @brief CMSIS MPU API for Armv8-M MPU\r
+ * @version V5.0.4\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef ARM_MPU_ARMV8_H\r
+#define ARM_MPU_ARMV8_H\r
+\r
+/** \brief Attribute for device memory (outer only) */\r
+#define ARM_MPU_ATTR_DEVICE ( 0U )\r
+\r
+/** \brief Attribute for non-cacheable, normal memory */\r
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )\r
+\r
+/** \brief Attribute for normal memory (outer and inner)\r
+* \param NT Non-Transient: Set to 1 for non-transient data.\r
+* \param WB Write-Back: Set to 1 to use write-back update policy.\r
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.\r
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.\r
+*/\r
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\r
+ (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\r
+\r
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)\r
+\r
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)\r
+\r
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\r
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)\r
+\r
+/** \brief Memory Attribute\r
+* \param O Outer memory attributes\r
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\r
+*/\r
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\r
+\r
+/** \brief Normal memory non-shareable */\r
+#define ARM_MPU_SH_NON (0U)\r
+\r
+/** \brief Normal memory outer shareable */\r
+#define ARM_MPU_SH_OUTER (2U)\r
+\r
+/** \brief Normal memory inner shareable */\r
+#define ARM_MPU_SH_INNER (3U)\r
+\r
+/** \brief Memory access permissions\r
+* \param RO Read-Only: Set to 1 for read-only memory.\r
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.\r
+*/\r
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\r
+\r
+/** \brief Region Base Address Register value\r
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\r
+* \param SH Defines the Shareability domain for this memory region.\r
+* \param RO Read-Only: Set to 1 for a read-only memory region.\r
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.\r
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.\r
+*/\r
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\r
+ ((BASE & MPU_RBAR_BASE_Pos) | \\r
+ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\r
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\r
+ ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\r
+\r
+/** \brief Region Limit Address Register value\r
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\r
+* \param IDX The attribute index to be associated with this memory region.\r
+*/\r
+#define ARM_MPU_RLAR(LIMIT, IDX) \\r
+ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\r
+ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\r
+ (MPU_RLAR_EN_Msk))\r
+\r
+/**\r
+* Struct for a single MPU Region\r
+*/\r
+typedef struct {\r
+ uint32_t RBAR; /*!< Region Base Address Register value */\r
+ uint32_t RLAR; /*!< Region Limit Address Register value */\r
+} ARM_MPU_Region_t;\r
+ \r
+/** Enable the MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Enable the Non-secure MPU.\r
+* \param MPU_Control Default access permissions for unconfigured regions.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+}\r
+\r
+/** Disable the Non-secure MPU.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)\r
+{\r
+ __DSB();\r
+ __ISB();\r
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk\r
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\r
+#endif\r
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;\r
+}\r
+#endif\r
+\r
+/** Set the memory attribute encoding to the given MPU.\r
+* \param mpu Pointer to the MPU to be configured.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\r
+{\r
+ const uint8_t reg = idx / 4U;\r
+ const uint32_t pos = ((idx % 4U) * 8U);\r
+ const uint32_t mask = 0xFFU << pos;\r
+ \r
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\r
+ return; // invalid index\r
+ }\r
+ \r
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\r
+}\r
+\r
+/** Set the memory attribute encoding.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Set the memory attribute encoding to the Non-secure MPU.\r
+* \param idx The attribute index to be set [0-7]\r
+* \param attr The attribute value to be set.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\r
+{\r
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\r
+}\r
+#endif\r
+\r
+/** Clear and disable the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RLAR = 0U;\r
+}\r
+\r
+/** Clear and disable the given MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\r
+{\r
+ ARM_MPU_ClrRegionEx(MPU, rnr);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Clear and disable the given Non-secure MPU region.\r
+* \param rnr Region number to be cleared.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\r
+{ \r
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);\r
+}\r
+#endif\r
+\r
+/** Configure the given MPU region of the given MPU.\r
+* \param mpu Pointer to MPU to be used.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ mpu->RNR = rnr;\r
+ mpu->RBAR = rbar;\r
+ mpu->RLAR = rlar;\r
+}\r
+\r
+/** Configure the given MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Configure the given Non-secure MPU region.\r
+* \param rnr Region number to be configured.\r
+* \param rbar Value for RBAR register.\r
+* \param rlar Value for RLAR register.\r
+*/ \r
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\r
+{\r
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); \r
+}\r
+#endif\r
+\r
+/** Memcopy with strictly ordered memory access, e.g. for register targets.\r
+* \param dst Destination data is copied to.\r
+* \param src Source data is copied from.\r
+* \param len Amount of data words to be copied.\r
+*/\r
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\r
+{\r
+ uint32_t i;\r
+ for (i = 0U; i < len; ++i) \r
+ {\r
+ dst[i] = src[i];\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table to the given MPU.\r
+* \param mpu Pointer to the MPU registers to be used.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\r
+ if (cnt == 1U) {\r
+ mpu->RNR = rnr;\r
+ orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\r
+ } else {\r
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);\r
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\r
+ \r
+ mpu->RNR = rnrBase;\r
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\r
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\r
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\r
+ table += c;\r
+ cnt -= c;\r
+ rnrOffset = 0U;\r
+ rnrBase += MPU_TYPE_RALIASES;\r
+ mpu->RNR = rnrBase;\r
+ }\r
+ \r
+ orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\r
+ }\r
+}\r
+\r
+/** Load the given number of MPU regions from a table.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);\r
+}\r
+\r
+#ifdef MPU_NS\r
+/** Load the given number of MPU regions from a table to the Non-secure MPU.\r
+* \param rnr First region number to be configured.\r
+* \param table Pointer to the MPU configuration table.\r
+* \param cnt Amount of regions to be configured.\r
+*/\r
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \r
+{\r
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file tz_context.h\r
+ * @brief Context Management for Armv8-M TrustZone\r
+ * @version V1.0.1\r
+ * @date 10. January 2018\r
+ ******************************************************************************/\r
+/*\r
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: Apache-2.0\r
+ *\r
+ * Licensed under the Apache License, Version 2.0 (the License); you may\r
+ * not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at\r
+ *\r
+ * www.apache.org/licenses/LICENSE-2.0\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software\r
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT\r
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ */\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined (__clang__)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef TZ_CONTEXT_H\r
+#define TZ_CONTEXT_H\r
+ \r
+#include <stdint.h>\r
+ \r
+#ifndef TZ_MODULEID_T\r
+#define TZ_MODULEID_T\r
+/// \details Data type that identifies secure software modules called by a process.\r
+typedef uint32_t TZ_ModuleId_t;\r
+#endif\r
+ \r
+/// \details TZ Memory ID identifies an allocated memory slot.\r
+typedef uint32_t TZ_MemoryId_t;\r
+ \r
+/// Initialize secure context memory system\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_InitContextSystem_S (void);\r
+ \r
+/// Allocate context memory for calling secure software modules in TrustZone\r
+/// \param[in] module identifies software modules called from non-secure mode\r
+/// \return value != 0 id TrustZone memory slot identifier\r
+/// \return value 0 no memory available or internal error\r
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\r
+ \r
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\r
+ \r
+/// Load secure context (called on RTOS thread context switch)\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\r
+ \r
+/// Store secure context (called on RTOS thread context switch)\r
+/// \param[in] id TrustZone memory slot identifier\r
+/// \return execution status (1: success, 0: error)\r
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\r
+ \r
+#endif // TZ_CONTEXT_H\r
--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include <stdint.h>\r
+#include "fsl_common.h"\r
+#include "fsl_debug_console.h"\r
+#include "board.h"\r
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED\r
+#include "fsl_i2c.h"\r
+#endif /* SDK_I2C_BASED_COMPONENT_USED */\r
+#if defined BOARD_USE_CODEC\r
+#include "fsl_wm8904.h"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+#if defined BOARD_USE_CODEC\r
+codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send,\r
+ .I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,\r
+ .op.Init = WM8904_Init,\r
+ .op.Deinit = WM8904_Deinit,\r
+ .op.SetFormat = WM8904_SetAudioFormat};\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+/* Initialize debug console. */\r
+void BOARD_InitDebugConsole(void)\r
+{\r
+ /* attach 12 MHz clock to FLEXCOMM0 (debug console) */\r
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);\r
+ \r
+ RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST);\r
+\r
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;\r
+\r
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);\r
+}\r
+\r
+void BOARD_InitDebugConsole_Core1(void)\r
+{\r
+ RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST_CORE1);\r
+\r
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ_CORE1;\r
+\r
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE_CORE1, BOARD_DEBUG_UART_BAUDRATE_CORE1, BOARD_DEBUG_UART_TYPE_CORE1,\r
+ uartClkSrcFreq);\r
+}\r
+\r
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED\r
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)\r
+{\r
+ i2c_master_config_t i2cConfig = {0};\r
+\r
+ I2C_MasterGetDefaultConfig(&i2cConfig);\r
+ I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);\r
+}\r
+\r
+status_t BOARD_I2C_Send(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *txBuff,\r
+ uint8_t txBuffSize)\r
+{\r
+ i2c_master_transfer_t masterXfer;\r
+\r
+ /* Prepare transfer structure. */\r
+ masterXfer.slaveAddress = deviceAddress;\r
+ masterXfer.direction = kI2C_Write;\r
+ masterXfer.subaddress = subAddress;\r
+ masterXfer.subaddressSize = subaddressSize;\r
+ masterXfer.data = txBuff;\r
+ masterXfer.dataSize = txBuffSize;\r
+ masterXfer.flags = kI2C_TransferDefaultFlag;\r
+\r
+ return I2C_MasterTransferBlocking(base, &masterXfer);\r
+}\r
+\r
+status_t BOARD_I2C_Receive(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *rxBuff,\r
+ uint8_t rxBuffSize)\r
+{\r
+ i2c_master_transfer_t masterXfer;\r
+\r
+ /* Prepare transfer structure. */\r
+ masterXfer.slaveAddress = deviceAddress;\r
+ masterXfer.subaddress = subAddress;\r
+ masterXfer.subaddressSize = subaddressSize;\r
+ masterXfer.data = rxBuff;\r
+ masterXfer.dataSize = rxBuffSize;\r
+ masterXfer.direction = kI2C_Read;\r
+ masterXfer.flags = kI2C_TransferDefaultFlag;\r
+\r
+ return I2C_MasterTransferBlocking(base, &masterXfer);\r
+}\r
+\r
+void BOARD_Accel_I2C_Init(void)\r
+{\r
+ BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);\r
+}\r
+\r
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)\r
+{\r
+ uint8_t data = (uint8_t)txBuff;\r
+\r
+ return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);\r
+}\r
+\r
+status_t BOARD_Accel_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)\r
+{\r
+ return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);\r
+}\r
+\r
+void BOARD_Codec_I2C_Init(void)\r
+{\r
+ BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);\r
+}\r
+\r
+status_t BOARD_Codec_I2C_Send(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)\r
+{\r
+ return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,\r
+ txBuffSize);\r
+}\r
+\r
+status_t BOARD_Codec_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)\r
+{\r
+ return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);\r
+}\r
+#endif /* SDK_I2C_BASED_COMPONENT_USED */\r
--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _BOARD_H_\r
+#define _BOARD_H_\r
+\r
+#include "clock_config.h"\r
+#include "fsl_common.h"\r
+#include "fsl_reset.h"\r
+#include "fsl_gpio.h"\r
+#include "fsl_iocon.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/*! @brief The board name */\r
+#define BOARD_NAME "LPCXpresso5500"\r
+\r
+/*! @brief The UART to use for debug messages. */\r
+/* TODO: rename UART to USART */\r
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart\r
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0\r
+#define BOARD_DEBUG_UART_INSTANCE 0U\r
+#define BOARD_DEBUG_UART_CLK_FREQ 12000000U\r
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0\r
+#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn\r
+#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0\r
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler\r
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn\r
+\r
+#define BOARD_ACCEL_I2C_BASEADDR I2C4\r
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000\r
+\r
+#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart\r
+#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1\r
+#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U\r
+#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U\r
+#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1\r
+#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn\r
+#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1\r
+#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler\r
+#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn\r
+\r
+#ifndef BOARD_DEBUG_UART_BAUDRATE\r
+#define BOARD_DEBUG_UART_BAUDRATE 115200U\r
+#endif /* BOARD_DEBUG_UART_BAUDRATE */\r
+\r
+#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1\r
+#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U\r
+#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */\r
+\r
+#define BOARD_CODEC_I2C_BASEADDR I2C4\r
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000\r
+\r
+#ifndef BOARD_LED_RED_GPIO\r
+#define BOARD_LED_RED_GPIO GPIO\r
+#endif\r
+#define BOARD_LED_RED_GPIO_PORT 1U\r
+#ifndef BOARD_LED_RED_GPIO_PIN\r
+#define BOARD_LED_RED_GPIO_PIN 6U\r
+#endif\r
+\r
+#ifndef BOARD_LED_BLUE_GPIO\r
+#define BOARD_LED_BLUE_GPIO GPIO\r
+#endif\r
+#define BOARD_LED_BLUE_GPIO_PORT 1U\r
+#ifndef BOARD_LED_BLUE_GPIO_PIN\r
+#define BOARD_LED_BLUE_GPIO_PIN 4U\r
+#endif\r
+\r
+#ifndef BOARD_LED_GREEN_GPIO\r
+#define BOARD_LED_GREEN_GPIO GPIO\r
+#endif\r
+#define BOARD_LED_GREEN_GPIO_PORT 1U\r
+#ifndef BOARD_LED_GREEN_GPIO_PIN\r
+#define BOARD_LED_GREEN_GPIO_PIN 7U\r
+#endif\r
+\r
+#ifndef BOARD_SW1_GPIO\r
+#define BOARD_SW1_GPIO GPIO\r
+#endif\r
+#define BOARD_SW1_GPIO_PORT 0U\r
+#ifndef BOARD_SW1_GPIO_PIN\r
+#define BOARD_SW1_GPIO_PIN 5U\r
+#endif\r
+#define BOARD_SW1_NAME "SW1"\r
+#define BOARD_SW1_IRQ PIN_INT0_IRQn\r
+#define BOARD_SW1_IRQ_HANDLER PIN_INT0_IRQHandler\r
+\r
+#ifndef BOARD_SW2_GPIO\r
+#define BOARD_SW2_GPIO GPIO\r
+#endif\r
+#define BOARD_SW2_GPIO_PORT 1U\r
+#ifndef BOARD_SW2_GPIO_PIN\r
+#define BOARD_SW2_GPIO_PIN 18U\r
+#endif\r
+#define BOARD_SW2_NAME "SW2"\r
+#define BOARD_SW2_IRQ PIN_INT1_IRQn\r
+#define BOARD_SW2_IRQ_HANDLER PIN_INT1_IRQHandler\r
+#define BOARD_SW2_GPIO_PININT_INDEX 1\r
+\r
+#ifndef BOARD_SW3_GPIO\r
+#define BOARD_SW3_GPIO GPIO\r
+#endif\r
+#define BOARD_SW3_GPIO_PORT 1U\r
+#ifndef BOARD_SW3_GPIO_PIN\r
+#define BOARD_SW3_GPIO_PIN 9U\r
+#endif\r
+#define BOARD_SW3_NAME "SW3"\r
+#define BOARD_SW3_IRQ PIN_INT1_IRQn\r
+#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler\r
+#define BOARD_SW3_GPIO_PININT_INDEX 1\r
+\r
+#define BOARD_SDIF_BASEADDR SDIF\r
+#define BOARD_SDIF_CLKSRC kCLOCK_SDio\r
+#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio)\r
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK\r
+#define BOARD_SDIF_IRQ SDIO_IRQn\r
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360\r
+#define BOARD_SD_CARD_DETECT_PIN 17\r
+#define BOARD_SD_CARD_DETECT_PORT 0\r
+#define BOARD_SD_CARD_DETECT_GPIO GPIO\r
+#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD\r
+\r
+#define BOARD_SDIF_CD_GPIO_INIT() \\r
+ { \\r
+ CLOCK_EnableClock(kCLOCK_Gpio2); \\r
+ GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \\r
+ }\r
+#define BOARD_SDIF_CD_STATUS() \\r
+ GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)\r
+\r
+/* Board led color mapping */\r
+#define LOGIC_LED_ON 0U\r
+#define LOGIC_LED_OFF 1U\r
+\r
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK\r
+\r
+#define LED_RED_INIT(output) \\r
+ { \\r
+ IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \\r
+ (IOCON_PIO_FUNC0 |IOCON_PIO_MODE_INACT |IOCON_PIO_SLEW_STANDARD |IOCON_PIO_INV_DI |IOCON_PIO_DIGITAL_EN |IOCON_PIO_OPENDRAIN_DI)); \\r
+ GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \\r
+ }\r
+#define LED_RED_ON() \\r
+ GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \\r
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 */\r
+#define LED_RED_OFF() \\r
+ GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \\r
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 \ \ \ \ \ \ \ \ \ \ \\r
+ */\r
+#define LED_RED_TOGGLE() \\r
+ GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \\r
+ 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */\r
+\r
+#define LED_BLUE_INIT(output) \\r
+ { \\r
+ IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \\r
+ (IOCON_PIO_FUNC0 |IOCON_PIO_MODE_INACT |IOCON_PIO_SLEW_STANDARD |IOCON_PIO_INV_DI |IOCON_PIO_DIGITAL_EN |IOCON_PIO_OPENDRAIN_DI)); \\r
+ GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \\r
+ }\r
+#define LED_BLUE_ON() \\r
+ GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \\r
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */\r
+#define LED_BLUE_OFF() \\r
+ GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \\r
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */\r
+#define LED_BLUE_TOGGLE() \\r
+ GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \\r
+ 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */\r
+\r
+#define LED_GREEN_INIT(output) \\r
+ GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \\r
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */\r
+#define LED_GREEN_ON() \\r
+ GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \\r
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */\r
+#define LED_GREEN_OFF() \\r
+ GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \\r
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */\r
+#define LED_GREEN_TOGGLE() \\r
+ GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \\r
+ 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */\r
+\r
+/*! @brief The WIFI-QCA shield pin. */\r
+#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO\r
+#define BOARD_INITGT202SHIELD_PWRON_PORT 1U\r
+#define BOARD_INITGT202SHIELD_PWRON_PIN 8U\r
+\r
+#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO\r
+#define BOARD_INITGT202SHIELD_IRQ_PORT 1U\r
+#define BOARD_INITGT202SHIELD_IRQ_PIN 9U\r
+\r
+/*! @brief The WIFI-QCA shield pin. */\r
+#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO\r
+#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U\r
+#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 7U\r
+\r
+#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO\r
+#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0U\r
+#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 15U\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+void BOARD_InitDebugConsole(void);\r
+void BOARD_InitDebugConsole_Core1(void);\r
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED\r
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);\r
+status_t BOARD_I2C_Send(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *txBuff,\r
+ uint8_t txBuffSize);\r
+status_t BOARD_I2C_Receive(I2C_Type *base,\r
+ uint8_t deviceAddress,\r
+ uint32_t subAddress,\r
+ uint8_t subaddressSize,\r
+ uint8_t *rxBuff,\r
+ uint8_t rxBuffSize);\r
+void BOARD_Accel_I2C_Init(void);\r
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);\r
+status_t BOARD_Accel_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);\r
+void BOARD_Codec_I2C_Init(void);\r
+status_t BOARD_Codec_I2C_Send(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);\r
+status_t BOARD_Codec_I2C_Receive(\r
+ uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);\r
+#endif /* SDK_I2C_BASED_COMPONENT_USED */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* _BOARD_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+/*\r
+ * How to set up clock using clock driver functions:\r
+ *\r
+ * 1. Setup clock sources.\r
+ *\r
+ * 2. Set up wait states of the flash.\r
+ *\r
+ * 3. Set up all dividers.\r
+ *\r
+ * 4. Set up all selectors to provide selected clocks.\r
+ */\r
+\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!GlobalInfo\r
+product: Clocks v5.0\r
+processor: LPC55S69\r
+package_id: LPC55S69JBD100\r
+mcu_data: ksdk2_0\r
+processor_version: 0.0.6\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+#include "fsl_power.h"\r
+#include "fsl_clock.h"\r
+#include "clock_config.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+/* System clock frequency. */\r
+extern uint32_t SystemCoreClock;\r
+\r
+/*******************************************************************************\r
+ ************************ BOARD_InitBootClocks function ************************\r
+ ******************************************************************************/\r
+void BOARD_InitBootClocks(void)\r
+{\r
+ BOARD_BootClockFROHF96M();\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockFRO12M **********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFRO12M\r
+outputs:\r
+- {id: System_clock.outFreq, value: 12 MHz}\r
+settings:\r
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}\r
+sources:\r
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFRO12M(void)\r
+{\r
+#ifndef SDK_SECONDARY_CORE\r
+ /*!< Set up the clock sources */\r
+ /*!< Configure FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */\r
+\r
+ CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */\r
+\r
+ POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */\r
+\r
+ /*< Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;\r
+#endif\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF96M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockFROHF96M\r
+called_from_default_init: true\r
+outputs:\r
+- {id: System_clock.outFreq, value: 96 MHz}\r
+settings:\r
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}\r
+- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}\r
+sources:\r
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockFROHF96M(void)\r
+{\r
+#ifndef SDK_SECONDARY_CORE\r
+ /*!< Set up the clock sources */\r
+ /*!< Configure FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */\r
+\r
+ CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */\r
+\r
+ POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */\r
+\r
+ /*< Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;\r
+#endif\r
+}\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockPLL100M *********************\r
+ ******************************************************************************/\r
+/* clang-format off */\r
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!Configuration\r
+name: BOARD_BootClockPLL100M\r
+outputs:\r
+- {id: System_clock.outFreq, value: 100 MHz}\r
+settings:\r
+- {id: PLL0_Mode, value: Normal}\r
+- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}\r
+- {id: ENABLE_CLKIN_ENA, value: Enabled}\r
+- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}\r
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}\r
+- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}\r
+- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}\r
+- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}\r
+- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}\r
+sources:\r
+- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}\r
+- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/\r
+/* clang-format on */\r
+\r
+/*******************************************************************************\r
+ * Variables for BOARD_BootClockPLL100M configuration\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Code for BOARD_BootClockPLL100M configuration\r
+ ******************************************************************************/\r
+void BOARD_BootClockPLL100M(void)\r
+{\r
+#ifndef SDK_SECONDARY_CORE\r
+ /*!< Set up the clock sources */\r
+ /*!< Configure FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */\r
+ CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */\r
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */\r
+\r
+ CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */\r
+ CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */\r
+\r
+ POWER_SetVoltageForFreq(100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */\r
+ CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */\r
+\r
+ /*!< Set up PLL */\r
+ CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); \r
+ const pll_setup_t pll0Setup = {\r
+ .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),\r
+ .pllndec = SYSCON_PLL0NDEC_NDIV(4U),\r
+ .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),\r
+ .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},\r
+ .pllRate = 100000000U,\r
+ .flags = PLL_SETUPFLAG_WAITLOCK\r
+ };\r
+ CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */\r
+\r
+ /*!< Set up dividers */\r
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */\r
+\r
+ /*!< Set up clock selectors - Attach clocks to the peripheries */\r
+ CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */\r
+\r
+ /*< Set SystemCoreClock variable. */\r
+ SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;\r
+#endif\r
+}\r
+\r
--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+\r
+#ifndef _CLOCK_CONFIG_H_\r
+#define _CLOCK_CONFIG_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */\r
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */\r
+\r
+/*******************************************************************************\r
+ ************************ BOARD_InitBootClocks function ************************\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes default configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_InitBootClocks(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockFRO12M **********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */\r
+\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockFRO12M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockFRO12M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************* Configuration BOARD_BootClockFROHF96M *********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */\r
+\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockFROHF96M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockFROHF96M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+/*******************************************************************************\r
+ ******************** Configuration BOARD_BootClockPLL100M *********************\r
+ ******************************************************************************/\r
+/*******************************************************************************\r
+ * Definitions for BOARD_BootClockPLL100M configuration\r
+ ******************************************************************************/\r
+#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */\r
+\r
+\r
+/*******************************************************************************\r
+ * API for BOARD_BootClockPLL100M configuration\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus*/\r
+\r
+/*!\r
+ * @brief This function executes configuration of clocks.\r
+ *\r
+ */\r
+void BOARD_BootClockPLL100M(void);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus*/\r
+\r
+#endif /* _CLOCK_CONFIG_H_ */\r
+\r
--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+\r
+/* clang-format off */\r
+/*\r
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+!!GlobalInfo\r
+product: Pins v5.0\r
+processor: LPC55S69\r
+package_id: LPC55S69JBD100\r
+mcu_data: ksdk2_0\r
+processor_version: 0.0.6\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********\r
+ */\r
+/* clang-format on */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_iocon.h"\r
+#include "pin_mux.h"\r
+\r
+/* FUNCTION ************************************************************************************************************\r
+ *\r
+ * Function Name : BOARD_InitBootPins\r
+ * Description : Calls initialization functions.\r
+ *\r
+ * END ****************************************************************************************************************/\r
+void BOARD_InitBootPins(void)\r
+{\r
+ BOARD_InitPins();\r
+}\r
+\r
+/* clang-format off */\r
+/*\r
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************\r
+BOARD_InitPins:\r
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}\r
+- pin_list:\r
+ - {pin_num: '92', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI_DATA, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI_DATA/SD1_D2/CTIMER2_MAT3/SCT0_OUT8/CMP0_OUT/PLU_OUT2/SECURE_GPIO0_29,\r
+ mode: inactive, slew_rate: standard, invert: disabled, digi_mode: digital, open_drain: disabled}\r
+ - {pin_num: '94', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO_WS, pin_signal: PIO0_30/FC0_TXD_SCL_MISO_WS/SD1_D3/CTIMER0_MAT0/SCT0_OUT9/SECURE_GPIO0_30, mode: inactive,\r
+ slew_rate: standard, invert: disabled, digi_mode: digital, open_drain: disabled}\r
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********\r
+ */\r
+/* clang-format on */\r
+\r
+/* FUNCTION ************************************************************************************************************\r
+ *\r
+ * Function Name : BOARD_InitPins\r
+ * Description : Configures pin routing and optionally pin electrical features.\r
+ *\r
+ * END ****************************************************************************************************************/\r
+/* Function assigned for the Cortex-M33 (Core #0) */\r
+void BOARD_InitPins(void)\r
+{\r
+ /* Enables the clock for the I/O controller.: Enable Clock. */\r
+ CLOCK_EnableClock(kCLOCK_Iocon);\r
+\r
+ const uint32_t port0_pin29_config = (/* Pin is configured as FC0_RXD_SDA_MOSI_DATA */\r
+ IOCON_PIO_FUNC1 |\r
+ /* No addition pin function */\r
+ IOCON_PIO_MODE_INACT |\r
+ /* Standard mode, output slew rate control is enabled */\r
+ IOCON_PIO_SLEW_STANDARD |\r
+ /* Input function is not inverted */\r
+ IOCON_PIO_INV_DI |\r
+ /* Enables digital function */\r
+ IOCON_PIO_DIGITAL_EN |\r
+ /* Open drain is disabled */\r
+ IOCON_PIO_OPENDRAIN_DI);\r
+ /* PORT0 PIN29 (coords: 92) is configured as FC0_RXD_SDA_MOSI_DATA */\r
+ IOCON_PinMuxSet(IOCON, 0U, 29U, port0_pin29_config);\r
+\r
+ const uint32_t port0_pin30_config = (/* Pin is configured as FC0_TXD_SCL_MISO_WS */\r
+ IOCON_PIO_FUNC1 |\r
+ /* No addition pin function */\r
+ IOCON_PIO_MODE_INACT |\r
+ /* Standard mode, output slew rate control is enabled */\r
+ IOCON_PIO_SLEW_STANDARD |\r
+ /* Input function is not inverted */\r
+ IOCON_PIO_INV_DI |\r
+ /* Enables digital function */\r
+ IOCON_PIO_DIGITAL_EN |\r
+ /* Open drain is disabled */\r
+ IOCON_PIO_OPENDRAIN_DI);\r
+ /* PORT0 PIN30 (coords: 94) is configured as FC0_TXD_SCL_MISO_WS */\r
+ IOCON_PinMuxSet(IOCON, 0U, 30U, port0_pin30_config);\r
+}\r
+/***********************************************************************************************************************\r
+ * EOF\r
+ **********************************************************************************************************************/\r
--- /dev/null
+/*\r
+ * Copyright 2017-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file\r
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.\r
+ **********************************************************************************************************************/\r
+\r
+#ifndef _PIN_MUX_H_\r
+#define _PIN_MUX_H_\r
+\r
+/*!\r
+ * @addtogroup pin_mux\r
+ * @{\r
+ */\r
+\r
+/***********************************************************************************************************************\r
+ * API\r
+ **********************************************************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @brief Calls initialization functions.\r
+ *\r
+ */\r
+void BOARD_InitBootPins(void);\r
+\r
+#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */\r
+#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */\r
+#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function is not inverted */\r
+#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */\r
+#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */\r
+#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard mode, output slew rate control is enabled */\r
+\r
+/*!\r
+ * @brief Configures pin routing and optionally pin electrical features.\r
+ *\r
+ */\r
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 (Core #0) */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */\r
+#endif /* _PIN_MUX_H_ */\r
+\r
+/***********************************************************************************************************************\r
+ * EOF\r
+ **********************************************************************************************************************/\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Include\r
+*************************************************************************************\r
+********************************************************************************** */\r
+#include "fsl_common.h"\r
+#include "generic_list.h"\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public functions\r
+*************************************************************************************\r
+********************************************************************************** */\r
+/*! *********************************************************************************\r
+* \brief Initialises the list descriptor.\r
+*\r
+* \param[in] list - LIST_ handle to init.\r
+* max - Maximum number of elements in list. 0 for unlimited.\r
+*\r
+* \return void.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+void LIST_Init(list_handle_t list, uint32_t max)\r
+{\r
+ list->head = NULL;\r
+ list->tail = NULL;\r
+ list->max = max;\r
+ list->size = 0;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Gets the list that contains the given element.\r
+*\r
+* \param[in] element - Handle of the element.\r
+*\r
+* \return NULL if element is orphan.\r
+* Handle of the list the element is inserted into.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_handle_t LIST_GetList(list_element_handle_t element)\r
+{\r
+ return element->list;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Links element to the tail of the list.\r
+*\r
+* \param[in] list - ID of list to insert into.\r
+* element - element to add\r
+*\r
+* \return kLIST_Full if list is full.\r
+* kLIST_Ok if insertion was successful.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)\r
+{\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((list->max != 0) && (list->max == list->size))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Full;\r
+ }\r
+\r
+ if (list->size == 0)\r
+ {\r
+ list->head = element;\r
+ }\r
+ else\r
+ {\r
+ list->tail->next = element;\r
+ }\r
+ element->prev = list->tail;\r
+ element->next = NULL;\r
+ element->list = list;\r
+ list->tail = element;\r
+ list->size++;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Links element to the head of the list.\r
+*\r
+* \param[in] list - ID of list to insert into.\r
+* element - element to add\r
+*\r
+* \return kLIST_Full if list is full.\r
+* kLIST_Ok if insertion was successful.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)\r
+{\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((list->max != 0) && (list->max == list->size))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Full;\r
+ }\r
+\r
+ if (list->size == 0)\r
+ {\r
+ list->tail = element;\r
+ }\r
+ else\r
+ {\r
+ list->head->prev = element;\r
+ }\r
+ element->next = list->head;\r
+ element->prev = NULL;\r
+ element->list = list;\r
+ list->head = element;\r
+ list->size++;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Unlinks element from the head of the list.\r
+*\r
+* \param[in] list - ID of list to remove from.\r
+*\r
+* \return NULL if list is empty.\r
+* ID of removed element(pointer) if removal was successful.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_element_handle_t LIST_RemoveHead(list_handle_t list)\r
+{\r
+ list_element_handle_t element;\r
+\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((NULL == list) || (list->size == 0))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return NULL; /*LIST_ is empty*/\r
+ }\r
+\r
+ element = list->head;\r
+ list->size--;\r
+ if (list->size == 0)\r
+ {\r
+ list->tail = NULL;\r
+ }\r
+ else\r
+ {\r
+ element->next->prev = NULL;\r
+ }\r
+ list->head = element->next; /*Is NULL if element is head*/\r
+ element->list = NULL;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return element;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Gets head element ID.\r
+*\r
+* \param[in] list - ID of list.\r
+*\r
+* \return NULL if list is empty.\r
+* ID of head element if list is not empty.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_element_handle_t LIST_GetHead(list_handle_t list)\r
+{\r
+ return list->head;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Gets next element ID.\r
+*\r
+* \param[in] element - ID of the element.\r
+*\r
+* \return NULL if element is tail.\r
+* ID of next element if exists.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_element_handle_t LIST_GetNext(list_element_handle_t element)\r
+{\r
+ return element->next;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Gets previous element ID.\r
+*\r
+* \param[in] element - ID of the element.\r
+*\r
+* \return NULL if element is head.\r
+* ID of previous element if exists.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)\r
+{\r
+ return element->prev;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Unlinks an element from its list.\r
+*\r
+* \param[in] element - ID of the element to remove.\r
+*\r
+* \return kLIST_OrphanElement if element is not part of any list.\r
+* kLIST_Ok if removal was successful.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_status_t LIST_RemoveElement(list_element_handle_t element)\r
+{\r
+ if (element->list == NULL)\r
+ {\r
+ return kLIST_OrphanElement; /*Element was previusly removed or never added*/\r
+ }\r
+\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if (element->prev == NULL) /*Element is head or solo*/\r
+ {\r
+ element->list->head = element->next; /*is null if solo*/\r
+ }\r
+ if (element->next == NULL) /*Element is tail or solo*/\r
+ {\r
+ element->list->tail = element->prev; /*is null if solo*/\r
+ }\r
+ if (element->prev != NULL) /*Element is not head*/\r
+ {\r
+ element->prev->next = element->next;\r
+ }\r
+ if (element->next != NULL) /*Element is not tail*/\r
+ {\r
+ element->next->prev = element->prev;\r
+ }\r
+ element->list->size--;\r
+ element->list = NULL;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Links an element in the previous position relative to a given member\r
+* of a list.\r
+*\r
+* \param[in] element - ID of a member of a list.\r
+* newElement - new element to insert before the given member.\r
+*\r
+* \return kLIST_OrphanElement if element is not part of any list.\r
+* kLIST_Full if list is full.\r
+* kLIST_Ok if insertion was successful.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)\r
+{\r
+ if (element->list == NULL)\r
+ {\r
+ return kLIST_OrphanElement; /*Element was previusly removed or never added*/\r
+ }\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+\r
+ if ((element->list->max != 0) && (element->list->max == element->list->size))\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Full;\r
+ }\r
+\r
+ if (element->prev == NULL) /*Element is list head*/\r
+ {\r
+ element->list->head = newElement;\r
+ }\r
+ else\r
+ {\r
+ element->prev->next = newElement;\r
+ }\r
+ newElement->list = element->list;\r
+ element->list->size++;\r
+ newElement->next = element;\r
+ newElement->prev = element->prev;\r
+ element->prev = newElement;\r
+\r
+ EnableGlobalIRQ(regPrimask);\r
+ return kLIST_Ok;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Gets the current size of a list.\r
+*\r
+* \param[in] list - ID of the list.\r
+*\r
+* \return Current size of the list.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+uint32_t LIST_GetSize(list_handle_t list)\r
+{\r
+ return list->size;\r
+}\r
+\r
+/*! *********************************************************************************\r
+* \brief Gets the number of free places in the list.\r
+*\r
+* \param[in] list - ID of the list.\r
+*\r
+* \return Available size of the list.\r
+*\r
+* \pre\r
+*\r
+* \post\r
+*\r
+* \remarks\r
+*\r
+********************************************************************************** */\r
+uint32_t LIST_GetAvailableSize(list_handle_t list)\r
+{\r
+ return (list->max - list->size);\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _GENERIC_LIST_H_\r
+#define _GENERIC_LIST_H_\r
+\r
+/*!*********************************************************************************\r
+*************************************************************************************\r
+* Include\r
+*************************************************************************************\r
+********************************************************************************** */\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public macro definitions\r
+*************************************************************************************\r
+********************************************************************************** */\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public type definitions\r
+*************************************************************************************\r
+********************************************************************************** */\r
+/*! @brief The list status */\r
+typedef enum _list_status\r
+{\r
+ kLIST_Ok = kStatus_Success, /*!< Success */\r
+ kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< FULL */\r
+ kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< Empty */\r
+ kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Orphan Element */\r
+}list_status_t;\r
+\r
+/*! @brief The list structure*/\r
+typedef struct list_tag\r
+{\r
+ struct list_element_tag *head; /*!< list head */\r
+ struct list_element_tag *tail; /*!< list tail */\r
+ uint16_t size; /*!< list size */\r
+ uint16_t max; /*!< list max number of elements */\r
+}list_t, *list_handle_t;\r
+\r
+/*! @brief The list element*/\r
+typedef struct list_element_tag\r
+{\r
+ struct list_element_tag *next; /*!< next list element */\r
+ struct list_element_tag *prev; /*!< previous list element */\r
+ struct list_tag *list; /*!< pointer to the list */\r
+}list_element_t, *list_element_handle_t;\r
+\r
+/*! *********************************************************************************\r
+*************************************************************************************\r
+* Public prototypes\r
+*************************************************************************************\r
+********************************************************************************** */\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+/*!\r
+ * @brief Initialize the list.\r
+ *\r
+ * This function initialize the list.\r
+ *\r
+ * @param list - List handle to initialize.\r
+ * @param max - Maximum number of elements in list. 0 for unlimited.\r
+ */\r
+void LIST_Init(list_handle_t list, uint32_t max);\r
+\r
+/*!\r
+ * @brief Gets the list that contains the given element.\r
+ *\r
+ *\r
+ * @param element - Handle of the element.\r
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.\r
+ */\r
+list_handle_t LIST_GetList(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Links element to the head of the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ * @param element - Handle of the element.\r
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.\r
+ */\r
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Links element to the tail of the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ * @param element - Handle of the element.\r
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.\r
+ */\r
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Unlinks element from the head of the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_RemoveHead(list_handle_t list);\r
+\r
+/*!\r
+ * @brief Gets head element handle.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_GetHead(list_handle_t list);\r
+\r
+/*!\r
+ * @brief Gets next element handle for given element handle.\r
+ *\r
+ * @param element - Handle of the element.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_GetNext(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Gets previous element handle for given element handle.\r
+ *\r
+ * @param element - Handle of the element.\r
+ *\r
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.\r
+ */\r
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Unlinks an element from its list.\r
+ *\r
+ * @param element - Handle of the element.\r
+ *\r
+ * @retval kLIST_OrphanElement if element is not part of any list.\r
+ * @retval kLIST_Ok if removal was successful.\r
+ */\r
+list_status_t LIST_RemoveElement(list_element_handle_t element);\r
+\r
+/*!\r
+ * @brief Links an element in the previous position relative to a given member of a list.\r
+ *\r
+ * @param element - Handle of the element.\r
+ * @param newElement - New element to insert before the given member.\r
+ *\r
+ * @retval kLIST_OrphanElement if element is not part of any list.\r
+ * @retval kLIST_Ok if removal was successful.\r
+ */\r
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);\r
+\r
+/*!\r
+ * @brief Gets the current size of a list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval Current size of the list.\r
+ */\r
+uint32_t LIST_GetSize(list_handle_t list);\r
+\r
+/*!\r
+ * @brief Gets the number of free places in the list.\r
+ *\r
+ * @param list - Handle of the list.\r
+ *\r
+ * @retval Available size of the list.\r
+ */\r
+uint32_t LIST_GetAvailableSize(list_handle_t list);\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+#endif /*_GENERIC_LIST_H_*/\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include <string.h>\r
+\r
+#include "serial_manager.h"\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#include "generic_list.h"\r
+\r
+/*\r
+ * The OSA_USED macro can only be defined when the OSA component is used.\r
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.\r
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED\r
+ * also cannot be defined.\r
+ * The source code path of the OSA component is <MCUXpresso_SDK>/components/osa.\r
+ *\r
+ */\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#include "common_task.h"\r
+#else\r
+#include "fsl_os_abstraction.h"\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#define SERIAL_EVENT_DATA_RECEIVED (1U << 0)\r
+#define SERIAL_EVENT_DATA_SENT (1U << 1)\r
+\r
+#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U\r
+#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+typedef enum _serial_manager_transmission_mode\r
+{\r
+ kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/\r
+ kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/\r
+} serial_manager_transmission_mode_t;\r
+\r
+/* TX transfer structure */\r
+typedef struct _serial_manager_transfer\r
+{\r
+ uint8_t *buffer;\r
+ volatile uint32_t length;\r
+ volatile uint32_t soFar;\r
+ serial_manager_transmission_mode_t mode;\r
+ serial_manager_status_t status;\r
+} serial_manager_transfer_t;\r
+#endif\r
+\r
+/* write handle structure */\r
+typedef struct _serial_manager_send_handle\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ list_element_t link; /*!< list element of the link */\r
+ serial_manager_transfer_t transfer;\r
+#endif\r
+ struct _serial_manager_handle *serialManagerHandle;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serial_manager_callback_t callback;\r
+ void *callbackParam;\r
+ uint32_t tag;\r
+#endif\r
+} serial_manager_write_handle_t;\r
+\r
+typedef serial_manager_write_handle_t serial_manager_read_handle_t;\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+/* receive state structure */\r
+typedef struct _serial_manager_read_ring_buffer\r
+{\r
+ uint8_t *ringBuffer;\r
+ uint32_t ringBufferSize;\r
+ volatile uint32_t ringHead;\r
+ volatile uint32_t ringTail;\r
+} serial_manager_read_ring_buffer_t;\r
+#endif\r
+\r
+#if defined(__CC_ARM)\r
+#pragma anon_unions\r
+#endif\r
+/* The serial manager handle structure */\r
+typedef struct _serial_manager_handle\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ list_t runningWriteHandleHead; /*!< The queue of running write handle */\r
+ list_t completedWriteHandleHead; /*!< The queue of completed write handle */\r
+#endif\r
+ serial_manager_read_handle_t *openedReadHandleHead;\r
+ uint32_t openedWriteHandleCount;\r
+ union\r
+ {\r
+ uint8_t lowLevelhandleBuffer[1];\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE];\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE];\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE];\r
+#endif\r
+ };\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serial_manager_read_ring_buffer_t ringBuffer;\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ common_task_message_t commontaskMsg;\r
+#else\r
+ uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */\r
+ uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+ serial_port_type_t type;\r
+} serial_manager_handle_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *config);\r
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#endif\r
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_UartIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);\r
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);\r
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);\r
+#endif\r
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);\r
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_Task(void *param);\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+\r
+#else\r
+ /*\r
+ * \brief Defines the serial manager task's stack\r
+ */\r
+OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false);\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_AddTail(list_t *queue, serial_manager_write_handle_t *node)\r
+{\r
+ LIST_AddTail(queue, &node->link);\r
+}\r
+\r
+static void SerialManager_RemoveHead(list_t *queue)\r
+{\r
+ LIST_RemoveHead(queue);\r
+}\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+ serial_manager_write_handle_t *writeHandle =\r
+ (serial_manager_write_handle_t *)LIST_GetHead(&handle->runningWriteHandleHead);\r
+\r
+ if (writeHandle)\r
+ {\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ writeHandle->transfer.buffer, writeHandle->transfer.length);\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+#else\r
+\r
+static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle,\r
+ serial_manager_write_handle_t *writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ if (writeHandle)\r
+ {\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle,\r
+ serial_manager_read_handle_t *readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ if (readHandle)\r
+ {\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length);\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_IsrFunction(serial_manager_handle_t *handle)\r
+{\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ EnableGlobalIRQ(regPrimask);\r
+}\r
+\r
+static void SerialManager_Task(void *param)\r
+{\r
+ serial_manager_handle_t *handle = (serial_manager_handle_t *)param;\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_callback_message_t msg;\r
+ if (NULL != handle)\r
+ {\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ osa_event_flags_t ev = 0;\r
+\r
+ do\r
+ {\r
+ if (KOSA_StatusSuccess ==\r
+ OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev))\r
+ {\r
+ if (ev & SERIAL_EVENT_DATA_SENT)\r
+#endif\r
+\r
+#endif\r
+ {\r
+ serialWriteHandle = (serial_manager_write_handle_t *)LIST_GetHead(&handle->completedWriteHandleHead);\r
+ while (NULL != serialWriteHandle)\r
+ {\r
+ SerialManager_RemoveHead(&handle->completedWriteHandleHead);\r
+ msg.buffer = serialWriteHandle->transfer.buffer;\r
+ msg.length = serialWriteHandle->transfer.soFar;\r
+ serialWriteHandle->transfer.buffer = NULL;\r
+ if (serialWriteHandle->callback)\r
+ {\r
+ serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg,\r
+ serialWriteHandle->transfer.status);\r
+ }\r
+ serialWriteHandle = (serial_manager_write_handle_t *)LIST_GetHead(&handle->completedWriteHandleHead);\r
+ }\r
+ }\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ if (ev & SERIAL_EVENT_DATA_RECEIVED)\r
+#endif\r
+\r
+#endif\r
+ {\r
+ serialReadHandle = handle->openedReadHandleHead;\r
+ if ((serialReadHandle) && (serialReadHandle->transfer.buffer) &&\r
+ (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length))\r
+ {\r
+ msg.buffer = serialReadHandle->transfer.buffer;\r
+ msg.length = serialReadHandle->transfer.soFar;\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ if (serialReadHandle->callback)\r
+ {\r
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg,\r
+ serialReadHandle->transfer.status);\r
+ }\r
+ }\r
+ }\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ }\r
+ } while (gUseRtos_c);\r
+#endif\r
+\r
+#endif\r
+ }\r
+}\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+static void SerialManager_TxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_write_handle_t *writeHandle;\r
+\r
+ assert(callbackParam);\r
+ assert(message);\r
+\r
+ handle = (serial_manager_handle_t *)callbackParam;\r
+\r
+ writeHandle = (serial_manager_write_handle_t *)LIST_GetHead(&handle->runningWriteHandleHead);\r
+\r
+ if (NULL != writeHandle)\r
+ {\r
+ SerialManager_RemoveHead(&handle->runningWriteHandleHead);\r
+ SerialManager_StartWriting(handle);\r
+ writeHandle->transfer.soFar = message->length;\r
+ writeHandle->transfer.status = status;\r
+ if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode)\r
+ {\r
+ SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle);\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ handle->commontaskMsg.callback = SerialManager_Task;\r
+ handle->commontaskMsg.callbackParam = handle;\r
+ COMMON_TASK_post_message(&handle->commontaskMsg);\r
+#else\r
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT);\r
+#endif\r
+\r
+#else\r
+ SerialManager_Task(handle);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ writeHandle->transfer.buffer = NULL;\r
+ }\r
+ }\r
+}\r
+\r
+static void SerialManager_RxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ uint32_t ringBufferLength;\r
+\r
+ assert(callbackParam);\r
+ assert(message);\r
+\r
+ handle = (serial_manager_handle_t *)callbackParam;\r
+\r
+ status = kStatus_SerialManager_Notify;\r
+\r
+ for (int i = 0; i < message->length; i++)\r
+ {\r
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i];\r
+ if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringHead = 0U;\r
+ }\r
+ if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail)\r
+ {\r
+ status = kStatus_SerialManager_RingBufferOverflow;\r
+ handle->ringBuffer.ringTail++;\r
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringTail = 0U;\r
+ }\r
+ }\r
+ }\r
+\r
+ ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;\r
+ ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;\r
+\r
+ if ((handle->openedReadHandleHead) && (handle->openedReadHandleHead->transfer.buffer))\r
+ {\r
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)\r
+ {\r
+ int remainLength =\r
+ handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar;\r
+ for (int i = 0; i < MIN(ringBufferLength, remainLength); i++)\r
+ {\r
+ handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] =\r
+ handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];\r
+ handle->ringBuffer.ringTail++;\r
+ handle->openedReadHandleHead->transfer.soFar++;\r
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringTail = 0U;\r
+ }\r
+ }\r
+ ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength);\r
+ }\r
+\r
+ if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar)\r
+ {\r
+ }\r
+ else\r
+ {\r
+ if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode)\r
+ {\r
+ handle->openedReadHandleHead->transfer.buffer = NULL;\r
+ }\r
+ else\r
+ {\r
+ handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success;\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ handle->commontaskMsg.callback = SerialManager_Task;\r
+ handle->commontaskMsg.callbackParam = handle;\r
+ COMMON_TASK_post_message(&handle->commontaskMsg);\r
+#else\r
+ (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED);\r
+#endif\r
+\r
+#else\r
+ SerialManager_Task(handle);\r
+#endif\r
+ }\r
+ }\r
+ }\r
+\r
+ if (ringBufferLength)\r
+ {\r
+ message->buffer = NULL;\r
+ message->length = ringBufferLength;\r
+ if ((NULL != handle->openedReadHandleHead->callback))\r
+ {\r
+ handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status);\r
+ }\r
+ }\r
+}\r
+\r
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ serial_manager_transmission_mode_t mode)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_status_t status = kStatus_SerialManager_Success;\r
+ uint32_t primask;\r
+ uint8_t isEmpty = 0U;\r
+\r
+ assert(writeHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+ handle = serialWriteHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback)));\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (serialWriteHandle->transfer.buffer)\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ serialWriteHandle->transfer.buffer = buffer;\r
+ serialWriteHandle->transfer.length = length;\r
+ serialWriteHandle->transfer.soFar = 0U;\r
+ serialWriteHandle->transfer.mode = mode;\r
+\r
+ if (NULL == LIST_GetHead(&handle->runningWriteHandleHead))\r
+ {\r
+ isEmpty = 1U;\r
+ }\r
+ SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle);\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (isEmpty)\r
+ {\r
+ status = SerialManager_StartWriting(handle);\r
+ if (kStatus_SerialManager_Success != status)\r
+ {\r
+ return status;\r
+ }\r
+ }\r
+\r
+ if (kSerialManager_TransmissionBlocking == mode)\r
+ {\r
+ while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar)\r
+ {\r
+#if defined(__GIC_PRIO_BITS)\r
+ if ((__get_CPSR() & CPSR_M_Msk) == 0x13)\r
+#else\r
+ if (__get_IPSR())\r
+#endif\r
+ {\r
+ SerialManager_IsrFunction(handle);\r
+ }\r
+ }\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ serial_manager_transmission_mode_t mode,\r
+ uint32_t *receivedLength)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_handle_t *handle;\r
+ uint32_t dataLength;\r
+ uint32_t primask;\r
+\r
+ assert(readHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+ handle = serialReadHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+ assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback)));\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (serialReadHandle->transfer.buffer)\r
+ {\r
+ EnableGlobalIRQ(primask);\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ serialReadHandle->transfer.buffer = buffer;\r
+ serialReadHandle->transfer.length = length;\r
+ serialReadHandle->transfer.soFar = 0U;\r
+ serialReadHandle->transfer.mode = mode;\r
+\r
+ dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;\r
+ dataLength = dataLength % handle->ringBuffer.ringBufferSize;\r
+\r
+ for (; serialReadHandle->transfer.soFar < MIN(dataLength, length); serialReadHandle->transfer.soFar++)\r
+ {\r
+ buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail];\r
+ handle->ringBuffer.ringTail++;\r
+ if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize)\r
+ {\r
+ handle->ringBuffer.ringTail = 0U;\r
+ }\r
+ }\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (receivedLength)\r
+ {\r
+ *receivedLength = serialReadHandle->transfer.soFar;\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ }\r
+ else\r
+ {\r
+ if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length)\r
+ {\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ if (kSerialManager_TransmissionNonBlocking == mode)\r
+ {\r
+ if (serialReadHandle->callback)\r
+ {\r
+ serial_manager_callback_message_t msg;\r
+ msg.buffer = buffer;\r
+ msg.length = serialReadHandle->transfer.soFar;\r
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success);\r
+ }\r
+ }\r
+ }\r
+\r
+ if (kSerialManager_TransmissionBlocking == mode)\r
+ {\r
+ while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar)\r
+ {\r
+ }\r
+ }\r
+ }\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#else\r
+\r
+static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ serial_manager_handle_t *handle;\r
+\r
+ assert(writeHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+ handle = serialWriteHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+\r
+ return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length);\r
+}\r
+\r
+static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_handle_t *handle;\r
+\r
+ assert(readHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+ handle = serialReadHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+\r
+ return SerialManager_StartReading(handle, serialReadHandle, buffer, length);\r
+}\r
+#endif\r
+\r
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_status_t status = kStatus_SerialManager_Error;\r
+\r
+ assert(config);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ assert(config->ringBuffer);\r
+ assert(config->ringBufferSize);\r
+#endif\r
+ assert(serialHandle);\r
+ if (SERIAL_MANAGER_HANDLE_SIZE < sizeof(serial_manager_handle_t))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+\r
+ memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE);\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+\r
+ COMMON_TASK_init();\r
+\r
+#else\r
+ if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+ handle->type = config->type;\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ handle->ringBuffer.ringBuffer = config->ringBuffer;\r
+ handle->ringBuffer.ringBufferSize = config->ringBufferSize;\r
+#endif\r
+\r
+ switch (config->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_RxCallback, handle);\r
+ }\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_RxCallback, handle);\r
+ }\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]),\r
+ SerialManager_TxCallback, handle);\r
+ }\r
+#endif\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+\r
+ assert(serialHandle);\r
+\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+\r
+ if ((handle->openedReadHandleHead) || (handle->openedWriteHandleCount))\r
+ {\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+\r
+ switch (handle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+#else\r
+ OSA_EventDestroy((osa_event_handle_t)handle->event);\r
+ OSA_TaskDestroy((osa_task_handle_t)handle->taskId);\r
+#endif\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+\r
+ assert(serialHandle);\r
+ assert(writeHandle);\r
+ if (SERIAL_MANAGER_WRITE_HANDLE_SIZE < sizeof(serial_manager_write_handle_t))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+\r
+ memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);\r
+\r
+ handle->openedWriteHandleCount++;\r
+\r
+ serialWriteHandle->serialManagerHandle = handle;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG;\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+\r
+ assert(writeHandle);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+ handle = (serial_manager_handle_t *)serialWriteHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ SerialManager_CancelWriting(writeHandle);\r
+#endif\r
+\r
+ handle->openedWriteHandleCount--;\r
+ memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+\r
+ assert(serialHandle);\r
+ assert(readHandle);\r
+ if (SERIAL_MANAGER_READ_HANDLE_SIZE < sizeof(serial_manager_read_handle_t))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+ handle = (serial_manager_handle_t *)serialHandle;\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+\r
+ if (handle->openedReadHandleHead)\r
+ {\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);\r
+\r
+ handle->openedReadHandleHead = serialReadHandle;\r
+\r
+ serialReadHandle->serialManagerHandle = handle;\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serialReadHandle->tag = SERIAL_MANAGER_READ_TAG;\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle)\r
+{\r
+ serial_manager_handle_t *handle;\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+\r
+ assert(readHandle);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+ handle = (serial_manager_handle_t *)serialReadHandle->serialManagerHandle;\r
+\r
+ assert(handle);\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ SerialManager_CancelReading(readHandle);\r
+#endif\r
+\r
+ handle->openedReadHandleHead = NULL;\r
+ memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking);\r
+#else\r
+ return SerialManager_Write(writeHandle, buffer, length);\r
+#endif\r
+}\r
+\r
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL);\r
+#else\r
+ return SerialManager_Read(readHandle, buffer, length);\r
+#endif\r
+}\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length)\r
+{\r
+ return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking);\r
+}\r
+\r
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL);\r
+}\r
+\r
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+ uint32_t primask;\r
+ uint8_t isNotUsed = 0;\r
+\r
+ assert(writeHandle);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+\r
+ assert(serialWriteHandle->serialManagerHandle);\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+\r
+ if ((serialWriteHandle->transfer.buffer) &&\r
+ (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ primask = DisableGlobalIRQ();\r
+ if (serialWriteHandle !=\r
+ (serial_manager_write_handle_t *)LIST_GetHead(&serialWriteHandle->serialManagerHandle->runningWriteHandleHead))\r
+ {\r
+ LIST_RemoveElement(&serialWriteHandle->link);\r
+ isNotUsed = 1;\r
+ }\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (isNotUsed)\r
+ {\r
+ serialWriteHandle->transfer.soFar = 0;\r
+ serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled;\r
+\r
+ SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle);\r
+#if defined(OSA_USED)\r
+\r
+#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U))\r
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task;\r
+ serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle;\r
+ COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg);\r
+#else\r
+ (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT);\r
+#endif\r
+\r
+#else\r
+ SerialManager_Task(serialWriteHandle->serialManagerHandle);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ switch (serialWriteHandle->serialManagerHandle->type)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ case kSerialPort_Uart:\r
+ Serial_UartCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ case kSerialPort_UsbCdc:\r
+ Serial_UsbCdcCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ case kSerialPort_Swo:\r
+ Serial_SwoCancelWrite(\r
+ ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0]));\r
+ break;\r
+#endif\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+\r
+ SerialManager_StartWriting(serialWriteHandle->serialManagerHandle);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+ serial_manager_callback_message_t msg;\r
+ uint8_t *buffer;\r
+ uint32_t primask;\r
+\r
+ assert(readHandle);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+\r
+ if ((serialReadHandle->transfer.buffer) && (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ primask = DisableGlobalIRQ();\r
+ buffer = serialReadHandle->transfer.buffer;\r
+ serialReadHandle->transfer.buffer = NULL;\r
+ serialReadHandle->transfer.length = 0;\r
+ msg.buffer = buffer;\r
+ msg.length = serialReadHandle->transfer.soFar;\r
+ EnableGlobalIRQ(primask);\r
+\r
+ if (buffer)\r
+ {\r
+ if (serialReadHandle->callback)\r
+ {\r
+ serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled);\r
+ }\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ uint32_t *receivedLength)\r
+{\r
+ assert(receivedLength);\r
+\r
+ return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength);\r
+}\r
+\r
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_manager_write_handle_t *serialWriteHandle;\r
+\r
+ assert(writeHandle);\r
+\r
+ serialWriteHandle = (serial_manager_write_handle_t *)writeHandle;\r
+\r
+ assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag);\r
+\r
+ serialWriteHandle->callbackParam = callbackParam;\r
+ serialWriteHandle->callback = callback;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_manager_read_handle_t *serialReadHandle;\r
+\r
+ assert(readHandle);\r
+\r
+ serialReadHandle = (serial_manager_read_handle_t *)readHandle;\r
+\r
+ assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag);\r
+\r
+ serialReadHandle->callbackParam = callbackParam;\r
+ serialReadHandle->callback = callback;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+#endif\r
+\r
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle)\r
+{\r
+ assert(serialHandle);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle)\r
+{\r
+ assert(serialHandle);\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __SERIAL_MANAGER_H__\r
+#define __SERIAL_MANAGER_H__\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#define SERIAL_MANAGER_NON_BLOCKING_MODE \\r
+ (1U) /* Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */\r
+#else\r
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE\r
+#define SERIAL_MANAGER_NON_BLOCKING_MODE \\r
+ (0U) /* Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */\r
+#endif\r
+#endif\r
+\r
+#ifndef SERIAL_PORT_TYPE_UART\r
+#define SERIAL_PORT_TYPE_UART (1U) /* Enable or disable uart port (1 - enable, 0 - disable) */\r
+#endif\r
+\r
+#ifndef SERIAL_PORT_TYPE_USBCDC\r
+#define SERIAL_PORT_TYPE_USBCDC (0U) /* Enable or disable USB CDC port (1 - enable, 0 - disable) */\r
+#endif\r
+\r
+#ifndef SERIAL_PORT_TYPE_SWO\r
+#define SERIAL_PORT_TYPE_SWO (0U) /* Enable or disable SWO port (1 - enable, 0 - disable) */\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)\r
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)\r
+#else\r
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)\r
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+#include "serial_port_uart.h"\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+\r
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#error The serial manager blocking mode cannot be supported for USB CDC.\r
+#endif\r
+\r
+#include "serial_port_usb.h"\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+#include "serial_port_swo.h"\r
+#endif\r
+\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+\r
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+\r
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+\r
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)\r
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP\r
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE\r
+#endif\r
+\r
+#endif\r
+\r
+/* SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */\r
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))\r
+#else\r
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC and SERIAL_PORT_TYPE_SWO should not be cleared at same time.\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)\r
+#else\r
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)\r
+#endif\r
+\r
+#define SERIAL_MANAGER_USE_COMMON_TASK (1U)\r
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)\r
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)\r
+\r
+typedef void *serial_handle_t;\r
+typedef void *serial_write_handle_t;\r
+typedef void *serial_read_handle_t;\r
+\r
+typedef enum _serial_port_type\r
+{\r
+ kSerialPort_Uart = 1U, /*!< Serial port UART */\r
+ kSerialPort_UsbCdc, /*!< Serial port USB CDC */\r
+ kSerialPort_Swo, /*!< Serial port SWO */\r
+} serial_port_type_t;\r
+\r
+typedef struct _serial_manager_config\r
+{\r
+ uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware.\r
+ Besides, the memory space cannot be free during the lifetime of the serial\r
+ manager module. */\r
+ uint32_t ringBufferSize; /*!< The size of the ring buffer */\r
+ serial_port_type_t type; /*!< Serial port type */\r
+ void *portConfig; /*!< Serial port configuration */\r
+} serial_manager_config_t;\r
+\r
+typedef enum _serial_manager_status\r
+{\r
+ kStatus_SerialManager_Success = kStatus_Success, /*!< Success */\r
+ kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */\r
+ kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */\r
+ kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */\r
+ kStatus_SerialManager_Canceled =\r
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */\r
+ kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */\r
+ kStatus_SerialManager_RingBufferOverflow =\r
+ MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */\r
+} serial_manager_status_t;\r
+\r
+/*! @brief Callback message structure */\r
+typedef struct _serial_manager_callback_message\r
+{\r
+ uint8_t *buffer; /*!< Transferred buffer */\r
+ uint32_t length; /*!< Transferred data length */\r
+} serial_manager_callback_message_t;\r
+\r
+/*! @brief callback function */\r
+typedef void (*serial_manager_callback_t)(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status);\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+/*!\r
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.\r
+ *\r
+ * This function configures the serial manager module with user-defined settings. The user can configure the\r
+ * configuration\r
+ * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE\r
+ * allocated by the caller.\r
+ * The serial manager module supports two types serial port, uart (includes UART, USART, LPSCI, LPUART, etc) and USB\r
+ * CDC.\r
+ * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using\r
+ * #serial_manager_config_t.\r
+ *\r
+ * Example below shows how to use this API to configure the serial manager.\r
+ * For UART,\r
+ * @code\r
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)\r
+ * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];\r
+ * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];\r
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];\r
+ *\r
+ * serial_manager_config_t config;\r
+ * serial_port_uart_config_t uartConfig;\r
+ * config.type = kSerialPort_Uart;\r
+ * config.ringBuffer = &s_ringBuffer[0];\r
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;\r
+ * uartConfig.instance = 0;\r
+ * uartConfig.clockRate = 24000000;\r
+ * uartConfig.baudRate = 115200;\r
+ * uartConfig.parityMode = kSerialManager_UartParityDisabled;\r
+ * uartConfig.stopBitCount = kSerialManager_UartOneStopBit;\r
+ * uartConfig.enableRx = 1;\r
+ * uartConfig.enableTx = 1;\r
+ * config.portConfig = &uartConfig;\r
+ * SerialManager_Init(s_serialHandle, &config);\r
+ * @endcode\r
+ * For USB CDC,\r
+ * @code\r
+ * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U)\r
+ * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];\r
+ * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0];\r
+ * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];\r
+ *\r
+ * serial_manager_config_t config;\r
+ * serial_port_usb_cdc_config_t usbCdcConfig;\r
+ * config.type = kSerialPort_UsbCdc;\r
+ * config.ringBuffer = &s_ringBuffer[0];\r
+ * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;\r
+ * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;\r
+ * config.portConfig = &usbCdcConfig;\r
+ * SerialManager_Init(s_serialHandle, &config);\r
+ * @endcode\r
+ *\r
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.\r
+ * @param config Pointer to user-defined configuration structure.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ * @retval kStatus_SerialManager_Success The serial manager module initialization succeed.\r
+ */\r
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);\r
+\r
+/*!\r
+ * @brief De-initializes the serial manager module instance.\r
+ *\r
+ * This function de-initializes the serial manager module instance. If the opened writing or\r
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.\r
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.\r
+ */\r
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);\r
+\r
+/*!\r
+ * @brief Opens a writing handle for the serial manager module.\r
+ *\r
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to\r
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling\r
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing\r
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission\r
+ * is needed for a task.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @param writeHandle The serial manager module writing handle pointer.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.\r
+ * @retval kStatus_SerialManager_Success The writing handle is opened.\r
+ *\r
+ * Example below shows how to use this API to write data.\r
+ * For task 1,\r
+ * @code\r
+ * static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE];\r
+ * static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0];\r
+ * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n";\r
+ * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);\r
+ * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);\r
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);\r
+ * @endcode\r
+ * For task 2,\r
+ * @code\r
+ * static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE];\r
+ * static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0];\r
+ * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n";\r
+ * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);\r
+ * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);\r
+ * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);\r
+ * @endcode\r
+ */\r
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);\r
+\r
+/*!\r
+ * @brief Closes a writing handle for the serial manager module.\r
+ *\r
+ * This function Closes a writing handle for the serial manager module.\r
+ *\r
+ * @param writeHandle The serial manager module writing handle pointer.\r
+ * @retval kStatus_SerialManager_Success The writing handle is closed.\r
+ */\r
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);\r
+\r
+/*!\r
+ * @brief Opens a reading handle for the serial manager module.\r
+ *\r
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be\r
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when\r
+ * the previous reading handle is not closed. And There can only one buffer for receiving for the\r
+ * reading handle at the same time.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @param readHandle The serial manager module reading handle pointer.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ * @retval kStatus_SerialManager_Success The reading handle is opened.\r
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.\r
+ *\r
+ * Example below shows how to use this API to read data.\r
+ * @code\r
+ * static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];\r
+ * static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0];\r
+ * SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);\r
+ * static uint8_t s_nonBlockingBuffer[64];\r
+ * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);\r
+ * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));\r
+ * @endcode\r
+ */\r
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);\r
+\r
+/*!\r
+ * @brief Closes a reading for the serial manager module.\r
+ *\r
+ * This function Closes a reading for the serial manager module.\r
+ *\r
+ * @param readHandle The serial manager module reading handle pointer.\r
+ * @retval kStatus_SerialManager_Success The reading handle is closed.\r
+ */\r
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);\r
+\r
+/*!\r
+ * @brief Transmits data with the blocking mode.\r
+ *\r
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.\r
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for transmission for the writing handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to write.\r
+ * @param length Length of the data to write.\r
+ * @retval kStatus_SerialManager_Success Successfully sent all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length);\r
+\r
+/*!\r
+ * @brief Reads data with the blocking mode.\r
+ *\r
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.\r
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for receiving for the reading handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to store the received data.\r
+ * @param length The length of the data to be received.\r
+ * @retval kStatus_SerialManager_Success Successfully received all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+/*!\r
+ * @brief Transmits data with the non-blocking mode.\r
+ *\r
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.\r
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes\r
+ * the status parameter @ref kStatus_SerialManager_Success.\r
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for transmission for the writing handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking\r
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to write.\r
+ * @param length Length of the data to write.\r
+ * @retval kStatus_SerialManager_Success Successfully sent all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length);\r
+\r
+/*!\r
+ * @brief Reads data with the non-blocking mode.\r
+ *\r
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.\r
+ * When all data is received, the module driver notifies the upper layer\r
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.\r
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.\r
+ * And There can only one buffer for receiving for the reading handle at the same time.\r
+ *\r
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking\r
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to store the received data.\r
+ * @param length The length of the data to be received.\r
+ * @retval kStatus_SerialManager_Success Successfully received all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length);\r
+\r
+/*!\r
+ * @brief Tries to read data.\r
+ *\r
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be\r
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.\r
+ * After the data is copied, the actual data length is passed by the parameter length.\r
+ * And There can only one buffer for receiving for the reading handle at the same time.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param buffer Start address of the data to store the received data.\r
+ * @param length The length of the data to be received.\r
+ * @param receivedLength Length received from the ring buffer directly.\r
+ * @retval kStatus_SerialManager_Success Successfully received all data.\r
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,\r
+ uint8_t *buffer,\r
+ uint32_t length,\r
+ uint32_t *receivedLength);\r
+\r
+/*!\r
+ * @brief Cancels unfinished send transmission.\r
+ *\r
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer\r
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.\r
+ *\r
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of\r
+ * the function #SerialManager_WriteBlocking.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);\r
+\r
+/*!\r
+ * @brief Cancels unfinished receive transmission.\r
+ *\r
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper\r
+ * layer\r
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.\r
+ *\r
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of\r
+ * the function #SerialManager_ReadBlocking.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.\r
+ * @retval kStatus_SerialManager_Error An error occurred.\r
+ */\r
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);\r
+\r
+/*!\r
+ * @brief Installs a TX callback and callback parameter.\r
+ *\r
+ * This function is used to install the TX callback and callback parameter for the serial manager module.\r
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param writeHandle The serial manager module handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_SerialManager_Success Successfully install the callback.\r
+ */\r
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+\r
+/*!\r
+ * @brief Installs a RX callback and callback parameter.\r
+ *\r
+ * This function is used to install the RX callback and callback parameter for the serial manager module.\r
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param readHandle The serial manager module handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_SerialManager_Success Successfully install the callback.\r
+ */\r
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam);\r
+\r
+#endif\r
+\r
+/*!\r
+ * @brief Prepares to enter low power consumption.\r
+ *\r
+ * This function is used to prepare to enter low power consumption.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Successful operation.\r
+ */\r
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);\r
+\r
+/*!\r
+ * @brief Restores from low power consumption.\r
+ *\r
+ * This function is used to restore from low power consumption.\r
+ *\r
+ * @param serialHandle The serial manager module handle pointer.\r
+ * @retval kStatus_SerialManager_Success Successful operation.\r
+ */\r
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+#endif /* __SERIAL_MANAGER_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "serial_manager.h"\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+#include "uart.h"\r
+\r
+#include "serial_port_uart.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U\r
+\r
+typedef struct _serial_uart_send_state\r
+{\r
+ serial_manager_callback_t callback;\r
+ void *callbackParam;\r
+ uint8_t *buffer;\r
+ uint32_t length;\r
+ volatile uint8_t busy;\r
+} serial_uart_send_state_t;\r
+\r
+typedef struct _serial_uart_recv_state\r
+{\r
+ serial_manager_callback_t callback;\r
+ void *callbackParam;\r
+ volatile uint8_t busy;\r
+ uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];\r
+} serial_uart_recv_state_t;\r
+#endif\r
+\r
+typedef struct _serial_uart_state\r
+{\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serial_uart_send_state_t tx;\r
+ serial_uart_recv_state_t rx;\r
+#endif\r
+ uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];\r
+} serial_uart_state_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+/* UART user callback */\r
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+ serial_manager_callback_message_t msg;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ hal_uart_transfer_t transfer;\r
+#endif\r
+\r
+ if (NULL == userData)\r
+ {\r
+ return;\r
+ }\r
+\r
+ serialUartHandle = (serial_uart_state_t *)userData;\r
+\r
+ if (kStatus_HAL_UartRxIdle == status)\r
+ {\r
+ if ((NULL != serialUartHandle->rx.callback))\r
+ {\r
+ msg.buffer = &serialUartHandle->rx.readBuffer[0];\r
+ msg.length = sizeof(serialUartHandle->rx.readBuffer);\r
+ serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);\r
+ }\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ transfer.data = &serialUartHandle->rx.readBuffer[0];\r
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);\r
+ if (kStatus_HAL_UartSuccess ==\r
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))\r
+#else\r
+ if (kStatus_HAL_UartSuccess ==\r
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))\r
+#endif\r
+ {\r
+ serialUartHandle->rx.busy = 1U;\r
+ }\r
+ else\r
+ {\r
+ serialUartHandle->rx.busy = 0U;\r
+ }\r
+ }\r
+ else if (kStatus_HAL_UartTxIdle == status)\r
+ {\r
+ if (serialUartHandle->tx.busy)\r
+ {\r
+ serialUartHandle->tx.busy = 0U;\r
+ if ((NULL != serialUartHandle->tx.callback))\r
+ {\r
+ msg.buffer = serialUartHandle->tx.buffer;\r
+ msg.length = serialUartHandle->tx.length;\r
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ }\r
+}\r
+#endif\r
+\r
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+ serial_port_uart_config_t *uartConfig;\r
+ hal_uart_config_t config;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ hal_uart_transfer_t transfer;\r
+#endif\r
+\r
+ assert(serialConfig);\r
+ assert(serialHandle);\r
+ if (SERIAL_PORT_UART_HANDLE_SIZE < sizeof(serial_uart_state_t))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ uartConfig = (serial_port_uart_config_t *)serialConfig;\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ config.baudRate_Bps = uartConfig->baudRate;\r
+ config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode;\r
+ config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;\r
+ config.enableRx = uartConfig->enableRx;\r
+ config.enableTx = uartConfig->enableTx;\r
+ config.srcClock_Hz = uartConfig->clockRate;\r
+ config.instance = uartConfig->instance;\r
+\r
+ if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ Serial_UartCallback, serialUartHandle))\r
+#else\r
+ if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ Serial_UartCallback, serialUartHandle))\r
+#endif\r
+ {\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+\r
+ if (uartConfig->enableRx)\r
+ {\r
+ serialUartHandle->rx.busy = 1U;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ transfer.data = &serialUartHandle->rx.readBuffer[0];\r
+ transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))\r
+#else\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))\r
+#endif\r
+ {\r
+ serialUartHandle->rx.busy = 0U;\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+ }\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#else\r
+ HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#endif\r
+#endif\r
+ HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+ serialUartHandle->tx.busy = 0U;\r
+ serialUartHandle->rx.busy = 0U;\r
+#endif\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+\r
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ hal_uart_transfer_t transfer;\r
+#endif\r
+\r
+ assert(serialHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ if (serialUartHandle->tx.busy)\r
+ {\r
+ return kStatus_SerialManager_Busy;\r
+ }\r
+ serialUartHandle->tx.busy = 1U;\r
+\r
+ serialUartHandle->tx.buffer = buffer;\r
+ serialUartHandle->tx.length = length;\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ transfer.data = buffer;\r
+ transfer.dataSize = length;\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))\r
+#else\r
+ if (kStatus_HAL_UartSuccess !=\r
+ HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))\r
+#endif\r
+ {\r
+ serialUartHandle->tx.busy = 0U;\r
+ return kStatus_SerialManager_Error;\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+#else\r
+\r
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),\r
+ buffer, length);\r
+}\r
+\r
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+ assert(buffer);\r
+ assert(length);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ return (serial_manager_status_t)HAL_UartReceiveBlocking(\r
+ ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);\r
+}\r
+\r
+#endif\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+ serial_manager_callback_message_t msg;\r
+ uint32_t primask;\r
+ uint8_t isBusy = 0U;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ primask = DisableGlobalIRQ();\r
+ isBusy = serialUartHandle->tx.busy;\r
+ serialUartHandle->tx.busy = 0U;\r
+ EnableGlobalIRQ(primask);\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#else\r
+ HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+#endif\r
+ if (isBusy)\r
+ {\r
+ if ((NULL != serialUartHandle->tx.callback))\r
+ {\r
+ msg.buffer = serialUartHandle->tx.buffer;\r
+ msg.length = serialUartHandle->tx.length;\r
+ serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);\r
+ }\r
+ }\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ serialUartHandle->tx.callback = callback;\r
+ serialUartHandle->tx.callbackParam = callbackParam;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,\r
+ serial_manager_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ serialUartHandle->rx.callback = callback;\r
+ serialUartHandle->rx.callbackParam = callbackParam;\r
+\r
+ return kStatus_SerialManager_Success;\r
+}\r
+\r
+void Serial_UartIsrFunction(serial_handle_t serialHandle)\r
+{\r
+ serial_uart_state_t *serialUartHandle;\r
+\r
+ assert(serialHandle);\r
+\r
+ serialUartHandle = (serial_uart_state_t *)serialHandle;\r
+\r
+ HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));\r
+}\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __SERIAL_PORT_UART_H__\r
+#define __SERIAL_PORT_UART_H__\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))\r
+#define SERIAL_PORT_UART_HANDLE_SIZE (166U)\r
+#else\r
+#define SERIAL_PORT_UART_HANDLE_SIZE (4U)\r
+#endif\r
+\r
+typedef enum _serial_port_uart_parity_mode\r
+{\r
+ kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */\r
+ kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */\r
+ kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */\r
+} serial_port_uart_parity_mode_t;\r
+\r
+typedef enum _serial_port_uart_stop_bit_count\r
+{\r
+ kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */\r
+ kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */\r
+} serial_port_uart_stop_bit_count_t;\r
+\r
+typedef struct _serial_port_uart_config\r
+{\r
+ uint32_t clockRate; /*!< clock rate */\r
+ uint32_t baudRate; /*!< baud rate */\r
+ serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */\r
+ serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */\r
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information\r
+ please refer to the SOC corresponding RM. */\r
+ uint8_t enableRx; /*!< Enable RX */\r
+ uint8_t enableTx; /*!< Enable TX */\r
+} serial_port_uart_config_t;\r
+\r
+#endif /* __SERIAL_PORT_UART_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef __HAL_UART_ADAPTER_H__\r
+#define __HAL_UART_ADAPTER_H__\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#define UART_ADAPTER_NON_BLOCKING_MODE \\r
+ (1U) /* Enable or disable Uart adapter non-blocking mode (1 - enable, 0 - disable) */\r
+#else\r
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE\r
+#define UART_ADAPTER_NON_BLOCKING_MODE \\r
+ (0U) /* Enable or disable Uart adapter non-blocking mode (1 - enable, 0 - disable) */\r
+#else\r
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE\r
+#endif\r
+#endif\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+#define HAL_UART_HANDLE_SIZE (90U)\r
+#else\r
+#define HAL_UART_HANDLE_SIZE (4U)\r
+#endif\r
+\r
+#define HAL_UART_TRANSFER_MODE \\r
+ (0U) /*!< Whether enable transactional function of the uart. (0 - disable, 1 - enable) \ \\r
+ */\r
+\r
+typedef void *hal_uart_handle_t;\r
+\r
+/*! @brief uart status */\r
+typedef enum _hal_uart_status\r
+{\r
+ kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */\r
+ kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */\r
+ kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */\r
+ kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL uart transmitter is idle. */\r
+ kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL uart receiver is idle */\r
+ kStatus_HAL_UartBaudrateNotSupport =\r
+ MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */\r
+ kStatus_HAL_UartProtocolError = MAKE_STATUS(\r
+ kStatusGroup_HAL_UART,\r
+ 6), /*!< Error occurs for Noise, Framing, Parity, etc.\r
+ For transcational transfer, The up layer needs to abort the transfer and then starts again */\r
+ kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL uart */\r
+} hal_uart_status_t;\r
+\r
+/*! @brief uart parity mode. */\r
+typedef enum _hal_uart_parity_mode\r
+{\r
+ kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */\r
+ kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */\r
+ kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */\r
+} hal_uart_parity_mode_t;\r
+\r
+/*! @brief uart stop bit count. */\r
+typedef enum _hal_uart_stop_bit_count\r
+{\r
+ kHAL_UartOneStopBit = 0U, /*!< One stop bit */\r
+ kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */\r
+} hal_uart_stop_bit_count_t;\r
+\r
+/*! @brief uart configuration structure. */\r
+typedef struct _hal_uart_config\r
+{\r
+ uint32_t srcClock_Hz; /*!< Source clock */\r
+ uint32_t baudRate_Bps; /*!< Baud rate */\r
+ hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */\r
+ hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */\r
+ uint8_t enableRx; /*!< Enable RX */\r
+ uint8_t enableTx; /*!< Enable TX */\r
+ uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the\r
+ SOC corresponding RM.\r
+ Invalid instance value will cause initialization failure. */\r
+} hal_uart_config_t;\r
+\r
+/*! @brief uart transfer callback function. */\r
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);\r
+\r
+/*! @brief uart transfer structure. */\r
+typedef struct _hal_uart_transfer\r
+{\r
+ uint8_t *data; /*!< The buffer of data to be transfer.*/\r
+ size_t dataSize; /*!< The byte count to be transfer. */\r
+} hal_uart_transfer_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+/*!\r
+ * @name Initialization and deinitialization\r
+ * @{\r
+ */\r
+\r
+/*!\r
+* @brief Initializes a uart instance with the uart handle and the user configuration structure.\r
+*\r
+* This function configures the uart module with user-defined settings. The user can configure the configuration\r
+* structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the\r
+* caller.\r
+* Example below shows how to use this API to configure the uart.\r
+* @code\r
+* uint8_t g_UartHandleBuffer[HAL_UART_HANDLE_SIZE];\r
+* hal_uart_handle_t g_UartHandle = &g_UartHandleBuffer[0];\r
+* hal_uart_config_t config;\r
+* config.srcClock_Hz = 48000000;\r
+* config.baudRate_Bps = 115200U;\r
+* config.parityMode = kHAL_UartParityDisabled;\r
+* config.stopBitCount = kHAL_UartOneStopBit;\r
+* config.enableRx = 1;\r
+* config.enableTx = 1;\r
+* config.instance = 0;\r
+* HAL_UartInit(g_UartHandle, &config);\r
+* @endcode\r
+*\r
+* @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.\r
+* @param config Pointer to user-defined configuration structure.\r
+* @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.\r
+* @retval kStatus_HAL_UartSuccess uart initialization succeed\r
+*/\r
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);\r
+\r
+/*!\r
+ * @brief Deinitializes a uart instance.\r
+ *\r
+ * This function waits for TX complete, disables TX and RX, and disables the uart clock.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @retval kStatus_HAL_UartSuccess uart de-initialization succeed\r
+ */\r
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Blocking bus Operations\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Reads RX data register using a blocking method.\r
+ *\r
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to\r
+ * have data, and reads data from the RX register.\r
+ *\r
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param data Start address of the buffer to store the received data.\r
+ * @param length Size of the buffer.\r
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.\r
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.\r
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.\r
+ */\r
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Writes to the TX register using a blocking method.\r
+ *\r
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO\r
+ * to have room and writes data to the TX buffer.\r
+ *\r
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking\r
+ * cannot be used at the same time.\r
+ * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.\r
+ */\r
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);\r
+\r
+/* @} */\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+\r
+/*!\r
+ * @name Transactional\r
+ * @note The transactional API and the functional API cannot be used at the same time. The macro\r
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the\r
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Installs a callback and callback parameter.\r
+ *\r
+ * This function is used to install the callback and callback parameter for uart module.\r
+ * When any status of the uart changed, the driver will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.\r
+ */\r
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam);\r
+\r
+/*!\r
+ * @brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be received.\r
+ * The receive request is saved by the uart driver.\r
+ * When the new data arrives, the receive request is serviced first.\r
+ * When all data is received, the uart driver notifies the upper layer\r
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.\r
+ *\r
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param transfer uart transfer structure, see #hal_uart_transfer_t.\r
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.\r
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);\r
+\r
+/*!\r
+ * @brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the ISR, the uart driver calls the callback\r
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.\r
+ *\r
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param transfer uart transfer structure. See #hal_uart_transfer_t.\r
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.\r
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param count Receive bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes written to the uart TX register.\r
+ *\r
+ * This function gets the number of bytes written to the uart TX\r
+ * register by using the interrupt method.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param count Send bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know\r
+ * how many bytes are not received yet.\r
+ *\r
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of\r
+ * the function #HAL_UartReceiveBlocking.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the receiving.\r
+ */\r
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data sending.\r
+ *\r
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out\r
+ * how many bytes are not sent out.\r
+ *\r
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of\r
+ * the function #HAL_UartSendBlocking.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the sending.\r
+ */\r
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);\r
+\r
+/* @} */\r
+\r
+#else\r
+\r
+/*!\r
+ * @name Functional API with non-blocking mode.\r
+ * @note The functional API and the transactional API cannot be used at the same time. The macro\r
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the\r
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Installs a callback and callback parameter.\r
+ *\r
+ * This function is used to install the callback and callback parameter for uart module.\r
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback\r
+ * function. And the status is also passed as status parameter when the callback is called.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param callback The callback function.\r
+ * @param callbackParam The parameter of the callback function.\r
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.\r
+ */\r
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam);\r
+\r
+/*!\r
+ * @brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be received.\r
+ * The receive request is saved by the uart adapter.\r
+ * When the new data arrives, the receive request is serviced first.\r
+ * When all data is received, the uart adapter notifies the upper layer\r
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.\r
+ *\r
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.\r
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the ISR, the uart driver calls the callback\r
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.\r
+ *\r
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking\r
+ * cannot be used at the same time.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.\r
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ */\r
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param count Receive bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Gets the number of bytes written to the uart TX register.\r
+ *\r
+ * This function gets the number of bytes written to the uart TX\r
+ * register by using the interrupt method.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @param count Send bytes count.\r
+ * @retval kStatus_HAL_UartError An error occurred.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count.\r
+ */\r
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know\r
+ * how many bytes are not received yet.\r
+ *\r
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of\r
+ * the function #HAL_UartReceiveBlocking.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the receiving.\r
+ */\r
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data sending.\r
+ *\r
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out\r
+ * how many bytes are not sent out.\r
+ *\r
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of\r
+ * the function #HAL_UartSendBlocking.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ * @retval kStatus_Success Get successfully abort the sending.\r
+ */\r
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);\r
+\r
+/* @} */\r
+\r
+#endif\r
+\r
+/*!\r
+ * @brief uart IRQ handle function.\r
+ *\r
+ * This function handles the uart transmit and receive IRQ request.\r
+ *\r
+ * @param handle uart handle pointer.\r
+ */\r
+void HAL_UartIsrFunction(hal_uart_handle_t handle);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+#endif /* __HAL_UART_ADAPTER_H__ */\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_usart.h"\r
+#include "fsl_flexcomm.h"\r
+\r
+#include "uart.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+/*! @brief uart RX state structure. */\r
+typedef struct _hal_uart_receive_state\r
+{\r
+ volatile uint8_t *buffer;\r
+ volatile uint32_t bufferLength;\r
+ volatile uint32_t bufferSofar;\r
+} hal_uart_receive_state_t;\r
+\r
+/*! @brief uart TX state structure. */\r
+typedef struct _hal_uart_send_state\r
+{\r
+ volatile uint8_t *buffer;\r
+ volatile uint32_t bufferLength;\r
+ volatile uint32_t bufferSofar;\r
+} hal_uart_send_state_t;\r
+#endif\r
+/*! @brief uart state structure. */\r
+typedef struct _hal_uart_state\r
+{\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+ hal_uart_transfer_callback_t callback;\r
+ void *callbackParam;\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ usart_handle_t hardwareHandle;\r
+#endif\r
+ hal_uart_receive_state_t rx;\r
+ hal_uart_send_state_t tx;\r
+#endif\r
+ uint8_t instance;\r
+} hal_uart_state_t;\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+/* Array of USART IRQ number. */\r
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;\r
+\r
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+#endif\r
+\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+static hal_uart_status_t HAL_UartGetStatus(status_t status)\r
+{\r
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;\r
+ switch (status)\r
+ {\r
+ case kStatus_Success:\r
+ uartStatus = kStatus_HAL_UartSuccess;\r
+ break;\r
+ case kStatus_USART_TxBusy:\r
+ uartStatus = kStatus_HAL_UartTxBusy;\r
+ break;\r
+ case kStatus_USART_RxBusy:\r
+ uartStatus = kStatus_HAL_UartRxBusy;\r
+ break;\r
+ case kStatus_USART_TxIdle:\r
+ uartStatus = kStatus_HAL_UartTxIdle;\r
+ break;\r
+ case kStatus_USART_RxIdle:\r
+ uartStatus = kStatus_HAL_UartRxIdle;\r
+ break;\r
+ case kStatus_USART_BaudrateNotSupport:\r
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;\r
+ break;\r
+ case kStatus_USART_NoiseError:\r
+ case kStatus_USART_FramingError:\r
+ case kStatus_USART_ParityError:\r
+ uartStatus = kStatus_HAL_UartProtocolError;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ return uartStatus;\r
+}\r
+#else\r
+static hal_uart_status_t HAL_UartGetStatus(status_t status)\r
+{\r
+ if (kStatus_Success == status)\r
+ {\r
+ return kStatus_HAL_UartSuccess;\r
+ }\r
+ else\r
+ {\r
+ return kStatus_HAL_UartError;\r
+ }\r
+}\r
+#endif\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);\r
+ assert(callbackParam);\r
+\r
+ uartHandle = (hal_uart_state_t *)callbackParam;\r
+\r
+ if (kStatus_HAL_UartProtocolError == uartStatus)\r
+ {\r
+ if (uartHandle->hardwareHandle.rxDataSize)\r
+ {\r
+ uartStatus = kStatus_HAL_UartError;\r
+ }\r
+ }\r
+\r
+ if (uartHandle->callback)\r
+ {\r
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);\r
+ }\r
+}\r
+\r
+#else\r
+\r
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)\r
+{\r
+ hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;\r
+ uint32_t status;\r
+ uint8_t instance;\r
+\r
+ if (NULL == uartHandle)\r
+ {\r
+ return;\r
+ }\r
+ instance = uartHandle->instance;\r
+\r
+ status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);\r
+\r
+ /* Receive data register full */\r
+ if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&\r
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))\r
+ {\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);\r
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[instance],\r
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);\r
+ if (uartHandle->callback)\r
+ {\r
+ uartHandle->rx.buffer = NULL;\r
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Send data register empty and the interrupt is enabled. */\r
+ if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&\r
+ (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))\r
+ {\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);\r
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);\r
+ if (uartHandle->callback)\r
+ {\r
+ uartHandle->tx.buffer = NULL;\r
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#if 1\r
+ USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);\r
+#endif\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ usart_config_t usartConfig;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(config);\r
+ assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));\r
+ assert(s_UsartAdapterBase[config->instance]);\r
+\r
+ if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))\r
+ {\r
+ return kStatus_HAL_UartError;\r
+ }\r
+\r
+ USART_GetDefaultConfig(&usartConfig);\r
+ usartConfig.baudRate_Bps = config->baudRate_Bps;\r
+\r
+ if (kHAL_UartParityEven == config->parityMode)\r
+ {\r
+ usartConfig.parityMode = kUSART_ParityEven;\r
+ }\r
+ else if (kHAL_UartParityOdd == config->parityMode)\r
+ {\r
+ usartConfig.parityMode = kUSART_ParityOdd;\r
+ }\r
+ else\r
+ {\r
+ usartConfig.parityMode = kUSART_ParityDisabled;\r
+ }\r
+\r
+ if (kHAL_UartTwoStopBit == config->stopBitCount)\r
+ {\r
+ usartConfig.stopBitCount = kUSART_TwoStopBit;\r
+ }\r
+ else\r
+ {\r
+ usartConfig.stopBitCount = kUSART_OneStopBit;\r
+ }\r
+ usartConfig.enableRx = config->enableRx;\r
+ usartConfig.enableTx = config->enableTx;\r
+ usartConfig.txWatermark = kUSART_TxFifo0;\r
+ usartConfig.rxWatermark = kUSART_RxFifo1;\r
+\r
+ status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);\r
+\r
+ if (kStatus_Success != status)\r
+ {\r
+ return HAL_UartGetStatus(status);\r
+ }\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+ uartHandle->instance = config->instance;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+ USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,\r
+ (usart_transfer_callback_t)HAL_UartCallback, handle);\r
+#else\r
+ /* Enable interrupt in NVIC. */\r
+ FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,\r
+ handle);\r
+ EnableIRQ(s_UsartIRQ[config->instance]);\r
+#endif\r
+\r
+#endif\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+\r
+ assert(handle);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ return kStatus_HAL_UartRxBusy;\r
+ }\r
+#endif\r
+\r
+ status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ return kStatus_HAL_UartTxBusy;\r
+ }\r
+#endif\r
+\r
+ USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+\r
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ uartHandle->callbackParam = callbackParam;\r
+ uartHandle->callback = callback;\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(transfer);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,\r
+ (usart_transfer_t *)transfer, NULL);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(transfer);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,\r
+ (usart_transfer_t *)transfer);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(count);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status =\r
+ USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ status_t status;\r
+ assert(handle);\r
+ assert(count);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);\r
+\r
+ return HAL_UartGetStatus(status);\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+#else\r
+\r
+/* None transactional API with non-blocking mode. */\r
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,\r
+ hal_uart_transfer_callback_t callback,\r
+ void *callbackParam)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ uartHandle->callbackParam = callbackParam;\r
+ uartHandle->callback = callback;\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ return kStatus_HAL_UartRxBusy;\r
+ }\r
+\r
+ uartHandle->rx.bufferLength = length;\r
+ uartHandle->rx.bufferSofar = 0;\r
+ uartHandle->rx.buffer = data;\r
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(data);\r
+ assert(length);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ return kStatus_HAL_UartTxBusy;\r
+ }\r
+ uartHandle->tx.bufferLength = length;\r
+ uartHandle->tx.bufferSofar = 0;\r
+ uartHandle->tx.buffer = (volatile uint8_t *)data;\r
+ USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(count);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ *count = uartHandle->rx.bufferSofar;\r
+ return kStatus_HAL_UartSuccess;\r
+ }\r
+ return kStatus_HAL_UartError;\r
+}\r
+\r
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *count)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(count);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ *count = uartHandle->tx.bufferSofar;\r
+ return kStatus_HAL_UartSuccess;\r
+ }\r
+ return kStatus_HAL_UartError;\r
+}\r
+\r
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->rx.buffer)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],\r
+ USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);\r
+ uartHandle->rx.buffer = NULL;\r
+ }\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+ if (uartHandle->tx.buffer)\r
+ {\r
+ USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);\r
+ uartHandle->tx.buffer = NULL;\r
+ }\r
+\r
+ return kStatus_HAL_UartSuccess;\r
+}\r
+\r
+#endif\r
+\r
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))\r
+\r
+void HAL_UartIsrFunction(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if 0\r
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+ USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);\r
+#if 0\r
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+}\r
+\r
+#else\r
+\r
+void HAL_UartIsrFunction(hal_uart_handle_t handle)\r
+{\r
+ hal_uart_state_t *uartHandle;\r
+ assert(handle);\r
+ assert(!HAL_UART_TRANSFER_MODE);\r
+\r
+ uartHandle = (hal_uart_state_t *)handle;\r
+\r
+#if 0\r
+ DisableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+ HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);\r
+#if 0\r
+ EnableIRQ(s_UsartIRQ[uartHandle->instance]);\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Processors: LPC55S69JBD100_cm33_core0\r
+** LPC55S69JET98_cm33_core0\r
+**\r
+** Compilers: GNU C Compiler\r
+** IAR ANSI C/C++ Compiler for ARM\r
+** Keil ARM C/C++ Compiler\r
+** MCUXpresso Compiler\r
+**\r
+** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018\r
+** Version: rev. 1.0, 2018-08-22\r
+** Build: b190122\r
+**\r
+** Abstract:\r
+** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0\r
+**\r
+** Copyright 1997-2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2018-08-22)\r
+** Initial version based on v0.2UM\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+/*!\r
+ * @file LPC55S69_cm33_core0.h\r
+ * @version 1.0\r
+ * @date 2018-08-22\r
+ * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0\r
+ *\r
+ * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0\r
+ */\r
+\r
+#ifndef _LPC55S69_CM33_CORE0_H_\r
+#define _LPC55S69_CM33_CORE0_H_ /**< Symbol preventing repeated inclusion */\r
+\r
+/** Memory map major version (memory maps with equal major version number are\r
+ * compatible) */\r
+#define MCU_MEM_MAP_VERSION 0x0100U\r
+/** Memory map minor version */\r
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Interrupt vector numbers\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers\r
+ * @{\r
+ */\r
+\r
+/** Interrupt Number Definitions */\r
+#define NUMBER_OF_INT_VECTORS 76 /**< Number of interrupts in the Vector table */\r
+\r
+typedef enum IRQn {\r
+ /* Auxiliary constants */\r
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */\r
+\r
+ /* Core interrupts */\r
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */\r
+ SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */\r
+ SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */\r
+\r
+ /* Device specific interrupts */\r
+ WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect, Flash interrupt */\r
+ DMA0_IRQn = 1, /**< DMA0 controller */\r
+ GINT0_IRQn = 2, /**< GPIO group 0 */\r
+ GINT1_IRQn = 3, /**< GPIO group 1 */\r
+ PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */\r
+ PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */\r
+ PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */\r
+ PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */\r
+ UTICK0_IRQn = 8, /**< Micro-tick Timer */\r
+ MRT0_IRQn = 9, /**< Multi-rate timer */\r
+ CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */\r
+ CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */\r
+ SCT0_IRQn = 12, /**< SCTimer/PWM */\r
+ CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */\r
+ FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */\r
+ ADC0_IRQn = 22, /**< ADC0 */\r
+ Reserved39_IRQn = 23, /**< Reserved interrupt */\r
+ ACMP_IRQn = 24, /**< ACMP interrupts */\r
+ Reserved41_IRQn = 25, /**< Reserved interrupt */\r
+ Reserved42_IRQn = 26, /**< Reserved interrupt */\r
+ USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */\r
+ USB0_IRQn = 28, /**< USB device */\r
+ RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */\r
+ Reserved46_IRQn = 30, /**< Reserved interrupt */\r
+ MAILBOX_IRQn = 31, /**< WAKEUP,Mailbox interrupt (present on selected devices) */\r
+ PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */\r
+ PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */\r
+ PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */\r
+ PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */\r
+ CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */\r
+ CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */\r
+ OS_EVENT_IRQn = 38, /**< OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */\r
+ Reserved55_IRQn = 39, /**< Reserved interrupt */\r
+ Reserved56_IRQn = 40, /**< Reserved interrupt */\r
+ Reserved57_IRQn = 41, /**< Reserved interrupt */\r
+ SDIO_IRQn = 42, /**< SD/MMC */\r
+ Reserved59_IRQn = 43, /**< Reserved interrupt */\r
+ Reserved60_IRQn = 44, /**< Reserved interrupt */\r
+ Reserved61_IRQn = 45, /**< Reserved interrupt */\r
+ USB1_UTMI_IRQn = 46, /**< USB1_UTMI */\r
+ USB1_IRQn = 47, /**< USB1 interrupt */\r
+ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */\r
+ SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */\r
+ SEC_GPIO_INT0_IRQ0_IRQn = 50, /**< SEC_GPIO_INT0_IRQ0 interrupt */\r
+ SEC_GPIO_INT0_IRQ1_IRQn = 51, /**< SEC_GPIO_INT0_IRQ1 interrupt */\r
+ PLU_IRQn = 52, /**< PLU interrupt */\r
+ SEC_VIO_IRQn = 53, /**< SEC_VIO interrupt */\r
+ HASHCRYPT_IRQn = 54, /**< HASHCRYPT interrupt */\r
+ CASER_IRQn = 55, /**< CASPER interrupt */\r
+ PUF_IRQn = 56, /**< PUF interrupt */\r
+ PQ_IRQn = 57, /**< PQ interrupt */\r
+ DMA1_IRQn = 58, /**< DMA1 interrupt */\r
+ LSPI_HS_IRQn = 59 /**< Flexcomm Interface 8 (SPI, , FLEXCOMM) */\r
+} IRQn_Type;\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Interrupt_vector_numbers */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Cortex M33 Core Configuration\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration\r
+ * @{\r
+ */\r
+\r
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */\r
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */\r
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */\r
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */\r
+#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */\r
+#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */\r
+\r
+#include "core_cm33.h" /* Core Peripheral Access Layer */\r
+#include "system_LPC55S69_cm33_core0.h" /* Device specific configuration file */\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Cortex_Core_Configuration */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Mapping Information\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Mapping_Information Mapping Information\r
+ * @{\r
+ */\r
+\r
+/** Mapping Information */\r
+/*!\r
+ * @addtogroup dma_request\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*!\r
+ * @brief Structure for the DMA hardware request\r
+ *\r
+ * Defines the structure for the DMA hardware request collections. The user can configure the\r
+ * hardware request to trigger the DMA transfer accordingly. The index\r
+ * of the hardware request varies according to the to SoC.\r
+ */\r
+typedef enum _dma_request_source\r
+{\r
+ kDma0RequestHashCrypt = 0U, /**< HashCrypt */\r
+ kDma1RequestHashCryptInput = 0U, /**< HashCrypt Input */\r
+ kDma0RequestNoDMARequest1 = 1U, /**< No DMA request 1 */\r
+ kDma1RequestNoDMARequest1 = 1U, /**< No DMA request 1 */\r
+ kDma0RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */\r
+ kDma1RequestFlexcomm8Rx = 2U, /**< Flexcomm Interface 8 RX */\r
+ kDma0RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */\r
+ kDma1RequestFlexcomm8Tx = 3U, /**< Flexcomm Interface 8 TX */\r
+ kDma0RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */\r
+ kDma1RequestFlexcomm0Rx = 4U, /**< Flexcomm Interface 0 RX/I2C Slave */\r
+ kDma0RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */\r
+ kDma1RequestFlexcomm0Tx = 5U, /**< Flexcomm Interface 0 TX/I2C Master */\r
+ kDma0RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */\r
+ kDma1RequestFlexcomm1Rx = 6U, /**< Flexcomm Interface 1 RX/I2C Slave */\r
+ kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */\r
+ kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */\r
+ kDma0RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */\r
+ kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */\r
+ kDma0RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */\r
+ kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */\r
+ kDma0RequestFlexcomm3Rx = 10U, /**< Flexcomm Interface 3 RX/I2C Slave */\r
+ kDma0RequestFlexcomm3Tx = 11U, /**< Flexcomm Interface 3 TX/I2C Master */\r
+ kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */\r
+ kDma0RequestFlexcomm4Tx = 13U, /**< Flexcomm Interface 4 TX/I2C Master */\r
+ kDma0RequestFlexcomm5Rx = 14U, /**< Flexcomm Interface 5 RX/I2C Slave */\r
+ kDma0RequestFlexcomm5Tx = 15U, /**< Flexcomm Interface 5 TX/I2C Master */\r
+ kDma0RequestFlexcomm6Rx = 16U, /**< Flexcomm Interface 6 RX/I2C Slave */\r
+ kDma0RequestFlexcomm6Tx = 17U, /**< Flexcomm Interface 6 TX/I2C Master */\r
+ kDma0RequestFlexcomm7Rx = 18U, /**< Flexcomm Interface 7 RX/I2C Slave */\r
+ kDma0RequestFlexcomm7Tx = 19U, /**< Flexcomm Interface 7 TX/I2C Master */\r
+ kDma0RequestNoDMARequest20 = 20U, /**< No DMA request 20 */\r
+ kDma0RequestADC0FIFO0 = 21U, /**< ADC0 FIFO 0 */\r
+ kDma0RequestADC0FIFO1 = 22U, /**< ADC0 FIFO 1 */\r
+} dma_request_source_t;\r
+\r
+/* @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Mapping_Information */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Device Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+\r
+/*\r
+** Start of section using anonymous unions\r
+*/\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #if (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang diagnostic push\r
+ #else\r
+ #pragma push\r
+ #pragma anon_unions\r
+ #endif\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+ #pragma language=extended\r
+#else\r
+ #error Not supported compiler type\r
+#endif\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ADC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** ADC - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */\r
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */\r
+ uint8_t RESERVED_0[8];\r
+ __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */\r
+ __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */\r
+ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */\r
+ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */\r
+ __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */\r
+ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */\r
+ uint8_t RESERVED_1[12];\r
+ __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */\r
+ __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */\r
+ uint8_t RESERVED_3[92];\r
+ __IO uint32_t TCTRL[16]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */\r
+ __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */\r
+ uint8_t RESERVED_4[8];\r
+ __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */\r
+ __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */\r
+ struct { /* offset: 0x100, array step: 0x8 */\r
+ __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */\r
+ __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */\r
+ } CMD[15];\r
+ uint8_t RESERVED_5[136];\r
+ __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */\r
+ uint8_t RESERVED_6[240];\r
+ __I uint32_t RESFIFO[2]; /**< ADC Data Result FIFO Register, array offset: 0x300, array step: 0x4 */\r
+ uint8_t RESERVED_7[248];\r
+ __IO uint32_t CAL_GAR[33]; /**< Calibration General A-Side Registers, array offset: 0x400, array step: 0x4 */\r
+ uint8_t RESERVED_8[124];\r
+ __IO uint32_t CAL_GBR[33]; /**< Calibration General B-Side Registers, array offset: 0x500, array step: 0x4 */\r
+ uint8_t RESERVED_9[2680];\r
+ __IO uint32_t TST; /**< ADC Test Register, offset: 0xFFC */\r
+} ADC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ADC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ADC_Register_Masks ADC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name VERID - Version ID Register */\r
+/*! @{ */\r
+#define ADC_VERID_RES_MASK (0x1U)\r
+#define ADC_VERID_RES_SHIFT (0U)\r
+/*! RES - Resolution\r
+ * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.\r
+ * 0b1..Up to 16-bit differential/16-bit single ended resolution supported.\r
+ */\r
+#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)\r
+#define ADC_VERID_DIFFEN_MASK (0x2U)\r
+#define ADC_VERID_DIFFEN_SHIFT (1U)\r
+/*! DIFFEN - Differential Supported\r
+ * 0b0..Differential operation not supported.\r
+ * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented.\r
+ */\r
+#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)\r
+#define ADC_VERID_MVI_MASK (0x8U)\r
+#define ADC_VERID_MVI_SHIFT (3U)\r
+/*! MVI - Multi Vref Implemented\r
+ * 0b0..Single voltage reference high (VREFH) input supported.\r
+ * 0b1..Multiple voltage reference high (VREFH) inputs supported.\r
+ */\r
+#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)\r
+#define ADC_VERID_CSW_MASK (0x70U)\r
+#define ADC_VERID_CSW_SHIFT (4U)\r
+/*! CSW - Channel Scale Width\r
+ * 0b000..Channel scaling not supported.\r
+ * 0b001..Channel scaling supported. 1-bit CSCALE control field.\r
+ * 0b110..Channel scaling supported. 6-bit CSCALE control field.\r
+ */\r
+#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)\r
+#define ADC_VERID_VR1RNGI_MASK (0x100U)\r
+#define ADC_VERID_VR1RNGI_SHIFT (8U)\r
+/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented\r
+ * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.\r
+ * 0b1..Range control required. CFG[VREF1RNG] is implemented.\r
+ */\r
+#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)\r
+#define ADC_VERID_IADCKI_MASK (0x200U)\r
+#define ADC_VERID_IADCKI_SHIFT (9U)\r
+/*! IADCKI - Internal ADC Clock implemented\r
+ * 0b0..Internal clock source not implemented.\r
+ * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.\r
+ */\r
+#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)\r
+#define ADC_VERID_CALOFSI_MASK (0x400U)\r
+#define ADC_VERID_CALOFSI_SHIFT (10U)\r
+/*! CALOFSI - Calibration Function Implemented\r
+ * 0b0..Calibration Not Implemented.\r
+ * 0b1..Calibration Implemented.\r
+ */\r
+#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)\r
+#define ADC_VERID_NUM_SEC_MASK (0x800U)\r
+#define ADC_VERID_NUM_SEC_SHIFT (11U)\r
+/*! NUM_SEC - Number of Single Ended Outputs Supported\r
+ * 0b0..This design supports one single ended conversion at a time.\r
+ * 0b1..This design supports two simultanious single ended conversions.\r
+ */\r
+#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK)\r
+#define ADC_VERID_NUM_FIFO_MASK (0x7000U)\r
+#define ADC_VERID_NUM_FIFO_SHIFT (12U)\r
+/*! NUM_FIFO - Number of FIFOs\r
+ * 0b000..N/A\r
+ * 0b001..This design supports one result FIFO.\r
+ * 0b010..This design supports two result FIFOs.\r
+ * 0b011..This design supports three result FIFOs.\r
+ * 0b100..This design supports four result FIFOs.\r
+ */\r
+#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK)\r
+#define ADC_VERID_MINOR_MASK (0xFF0000U)\r
+#define ADC_VERID_MINOR_SHIFT (16U)\r
+#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)\r
+#define ADC_VERID_MAJOR_MASK (0xFF000000U)\r
+#define ADC_VERID_MAJOR_SHIFT (24U)\r
+#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name PARAM - Parameter Register */\r
+/*! @{ */\r
+#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)\r
+#define ADC_PARAM_TRIG_NUM_SHIFT (0U)\r
+#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)\r
+#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)\r
+#define ADC_PARAM_FIFOSIZE_SHIFT (8U)\r
+/*! FIFOSIZE - Result FIFO Depth\r
+ * 0b00000001..Result FIFO depth = 1 dataword.\r
+ * 0b00000100..Result FIFO depth = 4 datawords.\r
+ * 0b00001000..Result FIFO depth = 8 datawords.\r
+ * 0b00010000..Result FIFO depth = 16 datawords.\r
+ * 0b00100000..Result FIFO depth = 32 datawords.\r
+ * 0b01000000..Result FIFO depth = 64 datawords.\r
+ */\r
+#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)\r
+#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)\r
+#define ADC_PARAM_CV_NUM_SHIFT (16U)\r
+#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)\r
+#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)\r
+#define ADC_PARAM_CMD_NUM_SHIFT (24U)\r
+#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL - ADC Control Register */\r
+/*! @{ */\r
+#define ADC_CTRL_ADCEN_MASK (0x1U)\r
+#define ADC_CTRL_ADCEN_SHIFT (0U)\r
+/*! ADCEN - ADC Enable\r
+ * 0b0..ADC is disabled.\r
+ * 0b1..ADC is enabled.\r
+ */\r
+#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)\r
+#define ADC_CTRL_RST_MASK (0x2U)\r
+#define ADC_CTRL_RST_SHIFT (1U)\r
+/*! RST - Software Reset\r
+ * 0b0..ADC logic is not reset.\r
+ * 0b1..ADC logic is reset.\r
+ */\r
+#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)\r
+#define ADC_CTRL_DOZEN_MASK (0x4U)\r
+#define ADC_CTRL_DOZEN_SHIFT (2U)\r
+/*! DOZEN - Doze Enable\r
+ * 0b0..ADC is enabled in Doze mode.\r
+ * 0b1..ADC is disabled in Doze mode.\r
+ */\r
+#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)\r
+#define ADC_CTRL_CAL_REQ_MASK (0x8U)\r
+#define ADC_CTRL_CAL_REQ_SHIFT (3U)\r
+/*! CAL_REQ - Auto-Calibration Request\r
+ * 0b0..No request for auto-calibration has been made.\r
+ * 0b1..A request for auto-calibration has been made\r
+ */\r
+#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK)\r
+#define ADC_CTRL_CALOFS_MASK (0x10U)\r
+#define ADC_CTRL_CALOFS_SHIFT (4U)\r
+/*! CALOFS - Configure for offset calibration function\r
+ * 0b0..Calibration function disabled\r
+ * 0b1..Request for offset calibration function\r
+ */\r
+#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK)\r
+#define ADC_CTRL_RSTFIFO0_MASK (0x100U)\r
+#define ADC_CTRL_RSTFIFO0_SHIFT (8U)\r
+/*! RSTFIFO0 - Reset FIFO 0\r
+ * 0b0..No effect.\r
+ * 0b1..FIFO 0 is reset.\r
+ */\r
+#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK)\r
+#define ADC_CTRL_RSTFIFO1_MASK (0x200U)\r
+#define ADC_CTRL_RSTFIFO1_SHIFT (9U)\r
+/*! RSTFIFO1 - Reset FIFO 1\r
+ * 0b0..No effect.\r
+ * 0b1..FIFO 1 is reset.\r
+ */\r
+#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK)\r
+#define ADC_CTRL_CAL_AVGS_MASK (0x70000U)\r
+#define ADC_CTRL_CAL_AVGS_SHIFT (16U)\r
+/*! CAL_AVGS - Auto-Calibration Averages\r
+ * 0b000..Single conversion.\r
+ * 0b001..2 conversions averaged.\r
+ * 0b010..4 conversions averaged.\r
+ * 0b011..8 conversions averaged.\r
+ * 0b100..16 conversions averaged.\r
+ * 0b101..32 conversions averaged.\r
+ * 0b110..64 conversions averaged.\r
+ * 0b111..128 conversions averaged.\r
+ */\r
+#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - ADC Status Register */\r
+/*! @{ */\r
+#define ADC_STAT_RDY0_MASK (0x1U)\r
+#define ADC_STAT_RDY0_SHIFT (0U)\r
+/*! RDY0 - Result FIFO 0 Ready Flag\r
+ * 0b0..Result FIFO 0 data level not above watermark level.\r
+ * 0b1..Result FIFO 0 holding data above watermark level.\r
+ */\r
+#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK)\r
+#define ADC_STAT_FOF0_MASK (0x2U)\r
+#define ADC_STAT_FOF0_SHIFT (1U)\r
+/*! FOF0 - Result FIFO 0 Overflow Flag\r
+ * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared.\r
+ * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.\r
+ */\r
+#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK)\r
+#define ADC_STAT_RDY1_MASK (0x4U)\r
+#define ADC_STAT_RDY1_SHIFT (2U)\r
+/*! RDY1 - Result FIFO1 Ready Flag\r
+ * 0b0..Result FIFO1 data level not above watermark level.\r
+ * 0b1..Result FIFO1 holding data above watermark level.\r
+ */\r
+#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK)\r
+#define ADC_STAT_FOF1_MASK (0x8U)\r
+#define ADC_STAT_FOF1_SHIFT (3U)\r
+/*! FOF1 - Result FIFO1 Overflow Flag\r
+ * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.\r
+ * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.\r
+ */\r
+#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK)\r
+#define ADC_STAT_TEXC_INT_MASK (0x100U)\r
+#define ADC_STAT_TEXC_INT_SHIFT (8U)\r
+/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception\r
+ * 0b0..No trigger exceptions have occurred.\r
+ * 0b1..A trigger exception has occurred and is pending acknowledgement.\r
+ */\r
+#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK)\r
+#define ADC_STAT_TCOMP_INT_MASK (0x200U)\r
+#define ADC_STAT_TCOMP_INT_SHIFT (9U)\r
+/*! TCOMP_INT - Interrupt Flag For Trigger Completion\r
+ * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion.\r
+ * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO.\r
+ */\r
+#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK)\r
+#define ADC_STAT_CAL_RDY_MASK (0x400U)\r
+#define ADC_STAT_CAL_RDY_SHIFT (10U)\r
+/*! CAL_RDY - Calibration Ready\r
+ * 0b0..Calibration is incomplete or hasn't been ran.\r
+ * 0b1..The ADC is calibrated.\r
+ */\r
+#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK)\r
+#define ADC_STAT_ADC_ACTIVE_MASK (0x800U)\r
+#define ADC_STAT_ADC_ACTIVE_SHIFT (11U)\r
+/*! ADC_ACTIVE - ADC Active\r
+ * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.\r
+ * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.\r
+ */\r
+#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)\r
+#define ADC_STAT_TRGACT_MASK (0xF0000U)\r
+#define ADC_STAT_TRGACT_SHIFT (16U)\r
+/*! TRGACT - Trigger Active\r
+ * 0b0000..Command (sequence) associated with Trigger 0 currently being executed.\r
+ * 0b0001..Command (sequence) associated with Trigger 1 currently being executed.\r
+ * 0b0010..Command (sequence) associated with Trigger 2 currently being executed.\r
+ * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed.\r
+ */\r
+#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)\r
+#define ADC_STAT_CMDACT_MASK (0xF000000U)\r
+#define ADC_STAT_CMDACT_SHIFT (24U)\r
+/*! CMDACT - Command Active\r
+ * 0b0000..No command is currently in progress.\r
+ * 0b0001..Command 1 currently being executed.\r
+ * 0b0010..Command 2 currently being executed.\r
+ * 0b0011-0b1111..Associated command number is currently being executed.\r
+ */\r
+#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)\r
+/*! @} */\r
+\r
+/*! @name IE - Interrupt Enable Register */\r
+/*! @{ */\r
+#define ADC_IE_FWMIE0_MASK (0x1U)\r
+#define ADC_IE_FWMIE0_SHIFT (0U)\r
+/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable\r
+ * 0b0..FIFO 0 watermark interrupts are not enabled.\r
+ * 0b1..FIFO 0 watermark interrupts are enabled.\r
+ */\r
+#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK)\r
+#define ADC_IE_FOFIE0_MASK (0x2U)\r
+#define ADC_IE_FOFIE0_SHIFT (1U)\r
+/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable\r
+ * 0b0..FIFO 0 overflow interrupts are not enabled.\r
+ * 0b1..FIFO 0 overflow interrupts are enabled.\r
+ */\r
+#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK)\r
+#define ADC_IE_FWMIE1_MASK (0x4U)\r
+#define ADC_IE_FWMIE1_SHIFT (2U)\r
+/*! FWMIE1 - FIFO1 Watermark Interrupt Enable\r
+ * 0b0..FIFO1 watermark interrupts are not enabled.\r
+ * 0b1..FIFO1 watermark interrupts are enabled.\r
+ */\r
+#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK)\r
+#define ADC_IE_FOFIE1_MASK (0x8U)\r
+#define ADC_IE_FOFIE1_SHIFT (3U)\r
+/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable\r
+ * 0b0..No result FIFO1 overflow has occurred since the last time the flag was cleared.\r
+ * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared.\r
+ */\r
+#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK)\r
+#define ADC_IE_TEXC_IE_MASK (0x100U)\r
+#define ADC_IE_TEXC_IE_SHIFT (8U)\r
+/*! TEXC_IE - Trigger Exception Interrupt Enable\r
+ * 0b0..Trigger exception interrupts are disabled.\r
+ * 0b1..Trigger exception interrupts are enabled.\r
+ */\r
+#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK)\r
+#define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U)\r
+#define ADC_IE_TCOMP_IE_SHIFT (16U)\r
+/*! TCOMP_IE - Trigger Completion Interrupt Enable\r
+ * 0b0000000000000000..Trigger completion interrupts are disabled.\r
+ * 0b0000000000000001..Trigger completion interrupts are enabled for trigger source 0 only.\r
+ * 0b0000000000000010..Trigger completion interrupts are enabled for trigger source 1 only.\r
+ * 0b0000000000000011-0b1111111111111110..Associated trigger completion interrupts are enabled.\r
+ * 0b1111111111111111..Trigger completion interrupts are enabled for every trigger source.\r
+ */\r
+#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DE - DMA Enable Register */\r
+/*! @{ */\r
+#define ADC_DE_FWMDE0_MASK (0x1U)\r
+#define ADC_DE_FWMDE0_SHIFT (0U)\r
+/*! FWMDE0 - FIFO 0 Watermark DMA Enable\r
+ * 0b0..DMA request disabled.\r
+ * 0b1..DMA request enabled.\r
+ */\r
+#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK)\r
+#define ADC_DE_FWMDE1_MASK (0x2U)\r
+#define ADC_DE_FWMDE1_SHIFT (1U)\r
+/*! FWMDE1 - FIFO1 Watermark DMA Enable\r
+ * 0b0..DMA request disabled.\r
+ * 0b1..DMA request enabled.\r
+ */\r
+#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK)\r
+/*! @} */\r
+\r
+/*! @name CFG - ADC Configuration Register */\r
+/*! @{ */\r
+#define ADC_CFG_TPRICTRL_MASK (0x3U)\r
+#define ADC_CFG_TPRICTRL_SHIFT (0U)\r
+/*! TPRICTRL - ADC trigger priority control\r
+ * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started.\r
+ * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced.\r
+ * 0b10..If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger.\r
+ * 0b11..RESERVED\r
+ */\r
+#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)\r
+#define ADC_CFG_PWRSEL_MASK (0x30U)\r
+#define ADC_CFG_PWRSEL_SHIFT (4U)\r
+/*! PWRSEL - Power Configuration Select\r
+ * 0b00..Lowest power setting.\r
+ * 0b01..Higher power setting than 0b0.\r
+ * 0b10..Higher power setting than 0b1.\r
+ * 0b11..Highest power setting.\r
+ */\r
+#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)\r
+#define ADC_CFG_REFSEL_MASK (0xC0U)\r
+#define ADC_CFG_REFSEL_SHIFT (6U)\r
+/*! REFSEL - Voltage Reference Selection\r
+ * 0b00..(Default) Option 1 setting.\r
+ * 0b01..Option 2 setting.\r
+ * 0b10..Option 3 setting.\r
+ * 0b11..Reserved\r
+ */\r
+#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)\r
+#define ADC_CFG_TRES_MASK (0x100U)\r
+#define ADC_CFG_TRES_SHIFT (8U)\r
+/*! TRES - Trigger Resume Enable\r
+ * 0b0..Trigger sequences interrupted by a high priority trigger exception will not be automatically resumed or restarted.\r
+ * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted.\r
+ */\r
+#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK)\r
+#define ADC_CFG_TCMDRES_MASK (0x200U)\r
+#define ADC_CFG_TCMDRES_SHIFT (9U)\r
+/*! TCMDRES - Trigger Command Resume\r
+ * 0b0..Trigger sequences interrupted by a high priority trigger exception will be automatically restarted.\r
+ * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception.\r
+ */\r
+#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK)\r
+#define ADC_CFG_HPT_EXDI_MASK (0x400U)\r
+#define ADC_CFG_HPT_EXDI_SHIFT (10U)\r
+/*! HPT_EXDI - High Priority Trigger Exception Disable\r
+ * 0b0..High priority trigger exceptions are enabled.\r
+ * 0b1..High priority trigger exceptions are disabled.\r
+ */\r
+#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK)\r
+#define ADC_CFG_PUDLY_MASK (0xFF0000U)\r
+#define ADC_CFG_PUDLY_SHIFT (16U)\r
+#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)\r
+#define ADC_CFG_PWREN_MASK (0x10000000U)\r
+#define ADC_CFG_PWREN_SHIFT (28U)\r
+/*! PWREN - ADC Analog Pre-Enable\r
+ * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.\r
+ * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). A single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog will remain pre-enabled, and no additional delays will be executed.\r
+ */\r
+#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)\r
+/*! @} */\r
+\r
+/*! @name PAUSE - ADC Pause Register */\r
+/*! @{ */\r
+#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)\r
+#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)\r
+#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)\r
+#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)\r
+#define ADC_PAUSE_PAUSEEN_SHIFT (31U)\r
+/*! PAUSEEN - PAUSE Option Enable\r
+ * 0b0..Pause operation disabled\r
+ * 0b1..Pause operation enabled\r
+ */\r
+#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name SWTRIG - Software Trigger Register */\r
+/*! @{ */\r
+#define ADC_SWTRIG_SWT0_MASK (0x1U)\r
+#define ADC_SWTRIG_SWT0_SHIFT (0U)\r
+/*! SWT0 - Software trigger 0 event\r
+ * 0b0..No trigger 0 event generated.\r
+ * 0b1..Trigger 0 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)\r
+#define ADC_SWTRIG_SWT1_MASK (0x2U)\r
+#define ADC_SWTRIG_SWT1_SHIFT (1U)\r
+/*! SWT1 - Software trigger 1 event\r
+ * 0b0..No trigger 1 event generated.\r
+ * 0b1..Trigger 1 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)\r
+#define ADC_SWTRIG_SWT2_MASK (0x4U)\r
+#define ADC_SWTRIG_SWT2_SHIFT (2U)\r
+/*! SWT2 - Software trigger 2 event\r
+ * 0b0..No trigger 2 event generated.\r
+ * 0b1..Trigger 2 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)\r
+#define ADC_SWTRIG_SWT3_MASK (0x8U)\r
+#define ADC_SWTRIG_SWT3_SHIFT (3U)\r
+/*! SWT3 - Software trigger 3 event\r
+ * 0b0..No trigger 3 event generated.\r
+ * 0b1..Trigger 3 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)\r
+#define ADC_SWTRIG_SWT4_MASK (0x10U)\r
+#define ADC_SWTRIG_SWT4_SHIFT (4U)\r
+/*! SWT4 - Software trigger 4 event\r
+ * 0b0..No trigger 4 event generated.\r
+ * 0b1..Trigger 4 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)\r
+#define ADC_SWTRIG_SWT5_MASK (0x20U)\r
+#define ADC_SWTRIG_SWT5_SHIFT (5U)\r
+/*! SWT5 - Software trigger 5 event\r
+ * 0b0..No trigger 5 event generated.\r
+ * 0b1..Trigger 5 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)\r
+#define ADC_SWTRIG_SWT6_MASK (0x40U)\r
+#define ADC_SWTRIG_SWT6_SHIFT (6U)\r
+/*! SWT6 - Software trigger 6 event\r
+ * 0b0..No trigger 6 event generated.\r
+ * 0b1..Trigger 6 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)\r
+#define ADC_SWTRIG_SWT7_MASK (0x80U)\r
+#define ADC_SWTRIG_SWT7_SHIFT (7U)\r
+/*! SWT7 - Software trigger 7 event\r
+ * 0b0..No trigger 7 event generated.\r
+ * 0b1..Trigger 7 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)\r
+#define ADC_SWTRIG_SWT8_MASK (0x100U)\r
+#define ADC_SWTRIG_SWT8_SHIFT (8U)\r
+/*! SWT8 - Software trigger 8 event\r
+ * 0b0..No trigger 8 event generated.\r
+ * 0b1..Trigger 8 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK)\r
+#define ADC_SWTRIG_SWT9_MASK (0x200U)\r
+#define ADC_SWTRIG_SWT9_SHIFT (9U)\r
+/*! SWT9 - Software trigger 9 event\r
+ * 0b0..No trigger 9 event generated.\r
+ * 0b1..Trigger 9 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK)\r
+#define ADC_SWTRIG_SWT10_MASK (0x400U)\r
+#define ADC_SWTRIG_SWT10_SHIFT (10U)\r
+/*! SWT10 - Software trigger 10 event\r
+ * 0b0..No trigger 10 event generated.\r
+ * 0b1..Trigger 10 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK)\r
+#define ADC_SWTRIG_SWT11_MASK (0x800U)\r
+#define ADC_SWTRIG_SWT11_SHIFT (11U)\r
+/*! SWT11 - Software trigger 11 event\r
+ * 0b0..No trigger 11 event generated.\r
+ * 0b1..Trigger 11 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK)\r
+#define ADC_SWTRIG_SWT12_MASK (0x1000U)\r
+#define ADC_SWTRIG_SWT12_SHIFT (12U)\r
+/*! SWT12 - Software trigger 12 event\r
+ * 0b0..No trigger 12 event generated.\r
+ * 0b1..Trigger 12 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK)\r
+#define ADC_SWTRIG_SWT13_MASK (0x2000U)\r
+#define ADC_SWTRIG_SWT13_SHIFT (13U)\r
+/*! SWT13 - Software trigger 13 event\r
+ * 0b0..No trigger 13 event generated.\r
+ * 0b1..Trigger 13 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK)\r
+#define ADC_SWTRIG_SWT14_MASK (0x4000U)\r
+#define ADC_SWTRIG_SWT14_SHIFT (14U)\r
+/*! SWT14 - Software trigger 14 event\r
+ * 0b0..No trigger 14 event generated.\r
+ * 0b1..Trigger 14 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK)\r
+#define ADC_SWTRIG_SWT15_MASK (0x8000U)\r
+#define ADC_SWTRIG_SWT15_SHIFT (15U)\r
+/*! SWT15 - Software trigger 15 event\r
+ * 0b0..No trigger 15 event generated.\r
+ * 0b1..Trigger 15 event generated.\r
+ */\r
+#define ADC_SWTRIG_SWT15(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT15_SHIFT)) & ADC_SWTRIG_SWT15_MASK)\r
+/*! @} */\r
+\r
+/*! @name TSTAT - Trigger Status Register */\r
+/*! @{ */\r
+#define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU)\r
+#define ADC_TSTAT_TEXC_NUM_SHIFT (0U)\r
+/*! TEXC_NUM - Trigger Exception Number\r
+ * 0b0000000000000000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1.\r
+ * 0b0000000000000001..Trigger 0 has been interrupted by a high priority exception.\r
+ * 0b0000000000000010..Trigger 1 has been interrupted by a high priority exception.\r
+ * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has interrupted by a high priority exception.\r
+ * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception.\r
+ */\r
+#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK)\r
+#define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U)\r
+#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U)\r
+/*! TCOMP_FLAG - Trigger Completion Flag\r
+ * 0b0000000000000000..No triggers have been completed. Trigger completion interrupts are disabled.\r
+ * 0b0000000000000001..Trigger 0 has been completed and triger 0 has enabled completion interrupts.\r
+ * 0b0000000000000010..Trigger 1 has been completed and triger 1 has enabled completion interrupts.\r
+ * 0b0000000000000011-0b1111111111111110..Associated trigger sequence has completed and has enabled completion interrupts.\r
+ * 0b1111111111111111..Every trigger sequence has been completed and every trigger has enabled completion interrupts.\r
+ */\r
+#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name OFSTRIM - ADC Offset Trim Register */\r
+/*! @{ */\r
+#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU)\r
+#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U)\r
+#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK)\r
+#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U)\r
+#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U)\r
+#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK)\r
+/*! @} */\r
+\r
+/*! @name TCTRL - Trigger Control Register */\r
+/*! @{ */\r
+#define ADC_TCTRL_HTEN_MASK (0x1U)\r
+#define ADC_TCTRL_HTEN_SHIFT (0U)\r
+/*! HTEN - Trigger enable\r
+ * 0b0..Hardware trigger source disabled\r
+ * 0b1..Hardware trigger source enabled\r
+ */\r
+#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)\r
+#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U)\r
+#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U)\r
+/*! FIFO_SEL_A - SAR Result Destination For Channel A\r
+ * 0b0..Result written to FIFO 0\r
+ * 0b1..Result written to FIFO 1\r
+ */\r
+#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK)\r
+#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U)\r
+#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U)\r
+/*! FIFO_SEL_B - SAR Result Destination For Channel B\r
+ * 0b0..Result written to FIFO 0\r
+ * 0b1..Result written to FIFO 1\r
+ */\r
+#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK)\r
+#define ADC_TCTRL_TPRI_MASK (0xF00U)\r
+#define ADC_TCTRL_TPRI_SHIFT (8U)\r
+/*! TPRI - Trigger priority setting\r
+ * 0b0000..Set to highest priority, Level 1\r
+ * 0b0001-0b1110..Set to corresponding priority level\r
+ * 0b1111..Set to lowest priority, Level 16\r
+ */\r
+#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)\r
+#define ADC_TCTRL_RSYNC_MASK (0x8000U)\r
+#define ADC_TCTRL_RSYNC_SHIFT (15U)\r
+#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK)\r
+#define ADC_TCTRL_TDLY_MASK (0xF0000U)\r
+#define ADC_TCTRL_TDLY_SHIFT (16U)\r
+#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)\r
+#define ADC_TCTRL_TCMD_MASK (0xF000000U)\r
+#define ADC_TCTRL_TCMD_SHIFT (24U)\r
+/*! TCMD - Trigger command select\r
+ * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.\r
+ * 0b0001..CMD1 is executed\r
+ * 0b0010-0b1110..Corresponding CMD is executed\r
+ * 0b1111..CMD15 is executed\r
+ */\r
+#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_TCTRL */\r
+#define ADC_TCTRL_COUNT (16U)\r
+\r
+/*! @name FCTRL - FIFO Control Register */\r
+/*! @{ */\r
+#define ADC_FCTRL_FCOUNT_MASK (0x1FU)\r
+#define ADC_FCTRL_FCOUNT_SHIFT (0U)\r
+#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)\r
+#define ADC_FCTRL_FWMARK_MASK (0xF0000U)\r
+#define ADC_FCTRL_FWMARK_SHIFT (16U)\r
+#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_FCTRL */\r
+#define ADC_FCTRL_COUNT (2U)\r
+\r
+/*! @name GCC - Gain Calibration Control */\r
+/*! @{ */\r
+#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU)\r
+#define ADC_GCC_GAIN_CAL_SHIFT (0U)\r
+#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK)\r
+#define ADC_GCC_RDY_MASK (0x1000000U)\r
+#define ADC_GCC_RDY_SHIFT (24U)\r
+/*! RDY - Gain Calibration Value Valid\r
+ * 0b0..The gain calibration value is invalid. Run the auto-calibration routine for this value to be written.\r
+ * 0b1..The gain calibration value is valid. It should be used to update the GCRa[GCALR] register field.\r
+ */\r
+#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_GCC */\r
+#define ADC_GCC_COUNT (2U)\r
+\r
+/*! @name GCR - Gain Calculation Result */\r
+/*! @{ */\r
+#define ADC_GCR_GCALR_MASK (0xFFFFU)\r
+#define ADC_GCR_GCALR_SHIFT (0U)\r
+#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK)\r
+#define ADC_GCR_RDY_MASK (0x1000000U)\r
+#define ADC_GCR_RDY_SHIFT (24U)\r
+/*! RDY - Gain Calculation Ready\r
+ * 0b0..The gain offset calculation value is invalid.\r
+ * 0b1..The gain calibration value is valid.\r
+ */\r
+#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_GCR */\r
+#define ADC_GCR_COUNT (2U)\r
+\r
+/*! @name CMDL - ADC Command Low Buffer Register */\r
+/*! @{ */\r
+#define ADC_CMDL_ADCH_MASK (0x1FU)\r
+#define ADC_CMDL_ADCH_SHIFT (0U)\r
+/*! ADCH - Input channel select\r
+ * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.\r
+ * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.\r
+ * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.\r
+ * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.\r
+ * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.\r
+ * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.\r
+ * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.\r
+ */\r
+#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)\r
+#define ADC_CMDL_CTYPE_MASK (0x60U)\r
+#define ADC_CMDL_CTYPE_SHIFT (5U)\r
+/*! CTYPE - Conversion Type\r
+ * 0b00..Single-Ended Mode. Only A side channel is converted.\r
+ * 0b01..Single-Ended Mode. Only B side channel is converted.\r
+ * 0b10..Differential Mode. A-B.\r
+ * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently.\r
+ */\r
+#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK)\r
+#define ADC_CMDL_MODE_MASK (0x80U)\r
+#define ADC_CMDL_MODE_SHIFT (7U)\r
+/*! MODE - Select resolution of conversions\r
+ * 0b0..Standard resolution. Single-ended 12-bit conversion; Differential 13-bit conversion with 2's complement output.\r
+ * 0b1..High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2's complement output.\r
+ */\r
+#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_CMDL */\r
+#define ADC_CMDL_COUNT (15U)\r
+\r
+/*! @name CMDH - ADC Command High Buffer Register */\r
+/*! @{ */\r
+#define ADC_CMDH_CMPEN_MASK (0x3U)\r
+#define ADC_CMDH_CMPEN_SHIFT (0U)\r
+/*! CMPEN - Compare Function Enable\r
+ * 0b00..Compare disabled.\r
+ * 0b01..Reserved\r
+ * 0b10..Compare enabled. Store on true.\r
+ * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.\r
+ */\r
+#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)\r
+#define ADC_CMDH_WAIT_TRIG_MASK (0x4U)\r
+#define ADC_CMDH_WAIT_TRIG_SHIFT (2U)\r
+/*! WAIT_TRIG - Wait for trigger assertion before execution.\r
+ * 0b0..This command will be automatically executed.\r
+ * 0b1..The active trigger must be asserted again before executing this command.\r
+ */\r
+#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK)\r
+#define ADC_CMDH_LWI_MASK (0x80U)\r
+#define ADC_CMDH_LWI_SHIFT (7U)\r
+/*! LWI - Loop with Increment\r
+ * 0b0..Auto channel increment disabled\r
+ * 0b1..Auto channel increment enabled\r
+ */\r
+#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)\r
+#define ADC_CMDH_STS_MASK (0x700U)\r
+#define ADC_CMDH_STS_SHIFT (8U)\r
+/*! STS - Sample Time Select\r
+ * 0b000..Minimum sample time of 3 ADCK cycles.\r
+ * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.\r
+ * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.\r
+ * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.\r
+ * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.\r
+ * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.\r
+ * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.\r
+ * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.\r
+ */\r
+#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)\r
+#define ADC_CMDH_AVGS_MASK (0x7000U)\r
+#define ADC_CMDH_AVGS_SHIFT (12U)\r
+/*! AVGS - Hardware Average Select\r
+ * 0b000..Single conversion.\r
+ * 0b001..2 conversions averaged.\r
+ * 0b010..4 conversions averaged.\r
+ * 0b011..8 conversions averaged.\r
+ * 0b100..16 conversions averaged.\r
+ * 0b101..32 conversions averaged.\r
+ * 0b110..64 conversions averaged.\r
+ * 0b111..128 conversions averaged.\r
+ */\r
+#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)\r
+#define ADC_CMDH_LOOP_MASK (0xF0000U)\r
+#define ADC_CMDH_LOOP_SHIFT (16U)\r
+/*! LOOP - Loop Count Select\r
+ * 0b0000..Looping not enabled. Command executes 1 time.\r
+ * 0b0001..Loop 1 time. Command executes 2 times.\r
+ * 0b0010..Loop 2 times. Command executes 3 times.\r
+ * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.\r
+ * 0b1111..Loop 15 times. Command executes 16 times.\r
+ */\r
+#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)\r
+#define ADC_CMDH_NEXT_MASK (0xF000000U)\r
+#define ADC_CMDH_NEXT_SHIFT (24U)\r
+/*! NEXT - Next Command Select\r
+ * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger.\r
+ * 0b0001..Select CMD1 command buffer register as next command.\r
+ * 0b0010-0b1110..Select corresponding CMD command buffer register as next command\r
+ * 0b1111..Select CMD15 command buffer register as next command.\r
+ */\r
+#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_CMDH */\r
+#define ADC_CMDH_COUNT (15U)\r
+\r
+/*! @name CV - Compare Value Register */\r
+/*! @{ */\r
+#define ADC_CV_CVL_MASK (0xFFFFU)\r
+#define ADC_CV_CVL_SHIFT (0U)\r
+#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)\r
+#define ADC_CV_CVH_MASK (0xFFFF0000U)\r
+#define ADC_CV_CVH_SHIFT (16U)\r
+#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_CV */\r
+#define ADC_CV_COUNT (4U)\r
+\r
+/*! @name RESFIFO - ADC Data Result FIFO Register */\r
+/*! @{ */\r
+#define ADC_RESFIFO_D_MASK (0xFFFFU)\r
+#define ADC_RESFIFO_D_SHIFT (0U)\r
+#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)\r
+#define ADC_RESFIFO_TSRC_MASK (0xF0000U)\r
+#define ADC_RESFIFO_TSRC_SHIFT (16U)\r
+/*! TSRC - Trigger Source\r
+ * 0b0000..Trigger source 0 initiated this conversion.\r
+ * 0b0001..Trigger source 1 initiated this conversion.\r
+ * 0b0010-0b1110..Corresponding trigger source initiated this conversion.\r
+ * 0b1111..Trigger source 15 initiated this conversion.\r
+ */\r
+#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)\r
+#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)\r
+#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)\r
+/*! LOOPCNT - Loop count value\r
+ * 0b0000..Result is from initial conversion in command.\r
+ * 0b0001..Result is from second conversion in command.\r
+ * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.\r
+ * 0b1111..Result is from 16th conversion in command.\r
+ */\r
+#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)\r
+#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)\r
+#define ADC_RESFIFO_CMDSRC_SHIFT (24U)\r
+/*! CMDSRC - Command Buffer Source\r
+ * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer.\r
+ * 0b0001..CMD1 buffer used as control settings for this conversion.\r
+ * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.\r
+ * 0b1111..CMD15 buffer used as control settings for this conversion.\r
+ */\r
+#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)\r
+#define ADC_RESFIFO_VALID_MASK (0x80000000U)\r
+#define ADC_RESFIFO_VALID_SHIFT (31U)\r
+/*! VALID - FIFO entry is valid\r
+ * 0b0..FIFO is empty. Discard any read from RESFIFO.\r
+ * 0b1..FIFO record read from RESFIFO is valid.\r
+ */\r
+#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_RESFIFO */\r
+#define ADC_RESFIFO_COUNT (2U)\r
+\r
+/*! @name CAL_GAR - Calibration General A-Side Registers */\r
+/*! @{ */\r
+#define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU)\r
+#define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U)\r
+#define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_CAL_GAR */\r
+#define ADC_CAL_GAR_COUNT (33U)\r
+\r
+/*! @name CAL_GBR - Calibration General B-Side Registers */\r
+/*! @{ */\r
+#define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU)\r
+#define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U)\r
+#define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK)\r
+/*! @} */\r
+\r
+/* The count of ADC_CAL_GBR */\r
+#define ADC_CAL_GBR_COUNT (33U)\r
+\r
+/*! @name TST - ADC Test Register */\r
+/*! @{ */\r
+#define ADC_TST_CST_LONG_MASK (0x1U)\r
+#define ADC_TST_CST_LONG_SHIFT (0U)\r
+/*! CST_LONG - Calibration Sample Time Long\r
+ * 0b0..Normal sample time. Minimum sample time of 3 ADCK cycles.\r
+ * 0b1..Increased sample time. 67 ADCK cycles total sample time.\r
+ */\r
+#define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK)\r
+#define ADC_TST_FOFFM_MASK (0x100U)\r
+#define ADC_TST_FOFFM_SHIFT (8U)\r
+/*! FOFFM - Force M-side positive offset\r
+ * 0b0..Normal operation. No forced offset.\r
+ * 0b1..Test configuration. Forced positive offset on MDAC.\r
+ */\r
+#define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK)\r
+#define ADC_TST_FOFFP_MASK (0x200U)\r
+#define ADC_TST_FOFFP_SHIFT (9U)\r
+/*! FOFFP - Force P-side positive offset\r
+ * 0b0..Normal operation. No forced offset.\r
+ * 0b1..Test configuration. Forced positive offset on PDAC.\r
+ */\r
+#define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK)\r
+#define ADC_TST_FOFFM2_MASK (0x400U)\r
+#define ADC_TST_FOFFM2_SHIFT (10U)\r
+/*! FOFFM2 - Force M-side negative offset\r
+ * 0b0..Normal operation. No forced offset.\r
+ * 0b1..Test configuration. Forced negative offset on MDAC.\r
+ */\r
+#define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK)\r
+#define ADC_TST_FOFFP2_MASK (0x800U)\r
+#define ADC_TST_FOFFP2_SHIFT (11U)\r
+/*! FOFFP2 - Force P-side negative offset\r
+ * 0b0..Normal operation. No forced offset.\r
+ * 0b1..Test configuration. Forced negative offset on PDAC.\r
+ */\r
+#define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK)\r
+#define ADC_TST_TESTEN_MASK (0x800000U)\r
+#define ADC_TST_TESTEN_SHIFT (23U)\r
+/*! TESTEN - Enable test configuration\r
+ * 0b0..Normal operation. Test configuration not enabled.\r
+ * 0b1..Hardware BIST Test in progress.\r
+ */\r
+#define ADC_TST_TESTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_TESTEN_SHIFT)) & ADC_TST_TESTEN_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ADC_Register_Masks */\r
+\r
+\r
+/* ADC - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral ADC0 base address */\r
+ #define ADC0_BASE (0x500A0000u)\r
+ /** Peripheral ADC0 base address */\r
+ #define ADC0_BASE_NS (0x400A0000u)\r
+ /** Peripheral ADC0 base pointer */\r
+ #define ADC0 ((ADC_Type *)ADC0_BASE)\r
+ /** Peripheral ADC0 base pointer */\r
+ #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS)\r
+ /** Array initializer of ADC peripheral base addresses */\r
+ #define ADC_BASE_ADDRS { ADC0_BASE }\r
+ /** Array initializer of ADC peripheral base pointers */\r
+ #define ADC_BASE_PTRS { ADC0 }\r
+ /** Array initializer of ADC peripheral base addresses */\r
+ #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS }\r
+ /** Array initializer of ADC peripheral base pointers */\r
+ #define ADC_BASE_PTRS_NS { ADC0_NS }\r
+#else\r
+ /** Peripheral ADC0 base address */\r
+ #define ADC0_BASE (0x400A0000u)\r
+ /** Peripheral ADC0 base pointer */\r
+ #define ADC0 ((ADC_Type *)ADC0_BASE)\r
+ /** Array initializer of ADC peripheral base addresses */\r
+ #define ADC_BASE_ADDRS { ADC0_BASE }\r
+ /** Array initializer of ADC peripheral base pointers */\r
+ #define ADC_BASE_PTRS { ADC0 }\r
+#endif\r
+/** Interrupt vectors for the ADC peripheral type */\r
+#define ADC_IRQS { ADC0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ADC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- AHB_SECURE_CTRL Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup AHB_SECURE_CTRL_Peripheral_Access_Layer AHB_SECURE_CTRL Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** AHB_SECURE_CTRL - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0, array step: 0x30 */\r
+ __IO uint32_t SLAVE_RULE; /**< , array offset: 0x0, array step: 0x30 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t SEC_CTRL_FLASH_MEM_RULE[3]; /**< Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total., array offset: 0x10, array step: index*0x30, index2*0x4 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t SEC_CTRL_ROM_MEM_RULE[4]; /**< Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total., array offset: 0x20, array step: index*0x30, index2*0x4 */\r
+ } SEC_CTRL_FLASH_ROM[1];\r
+ struct { /* offset: 0x30, array step: 0x14 */\r
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAMX slaves., array offset: 0x30, array step: 0x14 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[1]; /**< , array offset: 0x40, array step: index*0x14, index2*0x4 */\r
+ } SEC_CTRL_RAMX[1];\r
+ uint8_t RESERVED_0[12];\r
+ struct { /* offset: 0x50, array step: 0x18 */\r
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM0 slaves., array offset: 0x50, array step: 0x18 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[2]; /**< , array offset: 0x60, array step: index*0x18, index2*0x4 */\r
+ } SEC_CTRL_RAM0[1];\r
+ uint8_t RESERVED_1[8];\r
+ struct { /* offset: 0x70, array step: 0x18 */\r
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM1 slaves., array offset: 0x70, array step: 0x18 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[2]; /**< , array offset: 0x80, array step: index*0x18, index2*0x4 */\r
+ } SEC_CTRL_RAM1[1];\r
+ uint8_t RESERVED_2[8];\r
+ struct { /* offset: 0x90, array step: 0x18 */\r
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM2 slaves., array offset: 0x90, array step: 0x18 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[2]; /**< , array offset: 0xA0, array step: index*0x18, index2*0x4 */\r
+ } SEC_CTRL_RAM2[1];\r
+ uint8_t RESERVED_3[8];\r
+ struct { /* offset: 0xB0, array step: 0x18 */\r
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM3 slaves., array offset: 0xB0, array step: 0x18 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[2]; /**< , array offset: 0xC0, array step: index*0x18, index2*0x4 */\r
+ } SEC_CTRL_RAM3[1];\r
+ uint8_t RESERVED_4[8];\r
+ struct { /* offset: 0xD0, array step: 0x14 */\r
+ __IO uint32_t SLAVE_RULE; /**< Security access rules for RAM4 slaves., array offset: 0xD0, array step: 0x14 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[1]; /**< , array offset: 0xE0, array step: index*0x14, index2*0x4 */\r
+ } SEC_CTRL_RAM4[1];\r
+ uint8_t RESERVED_5[12];\r
+ struct { /* offset: 0xF0, array step: 0x30 */\r
+ __IO uint32_t SLAVE_RULE; /**< , array offset: 0xF0, array step: 0x30 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */\r
+ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */\r
+ } SEC_CTRL_APB_BRIDGE[1];\r
+ __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */\r
+ __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */\r
+ uint8_t RESERVED_6[8];\r
+ __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */\r
+ __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */\r
+ uint8_t RESERVED_7[12];\r
+ struct { /* offset: 0x144, array step: 0x14 */\r
+ __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */\r
+ __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x148, array step: 0x14 */\r
+ uint8_t RESERVED_0[8];\r
+ __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< , array offset: 0x154, array step: index*0x14, index2*0x4 */\r
+ } SEC_CTRL_AHB2[1];\r
+ uint8_t RESERVED_8[8];\r
+ struct { /* offset: 0x160, array step: 0x14 */\r
+ __IO uint32_t SLAVE_RULE; /**< , array offset: 0x160, array step: 0x14 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t MEM_RULE[1]; /**< , array offset: 0x170, array step: index*0x14, index2*0x4 */\r
+ } SEC_CTRL_USB_HS[1];\r
+ uint8_t RESERVED_9[3212];\r
+ __I uint32_t SEC_VIO_ADDR[18]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */\r
+ uint8_t RESERVED_10[56];\r
+ __I uint32_t SEC_VIO_MISC_INFO[18]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */\r
+ uint8_t RESERVED_11[56];\r
+ __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */\r
+ uint8_t RESERVED_12[124];\r
+ __IO uint32_t SEC_GPIO_MASK0; /**< Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world., offset: 0xF80 */\r
+ __IO uint32_t SEC_GPIO_MASK1; /**< Secure GPIO mask for port 1 pins., offset: 0xF84 */\r
+ __IO uint32_t SEC_GPIO_MASK2; /**< Secure GPIO mask for port 2 pins., offset: 0xF88 */\r
+ __IO uint32_t SEC_GPIO_MASK3; /**< Secure GPIO mask for port 3 pins., offset: 0xF8C */\r
+ __IO uint32_t SEC_CPU_INT_MASK0; /**< Secure Interrupt mask for CPU1, offset: 0xF90 */\r
+ __IO uint32_t SEC_CPU_INT_MASK1; /**< Secure Interrupt mask for CPU1, offset: 0xF94 */\r
+ uint8_t RESERVED_13[36];\r
+ __IO uint32_t SEC_MASK_LOCK; /**< Security General Purpose register access control., offset: 0xFBC */\r
+ uint8_t RESERVED_14[16];\r
+ __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */\r
+ __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */\r
+ uint8_t RESERVED_15[20];\r
+ __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */\r
+ __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */\r
+ uint8_t RESERVED_16[4];\r
+ __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */\r
+ __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */\r
+} AHB_SECURE_CTRL_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- AHB_SECURE_CTRL Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup AHB_SECURE_CTRL_Register_Masks AHB_SECURE_CTRL Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U)\r
+/*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U)\r
+/*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U)\r
+\r
+/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U)\r
+\r
+/*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U)\r
+/*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U)\r
+\r
+/*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U)\r
+/*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U)\r
+\r
+/*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U)\r
+/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U)\r
+\r
+/*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U)\r
+/*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U)\r
+\r
+/*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U)\r
+/*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U)\r
+/*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U)\r
+/*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U)\r
+/*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U)\r
+/*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U)\r
+\r
+/*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U)\r
+/*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U)\r
+/*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U)\r
+/*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U)\r
+/*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U)\r
+/*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0'\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U)\r
+/*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U)\r
+/*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U)\r
+/*! SYSCON_RULE - System Configuration\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U)\r
+/*! IOCON_RULE - I/O Configuration\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U)\r
+/*! GINT0_RULE - GPIO input Interrupt 0\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U)\r
+/*! GINT1_RULE - GPIO input Interrupt 1\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U)\r
+/*! PINT_RULE - Pin Interrupt and Pattern match\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U)\r
+/*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U)\r
+/*! PMUX_RULE - Peripherals mux\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U)\r
+/*! CTIMER0_RULE - Standard counter/Timer 0\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U)\r
+/*! CTIMER1_RULE - Standard counter/Timer 1\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U)\r
+/*! WWDT_RULE - Windiwed wtachdog Timer\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U)\r
+/*! MRT_RULE - Multi-rate Timer\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U)\r
+/*! UTICK_RULE - Micro-Timer\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U)\r
+/*! ANACTRL_RULE - Analog Modules controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U)\r
+/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_SHIFT (8U)\r
+/*! CAPTOUCH_RULE - Capacitive Touch controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_CAPTOUCH_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_SHIFT (20U)\r
+/*! EZH_RULE - EZH slave interface\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_EZH_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U)\r
+/*! PMC_RULE - Power Management Controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_SHIFT (8U)\r
+/*! PVT_RULE - Process and Voltage Monitoring controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PVT_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U)\r
+/*! SYSCTRL_RULE - System Controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U)\r
+/*! CTIMER2_RULE - Standard counter/Timer 2\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U)\r
+/*! CTIMER3_RULE - Standard counter/Timer 3\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U)\r
+/*! CTIMER4_RULE - Standard counter/Timer 4\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U)\r
+/*! RTC_RULE - Real Time Counter\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U)\r
+/*! OSEVENT_RULE - OS Event Timer\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U)\r
+/*! FLASH_CTRL_RULE - Flash Controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U)\r
+/*! PRINCE_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U)\r
+/*! USBHPHY_RULE - USB High Speed Phy controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U)\r
+/*! RNG_RULE - True Random Number Generator\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U)\r
+/*! PUFF_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U)\r
+/*! PLU_RULE - Programmable Look-Up logic\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_SHIFT (24U)\r
+/*! ROMPC_RULE - ROM patch controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_ROMPC_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U)\r
+/*! DMA0_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U)\r
+/*! FS_USB_DEV_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U)\r
+/*! SCT_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U)\r
+/*! FLEXCOMM0_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U)\r
+/*! FLEXCOMM1_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U)\r
+/*! FLEXCOMM2_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U)\r
+/*! FLEXCOMM3_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U)\r
+/*! FLEXCOMM4_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U)\r
+/*! MAILBOX_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U)\r
+/*! GPIO0_RULE - High Speed GPIO\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U)\r
+/*! USB_HS_DEV_RULE - USB high Speed device registers\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U)\r
+/*! CRC_RULE - CRC engine\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U)\r
+/*! FLEXCOMM5_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U)\r
+/*! FLEXCOMM6_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U)\r
+/*! FLEXCOMM7_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U)\r
+/*! SDIO_RULE\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U)\r
+/*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP)\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U)\r
+/*! HS_LSPI_RULE - High Speed SPI\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U)\r
+/*! ADC_RULE - ADC\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U)\r
+/*! USB_FS_HOST_RULE - USB Full Speed Host registers.\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U)\r
+/*! USB_HS_HOST_RULE - USB High speed host registers\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U)\r
+/*! HASH_RULE - SHA-2 crypto registers\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U)\r
+/*! CASPER_RULE - RSA/ECC crypto accelerator\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U)\r
+/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator)\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U)\r
+/*! DMA1_RULE - DMA Controller (Secure)\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U)\r
+/*! GPIO1_RULE - Secure High Speed GPIO\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U)\r
+/*! AHB_SEC_CTRL_RULE - AHB Secure Controller\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U)\r
+/*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U)\r
+/*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U)\r
+/*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U)\r
+/*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U)\r
+\r
+/*! @name SEC_CTRL_USB_HS_SLAVE_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U)\r
+/*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U)\r
+\r
+/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U)\r
+/*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U)\r
+/*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U)\r
+/*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U)\r
+/*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF\r
+ * 0b00..Non-secure and Non-priviledge user access allowed.\r
+ * 0b01..Non-secure and Privilege access allowed.\r
+ * 0b10..Secure and Non-priviledge user access allowed.\r
+ * 0b11..Secure and Priviledge user access allowed.\r
+ */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U)\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */\r
+#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U)\r
+\r
+/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU)\r
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */\r
+#define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (18U)\r
+\r
+/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK)\r
+/*! @} */\r
+\r
+/* The count of AHB_SECURE_CTRL_SEC_VIO_MISC_INFO */\r
+#define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_COUNT (18U)\r
+\r
+/*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U)\r
+#define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_GPIO_MASK2 - Secure GPIO mask for port 2 pins. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN0_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN1_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN2_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN3_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN4_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN5_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK (0x40U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN6_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK (0x80U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT (7U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN7_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK (0x100U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN8_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK (0x200U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT (9U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN9_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK (0x400U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN10_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK (0x800U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT (11U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN11_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK (0x1000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN12_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK (0x2000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT (13U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN13_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK (0x4000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN14_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK (0x8000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT (15U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN15_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK (0x10000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN16_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK (0x20000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT (17U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN17_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK (0x40000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN18_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK (0x80000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT (19U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN19_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK (0x100000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN20_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK (0x200000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT (21U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN21_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK (0x400000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN22_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK (0x800000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT (23U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN23_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK (0x1000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN24_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK (0x2000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT (25U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN25_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK (0x4000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT (26U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN26_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK (0x8000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT (27U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN27_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK (0x10000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT (28U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN28_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK (0x20000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT (29U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN29_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK (0x40000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN30_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK (0x80000000U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT (31U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK2_PIO2_PIN31_SEC_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_GPIO_MASK3 - Secure GPIO mask for port 3 pins. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN0_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN1_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN2_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN3_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN4_SEC_MASK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK3_PIO3_PIN5_SEC_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_MASK (0x40000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_EZH_ARCH_B_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_MASK (0x10000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_SHIFT (28U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_AMBER_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_MASK (0x20000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_SHIFT (29U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF0_RED_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_MASK (0x40000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_AMBER_IRQ_MASK)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_MASK (0x80000000U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_SHIFT (31U)\r
+#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PVTVF1_RED_IRQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEC_MASK_LOCK - Security General Purpose register access control. */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK2_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK (0xC0U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK3_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASTER_SEC_LEVEL - master secure level register */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_D_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_MASK (0xC000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_EZH_I_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_D_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK (0xC000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_EZH_I_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U)\r
+#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name MISC_CTRL_DP_REG - secure control duplicate register */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK)\r
+/*! @} */\r
+\r
+/*! @name MISC_CTRL_REG - secure control register */\r
+/*! @{ */\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U)\r
+#define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group AHB_SECURE_CTRL_Register_Masks */\r
+\r
+\r
+/* AHB_SECURE_CTRL - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral AHB_SECURE_CTRL base address */\r
+ #define AHB_SECURE_CTRL_BASE (0x500AC000u)\r
+ /** Peripheral AHB_SECURE_CTRL base address */\r
+ #define AHB_SECURE_CTRL_BASE_NS (0x400AC000u)\r
+ /** Peripheral AHB_SECURE_CTRL base pointer */\r
+ #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)\r
+ /** Peripheral AHB_SECURE_CTRL base pointer */\r
+ #define AHB_SECURE_CTRL_NS ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE_NS)\r
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */\r
+ #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }\r
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */\r
+ #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }\r
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */\r
+ #define AHB_SECURE_CTRL_BASE_ADDRS_NS { AHB_SECURE_CTRL_BASE_NS }\r
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */\r
+ #define AHB_SECURE_CTRL_BASE_PTRS_NS { AHB_SECURE_CTRL_NS }\r
+#else\r
+ /** Peripheral AHB_SECURE_CTRL base address */\r
+ #define AHB_SECURE_CTRL_BASE (0x400AC000u)\r
+ /** Peripheral AHB_SECURE_CTRL base pointer */\r
+ #define AHB_SECURE_CTRL ((AHB_SECURE_CTRL_Type *)AHB_SECURE_CTRL_BASE)\r
+ /** Array initializer of AHB_SECURE_CTRL peripheral base addresses */\r
+ #define AHB_SECURE_CTRL_BASE_ADDRS { AHB_SECURE_CTRL_BASE }\r
+ /** Array initializer of AHB_SECURE_CTRL peripheral base pointers */\r
+ #define AHB_SECURE_CTRL_BASE_PTRS { AHB_SECURE_CTRL }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group AHB_SECURE_CTRL_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ANACTRL Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ANACTRL_Peripheral_Access_Layer ANACTRL Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** ANACTRL - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t ANALOG_CTRL_CFG; /**< Various Analog blocks configuration (like FRO 192MHz trimmings source ...), offset: 0x0 */\r
+ __I uint32_t ANALOG_CTRL_STATUS; /**< Analog Macroblock Identity registers, Flash Status registers, offset: 0x4 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t FREQ_ME_CTRL; /**< Frequency Measure function control register, offset: 0xC */\r
+ __IO uint32_t FRO192M_CTRL; /**< 192MHz Free Running OScillator (FRO) Control register, offset: 0x10 */\r
+ __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */\r
+ __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */\r
+ __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */\r
+ uint8_t RESERVED_2[8];\r
+ __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */\r
+ __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */\r
+ uint8_t RESERVED_3[8];\r
+ __IO uint32_t RINGO0_CTRL; /**< First Ring Oscillator module control register., offset: 0x40 */\r
+ __IO uint32_t RINGO1_CTRL; /**< Second Ring Oscillator module control register., offset: 0x44 */\r
+ __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */\r
+ uint8_t RESERVED_4[100];\r
+ __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */\r
+ uint8_t RESERVED_5[12];\r
+ __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */\r
+ __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */\r
+ __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */\r
+ uint8_t RESERVED_6[52];\r
+ __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */\r
+ __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */\r
+ __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */\r
+} ANACTRL_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- ANACTRL Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup ANACTRL_Register_Masks ANACTRL Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */\r
+/*! @{ */\r
+#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U)\r
+#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U)\r
+/*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source.\r
+ * 0b0..FRO192M trimming and 'Enable' comes from eFUSE.\r
+ * 0b1..FRO192M trimming and 'Enable' comes from FRO192M_CTRL registers.\r
+ */\r
+#define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT)) & ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK)\r
+/*! @} */\r
+\r
+/*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */\r
+/*! @{ */\r
+#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U)\r
+/*! FLASH_PWRDWN - Flash Power Down status.\r
+ * 0b0..Flash is not in power down mode.\r
+ * 0b1..Flash is in power down mode.\r
+ */\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U)\r
+/*! FLASH_INIT_ERROR - Flash initialization error status.\r
+ * 0b0..No error.\r
+ * 0b1..At least one error occured during flash initialization..\r
+ */\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U)\r
+#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FREQ_ME_CTRL - Frequency Measure function control register */\r
+/*! @{ */\r
+#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU)\r
+#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U)\r
+#define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK)\r
+#define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U)\r
+#define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U)\r
+#define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */\r
+/*! @{ */\r
+#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU)\r
+#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U)\r
+#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK)\r
+#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U)\r
+#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U)\r
+#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK)\r
+#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U)\r
+#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U)\r
+/*! ENA_12MHZCLK - 12 MHz clock control.\r
+ * 0b0..12 MHz clock is disabled.\r
+ * 0b1..12 MHz clock is enabled.\r
+ */\r
+#define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK)\r
+#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U)\r
+#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U)\r
+/*! ENA_48MHZCLK - 48 MHz clock control.\r
+ * 0b0..48 MHz clock is disabled.\r
+ * 0b1..48 MHz clock is enabled.\r
+ */\r
+#define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK)\r
+#define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U)\r
+#define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U)\r
+#define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK)\r
+#define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U)\r
+#define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U)\r
+#define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK)\r
+#define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U)\r
+#define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U)\r
+#define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK)\r
+#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U)\r
+#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U)\r
+#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK)\r
+#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U)\r
+#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U)\r
+/*! ENA_96MHZCLK - 96 MHz clock control.\r
+ * 0b0..96 MHz clock is disabled.\r
+ * 0b1..96 MHz clock is enabled.\r
+ */\r
+#define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK)\r
+#define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U)\r
+#define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U)\r
+#define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK)\r
+/*! @} */\r
+\r
+/*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */\r
+/*! @{ */\r
+#define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U)\r
+#define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U)\r
+/*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled.\r
+ * 0b0..No output clock present (None of 12 MHz, 48 MHz or 96 MHz clock is available).\r
+ * 0b1..Clock is present (12 MHz, 48 MHz or 96 MHz can be output if they are enable respectively by FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK).\r
+ */\r
+#define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK)\r
+#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U)\r
+#define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U)\r
+#define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */\r
+/*! @{ */\r
+#define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U)\r
+#define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U)\r
+/*! VBATDIVENABLE - Switch On/Off VBAT divider branch.\r
+ * 0b0..VBAT divider branch is disabled.\r
+ * 0b1..VBAT divider branch is enabled.\r
+ */\r
+#define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */\r
+/*! @{ */\r
+#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU)\r
+#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U)\r
+#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK)\r
+#define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U)\r
+#define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U)\r
+#define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK)\r
+#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U)\r
+#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U)\r
+#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK)\r
+#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U)\r
+#define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U)\r
+#define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK)\r
+#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U)\r
+#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U)\r
+#define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK)\r
+#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U)\r
+#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U)\r
+/*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level.\r
+ * 0b0..XO AC buffer bypass is disabled.\r
+ * 0b1..XO AC buffer bypass is enabled.\r
+ */\r
+#define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK)\r
+#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U)\r
+#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U)\r
+/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL.\r
+ * 0b0..XO 32 MHz output to USB HS PLL is disabled.\r
+ * 0b1..XO 32 MHz output to USB HS PLL is enabled.\r
+ */\r
+#define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK)\r
+#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U)\r
+#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U)\r
+/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system.\r
+ * 0b0..XO 32 MHz output to CPU system is disabled.\r
+ * 0b1..XO 32 MHz output to CPU system is enabled.\r
+ */\r
+#define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U)\r
+/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal.\r
+ * 0b0..Sourced from CAPTESTSTART.\r
+ * 0b1..Sourced from calibration.\r
+ */\r
+#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U)\r
+/*! CAPTESTENABLE - Enable signal for captest.\r
+ * 0b0..Captest is disabled.\r
+ * 0b1..Captest is enabled.\r
+ */\r
+#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U)\r
+#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U)\r
+/*! CAPTESTOSCINSEL - Select the input for test.\r
+ * 0b0..osc_out (oscillator output) pin.\r
+ * 0b1..osc_in (oscillator) pin.\r
+ */\r
+#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */\r
+/*! @{ */\r
+#define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U)\r
+#define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U)\r
+/*! XO_READY - Indicates XO out frequency statibilty.\r
+ * 0b0..XO output frequency is not yet stable.\r
+ * 0b1..XO output frequency is stable.\r
+ */\r
+#define ANACTRL_XO32M_STATUS_XO_READY(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_STATUS_XO_READY_SHIFT)) & ANACTRL_XO32M_STATUS_XO_READY_MASK)\r
+/*! @} */\r
+\r
+/*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */\r
+/*! @{ */\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U)\r
+/*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control.\r
+ * 0b0..BOD VBAT interrupt is disabled.\r
+ * 0b1..BOD VBAT interrupt is enabled.\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U)\r
+/*! BODCORE_INT_ENABLE - BOD CORE interrupt control.\r
+ * 0b0..BOD CORE interrupt is disabled.\r
+ * 0b1..BOD CORE interrupt is enabled.\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U)\r
+/*! DCDC_INT_ENABLE - DCDC interrupt control.\r
+ * 0b0..DCDC interrupt is disabled.\r
+ * 0b1..DCDC interrupt is enabled.\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U)\r
+#define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK)\r
+/*! @} */\r
+\r
+/*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */\r
+/*! @{ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U)\r
+/*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable.\r
+ * 0b0..No interrupt pending..\r
+ * 0b1..Interrupt pending..\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U)\r
+/*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable.\r
+ * 0b0..No interrupt pending..\r
+ * 0b1..Interrupt pending..\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U)\r
+/*! BODVBAT_VAL - Current value of BOD VBAT power status output.\r
+ * 0b0..VBAT voltage level is below the threshold.\r
+ * 0b1..VBAT voltage level is above the threshold.\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U)\r
+/*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable.\r
+ * 0b0..No interrupt pending..\r
+ * 0b1..Interrupt pending..\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U)\r
+/*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable.\r
+ * 0b0..No interrupt pending..\r
+ * 0b1..Interrupt pending..\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U)\r
+/*! BODCORE_VAL - Current value of BOD CORE power status output.\r
+ * 0b0..CORE voltage level is below the threshold.\r
+ * 0b1..CORE voltage level is above the threshold.\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U)\r
+/*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable.\r
+ * 0b0..No interrupt pending..\r
+ * 0b1..Interrupt pending..\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U)\r
+/*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable.\r
+ * 0b0..No interrupt pending..\r
+ * 0b1..Interrupt pending..\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U)\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U)\r
+/*! DCDC_VAL - Current value of DCDC power status output.\r
+ * 0b0..DCDC output Voltage is below the targeted regulation level.\r
+ * 0b1..DCDC output Voltage is above the targeted regulation level.\r
+ */\r
+#define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name RINGO0_CTRL - First Ring Oscillator module control register. */\r
+/*! @{ */\r
+#define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U)\r
+#define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U)\r
+/*! SL - Select short or long ringo (for all ringos types).\r
+ * 0b0..Select short ringo (few elements).\r
+ * 0b1..Select long ringo (many elements).\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK)\r
+#define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U)\r
+#define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U)\r
+/*! FS - Ringo frequency output divider.\r
+ * 0b0..High frequency output (frequency lower than 100 MHz).\r
+ * 0b1..Low frequency output (frequency lower than 10 MHz).\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK)\r
+#define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU)\r
+#define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U)\r
+/*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control.\r
+ * 0b00..Normal mode.\r
+ * 0b01..P-Monitor mode. Measure with weak P transistor.\r
+ * 0b10..P-Monitor mode. Measure with weak N transistor.\r
+ * 0b11..Don't use.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK)\r
+#define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U)\r
+#define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U)\r
+/*! PD - Ringo module Power control.\r
+ * 0b0..The Ringo module is enabled.\r
+ * 0b1..The Ringo module is disabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U)\r
+#define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U)\r
+/*! E_ND0 - First NAND2-based ringo control.\r
+ * 0b0..First NAND2-based ringo is disabled.\r
+ * 0b1..First NAND2-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U)\r
+#define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U)\r
+/*! E_ND1 - Second NAND2-based ringo control.\r
+ * 0b0..Second NAND2-based ringo is disabled.\r
+ * 0b1..Second NAND2-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U)\r
+#define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U)\r
+/*! E_NR0 - First NOR2-based ringo control.\r
+ * 0b0..First NOR2-based ringo is disabled.\r
+ * 0b1..First NOR2-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U)\r
+#define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U)\r
+/*! E_NR1 - Second NOR2-based ringo control.\r
+ * 0b0..Second NORD2-based ringo is disabled.\r
+ * 0b1..Second NORD2-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U)\r
+#define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U)\r
+/*! E_IV0 - First Inverter-based ringo control.\r
+ * 0b0..First INV-based ringo is disabled.\r
+ * 0b1..First INV-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U)\r
+#define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U)\r
+/*! E_IV1 - Second Inverter-based ringo control.\r
+ * 0b0..Second INV-based ringo is disabled.\r
+ * 0b1..Second INV-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U)\r
+#define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U)\r
+/*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control.\r
+ * 0b0..First PN-based ringo is disabled.\r
+ * 0b1..First PN-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK)\r
+#define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U)\r
+#define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U)\r
+/*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control.\r
+ * 0b0..Second PN-based ringo is disabled.\r
+ * 0b1..Second PN-based ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK)\r
+#define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U)\r
+#define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U)\r
+#define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK)\r
+#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)\r
+#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U)\r
+#define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */\r
+/*! @{ */\r
+#define ANACTRL_RINGO1_CTRL_S_MASK (0x1U)\r
+#define ANACTRL_RINGO1_CTRL_S_SHIFT (0U)\r
+/*! S - Select short or long ringo (for all ringos types).\r
+ * 0b0..Select short ringo (few elements).\r
+ * 0b1..Select long ringo (many elements).\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK)\r
+#define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U)\r
+#define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U)\r
+/*! FS - Ringo frequency output divider.\r
+ * 0b0..High frequency output (frequency lower than 100 MHz).\r
+ * 0b1..Low frequency output (frequency lower than 10 MHz).\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK)\r
+#define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U)\r
+#define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U)\r
+/*! PD - Ringo module Power control.\r
+ * 0b0..The Ringo module is enabled.\r
+ * 0b1..The Ringo module is disabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK)\r
+#define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U)\r
+#define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U)\r
+/*! E_R24 - .\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK)\r
+#define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U)\r
+#define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U)\r
+/*! E_R35 - .\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK)\r
+#define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U)\r
+#define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U)\r
+/*! E_M2 - Metal 2 (M2) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK)\r
+#define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U)\r
+#define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U)\r
+/*! E_M3 - Metal 3 (M3) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK)\r
+#define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U)\r
+#define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U)\r
+/*! E_M4 - Metal 4 (M4) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK)\r
+#define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U)\r
+#define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U)\r
+/*! E_M5 - Metal 5 (M5) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK)\r
+#define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U)\r
+#define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U)\r
+#define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK)\r
+#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)\r
+#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U)\r
+#define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */\r
+/*! @{ */\r
+#define ANACTRL_RINGO2_CTRL_S_MASK (0x1U)\r
+#define ANACTRL_RINGO2_CTRL_S_SHIFT (0U)\r
+/*! S - Select short or long ringo (for all ringos types).\r
+ * 0b0..Select short ringo (few elements).\r
+ * 0b1..Select long ringo (many elements).\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK)\r
+#define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U)\r
+#define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U)\r
+/*! FS - Ringo frequency output divider.\r
+ * 0b0..High frequency output (frequency lower than 100 MHz).\r
+ * 0b1..Low frequency output (frequency lower than 10 MHz).\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK)\r
+#define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U)\r
+#define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U)\r
+/*! PD - Ringo module Power control.\r
+ * 0b0..The Ringo module is enabled.\r
+ * 0b1..The Ringo module is disabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK)\r
+#define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U)\r
+#define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U)\r
+/*! E_R24 - .\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK)\r
+#define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U)\r
+#define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U)\r
+/*! E_R35 - .\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK)\r
+#define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U)\r
+#define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U)\r
+/*! E_M2 - Metal 2 (M2) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK)\r
+#define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U)\r
+#define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U)\r
+/*! E_M3 - Metal 3 (M3) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK)\r
+#define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U)\r
+#define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U)\r
+/*! E_M4 - Metal 4 (M4) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK)\r
+#define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U)\r
+#define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U)\r
+/*! E_M5 - Metal 5 (M5) monitor control.\r
+ * 0b0..Ringo is disabled.\r
+ * 0b1..Ringo is enabled.\r
+ */\r
+#define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK)\r
+#define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U)\r
+#define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U)\r
+#define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK)\r
+#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U)\r
+#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U)\r
+#define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */\r
+/*! @{ */\r
+#define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U)\r
+#define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U)\r
+/*! BYPASS - Activate LDO bypass.\r
+ * 0b0..Disable bypass mode (for normal operations).\r
+ * 0b1..Activate LDO bypass.\r
+ */\r
+#define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK)\r
+#define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U)\r
+#define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U)\r
+/*! HIGHZ - .\r
+ * 0b0..Output in High normal state.\r
+ * 0b1..Output in High Impedance state.\r
+ */\r
+#define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK)\r
+#define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U)\r
+#define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U)\r
+/*! VOUT - Sets the LDO output level.\r
+ * 0b000..0.750 V.\r
+ * 0b001..0.775 V.\r
+ * 0b010..0.800 V.\r
+ * 0b011..0.825 V.\r
+ * 0b100..0.850 V.\r
+ * 0b101..0.875 V.\r
+ * 0b110..0.900 V.\r
+ * 0b111..0.925 V.\r
+ */\r
+#define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK)\r
+#define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U)\r
+#define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U)\r
+#define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK)\r
+#define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U)\r
+#define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U)\r
+#define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */\r
+/*! @{ */\r
+#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U)\r
+#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U)\r
+#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK)\r
+#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U)\r
+#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U)\r
+#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK)\r
+#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U)\r
+#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U)\r
+#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK)\r
+#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U)\r
+#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U)\r
+#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK)\r
+#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U)\r
+#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U)\r
+#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK)\r
+#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U)\r
+#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U)\r
+/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used.\r
+ * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used\r
+ * 0b1..32 kHz crystal oscillator calibration is used.\r
+ */\r
+#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */\r
+/*! @{ */\r
+#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U)\r
+#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U)\r
+#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK)\r
+#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U)\r
+#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U)\r
+#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK)\r
+#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U)\r
+#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U)\r
+#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK)\r
+/*! @} */\r
+\r
+/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */\r
+/*! @{ */\r
+#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU)\r
+#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U)\r
+#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK)\r
+#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U)\r
+#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U)\r
+#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */\r
+/*! @{ */\r
+#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U)\r
+#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U)\r
+#define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK)\r
+#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U)\r
+#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U)\r
+#define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK)\r
+#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U)\r
+#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U)\r
+#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */\r
+/*! @{ */\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U)\r
+#define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */\r
+/*! @{ */\r
+#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U)\r
+#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U)\r
+#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK)\r
+#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U)\r
+#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U)\r
+#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK)\r
+#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U)\r
+#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U)\r
+#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U)\r
+#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ANACTRL_Register_Masks */\r
+\r
+\r
+/* ANACTRL - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral ANACTRL base address */\r
+ #define ANACTRL_BASE (0x50013000u)\r
+ /** Peripheral ANACTRL base address */\r
+ #define ANACTRL_BASE_NS (0x40013000u)\r
+ /** Peripheral ANACTRL base pointer */\r
+ #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)\r
+ /** Peripheral ANACTRL base pointer */\r
+ #define ANACTRL_NS ((ANACTRL_Type *)ANACTRL_BASE_NS)\r
+ /** Array initializer of ANACTRL peripheral base addresses */\r
+ #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }\r
+ /** Array initializer of ANACTRL peripheral base pointers */\r
+ #define ANACTRL_BASE_PTRS { ANACTRL }\r
+ /** Array initializer of ANACTRL peripheral base addresses */\r
+ #define ANACTRL_BASE_ADDRS_NS { ANACTRL_BASE_NS }\r
+ /** Array initializer of ANACTRL peripheral base pointers */\r
+ #define ANACTRL_BASE_PTRS_NS { ANACTRL_NS }\r
+#else\r
+ /** Peripheral ANACTRL base address */\r
+ #define ANACTRL_BASE (0x40013000u)\r
+ /** Peripheral ANACTRL base pointer */\r
+ #define ANACTRL ((ANACTRL_Type *)ANACTRL_BASE)\r
+ /** Array initializer of ANACTRL peripheral base addresses */\r
+ #define ANACTRL_BASE_ADDRS { ANACTRL_BASE }\r
+ /** Array initializer of ANACTRL peripheral base pointers */\r
+ #define ANACTRL_BASE_PTRS { ANACTRL }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group ANACTRL_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CASPER Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CASPER_Peripheral_Access_Layer CASPER Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** CASPER - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL0; /**< Contains the offsets of AB and CD in the RAM., offset: 0x0 */\r
+ __IO uint32_t CTRL1; /**< Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR., offset: 0x4 */\r
+ __IO uint32_t LOADER; /**< Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations., offset: 0x8 */\r
+ __IO uint32_t STATUS; /**< Indicates operational status and would contain the carry bit if used., offset: 0xC */\r
+ __IO uint32_t INTENSET; /**< Sets interrupts, offset: 0x10 */\r
+ __IO uint32_t INTENCLR; /**< Clears interrupts, offset: 0x14 */\r
+ __I uint32_t INTSTAT; /**< Interrupt status bits (mask of INTENSET and STATUS), offset: 0x18 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t AREG; /**< A register, offset: 0x20 */\r
+ __IO uint32_t BREG; /**< B register, offset: 0x24 */\r
+ __IO uint32_t CREG; /**< C register, offset: 0x28 */\r
+ __IO uint32_t DREG; /**< D register, offset: 0x2C */\r
+ __IO uint32_t RES0; /**< Result register 0, offset: 0x30 */\r
+ __IO uint32_t RES1; /**< Result register 1, offset: 0x34 */\r
+ __IO uint32_t RES2; /**< Result register 2, offset: 0x38 */\r
+ __IO uint32_t RES3; /**< Result register 3, offset: 0x3C */\r
+ uint8_t RESERVED_1[32];\r
+ __IO uint32_t MASK; /**< Optional mask register, offset: 0x60 */\r
+ __IO uint32_t REMASK; /**< Optional re-mask register, offset: 0x64 */\r
+ uint8_t RESERVED_2[24];\r
+ __IO uint32_t LOCK; /**< Security lock register, offset: 0x80 */\r
+} CASPER_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CASPER Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CASPER_Register_Masks CASPER Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */\r
+/*! @{ */\r
+#define CASPER_CTRL0_ABBPAIR_MASK (0x1U)\r
+#define CASPER_CTRL0_ABBPAIR_SHIFT (0U)\r
+/*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up\r
+ * 0b0..Bank-pair 0 (1st)\r
+ * 0b1..Bank-pair 1 (2nd)\r
+ */\r
+#define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK)\r
+#define CASPER_CTRL0_ABOFF_MASK (0x4U)\r
+#define CASPER_CTRL0_ABOFF_SHIFT (2U)\r
+#define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK)\r
+#define CASPER_CTRL0_CDBPAIR_MASK (0x10000U)\r
+#define CASPER_CTRL0_CDBPAIR_SHIFT (16U)\r
+/*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up\r
+ * 0b0..Bank-pair 0 (1st)\r
+ * 0b1..Bank-pair 1 (2nd)\r
+ */\r
+#define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK)\r
+#define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U)\r
+#define CASPER_CTRL0_CDOFF_SHIFT (18U)\r
+#define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */\r
+/*! @{ */\r
+#define CASPER_CTRL1_ITER_MASK (0xFFU)\r
+#define CASPER_CTRL1_ITER_SHIFT (0U)\r
+#define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK)\r
+#define CASPER_CTRL1_MODE_MASK (0xFF00U)\r
+#define CASPER_CTRL1_MODE_SHIFT (8U)\r
+#define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK)\r
+#define CASPER_CTRL1_RESBPAIR_MASK (0x10000U)\r
+#define CASPER_CTRL1_RESBPAIR_SHIFT (16U)\r
+/*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally this is not the same bank as ABBPAIR (when 4-up supported)\r
+ * 0b0..Bank-pair 0 (1st)\r
+ * 0b1..Bank-pair 1 (2nd)\r
+ */\r
+#define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK)\r
+#define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U)\r
+#define CASPER_CTRL1_RESOFF_SHIFT (18U)\r
+#define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK)\r
+#define CASPER_CTRL1_CSKIP_MASK (0xC0000000U)\r
+#define CASPER_CTRL1_CSKIP_SHIFT (30U)\r
+/*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0:\r
+ * 0b00..No Skip\r
+ * 0b01..Skip if Carry is 1\r
+ * 0b10..Skip if Carry is 0\r
+ * 0b11..Set CTRLOFF to CDOFF and Skip\r
+ */\r
+#define CASPER_CTRL1_CSKIP(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_CSKIP_SHIFT)) & CASPER_CTRL1_CSKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */\r
+/*! @{ */\r
+#define CASPER_LOADER_COUNT_MASK (0xFFU)\r
+#define CASPER_LOADER_COUNT_SHIFT (0U)\r
+#define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK)\r
+#define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U)\r
+#define CASPER_LOADER_CTRLBPAIR_SHIFT (16U)\r
+/*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not matter which bank is used as this is loaded when not performing an operation.\r
+ * 0b0..Bank-pair 0 (1st)\r
+ * 0b1..Bank-pair 1 (2nd)\r
+ */\r
+#define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK)\r
+#define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U)\r
+#define CASPER_LOADER_CTRLOFF_SHIFT (18U)\r
+#define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - Indicates operational status and would contain the carry bit if used. */\r
+/*! @{ */\r
+#define CASPER_STATUS_DONE_MASK (0x1U)\r
+#define CASPER_STATUS_DONE_SHIFT (0U)\r
+/*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear.\r
+ * 0b0..Busy or just cleared\r
+ * 0b1..Completed last operation\r
+ */\r
+#define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK)\r
+#define CASPER_STATUS_CARRY_MASK (0x10U)\r
+#define CASPER_STATUS_CARRY_SHIFT (4U)\r
+/*! CARRY - Last carry value if operation produced a carry bit\r
+ * 0b0..Carry was 0 or no carry\r
+ * 0b1..Carry was 1\r
+ */\r
+#define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK)\r
+#define CASPER_STATUS_BUSY_MASK (0x20U)\r
+#define CASPER_STATUS_BUSY_SHIFT (5U)\r
+/*! BUSY - Indicates if the accelerator is busy performing an operation\r
+ * 0b0..Not busy - is idle\r
+ * 0b1..Is busy\r
+ */\r
+#define CASPER_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_BUSY_SHIFT)) & CASPER_STATUS_BUSY_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Sets interrupts */\r
+/*! @{ */\r
+#define CASPER_INTENSET_DONE_MASK (0x1U)\r
+#define CASPER_INTENSET_DONE_SHIFT (0U)\r
+/*! DONE - Set if the accelerator should interrupt when done.\r
+ * 0b0..Do not interrupt when done\r
+ * 0b1..Interrupt when done\r
+ */\r
+#define CASPER_INTENSET_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENSET_DONE_SHIFT)) & CASPER_INTENSET_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Clears interrupts */\r
+/*! @{ */\r
+#define CASPER_INTENCLR_DONE_MASK (0x1U)\r
+#define CASPER_INTENCLR_DONE_SHIFT (0U)\r
+/*! DONE - Written to clear an interrupt set with INTENSET.\r
+ * 0b0..If written 0, ignored\r
+ * 0b1..If written 1, do not Interrupt when done\r
+ */\r
+#define CASPER_INTENCLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTENCLR_DONE_SHIFT)) & CASPER_INTENCLR_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */\r
+/*! @{ */\r
+#define CASPER_INTSTAT_DONE_MASK (0x1U)\r
+#define CASPER_INTSTAT_DONE_SHIFT (0U)\r
+/*! DONE - If set, interrupt is caused by accelerator being done.\r
+ * 0b0..Not caused by accelerator being done\r
+ * 0b1..Caused by accelerator being done\r
+ */\r
+#define CASPER_INTSTAT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_INTSTAT_DONE_SHIFT)) & CASPER_INTSTAT_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name AREG - A register */\r
+/*! @{ */\r
+#define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_AREG_REG_VALUE_SHIFT (0U)\r
+#define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name BREG - B register */\r
+/*! @{ */\r
+#define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_BREG_REG_VALUE_SHIFT (0U)\r
+#define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CREG - C register */\r
+/*! @{ */\r
+#define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_CREG_REG_VALUE_SHIFT (0U)\r
+#define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DREG - D register */\r
+/*! @{ */\r
+#define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_DREG_REG_VALUE_SHIFT (0U)\r
+#define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name RES0 - Result register 0 */\r
+/*! @{ */\r
+#define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_RES0_REG_VALUE_SHIFT (0U)\r
+#define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name RES1 - Result register 1 */\r
+/*! @{ */\r
+#define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_RES1_REG_VALUE_SHIFT (0U)\r
+#define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name RES2 - Result register 2 */\r
+/*! @{ */\r
+#define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_RES2_REG_VALUE_SHIFT (0U)\r
+#define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name RES3 - Result register 3 */\r
+/*! @{ */\r
+#define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU)\r
+#define CASPER_RES3_REG_VALUE_SHIFT (0U)\r
+#define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASK - Optional mask register */\r
+/*! @{ */\r
+#define CASPER_MASK_MASK_MASK (0xFFFFFFFFU)\r
+#define CASPER_MASK_MASK_SHIFT (0U)\r
+#define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name REMASK - Optional re-mask register */\r
+/*! @{ */\r
+#define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU)\r
+#define CASPER_REMASK_MASK_SHIFT (0U)\r
+#define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name LOCK - Security lock register */\r
+/*! @{ */\r
+#define CASPER_LOCK_LOCK_MASK (0x1U)\r
+#define CASPER_LOCK_LOCK_SHIFT (0U)\r
+/*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock.\r
+ * 0b0..unlock\r
+ * 0b1..Lock to current security level\r
+ */\r
+#define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK)\r
+#define CASPER_LOCK_KEY_MASK (0x1FFF0U)\r
+#define CASPER_LOCK_KEY_SHIFT (4U)\r
+/*! KEY - Must be written as 0x73D to change the register.\r
+ * 0b0011100111101..If set during write, will allow lock or unlock\r
+ */\r
+#define CASPER_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_KEY_SHIFT)) & CASPER_LOCK_KEY_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CASPER_Register_Masks */\r
+\r
+\r
+/* CASPER - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral CASPER base address */\r
+ #define CASPER_BASE (0x500A5000u)\r
+ /** Peripheral CASPER base address */\r
+ #define CASPER_BASE_NS (0x400A5000u)\r
+ /** Peripheral CASPER base pointer */\r
+ #define CASPER ((CASPER_Type *)CASPER_BASE)\r
+ /** Peripheral CASPER base pointer */\r
+ #define CASPER_NS ((CASPER_Type *)CASPER_BASE_NS)\r
+ /** Array initializer of CASPER peripheral base addresses */\r
+ #define CASPER_BASE_ADDRS { CASPER_BASE }\r
+ /** Array initializer of CASPER peripheral base pointers */\r
+ #define CASPER_BASE_PTRS { CASPER }\r
+ /** Array initializer of CASPER peripheral base addresses */\r
+ #define CASPER_BASE_ADDRS_NS { CASPER_BASE_NS }\r
+ /** Array initializer of CASPER peripheral base pointers */\r
+ #define CASPER_BASE_PTRS_NS { CASPER_NS }\r
+#else\r
+ /** Peripheral CASPER base address */\r
+ #define CASPER_BASE (0x400A5000u)\r
+ /** Peripheral CASPER base pointer */\r
+ #define CASPER ((CASPER_Type *)CASPER_BASE)\r
+ /** Array initializer of CASPER peripheral base addresses */\r
+ #define CASPER_BASE_ADDRS { CASPER_BASE }\r
+ /** Array initializer of CASPER peripheral base pointers */\r
+ #define CASPER_BASE_PTRS { CASPER }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CASPER_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CRC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** CRC - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */\r
+ __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */\r
+ union { /* offset: 0x8 */\r
+ __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */\r
+ __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */\r
+ };\r
+} CRC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CRC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CRC_Register_Masks CRC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MODE - CRC mode register */\r
+/*! @{ */\r
+#define CRC_MODE_CRC_POLY_MASK (0x3U)\r
+#define CRC_MODE_CRC_POLY_SHIFT (0U)\r
+#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)\r
+#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)\r
+#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)\r
+#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)\r
+#define CRC_MODE_CMPL_WR_MASK (0x8U)\r
+#define CRC_MODE_CMPL_WR_SHIFT (3U)\r
+#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)\r
+#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)\r
+#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)\r
+#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)\r
+#define CRC_MODE_CMPL_SUM_MASK (0x20U)\r
+#define CRC_MODE_CMPL_SUM_SHIFT (5U)\r
+#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)\r
+/*! @} */\r
+\r
+/*! @name SEED - CRC seed register */\r
+/*! @{ */\r
+#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)\r
+#define CRC_SEED_CRC_SEED_SHIFT (0U)\r
+#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)\r
+/*! @} */\r
+\r
+/*! @name SUM - CRC checksum register */\r
+/*! @{ */\r
+#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)\r
+#define CRC_SUM_CRC_SUM_SHIFT (0U)\r
+#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)\r
+/*! @} */\r
+\r
+/*! @name WR_DATA - CRC data register */\r
+/*! @{ */\r
+#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)\r
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)\r
+#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CRC_Register_Masks */\r
+\r
+\r
+/* CRC - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral CRC_ENGINE base address */\r
+ #define CRC_ENGINE_BASE (0x50095000u)\r
+ /** Peripheral CRC_ENGINE base address */\r
+ #define CRC_ENGINE_BASE_NS (0x40095000u)\r
+ /** Peripheral CRC_ENGINE base pointer */\r
+ #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)\r
+ /** Peripheral CRC_ENGINE base pointer */\r
+ #define CRC_ENGINE_NS ((CRC_Type *)CRC_ENGINE_BASE_NS)\r
+ /** Array initializer of CRC peripheral base addresses */\r
+ #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }\r
+ /** Array initializer of CRC peripheral base pointers */\r
+ #define CRC_BASE_PTRS { CRC_ENGINE }\r
+ /** Array initializer of CRC peripheral base addresses */\r
+ #define CRC_BASE_ADDRS_NS { CRC_ENGINE_BASE_NS }\r
+ /** Array initializer of CRC peripheral base pointers */\r
+ #define CRC_BASE_PTRS_NS { CRC_ENGINE_NS }\r
+#else\r
+ /** Peripheral CRC_ENGINE base address */\r
+ #define CRC_ENGINE_BASE (0x40095000u)\r
+ /** Peripheral CRC_ENGINE base pointer */\r
+ #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)\r
+ /** Array initializer of CRC peripheral base addresses */\r
+ #define CRC_BASE_ADDRS { CRC_ENGINE_BASE }\r
+ /** Array initializer of CRC peripheral base pointers */\r
+ #define CRC_BASE_PTRS { CRC_ENGINE }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CRC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CTIMER Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** CTIMER - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */\r
+ __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */\r
+ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */\r
+ __IO uint32_t PR; /**< Prescale Register, offset: 0xC */\r
+ __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */\r
+ __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */\r
+ __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */\r
+ __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */\r
+ __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */\r
+ __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */\r
+ uint8_t RESERVED_0[48];\r
+ __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */\r
+ __IO uint32_t PWMC; /**< PWM Control Register. This register enables PWM mode for the external match pins., offset: 0x74 */\r
+ __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */\r
+} CTIMER_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- CTIMER Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */\r
+/*! @{ */\r
+#define CTIMER_IR_MR0INT_MASK (0x1U)\r
+#define CTIMER_IR_MR0INT_SHIFT (0U)\r
+#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)\r
+#define CTIMER_IR_MR1INT_MASK (0x2U)\r
+#define CTIMER_IR_MR1INT_SHIFT (1U)\r
+#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)\r
+#define CTIMER_IR_MR2INT_MASK (0x4U)\r
+#define CTIMER_IR_MR2INT_SHIFT (2U)\r
+#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)\r
+#define CTIMER_IR_MR3INT_MASK (0x8U)\r
+#define CTIMER_IR_MR3INT_SHIFT (3U)\r
+#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)\r
+#define CTIMER_IR_CR0INT_MASK (0x10U)\r
+#define CTIMER_IR_CR0INT_SHIFT (4U)\r
+#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)\r
+#define CTIMER_IR_CR1INT_MASK (0x20U)\r
+#define CTIMER_IR_CR1INT_SHIFT (5U)\r
+#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)\r
+#define CTIMER_IR_CR2INT_MASK (0x40U)\r
+#define CTIMER_IR_CR2INT_SHIFT (6U)\r
+#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)\r
+#define CTIMER_IR_CR3INT_MASK (0x80U)\r
+#define CTIMER_IR_CR3INT_SHIFT (7U)\r
+#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */\r
+/*! @{ */\r
+#define CTIMER_TCR_CEN_MASK (0x1U)\r
+#define CTIMER_TCR_CEN_SHIFT (0U)\r
+/*! CEN - Counter enable.\r
+ * 0b0..Disabled.The counters are disabled.\r
+ * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled.\r
+ */\r
+#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)\r
+#define CTIMER_TCR_CRST_MASK (0x2U)\r
+#define CTIMER_TCR_CRST_SHIFT (1U)\r
+/*! CRST - Counter reset.\r
+ * 0b0..Disabled. Do nothing.\r
+ * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.\r
+ */\r
+#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name TC - Timer Counter */\r
+/*! @{ */\r
+#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)\r
+#define CTIMER_TC_TCVAL_SHIFT (0U)\r
+#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PR - Prescale Register */\r
+/*! @{ */\r
+#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)\r
+#define CTIMER_PR_PRVAL_SHIFT (0U)\r
+#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PC - Prescale Counter */\r
+/*! @{ */\r
+#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)\r
+#define CTIMER_PC_PCVAL_SHIFT (0U)\r
+#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCR - Match Control Register */\r
+/*! @{ */\r
+#define CTIMER_MCR_MR0I_MASK (0x1U)\r
+#define CTIMER_MCR_MR0I_SHIFT (0U)\r
+#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)\r
+#define CTIMER_MCR_MR0R_MASK (0x2U)\r
+#define CTIMER_MCR_MR0R_SHIFT (1U)\r
+#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)\r
+#define CTIMER_MCR_MR0S_MASK (0x4U)\r
+#define CTIMER_MCR_MR0S_SHIFT (2U)\r
+#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)\r
+#define CTIMER_MCR_MR1I_MASK (0x8U)\r
+#define CTIMER_MCR_MR1I_SHIFT (3U)\r
+#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)\r
+#define CTIMER_MCR_MR1R_MASK (0x10U)\r
+#define CTIMER_MCR_MR1R_SHIFT (4U)\r
+#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)\r
+#define CTIMER_MCR_MR1S_MASK (0x20U)\r
+#define CTIMER_MCR_MR1S_SHIFT (5U)\r
+#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)\r
+#define CTIMER_MCR_MR2I_MASK (0x40U)\r
+#define CTIMER_MCR_MR2I_SHIFT (6U)\r
+#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)\r
+#define CTIMER_MCR_MR2R_MASK (0x80U)\r
+#define CTIMER_MCR_MR2R_SHIFT (7U)\r
+#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)\r
+#define CTIMER_MCR_MR2S_MASK (0x100U)\r
+#define CTIMER_MCR_MR2S_SHIFT (8U)\r
+#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)\r
+#define CTIMER_MCR_MR3I_MASK (0x200U)\r
+#define CTIMER_MCR_MR3I_SHIFT (9U)\r
+#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)\r
+#define CTIMER_MCR_MR3R_MASK (0x400U)\r
+#define CTIMER_MCR_MR3R_SHIFT (10U)\r
+#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)\r
+#define CTIMER_MCR_MR3S_MASK (0x800U)\r
+#define CTIMER_MCR_MR3S_SHIFT (11U)\r
+#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)\r
+#define CTIMER_MCR_MR0RL_MASK (0x1000000U)\r
+#define CTIMER_MCR_MR0RL_SHIFT (24U)\r
+#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)\r
+#define CTIMER_MCR_MR1RL_MASK (0x2000000U)\r
+#define CTIMER_MCR_MR1RL_SHIFT (25U)\r
+#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)\r
+#define CTIMER_MCR_MR2RL_MASK (0x4000000U)\r
+#define CTIMER_MCR_MR2RL_SHIFT (26U)\r
+#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)\r
+#define CTIMER_MCR_MR3RL_MASK (0x8000000U)\r
+#define CTIMER_MCR_MR3RL_SHIFT (27U)\r
+#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */\r
+/*! @{ */\r
+#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)\r
+#define CTIMER_MR_MATCH_SHIFT (0U)\r
+#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)\r
+/*! @} */\r
+\r
+/* The count of CTIMER_MR */\r
+#define CTIMER_MR_COUNT (4U)\r
+\r
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */\r
+/*! @{ */\r
+#define CTIMER_CCR_CAP0RE_MASK (0x1U)\r
+#define CTIMER_CCR_CAP0RE_SHIFT (0U)\r
+#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)\r
+#define CTIMER_CCR_CAP0FE_MASK (0x2U)\r
+#define CTIMER_CCR_CAP0FE_SHIFT (1U)\r
+#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)\r
+#define CTIMER_CCR_CAP0I_MASK (0x4U)\r
+#define CTIMER_CCR_CAP0I_SHIFT (2U)\r
+#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)\r
+#define CTIMER_CCR_CAP1RE_MASK (0x8U)\r
+#define CTIMER_CCR_CAP1RE_SHIFT (3U)\r
+#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)\r
+#define CTIMER_CCR_CAP1FE_MASK (0x10U)\r
+#define CTIMER_CCR_CAP1FE_SHIFT (4U)\r
+#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)\r
+#define CTIMER_CCR_CAP1I_MASK (0x20U)\r
+#define CTIMER_CCR_CAP1I_SHIFT (5U)\r
+#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)\r
+#define CTIMER_CCR_CAP2RE_MASK (0x40U)\r
+#define CTIMER_CCR_CAP2RE_SHIFT (6U)\r
+#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)\r
+#define CTIMER_CCR_CAP2FE_MASK (0x80U)\r
+#define CTIMER_CCR_CAP2FE_SHIFT (7U)\r
+#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)\r
+#define CTIMER_CCR_CAP2I_MASK (0x100U)\r
+#define CTIMER_CCR_CAP2I_SHIFT (8U)\r
+#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)\r
+#define CTIMER_CCR_CAP3RE_MASK (0x200U)\r
+#define CTIMER_CCR_CAP3RE_SHIFT (9U)\r
+#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)\r
+#define CTIMER_CCR_CAP3FE_MASK (0x400U)\r
+#define CTIMER_CCR_CAP3FE_SHIFT (10U)\r
+#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)\r
+#define CTIMER_CCR_CAP3I_MASK (0x800U)\r
+#define CTIMER_CCR_CAP3I_SHIFT (11U)\r
+#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)\r
+/*! @} */\r
+\r
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */\r
+/*! @{ */\r
+#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)\r
+#define CTIMER_CR_CAP_SHIFT (0U)\r
+#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)\r
+/*! @} */\r
+\r
+/* The count of CTIMER_CR */\r
+#define CTIMER_CR_COUNT (4U)\r
+\r
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */\r
+/*! @{ */\r
+#define CTIMER_EMR_EM0_MASK (0x1U)\r
+#define CTIMER_EMR_EM0_SHIFT (0U)\r
+#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)\r
+#define CTIMER_EMR_EM1_MASK (0x2U)\r
+#define CTIMER_EMR_EM1_SHIFT (1U)\r
+#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)\r
+#define CTIMER_EMR_EM2_MASK (0x4U)\r
+#define CTIMER_EMR_EM2_SHIFT (2U)\r
+#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)\r
+#define CTIMER_EMR_EM3_MASK (0x8U)\r
+#define CTIMER_EMR_EM3_SHIFT (3U)\r
+#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)\r
+#define CTIMER_EMR_EMC0_MASK (0x30U)\r
+#define CTIMER_EMR_EMC0_SHIFT (4U)\r
+/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)\r
+#define CTIMER_EMR_EMC1_MASK (0xC0U)\r
+#define CTIMER_EMR_EMC1_SHIFT (6U)\r
+/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)\r
+#define CTIMER_EMR_EMC2_MASK (0x300U)\r
+#define CTIMER_EMR_EMC2_SHIFT (8U)\r
+/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)\r
+#define CTIMER_EMR_EMC3_MASK (0xC00U)\r
+#define CTIMER_EMR_EMC3_SHIFT (10U)\r
+/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3.\r
+ * 0b00..Do Nothing.\r
+ * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out).\r
+ * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out).\r
+ * 0b11..Toggle. Toggle the corresponding External Match bit/output.\r
+ */\r
+#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */\r
+/*! @{ */\r
+#define CTIMER_CTCR_CTMODE_MASK (0x3U)\r
+#define CTIMER_CTCR_CTMODE_SHIFT (0U)\r
+/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.\r
+ * 0b00..Timer Mode. Incremented every rising APB bus clock edge.\r
+ * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2.\r
+ * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2.\r
+ * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2.\r
+ */\r
+#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)\r
+#define CTIMER_CTCR_CINSEL_MASK (0xCU)\r
+#define CTIMER_CTCR_CINSEL_SHIFT (2U)\r
+/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.\r
+ * 0b00..Channel 0. CAPn.0 for CTIMERn\r
+ * 0b01..Channel 1. CAPn.1 for CTIMERn\r
+ * 0b10..Channel 2. CAPn.2 for CTIMERn\r
+ * 0b11..Channel 3. CAPn.3 for CTIMERn\r
+ */\r
+#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)\r
+#define CTIMER_CTCR_ENCC_MASK (0x10U)\r
+#define CTIMER_CTCR_ENCC_SHIFT (4U)\r
+#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)\r
+#define CTIMER_CTCR_SELCC_MASK (0xE0U)\r
+#define CTIMER_CTCR_SELCC_SHIFT (5U)\r
+/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved.\r
+ * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set).\r
+ * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set).\r
+ * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set).\r
+ * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set).\r
+ * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set).\r
+ * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set).\r
+ */\r
+#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */\r
+/*! @{ */\r
+#define CTIMER_PWMC_PWMEN0_MASK (0x1U)\r
+#define CTIMER_PWMC_PWMEN0_SHIFT (0U)\r
+/*! PWMEN0 - PWM mode enable for channel0.\r
+ * 0b0..Match. CTIMERn_MAT0 is controlled by EM0.\r
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0.\r
+ */\r
+#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)\r
+#define CTIMER_PWMC_PWMEN1_MASK (0x2U)\r
+#define CTIMER_PWMC_PWMEN1_SHIFT (1U)\r
+/*! PWMEN1 - PWM mode enable for channel1.\r
+ * 0b0..Match. CTIMERn_MAT01 is controlled by EM1.\r
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1.\r
+ */\r
+#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)\r
+#define CTIMER_PWMC_PWMEN2_MASK (0x4U)\r
+#define CTIMER_PWMC_PWMEN2_SHIFT (2U)\r
+/*! PWMEN2 - PWM mode enable for channel2.\r
+ * 0b0..Match. CTIMERn_MAT2 is controlled by EM2.\r
+ * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2.\r
+ */\r
+#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)\r
+#define CTIMER_PWMC_PWMEN3_MASK (0x8U)\r
+#define CTIMER_PWMC_PWMEN3_SHIFT (3U)\r
+/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle.\r
+ * 0b0..Match. CTIMERn_MAT3 is controlled by EM3.\r
+ * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3.\r
+ */\r
+#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSR - Match Shadow Register */\r
+/*! @{ */\r
+#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)\r
+#define CTIMER_MSR_SHADOWW_SHIFT (0U)\r
+#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)\r
+/*! @} */\r
+\r
+/* The count of CTIMER_MSR */\r
+#define CTIMER_MSR_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CTIMER_Register_Masks */\r
+\r
+\r
+/* CTIMER - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral CTIMER0 base address */\r
+ #define CTIMER0_BASE (0x50008000u)\r
+ /** Peripheral CTIMER0 base address */\r
+ #define CTIMER0_BASE_NS (0x40008000u)\r
+ /** Peripheral CTIMER0 base pointer */\r
+ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)\r
+ /** Peripheral CTIMER0 base pointer */\r
+ #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS)\r
+ /** Peripheral CTIMER1 base address */\r
+ #define CTIMER1_BASE (0x50009000u)\r
+ /** Peripheral CTIMER1 base address */\r
+ #define CTIMER1_BASE_NS (0x40009000u)\r
+ /** Peripheral CTIMER1 base pointer */\r
+ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)\r
+ /** Peripheral CTIMER1 base pointer */\r
+ #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS)\r
+ /** Peripheral CTIMER2 base address */\r
+ #define CTIMER2_BASE (0x50028000u)\r
+ /** Peripheral CTIMER2 base address */\r
+ #define CTIMER2_BASE_NS (0x40028000u)\r
+ /** Peripheral CTIMER2 base pointer */\r
+ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)\r
+ /** Peripheral CTIMER2 base pointer */\r
+ #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS)\r
+ /** Peripheral CTIMER3 base address */\r
+ #define CTIMER3_BASE (0x50029000u)\r
+ /** Peripheral CTIMER3 base address */\r
+ #define CTIMER3_BASE_NS (0x40029000u)\r
+ /** Peripheral CTIMER3 base pointer */\r
+ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)\r
+ /** Peripheral CTIMER3 base pointer */\r
+ #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS)\r
+ /** Peripheral CTIMER4 base address */\r
+ #define CTIMER4_BASE (0x5002A000u)\r
+ /** Peripheral CTIMER4 base address */\r
+ #define CTIMER4_BASE_NS (0x4002A000u)\r
+ /** Peripheral CTIMER4 base pointer */\r
+ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)\r
+ /** Peripheral CTIMER4 base pointer */\r
+ #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS)\r
+ /** Array initializer of CTIMER peripheral base addresses */\r
+ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }\r
+ /** Array initializer of CTIMER peripheral base pointers */\r
+ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }\r
+ /** Array initializer of CTIMER peripheral base addresses */\r
+ #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS }\r
+ /** Array initializer of CTIMER peripheral base pointers */\r
+ #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS }\r
+#else\r
+ /** Peripheral CTIMER0 base address */\r
+ #define CTIMER0_BASE (0x40008000u)\r
+ /** Peripheral CTIMER0 base pointer */\r
+ #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)\r
+ /** Peripheral CTIMER1 base address */\r
+ #define CTIMER1_BASE (0x40009000u)\r
+ /** Peripheral CTIMER1 base pointer */\r
+ #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)\r
+ /** Peripheral CTIMER2 base address */\r
+ #define CTIMER2_BASE (0x40028000u)\r
+ /** Peripheral CTIMER2 base pointer */\r
+ #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)\r
+ /** Peripheral CTIMER3 base address */\r
+ #define CTIMER3_BASE (0x40029000u)\r
+ /** Peripheral CTIMER3 base pointer */\r
+ #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)\r
+ /** Peripheral CTIMER4 base address */\r
+ #define CTIMER4_BASE (0x4002A000u)\r
+ /** Peripheral CTIMER4 base pointer */\r
+ #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)\r
+ /** Array initializer of CTIMER peripheral base addresses */\r
+ #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }\r
+ /** Array initializer of CTIMER peripheral base pointers */\r
+ #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }\r
+#endif\r
+/** Interrupt vectors for the CTIMER peripheral type */\r
+#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group CTIMER_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DGBMAILBOX Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** DGBMAILBOX - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */\r
+ __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */\r
+ __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */\r
+ uint8_t RESERVED_0[240];\r
+ __I uint32_t ID; /**< Identification register, offset: 0xFC */\r
+} DGBMAILBOX_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DGBMAILBOX Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CSW - CRC mode register */\r
+/*! @{ */\r
+#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U)\r
+#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U)\r
+#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK)\r
+#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U)\r
+#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U)\r
+#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK)\r
+#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U)\r
+#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U)\r
+#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK)\r
+#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U)\r
+#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U)\r
+#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK)\r
+#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U)\r
+#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U)\r
+#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK)\r
+#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U)\r
+#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U)\r
+#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name REQUEST - CRC seed register */\r
+/*! @{ */\r
+#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU)\r
+#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U)\r
+#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name RETURN - Return value from ROM. */\r
+/*! @{ */\r
+#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU)\r
+#define DGBMAILBOX_RETURN_RET_SHIFT (0U)\r
+#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Identification register */\r
+/*! @{ */\r
+#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU)\r
+#define DGBMAILBOX_ID_ID_SHIFT (0U)\r
+#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DGBMAILBOX_Register_Masks */\r
+\r
+\r
+/* DGBMAILBOX - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral DGBMAILBOX base address */\r
+ #define DGBMAILBOX_BASE (0x5009C000u)\r
+ /** Peripheral DGBMAILBOX base address */\r
+ #define DGBMAILBOX_BASE_NS (0x4009C000u)\r
+ /** Peripheral DGBMAILBOX base pointer */\r
+ #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE)\r
+ /** Peripheral DGBMAILBOX base pointer */\r
+ #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS)\r
+ /** Array initializer of DGBMAILBOX peripheral base addresses */\r
+ #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE }\r
+ /** Array initializer of DGBMAILBOX peripheral base pointers */\r
+ #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX }\r
+ /** Array initializer of DGBMAILBOX peripheral base addresses */\r
+ #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS }\r
+ /** Array initializer of DGBMAILBOX peripheral base pointers */\r
+ #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS }\r
+#else\r
+ /** Peripheral DGBMAILBOX base address */\r
+ #define DGBMAILBOX_BASE (0x4009C000u)\r
+ /** Peripheral DGBMAILBOX base pointer */\r
+ #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE)\r
+ /** Array initializer of DGBMAILBOX peripheral base addresses */\r
+ #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE }\r
+ /** Array initializer of DGBMAILBOX peripheral base pointers */\r
+ #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DMA Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** DMA - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */\r
+ __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */\r
+ __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */\r
+ uint8_t RESERVED_0[20];\r
+ struct { /* offset: 0x20, array step: 0x5C */\r
+ __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */\r
+ uint8_t RESERVED_0[4];\r
+ __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */\r
+ uint8_t RESERVED_1[4];\r
+ __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */\r
+ uint8_t RESERVED_2[4];\r
+ __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */\r
+ uint8_t RESERVED_4[4];\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */\r
+ uint8_t RESERVED_5[4];\r
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */\r
+ uint8_t RESERVED_6[4];\r
+ __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */\r
+ uint8_t RESERVED_7[4];\r
+ __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */\r
+ uint8_t RESERVED_8[4];\r
+ __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */\r
+ uint8_t RESERVED_9[4];\r
+ __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */\r
+ uint8_t RESERVED_10[4];\r
+ __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */\r
+ } COMMON[1];\r
+ uint8_t RESERVED_1[900];\r
+ struct { /* offset: 0x400, array step: 0x10 */\r
+ __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */\r
+ __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */\r
+ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */\r
+ uint8_t RESERVED_0[4];\r
+ } CHANNEL[30];\r
+} DMA_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- DMA Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup DMA_Register_Masks DMA Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - DMA control. */\r
+/*! @{ */\r
+#define DMA_CTRL_ENABLE_MASK (0x1U)\r
+#define DMA_CTRL_ENABLE_SHIFT (0U)\r
+/*! ENABLE - DMA controller master enable.\r
+ * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled.\r
+ * 0b1..Enabled. The DMA controller is enabled.\r
+ */\r
+#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt status. */\r
+/*! @{ */\r
+#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)\r
+#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)\r
+/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending.\r
+ * 0b0..Not pending. No enabled interrupts are pending.\r
+ * 0b1..Pending. At least one enabled interrupt is pending.\r
+ */\r
+#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)\r
+#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)\r
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)\r
+/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending.\r
+ * 0b0..Not pending. No error interrupts are pending.\r
+ * 0b1..Pending. At least one error interrupt is pending.\r
+ */\r
+#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */\r
+/*! @{ */\r
+#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)\r
+#define DMA_SRAMBASE_OFFSET_SHIFT (9U)\r
+#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)\r
+/*! @} */\r
+\r
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)\r
+#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ENABLESET */\r
+#define DMA_COMMON_ENABLESET_COUNT (1U)\r
+\r
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)\r
+#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ENABLECLR */\r
+#define DMA_COMMON_ENABLECLR_COUNT (1U)\r
+\r
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)\r
+#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ACTIVE */\r
+#define DMA_COMMON_ACTIVE_COUNT (1U)\r
+\r
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_BUSY_BSY_SHIFT (0U)\r
+#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_BUSY */\r
+#define DMA_COMMON_BUSY_COUNT (1U)\r
+\r
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)\r
+#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ERRINT */\r
+#define DMA_COMMON_ERRINT_COUNT (1U)\r
+\r
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)\r
+#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTENSET */\r
+#define DMA_COMMON_INTENSET_COUNT (1U)\r
+\r
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)\r
+#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTENCLR */\r
+#define DMA_COMMON_INTENCLR_COUNT (1U)\r
+\r
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTA_IA_SHIFT (0U)\r
+#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTA */\r
+#define DMA_COMMON_INTA_COUNT (1U)\r
+\r
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_INTB_IB_SHIFT (0U)\r
+#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_INTB */\r
+#define DMA_COMMON_INTB_COUNT (1U)\r
+\r
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_SETVALID_SV_SHIFT (0U)\r
+#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_SETVALID */\r
+#define DMA_COMMON_SETVALID_COUNT (1U)\r
+\r
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)\r
+#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_SETTRIG */\r
+#define DMA_COMMON_SETTRIG_COUNT (1U)\r
+\r
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */\r
+/*! @{ */\r
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)\r
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)\r
+#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_COMMON_ABORT */\r
+#define DMA_COMMON_ABORT_COUNT (1U)\r
+\r
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */\r
+/*! @{ */\r
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)\r
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)\r
+/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller.\r
+ * 0b0..Disabled. Peripheral DMA requests are disabled.\r
+ * 0b1..Enabled. Peripheral DMA requests are enabled.\r
+ */\r
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)\r
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)\r
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)\r
+/*! HWTRIGEN - Hardware Triggering Enable for this channel.\r
+ * 0b0..Disabled. Hardware triggering is not used.\r
+ * 0b1..Enabled. Use hardware triggering.\r
+ */\r
+#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)\r
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)\r
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)\r
+/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel.\r
+ * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE.\r
+ * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE.\r
+ */\r
+#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)\r
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)\r
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)\r
+/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered.\r
+ * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger.\r
+ * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed.\r
+ */\r
+#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)\r
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)\r
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)\r
+/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer.\r
+ * 0b0..Single transfer. Hardware trigger causes a single transfer.\r
+ * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete.\r
+ */\r
+#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)\r
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)\r
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)\r
+#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)\r
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)\r
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)\r
+/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst.\r
+ * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel.\r
+ * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel.\r
+ */\r
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)\r
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)\r
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)\r
+/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst.\r
+ * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel.\r
+ * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel.\r
+ */\r
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)\r
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)\r
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)\r
+#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_CHANNEL_CFG */\r
+#define DMA_CHANNEL_CFG_COUNT (30U)\r
+\r
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */\r
+/*! @{ */\r
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)\r
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)\r
+/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.\r
+ * 0b0..No effect. No effect on DMA operation.\r
+ * 0b1..Valid pending.\r
+ */\r
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)\r
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)\r
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)\r
+/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.\r
+ * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.\r
+ * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.\r
+ */\r
+#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_CHANNEL_CTLSTAT */\r
+#define DMA_CHANNEL_CTLSTAT_COUNT (30U)\r
+\r
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */\r
+/*! @{ */\r
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)\r
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)\r
+/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.\r
+ * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting.\r
+ * 0b1..Valid. The current channel descriptor is considered valid.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)\r
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)\r
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)\r
+/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.\r
+ * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted.\r
+ * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)\r
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)\r
+/*! SWTRIG - Software Trigger.\r
+ * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel.\r
+ * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)\r
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)\r
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)\r
+/*! CLRTRIG - Clear Trigger.\r
+ * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started.\r
+ * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)\r
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)\r
+/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.\r
+ * 0b0..No effect.\r
+ * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)\r
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)\r
+/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.\r
+ * 0b0..No effect.\r
+ * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)\r
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)\r
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)\r
+/*! WIDTH - Transfer width used for this DMA channel.\r
+ * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes).\r
+ * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes).\r
+ * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes).\r
+ * 0b11..Reserved. Reserved setting, do not use.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)\r
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)\r
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)\r
+/*! SRCINC - Determines whether the source address is incremented for each DMA transfer.\r
+ * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device.\r
+ * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory.\r
+ * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer.\r
+ * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)\r
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)\r
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)\r
+/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer.\r
+ * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device.\r
+ * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory.\r
+ * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer.\r
+ * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer.\r
+ */\r
+#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)\r
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)\r
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)\r
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)\r
+/*! @} */\r
+\r
+/* The count of DMA_CHANNEL_XFERCFG */\r
+#define DMA_CHANNEL_XFERCFG_COUNT (30U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DMA_Register_Masks */\r
+\r
+\r
+/* DMA - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral DMA0 base address */\r
+ #define DMA0_BASE (0x50082000u)\r
+ /** Peripheral DMA0 base address */\r
+ #define DMA0_BASE_NS (0x40082000u)\r
+ /** Peripheral DMA0 base pointer */\r
+ #define DMA0 ((DMA_Type *)DMA0_BASE)\r
+ /** Peripheral DMA0 base pointer */\r
+ #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS)\r
+ /** Peripheral DMA1 base address */\r
+ #define DMA1_BASE (0x500A7000u)\r
+ /** Peripheral DMA1 base address */\r
+ #define DMA1_BASE_NS (0x400A7000u)\r
+ /** Peripheral DMA1 base pointer */\r
+ #define DMA1 ((DMA_Type *)DMA1_BASE)\r
+ /** Peripheral DMA1 base pointer */\r
+ #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS)\r
+ /** Array initializer of DMA peripheral base addresses */\r
+ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }\r
+ /** Array initializer of DMA peripheral base pointers */\r
+ #define DMA_BASE_PTRS { DMA0, DMA1 }\r
+ /** Array initializer of DMA peripheral base addresses */\r
+ #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS }\r
+ /** Array initializer of DMA peripheral base pointers */\r
+ #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS }\r
+#else\r
+ /** Peripheral DMA0 base address */\r
+ #define DMA0_BASE (0x40082000u)\r
+ /** Peripheral DMA0 base pointer */\r
+ #define DMA0 ((DMA_Type *)DMA0_BASE)\r
+ /** Peripheral DMA1 base address */\r
+ #define DMA1_BASE (0x400A7000u)\r
+ /** Peripheral DMA1 base pointer */\r
+ #define DMA1 ((DMA_Type *)DMA1_BASE)\r
+ /** Array initializer of DMA peripheral base addresses */\r
+ #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE }\r
+ /** Array initializer of DMA peripheral base pointers */\r
+ #define DMA_BASE_PTRS { DMA0, DMA1 }\r
+#endif\r
+/** Interrupt vectors for the DMA peripheral type */\r
+#define DMA_IRQS { DMA0_IRQn, DMA1_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group DMA_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_Peripheral_Access_Layer FLASH Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** FLASH - Register Layout Typedef */\r
+typedef struct {\r
+ __O uint32_t CMD; /**< command register, offset: 0x0 */\r
+ __O uint32_t EVENT; /**< event register, offset: 0x4 */\r
+ __IO uint32_t BURST; /**< read burst register, offset: 0x8 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */\r
+ __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */\r
+ uint8_t RESERVED_1[104];\r
+ __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */\r
+ uint8_t RESERVED_2[3896];\r
+ __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */\r
+ __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */\r
+ __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */\r
+ __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */\r
+ __O uint32_t INT_CLR_STATUS; /**< Clear interrupt status bits, offset: 0xFE8 */\r
+ __O uint32_t INT_SET_STATUS; /**< Set interrupt status bits, offset: 0xFEC */\r
+ uint8_t RESERVED_3[12];\r
+ __I uint32_t MODULE_ID; /**< Controller+Memory module identification, offset: 0xFFC */\r
+} FLASH_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_Register_Masks FLASH Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CMD - command register */\r
+/*! @{ */\r
+#define FLASH_CMD_CMD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMD_CMD_SHIFT (0U)\r
+#define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVENT - event register */\r
+/*! @{ */\r
+#define FLASH_EVENT_RST_MASK (0x1U)\r
+#define FLASH_EVENT_RST_SHIFT (0U)\r
+#define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK)\r
+#define FLASH_EVENT_WAKEUP_MASK (0x2U)\r
+#define FLASH_EVENT_WAKEUP_SHIFT (1U)\r
+#define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK)\r
+#define FLASH_EVENT_ABORT_MASK (0x4U)\r
+#define FLASH_EVENT_ABORT_SHIFT (2U)\r
+#define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK)\r
+/*! @} */\r
+\r
+/*! @name BURST - read burst register */\r
+/*! @{ */\r
+#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU)\r
+#define FLASH_BURST_XOR_MASK_SHIFT (0U)\r
+#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK)\r
+#define FLASH_BURST_DESCR1_MASK (0xF00000U)\r
+#define FLASH_BURST_DESCR1_SHIFT (20U)\r
+#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK)\r
+#define FLASH_BURST_DESCR2_MASK (0xF000000U)\r
+#define FLASH_BURST_DESCR2_SHIFT (24U)\r
+#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK)\r
+#define FLASH_BURST_DESCR3_MASK (0xF0000000U)\r
+#define FLASH_BURST_DESCR3_SHIFT (28U)\r
+#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK)\r
+/*! @} */\r
+\r
+/*! @name STARTA - start (or only) address for next flash command */\r
+/*! @{ */\r
+#define FLASH_STARTA_STARTA_MASK (0x3FFFFU)\r
+#define FLASH_STARTA_STARTA_SHIFT (0U)\r
+#define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK)\r
+/*! @} */\r
+\r
+/*! @name STOPA - end address for next flash command, if command operates on address ranges */\r
+/*! @{ */\r
+#define FLASH_STOPA_STOPA_MASK (0x3FFFFU)\r
+#define FLASH_STOPA_STOPA_SHIFT (0U)\r
+#define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */\r
+/*! @{ */\r
+#define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU)\r
+#define FLASH_DATAW_DATAW_SHIFT (0U)\r
+#define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_DATAW */\r
+#define FLASH_DATAW_COUNT (8U)\r
+\r
+/*! @name INT_CLR_ENABLE - Clear interrupt enable bits */\r
+/*! @{ */\r
+#define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U)\r
+#define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U)\r
+#define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK)\r
+#define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U)\r
+#define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U)\r
+#define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK)\r
+#define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U)\r
+#define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U)\r
+#define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK)\r
+#define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U)\r
+#define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U)\r
+#define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_SET_ENABLE - Set interrupt enable bits */\r
+/*! @{ */\r
+#define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U)\r
+#define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U)\r
+#define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK)\r
+#define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U)\r
+#define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U)\r
+#define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK)\r
+#define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U)\r
+#define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U)\r
+#define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK)\r
+#define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U)\r
+#define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U)\r
+#define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_STATUS - Interrupt status bits */\r
+/*! @{ */\r
+#define FLASH_INT_STATUS_FAIL_MASK (0x1U)\r
+#define FLASH_INT_STATUS_FAIL_SHIFT (0U)\r
+#define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK)\r
+#define FLASH_INT_STATUS_ERR_MASK (0x2U)\r
+#define FLASH_INT_STATUS_ERR_SHIFT (1U)\r
+#define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK)\r
+#define FLASH_INT_STATUS_DONE_MASK (0x4U)\r
+#define FLASH_INT_STATUS_DONE_SHIFT (2U)\r
+#define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK)\r
+#define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U)\r
+#define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U)\r
+#define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_ENABLE - Interrupt enable bits */\r
+/*! @{ */\r
+#define FLASH_INT_ENABLE_FAIL_MASK (0x1U)\r
+#define FLASH_INT_ENABLE_FAIL_SHIFT (0U)\r
+#define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK)\r
+#define FLASH_INT_ENABLE_ERR_MASK (0x2U)\r
+#define FLASH_INT_ENABLE_ERR_SHIFT (1U)\r
+#define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK)\r
+#define FLASH_INT_ENABLE_DONE_MASK (0x4U)\r
+#define FLASH_INT_ENABLE_DONE_SHIFT (2U)\r
+#define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK)\r
+#define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U)\r
+#define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U)\r
+#define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_CLR_STATUS - Clear interrupt status bits */\r
+/*! @{ */\r
+#define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U)\r
+#define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U)\r
+#define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK)\r
+#define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U)\r
+#define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U)\r
+#define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK)\r
+#define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U)\r
+#define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U)\r
+#define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK)\r
+#define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U)\r
+#define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U)\r
+#define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_SET_STATUS - Set interrupt status bits */\r
+/*! @{ */\r
+#define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U)\r
+#define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U)\r
+#define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK)\r
+#define FLASH_INT_SET_STATUS_ERR_MASK (0x2U)\r
+#define FLASH_INT_SET_STATUS_ERR_SHIFT (1U)\r
+#define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK)\r
+#define FLASH_INT_SET_STATUS_DONE_MASK (0x4U)\r
+#define FLASH_INT_SET_STATUS_DONE_SHIFT (2U)\r
+#define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK)\r
+#define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U)\r
+#define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U)\r
+#define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MODULE_ID - Controller+Memory module identification */\r
+/*! @{ */\r
+#define FLASH_MODULE_ID_APERTURE_MASK (0xFFU)\r
+#define FLASH_MODULE_ID_APERTURE_SHIFT (0U)\r
+#define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK)\r
+#define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U)\r
+#define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U)\r
+#define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK)\r
+#define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U)\r
+#define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U)\r
+#define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK)\r
+#define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U)\r
+#define FLASH_MODULE_ID_ID_SHIFT (16U)\r
+#define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_Register_Masks */\r
+\r
+\r
+/* FLASH - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral FLASH base address */\r
+ #define FLASH_BASE (0x50034000u)\r
+ /** Peripheral FLASH base address */\r
+ #define FLASH_BASE_NS (0x40034000u)\r
+ /** Peripheral FLASH base pointer */\r
+ #define FLASH ((FLASH_Type *)FLASH_BASE)\r
+ /** Peripheral FLASH base pointer */\r
+ #define FLASH_NS ((FLASH_Type *)FLASH_BASE_NS)\r
+ /** Array initializer of FLASH peripheral base addresses */\r
+ #define FLASH_BASE_ADDRS { FLASH_BASE }\r
+ /** Array initializer of FLASH peripheral base pointers */\r
+ #define FLASH_BASE_PTRS { FLASH }\r
+ /** Array initializer of FLASH peripheral base addresses */\r
+ #define FLASH_BASE_ADDRS_NS { FLASH_BASE_NS }\r
+ /** Array initializer of FLASH peripheral base pointers */\r
+ #define FLASH_BASE_PTRS_NS { FLASH_NS }\r
+#else\r
+ /** Peripheral FLASH base address */\r
+ #define FLASH_BASE (0x40034000u)\r
+ /** Peripheral FLASH base pointer */\r
+ #define FLASH ((FLASH_Type *)FLASH_BASE)\r
+ /** Array initializer of FLASH peripheral base addresses */\r
+ #define FLASH_BASE_ADDRS { FLASH_BASE }\r
+ /** Array initializer of FLASH peripheral base pointers */\r
+ #define FLASH_BASE_PTRS { FLASH }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH_CFPA Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_CFPA_Peripheral_Access_Layer FLASH_CFPA Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** FLASH_CFPA - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t HEADER; /**< ., offset: 0x0 */\r
+ __IO uint32_t VERSION; /**< ., offset: 0x4 */\r
+ __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */\r
+ __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */\r
+ __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */\r
+ __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */\r
+ __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */\r
+ __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */\r
+ __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */\r
+ __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */\r
+ union { /* offset: 0x30 */\r
+ __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */\r
+ struct { /* offset: 0x30 */\r
+ __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */\r
+ __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */\r
+ __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */\r
+ } PRINCE_REGION0_IV_CODE_CORE;\r
+ };\r
+ union { /* offset: 0x68 */\r
+ __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */\r
+ struct { /* offset: 0x68 */\r
+ __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */\r
+ __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */\r
+ __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */\r
+ } PRINCE_REGION1_IV_CODE_CORE;\r
+ };\r
+ union { /* offset: 0xA0 */\r
+ __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */\r
+ struct { /* offset: 0xA0 */\r
+ __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */\r
+ __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */\r
+ __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */\r
+ } PRINCE_REGION2_IV_CODE_CORE;\r
+ };\r
+ uint8_t RESERVED_1[40];\r
+ __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */\r
+ __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */\r
+} FLASH_CFPA_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH_CFPA Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_CFPA_Register_Masks FLASH_CFPA Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name HEADER - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_HEADER_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name VERSION - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_VERSION_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */\r
+/*! @{ */\r
+#define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */\r
+/*! @{ */\r
+#define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */\r
+/*! @{ */\r
+#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name ROTKH_REVOKE - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U)\r
+#define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name VENDOR_USAGE - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU)\r
+#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U)\r
+#define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK)\r
+#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U)\r
+#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U)\r
+#define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */\r
+/*! @{ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U)\r
+/*! NIDEN - Non Secure non-invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U)\r
+/*! DBGEN - Non Secure debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)\r
+/*! SPNIDEN - Secure non-invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U)\r
+/*! SPIDEN - Secure invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U)\r
+/*! TAPEN - JTAG TAP enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U)\r
+/*! MCM33_DBGEN - Micro CM33 invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)\r
+/*! ISP_CMD_EN - ISP Boot Command enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)\r
+/*! FA_CMD_EN - FA Command enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)\r
+/*! ME_CMD_EN - Flash Mass Erase Command enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U)\r
+/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */\r
+/*! @{ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U)\r
+/*! NIDEN - Non Secure non-invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U)\r
+/*! DBGEN - Non Secure debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)\r
+/*! SPNIDEN - Secure non-invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)\r
+/*! SPIDEN - Secure invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U)\r
+/*! TAPEN - JTAG TAP fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U)\r
+/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)\r
+/*! ISP_CMD_EN - ISP Boot Command fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)\r
+/*! FA_CMD_EN - FA Command fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)\r
+/*! ME_CMD_EN - Flash Mass Erase Command fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U)\r
+/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)\r
+#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */\r
+/*! @{ */\r
+#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */\r
+/*! @{ */\r
+#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION0_IV_CODE - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U)\r
+\r
+/*! @name PRINCE_REGION0_IV_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION0_IV_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION0_IV_BODY - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */\r
+#define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U)\r
+\r
+/*! @name PRINCE_REGION1_IV_CODE - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U)\r
+\r
+/*! @name PRINCE_REGION1_IV_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION1_IV_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION1_IV_BODY - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */\r
+#define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U)\r
+\r
+/*! @name PRINCE_REGION2_IV_CODE - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U)\r
+\r
+/*! @name PRINCE_REGION2_IV_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION2_IV_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION2_IV_BODY - . */\r
+/*! @{ */\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_PRINCE_REGION2_IV_BODY */\r
+#define FLASH_CFPA_PRINCE_REGION2_IV_BODY_COUNT (12U)\r
+\r
+/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */\r
+/*! @{ */\r
+#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_CUSTOMER_DEFINED */\r
+#define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U)\r
+\r
+/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */\r
+/*! @{ */\r
+#define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U)\r
+#define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CFPA_SHA256_DIGEST */\r
+#define FLASH_CFPA_SHA256_DIGEST_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_CFPA_Register_Masks */\r
+\r
+\r
+/* FLASH_CFPA - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral FLASH_CFPA0 base address */\r
+ #define FLASH_CFPA0_BASE (0x1009E000u)\r
+ /** Peripheral FLASH_CFPA0 base address */\r
+ #define FLASH_CFPA0_BASE_NS (0x9E000u)\r
+ /** Peripheral FLASH_CFPA0 base pointer */\r
+ #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)\r
+ /** Peripheral FLASH_CFPA0 base pointer */\r
+ #define FLASH_CFPA0_NS ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE_NS)\r
+ /** Peripheral FLASH_CFPA1 base address */\r
+ #define FLASH_CFPA1_BASE (0x1009E200u)\r
+ /** Peripheral FLASH_CFPA1 base address */\r
+ #define FLASH_CFPA1_BASE_NS (0x9E200u)\r
+ /** Peripheral FLASH_CFPA1 base pointer */\r
+ #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)\r
+ /** Peripheral FLASH_CFPA1 base pointer */\r
+ #define FLASH_CFPA1_NS ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE_NS)\r
+ /** Peripheral FLASH_CFPA_SCRATCH base address */\r
+ #define FLASH_CFPA_SCRATCH_BASE (0x1009DE00u)\r
+ /** Peripheral FLASH_CFPA_SCRATCH base address */\r
+ #define FLASH_CFPA_SCRATCH_BASE_NS (0x9DE00u)\r
+ /** Peripheral FLASH_CFPA_SCRATCH base pointer */\r
+ #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)\r
+ /** Peripheral FLASH_CFPA_SCRATCH base pointer */\r
+ #define FLASH_CFPA_SCRATCH_NS ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE_NS)\r
+ /** Array initializer of FLASH_CFPA peripheral base addresses */\r
+ #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }\r
+ /** Array initializer of FLASH_CFPA peripheral base pointers */\r
+ #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }\r
+ /** Array initializer of FLASH_CFPA peripheral base addresses */\r
+ #define FLASH_CFPA_BASE_ADDRS_NS { FLASH_CFPA0_BASE_NS, FLASH_CFPA1_BASE_NS, FLASH_CFPA_SCRATCH_BASE_NS }\r
+ /** Array initializer of FLASH_CFPA peripheral base pointers */\r
+ #define FLASH_CFPA_BASE_PTRS_NS { FLASH_CFPA0_NS, FLASH_CFPA1_NS, FLASH_CFPA_SCRATCH_NS }\r
+#else\r
+ /** Peripheral FLASH_CFPA0 base address */\r
+ #define FLASH_CFPA0_BASE (0x9E000u)\r
+ /** Peripheral FLASH_CFPA0 base pointer */\r
+ #define FLASH_CFPA0 ((FLASH_CFPA_Type *)FLASH_CFPA0_BASE)\r
+ /** Peripheral FLASH_CFPA1 base address */\r
+ #define FLASH_CFPA1_BASE (0x9E200u)\r
+ /** Peripheral FLASH_CFPA1 base pointer */\r
+ #define FLASH_CFPA1 ((FLASH_CFPA_Type *)FLASH_CFPA1_BASE)\r
+ /** Peripheral FLASH_CFPA_SCRATCH base address */\r
+ #define FLASH_CFPA_SCRATCH_BASE (0x9DE00u)\r
+ /** Peripheral FLASH_CFPA_SCRATCH base pointer */\r
+ #define FLASH_CFPA_SCRATCH ((FLASH_CFPA_Type *)FLASH_CFPA_SCRATCH_BASE)\r
+ /** Array initializer of FLASH_CFPA peripheral base addresses */\r
+ #define FLASH_CFPA_BASE_ADDRS { FLASH_CFPA0_BASE, FLASH_CFPA1_BASE, FLASH_CFPA_SCRATCH_BASE }\r
+ /** Array initializer of FLASH_CFPA peripheral base pointers */\r
+ #define FLASH_CFPA_BASE_PTRS { FLASH_CFPA0, FLASH_CFPA1, FLASH_CFPA_SCRATCH }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_CFPA_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH_CMPA Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_CMPA_Peripheral_Access_Layer FLASH_CMPA Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** FLASH_CMPA - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */\r
+ __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */\r
+ __IO uint32_t USB_ID; /**< ., offset: 0x8 */\r
+ __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */\r
+ __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */\r
+ __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */\r
+ __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */\r
+ __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */\r
+ __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */\r
+ __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */\r
+ __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */\r
+ __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */\r
+ uint8_t RESERVED_0[32];\r
+ __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */\r
+ uint8_t RESERVED_1[144];\r
+ __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */\r
+ __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */\r
+} FLASH_CMPA_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH_CMPA Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_CMPA_Register_Masks FLASH_CMPA Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name BOOT_CFG - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U)\r
+#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U)\r
+/*! DEFAULT_ISP_MODE - Default ISP mode:\r
+ * 0b000..Auto ISP\r
+ * 0b001..USB_HID_MSC\r
+ * 0b010..SPI Slave ISP\r
+ * 0b011..I2C Slave ISP\r
+ * 0b111..Disable ISP fall through\r
+ */\r
+#define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK)\r
+#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U)\r
+#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U)\r
+/*! BOOT_SPEED - Core clock:\r
+ * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE\r
+ * 0b01..48MHz FRO\r
+ * 0b10..96MHz FRO\r
+ */\r
+#define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK)\r
+#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U)\r
+#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U)\r
+#define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name SPI_FLASH_CFG - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB_ID - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU)\r
+#define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U)\r
+#define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK)\r
+#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U)\r
+#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U)\r
+#define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIO_CFG - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name DCFG_CC_SOCU_PIN - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U)\r
+/*! NIDEN - Non Secure non-invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U)\r
+/*! DBGEN - Non Secure debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U)\r
+/*! SPNIDEN - Secure non-invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U)\r
+/*! SPIDEN - Secure invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U)\r
+/*! TAPEN - JTAG TAP enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U)\r
+/*! MCM33_DBGEN - Micro CM33 invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U)\r
+/*! ISP_CMD_EN - ISP Boot Command enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U)\r
+/*! FA_CMD_EN - FA Command enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U)\r
+/*! ME_CMD_EN - Flash Mass Erase Command enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U)\r
+/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable\r
+ * 0b0..Use DAP to enable\r
+ * 0b1..Fixed state\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DCFG_CC_SOCU_DFLT - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U)\r
+/*! NIDEN - Non Secure non-invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U)\r
+/*! DBGEN - Non Secure debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U)\r
+/*! SPNIDEN - Secure non-invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U)\r
+/*! SPIDEN - Secure invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U)\r
+/*! TAPEN - JTAG TAP fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U)\r
+/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U)\r
+/*! ISP_CMD_EN - ISP Boot Command fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U)\r
+/*! FA_CMD_EN - FA Command fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U)\r
+/*! ME_CMD_EN - Flash Mass Erase Command fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U)\r
+/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state\r
+ * 0b0..Disable\r
+ * 0b1..Enable\r
+ */\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U)\r
+#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DAP_VENDOR_USAGE_FIXED - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U)\r
+#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U)\r
+#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SECURE_BOOT_CFG - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U)\r
+#define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_BASE_ADDR - . */\r
+/*! @{ */\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U)\r
+#define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_SR_0 - Region 0, sub-region enable */\r
+/*! @{ */\r
+#define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_SR_1 - Region 1, sub-region enable */\r
+/*! @{ */\r
+#define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_SR_2 - Region 2, sub-region enable */\r
+/*! @{ */\r
+#define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */\r
+/*! @{ */\r
+#define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CMPA_ROTKH */\r
+#define FLASH_CMPA_ROTKH_COUNT (8U)\r
+\r
+/*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */\r
+/*! @{ */\r
+#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CMPA_CUSTOMER_DEFINED */\r
+#define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U)\r
+\r
+/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */\r
+/*! @{ */\r
+#define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U)\r
+#define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_CMPA_SHA256_DIGEST */\r
+#define FLASH_CMPA_SHA256_DIGEST_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_CMPA_Register_Masks */\r
+\r
+\r
+/* FLASH_CMPA - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral FLASH_CMPA base address */\r
+ #define FLASH_CMPA_BASE (0x1009E400u)\r
+ /** Peripheral FLASH_CMPA base address */\r
+ #define FLASH_CMPA_BASE_NS (0x9E400u)\r
+ /** Peripheral FLASH_CMPA base pointer */\r
+ #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)\r
+ /** Peripheral FLASH_CMPA base pointer */\r
+ #define FLASH_CMPA_NS ((FLASH_CMPA_Type *)FLASH_CMPA_BASE_NS)\r
+ /** Array initializer of FLASH_CMPA peripheral base addresses */\r
+ #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE }\r
+ /** Array initializer of FLASH_CMPA peripheral base pointers */\r
+ #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA }\r
+ /** Array initializer of FLASH_CMPA peripheral base addresses */\r
+ #define FLASH_CMPA_BASE_ADDRS_NS { FLASH_CMPA_BASE_NS }\r
+ /** Array initializer of FLASH_CMPA peripheral base pointers */\r
+ #define FLASH_CMPA_BASE_PTRS_NS { FLASH_CMPA_NS }\r
+#else\r
+ /** Peripheral FLASH_CMPA base address */\r
+ #define FLASH_CMPA_BASE (0x9E400u)\r
+ /** Peripheral FLASH_CMPA base pointer */\r
+ #define FLASH_CMPA ((FLASH_CMPA_Type *)FLASH_CMPA_BASE)\r
+ /** Array initializer of FLASH_CMPA peripheral base addresses */\r
+ #define FLASH_CMPA_BASE_ADDRS { FLASH_CMPA_BASE }\r
+ /** Array initializer of FLASH_CMPA peripheral base pointers */\r
+ #define FLASH_CMPA_BASE_PTRS { FLASH_CMPA }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_CMPA_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH_KEY_STORE Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_KEY_STORE_Peripheral_Access_Layer FLASH_KEY_STORE Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** FLASH_KEY_STORE - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0 */\r
+ __IO uint32_t HEADER; /**< Valid Key Sore Header : 0x95959595, offset: 0x0 */\r
+ __IO uint32_t PUF_DISCHARGE_TIME_IN_MS; /**< puf discharge time in ms., offset: 0x4 */\r
+ } KEY_STORE_HEADER;\r
+ __IO uint32_t ACTIVATION_CODE[298]; /**< ., array offset: 0x8, array step: 0x4 */\r
+ union { /* offset: 0x4B0 */\r
+ __IO uint32_t SBKEY_KEY_CODE[14]; /**< ., array offset: 0x4B0, array step: 0x4 */\r
+ struct { /* offset: 0x4B0 */\r
+ __IO uint32_t SBKEY_HEADER0; /**< ., offset: 0x4B0 */\r
+ __IO uint32_t SBKEY_HEADER1; /**< ., offset: 0x4B4 */\r
+ __IO uint32_t SBKEY_BODY[12]; /**< ., array offset: 0x4B8, array step: 0x4 */\r
+ } SBKEY_KEY_CODE_CORE;\r
+ };\r
+ union { /* offset: 0x4E8 */\r
+ __IO uint32_t USER_KEK_KEY_CODE[14]; /**< ., array offset: 0x4E8, array step: 0x4 */\r
+ struct { /* offset: 0x4E8 */\r
+ __IO uint32_t USER_KEK_HEADER0; /**< ., offset: 0x4E8 */\r
+ __IO uint32_t USER_KEK_HEADER1; /**< ., offset: 0x4EC */\r
+ __IO uint32_t USER_KEK_BODY[12]; /**< ., array offset: 0x4F0, array step: 0x4 */\r
+ } USER_KEK_KEY_CODE_CORE;\r
+ };\r
+ union { /* offset: 0x520 */\r
+ __IO uint32_t UDS_KEY_CODE[14]; /**< ., array offset: 0x520, array step: 0x4 */\r
+ struct { /* offset: 0x520 */\r
+ __IO uint32_t UDS_HEADER0; /**< ., offset: 0x520 */\r
+ __IO uint32_t UDS_HEADER1; /**< ., offset: 0x524 */\r
+ __IO uint32_t UDS_BODY[12]; /**< ., array offset: 0x528, array step: 0x4 */\r
+ } UDS_KEY_CODE_CORE;\r
+ };\r
+ union { /* offset: 0x558 */\r
+ __IO uint32_t PRINCE_REGION0_KEY_CODE[14]; /**< ., array offset: 0x558, array step: 0x4 */\r
+ struct { /* offset: 0x558 */\r
+ __IO uint32_t PRINCE_REGION0_HEADER0; /**< ., offset: 0x558 */\r
+ __IO uint32_t PRINCE_REGION0_HEADER1; /**< ., offset: 0x55C */\r
+ __IO uint32_t PRINCE_REGION0_BODY[12]; /**< ., array offset: 0x560, array step: 0x4 */\r
+ } PRINCE_REGION0_KEY_CODE_CORE;\r
+ };\r
+ union { /* offset: 0x590 */\r
+ __IO uint32_t PRINCE_REGION1_KEY_CODE[14]; /**< ., array offset: 0x590, array step: 0x4 */\r
+ struct { /* offset: 0x590 */\r
+ __IO uint32_t PRINCE_REGION1_HEADER0; /**< ., offset: 0x590 */\r
+ __IO uint32_t PRINCE_REGION1_HEADER1; /**< ., offset: 0x594 */\r
+ __IO uint32_t PRINCE_REGION1_BODY[12]; /**< ., array offset: 0x598, array step: 0x4 */\r
+ } PRINCE_REGION1_KEY_CODE_CORE;\r
+ };\r
+ union { /* offset: 0x5C8 */\r
+ __IO uint32_t PRINCE_REGION2_KEY_CODE[14]; /**< ., array offset: 0x5C8, array step: 0x4 */\r
+ struct { /* offset: 0x5C8 */\r
+ __IO uint32_t PRINCE_REGION2_HEADER0; /**< ., offset: 0x5C8 */\r
+ __IO uint32_t PRINCE_REGION2_HEADER1; /**< ., offset: 0x5CC */\r
+ __IO uint32_t PRINCE_REGION2_BODY[12]; /**< ., array offset: 0x5D0, array step: 0x4 */\r
+ } PRINCE_REGION2_KEY_CODE_CORE;\r
+ };\r
+} FLASH_KEY_STORE_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLASH_KEY_STORE Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLASH_KEY_STORE_Register_Masks FLASH_KEY_STORE Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name HEADER - Valid Key Sore Header : 0x95959595 */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name ACTIVATION_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_ACTIVATION_CODE */\r
+#define FLASH_KEY_STORE_ACTIVATION_CODE_COUNT (298U)\r
+\r
+/*! @name SBKEY_KEY_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_SBKEY_KEY_CODE */\r
+#define FLASH_KEY_STORE_SBKEY_KEY_CODE_COUNT (14U)\r
+\r
+/*! @name SBKEY_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name SBKEY_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name SBKEY_BODY - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_SBKEY_BODY */\r
+#define FLASH_KEY_STORE_SBKEY_BODY_COUNT (12U)\r
+\r
+/*! @name USER_KEK_KEY_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_USER_KEK_KEY_CODE */\r
+#define FLASH_KEY_STORE_USER_KEK_KEY_CODE_COUNT (14U)\r
+\r
+/*! @name USER_KEK_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name USER_KEK_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USER_KEK_BODY - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_USER_KEK_BODY */\r
+#define FLASH_KEY_STORE_USER_KEK_BODY_COUNT (12U)\r
+\r
+/*! @name UDS_KEY_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_UDS_KEY_CODE */\r
+#define FLASH_KEY_STORE_UDS_KEY_CODE_COUNT (14U)\r
+\r
+/*! @name UDS_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name UDS_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name UDS_BODY - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_UDS_BODY */\r
+#define FLASH_KEY_STORE_UDS_BODY_COUNT (12U)\r
+\r
+/*! @name PRINCE_REGION0_KEY_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE */\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_COUNT (14U)\r
+\r
+/*! @name PRINCE_REGION0_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION0_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION0_BODY - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_PRINCE_REGION0_BODY */\r
+#define FLASH_KEY_STORE_PRINCE_REGION0_BODY_COUNT (12U)\r
+\r
+/*! @name PRINCE_REGION1_KEY_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE */\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_COUNT (14U)\r
+\r
+/*! @name PRINCE_REGION1_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION1_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION1_BODY - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_PRINCE_REGION1_BODY */\r
+#define FLASH_KEY_STORE_PRINCE_REGION1_BODY_COUNT (12U)\r
+\r
+/*! @name PRINCE_REGION2_KEY_CODE - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE */\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_COUNT (14U)\r
+\r
+/*! @name PRINCE_REGION2_HEADER0 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION2_HEADER1 - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRINCE_REGION2_BODY - . */\r
+/*! @{ */\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U)\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK)\r
+/*! @} */\r
+\r
+/* The count of FLASH_KEY_STORE_PRINCE_REGION2_BODY */\r
+#define FLASH_KEY_STORE_PRINCE_REGION2_BODY_COUNT (12U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_KEY_STORE_Register_Masks */\r
+\r
+\r
+/* FLASH_KEY_STORE - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral FLASH_KEY_STORE base address */\r
+ #define FLASH_KEY_STORE_BASE (0x1009E600u)\r
+ /** Peripheral FLASH_KEY_STORE base address */\r
+ #define FLASH_KEY_STORE_BASE_NS (0x9E600u)\r
+ /** Peripheral FLASH_KEY_STORE base pointer */\r
+ #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)\r
+ /** Peripheral FLASH_KEY_STORE base pointer */\r
+ #define FLASH_KEY_STORE_NS ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE_NS)\r
+ /** Array initializer of FLASH_KEY_STORE peripheral base addresses */\r
+ #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE }\r
+ /** Array initializer of FLASH_KEY_STORE peripheral base pointers */\r
+ #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE }\r
+ /** Array initializer of FLASH_KEY_STORE peripheral base addresses */\r
+ #define FLASH_KEY_STORE_BASE_ADDRS_NS { FLASH_KEY_STORE_BASE_NS }\r
+ /** Array initializer of FLASH_KEY_STORE peripheral base pointers */\r
+ #define FLASH_KEY_STORE_BASE_PTRS_NS { FLASH_KEY_STORE_NS }\r
+#else\r
+ /** Peripheral FLASH_KEY_STORE base address */\r
+ #define FLASH_KEY_STORE_BASE (0x9E600u)\r
+ /** Peripheral FLASH_KEY_STORE base pointer */\r
+ #define FLASH_KEY_STORE ((FLASH_KEY_STORE_Type *)FLASH_KEY_STORE_BASE)\r
+ /** Array initializer of FLASH_KEY_STORE peripheral base addresses */\r
+ #define FLASH_KEY_STORE_BASE_ADDRS { FLASH_KEY_STORE_BASE }\r
+ /** Array initializer of FLASH_KEY_STORE peripheral base pointers */\r
+ #define FLASH_KEY_STORE_BASE_PTRS { FLASH_KEY_STORE }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLASH_KEY_STORE_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLEXCOMM Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** FLEXCOMM - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[4088];\r
+ __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */\r
+ __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */\r
+} FLEXCOMM_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- FLEXCOMM Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */\r
+/*! @{ */\r
+#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)\r
+#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)\r
+/*! PERSEL - Peripheral Select. This field is writable by software.\r
+ * 0b000..No peripheral selected.\r
+ * 0b001..USART function selected.\r
+ * 0b010..SPI function selected.\r
+ * 0b011..I2C function selected.\r
+ * 0b100..I2S transmit function selected.\r
+ * 0b101..I2S receive function selected.\r
+ * 0b110..Reserved\r
+ * 0b111..Reserved\r
+ */\r
+#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)\r
+#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)\r
+#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)\r
+/*! LOCK - Lock the peripheral select. This field is writable by software.\r
+ * 0b0..Peripheral select can be changed by software.\r
+ * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset.\r
+ */\r
+#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)\r
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)\r
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)\r
+/*! USARTPRESENT - USART present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the USART function.\r
+ * 0b1..This Flexcomm includes the USART function.\r
+ */\r
+#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)\r
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)\r
+/*! SPIPRESENT - SPI present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the SPI function.\r
+ * 0b1..This Flexcomm includes the SPI function.\r
+ */\r
+#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)\r
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)\r
+/*! I2CPRESENT - I2C present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the I2C function.\r
+ * 0b1..This Flexcomm includes the I2C function.\r
+ */\r
+#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)\r
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)\r
+/*! I2SPRESENT - I 2S present indicator. This field is Read-only.\r
+ * 0b0..This Flexcomm does not include the I2S function.\r
+ * 0b1..This Flexcomm includes the I2S function.\r
+ */\r
+#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)\r
+#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)\r
+#define FLEXCOMM_PSELID_ID_SHIFT (12U)\r
+#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)\r
+/*! @} */\r
+\r
+/*! @name PID - Peripheral identification register. */\r
+/*! @{ */\r
+#define FLEXCOMM_PID_Aperture_MASK (0xFFU)\r
+#define FLEXCOMM_PID_Aperture_SHIFT (0U)\r
+#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK)\r
+#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)\r
+#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)\r
+#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)\r
+#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)\r
+#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)\r
+#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)\r
+#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)\r
+#define FLEXCOMM_PID_ID_SHIFT (16U)\r
+#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLEXCOMM_Register_Masks */\r
+\r
+\r
+/* FLEXCOMM - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral FLEXCOMM0 base address */\r
+ #define FLEXCOMM0_BASE (0x50086000u)\r
+ /** Peripheral FLEXCOMM0 base address */\r
+ #define FLEXCOMM0_BASE_NS (0x40086000u)\r
+ /** Peripheral FLEXCOMM0 base pointer */\r
+ #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)\r
+ /** Peripheral FLEXCOMM0 base pointer */\r
+ #define FLEXCOMM0_NS ((FLEXCOMM_Type *)FLEXCOMM0_BASE_NS)\r
+ /** Peripheral FLEXCOMM1 base address */\r
+ #define FLEXCOMM1_BASE (0x50087000u)\r
+ /** Peripheral FLEXCOMM1 base address */\r
+ #define FLEXCOMM1_BASE_NS (0x40087000u)\r
+ /** Peripheral FLEXCOMM1 base pointer */\r
+ #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)\r
+ /** Peripheral FLEXCOMM1 base pointer */\r
+ #define FLEXCOMM1_NS ((FLEXCOMM_Type *)FLEXCOMM1_BASE_NS)\r
+ /** Peripheral FLEXCOMM2 base address */\r
+ #define FLEXCOMM2_BASE (0x50088000u)\r
+ /** Peripheral FLEXCOMM2 base address */\r
+ #define FLEXCOMM2_BASE_NS (0x40088000u)\r
+ /** Peripheral FLEXCOMM2 base pointer */\r
+ #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)\r
+ /** Peripheral FLEXCOMM2 base pointer */\r
+ #define FLEXCOMM2_NS ((FLEXCOMM_Type *)FLEXCOMM2_BASE_NS)\r
+ /** Peripheral FLEXCOMM3 base address */\r
+ #define FLEXCOMM3_BASE (0x50089000u)\r
+ /** Peripheral FLEXCOMM3 base address */\r
+ #define FLEXCOMM3_BASE_NS (0x40089000u)\r
+ /** Peripheral FLEXCOMM3 base pointer */\r
+ #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)\r
+ /** Peripheral FLEXCOMM3 base pointer */\r
+ #define FLEXCOMM3_NS ((FLEXCOMM_Type *)FLEXCOMM3_BASE_NS)\r
+ /** Peripheral FLEXCOMM4 base address */\r
+ #define FLEXCOMM4_BASE (0x5008A000u)\r
+ /** Peripheral FLEXCOMM4 base address */\r
+ #define FLEXCOMM4_BASE_NS (0x4008A000u)\r
+ /** Peripheral FLEXCOMM4 base pointer */\r
+ #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)\r
+ /** Peripheral FLEXCOMM4 base pointer */\r
+ #define FLEXCOMM4_NS ((FLEXCOMM_Type *)FLEXCOMM4_BASE_NS)\r
+ /** Peripheral FLEXCOMM5 base address */\r
+ #define FLEXCOMM5_BASE (0x50096000u)\r
+ /** Peripheral FLEXCOMM5 base address */\r
+ #define FLEXCOMM5_BASE_NS (0x40096000u)\r
+ /** Peripheral FLEXCOMM5 base pointer */\r
+ #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)\r
+ /** Peripheral FLEXCOMM5 base pointer */\r
+ #define FLEXCOMM5_NS ((FLEXCOMM_Type *)FLEXCOMM5_BASE_NS)\r
+ /** Peripheral FLEXCOMM6 base address */\r
+ #define FLEXCOMM6_BASE (0x50097000u)\r
+ /** Peripheral FLEXCOMM6 base address */\r
+ #define FLEXCOMM6_BASE_NS (0x40097000u)\r
+ /** Peripheral FLEXCOMM6 base pointer */\r
+ #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)\r
+ /** Peripheral FLEXCOMM6 base pointer */\r
+ #define FLEXCOMM6_NS ((FLEXCOMM_Type *)FLEXCOMM6_BASE_NS)\r
+ /** Peripheral FLEXCOMM7 base address */\r
+ #define FLEXCOMM7_BASE (0x50098000u)\r
+ /** Peripheral FLEXCOMM7 base address */\r
+ #define FLEXCOMM7_BASE_NS (0x40098000u)\r
+ /** Peripheral FLEXCOMM7 base pointer */\r
+ #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)\r
+ /** Peripheral FLEXCOMM7 base pointer */\r
+ #define FLEXCOMM7_NS ((FLEXCOMM_Type *)FLEXCOMM7_BASE_NS)\r
+ /** Peripheral FLEXCOMM8 base address */\r
+ #define FLEXCOMM8_BASE (0x5009F000u)\r
+ /** Peripheral FLEXCOMM8 base address */\r
+ #define FLEXCOMM8_BASE_NS (0x4009F000u)\r
+ /** Peripheral FLEXCOMM8 base pointer */\r
+ #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)\r
+ /** Peripheral FLEXCOMM8 base pointer */\r
+ #define FLEXCOMM8_NS ((FLEXCOMM_Type *)FLEXCOMM8_BASE_NS)\r
+ /** Array initializer of FLEXCOMM peripheral base addresses */\r
+ #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }\r
+ /** Array initializer of FLEXCOMM peripheral base pointers */\r
+ #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }\r
+ /** Array initializer of FLEXCOMM peripheral base addresses */\r
+ #define FLEXCOMM_BASE_ADDRS_NS { FLEXCOMM0_BASE_NS, FLEXCOMM1_BASE_NS, FLEXCOMM2_BASE_NS, FLEXCOMM3_BASE_NS, FLEXCOMM4_BASE_NS, FLEXCOMM5_BASE_NS, FLEXCOMM6_BASE_NS, FLEXCOMM7_BASE_NS, FLEXCOMM8_BASE_NS }\r
+ /** Array initializer of FLEXCOMM peripheral base pointers */\r
+ #define FLEXCOMM_BASE_PTRS_NS { FLEXCOMM0_NS, FLEXCOMM1_NS, FLEXCOMM2_NS, FLEXCOMM3_NS, FLEXCOMM4_NS, FLEXCOMM5_NS, FLEXCOMM6_NS, FLEXCOMM7_NS, FLEXCOMM8_NS }\r
+#else\r
+ /** Peripheral FLEXCOMM0 base address */\r
+ #define FLEXCOMM0_BASE (0x40086000u)\r
+ /** Peripheral FLEXCOMM0 base pointer */\r
+ #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)\r
+ /** Peripheral FLEXCOMM1 base address */\r
+ #define FLEXCOMM1_BASE (0x40087000u)\r
+ /** Peripheral FLEXCOMM1 base pointer */\r
+ #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)\r
+ /** Peripheral FLEXCOMM2 base address */\r
+ #define FLEXCOMM2_BASE (0x40088000u)\r
+ /** Peripheral FLEXCOMM2 base pointer */\r
+ #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)\r
+ /** Peripheral FLEXCOMM3 base address */\r
+ #define FLEXCOMM3_BASE (0x40089000u)\r
+ /** Peripheral FLEXCOMM3 base pointer */\r
+ #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)\r
+ /** Peripheral FLEXCOMM4 base address */\r
+ #define FLEXCOMM4_BASE (0x4008A000u)\r
+ /** Peripheral FLEXCOMM4 base pointer */\r
+ #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)\r
+ /** Peripheral FLEXCOMM5 base address */\r
+ #define FLEXCOMM5_BASE (0x40096000u)\r
+ /** Peripheral FLEXCOMM5 base pointer */\r
+ #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)\r
+ /** Peripheral FLEXCOMM6 base address */\r
+ #define FLEXCOMM6_BASE (0x40097000u)\r
+ /** Peripheral FLEXCOMM6 base pointer */\r
+ #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)\r
+ /** Peripheral FLEXCOMM7 base address */\r
+ #define FLEXCOMM7_BASE (0x40098000u)\r
+ /** Peripheral FLEXCOMM7 base pointer */\r
+ #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)\r
+ /** Peripheral FLEXCOMM8 base address */\r
+ #define FLEXCOMM8_BASE (0x4009F000u)\r
+ /** Peripheral FLEXCOMM8 base pointer */\r
+ #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)\r
+ /** Array initializer of FLEXCOMM peripheral base addresses */\r
+ #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE }\r
+ /** Array initializer of FLEXCOMM peripheral base pointers */\r
+ #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8 }\r
+#endif\r
+/** Interrupt vectors for the FLEXCOMM peripheral type */\r
+#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, LSPI_HS_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GINT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** GINT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */\r
+ uint8_t RESERVED_0[28];\r
+ __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */\r
+ uint8_t RESERVED_1[24];\r
+ __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */\r
+} GINT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GINT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GINT_Register_Masks GINT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - GPIO grouped interrupt control register */\r
+/*! @{ */\r
+#define GINT_CTRL_INT_MASK (0x1U)\r
+#define GINT_CTRL_INT_SHIFT (0U)\r
+/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.\r
+ * 0b0..No request. No interrupt request is pending.\r
+ * 0b1..Request active. Interrupt request is active.\r
+ */\r
+#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)\r
+#define GINT_CTRL_COMB_MASK (0x2U)\r
+#define GINT_CTRL_COMB_SHIFT (1U)\r
+/*! COMB - Combine enabled inputs for group interrupt\r
+ * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity).\r
+ * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity).\r
+ */\r
+#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)\r
+#define GINT_CTRL_TRIG_MASK (0x4U)\r
+#define GINT_CTRL_TRIG_SHIFT (2U)\r
+/*! TRIG - Group interrupt trigger\r
+ * 0b0..Edge-triggered.\r
+ * 0b1..Level-triggered.\r
+ */\r
+#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */\r
+/*! @{ */\r
+#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)\r
+#define GINT_PORT_POL_POL_SHIFT (0U)\r
+#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)\r
+/*! @} */\r
+\r
+/* The count of GINT_PORT_POL */\r
+#define GINT_PORT_POL_COUNT (2U)\r
+\r
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */\r
+/*! @{ */\r
+#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)\r
+#define GINT_PORT_ENA_ENA_SHIFT (0U)\r
+#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)\r
+/*! @} */\r
+\r
+/* The count of GINT_PORT_ENA */\r
+#define GINT_PORT_ENA_COUNT (2U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GINT_Register_Masks */\r
+\r
+\r
+/* GINT - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral GINT0 base address */\r
+ #define GINT0_BASE (0x50002000u)\r
+ /** Peripheral GINT0 base address */\r
+ #define GINT0_BASE_NS (0x40002000u)\r
+ /** Peripheral GINT0 base pointer */\r
+ #define GINT0 ((GINT_Type *)GINT0_BASE)\r
+ /** Peripheral GINT0 base pointer */\r
+ #define GINT0_NS ((GINT_Type *)GINT0_BASE_NS)\r
+ /** Peripheral GINT1 base address */\r
+ #define GINT1_BASE (0x50003000u)\r
+ /** Peripheral GINT1 base address */\r
+ #define GINT1_BASE_NS (0x40003000u)\r
+ /** Peripheral GINT1 base pointer */\r
+ #define GINT1 ((GINT_Type *)GINT1_BASE)\r
+ /** Peripheral GINT1 base pointer */\r
+ #define GINT1_NS ((GINT_Type *)GINT1_BASE_NS)\r
+ /** Array initializer of GINT peripheral base addresses */\r
+ #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }\r
+ /** Array initializer of GINT peripheral base pointers */\r
+ #define GINT_BASE_PTRS { GINT0, GINT1 }\r
+ /** Array initializer of GINT peripheral base addresses */\r
+ #define GINT_BASE_ADDRS_NS { GINT0_BASE_NS, GINT1_BASE_NS }\r
+ /** Array initializer of GINT peripheral base pointers */\r
+ #define GINT_BASE_PTRS_NS { GINT0_NS, GINT1_NS }\r
+#else\r
+ /** Peripheral GINT0 base address */\r
+ #define GINT0_BASE (0x40002000u)\r
+ /** Peripheral GINT0 base pointer */\r
+ #define GINT0 ((GINT_Type *)GINT0_BASE)\r
+ /** Peripheral GINT1 base address */\r
+ #define GINT1_BASE (0x40003000u)\r
+ /** Peripheral GINT1 base pointer */\r
+ #define GINT1 ((GINT_Type *)GINT1_BASE)\r
+ /** Array initializer of GINT peripheral base addresses */\r
+ #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }\r
+ /** Array initializer of GINT peripheral base pointers */\r
+ #define GINT_BASE_PTRS { GINT0, GINT1 }\r
+#endif\r
+/** Interrupt vectors for the GINT peripheral type */\r
+#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GINT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GPIO Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** GPIO - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */\r
+ uint8_t RESERVED_0[3968];\r
+ __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */\r
+ uint8_t RESERVED_1[3584];\r
+ __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */\r
+ uint8_t RESERVED_2[112];\r
+ __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */\r
+ uint8_t RESERVED_3[112];\r
+ __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */\r
+ uint8_t RESERVED_4[112];\r
+ __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */\r
+ uint8_t RESERVED_5[112];\r
+ __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */\r
+ uint8_t RESERVED_6[112];\r
+ __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */\r
+ uint8_t RESERVED_7[112];\r
+ __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */\r
+ uint8_t RESERVED_8[112];\r
+ __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */\r
+ uint8_t RESERVED_9[112];\r
+ __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */\r
+ uint8_t RESERVED_10[112];\r
+ __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */\r
+} GPIO_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- GPIO Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name B - Byte pin registers for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_B_PBYTE_MASK (0x1U)\r
+#define GPIO_B_PBYTE_SHIFT (0U)\r
+#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_B */\r
+#define GPIO_B_COUNT (4U)\r
+\r
+/* The count of GPIO_B */\r
+#define GPIO_B_COUNT2 (32U)\r
+\r
+/*! @name W - Word pin registers for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)\r
+#define GPIO_W_PWORD_SHIFT (0U)\r
+#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_W */\r
+#define GPIO_W_COUNT (4U)\r
+\r
+/* The count of GPIO_W */\r
+#define GPIO_W_COUNT2 (32U)\r
+\r
+/*! @name DIR - Direction registers for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)\r
+#define GPIO_DIR_DIRP_SHIFT (0U)\r
+#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIR */\r
+#define GPIO_DIR_COUNT (4U)\r
+\r
+/*! @name MASK - Mask register for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)\r
+#define GPIO_MASK_MASKP_SHIFT (0U)\r
+#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_MASK */\r
+#define GPIO_MASK_COUNT (4U)\r
+\r
+/*! @name PIN - Port pin register for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)\r
+#define GPIO_PIN_PORT_SHIFT (0U)\r
+#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_PIN */\r
+#define GPIO_PIN_COUNT (4U)\r
+\r
+/*! @name MPIN - Masked port register for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)\r
+#define GPIO_MPIN_MPORTP_SHIFT (0U)\r
+#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_MPIN */\r
+#define GPIO_MPIN_COUNT (4U)\r
+\r
+/*! @name SET - Write: Set register for port. Read: output bits for port */\r
+/*! @{ */\r
+#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)\r
+#define GPIO_SET_SETP_SHIFT (0U)\r
+#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_SET */\r
+#define GPIO_SET_COUNT (4U)\r
+\r
+/*! @name CLR - Clear port for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)\r
+#define GPIO_CLR_CLRP_SHIFT (0U)\r
+#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_CLR */\r
+#define GPIO_CLR_COUNT (4U)\r
+\r
+/*! @name NOT - Toggle port for all port GPIO pins */\r
+/*! @{ */\r
+#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)\r
+#define GPIO_NOT_NOTP_SHIFT (0U)\r
+#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_NOT */\r
+#define GPIO_NOT_COUNT (4U)\r
+\r
+/*! @name DIRSET - Set pin direction bits for port */\r
+/*! @{ */\r
+#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)\r
+#define GPIO_DIRSET_DIRSETP_SHIFT (0U)\r
+#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIRSET */\r
+#define GPIO_DIRSET_COUNT (4U)\r
+\r
+/*! @name DIRCLR - Clear pin direction bits for port */\r
+/*! @{ */\r
+#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)\r
+#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)\r
+#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIRCLR */\r
+#define GPIO_DIRCLR_COUNT (4U)\r
+\r
+/*! @name DIRNOT - Toggle pin direction bits for port */\r
+/*! @{ */\r
+#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)\r
+#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)\r
+#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)\r
+/*! @} */\r
+\r
+/* The count of GPIO_DIRNOT */\r
+#define GPIO_DIRNOT_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GPIO_Register_Masks */\r
+\r
+\r
+/* GPIO - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral GPIO base address */\r
+ #define GPIO_BASE (0x5008C000u)\r
+ /** Peripheral GPIO base address */\r
+ #define GPIO_BASE_NS (0x4008C000u)\r
+ /** Peripheral GPIO base pointer */\r
+ #define GPIO ((GPIO_Type *)GPIO_BASE)\r
+ /** Peripheral GPIO base pointer */\r
+ #define GPIO_NS ((GPIO_Type *)GPIO_BASE_NS)\r
+ /** Peripheral SECGPIO base address */\r
+ #define SECGPIO_BASE (0x500A8000u)\r
+ /** Peripheral SECGPIO base address */\r
+ #define SECGPIO_BASE_NS (0x400A8000u)\r
+ /** Peripheral SECGPIO base pointer */\r
+ #define SECGPIO ((GPIO_Type *)SECGPIO_BASE)\r
+ /** Peripheral SECGPIO base pointer */\r
+ #define SECGPIO_NS ((GPIO_Type *)SECGPIO_BASE_NS)\r
+ /** Array initializer of GPIO peripheral base addresses */\r
+ #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE }\r
+ /** Array initializer of GPIO peripheral base pointers */\r
+ #define GPIO_BASE_PTRS { GPIO, SECGPIO }\r
+ /** Array initializer of GPIO peripheral base addresses */\r
+ #define GPIO_BASE_ADDRS_NS { GPIO_BASE_NS, SECGPIO_BASE_NS }\r
+ /** Array initializer of GPIO peripheral base pointers */\r
+ #define GPIO_BASE_PTRS_NS { GPIO_NS, SECGPIO_NS }\r
+#else\r
+ /** Peripheral GPIO base address */\r
+ #define GPIO_BASE (0x4008C000u)\r
+ /** Peripheral GPIO base pointer */\r
+ #define GPIO ((GPIO_Type *)GPIO_BASE)\r
+ /** Peripheral SECGPIO base address */\r
+ #define SECGPIO_BASE (0x400A8000u)\r
+ /** Peripheral SECGPIO base pointer */\r
+ #define SECGPIO ((GPIO_Type *)SECGPIO_BASE)\r
+ /** Array initializer of GPIO peripheral base addresses */\r
+ #define GPIO_BASE_ADDRS { GPIO_BASE, SECGPIO_BASE }\r
+ /** Array initializer of GPIO peripheral base pointers */\r
+ #define GPIO_BASE_PTRS { GPIO, SECGPIO }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group GPIO_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- HASHCRYPT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup HASHCRYPT_Peripheral_Access_Layer HASHCRYPT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** HASHCRYPT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */\r
+ __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */\r
+ __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */\r
+ __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */\r
+ __IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available), offset: 0x10 */\r
+ __IO uint32_t MEMADDR; /**< Address to start memory access from (if available)., offset: 0x14 */\r
+ uint8_t RESERVED_0[8];\r
+ __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */\r
+ __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */\r
+ __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */\r
+ __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */\r
+ __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */\r
+ __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */\r
+ __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */\r
+} HASHCRYPT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- HASHCRYPT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup HASHCRYPT_Register_Masks HASHCRYPT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - Is control register to enable and operate Hash and Crypto */\r
+/*! @{ */\r
+#define HASHCRYPT_CTRL_MODE_MASK (0x7U)\r
+#define HASHCRYPT_CTRL_MODE_SHIFT (0U)\r
+/*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available.\r
+ * 0b000..Disabled\r
+ * 0b001..SHA1 is enabled\r
+ * 0b010..SHA2-256 is enabled\r
+ * 0b011..SHA2-512 is enabled (if available)\r
+ * 0b100..AES if available (see also CRYPTCFG register for more controls)\r
+ * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls)\r
+ * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register)\r
+ * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls)\r
+ */\r
+#define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK)\r
+#define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U)\r
+#define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U)\r
+/*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1.\r
+ * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result.\r
+ */\r
+#define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK)\r
+#define HASHCRYPT_CTRL_DMA_I_MASK (0x100U)\r
+#define HASHCRYPT_CTRL_DMA_I_SHIFT (8U)\r
+/*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed).\r
+ * 0b0..DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used.\r
+ * 0b1..DMA will push in the data.\r
+ */\r
+#define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK)\r
+#define HASHCRYPT_CTRL_DMA_O_MASK (0x200U)\r
+#define HASHCRYPT_CTRL_DMA_O_SHIFT (9U)\r
+/*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses.\r
+ * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt.\r
+ */\r
+#define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK)\r
+#define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U)\r
+#define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U)\r
+#define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - Indicates status of Hash peripheral. */\r
+/*! @{ */\r
+#define HASHCRYPT_STATUS_WAITING_MASK (0x1U)\r
+#define HASHCRYPT_STATUS_WAITING_SHIFT (0U)\r
+/*! WAITING - If 1, the block is waiting for more data to process.\r
+ * 0b0..Not waiting for data - may be disabled or may be busy. Note that for cryptographic uses, this is not set if IsLast is set nor will it set until at least 1 word is read of the output.\r
+ * 0b1..Waiting for data to be written in (16 words)\r
+ */\r
+#define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK)\r
+#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U)\r
+#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U)\r
+/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled.\r
+ * 0b0..No Digest is ready\r
+ * 0b1..Digest is ready. Application may read it or may write more data\r
+ */\r
+#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)\r
+#define HASHCRYPT_STATUS_ERROR_MASK (0x4U)\r
+#define HASHCRYPT_STATUS_ERROR_SHIFT (2U)\r
+/*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA was written when it was not appropriate. For Master cases, this is an AHB bus error; the COUNT field will indicate which block it was on.\r
+ * 0b0..No error.\r
+ * 0b1..An error occurred since last cleared (written 1 to clear).\r
+ */\r
+#define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK)\r
+#define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U)\r
+#define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U)\r
+/*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING)\r
+ * 0b0..No Key is needed and writes will not be treated as Key\r
+ * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING.\r
+ */\r
+#define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK)\r
+#define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U)\r
+#define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U)\r
+/*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING)\r
+ * 0b0..No IV/Nonce is needed, either because written already or because not needed.\r
+ * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING.\r
+ */\r
+#define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK)\r
+#define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U)\r
+#define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U)\r
+#define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */\r
+/*! @{ */\r
+#define HASHCRYPT_INTENSET_WAITING_MASK (0x1U)\r
+#define HASHCRYPT_INTENSET_WAITING_SHIFT (0U)\r
+/*! WAITING - Indicates if should interrupt when waiting for data input.\r
+ * 0b0..Will not interrupt when waiting.\r
+ * 0b1..Will interrupt when waiting\r
+ */\r
+#define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK)\r
+#define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U)\r
+#define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U)\r
+/*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence).\r
+ * 0b0..Will not interrupt when Digest is ready\r
+ * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done).\r
+ */\r
+#define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK)\r
+#define HASHCRYPT_INTENSET_ERROR_MASK (0x4U)\r
+#define HASHCRYPT_INTENSET_ERROR_SHIFT (2U)\r
+/*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status)\r
+ * 0b0..Will not interrupt on Error.\r
+ * 0b1..Will interrupt on Error (until cleared).\r
+ */\r
+#define HASHCRYPT_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_ERROR_SHIFT)) & HASHCRYPT_INTENSET_ERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Write 1 to clear interrupts. */\r
+/*! @{ */\r
+#define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U)\r
+#define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U)\r
+#define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK)\r
+#define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U)\r
+#define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U)\r
+#define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK)\r
+#define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U)\r
+#define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U)\r
+#define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name MEMCTRL - Setup Master to access memory (if available) */\r
+/*! @{ */\r
+#define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U)\r
+#define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U)\r
+/*! MASTER\r
+ * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA.\r
+ * 0b1..Mastering is enabled and DMA and INDATA should not be used.\r
+ */\r
+#define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK)\r
+#define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U)\r
+#define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U)\r
+#define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name MEMADDR - Address to start memory access from (if available). */\r
+/*! @{ */\r
+#define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU)\r
+#define HASHCRYPT_MEMADDR_BASE_SHIFT (0U)\r
+#define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INDATA - Input of 16 words at a time to load up buffer. */\r
+/*! @{ */\r
+#define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU)\r
+#define HASHCRYPT_INDATA_DATA_SHIFT (0U)\r
+#define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name ALIAS - */\r
+/*! @{ */\r
+#define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU)\r
+#define HASHCRYPT_ALIAS_DATA_SHIFT (0U)\r
+#define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of HASHCRYPT_ALIAS */\r
+#define HASHCRYPT_ALIAS_COUNT (7U)\r
+\r
+/*! @name OUTDATA0 - */\r
+/*! @{ */\r
+#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU)\r
+#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U)\r
+#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK)\r
+/*! @} */\r
+\r
+/* The count of HASHCRYPT_OUTDATA0 */\r
+#define HASHCRYPT_OUTDATA0_COUNT (8U)\r
+\r
+/*! @name OUTDATA1 - */\r
+/*! @{ */\r
+#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU)\r
+#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U)\r
+#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK)\r
+/*! @} */\r
+\r
+/* The count of HASHCRYPT_OUTDATA1 */\r
+#define HASHCRYPT_OUTDATA1_COUNT (8U)\r
+\r
+/*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */\r
+/*! @{ */\r
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U)\r
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U)\r
+#define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK)\r
+#define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U)\r
+#define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U)\r
+#define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK)\r
+#define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U)\r
+#define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U)\r
+#define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK)\r
+#define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U)\r
+#define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U)\r
+#define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK)\r
+#define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U)\r
+#define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U)\r
+/*! AESMODE - AES Cipher mode to use if plain AES\r
+ * 0b00..ECB - used as is\r
+ * 0b01..CBC mode (see details on IV/nonce)\r
+ * 0b10..CTR mode (see details on IV/nonce). See also AESCTRPOS.\r
+ * 0b11..reserved\r
+ */\r
+#define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK)\r
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U)\r
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U)\r
+/*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB\r
+ * 0b0..Encrypt\r
+ * 0b1..Decrypt\r
+ */\r
+#define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK)\r
+#define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U)\r
+#define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U)\r
+/*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are used, only the highest level is permitted to select this.\r
+ * 0b0..User key provided in normal way\r
+ * 0b1..Secret key provided in hidden way by HW\r
+ */\r
+#define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK)\r
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U)\r
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U)\r
+/*! AESKEYSZ - Sets the AES key size\r
+ * 0b00..128 bit key\r
+ * 0b01..192 bit key\r
+ * 0b10..256 bit key\r
+ * 0b11..reserved\r
+ */\r
+#define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK)\r
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U)\r
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U)\r
+#define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK)\r
+#define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U)\r
+#define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U)\r
+#define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK)\r
+#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U)\r
+#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U)\r
+#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK)\r
+#define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U)\r
+#define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U)\r
+/*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV.\r
+ * 0b00..32 bits of the IV/ctr are used (from 127:96)\r
+ * 0b01..64 bits of the IV/ctr are used (from 127:64)\r
+ * 0b10..96 bits of the IV/ctr are used (from 127:32)\r
+ * 0b11..All 128 bits of the IV/ctr are used\r
+ */\r
+#define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK)\r
+#define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U)\r
+#define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U)\r
+/*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new IV/ctr (counter start). This optimizes the performance of the stream of blocks after the 1st.\r
+ * 0b00..8 blocks\r
+ * 0b01..16 blocks\r
+ * 0b10..32 blocks\r
+ * 0b11..64 blocks\r
+ */\r
+#define HASHCRYPT_CRYPTCFG_ICBSTRM(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSTRM_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */\r
+/*! @{ */\r
+#define HASHCRYPT_CONFIG_DUAL_MASK (0x1U)\r
+#define HASHCRYPT_CONFIG_DUAL_SHIFT (0U)\r
+#define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK)\r
+#define HASHCRYPT_CONFIG_DMA_MASK (0x2U)\r
+#define HASHCRYPT_CONFIG_DMA_SHIFT (1U)\r
+#define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK)\r
+#define HASHCRYPT_CONFIG_AHB_MASK (0x8U)\r
+#define HASHCRYPT_CONFIG_AHB_SHIFT (3U)\r
+#define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK)\r
+#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U)\r
+#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U)\r
+#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK)\r
+#define HASHCRYPT_CONFIG_AES_MASK (0x40U)\r
+#define HASHCRYPT_CONFIG_AES_SHIFT (6U)\r
+#define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK)\r
+#define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U)\r
+#define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U)\r
+#define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK)\r
+#define HASHCRYPT_CONFIG_SECRET_MASK (0x100U)\r
+#define HASHCRYPT_CONFIG_SECRET_SHIFT (8U)\r
+#define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK)\r
+#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U)\r
+#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U)\r
+#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK)\r
+#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U)\r
+#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U)\r
+#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK)\r
+#define HASHCRYPT_CONFIG_ICB_MASK (0x800U)\r
+#define HASHCRYPT_CONFIG_ICB_SHIFT (11U)\r
+#define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK)\r
+/*! @} */\r
+\r
+/*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */\r
+/*! @{ */\r
+#define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U)\r
+#define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U)\r
+/*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. If locked already, may only write if at same or higher security level as lock. Reads as: 0 if unlocked, else 1, 2, 3 to indicate security level it is locked at. NOTE: this and ID are the only readable registers if locked and current state is lower than lock level.\r
+ * 0b00..Unlocks, so block is open to all. But, AHB Master will only issue non-secure requests.\r
+ * 0b01..Locks to the current security level. AHB Master will issue requests at this level.\r
+ */\r
+#define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK)\r
+#define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U)\r
+#define HASHCRYPT_LOCK_PATTERN_SHIFT (4U)\r
+#define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASK - */\r
+/*! @{ */\r
+#define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU)\r
+#define HASHCRYPT_MASK_MASK_SHIFT (0U)\r
+#define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK)\r
+/*! @} */\r
+\r
+/* The count of HASHCRYPT_MASK */\r
+#define HASHCRYPT_MASK_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group HASHCRYPT_Register_Masks */\r
+\r
+\r
+/* HASHCRYPT - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral HASHCRYPT base address */\r
+ #define HASHCRYPT_BASE (0x500A4000u)\r
+ /** Peripheral HASHCRYPT base address */\r
+ #define HASHCRYPT_BASE_NS (0x400A4000u)\r
+ /** Peripheral HASHCRYPT base pointer */\r
+ #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)\r
+ /** Peripheral HASHCRYPT base pointer */\r
+ #define HASHCRYPT_NS ((HASHCRYPT_Type *)HASHCRYPT_BASE_NS)\r
+ /** Array initializer of HASHCRYPT peripheral base addresses */\r
+ #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE }\r
+ /** Array initializer of HASHCRYPT peripheral base pointers */\r
+ #define HASHCRYPT_BASE_PTRS { HASHCRYPT }\r
+ /** Array initializer of HASHCRYPT peripheral base addresses */\r
+ #define HASHCRYPT_BASE_ADDRS_NS { HASHCRYPT_BASE_NS }\r
+ /** Array initializer of HASHCRYPT peripheral base pointers */\r
+ #define HASHCRYPT_BASE_PTRS_NS { HASHCRYPT_NS }\r
+#else\r
+ /** Peripheral HASHCRYPT base address */\r
+ #define HASHCRYPT_BASE (0x400A4000u)\r
+ /** Peripheral HASHCRYPT base pointer */\r
+ #define HASHCRYPT ((HASHCRYPT_Type *)HASHCRYPT_BASE)\r
+ /** Array initializer of HASHCRYPT peripheral base addresses */\r
+ #define HASHCRYPT_BASE_ADDRS { HASHCRYPT_BASE }\r
+ /** Array initializer of HASHCRYPT peripheral base pointers */\r
+ #define HASHCRYPT_BASE_PTRS { HASHCRYPT }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group HASHCRYPT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2C Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** I2C - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[2048];\r
+ __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */\r
+ __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */\r
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */\r
+ __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */\r
+ __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */\r
+ __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */\r
+ __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */\r
+ __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */\r
+ uint8_t RESERVED_2[20];\r
+ __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */\r
+ __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */\r
+ __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */\r
+ __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */\r
+ uint8_t RESERVED_3[36];\r
+ __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */\r
+ uint8_t RESERVED_4[1912];\r
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */\r
+} I2C_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2C Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2C_Register_Masks I2C Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG - Configuration for shared functions. */\r
+/*! @{ */\r
+#define I2C_CFG_MSTEN_MASK (0x1U)\r
+#define I2C_CFG_MSTEN_SHIFT (0U)\r
+/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset.\r
+ * 0b0..Disabled. The I2C Master function is disabled.\r
+ * 0b1..Enabled. The I2C Master function is enabled.\r
+ */\r
+#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)\r
+#define I2C_CFG_SLVEN_MASK (0x2U)\r
+#define I2C_CFG_SLVEN_SHIFT (1U)\r
+/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset.\r
+ * 0b0..Disabled. The I2C slave function is disabled.\r
+ * 0b1..Enabled. The I2C slave function is enabled.\r
+ */\r
+#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)\r
+#define I2C_CFG_MONEN_MASK (0x4U)\r
+#define I2C_CFG_MONEN_SHIFT (2U)\r
+/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset.\r
+ * 0b0..Disabled. The I2C Monitor function is disabled.\r
+ * 0b1..Enabled. The I2C Monitor function is enabled.\r
+ */\r
+#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)\r
+#define I2C_CFG_TIMEOUTEN_MASK (0x8U)\r
+#define I2C_CFG_TIMEOUTEN_SHIFT (3U)\r
+/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset.\r
+ * 0b0..Disabled. Time-out function is disabled.\r
+ * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system.\r
+ */\r
+#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)\r
+#define I2C_CFG_MONCLKSTR_MASK (0x10U)\r
+#define I2C_CFG_MONCLKSTR_SHIFT (4U)\r
+/*! MONCLKSTR - Monitor function Clock Stretching.\r
+ * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical.\r
+ * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function.\r
+ */\r
+#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)\r
+#define I2C_CFG_HSCAPABLE_MASK (0x20U)\r
+#define I2C_CFG_HSCAPABLE_SHIFT (5U)\r
+/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor.\r
+ * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin,\r
+ * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information.\r
+ */\r
+#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */\r
+/*! @{ */\r
+#define I2C_STAT_MSTPENDING_MASK (0x1U)\r
+#define I2C_STAT_MSTPENDING_SHIFT (0U)\r
+/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt.\r
+ * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command.\r
+ * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit.\r
+ */\r
+#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)\r
+#define I2C_STAT_MSTSTATE_MASK (0xEU)\r
+#define I2C_STAT_MSTSTATE_SHIFT (1U)\r
+/*! MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses.\r
+ * 0b000..Idle. The Master function is available to be used for a new transaction.\r
+ * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave.\r
+ * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave.\r
+ * 0b011..NACK Address. Slave NACKed address.\r
+ * 0b100..NACK Data. Slave NACKed transmitted data.\r
+ */\r
+#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)\r
+#define I2C_STAT_MSTARBLOSS_MASK (0x10U)\r
+#define I2C_STAT_MSTARBLOSS_SHIFT (4U)\r
+/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.\r
+ * 0b0..No Arbitration Loss has occurred.\r
+ * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle.\r
+ */\r
+#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)\r
+#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)\r
+#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)\r
+/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE.\r
+ * 0b0..No Start/Stop Error has occurred.\r
+ * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled.\r
+ */\r
+#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)\r
+#define I2C_STAT_SLVPENDING_MASK (0x100U)\r
+#define I2C_STAT_SLVPENDING_SHIFT (8U)\r
+/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched.\r
+ * 0b0..In progress. The Slave function does not currently need service.\r
+ * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field.\r
+ */\r
+#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)\r
+#define I2C_STAT_SLVSTATE_MASK (0x600U)\r
+#define I2C_STAT_SLVSTATE_SHIFT (9U)\r
+/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes.\r
+ * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware.\r
+ * 0b01..Slave receive. Received data is available (Slave Receiver mode).\r
+ * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode).\r
+ */\r
+#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)\r
+#define I2C_STAT_SLVNOTSTR_MASK (0x800U)\r
+#define I2C_STAT_SLVNOTSTR_SHIFT (11U)\r
+/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time.\r
+ * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time.\r
+ * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time.\r
+ */\r
+#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)\r
+#define I2C_STAT_SLVIDX_MASK (0x3000U)\r
+#define I2C_STAT_SLVIDX_SHIFT (12U)\r
+/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here.\r
+ * 0b00..Address 0. Slave address 0 was matched.\r
+ * 0b01..Address 1. Slave address 1 was matched.\r
+ * 0b10..Address 2. Slave address 2 was matched.\r
+ * 0b11..Address 3. Slave address 3 was matched.\r
+ */\r
+#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)\r
+#define I2C_STAT_SLVSEL_MASK (0x4000U)\r
+#define I2C_STAT_SLVSEL_SHIFT (14U)\r
+/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data.\r
+ * 0b0..Not selected. The Slave function is not currently selected.\r
+ * 0b1..Selected. The Slave function is currently selected.\r
+ */\r
+#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)\r
+#define I2C_STAT_SLVDESEL_MASK (0x8000U)\r
+#define I2C_STAT_SLVDESEL_SHIFT (15U)\r
+/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit.\r
+ * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag.\r
+ * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs.\r
+ */\r
+#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)\r
+#define I2C_STAT_MONRDY_MASK (0x10000U)\r
+#define I2C_STAT_MONRDY_SHIFT (16U)\r
+/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read.\r
+ * 0b0..No data. The Monitor function does not currently have data available.\r
+ * 0b1..Data waiting. The Monitor function has data waiting to be read.\r
+ */\r
+#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)\r
+#define I2C_STAT_MONOV_MASK (0x20000U)\r
+#define I2C_STAT_MONOV_SHIFT (17U)\r
+/*! MONOV - Monitor Overflow flag.\r
+ * 0b0..No overrun. Monitor data has not overrun.\r
+ * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag.\r
+ */\r
+#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)\r
+#define I2C_STAT_MONACTIVE_MASK (0x40000U)\r
+#define I2C_STAT_MONACTIVE_SHIFT (18U)\r
+/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop.\r
+ * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive.\r
+ * 0b1..Active. The Monitor function considers the I2C bus to be active.\r
+ */\r
+#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)\r
+#define I2C_STAT_MONIDLE_MASK (0x80000U)\r
+#define I2C_STAT_MONIDLE_SHIFT (19U)\r
+/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit.\r
+ * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software.\r
+ * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software.\r
+ */\r
+#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)\r
+#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)\r
+#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)\r
+/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle.\r
+ * 0b0..No time-out. I2C bus events have not caused a time-out.\r
+ * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register.\r
+ */\r
+#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)\r
+#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)\r
+#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)\r
+/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit.\r
+ * 0b0..No time-out. SCL low time has not caused a time-out.\r
+ * 0b1..Time-out. SCL low time has caused a time-out.\r
+ */\r
+#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Interrupt Enable Set and read register. */\r
+/*! @{ */\r
+#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)\r
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)\r
+/*! MSTPENDINGEN - Master Pending interrupt Enable.\r
+ * 0b0..Disabled. The MstPending interrupt is disabled.\r
+ * 0b1..Enabled. The MstPending interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)\r
+#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)\r
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)\r
+/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable.\r
+ * 0b0..Disabled. The MstArbLoss interrupt is disabled.\r
+ * 0b1..Enabled. The MstArbLoss interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)\r
+#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)\r
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)\r
+/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable.\r
+ * 0b0..Disabled. The MstStStpErr interrupt is disabled.\r
+ * 0b1..Enabled. The MstStStpErr interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)\r
+#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)\r
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)\r
+/*! SLVPENDINGEN - Slave Pending interrupt Enable.\r
+ * 0b0..Disabled. The SlvPending interrupt is disabled.\r
+ * 0b1..Enabled. The SlvPending interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)\r
+#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)\r
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)\r
+/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable.\r
+ * 0b0..Disabled. The SlvNotStr interrupt is disabled.\r
+ * 0b1..Enabled. The SlvNotStr interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)\r
+#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)\r
+#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)\r
+/*! SLVDESELEN - Slave Deselect interrupt Enable.\r
+ * 0b0..Disabled. The SlvDeSel interrupt is disabled.\r
+ * 0b1..Enabled. The SlvDeSel interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)\r
+#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)\r
+#define I2C_INTENSET_MONRDYEN_SHIFT (16U)\r
+/*! MONRDYEN - Monitor data Ready interrupt Enable.\r
+ * 0b0..Disabled. The MonRdy interrupt is disabled.\r
+ * 0b1..Enabled. The MonRdy interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)\r
+#define I2C_INTENSET_MONOVEN_MASK (0x20000U)\r
+#define I2C_INTENSET_MONOVEN_SHIFT (17U)\r
+/*! MONOVEN - Monitor Overrun interrupt Enable.\r
+ * 0b0..Disabled. The MonOv interrupt is disabled.\r
+ * 0b1..Enabled. The MonOv interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)\r
+#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)\r
+#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)\r
+/*! MONIDLEEN - Monitor Idle interrupt Enable.\r
+ * 0b0..Disabled. The MonIdle interrupt is disabled.\r
+ * 0b1..Enabled. The MonIdle interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)\r
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)\r
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)\r
+/*! EVENTTIMEOUTEN - Event time-out interrupt Enable.\r
+ * 0b0..Disabled. The Event time-out interrupt is disabled.\r
+ * 0b1..Enabled. The Event time-out interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)\r
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)\r
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)\r
+/*! SCLTIMEOUTEN - SCL time-out interrupt Enable.\r
+ * 0b0..Disabled. The SCL time-out interrupt is disabled.\r
+ * 0b1..Enabled. The SCL time-out interrupt is enabled.\r
+ */\r
+#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Interrupt Enable Clear register. */\r
+/*! @{ */\r
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)\r
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)\r
+#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)\r
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)\r
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)\r
+#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)\r
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)\r
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)\r
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)\r
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)\r
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)\r
+#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)\r
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)\r
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)\r
+#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)\r
+#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)\r
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)\r
+#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)\r
+#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)\r
+#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)\r
+#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)\r
+#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)\r
+#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)\r
+#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)\r
+#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)\r
+#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)\r
+#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)\r
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)\r
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)\r
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)\r
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)\r
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)\r
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name TIMEOUT - Time-out value register. */\r
+/*! @{ */\r
+#define I2C_TIMEOUT_TOMIN_MASK (0xFU)\r
+#define I2C_TIMEOUT_TOMIN_SHIFT (0U)\r
+#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)\r
+#define I2C_TIMEOUT_TO_MASK (0xFFF0U)\r
+#define I2C_TIMEOUT_TO_SHIFT (4U)\r
+#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */\r
+/*! @{ */\r
+#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)\r
+#define I2C_CLKDIV_DIVVAL_SHIFT (0U)\r
+#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */\r
+/*! @{ */\r
+#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)\r
+#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)\r
+#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)\r
+#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)\r
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)\r
+#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)\r
+#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)\r
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)\r
+#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)\r
+#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)\r
+#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)\r
+#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)\r
+#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)\r
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)\r
+#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)\r
+#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)\r
+#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)\r
+#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)\r
+#define I2C_INTSTAT_MONRDY_MASK (0x10000U)\r
+#define I2C_INTSTAT_MONRDY_SHIFT (16U)\r
+#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)\r
+#define I2C_INTSTAT_MONOV_MASK (0x20000U)\r
+#define I2C_INTSTAT_MONOV_SHIFT (17U)\r
+#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)\r
+#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)\r
+#define I2C_INTSTAT_MONIDLE_SHIFT (19U)\r
+#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)\r
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)\r
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)\r
+#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)\r
+#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)\r
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)\r
+#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSTCTL - Master control register. */\r
+/*! @{ */\r
+#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)\r
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)\r
+/*! MSTCONTINUE - Master Continue. This bit is write-only.\r
+ * 0b0..No effect.\r
+ * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation.\r
+ */\r
+#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)\r
+#define I2C_MSTCTL_MSTSTART_MASK (0x2U)\r
+#define I2C_MSTCTL_MSTSTART_SHIFT (1U)\r
+/*! MSTSTART - Master Start control. This bit is write-only.\r
+ * 0b0..No effect.\r
+ * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time.\r
+ */\r
+#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)\r
+#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)\r
+#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)\r
+/*! MSTSTOP - Master Stop control. This bit is write-only.\r
+ * 0b0..No effect.\r
+ * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode).\r
+ */\r
+#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)\r
+#define I2C_MSTCTL_MSTDMA_MASK (0x8U)\r
+#define I2C_MSTCTL_MSTDMA_SHIFT (3U)\r
+/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write.\r
+ * 0b0..Disable. No DMA requests are generated for master operation.\r
+ * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically.\r
+ */\r
+#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSTTIME - Master timing configuration. */\r
+/*! @{ */\r
+#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)\r
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)\r
+/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW.\r
+ * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider.\r
+ * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider.\r
+ * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider.\r
+ * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider.\r
+ * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider.\r
+ * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider.\r
+ * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider.\r
+ * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider.\r
+ */\r
+#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)\r
+#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)\r
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)\r
+/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH.\r
+ * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider.\r
+ * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider .\r
+ * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider.\r
+ * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider.\r
+ * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider.\r
+ * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider.\r
+ * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider.\r
+ * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider.\r
+ */\r
+#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)\r
+/*! @} */\r
+\r
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */\r
+/*! @{ */\r
+#define I2C_MSTDAT_DATA_MASK (0xFFU)\r
+#define I2C_MSTDAT_DATA_SHIFT (0U)\r
+#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name SLVCTL - Slave control register. */\r
+/*! @{ */\r
+#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)\r
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)\r
+/*! SLVCONTINUE - Slave Continue.\r
+ * 0b0..No effect.\r
+ * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1.\r
+ */\r
+#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)\r
+#define I2C_SLVCTL_SLVNACK_MASK (0x2U)\r
+#define I2C_SLVCTL_SLVNACK_SHIFT (1U)\r
+/*! SLVNACK - Slave NACK.\r
+ * 0b0..No effect.\r
+ * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode).\r
+ */\r
+#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)\r
+#define I2C_SLVCTL_SLVDMA_MASK (0x8U)\r
+#define I2C_SLVCTL_SLVDMA_SHIFT (3U)\r
+/*! SLVDMA - Slave DMA enable.\r
+ * 0b0..Disabled. No DMA requests are issued for Slave mode operation.\r
+ * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception.\r
+ */\r
+#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)\r
+#define I2C_SLVCTL_AUTOACK_MASK (0x100U)\r
+#define I2C_SLVCTL_AUTOACK_SHIFT (8U)\r
+/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt.\r
+ * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored).\r
+ * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated.\r
+ */\r
+#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)\r
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)\r
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)\r
+/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation.\r
+ * 0b0..The expected next operation in Automatic Mode is an I2C write.\r
+ * 0b1..The expected next operation in Automatic Mode is an I2C read.\r
+ */\r
+#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)\r
+/*! @} */\r
+\r
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */\r
+/*! @{ */\r
+#define I2C_SLVDAT_DATA_MASK (0xFFU)\r
+#define I2C_SLVDAT_DATA_SHIFT (0U)\r
+#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name SLVADR - Slave address register. */\r
+/*! @{ */\r
+#define I2C_SLVADR_SADISABLE_MASK (0x1U)\r
+#define I2C_SLVADR_SADISABLE_SHIFT (0U)\r
+/*! SADISABLE - Slave Address n Disable.\r
+ * 0b0..Enabled. Slave Address n is enabled.\r
+ * 0b1..Ignored Slave Address n is ignored.\r
+ */\r
+#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)\r
+#define I2C_SLVADR_SLVADR_MASK (0xFEU)\r
+#define I2C_SLVADR_SLVADR_SHIFT (1U)\r
+#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)\r
+#define I2C_SLVADR_AUTONACK_MASK (0x8000U)\r
+#define I2C_SLVADR_AUTONACK_SHIFT (15U)\r
+/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations.\r
+ * 0b0..Normal operation, matching I2C addresses are not ignored.\r
+ * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction.\r
+ */\r
+#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2C_SLVADR */\r
+#define I2C_SLVADR_COUNT (4U)\r
+\r
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */\r
+/*! @{ */\r
+#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)\r
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)\r
+/*! QUALMODE0 - Qualify mode for slave address 0.\r
+ * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.\r
+ * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses.\r
+ */\r
+#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)\r
+#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)\r
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)\r
+#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)\r
+/*! @} */\r
+\r
+/*! @name MONRXDAT - Monitor receiver data register. */\r
+/*! @{ */\r
+#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)\r
+#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)\r
+#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)\r
+#define I2C_MONRXDAT_MONSTART_MASK (0x100U)\r
+#define I2C_MONRXDAT_MONSTART_SHIFT (8U)\r
+/*! MONSTART - Monitor Received Start.\r
+ * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus.\r
+ * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus.\r
+ */\r
+#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)\r
+#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)\r
+#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)\r
+/*! MONRESTART - Monitor Received Repeated Start.\r
+ * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus.\r
+ * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus.\r
+ */\r
+#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)\r
+#define I2C_MONRXDAT_MONNACK_MASK (0x400U)\r
+#define I2C_MONRXDAT_MONNACK_SHIFT (10U)\r
+/*! MONNACK - Monitor Received NACK.\r
+ * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver.\r
+ * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver.\r
+ */\r
+#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Peripheral identification register. */\r
+/*! @{ */\r
+#define I2C_ID_APERTURE_MASK (0xFFU)\r
+#define I2C_ID_APERTURE_SHIFT (0U)\r
+#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)\r
+#define I2C_ID_MINOR_REV_MASK (0xF00U)\r
+#define I2C_ID_MINOR_REV_SHIFT (8U)\r
+#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)\r
+#define I2C_ID_MAJOR_REV_MASK (0xF000U)\r
+#define I2C_ID_MAJOR_REV_SHIFT (12U)\r
+#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)\r
+#define I2C_ID_ID_MASK (0xFFFF0000U)\r
+#define I2C_ID_ID_SHIFT (16U)\r
+#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2C_Register_Masks */\r
+\r
+\r
+/* I2C - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral I2C0 base address */\r
+ #define I2C0_BASE (0x50086000u)\r
+ /** Peripheral I2C0 base address */\r
+ #define I2C0_BASE_NS (0x40086000u)\r
+ /** Peripheral I2C0 base pointer */\r
+ #define I2C0 ((I2C_Type *)I2C0_BASE)\r
+ /** Peripheral I2C0 base pointer */\r
+ #define I2C0_NS ((I2C_Type *)I2C0_BASE_NS)\r
+ /** Peripheral I2C1 base address */\r
+ #define I2C1_BASE (0x50087000u)\r
+ /** Peripheral I2C1 base address */\r
+ #define I2C1_BASE_NS (0x40087000u)\r
+ /** Peripheral I2C1 base pointer */\r
+ #define I2C1 ((I2C_Type *)I2C1_BASE)\r
+ /** Peripheral I2C1 base pointer */\r
+ #define I2C1_NS ((I2C_Type *)I2C1_BASE_NS)\r
+ /** Peripheral I2C2 base address */\r
+ #define I2C2_BASE (0x50088000u)\r
+ /** Peripheral I2C2 base address */\r
+ #define I2C2_BASE_NS (0x40088000u)\r
+ /** Peripheral I2C2 base pointer */\r
+ #define I2C2 ((I2C_Type *)I2C2_BASE)\r
+ /** Peripheral I2C2 base pointer */\r
+ #define I2C2_NS ((I2C_Type *)I2C2_BASE_NS)\r
+ /** Peripheral I2C3 base address */\r
+ #define I2C3_BASE (0x50089000u)\r
+ /** Peripheral I2C3 base address */\r
+ #define I2C3_BASE_NS (0x40089000u)\r
+ /** Peripheral I2C3 base pointer */\r
+ #define I2C3 ((I2C_Type *)I2C3_BASE)\r
+ /** Peripheral I2C3 base pointer */\r
+ #define I2C3_NS ((I2C_Type *)I2C3_BASE_NS)\r
+ /** Peripheral I2C4 base address */\r
+ #define I2C4_BASE (0x5008A000u)\r
+ /** Peripheral I2C4 base address */\r
+ #define I2C4_BASE_NS (0x4008A000u)\r
+ /** Peripheral I2C4 base pointer */\r
+ #define I2C4 ((I2C_Type *)I2C4_BASE)\r
+ /** Peripheral I2C4 base pointer */\r
+ #define I2C4_NS ((I2C_Type *)I2C4_BASE_NS)\r
+ /** Peripheral I2C5 base address */\r
+ #define I2C5_BASE (0x50096000u)\r
+ /** Peripheral I2C5 base address */\r
+ #define I2C5_BASE_NS (0x40096000u)\r
+ /** Peripheral I2C5 base pointer */\r
+ #define I2C5 ((I2C_Type *)I2C5_BASE)\r
+ /** Peripheral I2C5 base pointer */\r
+ #define I2C5_NS ((I2C_Type *)I2C5_BASE_NS)\r
+ /** Peripheral I2C6 base address */\r
+ #define I2C6_BASE (0x50097000u)\r
+ /** Peripheral I2C6 base address */\r
+ #define I2C6_BASE_NS (0x40097000u)\r
+ /** Peripheral I2C6 base pointer */\r
+ #define I2C6 ((I2C_Type *)I2C6_BASE)\r
+ /** Peripheral I2C6 base pointer */\r
+ #define I2C6_NS ((I2C_Type *)I2C6_BASE_NS)\r
+ /** Peripheral I2C7 base address */\r
+ #define I2C7_BASE (0x50098000u)\r
+ /** Peripheral I2C7 base address */\r
+ #define I2C7_BASE_NS (0x40098000u)\r
+ /** Peripheral I2C7 base pointer */\r
+ #define I2C7 ((I2C_Type *)I2C7_BASE)\r
+ /** Peripheral I2C7 base pointer */\r
+ #define I2C7_NS ((I2C_Type *)I2C7_BASE_NS)\r
+ /** Array initializer of I2C peripheral base addresses */\r
+ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }\r
+ /** Array initializer of I2C peripheral base pointers */\r
+ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }\r
+ /** Array initializer of I2C peripheral base addresses */\r
+ #define I2C_BASE_ADDRS_NS { I2C0_BASE_NS, I2C1_BASE_NS, I2C2_BASE_NS, I2C3_BASE_NS, I2C4_BASE_NS, I2C5_BASE_NS, I2C6_BASE_NS, I2C7_BASE_NS }\r
+ /** Array initializer of I2C peripheral base pointers */\r
+ #define I2C_BASE_PTRS_NS { I2C0_NS, I2C1_NS, I2C2_NS, I2C3_NS, I2C4_NS, I2C5_NS, I2C6_NS, I2C7_NS }\r
+#else\r
+ /** Peripheral I2C0 base address */\r
+ #define I2C0_BASE (0x40086000u)\r
+ /** Peripheral I2C0 base pointer */\r
+ #define I2C0 ((I2C_Type *)I2C0_BASE)\r
+ /** Peripheral I2C1 base address */\r
+ #define I2C1_BASE (0x40087000u)\r
+ /** Peripheral I2C1 base pointer */\r
+ #define I2C1 ((I2C_Type *)I2C1_BASE)\r
+ /** Peripheral I2C2 base address */\r
+ #define I2C2_BASE (0x40088000u)\r
+ /** Peripheral I2C2 base pointer */\r
+ #define I2C2 ((I2C_Type *)I2C2_BASE)\r
+ /** Peripheral I2C3 base address */\r
+ #define I2C3_BASE (0x40089000u)\r
+ /** Peripheral I2C3 base pointer */\r
+ #define I2C3 ((I2C_Type *)I2C3_BASE)\r
+ /** Peripheral I2C4 base address */\r
+ #define I2C4_BASE (0x4008A000u)\r
+ /** Peripheral I2C4 base pointer */\r
+ #define I2C4 ((I2C_Type *)I2C4_BASE)\r
+ /** Peripheral I2C5 base address */\r
+ #define I2C5_BASE (0x40096000u)\r
+ /** Peripheral I2C5 base pointer */\r
+ #define I2C5 ((I2C_Type *)I2C5_BASE)\r
+ /** Peripheral I2C6 base address */\r
+ #define I2C6_BASE (0x40097000u)\r
+ /** Peripheral I2C6 base pointer */\r
+ #define I2C6 ((I2C_Type *)I2C6_BASE)\r
+ /** Peripheral I2C7 base address */\r
+ #define I2C7_BASE (0x40098000u)\r
+ /** Peripheral I2C7 base pointer */\r
+ #define I2C7 ((I2C_Type *)I2C7_BASE)\r
+ /** Array initializer of I2C peripheral base addresses */\r
+ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE }\r
+ /** Array initializer of I2C peripheral base pointers */\r
+ #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 }\r
+#endif\r
+/** Interrupt vectors for the I2C peripheral type */\r
+#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2C_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2S Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** I2S - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[3072];\r
+ __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */\r
+ __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */\r
+ __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */\r
+ struct { /* offset: 0xC20, array step: 0x20 */\r
+ __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */\r
+ __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */\r
+ __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */\r
+ uint8_t RESERVED_0[20];\r
+ } SECCHANNEL[3];\r
+ uint8_t RESERVED_2[384];\r
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */\r
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */\r
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */\r
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */\r
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */\r
+ uint8_t RESERVED_4[4];\r
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */\r
+ __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */\r
+ uint8_t RESERVED_5[8];\r
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */\r
+ __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */\r
+ uint8_t RESERVED_6[8];\r
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */\r
+ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */\r
+ uint8_t RESERVED_7[436];\r
+ __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */\r
+} I2S_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- I2S Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup I2S_Register_Masks I2S Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */\r
+/*! @{ */\r
+#define I2S_CFG1_MAINENABLE_MASK (0x1U)\r
+#define I2S_CFG1_MAINENABLE_SHIFT (0U)\r
+/*! MAINENABLE - Main enable for I 2S function in this Flexcomm\r
+ * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled.\r
+ * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits.\r
+ */\r
+#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)\r
+#define I2S_CFG1_DATAPAUSE_MASK (0x2U)\r
+#define I2S_CFG1_DATAPAUSE_SHIFT (1U)\r
+/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame.\r
+ * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused.\r
+ * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1.\r
+ */\r
+#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)\r
+#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)\r
+#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)\r
+/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.\r
+ * 0b00..1 I2S channel pairs in this flexcomm\r
+ * 0b01..2 I2S channel pairs in this flexcomm\r
+ * 0b10..3 I2S channel pairs in this flexcomm\r
+ * 0b11..4 I2S channel pairs in this flexcomm\r
+ */\r
+#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)\r
+#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)\r
+#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)\r
+/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.\r
+ * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data.\r
+ * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock.\r
+ * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data.\r
+ * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices.\r
+ */\r
+#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)\r
+#define I2S_CFG1_MODE_MASK (0xC0U)\r
+#define I2S_CFG1_MODE_SHIFT (6U)\r
+/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples.\r
+ * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right.\r
+ * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0.\r
+ * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame.\r
+ * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame.\r
+ */\r
+#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)\r
+#define I2S_CFG1_RIGHTLOW_MASK (0x100U)\r
+#define I2S_CFG1_RIGHTLOW_SHIFT (8U)\r
+/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.\r
+ * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel.\r
+ * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel.\r
+ */\r
+#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)\r
+#define I2S_CFG1_LEFTJUST_MASK (0x200U)\r
+#define I2S_CFG1_LEFTJUST_SHIFT (9U)\r
+/*! LEFTJUST - Left Justify data.\r
+ * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus.\r
+ * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus.\r
+ */\r
+#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)\r
+#define I2S_CFG1_ONECHANNEL_MASK (0x400U)\r
+#define I2S_CFG1_ONECHANNEL_SHIFT (10U)\r
+/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.\r
+ * 0b0..I2S data for this channel pair is treated as left and right channels.\r
+ * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION.\r
+ */\r
+#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)\r
+#define I2S_CFG1_PDMDATA_MASK (0x800U)\r
+#define I2S_CFG1_PDMDATA_SHIFT (11U)\r
+/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7.\r
+ * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO.\r
+ * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun.\r
+ */\r
+#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)\r
+#define I2S_CFG1_SCK_POL_MASK (0x1000U)\r
+#define I2S_CFG1_SCK_POL_SHIFT (12U)\r
+/*! SCK_POL - SCK polarity.\r
+ * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S).\r
+ * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges.\r
+ */\r
+#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)\r
+#define I2S_CFG1_WS_POL_MASK (0x2000U)\r
+#define I2S_CFG1_WS_POL_SHIFT (13U)\r
+/*! WS_POL - WS polarity.\r
+ * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S).\r
+ * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S).\r
+ */\r
+#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)\r
+#define I2S_CFG1_DATALEN_MASK (0x1F0000U)\r
+#define I2S_CFG1_DATALEN_SHIFT (16U)\r
+#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */\r
+/*! @{ */\r
+#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)\r
+#define I2S_CFG2_FRAMELEN_SHIFT (0U)\r
+#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)\r
+#define I2S_CFG2_POSITION_MASK (0x1FF0000U)\r
+#define I2S_CFG2_POSITION_SHIFT (16U)\r
+#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - Status register for the primary channel pair. */\r
+/*! @{ */\r
+#define I2S_STAT_BUSY_MASK (0x1U)\r
+#define I2S_STAT_BUSY_SHIFT (0U)\r
+/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair.\r
+ * 0b0..The transmitter/receiver for channel pair is currently idle.\r
+ * 0b1..The transmitter/receiver for channel pair is currently processing data.\r
+ */\r
+#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)\r
+#define I2S_STAT_SLVFRMERR_MASK (0x2U)\r
+#define I2S_STAT_SLVFRMERR_SHIFT (1U)\r
+/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream.\r
+ * 0b0..No error has been recorded.\r
+ * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position.\r
+ */\r
+#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)\r
+#define I2S_STAT_LR_MASK (0x4U)\r
+#define I2S_STAT_LR_SHIFT (2U)\r
+/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair.\r
+ * 0b0..Left channel.\r
+ * 0b1..Right channel.\r
+ */\r
+#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)\r
+#define I2S_STAT_DATAPAUSED_MASK (0x8U)\r
+#define I2S_STAT_DATAPAUSED_SHIFT (3U)\r
+/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels\r
+ * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register.\r
+ * 0b1..A data pause has been requested and is now in force.\r
+ */\r
+#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)\r
+/*! @} */\r
+\r
+/*! @name DIV - Clock divider, used by all channel pairs. */\r
+/*! @{ */\r
+#define I2S_DIV_DIV_MASK (0xFFFU)\r
+#define I2S_DIV_DIV_SHIFT (0U)\r
+#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)\r
+/*! @} */\r
+\r
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */\r
+/*! @{ */\r
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)\r
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)\r
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)\r
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)\r
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)\r
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2S_SECCHANNEL_PCFG1 */\r
+#define I2S_SECCHANNEL_PCFG1_COUNT (3U)\r
+\r
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */\r
+/*! @{ */\r
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)\r
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)\r
+#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2S_SECCHANNEL_PCFG2 */\r
+#define I2S_SECCHANNEL_PCFG2_COUNT (3U)\r
+\r
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */\r
+/*! @{ */\r
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)\r
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)\r
+#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)\r
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)\r
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)\r
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)\r
+#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)\r
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)\r
+#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)\r
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)\r
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)\r
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)\r
+/*! @} */\r
+\r
+/* The count of I2S_SECCHANNEL_PSTAT */\r
+#define I2S_SECCHANNEL_PSTAT_COUNT (3U)\r
+\r
+/*! @name FIFOCFG - FIFO configuration and enable register. */\r
+/*! @{ */\r
+#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)\r
+#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)\r
+/*! ENABLETX - Enable the transmit FIFO.\r
+ * 0b0..The transmit FIFO is not enabled.\r
+ * 0b1..The transmit FIFO is enabled.\r
+ */\r
+#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)\r
+#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)\r
+#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)\r
+/*! ENABLERX - Enable the receive FIFO.\r
+ * 0b0..The receive FIFO is not enabled.\r
+ * 0b1..The receive FIFO is enabled.\r
+ */\r
+#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)\r
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)\r
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)\r
+/*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.\r
+ * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair.\r
+ * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred.\r
+ */\r
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)\r
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)\r
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)\r
+/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.\r
+ * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values.\r
+ * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values.\r
+ */\r
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)\r
+#define I2S_FIFOCFG_SIZE_MASK (0x30U)\r
+#define I2S_FIFOCFG_SIZE_SHIFT (4U)\r
+#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)\r
+#define I2S_FIFOCFG_DMATX_MASK (0x1000U)\r
+#define I2S_FIFOCFG_DMATX_SHIFT (12U)\r
+/*! DMATX - DMA configuration for transmit.\r
+ * 0b0..DMA is not used for the transmit function.\r
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)\r
+#define I2S_FIFOCFG_DMARX_MASK (0x2000U)\r
+#define I2S_FIFOCFG_DMARX_SHIFT (13U)\r
+/*! DMARX - DMA configuration for receive.\r
+ * 0b0..DMA is not used for the receive function.\r
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)\r
+#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)\r
+#define I2S_FIFOCFG_WAKETX_SHIFT (14U)\r
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.\r
+ */\r
+#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)\r
+#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)\r
+#define I2S_FIFOCFG_WAKERX_SHIFT (15U)\r
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.\r
+ */\r
+#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)\r
+#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)\r
+#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)\r
+#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)\r
+#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)\r
+#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)\r
+#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)\r
+#define I2S_FIFOCFG_POPDBG_MASK (0x40000U)\r
+#define I2S_FIFOCFG_POPDBG_SHIFT (18U)\r
+/*! POPDBG - Pop FIFO for debug reads.\r
+ * 0b0..Debug reads of the FIFO do not pop the FIFO.\r
+ * 0b1..A debug read will cause the FIFO to pop.\r
+ */\r
+#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOSTAT - FIFO status register. */\r
+/*! @{ */\r
+#define I2S_FIFOSTAT_TXERR_MASK (0x1U)\r
+#define I2S_FIFOSTAT_TXERR_SHIFT (0U)\r
+#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)\r
+#define I2S_FIFOSTAT_RXERR_MASK (0x2U)\r
+#define I2S_FIFOSTAT_RXERR_SHIFT (1U)\r
+#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)\r
+#define I2S_FIFOSTAT_PERINT_MASK (0x8U)\r
+#define I2S_FIFOSTAT_PERINT_SHIFT (3U)\r
+#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)\r
+#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)\r
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)\r
+#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)\r
+#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)\r
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)\r
+#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)\r
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)\r
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)\r
+#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)\r
+#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)\r
+#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)\r
+#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)\r
+#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)\r
+#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)\r
+#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)\r
+#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)\r
+#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)\r
+#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */\r
+/*! @{ */\r
+#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)\r
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)\r
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\r
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.\r
+ */\r
+#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)\r
+#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)\r
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)\r
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\r
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.\r
+ */\r
+#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)\r
+#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)\r
+#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)\r
+#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)\r
+#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)\r
+#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)\r
+#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */\r
+/*! @{ */\r
+#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)\r
+#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)\r
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a transmit error.\r
+ * 0b1..An interrupt will be generated when a transmit error occurs.\r
+ */\r
+#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)\r
+#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)\r
+#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)\r
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a receive error.\r
+ * 0b1..An interrupt will be generated when a receive error occurs.\r
+ */\r
+#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)\r
+#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)\r
+#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the TX FIFO level.\r
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.\r
+ */\r
+#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)\r
+#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)\r
+#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the RX FIFO level.\r
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.\r
+ */\r
+#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */\r
+/*! @{ */\r
+#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)\r
+#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)\r
+#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)\r
+#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)\r
+#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)\r
+#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)\r
+#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)\r
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)\r
+#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)\r
+#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)\r
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)\r
+#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */\r
+/*! @{ */\r
+#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)\r
+#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)\r
+#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)\r
+#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)\r
+#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)\r
+#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)\r
+#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)\r
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)\r
+#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)\r
+#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)\r
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)\r
+#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)\r
+#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)\r
+#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)\r
+#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR - FIFO write data. */\r
+/*! @{ */\r
+#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)\r
+#define I2S_FIFOWR_TXDATA_SHIFT (0U)\r
+#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */\r
+/*! @{ */\r
+#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)\r
+#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)\r
+#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD - FIFO read data. */\r
+/*! @{ */\r
+#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)\r
+#define I2S_FIFORD_RXDATA_SHIFT (0U)\r
+#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */\r
+/*! @{ */\r
+#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)\r
+#define I2S_FIFORD48H_RXDATA_SHIFT (0U)\r
+#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */\r
+/*! @{ */\r
+#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)\r
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)\r
+#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */\r
+/*! @{ */\r
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)\r
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)\r
+#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - I2S Module identification */\r
+/*! @{ */\r
+#define I2S_ID_Aperture_MASK (0xFFU)\r
+#define I2S_ID_Aperture_SHIFT (0U)\r
+#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)\r
+#define I2S_ID_Minor_Rev_MASK (0xF00U)\r
+#define I2S_ID_Minor_Rev_SHIFT (8U)\r
+#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)\r
+#define I2S_ID_Major_Rev_MASK (0xF000U)\r
+#define I2S_ID_Major_Rev_SHIFT (12U)\r
+#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)\r
+#define I2S_ID_ID_MASK (0xFFFF0000U)\r
+#define I2S_ID_ID_SHIFT (16U)\r
+#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2S_Register_Masks */\r
+\r
+\r
+/* I2S - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral I2S0 base address */\r
+ #define I2S0_BASE (0x50086000u)\r
+ /** Peripheral I2S0 base address */\r
+ #define I2S0_BASE_NS (0x40086000u)\r
+ /** Peripheral I2S0 base pointer */\r
+ #define I2S0 ((I2S_Type *)I2S0_BASE)\r
+ /** Peripheral I2S0 base pointer */\r
+ #define I2S0_NS ((I2S_Type *)I2S0_BASE_NS)\r
+ /** Peripheral I2S1 base address */\r
+ #define I2S1_BASE (0x50087000u)\r
+ /** Peripheral I2S1 base address */\r
+ #define I2S1_BASE_NS (0x40087000u)\r
+ /** Peripheral I2S1 base pointer */\r
+ #define I2S1 ((I2S_Type *)I2S1_BASE)\r
+ /** Peripheral I2S1 base pointer */\r
+ #define I2S1_NS ((I2S_Type *)I2S1_BASE_NS)\r
+ /** Peripheral I2S2 base address */\r
+ #define I2S2_BASE (0x50088000u)\r
+ /** Peripheral I2S2 base address */\r
+ #define I2S2_BASE_NS (0x40088000u)\r
+ /** Peripheral I2S2 base pointer */\r
+ #define I2S2 ((I2S_Type *)I2S2_BASE)\r
+ /** Peripheral I2S2 base pointer */\r
+ #define I2S2_NS ((I2S_Type *)I2S2_BASE_NS)\r
+ /** Peripheral I2S3 base address */\r
+ #define I2S3_BASE (0x50089000u)\r
+ /** Peripheral I2S3 base address */\r
+ #define I2S3_BASE_NS (0x40089000u)\r
+ /** Peripheral I2S3 base pointer */\r
+ #define I2S3 ((I2S_Type *)I2S3_BASE)\r
+ /** Peripheral I2S3 base pointer */\r
+ #define I2S3_NS ((I2S_Type *)I2S3_BASE_NS)\r
+ /** Peripheral I2S4 base address */\r
+ #define I2S4_BASE (0x5008A000u)\r
+ /** Peripheral I2S4 base address */\r
+ #define I2S4_BASE_NS (0x4008A000u)\r
+ /** Peripheral I2S4 base pointer */\r
+ #define I2S4 ((I2S_Type *)I2S4_BASE)\r
+ /** Peripheral I2S4 base pointer */\r
+ #define I2S4_NS ((I2S_Type *)I2S4_BASE_NS)\r
+ /** Peripheral I2S5 base address */\r
+ #define I2S5_BASE (0x50096000u)\r
+ /** Peripheral I2S5 base address */\r
+ #define I2S5_BASE_NS (0x40096000u)\r
+ /** Peripheral I2S5 base pointer */\r
+ #define I2S5 ((I2S_Type *)I2S5_BASE)\r
+ /** Peripheral I2S5 base pointer */\r
+ #define I2S5_NS ((I2S_Type *)I2S5_BASE_NS)\r
+ /** Peripheral I2S6 base address */\r
+ #define I2S6_BASE (0x50097000u)\r
+ /** Peripheral I2S6 base address */\r
+ #define I2S6_BASE_NS (0x40097000u)\r
+ /** Peripheral I2S6 base pointer */\r
+ #define I2S6 ((I2S_Type *)I2S6_BASE)\r
+ /** Peripheral I2S6 base pointer */\r
+ #define I2S6_NS ((I2S_Type *)I2S6_BASE_NS)\r
+ /** Peripheral I2S7 base address */\r
+ #define I2S7_BASE (0x50098000u)\r
+ /** Peripheral I2S7 base address */\r
+ #define I2S7_BASE_NS (0x40098000u)\r
+ /** Peripheral I2S7 base pointer */\r
+ #define I2S7 ((I2S_Type *)I2S7_BASE)\r
+ /** Peripheral I2S7 base pointer */\r
+ #define I2S7_NS ((I2S_Type *)I2S7_BASE_NS)\r
+ /** Array initializer of I2S peripheral base addresses */\r
+ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }\r
+ /** Array initializer of I2S peripheral base pointers */\r
+ #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }\r
+ /** Array initializer of I2S peripheral base addresses */\r
+ #define I2S_BASE_ADDRS_NS { I2S0_BASE_NS, I2S1_BASE_NS, I2S2_BASE_NS, I2S3_BASE_NS, I2S4_BASE_NS, I2S5_BASE_NS, I2S6_BASE_NS, I2S7_BASE_NS }\r
+ /** Array initializer of I2S peripheral base pointers */\r
+ #define I2S_BASE_PTRS_NS { I2S0_NS, I2S1_NS, I2S2_NS, I2S3_NS, I2S4_NS, I2S5_NS, I2S6_NS, I2S7_NS }\r
+#else\r
+ /** Peripheral I2S0 base address */\r
+ #define I2S0_BASE (0x40086000u)\r
+ /** Peripheral I2S0 base pointer */\r
+ #define I2S0 ((I2S_Type *)I2S0_BASE)\r
+ /** Peripheral I2S1 base address */\r
+ #define I2S1_BASE (0x40087000u)\r
+ /** Peripheral I2S1 base pointer */\r
+ #define I2S1 ((I2S_Type *)I2S1_BASE)\r
+ /** Peripheral I2S2 base address */\r
+ #define I2S2_BASE (0x40088000u)\r
+ /** Peripheral I2S2 base pointer */\r
+ #define I2S2 ((I2S_Type *)I2S2_BASE)\r
+ /** Peripheral I2S3 base address */\r
+ #define I2S3_BASE (0x40089000u)\r
+ /** Peripheral I2S3 base pointer */\r
+ #define I2S3 ((I2S_Type *)I2S3_BASE)\r
+ /** Peripheral I2S4 base address */\r
+ #define I2S4_BASE (0x4008A000u)\r
+ /** Peripheral I2S4 base pointer */\r
+ #define I2S4 ((I2S_Type *)I2S4_BASE)\r
+ /** Peripheral I2S5 base address */\r
+ #define I2S5_BASE (0x40096000u)\r
+ /** Peripheral I2S5 base pointer */\r
+ #define I2S5 ((I2S_Type *)I2S5_BASE)\r
+ /** Peripheral I2S6 base address */\r
+ #define I2S6_BASE (0x40097000u)\r
+ /** Peripheral I2S6 base pointer */\r
+ #define I2S6 ((I2S_Type *)I2S6_BASE)\r
+ /** Peripheral I2S7 base address */\r
+ #define I2S7_BASE (0x40098000u)\r
+ /** Peripheral I2S7 base pointer */\r
+ #define I2S7 ((I2S_Type *)I2S7_BASE)\r
+ /** Array initializer of I2S peripheral base addresses */\r
+ #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE, I2S2_BASE, I2S3_BASE, I2S4_BASE, I2S5_BASE, I2S6_BASE, I2S7_BASE }\r
+ /** Array initializer of I2S peripheral base pointers */\r
+ #define I2S_BASE_PTRS { I2S0, I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7 }\r
+#endif\r
+/** Interrupt vectors for the I2S peripheral type */\r
+#define I2S_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group I2S_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- INPUTMUX Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** INPUTMUX - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t SCT0_INMUX[7]; /**< Input mux register for SCT0 input, array offset: 0x0, array step: 0x4 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t TIMER0CAPTSEL[4]; /**< Capture select registers for TIMER0 inputs, array offset: 0x20, array step: 0x4 */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t TIMER1CAPTSEL[4]; /**< Capture select registers for TIMER1 inputs, array offset: 0x40, array step: 0x4 */\r
+ uint8_t RESERVED_2[16];\r
+ __IO uint32_t TIMER2CAPTSEL[4]; /**< Capture select registers for TIMER2 inputs, array offset: 0x60, array step: 0x4 */\r
+ uint8_t RESERVED_3[80];\r
+ __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */\r
+ __IO uint32_t DMA0_ITRIG_INMUX[23]; /**< Trigger select register for DMA0 channel, array offset: 0xE0, array step: 0x4 */\r
+ uint8_t RESERVED_4[36];\r
+ __IO uint32_t DMA0_OTRIG_INMUX[4]; /**< DMA0 output trigger selection to become DMA0 trigger, array offset: 0x160, array step: 0x4 */\r
+ uint8_t RESERVED_5[16];\r
+ __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */\r
+ __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */\r
+ uint8_t RESERVED_6[24];\r
+ __IO uint32_t TIMER3CAPTSEL[4]; /**< Capture select registers for TIMER3 inputs, array offset: 0x1A0, array step: 0x4 */\r
+ uint8_t RESERVED_7[16];\r
+ __IO uint32_t TIMER4CAPTSEL[4]; /**< Capture select registers for TIMER4 inputs, array offset: 0x1C0, array step: 0x4 */\r
+ uint8_t RESERVED_8[16];\r
+ __IO uint32_t PINTSECSEL[2]; /**< Pin interrupt secure select register, array offset: 0x1E0, array step: 0x4 */\r
+ uint8_t RESERVED_9[24];\r
+ __IO uint32_t DMA1_ITRIG_INMUX[10]; /**< Trigger select register for DMA1 channel, array offset: 0x200, array step: 0x4 */\r
+ uint8_t RESERVED_10[24];\r
+ __IO uint32_t DMA1_OTRIG_INMUX[4]; /**< DMA1 output trigger selection to become DMA1 trigger, array offset: 0x240, array step: 0x4 */\r
+ uint8_t RESERVED_11[1264];\r
+ __IO uint32_t DMA0_REQ_ENA; /**< Enable DMA0 requests, offset: 0x740 */\r
+ uint8_t RESERVED_12[4];\r
+ __O uint32_t DMA0_REQ_ENA_SET; /**< Set one or several bits in DMA0_REQ_ENA register, offset: 0x748 */\r
+ uint8_t RESERVED_13[4];\r
+ __O uint32_t DMA0_REQ_ENA_CLR; /**< Clear one or several bits in DMA0_REQ_ENA register, offset: 0x750 */\r
+ uint8_t RESERVED_14[12];\r
+ __IO uint32_t DMA1_REQ_ENA; /**< Enable DMA1 requests, offset: 0x760 */\r
+ uint8_t RESERVED_15[4];\r
+ __O uint32_t DMA1_REQ_ENA_SET; /**< Set one or several bits in DMA1_REQ_ENA register, offset: 0x768 */\r
+ uint8_t RESERVED_16[4];\r
+ __O uint32_t DMA1_REQ_ENA_CLR; /**< Clear one or several bits in DMA1_REQ_ENA register, offset: 0x770 */\r
+ uint8_t RESERVED_17[12];\r
+ __IO uint32_t DMA0_ITRIG_ENA; /**< Enable DMA0 triggers, offset: 0x780 */\r
+ uint8_t RESERVED_18[4];\r
+ __O uint32_t DMA0_ITRIG_ENA_SET; /**< Set one or several bits in DMA0_ITRIG_ENA register, offset: 0x788 */\r
+ uint8_t RESERVED_19[4];\r
+ __O uint32_t DMA0_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA0_ITRIG_ENA register, offset: 0x790 */\r
+ uint8_t RESERVED_20[12];\r
+ __IO uint32_t DMA1_ITRIG_ENA; /**< Enable DMA1 triggers, offset: 0x7A0 */\r
+ uint8_t RESERVED_21[4];\r
+ __O uint32_t DMA1_ITRIG_ENA_SET; /**< Set one or several bits in DMA1_ITRIG_ENA register, offset: 0x7A8 */\r
+ uint8_t RESERVED_22[4];\r
+ __O uint32_t DMA1_ITRIG_ENA_CLR; /**< Clear one or several bits in DMA1_ITRIG_ENA register, offset: 0x7B0 */\r
+} INPUTMUX_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- INPUTMUX Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name SCT0_INMUX - Input mux register for SCT0 input */\r
+/*! @{ */\r
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)\r
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)\r
+/*! INP_N - Input number to SCT0 inputs 0 to 6..\r
+ * 0b00000..SCT_GPI0 function selected from IOCON register\r
+ * 0b00001..SCT_GPI1 function selected from IOCON register\r
+ * 0b00010..SCT_GPI2 function selected from IOCON register\r
+ * 0b00011..SCT_GPI3 function selected from IOCON register\r
+ * 0b00100..SCT_GPI4 function selected from IOCON register\r
+ * 0b00101..SCT_GPI5 function selected from IOCON register\r
+ * 0b00110..SCT_GPI6 function selected from IOCON register\r
+ * 0b00111..SCT_GPI7 function selected from IOCON register\r
+ * 0b01000..T0_OUT0 ctimer 0 match[0] output\r
+ * 0b01001..T1_OUT0 ctimer 1 match[0] output\r
+ * 0b01010..T2_OUT0 ctimer 2 match[0] output\r
+ * 0b01011..T3_OUT0 ctimer 3 match[0] output\r
+ * 0b01100..T4_OUT0 ctimer 4 match[0] output\r
+ * 0b01101..ADC_IRQ interrupt request from ADC\r
+ * 0b01110..GPIOINT_BMATCH\r
+ * 0b01111..USB0_FRAME_TOGGLE\r
+ * 0b10000..USB1_FRAME_TOGGLE\r
+ * 0b10001..COMP_OUTPUT output from analog comparator\r
+ * 0b10010..I2S_SHARED_SCK[0] output from I2S pin sharing\r
+ * 0b10011..I2S_SHARED_SCK[1] output from I2S pin sharing\r
+ * 0b10100..I2S_SHARED_WS[0] output from I2S pin sharing\r
+ * 0b10101..I2S_SHARED_WS[1] output from I2S pin sharing\r
+ * 0b10110..ARM_TXEV interrupt event from cpu0 or cpu1\r
+ * 0b10111..DEBUG_HALTED from cpu0 or cpu1\r
+ * 0b11000-0b11111..None\r
+ */\r
+#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_SCT0_INMUX */\r
+#define INPUTMUX_SCT0_INMUX_COUNT (7U)\r
+\r
+/*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */\r
+/*! @{ */\r
+#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU)\r
+#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U)\r
+/*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4\r
+ * 0b00000..CT_INP0 function selected from IOCON register\r
+ * 0b00001..CT_INP1 function selected from IOCON register\r
+ * 0b00010..CT_INP2 function selected from IOCON register\r
+ * 0b00011..CT_INP3 function selected from IOCON register\r
+ * 0b00100..CT_INP4 function selected from IOCON register\r
+ * 0b00101..CT_INP5 function selected from IOCON register\r
+ * 0b00110..CT_INP6 function selected from IOCON register\r
+ * 0b00111..CT_INP7 function selected from IOCON register\r
+ * 0b01000..CT_INP8 function selected from IOCON register\r
+ * 0b01001..CT_INP9 function selected from IOCON register\r
+ * 0b01010..CT_INP10 function selected from IOCON register\r
+ * 0b01011..CT_INP11 function selected from IOCON register\r
+ * 0b01100..CT_INP12 function selected from IOCON register\r
+ * 0b01101..CT_INP13 function selected from IOCON register\r
+ * 0b01110..CT_INP14 function selected from IOCON register\r
+ * 0b01111..CT_INP15 function selected from IOCON register\r
+ * 0b10000..CT_INP16 function selected from IOCON register\r
+ * 0b10001..CT_INP17 function selected from IOCON register\r
+ * 0b10010..CT_INP18 function selected from IOCON register\r
+ * 0b10011..CT_INP19 function selected from IOCON register\r
+ * 0b10100..USB0_FRAME_TOGGLE\r
+ * 0b10101..USB1_FRAME_TOGGLE\r
+ * 0b10110..COMP_OUTPUT output from analog comparator\r
+ * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing\r
+ * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing\r
+ * 0b11001-0b11111..None\r
+ */\r
+#define INPUTMUX_TIMER0CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_TIMER0CAPTSEL */\r
+#define INPUTMUX_TIMER0CAPTSEL_COUNT (4U)\r
+\r
+/*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */\r
+/*! @{ */\r
+#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU)\r
+#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U)\r
+/*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4\r
+ * 0b00000..CT_INP0 function selected from IOCON register\r
+ * 0b00001..CT_INP1 function selected from IOCON register\r
+ * 0b00010..CT_INP2 function selected from IOCON register\r
+ * 0b00011..CT_INP3 function selected from IOCON register\r
+ * 0b00100..CT_INP4 function selected from IOCON register\r
+ * 0b00101..CT_INP5 function selected from IOCON register\r
+ * 0b00110..CT_INP6 function selected from IOCON register\r
+ * 0b00111..CT_INP7 function selected from IOCON register\r
+ * 0b01000..CT_INP8 function selected from IOCON register\r
+ * 0b01001..CT_INP9 function selected from IOCON register\r
+ * 0b01010..CT_INP10 function selected from IOCON register\r
+ * 0b01011..CT_INP11 function selected from IOCON register\r
+ * 0b01100..CT_INP12 function selected from IOCON register\r
+ * 0b01101..CT_INP13 function selected from IOCON register\r
+ * 0b01110..CT_INP14 function selected from IOCON register\r
+ * 0b01111..CT_INP15 function selected from IOCON register\r
+ * 0b10000..CT_INP16 function selected from IOCON register\r
+ * 0b10001..CT_INP17 function selected from IOCON register\r
+ * 0b10010..CT_INP18 function selected from IOCON register\r
+ * 0b10011..CT_INP19 function selected from IOCON register\r
+ * 0b10100..USB0_FRAME_TOGGLE\r
+ * 0b10101..USB1_FRAME_TOGGLE\r
+ * 0b10110..COMP_OUTPUT output from analog comparator\r
+ * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing\r
+ * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing\r
+ * 0b11001-0b11111..None\r
+ */\r
+#define INPUTMUX_TIMER1CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_TIMER1CAPTSEL */\r
+#define INPUTMUX_TIMER1CAPTSEL_COUNT (4U)\r
+\r
+/*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */\r
+/*! @{ */\r
+#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU)\r
+#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U)\r
+/*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4\r
+ * 0b00000..CT_INP0 function selected from IOCON register\r
+ * 0b00001..CT_INP1 function selected from IOCON register\r
+ * 0b00010..CT_INP2 function selected from IOCON register\r
+ * 0b00011..CT_INP3 function selected from IOCON register\r
+ * 0b00100..CT_INP4 function selected from IOCON register\r
+ * 0b00101..CT_INP5 function selected from IOCON register\r
+ * 0b00110..CT_INP6 function selected from IOCON register\r
+ * 0b00111..CT_INP7 function selected from IOCON register\r
+ * 0b01000..CT_INP8 function selected from IOCON register\r
+ * 0b01001..CT_INP9 function selected from IOCON register\r
+ * 0b01010..CT_INP10 function selected from IOCON register\r
+ * 0b01011..CT_INP11 function selected from IOCON register\r
+ * 0b01100..CT_INP12 function selected from IOCON register\r
+ * 0b01101..CT_INP13 function selected from IOCON register\r
+ * 0b01110..CT_INP14 function selected from IOCON register\r
+ * 0b01111..CT_INP15 function selected from IOCON register\r
+ * 0b10000..CT_INP16 function selected from IOCON register\r
+ * 0b10001..CT_INP17 function selected from IOCON register\r
+ * 0b10010..CT_INP18 function selected from IOCON register\r
+ * 0b10011..CT_INP19 function selected from IOCON register\r
+ * 0b10100..USB0_FRAME_TOGGLE\r
+ * 0b10101..USB1_FRAME_TOGGLE\r
+ * 0b10110..COMP_OUTPUT output from analog comparator\r
+ * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing\r
+ * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing\r
+ * 0b11001-0b11111..None\r
+ */\r
+#define INPUTMUX_TIMER2CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_TIMER2CAPTSEL */\r
+#define INPUTMUX_TIMER2CAPTSEL_COUNT (4U)\r
+\r
+/*! @name PINTSEL - Pin interrupt select register */\r
+/*! @{ */\r
+#define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU)\r
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)\r
+#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_PINTSEL */\r
+#define INPUTMUX_PINTSEL_COUNT (8U)\r
+\r
+/*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU)\r
+#define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U)\r
+/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22).\r
+ * 0b00000..Pin interrupt 0\r
+ * 0b00001..Pin interrupt 1\r
+ * 0b00010..Pin interrupt 2\r
+ * 0b00011..Pin interrupt 3\r
+ * 0b00100..Timer CTIMER0 Match 0\r
+ * 0b00101..Timer CTIMER0 Match 1\r
+ * 0b00110..Timer CTIMER1 Match 0\r
+ * 0b00111..Timer CTIMER1 Match 1\r
+ * 0b01000..Timer CTIMER2 Match 0\r
+ * 0b01001..Timer CTIMER2 Match 1\r
+ * 0b01010..Timer CTIMER3 Match 0\r
+ * 0b01011..Timer CTIMER3 Match 1\r
+ * 0b01100..Timer CTIMER4 Match 0\r
+ * 0b01101..Timer CTIMER4 Match 1\r
+ * 0b01110..COMP_OUTPUT\r
+ * 0b01111..DMA0 output trigger mux 0\r
+ * 0b10000..DMA0 output trigger mux 1\r
+ * 0b10001..DMA0 output trigger mux 1\r
+ * 0b10010..DMA0 output trigger mux 3\r
+ * 0b10011..SCT0 DMA request 0\r
+ * 0b10100..SCT0 DMA request 1\r
+ * 0b10101..HASH DMA RX trigger\r
+ * 0b10110-0b11111..None\r
+ */\r
+#define INPUTMUX_DMA0_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_DMA0_ITRIG_INMUX */\r
+#define INPUTMUX_DMA0_ITRIG_INMUX_COUNT (23U)\r
+\r
+/*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU)\r
+#define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U)\r
+#define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_DMA0_OTRIG_INMUX */\r
+#define INPUTMUX_DMA0_OTRIG_INMUX_COUNT (4U)\r
+\r
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */\r
+/*! @{ */\r
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)\r
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)\r
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */\r
+/*! @{ */\r
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)\r
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)\r
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */\r
+/*! @{ */\r
+#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU)\r
+#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U)\r
+/*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4\r
+ * 0b00000..CT_INP0 function selected from IOCON register\r
+ * 0b00001..CT_INP1 function selected from IOCON register\r
+ * 0b00010..CT_INP2 function selected from IOCON register\r
+ * 0b00011..CT_INP3 function selected from IOCON register\r
+ * 0b00100..CT_INP4 function selected from IOCON register\r
+ * 0b00101..CT_INP5 function selected from IOCON register\r
+ * 0b00110..CT_INP6 function selected from IOCON register\r
+ * 0b00111..CT_INP7 function selected from IOCON register\r
+ * 0b01000..CT_INP8 function selected from IOCON register\r
+ * 0b01001..CT_INP9 function selected from IOCON register\r
+ * 0b01010..CT_INP10 function selected from IOCON register\r
+ * 0b01011..CT_INP11 function selected from IOCON register\r
+ * 0b01100..CT_INP12 function selected from IOCON register\r
+ * 0b01101..CT_INP13 function selected from IOCON register\r
+ * 0b01110..CT_INP14 function selected from IOCON register\r
+ * 0b01111..CT_INP15 function selected from IOCON register\r
+ * 0b10000..CT_INP16 function selected from IOCON register\r
+ * 0b10001..CT_INP17 function selected from IOCON register\r
+ * 0b10010..CT_INP18 function selected from IOCON register\r
+ * 0b10011..CT_INP19 function selected from IOCON register\r
+ * 0b10100..USB0_FRAME_TOGGLE\r
+ * 0b10101..USB1_FRAME_TOGGLE\r
+ * 0b10110..COMP_OUTPUT output from analog comparator\r
+ * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing\r
+ * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing\r
+ * 0b11001-0b11111..None\r
+ */\r
+#define INPUTMUX_TIMER3CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_TIMER3CAPTSEL */\r
+#define INPUTMUX_TIMER3CAPTSEL_COUNT (4U)\r
+\r
+/*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */\r
+/*! @{ */\r
+#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU)\r
+#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U)\r
+/*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4\r
+ * 0b00000..CT_INP0 function selected from IOCON register\r
+ * 0b00001..CT_INP1 function selected from IOCON register\r
+ * 0b00010..CT_INP2 function selected from IOCON register\r
+ * 0b00011..CT_INP3 function selected from IOCON register\r
+ * 0b00100..CT_INP4 function selected from IOCON register\r
+ * 0b00101..CT_INP5 function selected from IOCON register\r
+ * 0b00110..CT_INP6 function selected from IOCON register\r
+ * 0b00111..CT_INP7 function selected from IOCON register\r
+ * 0b01000..CT_INP8 function selected from IOCON register\r
+ * 0b01001..CT_INP9 function selected from IOCON register\r
+ * 0b01010..CT_INP10 function selected from IOCON register\r
+ * 0b01011..CT_INP11 function selected from IOCON register\r
+ * 0b01100..CT_INP12 function selected from IOCON register\r
+ * 0b01101..CT_INP13 function selected from IOCON register\r
+ * 0b01110..CT_INP14 function selected from IOCON register\r
+ * 0b01111..CT_INP15 function selected from IOCON register\r
+ * 0b10000..CT_INP16 function selected from IOCON register\r
+ * 0b10001..CT_INP17 function selected from IOCON register\r
+ * 0b10010..CT_INP18 function selected from IOCON register\r
+ * 0b10011..CT_INP19 function selected from IOCON register\r
+ * 0b10100..USB0_FRAME_TOGGLE\r
+ * 0b10101..USB1_FRAME_TOGGLE\r
+ * 0b10110..COMP_OUTPUT output from analog comparator\r
+ * 0b10111..I2S_SHARED_WS[0] output from I2S pin sharing\r
+ * 0b11000..I2S_SHARED_WS[1] output from I2S pin sharing\r
+ * 0b11001-0b11111..None\r
+ */\r
+#define INPUTMUX_TIMER4CAPTSEL_CAPTSEL(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT)) & INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_TIMER4CAPTSEL */\r
+#define INPUTMUX_TIMER4CAPTSEL_COUNT (4U)\r
+\r
+/*! @name PINTSECSEL - Pin interrupt secure select register */\r
+/*! @{ */\r
+#define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU)\r
+#define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U)\r
+#define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_PINTSECSEL */\r
+#define INPUTMUX_PINTSECSEL_COUNT (2U)\r
+\r
+/*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU)\r
+#define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U)\r
+/*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9).\r
+ * 0b0000..Pin interrupt 0\r
+ * 0b0001..Pin interrupt 1\r
+ * 0b0010..Pin interrupt 2\r
+ * 0b0011..Pin interrupt 3\r
+ * 0b0100..Timer CTIMER0 Match 0\r
+ * 0b0101..Timer CTIMER0 Match 1\r
+ * 0b0110..Timer CTIMER2 Match 0\r
+ * 0b0111..Timer CTIMER4 Match 0\r
+ * 0b1000..DMA1 output trigger mux 0\r
+ * 0b1001..DMA1 output trigger mux 1\r
+ * 0b1010..DMA1 output trigger mux 2\r
+ * 0b1011..DMA1 output trigger mux 3\r
+ * 0b1100..SCT0 DMA request 0\r
+ * 0b1101..SCT0 DMA request 1\r
+ * 0b1110..HASH DMA RX trigger\r
+ * 0b1111..None\r
+ */\r
+#define INPUTMUX_DMA1_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_DMA1_ITRIG_INMUX */\r
+#define INPUTMUX_DMA1_ITRIG_INMUX_COUNT (10U)\r
+\r
+/*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU)\r
+#define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U)\r
+#define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of INPUTMUX_DMA1_OTRIG_INMUX */\r
+#define INPUTMUX_DMA1_OTRIG_INMUX_COUNT (4U)\r
+\r
+/*! @name DMA0_REQ_ENA - Enable DMA0 requests */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU)\r
+#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U)\r
+#define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU)\r
+#define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U)\r
+#define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU)\r
+#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U)\r
+#define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1_REQ_ENA - Enable DMA1 requests */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU)\r
+#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U)\r
+#define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU)\r
+#define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U)\r
+#define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU)\r
+#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U)\r
+#define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU)\r
+#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U)\r
+#define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU)\r
+#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U)\r
+#define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU)\r
+#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U)\r
+#define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU)\r
+#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U)\r
+#define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU)\r
+#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U)\r
+#define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */\r
+/*! @{ */\r
+#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU)\r
+#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U)\r
+#define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group INPUTMUX_Register_Masks */\r
+\r
+\r
+/* INPUTMUX - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral INPUTMUX base address */\r
+ #define INPUTMUX_BASE (0x50006000u)\r
+ /** Peripheral INPUTMUX base address */\r
+ #define INPUTMUX_BASE_NS (0x40006000u)\r
+ /** Peripheral INPUTMUX base pointer */\r
+ #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)\r
+ /** Peripheral INPUTMUX base pointer */\r
+ #define INPUTMUX_NS ((INPUTMUX_Type *)INPUTMUX_BASE_NS)\r
+ /** Array initializer of INPUTMUX peripheral base addresses */\r
+ #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }\r
+ /** Array initializer of INPUTMUX peripheral base pointers */\r
+ #define INPUTMUX_BASE_PTRS { INPUTMUX }\r
+ /** Array initializer of INPUTMUX peripheral base addresses */\r
+ #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX_BASE_NS }\r
+ /** Array initializer of INPUTMUX peripheral base pointers */\r
+ #define INPUTMUX_BASE_PTRS_NS { INPUTMUX_NS }\r
+#else\r
+ /** Peripheral INPUTMUX base address */\r
+ #define INPUTMUX_BASE (0x40006000u)\r
+ /** Peripheral INPUTMUX base pointer */\r
+ #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)\r
+ /** Array initializer of INPUTMUX peripheral base addresses */\r
+ #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }\r
+ /** Array initializer of INPUTMUX peripheral base pointers */\r
+ #define INPUTMUX_BASE_PTRS { INPUTMUX }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- IOCON Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** IOCON - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */\r
+} IOCON_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- IOCON Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */\r
+/*! @{ */\r
+#define IOCON_PIO_FUNC_MASK (0xFU)\r
+#define IOCON_PIO_FUNC_SHIFT (0U)\r
+/*! FUNC - Selects pin function.\r
+ * 0b0000..Alternative connection 0.\r
+ * 0b0001..Alternative connection 1.\r
+ * 0b0010..Alternative connection 2.\r
+ * 0b0011..Alternative connection 3.\r
+ * 0b0100..Alternative connection 4.\r
+ * 0b0101..Alternative connection 5.\r
+ * 0b0110..Alternative connection 6.\r
+ * 0b0111..Alternative connection 7.\r
+ */\r
+#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)\r
+#define IOCON_PIO_MODE_MASK (0x30U)\r
+#define IOCON_PIO_MODE_SHIFT (4U)\r
+/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control).\r
+ * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled).\r
+ * 0b01..Pull-down. Pull-down resistor enabled.\r
+ * 0b10..Pull-up. Pull-up resistor enabled.\r
+ * 0b11..Repeater. Repeater mode.\r
+ */\r
+#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)\r
+#define IOCON_PIO_SLEW_MASK (0x40U)\r
+#define IOCON_PIO_SLEW_SHIFT (6U)\r
+/*! SLEW - Driver slew rate.\r
+ * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously.\r
+ * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details.\r
+ */\r
+#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)\r
+#define IOCON_PIO_INVERT_MASK (0x80U)\r
+#define IOCON_PIO_INVERT_SHIFT (7U)\r
+/*! INVERT - Input polarity.\r
+ * 0b0..Disabled. Input function is not inverted.\r
+ * 0b1..Enabled. Input is function inverted.\r
+ */\r
+#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)\r
+#define IOCON_PIO_DIGIMODE_MASK (0x100U)\r
+#define IOCON_PIO_DIGIMODE_SHIFT (8U)\r
+/*! DIGIMODE - Select Digital mode.\r
+ * 0b0..Analog mode, digital input is disabled.\r
+ * 0b1..Digital mode, digital input is enabled.\r
+ */\r
+#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)\r
+#define IOCON_PIO_OD_MASK (0x200U)\r
+#define IOCON_PIO_OD_SHIFT (9U)\r
+/*! OD - Controls open-drain mode.\r
+ * 0b0..Normal. Normal push-pull output\r
+ * 0b1..Open-drain. Simulated open-drain output (high drive disabled).\r
+ */\r
+#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)\r
+#define IOCON_PIO_ASW_MASK (0x400U)\r
+#define IOCON_PIO_ASW_SHIFT (10U)\r
+/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0\r
+ * 0b0..Analog switch is open.\r
+ * 0b1..Analog switch is closed.\r
+ */\r
+#define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK)\r
+#define IOCON_PIO_SSEL_MASK (0x800U)\r
+#define IOCON_PIO_SSEL_SHIFT (11U)\r
+/*! SSEL - Supply Selection bit.\r
+ * 0b0..3V3 Signaling in I2C Mode.\r
+ * 0b1..1V8 Signaling in I2C Mode.\r
+ */\r
+#define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK)\r
+#define IOCON_PIO_FILTEROFF_MASK (0x1000U)\r
+#define IOCON_PIO_FILTEROFF_SHIFT (12U)\r
+/*! FILTEROFF - Controls input glitch filter.\r
+ * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out.\r
+ * 0b1..Filter disabled. No input filtering is done.\r
+ */\r
+#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)\r
+#define IOCON_PIO_ECS_MASK (0x2000U)\r
+#define IOCON_PIO_ECS_SHIFT (13U)\r
+/*! ECS - Pull-up current source enable in IIC mode.\r
+ * 0b1..Enabled. Pull resistor is conencted.\r
+ * 0b0..Disabled. IO is in open drain.\r
+ */\r
+#define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK)\r
+#define IOCON_PIO_EGP_MASK (0x4000U)\r
+#define IOCON_PIO_EGP_SHIFT (14U)\r
+/*! EGP - Controls slew rate of I2C pad.\r
+ * 0b0..I2C mode.\r
+ * 0b1..GPIO mode.\r
+ */\r
+#define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK)\r
+#define IOCON_PIO_I2CFILTER_MASK (0x8000U)\r
+#define IOCON_PIO_I2CFILTER_SHIFT (15U)\r
+/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation.\r
+ * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C.\r
+ * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C.\r
+ */\r
+#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)\r
+/*! @} */\r
+\r
+/* The count of IOCON_PIO */\r
+#define IOCON_PIO_COUNT (2U)\r
+\r
+/* The count of IOCON_PIO */\r
+#define IOCON_PIO_COUNT2 (32U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group IOCON_Register_Masks */\r
+\r
+\r
+/* IOCON - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral IOCON base address */\r
+ #define IOCON_BASE (0x50001000u)\r
+ /** Peripheral IOCON base address */\r
+ #define IOCON_BASE_NS (0x40001000u)\r
+ /** Peripheral IOCON base pointer */\r
+ #define IOCON ((IOCON_Type *)IOCON_BASE)\r
+ /** Peripheral IOCON base pointer */\r
+ #define IOCON_NS ((IOCON_Type *)IOCON_BASE_NS)\r
+ /** Array initializer of IOCON peripheral base addresses */\r
+ #define IOCON_BASE_ADDRS { IOCON_BASE }\r
+ /** Array initializer of IOCON peripheral base pointers */\r
+ #define IOCON_BASE_PTRS { IOCON }\r
+ /** Array initializer of IOCON peripheral base addresses */\r
+ #define IOCON_BASE_ADDRS_NS { IOCON_BASE_NS }\r
+ /** Array initializer of IOCON peripheral base pointers */\r
+ #define IOCON_BASE_PTRS_NS { IOCON_NS }\r
+#else\r
+ /** Peripheral IOCON base address */\r
+ #define IOCON_BASE (0x40001000u)\r
+ /** Peripheral IOCON base pointer */\r
+ #define IOCON ((IOCON_Type *)IOCON_BASE)\r
+ /** Array initializer of IOCON peripheral base addresses */\r
+ #define IOCON_BASE_ADDRS { IOCON_BASE }\r
+ /** Array initializer of IOCON peripheral base pointers */\r
+ #define IOCON_BASE_PTRS { IOCON }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group IOCON_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- MAILBOX Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup MAILBOX_Peripheral_Access_Layer MAILBOX Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** MAILBOX - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0, array step: 0x10 */\r
+ __IO uint32_t IRQ; /**< Interrupt request register for the Cortex-M0+ CPU., array offset: 0x0, array step: 0x10 */\r
+ __O uint32_t IRQSET; /**< Set bits in IRQ0, array offset: 0x4, array step: 0x10 */\r
+ __O uint32_t IRQCLR; /**< Clear bits in IRQ0, array offset: 0x8, array step: 0x10 */\r
+ uint8_t RESERVED_0[4];\r
+ } MBOXIRQ[2];\r
+ uint8_t RESERVED_0[216];\r
+ __IO uint32_t MUTEX; /**< Mutual exclusion register[1], offset: 0xF8 */\r
+} MAILBOX_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- MAILBOX Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup MAILBOX_Register_Masks MAILBOX Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */\r
+/*! @{ */\r
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU)\r
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U)\r
+#define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK)\r
+/*! @} */\r
+\r
+/* The count of MAILBOX_MBOXIRQ_IRQ */\r
+#define MAILBOX_MBOXIRQ_IRQ_COUNT (2U)\r
+\r
+/*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */\r
+/*! @{ */\r
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU)\r
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U)\r
+#define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK)\r
+/*! @} */\r
+\r
+/* The count of MAILBOX_MBOXIRQ_IRQSET */\r
+#define MAILBOX_MBOXIRQ_IRQSET_COUNT (2U)\r
+\r
+/*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */\r
+/*! @{ */\r
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU)\r
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U)\r
+#define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of MAILBOX_MBOXIRQ_IRQCLR */\r
+#define MAILBOX_MBOXIRQ_IRQCLR_COUNT (2U)\r
+\r
+/*! @name MUTEX - Mutual exclusion register[1] */\r
+/*! @{ */\r
+#define MAILBOX_MUTEX_EX_MASK (0x1U)\r
+#define MAILBOX_MUTEX_EX_SHIFT (0U)\r
+#define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group MAILBOX_Register_Masks */\r
+\r
+\r
+/* MAILBOX - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral MAILBOX base address */\r
+ #define MAILBOX_BASE (0x5008B000u)\r
+ /** Peripheral MAILBOX base address */\r
+ #define MAILBOX_BASE_NS (0x4008B000u)\r
+ /** Peripheral MAILBOX base pointer */\r
+ #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)\r
+ /** Peripheral MAILBOX base pointer */\r
+ #define MAILBOX_NS ((MAILBOX_Type *)MAILBOX_BASE_NS)\r
+ /** Array initializer of MAILBOX peripheral base addresses */\r
+ #define MAILBOX_BASE_ADDRS { MAILBOX_BASE }\r
+ /** Array initializer of MAILBOX peripheral base pointers */\r
+ #define MAILBOX_BASE_PTRS { MAILBOX }\r
+ /** Array initializer of MAILBOX peripheral base addresses */\r
+ #define MAILBOX_BASE_ADDRS_NS { MAILBOX_BASE_NS }\r
+ /** Array initializer of MAILBOX peripheral base pointers */\r
+ #define MAILBOX_BASE_PTRS_NS { MAILBOX_NS }\r
+#else\r
+ /** Peripheral MAILBOX base address */\r
+ #define MAILBOX_BASE (0x4008B000u)\r
+ /** Peripheral MAILBOX base pointer */\r
+ #define MAILBOX ((MAILBOX_Type *)MAILBOX_BASE)\r
+ /** Array initializer of MAILBOX peripheral base addresses */\r
+ #define MAILBOX_BASE_ADDRS { MAILBOX_BASE }\r
+ /** Array initializer of MAILBOX peripheral base pointers */\r
+ #define MAILBOX_BASE_PTRS { MAILBOX }\r
+#endif\r
+/** Interrupt vectors for the MAILBOX peripheral type */\r
+#define MAILBOX_IRQS { MAILBOX_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group MAILBOX_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- MRT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** MRT - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0, array step: 0x10 */\r
+ __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */\r
+ __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */\r
+ __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */\r
+ __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */\r
+ } CHANNEL[4];\r
+ uint8_t RESERVED_0[176];\r
+ __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */\r
+ __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */\r
+ __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */\r
+} MRT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- MRT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup MRT_Register_Masks MRT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)\r
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)\r
+#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)\r
+#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)\r
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)\r
+/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0.\r
+ * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected.\r
+ * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running.\r
+ */\r
+#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_INTVAL */\r
+#define MRT_CHANNEL_INTVAL_COUNT (4U)\r
+\r
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)\r
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)\r
+#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_TIMER */\r
+#define MRT_CHANNEL_TIMER_COUNT (4U)\r
+\r
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)\r
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)\r
+/*! INTEN - Enable the TIMERn interrupt.\r
+ * 0b0..Disabled. TIMERn interrupt is disabled.\r
+ * 0b1..Enabled. TIMERn interrupt is enabled.\r
+ */\r
+#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)\r
+#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)\r
+#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)\r
+/*! MODE - Selects timer mode.\r
+ * 0b00..Repeat interrupt mode.\r
+ * 0b01..One-shot interrupt mode.\r
+ * 0b10..One-shot stall mode.\r
+ * 0b11..Reserved.\r
+ */\r
+#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_CTRL */\r
+#define MRT_CHANNEL_CTRL_COUNT (4U)\r
+\r
+/*! @name CHANNEL_STAT - MRT Status register. */\r
+/*! @{ */\r
+#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)\r
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)\r
+/*! INTFLAG - Monitors the interrupt flag.\r
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.\r
+ * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.\r
+ */\r
+#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)\r
+#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)\r
+#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)\r
+/*! RUN - Indicates the state of TIMERn. This bit is read-only.\r
+ * 0b0..Idle state. TIMERn is stopped.\r
+ * 0b1..Running. TIMERn is running.\r
+ */\r
+#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)\r
+#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)\r
+#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)\r
+/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes.\r
+ * 0b0..This channel is not in use.\r
+ * 0b1..This channel is in use.\r
+ */\r
+#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)\r
+/*! @} */\r
+\r
+/* The count of MRT_CHANNEL_STAT */\r
+#define MRT_CHANNEL_STAT_COUNT (4U)\r
+\r
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */\r
+/*! @{ */\r
+#define MRT_MODCFG_NOC_MASK (0xFU)\r
+#define MRT_MODCFG_NOC_SHIFT (0U)\r
+#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)\r
+#define MRT_MODCFG_NOB_MASK (0x1F0U)\r
+#define MRT_MODCFG_NOB_SHIFT (4U)\r
+#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)\r
+#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)\r
+#define MRT_MODCFG_MULTITASK_SHIFT (31U)\r
+/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register.\r
+ * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset.\r
+ * 0b1..Multi-task mode.\r
+ */\r
+#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */\r
+/*! @{ */\r
+#define MRT_IDLE_CH_CHAN_MASK (0xF0U)\r
+#define MRT_IDLE_CH_CHAN_SHIFT (4U)\r
+#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)\r
+/*! @} */\r
+\r
+/*! @name IRQ_FLAG - Global interrupt flag register */\r
+/*! @{ */\r
+#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)\r
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)\r
+/*! GFLAG0 - Monitors the interrupt flag of TIMER0.\r
+ * 0b0..No pending interrupt. Writing a zero is equivalent to no operation.\r
+ * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request.\r
+ */\r
+#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)\r
+#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)\r
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)\r
+#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)\r
+#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)\r
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)\r
+#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)\r
+#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)\r
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)\r
+#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group MRT_Register_Masks */\r
+\r
+\r
+/* MRT - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral MRT0 base address */\r
+ #define MRT0_BASE (0x5000D000u)\r
+ /** Peripheral MRT0 base address */\r
+ #define MRT0_BASE_NS (0x4000D000u)\r
+ /** Peripheral MRT0 base pointer */\r
+ #define MRT0 ((MRT_Type *)MRT0_BASE)\r
+ /** Peripheral MRT0 base pointer */\r
+ #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS)\r
+ /** Array initializer of MRT peripheral base addresses */\r
+ #define MRT_BASE_ADDRS { MRT0_BASE }\r
+ /** Array initializer of MRT peripheral base pointers */\r
+ #define MRT_BASE_PTRS { MRT0 }\r
+ /** Array initializer of MRT peripheral base addresses */\r
+ #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS }\r
+ /** Array initializer of MRT peripheral base pointers */\r
+ #define MRT_BASE_PTRS_NS { MRT0_NS }\r
+#else\r
+ /** Peripheral MRT0 base address */\r
+ #define MRT0_BASE (0x4000D000u)\r
+ /** Peripheral MRT0 base pointer */\r
+ #define MRT0 ((MRT_Type *)MRT0_BASE)\r
+ /** Array initializer of MRT peripheral base addresses */\r
+ #define MRT_BASE_ADDRS { MRT0_BASE }\r
+ /** Array initializer of MRT peripheral base pointers */\r
+ #define MRT_BASE_PTRS { MRT0 }\r
+#endif\r
+/** Interrupt vectors for the MRT peripheral type */\r
+#define MRT_IRQS { MRT0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group MRT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- OSTIMER Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** OSTIMER - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */\r
+ __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */\r
+ __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */\r
+ __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */\r
+ __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */\r
+ __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */\r
+} OSTIMER_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- OSTIMER Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name EVTIMERL - EVTIMER Low Register */\r
+/*! @{ */\r
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)\r
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U)\r
+#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVTIMERH - EVTIMER High Register */\r
+/*! @{ */\r
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU)\r
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U)\r
+#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */\r
+/*! @{ */\r
+#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU)\r
+#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U)\r
+#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAPTUREN_H - Local Capture High Register for CPUn */\r
+/*! @{ */\r
+#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU)\r
+#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U)\r
+#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MATCHN_L - Local Match Low Register for CPUn */\r
+/*! @{ */\r
+#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU)\r
+#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U)\r
+#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name MATCHN_H - Match High Register for CPUn */\r
+/*! @{ */\r
+#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU)\r
+#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U)\r
+#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK)\r
+/*! @} */\r
+\r
+/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */\r
+/*! @{ */\r
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U)\r
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U)\r
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK)\r
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U)\r
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U)\r
+#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group OSTIMER_Register_Masks */\r
+\r
+\r
+/* OSTIMER - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral OSTIMER base address */\r
+ #define OSTIMER_BASE (0x5002D000u)\r
+ /** Peripheral OSTIMER base address */\r
+ #define OSTIMER_BASE_NS (0x4002D000u)\r
+ /** Peripheral OSTIMER base pointer */\r
+ #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE)\r
+ /** Peripheral OSTIMER base pointer */\r
+ #define OSTIMER_NS ((OSTIMER_Type *)OSTIMER_BASE_NS)\r
+ /** Array initializer of OSTIMER peripheral base addresses */\r
+ #define OSTIMER_BASE_ADDRS { OSTIMER_BASE }\r
+ /** Array initializer of OSTIMER peripheral base pointers */\r
+ #define OSTIMER_BASE_PTRS { OSTIMER }\r
+ /** Array initializer of OSTIMER peripheral base addresses */\r
+ #define OSTIMER_BASE_ADDRS_NS { OSTIMER_BASE_NS }\r
+ /** Array initializer of OSTIMER peripheral base pointers */\r
+ #define OSTIMER_BASE_PTRS_NS { OSTIMER_NS }\r
+#else\r
+ /** Peripheral OSTIMER base address */\r
+ #define OSTIMER_BASE (0x4002D000u)\r
+ /** Peripheral OSTIMER base pointer */\r
+ #define OSTIMER ((OSTIMER_Type *)OSTIMER_BASE)\r
+ /** Array initializer of OSTIMER peripheral base addresses */\r
+ #define OSTIMER_BASE_ADDRS { OSTIMER_BASE }\r
+ /** Array initializer of OSTIMER peripheral base pointers */\r
+ #define OSTIMER_BASE_PTRS { OSTIMER }\r
+#endif\r
+/** Interrupt vectors for the OSTIMER peripheral type */\r
+#define OSTIMER_IRQS { OS_EVENT_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group OSTIMER_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PINT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** PINT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */\r
+ __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */\r
+ __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */\r
+ __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */\r
+ __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */\r
+ __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */\r
+ __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */\r
+ __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */\r
+ __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */\r
+ __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */\r
+ __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */\r
+ __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */\r
+ __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */\r
+} PINT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PINT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PINT_Register_Masks PINT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name ISEL - Pin Interrupt Mode register */\r
+/*! @{ */\r
+#define PINT_ISEL_PMODE_MASK (0xFFU)\r
+#define PINT_ISEL_PMODE_SHIFT (0U)\r
+#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */\r
+/*! @{ */\r
+#define PINT_IENR_ENRL_MASK (0xFFU)\r
+#define PINT_IENR_ENRL_SHIFT (0U)\r
+#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */\r
+/*! @{ */\r
+#define PINT_SIENR_SETENRL_MASK (0xFFU)\r
+#define PINT_SIENR_SETENRL_SHIFT (0U)\r
+#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */\r
+/*! @{ */\r
+#define PINT_CIENR_CENRL_MASK (0xFFU)\r
+#define PINT_CIENR_CENRL_SHIFT (0U)\r
+#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */\r
+/*! @{ */\r
+#define PINT_IENF_ENAF_MASK (0xFFU)\r
+#define PINT_IENF_ENAF_SHIFT (0U)\r
+#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)\r
+/*! @} */\r
+\r
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */\r
+/*! @{ */\r
+#define PINT_SIENF_SETENAF_MASK (0xFFU)\r
+#define PINT_SIENF_SETENAF_SHIFT (0U)\r
+#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)\r
+/*! @} */\r
+\r
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */\r
+/*! @{ */\r
+#define PINT_CIENF_CENAF_MASK (0xFFU)\r
+#define PINT_CIENF_CENAF_SHIFT (0U)\r
+#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)\r
+/*! @} */\r
+\r
+/*! @name RISE - Pin interrupt rising edge register */\r
+/*! @{ */\r
+#define PINT_RISE_RDET_MASK (0xFFU)\r
+#define PINT_RISE_RDET_SHIFT (0U)\r
+#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)\r
+/*! @} */\r
+\r
+/*! @name FALL - Pin interrupt falling edge register */\r
+/*! @{ */\r
+#define PINT_FALL_FDET_MASK (0xFFU)\r
+#define PINT_FALL_FDET_SHIFT (0U)\r
+#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)\r
+/*! @} */\r
+\r
+/*! @name IST - Pin interrupt status register */\r
+/*! @{ */\r
+#define PINT_IST_PSTAT_MASK (0xFFU)\r
+#define PINT_IST_PSTAT_SHIFT (0U)\r
+#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name PMCTRL - Pattern match interrupt control register */\r
+/*! @{ */\r
+#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)\r
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)\r
+/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.\r
+ * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function.\r
+ * 0b1..Pattern match. Interrupts are driven in response to pattern matches.\r
+ */\r
+#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)\r
+#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)\r
+#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)\r
+/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true.\r
+ * 0b0..Disabled. RXEV output to the CPU is disabled.\r
+ * 0b1..Enabled. RXEV output to the CPU is enabled.\r
+ */\r
+#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)\r
+#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)\r
+#define PINT_PMCTRL_PMAT_SHIFT (24U)\r
+#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */\r
+/*! @{ */\r
+#define PINT_PMSRC_SRC0_MASK (0x700U)\r
+#define PINT_PMSRC_SRC0_SHIFT (8U)\r
+/*! SRC0 - Selects the input source for bit slice 0\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0.\r
+ */\r
+#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)\r
+#define PINT_PMSRC_SRC1_MASK (0x3800U)\r
+#define PINT_PMSRC_SRC1_SHIFT (11U)\r
+/*! SRC1 - Selects the input source for bit slice 1\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1.\r
+ */\r
+#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)\r
+#define PINT_PMSRC_SRC2_MASK (0x1C000U)\r
+#define PINT_PMSRC_SRC2_SHIFT (14U)\r
+/*! SRC2 - Selects the input source for bit slice 2\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2.\r
+ */\r
+#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)\r
+#define PINT_PMSRC_SRC3_MASK (0xE0000U)\r
+#define PINT_PMSRC_SRC3_SHIFT (17U)\r
+/*! SRC3 - Selects the input source for bit slice 3\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3.\r
+ */\r
+#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)\r
+#define PINT_PMSRC_SRC4_MASK (0x700000U)\r
+#define PINT_PMSRC_SRC4_SHIFT (20U)\r
+/*! SRC4 - Selects the input source for bit slice 4\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4.\r
+ */\r
+#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)\r
+#define PINT_PMSRC_SRC5_MASK (0x3800000U)\r
+#define PINT_PMSRC_SRC5_SHIFT (23U)\r
+/*! SRC5 - Selects the input source for bit slice 5\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5.\r
+ */\r
+#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)\r
+#define PINT_PMSRC_SRC6_MASK (0x1C000000U)\r
+#define PINT_PMSRC_SRC6_SHIFT (26U)\r
+/*! SRC6 - Selects the input source for bit slice 6\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6.\r
+ */\r
+#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)\r
+#define PINT_PMSRC_SRC7_MASK (0xE0000000U)\r
+#define PINT_PMSRC_SRC7_SHIFT (29U)\r
+/*! SRC7 - Selects the input source for bit slice 7\r
+ * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7.\r
+ * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7.\r
+ * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7.\r
+ * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7.\r
+ * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7.\r
+ * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7.\r
+ * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7.\r
+ * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7.\r
+ */\r
+#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)\r
+/*! @} */\r
+\r
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */\r
+/*! @{ */\r
+#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)\r
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)\r
+/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint.\r
+ * 0b0..No effect. Slice 0 is not an endpoint.\r
+ * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)\r
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)\r
+/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint.\r
+ * 0b0..No effect. Slice 1 is not an endpoint.\r
+ * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)\r
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)\r
+/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint.\r
+ * 0b0..No effect. Slice 2 is not an endpoint.\r
+ * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)\r
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)\r
+/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint.\r
+ * 0b0..No effect. Slice 3 is not an endpoint.\r
+ * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)\r
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)\r
+/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint.\r
+ * 0b0..No effect. Slice 4 is not an endpoint.\r
+ * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)\r
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)\r
+/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint.\r
+ * 0b0..No effect. Slice 5 is not an endpoint.\r
+ * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)\r
+#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)\r
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)\r
+/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint.\r
+ * 0b0..No effect. Slice 6 is not an endpoint.\r
+ * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true.\r
+ */\r
+#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)\r
+#define PINT_PMCFG_CFG0_MASK (0x700U)\r
+#define PINT_PMCFG_CFG0_SHIFT (8U)\r
+/*! CFG0 - Specifies the match contribution condition for bit slice 0.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)\r
+#define PINT_PMCFG_CFG1_MASK (0x3800U)\r
+#define PINT_PMCFG_CFG1_SHIFT (11U)\r
+/*! CFG1 - Specifies the match contribution condition for bit slice 1.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)\r
+#define PINT_PMCFG_CFG2_MASK (0x1C000U)\r
+#define PINT_PMCFG_CFG2_SHIFT (14U)\r
+/*! CFG2 - Specifies the match contribution condition for bit slice 2.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)\r
+#define PINT_PMCFG_CFG3_MASK (0xE0000U)\r
+#define PINT_PMCFG_CFG3_SHIFT (17U)\r
+/*! CFG3 - Specifies the match contribution condition for bit slice 3.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)\r
+#define PINT_PMCFG_CFG4_MASK (0x700000U)\r
+#define PINT_PMCFG_CFG4_SHIFT (20U)\r
+/*! CFG4 - Specifies the match contribution condition for bit slice 4.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)\r
+#define PINT_PMCFG_CFG5_MASK (0x3800000U)\r
+#define PINT_PMCFG_CFG5_SHIFT (23U)\r
+/*! CFG5 - Specifies the match contribution condition for bit slice 5.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)\r
+#define PINT_PMCFG_CFG6_MASK (0x1C000000U)\r
+#define PINT_PMCFG_CFG6_SHIFT (26U)\r
+/*! CFG6 - Specifies the match contribution condition for bit slice 6.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)\r
+#define PINT_PMCFG_CFG7_MASK (0xE0000000U)\r
+#define PINT_PMCFG_CFG7_SHIFT (29U)\r
+/*! CFG7 - Specifies the match contribution condition for bit slice 7.\r
+ * 0b000..Constant HIGH. This bit slice always contributes to a product term match.\r
+ * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to.\r
+ * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register.\r
+ * 0b101..Low level. Match occurs when there is a low level on the specified input.\r
+ * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices).\r
+ * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle.\r
+ */\r
+#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PINT_Register_Masks */\r
+\r
+\r
+/* PINT - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral PINT base address */\r
+ #define PINT_BASE (0x50004000u)\r
+ /** Peripheral PINT base address */\r
+ #define PINT_BASE_NS (0x40004000u)\r
+ /** Peripheral PINT base pointer */\r
+ #define PINT ((PINT_Type *)PINT_BASE)\r
+ /** Peripheral PINT base pointer */\r
+ #define PINT_NS ((PINT_Type *)PINT_BASE_NS)\r
+ /** Peripheral SECPINT base address */\r
+ #define SECPINT_BASE (0x50005000u)\r
+ /** Peripheral SECPINT base address */\r
+ #define SECPINT_BASE_NS (0x40005000u)\r
+ /** Peripheral SECPINT base pointer */\r
+ #define SECPINT ((PINT_Type *)SECPINT_BASE)\r
+ /** Peripheral SECPINT base pointer */\r
+ #define SECPINT_NS ((PINT_Type *)SECPINT_BASE_NS)\r
+ /** Array initializer of PINT peripheral base addresses */\r
+ #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE }\r
+ /** Array initializer of PINT peripheral base pointers */\r
+ #define PINT_BASE_PTRS { PINT, SECPINT }\r
+ /** Array initializer of PINT peripheral base addresses */\r
+ #define PINT_BASE_ADDRS_NS { PINT_BASE_NS, SECPINT_BASE_NS }\r
+ /** Array initializer of PINT peripheral base pointers */\r
+ #define PINT_BASE_PTRS_NS { PINT_NS, SECPINT_NS }\r
+#else\r
+ /** Peripheral PINT base address */\r
+ #define PINT_BASE (0x40004000u)\r
+ /** Peripheral PINT base pointer */\r
+ #define PINT ((PINT_Type *)PINT_BASE)\r
+ /** Peripheral SECPINT base address */\r
+ #define SECPINT_BASE (0x40005000u)\r
+ /** Peripheral SECPINT base pointer */\r
+ #define SECPINT ((PINT_Type *)SECPINT_BASE)\r
+ /** Array initializer of PINT peripheral base addresses */\r
+ #define PINT_BASE_ADDRS { PINT_BASE, SECPINT_BASE }\r
+ /** Array initializer of PINT peripheral base pointers */\r
+ #define PINT_BASE_PTRS { PINT, SECPINT }\r
+#endif\r
+/** Interrupt vectors for the PINT peripheral type */\r
+#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn, SEC_GPIO_INT0_IRQ0_IRQn, SEC_GPIO_INT0_IRQ1_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PINT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PLU Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** PLU - Register Layout Typedef */\r
+typedef struct {\r
+ struct { /* offset: 0x0, array step: 0x20 */\r
+ __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */\r
+ uint8_t RESERVED_0[12];\r
+ } LUT[26];\r
+ uint8_t RESERVED_0[1216];\r
+ __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */\r
+ uint8_t RESERVED_1[152];\r
+ __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */\r
+ __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */\r
+ uint8_t RESERVED_2[760];\r
+ __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */\r
+} PLU_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PLU Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PLU_Register_Masks PLU Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */\r
+/*! @{ */\r
+#define PLU_LUT_INP_LUT_INP_MASK (0x3FU)\r
+#define PLU_LUT_INP_LUT_INP_SHIFT (0U)\r
+/*! LUT_INP - Selects the input source to be connected to LUT25 input4.\r
+ * 0b000000..The PLU primary inputs 0.\r
+ * 0b000001..The PLU primary inputs 1.\r
+ * 0b000010..The PLU primary inputs 2.\r
+ * 0b000011..The PLU primary inputs 3.\r
+ * 0b000100..The PLU primary inputs 4.\r
+ * 0b000101..The PLU primary inputs 5.\r
+ * 0b000110..Tie low.\r
+ * 0b000111..The output of LUT1.\r
+ * 0b001000..The output of LUT2.\r
+ * 0b001001..The output of LUT3.\r
+ * 0b001010..The output of LUT4.\r
+ * 0b001011..The output of LUT5.\r
+ * 0b001100..The output of LUT6.\r
+ * 0b001101..The output of LUT7.\r
+ * 0b001110..The output of LUT8.\r
+ * 0b001111..The output of LUT9.\r
+ * 0b010000..The output of LUT10.\r
+ * 0b010001..The output of LUT11.\r
+ * 0b010010..The output of LUT12.\r
+ * 0b010011..The output of LUT13.\r
+ * 0b010100..The output of LUT14.\r
+ * 0b010101..The output of LUT15.\r
+ * 0b010110..The output of LUT16.\r
+ * 0b010111..The output of LUT17.\r
+ * 0b011000..The output of LUT18.\r
+ * 0b011001..The output of LUT19.\r
+ * 0b011010..The output of LUT20.\r
+ * 0b011011..The output of LUT21.\r
+ * 0b011100..The output of LUT22.\r
+ * 0b011101..The output of LUT23.\r
+ * 0b011110..The output of LUT24.\r
+ * 0b011111..The output of LUT25.\r
+ * 0b100000..state(0).\r
+ * 0b100001..state(1).\r
+ * 0b100010..state(2).\r
+ * 0b100011..state(3).\r
+ */\r
+#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK)\r
+/*! @} */\r
+\r
+/* The count of PLU_LUT_INP */\r
+#define PLU_LUT_INP_COUNT (26U)\r
+\r
+/* The count of PLU_LUT_INP */\r
+#define PLU_LUT_INP_COUNT2 (5U)\r
+\r
+/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */\r
+/*! @{ */\r
+#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU)\r
+#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U)\r
+#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK)\r
+/*! @} */\r
+\r
+/* The count of PLU_LUT_T_LUT_TRUTH */\r
+#define PLU_LUT_T_LUT_TRUTH_COUNT (26U)\r
+\r
+/*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */\r
+/*! @{ */\r
+#define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU)\r
+#define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U)\r
+#define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK)\r
+/*! @} */\r
+\r
+/*! @name WAKEINT - Wakeup interrupt control for PLU */\r
+/*! @{ */\r
+#define PLU_WAKEINT_MASK_MASK (0xFFU)\r
+#define PLU_WAKEINT_MASK_SHIFT (0U)\r
+#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK)\r
+#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U)\r
+#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U)\r
+/*! FILTER_MODE - control input of the PLU, add filtering for glitch\r
+ * 0b00..Bypass mode.\r
+ * 0b01..Filter 1 clock period.\r
+ * 0b10..Filter 2 clock period.\r
+ * 0b11..Filter 3 clock period.\r
+ */\r
+#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK)\r
+#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U)\r
+#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U)\r
+#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK)\r
+#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U)\r
+#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U)\r
+#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK)\r
+#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U)\r
+#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U)\r
+#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK)\r
+/*! @} */\r
+\r
+/*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */\r
+/*! @{ */\r
+#define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU)\r
+#define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U)\r
+/*! OUTPUTn - Selects the source to be connected to PLU Output 7.\r
+ * 0b00000..The PLU output 0.\r
+ * 0b00001..The PLU output 1.\r
+ * 0b00010..The PLU output 2.\r
+ * 0b00011..The PLU output 3.\r
+ * 0b00100..The PLU output 4.\r
+ * 0b00101..The PLU output 5.\r
+ * 0b00110..The PLU output 6.\r
+ * 0b00111..The PLU output 7.\r
+ * 0b01000..The PLU output 8.\r
+ * 0b01001..The PLU output 9.\r
+ * 0b01010..The PLU output 10.\r
+ * 0b01011..The PLU output 11.\r
+ * 0b01100..The PLU output 12.\r
+ * 0b01101..The PLU output 13.\r
+ * 0b01110..The PLU output 14.\r
+ * 0b01111..The PLU output 15.\r
+ * 0b10000..The PLU output 16.\r
+ * 0b10001..The PLU output 17.\r
+ * 0b10010..The PLU output 18.\r
+ * 0b10011..The PLU output 19.\r
+ * 0b10100..The PLU output 20.\r
+ * 0b10101..The PLU output 21.\r
+ * 0b10110..The PLU output 22.\r
+ * 0b10111..The PLU output 23.\r
+ * 0b11000..The PLU output 24.\r
+ * 0b11001..The PLU output 25.\r
+ * 0b11010..state(0).\r
+ * 0b11011..state(1).\r
+ * 0b11100..state(2).\r
+ * 0b11101..state(3).\r
+ */\r
+#define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK)\r
+/*! @} */\r
+\r
+/* The count of PLU_OUTPUT_MUX */\r
+#define PLU_OUTPUT_MUX_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PLU_Register_Masks */\r
+\r
+\r
+/* PLU - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral PLU base address */\r
+ #define PLU_BASE (0x5003D000u)\r
+ /** Peripheral PLU base address */\r
+ #define PLU_BASE_NS (0x4003D000u)\r
+ /** Peripheral PLU base pointer */\r
+ #define PLU ((PLU_Type *)PLU_BASE)\r
+ /** Peripheral PLU base pointer */\r
+ #define PLU_NS ((PLU_Type *)PLU_BASE_NS)\r
+ /** Array initializer of PLU peripheral base addresses */\r
+ #define PLU_BASE_ADDRS { PLU_BASE }\r
+ /** Array initializer of PLU peripheral base pointers */\r
+ #define PLU_BASE_PTRS { PLU }\r
+ /** Array initializer of PLU peripheral base addresses */\r
+ #define PLU_BASE_ADDRS_NS { PLU_BASE_NS }\r
+ /** Array initializer of PLU peripheral base pointers */\r
+ #define PLU_BASE_PTRS_NS { PLU_NS }\r
+#else\r
+ /** Peripheral PLU base address */\r
+ #define PLU_BASE (0x4003D000u)\r
+ /** Peripheral PLU base pointer */\r
+ #define PLU ((PLU_Type *)PLU_BASE)\r
+ /** Array initializer of PLU peripheral base addresses */\r
+ #define PLU_BASE_ADDRS { PLU_BASE }\r
+ /** Array initializer of PLU peripheral base pointers */\r
+ #define PLU_BASE_PTRS { PLU }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PLU_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PMC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** PMC - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[8];\r
+ __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */\r
+ __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */\r
+ uint8_t RESERVED_1[32];\r
+ __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */\r
+ uint8_t RESERVED_3[8];\r
+ __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */\r
+ __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */\r
+ __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */\r
+ __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */\r
+ uint8_t RESERVED_4[20];\r
+ __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */\r
+ uint8_t RESERVED_5[8];\r
+ __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */\r
+ uint8_t RESERVED_6[12];\r
+ __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */\r
+ uint8_t RESERVED_7[16];\r
+ __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */\r
+ __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */\r
+ uint8_t RESERVED_8[16];\r
+ __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */\r
+ uint8_t RESERVED_9[4];\r
+ __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */\r
+ uint8_t RESERVED_10[4];\r
+ __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */\r
+ uint8_t RESERVED_11[4];\r
+ __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */\r
+} PMC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PMC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PMC_Register_Masks PMC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U)\r
+#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U)\r
+/*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer).\r
+ * 0b0..Reset event from DEEP POWER DOWN mode is disable.\r
+ * 0b1..Reset event from DEEP POWER DOWN mode is enable.\r
+ */\r
+#define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK)\r
+#define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U)\r
+#define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U)\r
+/*! BODVBATRESETENABLE - BOD VBAT reset enable.\r
+ * 0b0..BOD VBAT reset is disable.\r
+ * 0b1..BOD VBAT reset is enable.\r
+ */\r
+#define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)\r
+#define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U)\r
+#define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U)\r
+/*! BODCORERESETENABLE - BOD CORE reset enable.\r
+ * 0b0..BOD CORE reset is disable.\r
+ * 0b1..BOD CORE reset is enable.\r
+ */\r
+#define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK)\r
+#define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U)\r
+#define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U)\r
+/*! SWRRESETENABLE - Software reset enable.\r
+ * 0b0..Software reset is disable.\r
+ * 0b1..Software reset is enable.\r
+ */\r
+#define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */\r
+/*! @{ */\r
+#define PMC_RESETCAUSE_POR_MASK (0x1U)\r
+#define PMC_RESETCAUSE_POR_SHIFT (0U)\r
+#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK)\r
+#define PMC_RESETCAUSE_PADRESET_MASK (0x2U)\r
+#define PMC_RESETCAUSE_PADRESET_SHIFT (1U)\r
+#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK)\r
+#define PMC_RESETCAUSE_BODRESET_MASK (0x4U)\r
+#define PMC_RESETCAUSE_BODRESET_SHIFT (2U)\r
+#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK)\r
+#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U)\r
+#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U)\r
+#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK)\r
+#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U)\r
+#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U)\r
+#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK)\r
+#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U)\r
+#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U)\r
+#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK)\r
+#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U)\r
+#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U)\r
+#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK)\r
+#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U)\r
+#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U)\r
+#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK)\r
+#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U)\r
+#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U)\r
+#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK)\r
+/*! @} */\r
+\r
+/*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_BODVBAT_TRIGLVL_MASK (0x1FU)\r
+#define PMC_BODVBAT_TRIGLVL_SHIFT (0U)\r
+/*! TRIGLVL - BoD trigger level.\r
+ * 0b00000..1.00 V.\r
+ * 0b00001..1.10 V.\r
+ * 0b00010..1.20 V.\r
+ * 0b00011..1.30 V.\r
+ * 0b00100..1.40 V.\r
+ * 0b00101..1.50 V.\r
+ * 0b00110..1.60 V.\r
+ * 0b00111..1.65 V.\r
+ * 0b01000..1.70 V.\r
+ * 0b01001..1.75 V.\r
+ * 0b01010..1.80 V.\r
+ * 0b01011..1.90 V.\r
+ * 0b01100..2.00 V.\r
+ * 0b01101..2.10 V.\r
+ * 0b01110..2.20 V.\r
+ * 0b01111..2.30 V.\r
+ * 0b10000..2.40 V.\r
+ * 0b10001..2.50 V.\r
+ * 0b10010..2.60 V.\r
+ * 0b10011..2.70 V.\r
+ * 0b10100..2.806 V.\r
+ * 0b10101..2.90 V.\r
+ * 0b10110..3.00 V.\r
+ * 0b10111..3.10 V.\r
+ * 0b11000..3.20 V.\r
+ * 0b11001..3.30 V.\r
+ * 0b11010..3.30 V.\r
+ * 0b11011..3.30 V.\r
+ * 0b11100..3.30 V.\r
+ * 0b11101..3.30 V.\r
+ * 0b11110..3.30 V.\r
+ * 0b11111..3.30 V.\r
+ */\r
+#define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK)\r
+#define PMC_BODVBAT_HYST_MASK (0x60U)\r
+#define PMC_BODVBAT_HYST_SHIFT (5U)\r
+/*! HYST - BoD Hysteresis control.\r
+ * 0b00..25 mV.\r
+ * 0b01..50 mV.\r
+ * 0b10..75 mV.\r
+ * 0b11..100 mV.\r
+ */\r
+#define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK)\r
+/*! @} */\r
+\r
+/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_BODCORE_TRIGLVL_MASK (0x7U)\r
+#define PMC_BODCORE_TRIGLVL_SHIFT (0U)\r
+/*! TRIGLVL - BoD trigger level.\r
+ * 0b000..0.60 V.\r
+ * 0b001..0.65 V.\r
+ * 0b010..0.70 V.\r
+ * 0b011..0.75 V.\r
+ * 0b100..0.80 V.\r
+ * 0b101..0.85 V.\r
+ * 0b110..0.90 V.\r
+ * 0b111..0.95 V.\r
+ */\r
+#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK)\r
+#define PMC_BODCORE_HYST_MASK (0x30U)\r
+#define PMC_BODCORE_HYST_SHIFT (4U)\r
+/*! HYST - BoD Core Hysteresis control.\r
+ * 0b00..25 mV.\r
+ * 0b01..50 mV.\r
+ * 0b10..75 mV.\r
+ * 0b11..100 mV.\r
+ */\r
+#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK)\r
+/*! @} */\r
+\r
+/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_FRO1M_FREQSEL_MASK (0x7FU)\r
+#define PMC_FRO1M_FREQSEL_SHIFT (0U)\r
+#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK)\r
+#define PMC_FRO1M_ATBCTRL_MASK (0x180U)\r
+#define PMC_FRO1M_ATBCTRL_SHIFT (7U)\r
+#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK)\r
+#define PMC_FRO1M_DIVSEL_MASK (0x3E00U)\r
+#define PMC_FRO1M_DIVSEL_SHIFT (9U)\r
+/*! DIVSEL - Divider selection bits.\r
+ * 0b00000..2.0.\r
+ * 0b00001..4.0.\r
+ * 0b00010..6.0.\r
+ * 0b00011..8.0.\r
+ * 0b00100..10.0.\r
+ * 0b00101..12.0.\r
+ * 0b00110..14.0.\r
+ * 0b00111..16.0.\r
+ * 0b01000..18.0.\r
+ * 0b01001..20.0.\r
+ * 0b01010..22.0.\r
+ * 0b01011..24.0.\r
+ * 0b01100..26.0.\r
+ * 0b01101..28.0.\r
+ * 0b01110..30.0.\r
+ * 0b01111..32.0.\r
+ * 0b10000..34.0.\r
+ * 0b10001..36.0.\r
+ * 0b10010..38.0.\r
+ * 0b10011..40.0.\r
+ * 0b10100..42.0.\r
+ * 0b10101..44.0.\r
+ * 0b10110..46.0.\r
+ * 0b10111..48.0.\r
+ * 0b11000..50.0.\r
+ * 0b11001..52.0.\r
+ * 0b11010..54.0.\r
+ * 0b11011..56.0.\r
+ * 0b11100..58.0.\r
+ * 0b11101..60.0.\r
+ * 0b11110..62.0.\r
+ * 0b11111..1.0.\r
+ */\r
+#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */\r
+/*! @{ */\r
+#define PMC_FRO32K_NTAT_MASK (0xEU)\r
+#define PMC_FRO32K_NTAT_SHIFT (1U)\r
+#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK)\r
+#define PMC_FRO32K_PTAT_MASK (0x70U)\r
+#define PMC_FRO32K_PTAT_SHIFT (4U)\r
+#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK)\r
+#define PMC_FRO32K_CAPCAL_MASK (0xFF80U)\r
+#define PMC_FRO32K_CAPCAL_SHIFT (7U)\r
+#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK)\r
+#define PMC_FRO32K_ATBCTRL_MASK (0x30000U)\r
+#define PMC_FRO32K_ATBCTRL_SHIFT (16U)\r
+#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK)\r
+/*! @} */\r
+\r
+/*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */\r
+/*! @{ */\r
+#define PMC_XTAL32K_IREF_MASK (0x6U)\r
+#define PMC_XTAL32K_IREF_SHIFT (1U)\r
+#define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK)\r
+#define PMC_XTAL32K_TEST_MASK (0x8U)\r
+#define PMC_XTAL32K_TEST_SHIFT (3U)\r
+#define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK)\r
+#define PMC_XTAL32K_IBIAS_MASK (0x30U)\r
+#define PMC_XTAL32K_IBIAS_SHIFT (4U)\r
+#define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK)\r
+#define PMC_XTAL32K_AMPL_MASK (0xC0U)\r
+#define PMC_XTAL32K_AMPL_SHIFT (6U)\r
+#define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK)\r
+#define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U)\r
+#define PMC_XTAL32K_CAPBANKIN_SHIFT (8U)\r
+#define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK)\r
+#define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U)\r
+#define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U)\r
+#define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK)\r
+#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U)\r
+#define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U)\r
+/*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set.\r
+ * 0b0..Sourced from CAPTESTSTART.\r
+ * 0b1..Sourced from calibration.\r
+ */\r
+#define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK)\r
+#define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U)\r
+#define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U)\r
+#define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK)\r
+#define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U)\r
+#define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U)\r
+#define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK)\r
+#define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U)\r
+#define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U)\r
+/*! CAPTESTOSCINSEL - Select the input for test.\r
+ * 0b0..Oscillator output pin (osc_out).\r
+ * 0b1..Oscillator input pin (osc_in).\r
+ */\r
+#define PMC_XTAL32K_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT)) & PMC_XTAL32K_CAPTESTOSCINSEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_COMP_HYST_MASK (0x2U)\r
+#define PMC_COMP_HYST_SHIFT (1U)\r
+/*! HYST - Hysteris when hyst = '1'.\r
+ * 0b0..Hysteresis is disable.\r
+ * 0b1..Hysteresis is enable.\r
+ */\r
+#define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK)\r
+#define PMC_COMP_VREFINPUT_MASK (0x4U)\r
+#define PMC_COMP_VREFINPUT_SHIFT (2U)\r
+/*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder).\r
+ * 0b0..Select internal VREF.\r
+ * 0b1..Select VDDA.\r
+ */\r
+#define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK)\r
+#define PMC_COMP_LOWPOWER_MASK (0x8U)\r
+#define PMC_COMP_LOWPOWER_SHIFT (3U)\r
+/*! LOWPOWER - Low power mode.\r
+ * 0b0..High speed mode.\r
+ * 0b1..Low power mode (Low speed).\r
+ */\r
+#define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK)\r
+#define PMC_COMP_PMUX_MASK (0x70U)\r
+#define PMC_COMP_PMUX_SHIFT (4U)\r
+/*! PMUX - Control word for P multiplexer:.\r
+ * 0b000..VREF (See fiedl VREFINPUT).\r
+ * 0b001..Pin P0_0.\r
+ * 0b010..Pin P0_9.\r
+ * 0b011..Pin P0_18.\r
+ * 0b100..Pin P1_14.\r
+ * 0b101..Pin P2_23.\r
+ */\r
+#define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK)\r
+#define PMC_COMP_NMUX_MASK (0x380U)\r
+#define PMC_COMP_NMUX_SHIFT (7U)\r
+/*! NMUX - Control word for N multiplexer:.\r
+ * 0b000..VREF (See field VREFINPUT).\r
+ * 0b001..Pin P0_0.\r
+ * 0b010..Pin P0_9.\r
+ * 0b011..Pin P0_18.\r
+ * 0b100..Pin P1_14.\r
+ * 0b101..Pin P2_23.\r
+ */\r
+#define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK)\r
+#define PMC_COMP_VREF_MASK (0x7C00U)\r
+#define PMC_COMP_VREF_SHIFT (10U)\r
+#define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK)\r
+#define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U)\r
+#define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U)\r
+#define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)\r
+#define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U)\r
+#define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U)\r
+#define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK)\r
+#define PMC_COMP_PMUXCAPT_MASK (0xE00000U)\r
+#define PMC_COMP_PMUXCAPT_SHIFT (21U)\r
+#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */\r
+/*! @{ */\r
+#define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U)\r
+#define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U)\r
+/*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode.\r
+ * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 0.\r
+ * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0.\r
+ */\r
+#define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK)\r
+#define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U)\r
+#define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U)\r
+/*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode.\r
+ * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 1.\r
+ * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1.\r
+ */\r
+#define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK)\r
+#define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U)\r
+#define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U)\r
+/*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode.\r
+ * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 2.\r
+ * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2.\r
+ */\r
+#define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK)\r
+#define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U)\r
+#define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U)\r
+/*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode.\r
+ * 0b0..Last wake up from Deep Power down mode was NOT triggred by wake up I/O 3.\r
+ * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 3.\r
+ */\r
+#define PMC_WAKEIOCAUSE_WAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP3_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP3_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */\r
+/*! @{ */\r
+#define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U)\r
+#define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U)\r
+#define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK)\r
+#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U)\r
+#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U)\r
+#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK)\r
+#define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U)\r
+#define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U)\r
+/*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator.\r
+ * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared..\r
+ * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared..\r
+ */\r
+#define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK)\r
+/*! @} */\r
+\r
+/*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */\r
+/*! @{ */\r
+#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU)\r
+#define PMC_AOREG1_DATA31_0_SHIFT (0U)\r
+#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK)\r
+/*! @} */\r
+\r
+/*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */\r
+/*! @{ */\r
+#define PMC_RTCOSC32K_SEL_MASK (0x1U)\r
+#define PMC_RTCOSC32K_SEL_SHIFT (0U)\r
+/*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) .\r
+ * 0b0..FRO 32 KHz.\r
+ * 0b1..XTAL 32KHz.\r
+ */\r
+#define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK)\r
+#define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU)\r
+#define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U)\r
+#define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK)\r
+#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U)\r
+#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U)\r
+#define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK)\r
+#define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U)\r
+#define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U)\r
+#define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK)\r
+#define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U)\r
+#define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U)\r
+#define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK)\r
+#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U)\r
+#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U)\r
+#define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */\r
+/*! @{ */\r
+#define PMC_OSTIMER_SOFTRESET_MASK (0x1U)\r
+#define PMC_OSTIMER_SOFTRESET_SHIFT (0U)\r
+#define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK)\r
+#define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U)\r
+#define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U)\r
+#define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK)\r
+#define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U)\r
+#define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U)\r
+#define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK)\r
+#define PMC_OSTIMER_OSC32KPD_MASK (0x8U)\r
+#define PMC_OSTIMER_OSC32KPD_SHIFT (3U)\r
+#define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK)\r
+/*! @} */\r
+\r
+/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U)\r
+#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U)\r
+/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..DCDC is powered on during low power mode..\r
+ * 0b1..DCDC is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U)\r
+#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U)\r
+/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN).\r
+ * 0b0..Analog Bias is powered on during low power mode..\r
+ * 0b1..Analog Bias is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U)\r
+#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U)\r
+/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN).\r
+ * 0b0..BOD CORE is powered on during low power mode..\r
+ * 0b1..BOD CORE is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U)\r
+#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U)\r
+/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN).\r
+ * 0b0..BOD VBAT is powered on during low power mode..\r
+ * 0b1..BOD VBAT is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U)\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U)\r
+/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN.\r
+ * 0b0..FRO 1MHz is powered on during low power mode..\r
+ * 0b1..FRO 1MHz is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U)\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U)\r
+/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..FRO 192 MHz is powered on during low power mode..\r
+ * 0b1..FRO 192 MHz is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U)\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U)\r
+/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN.\r
+ * 0b0..FRO 32 KHz is powered on during low power mode..\r
+ * 0b1..FRO 32 KHz is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U)\r
+#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U)\r
+/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN.\r
+ * 0b0..crystal 32 KHz is powered on during low power mode..\r
+ * 0b1..crystal 32 KHz is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U)\r
+#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U)\r
+/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..crystal 32 MHz is powered on during low power mode..\r
+ * 0b1..crystal 32 MHz is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U)\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U)\r
+/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..System PLL (also refered as PLL0) is powered on during low power mode..\r
+ * 0b1..System PLL (also refered as PLL0) is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U)\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U)\r
+/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode..\r
+ * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U)\r
+#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U)\r
+/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..USB Full Speed phy is powered on during low power mode..\r
+ * 0b1..USB Full Speed phy is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U)\r
+/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..USB High Speed Phy is powered on during low power mode..\r
+ * 0b1..USB High Speed Phy is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U)\r
+/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN).\r
+ * 0b0..Analog Comparator is powered on during low power mode..\r
+ * 0b1..Analog Comparator is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U)\r
+/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..Temperature Sensor is powered on during low power mode..\r
+ * 0b1..Temperature Sensor is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U)\r
+/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..General Purpose ADC (GPADC) is powered on during low power mode..\r
+ * 0b1..General Purpose ADC (GPADC) is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U)\r
+/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN.\r
+ * 0b0..Memories LDO is powered on during low power mode..\r
+ * 0b1..Memories LDO is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U)\r
+/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN).\r
+ * 0b0..Deep Sleep LDO is powered on during low power mode..\r
+ * 0b1..Deep Sleep LDO is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U)\r
+/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..USB high speed LDO is powered on during low power mode..\r
+ * 0b1..USB high speed LDO is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U)\r
+/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN).\r
+ * 0b0..is powered on during low power mode..\r
+ * 0b1..is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U)\r
+/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..crystal 32 MHz LDO is powered on during low power mode..\r
+ * 0b1..crystal 32 MHz LDO is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U)\r
+/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..Flash NV (high voltage) is powered on during low power mode..\r
+ * 0b1..Flash NV (high voltage) is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U)\r
+/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode..\r
+ * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U)\r
+/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode..\r
+ * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK)\r
+#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U)\r
+#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U)\r
+/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN).\r
+ * 0b0..ROM is powered on during low power mode..\r
+ * 0b1..ROM is powered off during low power mode..\r
+ */\r
+#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK)\r
+/*! @} */\r
+\r
+/*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U)\r
+#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U)\r
+/*! PDEN_DCDC - Controls power to Bulk DCDC Converter.\r
+ * 0b0..DCDC is powered.\r
+ * 0b1..DCDC is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U)\r
+#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U)\r
+/*! PDEN_BIAS - Controls power to .\r
+ * 0b0..Analog Bias is powered.\r
+ * 0b1..Analog Bias is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U)\r
+#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U)\r
+/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD).\r
+ * 0b0..BOD CORE is powered.\r
+ * 0b1..BOD CORE is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U)\r
+#define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U)\r
+/*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD).\r
+ * 0b0..BOD VBAT is powered.\r
+ * 0b1..BOD VBAT is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U)\r
+#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U)\r
+/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO.\r
+ * 0b0..FRO 192MHz is powered.\r
+ * 0b1..FRO 192MHz is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U)\r
+#define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U)\r
+/*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz.\r
+ * 0b0..FRO32KHz is powered.\r
+ * 0b1..FRO32KHz is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U)\r
+#define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U)\r
+/*! PDEN_XTAL32K - Controls power to crystal 32 KHz.\r
+ * 0b0..Crystal 32KHz is powered.\r
+ * 0b1..Crystal 32KHz is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U)\r
+#define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U)\r
+/*! PDEN_XTAL32M - Controls power to crystal 32 MHz.\r
+ * 0b0..Crystal 32MHz is powered.\r
+ * 0b1..Crystal 32MHz is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U)\r
+#define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U)\r
+/*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0).\r
+ * 0b0..PLL0 is powered.\r
+ * 0b1..PLL0 is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U)\r
+#define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U)\r
+/*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1).\r
+ * 0b0..PLL1 is powered.\r
+ * 0b1..PLL1 is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U)\r
+#define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U)\r
+/*! PDEN_USBFSPHY - Controls power to USB Full Speed phy.\r
+ * 0b0..USB Full Speed phy is powered.\r
+ * 0b1..USB Full Speed phy is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U)\r
+#define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U)\r
+/*! PDEN_USBHSPHY - Controls power to USB High Speed Phy.\r
+ * 0b0..USB HS phy is powered.\r
+ * 0b1..USB HS phy is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U)\r
+#define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U)\r
+/*! PDEN_COMP - Controls power to Analog Comparator.\r
+ * 0b0..Analog Comparator is powered.\r
+ * 0b1..Analog Comparator is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U)\r
+#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U)\r
+/*! PDEN_TEMPSENS - Controls power to Temperature Sensor.\r
+ * 0b0..Temperature Sensor is powered.\r
+ * 0b1..Temperature Sensor is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U)\r
+#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U)\r
+/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC).\r
+ * 0b0..GPADC is powered.\r
+ * 0b1..GPADC is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U)\r
+#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U)\r
+/*! PDEN_LDOMEM - Controls power to Memories LDO.\r
+ * 0b0..Memories LDO is powered.\r
+ * 0b1..Memories LDO is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U)\r
+#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U)\r
+/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO.\r
+ * 0b0..Deep Sleep LDO is powered.\r
+ * 0b1..Deep Sleep LDO is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U)\r
+#define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U)\r
+/*! PDEN_LDOUSBHS - Controls power to USB high speed LDO.\r
+ * 0b0..USB high speed LDO is powered.\r
+ * 0b1..USB high speed LDO is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U)\r
+#define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U)\r
+/*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS)\r
+ * 0b0..auxiliary biasing is powered.\r
+ * 0b1..auxiliary biasing is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U)\r
+#define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U)\r
+/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO.\r
+ * 0b0..crystal 32 MHz LDO is powered.\r
+ * 0b1..crystal 32 MHz LDO is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U)\r
+#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U)\r
+/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO.\r
+ * 0b0..Flash NV LDO is powered.\r
+ * 0b1..Flash NV LDO is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U)\r
+#define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U)\r
+/*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources.\r
+ * 0b0..TRNG clocks are powered.\r
+ * 0b1..TRNG clocks are powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK)\r
+#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U)\r
+#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U)\r
+/*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module.\r
+ * 0b0..PLL0 Sread spectrum module is powered.\r
+ * 0b1..PLL0 Sread spectrum module is powered down.\r
+ */\r
+#define PMC_PDRUNCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK)\r
+/*! @} */\r
+\r
+/*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU)\r
+#define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U)\r
+#define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK)\r
+/*! @} */\r
+\r
+/*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */\r
+/*! @{ */\r
+#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU)\r
+#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U)\r
+#define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PMC_Register_Masks */\r
+\r
+\r
+/* PMC - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral PMC base address */\r
+ #define PMC_BASE (0x50020000u)\r
+ /** Peripheral PMC base address */\r
+ #define PMC_BASE_NS (0x40020000u)\r
+ /** Peripheral PMC base pointer */\r
+ #define PMC ((PMC_Type *)PMC_BASE)\r
+ /** Peripheral PMC base pointer */\r
+ #define PMC_NS ((PMC_Type *)PMC_BASE_NS)\r
+ /** Array initializer of PMC peripheral base addresses */\r
+ #define PMC_BASE_ADDRS { PMC_BASE }\r
+ /** Array initializer of PMC peripheral base pointers */\r
+ #define PMC_BASE_PTRS { PMC }\r
+ /** Array initializer of PMC peripheral base addresses */\r
+ #define PMC_BASE_ADDRS_NS { PMC_BASE_NS }\r
+ /** Array initializer of PMC peripheral base pointers */\r
+ #define PMC_BASE_PTRS_NS { PMC_NS }\r
+#else\r
+ /** Peripheral PMC base address */\r
+ #define PMC_BASE (0x40020000u)\r
+ /** Peripheral PMC base pointer */\r
+ #define PMC ((PMC_Type *)PMC_BASE)\r
+ /** Array initializer of PMC peripheral base addresses */\r
+ #define PMC_BASE_ADDRS { PMC_BASE }\r
+ /** Array initializer of PMC peripheral base pointers */\r
+ #define PMC_BASE_PTRS { PMC }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PMC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- POWERQUAD Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup POWERQUAD_Peripheral_Access_Layer POWERQUAD Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** POWERQUAD - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t OUTBASE; /**< Base address register for output region, offset: 0x0 */\r
+ __IO uint32_t OUTFORMAT; /**< Output format, offset: 0x4 */\r
+ __IO uint32_t TMPBASE; /**< Base address register for temp region, offset: 0x8 */\r
+ __IO uint32_t TMPFORMAT; /**< Temp format, offset: 0xC */\r
+ __IO uint32_t INABASE; /**< Base address register for input A region, offset: 0x10 */\r
+ __IO uint32_t INAFORMAT; /**< Input A format, offset: 0x14 */\r
+ __IO uint32_t INBBASE; /**< Base address register for input B region, offset: 0x18 */\r
+ __IO uint32_t INBFORMAT; /**< Input B format, offset: 0x1C */\r
+ uint8_t RESERVED_0[224];\r
+ __IO uint32_t CONTROL; /**< PowerQuad Control register, offset: 0x100 */\r
+ __IO uint32_t LENGTH; /**< Length register, offset: 0x104 */\r
+ __IO uint32_t CPPRE; /**< Pre-scale register, offset: 0x108 */\r
+ __IO uint32_t MISC; /**< Misc register, offset: 0x10C */\r
+ __IO uint32_t CURSORY; /**< Cursory register, offset: 0x110 */\r
+ uint8_t RESERVED_1[108];\r
+ __IO uint32_t CORDIC_X; /**< Cordic input X register, offset: 0x180 */\r
+ __IO uint32_t CORDIC_Y; /**< Cordic input Y register, offset: 0x184 */\r
+ __IO uint32_t CORDIC_Z; /**< Cordic input Z register, offset: 0x188 */\r
+ __IO uint32_t ERRSTAT; /**< Read/Write register where error statuses are captured (sticky), offset: 0x18C */\r
+ __IO uint32_t INTREN; /**< INTERRUPT enable register, offset: 0x190 */\r
+ __IO uint32_t EVENTEN; /**< Event Enable register, offset: 0x194 */\r
+ __IO uint32_t INTRSTAT; /**< INTERRUPT STATUS register, offset: 0x198 */\r
+ uint8_t RESERVED_2[100];\r
+ __IO uint32_t GPREG[16]; /**< General purpose register bank N., array offset: 0x200, array step: 0x4 */\r
+ __IO uint32_t COMPREG[8]; /**< Compute register bank, array offset: 0x240, array step: 0x4 */\r
+} POWERQUAD_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- POWERQUAD Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup POWERQUAD_Register_Masks POWERQUAD Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name OUTBASE - Base address register for output region */\r
+/*! @{ */\r
+#define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U)\r
+#define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name OUTFORMAT - Output format */\r
+/*! @{ */\r
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U)\r
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U)\r
+#define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK)\r
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U)\r
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U)\r
+#define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK)\r
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U)\r
+#define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U)\r
+#define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK)\r
+/*! @} */\r
+\r
+/*! @name TMPBASE - Base address register for temp region */\r
+/*! @{ */\r
+#define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U)\r
+#define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name TMPFORMAT - Temp format */\r
+/*! @{ */\r
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U)\r
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U)\r
+#define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK)\r
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U)\r
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U)\r
+#define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK)\r
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U)\r
+#define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U)\r
+#define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK)\r
+/*! @} */\r
+\r
+/*! @name INABASE - Base address register for input A region */\r
+/*! @{ */\r
+#define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_INABASE_INABASE_SHIFT (0U)\r
+#define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INAFORMAT - Input A format */\r
+/*! @{ */\r
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U)\r
+#define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U)\r
+#define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK)\r
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U)\r
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U)\r
+#define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK)\r
+#define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U)\r
+#define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U)\r
+#define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK)\r
+/*! @} */\r
+\r
+/*! @name INBBASE - Base address register for input B region */\r
+/*! @{ */\r
+#define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_INBBASE_INBBASE_SHIFT (0U)\r
+#define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INBFORMAT - Input B format */\r
+/*! @{ */\r
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U)\r
+#define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U)\r
+#define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK)\r
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U)\r
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U)\r
+#define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK)\r
+#define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U)\r
+#define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U)\r
+#define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONTROL - PowerQuad Control register */\r
+/*! @{ */\r
+#define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU)\r
+#define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U)\r
+#define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK)\r
+#define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U)\r
+#define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U)\r
+#define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK)\r
+#define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U)\r
+#define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U)\r
+#define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK)\r
+/*! @} */\r
+\r
+/*! @name LENGTH - Length register */\r
+/*! @{ */\r
+#define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U)\r
+#define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPPRE - Pre-scale register */\r
+/*! @{ */\r
+#define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU)\r
+#define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U)\r
+#define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK)\r
+#define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U)\r
+#define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U)\r
+#define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK)\r
+#define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U)\r
+#define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U)\r
+#define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK)\r
+#define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U)\r
+#define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U)\r
+#define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK)\r
+/*! @} */\r
+\r
+/*! @name MISC - Misc register */\r
+/*! @{ */\r
+#define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_MISC_INST_MISC_SHIFT (0U)\r
+#define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK)\r
+/*! @} */\r
+\r
+/*! @name CURSORY - Cursory register */\r
+/*! @{ */\r
+#define POWERQUAD_CURSORY_CURSORY_MASK (0x1U)\r
+#define POWERQUAD_CURSORY_CURSORY_SHIFT (0U)\r
+#define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK)\r
+/*! @} */\r
+\r
+/*! @name CORDIC_X - Cordic input X register */\r
+/*! @{ */\r
+#define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U)\r
+#define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK)\r
+/*! @} */\r
+\r
+/*! @name CORDIC_Y - Cordic input Y register */\r
+/*! @{ */\r
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U)\r
+#define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK)\r
+/*! @} */\r
+\r
+/*! @name CORDIC_Z - Cordic input Z register */\r
+/*! @{ */\r
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U)\r
+#define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK)\r
+/*! @} */\r
+\r
+/*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */\r
+/*! @{ */\r
+#define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U)\r
+#define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U)\r
+#define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK)\r
+#define POWERQUAD_ERRSTAT_NAN_MASK (0x2U)\r
+#define POWERQUAD_ERRSTAT_NAN_SHIFT (1U)\r
+#define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK)\r
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U)\r
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U)\r
+#define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK)\r
+#define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U)\r
+#define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U)\r
+#define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK)\r
+#define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U)\r
+#define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U)\r
+#define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTREN - INTERRUPT enable register */\r
+/*! @{ */\r
+#define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U)\r
+#define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U)\r
+#define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK)\r
+#define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U)\r
+#define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U)\r
+#define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK)\r
+#define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U)\r
+#define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U)\r
+#define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK)\r
+#define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U)\r
+#define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U)\r
+#define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK)\r
+#define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U)\r
+#define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U)\r
+#define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK)\r
+#define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U)\r
+#define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U)\r
+#define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVENTEN - Event Enable register */\r
+/*! @{ */\r
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U)\r
+#define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U)\r
+#define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK)\r
+#define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U)\r
+#define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U)\r
+#define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK)\r
+#define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U)\r
+#define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U)\r
+#define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK)\r
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U)\r
+#define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U)\r
+#define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK)\r
+#define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U)\r
+#define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U)\r
+#define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK)\r
+#define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U)\r
+#define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U)\r
+#define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTRSTAT - INTERRUPT STATUS register */\r
+/*! @{ */\r
+#define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U)\r
+#define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U)\r
+#define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name GPREG - General purpose register bank N. */\r
+/*! @{ */\r
+#define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_GPREG_GPREG_SHIFT (0U)\r
+#define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK)\r
+/*! @} */\r
+\r
+/* The count of POWERQUAD_GPREG */\r
+#define POWERQUAD_GPREG_COUNT (16U)\r
+\r
+/*! @name COMPREGS_COMPREG - Compute register bank */\r
+/*! @{ */\r
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU)\r
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U)\r
+#define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK)\r
+/*! @} */\r
+\r
+/* The count of POWERQUAD_COMPREGS_COMPREG */\r
+#define POWERQUAD_COMPREGS_COMPREG_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group POWERQUAD_Register_Masks */\r
+\r
+\r
+/* POWERQUAD - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral POWERQUAD base address */\r
+ #define POWERQUAD_BASE (0x500A6000u)\r
+ /** Peripheral POWERQUAD base address */\r
+ #define POWERQUAD_BASE_NS (0x400A6000u)\r
+ /** Peripheral POWERQUAD base pointer */\r
+ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)\r
+ /** Peripheral POWERQUAD base pointer */\r
+ #define POWERQUAD_NS ((POWERQUAD_Type *)POWERQUAD_BASE_NS)\r
+ /** Array initializer of POWERQUAD peripheral base addresses */\r
+ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE }\r
+ /** Array initializer of POWERQUAD peripheral base pointers */\r
+ #define POWERQUAD_BASE_PTRS { POWERQUAD }\r
+ /** Array initializer of POWERQUAD peripheral base addresses */\r
+ #define POWERQUAD_BASE_ADDRS_NS { POWERQUAD_BASE_NS }\r
+ /** Array initializer of POWERQUAD peripheral base pointers */\r
+ #define POWERQUAD_BASE_PTRS_NS { POWERQUAD_NS }\r
+#else\r
+ /** Peripheral POWERQUAD base address */\r
+ #define POWERQUAD_BASE (0x400A6000u)\r
+ /** Peripheral POWERQUAD base pointer */\r
+ #define POWERQUAD ((POWERQUAD_Type *)POWERQUAD_BASE)\r
+ /** Array initializer of POWERQUAD peripheral base addresses */\r
+ #define POWERQUAD_BASE_ADDRS { POWERQUAD_BASE }\r
+ /** Array initializer of POWERQUAD peripheral base pointers */\r
+ #define POWERQUAD_BASE_PTRS { POWERQUAD }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group POWERQUAD_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PRINCE Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PRINCE_Peripheral_Access_Layer PRINCE Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** PRINCE - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t ENC_ENABLE; /**< Encryption Enable register, offset: 0x0 */\r
+ __O uint32_t MASK_LSB; /**< Data Mask register, 32 Least Significant Bits, offset: 0x4 */\r
+ __O uint32_t MASK_MSB; /**< Data Mask register, 32 Most Significant Bits, offset: 0x8 */\r
+ __IO uint32_t LOCK; /**< Lock register, offset: 0xC */\r
+ __O uint32_t IV_LSB0; /**< Initial Vector register for region 0, Least Significant Bits, offset: 0x10 */\r
+ __O uint32_t IV_MSB0; /**< Initial Vector register for region 0, Most Significant Bits, offset: 0x14 */\r
+ __IO uint32_t BASE_ADDR0; /**< Base Address for region 0 register, offset: 0x18 */\r
+ __IO uint32_t SR_ENABLE0; /**< Sub-Region Enable register for region 0, offset: 0x1C */\r
+ __O uint32_t IV_LSB1; /**< Initial Vector register for region 1, Least Significant Bits, offset: 0x20 */\r
+ __O uint32_t IV_MSB1; /**< Initial Vector register for region 1, Most Significant Bits, offset: 0x24 */\r
+ __IO uint32_t BASE_ADDR1; /**< Base Address for region 1 register, offset: 0x28 */\r
+ __IO uint32_t SR_ENABLE1; /**< Sub-Region Enable register for region 1, offset: 0x2C */\r
+ __O uint32_t IV_LSB2; /**< Initial Vector register for region 2, Least Significant Bits, offset: 0x30 */\r
+ __O uint32_t IV_MSB2; /**< Initial Vector register for region 2, Most Significant Bits, offset: 0x34 */\r
+ __IO uint32_t BASE_ADDR2; /**< Base Address for region 2 register, offset: 0x38 */\r
+ __IO uint32_t SR_ENABLE2; /**< Sub-Region Enable register for region 2, offset: 0x3C */\r
+} PRINCE_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PRINCE Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PRINCE_Register_Masks PRINCE Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name ENC_ENABLE - Encryption Enable register */\r
+/*! @{ */\r
+#define PRINCE_ENC_ENABLE_EN_MASK (0x1U)\r
+#define PRINCE_ENC_ENABLE_EN_SHIFT (0U)\r
+/*! EN - Encryption Enable.\r
+ * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled..\r
+ * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled..\r
+ */\r
+#define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U)\r
+#define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U)\r
+#define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name LOCK - Lock register */\r
+/*! @{ */\r
+#define PRINCE_LOCK_LOCKREG0_MASK (0x1U)\r
+#define PRINCE_LOCK_LOCKREG0_SHIFT (0U)\r
+/*! LOCKREG0 - Lock Region 0 registers.\r
+ * 0b0..Disabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are writable..\r
+ * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable..\r
+ */\r
+#define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK)\r
+#define PRINCE_LOCK_LOCKREG1_MASK (0x2U)\r
+#define PRINCE_LOCK_LOCKREG1_SHIFT (1U)\r
+/*! LOCKREG1 - Lock Region 1 registers.\r
+ * 0b0..Disabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are writable..\r
+ * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable..\r
+ */\r
+#define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK)\r
+#define PRINCE_LOCK_LOCKREG2_MASK (0x4U)\r
+#define PRINCE_LOCK_LOCKREG2_SHIFT (2U)\r
+/*! LOCKREG2 - Lock Region 2 registers.\r
+ * 0b0..Disabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are writable..\r
+ * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable..\r
+ */\r
+#define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK)\r
+#define PRINCE_LOCK_LOCKMASK_MASK (0x100U)\r
+#define PRINCE_LOCK_LOCKMASK_SHIFT (8U)\r
+/*! LOCKMASK - Lock the Mask registers.\r
+ * 0b0..Disabled. MASK_LSB, and MASK_MSB are writable..\r
+ * 0b1..Enabled. MASK_LSB, and MASK_MSB are not writable..\r
+ */\r
+#define PRINCE_LOCK_LOCKMASK(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKMASK_SHIFT)) & PRINCE_LOCK_LOCKMASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_IV_LSB0_IVVAL_SHIFT (0U)\r
+#define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_IV_MSB0_IVVAL_SHIFT (0U)\r
+#define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name BASE_ADDR0 - Base Address for region 0 register */\r
+/*! @{ */\r
+#define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU)\r
+#define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U)\r
+#define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK)\r
+#define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U)\r
+#define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U)\r
+#define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */\r
+/*! @{ */\r
+#define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU)\r
+#define PRINCE_SR_ENABLE0_EN_SHIFT (0U)\r
+#define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_IV_LSB1_IVVAL_SHIFT (0U)\r
+#define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_IV_MSB1_IVVAL_SHIFT (0U)\r
+#define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name BASE_ADDR1 - Base Address for region 1 register */\r
+/*! @{ */\r
+#define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU)\r
+#define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U)\r
+#define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK)\r
+#define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U)\r
+#define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U)\r
+#define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */\r
+/*! @{ */\r
+#define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU)\r
+#define PRINCE_SR_ENABLE1_EN_SHIFT (0U)\r
+#define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_IV_LSB2_IVVAL_SHIFT (0U)\r
+#define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */\r
+/*! @{ */\r
+#define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU)\r
+#define PRINCE_IV_MSB2_IVVAL_SHIFT (0U)\r
+#define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name BASE_ADDR2 - Base Address for region 2 register */\r
+/*! @{ */\r
+#define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU)\r
+#define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U)\r
+#define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK)\r
+#define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U)\r
+#define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U)\r
+#define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */\r
+/*! @{ */\r
+#define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU)\r
+#define PRINCE_SR_ENABLE2_EN_SHIFT (0U)\r
+#define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PRINCE_Register_Masks */\r
+\r
+\r
+/* PRINCE - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral PRINCE base address */\r
+ #define PRINCE_BASE (0x50035000u)\r
+ /** Peripheral PRINCE base address */\r
+ #define PRINCE_BASE_NS (0x40035000u)\r
+ /** Peripheral PRINCE base pointer */\r
+ #define PRINCE ((PRINCE_Type *)PRINCE_BASE)\r
+ /** Peripheral PRINCE base pointer */\r
+ #define PRINCE_NS ((PRINCE_Type *)PRINCE_BASE_NS)\r
+ /** Array initializer of PRINCE peripheral base addresses */\r
+ #define PRINCE_BASE_ADDRS { PRINCE_BASE }\r
+ /** Array initializer of PRINCE peripheral base pointers */\r
+ #define PRINCE_BASE_PTRS { PRINCE }\r
+ /** Array initializer of PRINCE peripheral base addresses */\r
+ #define PRINCE_BASE_ADDRS_NS { PRINCE_BASE_NS }\r
+ /** Array initializer of PRINCE peripheral base pointers */\r
+ #define PRINCE_BASE_PTRS_NS { PRINCE_NS }\r
+#else\r
+ /** Peripheral PRINCE base address */\r
+ #define PRINCE_BASE (0x40035000u)\r
+ /** Peripheral PRINCE base pointer */\r
+ #define PRINCE ((PRINCE_Type *)PRINCE_BASE)\r
+ /** Array initializer of PRINCE peripheral base addresses */\r
+ #define PRINCE_BASE_ADDRS { PRINCE_BASE }\r
+ /** Array initializer of PRINCE peripheral base pointers */\r
+ #define PRINCE_BASE_PTRS { PRINCE }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PRINCE_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PUF Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** PUF - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< PUF Control register, offset: 0x0 */\r
+ __IO uint32_t KEYINDEX; /**< PUF Key Index register, offset: 0x4 */\r
+ __IO uint32_t KEYSIZE; /**< PUF Key Size register, offset: 0x8 */\r
+ uint8_t RESERVED_0[20];\r
+ __I uint32_t STAT; /**< PUF Status register, offset: 0x20 */\r
+ uint8_t RESERVED_1[4];\r
+ __I uint32_t ALLOW; /**< PUF Allow register, offset: 0x28 */\r
+ uint8_t RESERVED_2[20];\r
+ __O uint32_t KEYINPUT; /**< PUF Key Input register, offset: 0x40 */\r
+ __O uint32_t CODEINPUT; /**< PUF Code Input register, offset: 0x44 */\r
+ __I uint32_t CODEOUTPUT; /**< PUF Code Output register, offset: 0x48 */\r
+ uint8_t RESERVED_3[20];\r
+ __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index register, offset: 0x60 */\r
+ __I uint32_t KEYOUTPUT; /**< PUF Key Output register, offset: 0x64 */\r
+ uint8_t RESERVED_4[116];\r
+ __IO uint32_t IFSTAT; /**< PUF Interface Status and clear register, offset: 0xDC */\r
+ uint8_t RESERVED_5[28];\r
+ __I uint32_t VERSION; /**< PUF version register., offset: 0xFC */\r
+ __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */\r
+ __IO uint32_t INTSTAT; /**< PUF interrupt status, offset: 0x104 */\r
+ __IO uint32_t PWRCTRL; /**< PUF RAM Power Control, offset: 0x108 */\r
+ __IO uint32_t CFG; /**< PUF config register for block bits, offset: 0x10C */\r
+ uint8_t RESERVED_6[240];\r
+ __IO uint32_t KEYLOCK; /**< Only reset in case of full IC reset, offset: 0x200 */\r
+ __IO uint32_t KEYENABLE; /**< , offset: 0x204 */\r
+ __O uint32_t KEYRESET; /**< Reinitialize Keys shift registers counters, offset: 0x208 */\r
+ __IO uint32_t IDXBLK_L; /**< , offset: 0x20C */\r
+ __IO uint32_t IDXBLK_H_DP; /**< , offset: 0x210 */\r
+ __O uint32_t KEYMASK[4]; /**< Only reset in case of full IC reset, array offset: 0x214, array step: 0x4 */\r
+ uint8_t RESERVED_7[48];\r
+ __IO uint32_t IDXBLK_H; /**< , offset: 0x254 */\r
+ __IO uint32_t IDXBLK_L_DP; /**< , offset: 0x258 */\r
+ __I uint32_t SHIFT_STATUS; /**< , offset: 0x25C */\r
+} PUF_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- PUF Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup PUF_Register_Masks PUF Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - PUF Control register */\r
+/*! @{ */\r
+#define PUF_CTRL_ZEROIZE_MASK (0x1U)\r
+#define PUF_CTRL_ZEROIZE_SHIFT (0U)\r
+#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)\r
+#define PUF_CTRL_ENROLL_MASK (0x2U)\r
+#define PUF_CTRL_ENROLL_SHIFT (1U)\r
+#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)\r
+#define PUF_CTRL_START_MASK (0x4U)\r
+#define PUF_CTRL_START_SHIFT (2U)\r
+#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)\r
+#define PUF_CTRL_GENERATEKEY_MASK (0x8U)\r
+#define PUF_CTRL_GENERATEKEY_SHIFT (3U)\r
+#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)\r
+#define PUF_CTRL_SETKEY_MASK (0x10U)\r
+#define PUF_CTRL_SETKEY_SHIFT (4U)\r
+#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)\r
+#define PUF_CTRL_GETKEY_MASK (0x40U)\r
+#define PUF_CTRL_GETKEY_SHIFT (6U)\r
+#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYINDEX - PUF Key Index register */\r
+/*! @{ */\r
+#define PUF_KEYINDEX_KEYIDX_MASK (0xFU)\r
+#define PUF_KEYINDEX_KEYIDX_SHIFT (0U)\r
+#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYSIZE - PUF Key Size register */\r
+/*! @{ */\r
+#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU)\r
+#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U)\r
+#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - PUF Status register */\r
+/*! @{ */\r
+#define PUF_STAT_BUSY_MASK (0x1U)\r
+#define PUF_STAT_BUSY_SHIFT (0U)\r
+#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)\r
+#define PUF_STAT_SUCCESS_MASK (0x2U)\r
+#define PUF_STAT_SUCCESS_SHIFT (1U)\r
+#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)\r
+#define PUF_STAT_ERROR_MASK (0x4U)\r
+#define PUF_STAT_ERROR_SHIFT (2U)\r
+#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)\r
+#define PUF_STAT_KEYINREQ_MASK (0x10U)\r
+#define PUF_STAT_KEYINREQ_SHIFT (4U)\r
+#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)\r
+#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U)\r
+#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U)\r
+#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)\r
+#define PUF_STAT_CODEINREQ_MASK (0x40U)\r
+#define PUF_STAT_CODEINREQ_SHIFT (6U)\r
+#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)\r
+#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U)\r
+#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U)\r
+#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ALLOW - PUF Allow register */\r
+/*! @{ */\r
+#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U)\r
+#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U)\r
+#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)\r
+#define PUF_ALLOW_ALLOWSTART_MASK (0x2U)\r
+#define PUF_ALLOW_ALLOWSTART_SHIFT (1U)\r
+#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)\r
+#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U)\r
+#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U)\r
+#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)\r
+#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U)\r
+#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U)\r
+#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYINPUT - PUF Key Input register */\r
+/*! @{ */\r
+#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU)\r
+#define PUF_KEYINPUT_KEYIN_SHIFT (0U)\r
+#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CODEINPUT - PUF Code Input register */\r
+/*! @{ */\r
+#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU)\r
+#define PUF_CODEINPUT_CODEIN_SHIFT (0U)\r
+#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CODEOUTPUT - PUF Code Output register */\r
+/*! @{ */\r
+#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU)\r
+#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U)\r
+#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYOUTINDEX - PUF Key Output Index register */\r
+/*! @{ */\r
+#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU)\r
+#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U)\r
+#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYOUTPUT - PUF Key Output register */\r
+/*! @{ */\r
+#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU)\r
+#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U)\r
+#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name IFSTAT - PUF Interface Status and clear register */\r
+/*! @{ */\r
+#define PUF_IFSTAT_ERROR_MASK (0x1U)\r
+#define PUF_IFSTAT_ERROR_SHIFT (0U)\r
+#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)\r
+/*! @} */\r
+\r
+/*! @name VERSION - PUF version register. */\r
+/*! @{ */\r
+#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU)\r
+#define PUF_VERSION_KEYOUT_SHIFT (0U)\r
+#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTEN - PUF Interrupt Enable */\r
+/*! @{ */\r
+#define PUF_INTEN_READYEN_MASK (0x1U)\r
+#define PUF_INTEN_READYEN_SHIFT (0U)\r
+#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)\r
+#define PUF_INTEN_SUCCESEN_MASK (0x2U)\r
+#define PUF_INTEN_SUCCESEN_SHIFT (1U)\r
+#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK)\r
+#define PUF_INTEN_ERROREN_MASK (0x4U)\r
+#define PUF_INTEN_ERROREN_SHIFT (2U)\r
+#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)\r
+#define PUF_INTEN_KEYINREQEN_MASK (0x10U)\r
+#define PUF_INTEN_KEYINREQEN_SHIFT (4U)\r
+#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)\r
+#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U)\r
+#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U)\r
+#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)\r
+#define PUF_INTEN_CODEINREQEN_MASK (0x40U)\r
+#define PUF_INTEN_CODEINREQEN_SHIFT (6U)\r
+#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)\r
+#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U)\r
+#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U)\r
+#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - PUF interrupt status */\r
+/*! @{ */\r
+#define PUF_INTSTAT_READY_MASK (0x1U)\r
+#define PUF_INTSTAT_READY_SHIFT (0U)\r
+#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)\r
+#define PUF_INTSTAT_SUCCESS_MASK (0x2U)\r
+#define PUF_INTSTAT_SUCCESS_SHIFT (1U)\r
+#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)\r
+#define PUF_INTSTAT_ERROR_MASK (0x4U)\r
+#define PUF_INTSTAT_ERROR_SHIFT (2U)\r
+#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)\r
+#define PUF_INTSTAT_KEYINREQ_MASK (0x10U)\r
+#define PUF_INTSTAT_KEYINREQ_SHIFT (4U)\r
+#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)\r
+#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U)\r
+#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U)\r
+#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)\r
+#define PUF_INTSTAT_CODEINREQ_MASK (0x40U)\r
+#define PUF_INTSTAT_CODEINREQ_SHIFT (6U)\r
+#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)\r
+#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U)\r
+#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U)\r
+#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWRCTRL - PUF RAM Power Control */\r
+/*! @{ */\r
+#define PUF_PWRCTRL_RAMON_MASK (0x1U)\r
+#define PUF_PWRCTRL_RAMON_SHIFT (0U)\r
+#define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK)\r
+#define PUF_PWRCTRL_RAMSTAT_MASK (0x2U)\r
+#define PUF_PWRCTRL_RAMSTAT_SHIFT (1U)\r
+#define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name CFG - PUF config register for block bits */\r
+/*! @{ */\r
+#define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U)\r
+#define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U)\r
+#define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK)\r
+#define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U)\r
+#define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U)\r
+#define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYLOCK - Only reset in case of full IC reset */\r
+/*! @{ */\r
+#define PUF_KEYLOCK_KEY0_MASK (0x3U)\r
+#define PUF_KEYLOCK_KEY0_SHIFT (0U)\r
+#define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK)\r
+#define PUF_KEYLOCK_KEY1_MASK (0xCU)\r
+#define PUF_KEYLOCK_KEY1_SHIFT (2U)\r
+#define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK)\r
+#define PUF_KEYLOCK_KEY2_MASK (0x30U)\r
+#define PUF_KEYLOCK_KEY2_SHIFT (4U)\r
+#define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK)\r
+#define PUF_KEYLOCK_KEY3_MASK (0xC0U)\r
+#define PUF_KEYLOCK_KEY3_SHIFT (6U)\r
+#define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYENABLE - */\r
+/*! @{ */\r
+#define PUF_KEYENABLE_KEY0_MASK (0x3U)\r
+#define PUF_KEYENABLE_KEY0_SHIFT (0U)\r
+#define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK)\r
+#define PUF_KEYENABLE_KEY1_MASK (0xCU)\r
+#define PUF_KEYENABLE_KEY1_SHIFT (2U)\r
+#define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK)\r
+#define PUF_KEYENABLE_KEY2_MASK (0x30U)\r
+#define PUF_KEYENABLE_KEY2_SHIFT (4U)\r
+#define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK)\r
+#define PUF_KEYENABLE_KEY3_MASK (0xC0U)\r
+#define PUF_KEYENABLE_KEY3_SHIFT (6U)\r
+#define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYRESET - Reinitialize Keys shift registers counters */\r
+/*! @{ */\r
+#define PUF_KEYRESET_KEY0_MASK (0x3U)\r
+#define PUF_KEYRESET_KEY0_SHIFT (0U)\r
+#define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK)\r
+#define PUF_KEYRESET_KEY1_MASK (0xCU)\r
+#define PUF_KEYRESET_KEY1_SHIFT (2U)\r
+#define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK)\r
+#define PUF_KEYRESET_KEY2_MASK (0x30U)\r
+#define PUF_KEYRESET_KEY2_SHIFT (4U)\r
+#define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK)\r
+#define PUF_KEYRESET_KEY3_MASK (0xC0U)\r
+#define PUF_KEYRESET_KEY3_SHIFT (6U)\r
+#define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDXBLK_L - */\r
+/*! @{ */\r
+#define PUF_IDXBLK_L_IDX0_MASK (0x3U)\r
+#define PUF_IDXBLK_L_IDX0_SHIFT (0U)\r
+#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK)\r
+#define PUF_IDXBLK_L_IDX1_MASK (0xCU)\r
+#define PUF_IDXBLK_L_IDX1_SHIFT (2U)\r
+#define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK)\r
+#define PUF_IDXBLK_L_IDX2_MASK (0x30U)\r
+#define PUF_IDXBLK_L_IDX2_SHIFT (4U)\r
+#define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK)\r
+#define PUF_IDXBLK_L_IDX3_MASK (0xC0U)\r
+#define PUF_IDXBLK_L_IDX3_SHIFT (6U)\r
+#define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK)\r
+#define PUF_IDXBLK_L_IDX4_MASK (0x300U)\r
+#define PUF_IDXBLK_L_IDX4_SHIFT (8U)\r
+#define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK)\r
+#define PUF_IDXBLK_L_IDX5_MASK (0xC00U)\r
+#define PUF_IDXBLK_L_IDX5_SHIFT (10U)\r
+#define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK)\r
+#define PUF_IDXBLK_L_IDX6_MASK (0x3000U)\r
+#define PUF_IDXBLK_L_IDX6_SHIFT (12U)\r
+#define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK)\r
+#define PUF_IDXBLK_L_IDX7_MASK (0xC000U)\r
+#define PUF_IDXBLK_L_IDX7_SHIFT (14U)\r
+#define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK)\r
+#define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U)\r
+#define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U)\r
+#define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDXBLK_H_DP - */\r
+/*! @{ */\r
+#define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U)\r
+#define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U)\r
+#define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU)\r
+#define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U)\r
+#define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U)\r
+#define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U)\r
+#define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U)\r
+#define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U)\r
+#define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U)\r
+#define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U)\r
+#define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U)\r
+#define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U)\r
+#define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U)\r
+#define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U)\r
+#define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK)\r
+#define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U)\r
+#define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U)\r
+#define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEYMASK - Only reset in case of full IC reset */\r
+/*! @{ */\r
+#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU)\r
+#define PUF_KEYMASK_KEYMASK_SHIFT (0U)\r
+#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)\r
+/*! @} */\r
+\r
+/* The count of PUF_KEYMASK */\r
+#define PUF_KEYMASK_COUNT (4U)\r
+\r
+/*! @name IDXBLK_H - */\r
+/*! @{ */\r
+#define PUF_IDXBLK_H_IDX8_MASK (0x3U)\r
+#define PUF_IDXBLK_H_IDX8_SHIFT (0U)\r
+#define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK)\r
+#define PUF_IDXBLK_H_IDX9_MASK (0xCU)\r
+#define PUF_IDXBLK_H_IDX9_SHIFT (2U)\r
+#define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK)\r
+#define PUF_IDXBLK_H_IDX10_MASK (0x30U)\r
+#define PUF_IDXBLK_H_IDX10_SHIFT (4U)\r
+#define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK)\r
+#define PUF_IDXBLK_H_IDX11_MASK (0xC0U)\r
+#define PUF_IDXBLK_H_IDX11_SHIFT (6U)\r
+#define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK)\r
+#define PUF_IDXBLK_H_IDX12_MASK (0x300U)\r
+#define PUF_IDXBLK_H_IDX12_SHIFT (8U)\r
+#define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK)\r
+#define PUF_IDXBLK_H_IDX13_MASK (0xC00U)\r
+#define PUF_IDXBLK_H_IDX13_SHIFT (10U)\r
+#define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK)\r
+#define PUF_IDXBLK_H_IDX14_MASK (0x3000U)\r
+#define PUF_IDXBLK_H_IDX14_SHIFT (12U)\r
+#define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK)\r
+#define PUF_IDXBLK_H_IDX15_MASK (0xC000U)\r
+#define PUF_IDXBLK_H_IDX15_SHIFT (14U)\r
+#define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK)\r
+#define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U)\r
+#define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U)\r
+#define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDXBLK_L_DP - */\r
+/*! @{ */\r
+#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U)\r
+#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U)\r
+#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU)\r
+#define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U)\r
+#define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U)\r
+#define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U)\r
+#define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U)\r
+#define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U)\r
+#define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U)\r
+#define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U)\r
+#define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U)\r
+#define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U)\r
+#define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U)\r
+#define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U)\r
+#define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK)\r
+#define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U)\r
+#define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U)\r
+#define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK)\r
+/*! @} */\r
+\r
+/*! @name SHIFT_STATUS - */\r
+/*! @{ */\r
+#define PUF_SHIFT_STATUS_KEY0_MASK (0xFU)\r
+#define PUF_SHIFT_STATUS_KEY0_SHIFT (0U)\r
+#define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK)\r
+#define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U)\r
+#define PUF_SHIFT_STATUS_KEY1_SHIFT (4U)\r
+#define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK)\r
+#define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U)\r
+#define PUF_SHIFT_STATUS_KEY2_SHIFT (8U)\r
+#define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK)\r
+#define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U)\r
+#define PUF_SHIFT_STATUS_KEY3_SHIFT (12U)\r
+#define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PUF_Register_Masks */\r
+\r
+\r
+/* PUF - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral PUF base address */\r
+ #define PUF_BASE (0x5003B000u)\r
+ /** Peripheral PUF base address */\r
+ #define PUF_BASE_NS (0x4003B000u)\r
+ /** Peripheral PUF base pointer */\r
+ #define PUF ((PUF_Type *)PUF_BASE)\r
+ /** Peripheral PUF base pointer */\r
+ #define PUF_NS ((PUF_Type *)PUF_BASE_NS)\r
+ /** Array initializer of PUF peripheral base addresses */\r
+ #define PUF_BASE_ADDRS { PUF_BASE }\r
+ /** Array initializer of PUF peripheral base pointers */\r
+ #define PUF_BASE_PTRS { PUF }\r
+ /** Array initializer of PUF peripheral base addresses */\r
+ #define PUF_BASE_ADDRS_NS { PUF_BASE_NS }\r
+ /** Array initializer of PUF peripheral base pointers */\r
+ #define PUF_BASE_PTRS_NS { PUF_NS }\r
+#else\r
+ /** Peripheral PUF base address */\r
+ #define PUF_BASE (0x4003B000u)\r
+ /** Peripheral PUF base pointer */\r
+ #define PUF ((PUF_Type *)PUF_BASE)\r
+ /** Array initializer of PUF peripheral base addresses */\r
+ #define PUF_BASE_ADDRS { PUF_BASE }\r
+ /** Array initializer of PUF peripheral base pointers */\r
+ #define PUF_BASE_PTRS { PUF }\r
+#endif\r
+/** Interrupt vectors for the PUF peripheral type */\r
+#define PUF_IRQS { PUF_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group PUF_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RNG Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** RNG - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */\r
+ __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */\r
+ __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */\r
+ __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */\r
+ __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */\r
+ __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */\r
+ __IO uint32_t MISC_CFG; /**< , offset: 0x18 */\r
+ uint8_t RESERVED_0[4056];\r
+ __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */\r
+ uint8_t RESERVED_1[4];\r
+ __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */\r
+} RNG_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RNG Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RNG_Register_Masks RNG Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */\r
+/*! @{ */\r
+#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU)\r
+#define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U)\r
+#define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK)\r
+/*! @} */\r
+\r
+/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */\r
+/*! @{ */\r
+#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU)\r
+#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U)\r
+#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNTER_VAL - */\r
+/*! @{ */\r
+#define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU)\r
+#define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U)\r
+#define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK)\r
+#define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U)\r
+#define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U)\r
+#define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNTER_CFG - */\r
+/*! @{ */\r
+#define RNG_COUNTER_CFG_MODE_MASK (0x3U)\r
+#define RNG_COUNTER_CFG_MODE_SHIFT (0U)\r
+#define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK)\r
+#define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU)\r
+#define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U)\r
+#define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK)\r
+#define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U)\r
+#define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U)\r
+#define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK)\r
+#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U)\r
+#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U)\r
+#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK)\r
+#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U)\r
+#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U)\r
+#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK)\r
+/*! @} */\r
+\r
+/*! @name ONLINE_TEST_CFG - */\r
+/*! @{ */\r
+#define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U)\r
+#define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U)\r
+#define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK)\r
+#define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U)\r
+#define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U)\r
+#define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ONLINE_TEST_VAL - */\r
+/*! @{ */\r
+#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU)\r
+#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U)\r
+#define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK)\r
+#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U)\r
+#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U)\r
+#define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK)\r
+#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U)\r
+#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U)\r
+#define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK)\r
+/*! @} */\r
+\r
+/*! @name MISC_CFG - */\r
+/*! @{ */\r
+#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U)\r
+#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U)\r
+#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK)\r
+#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U)\r
+#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U)\r
+#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK)\r
+/*! @} */\r
+\r
+/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */\r
+/*! @{ */\r
+#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U)\r
+#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U)\r
+#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK)\r
+#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U)\r
+#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U)\r
+#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK)\r
+#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U)\r
+#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U)\r
+#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK)\r
+/*! @} */\r
+\r
+/*! @name MODULEID - IP identifier */\r
+/*! @{ */\r
+#define RNG_MODULEID_APERTURE_MASK (0xFFU)\r
+#define RNG_MODULEID_APERTURE_SHIFT (0U)\r
+#define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK)\r
+#define RNG_MODULEID_MIN_REV_MASK (0xF00U)\r
+#define RNG_MODULEID_MIN_REV_SHIFT (8U)\r
+#define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK)\r
+#define RNG_MODULEID_MAJ_REV_MASK (0xF000U)\r
+#define RNG_MODULEID_MAJ_REV_SHIFT (12U)\r
+#define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK)\r
+#define RNG_MODULEID_ID_MASK (0xFFFF0000U)\r
+#define RNG_MODULEID_ID_SHIFT (16U)\r
+#define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RNG_Register_Masks */\r
+\r
+\r
+/* RNG - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral RNG base address */\r
+ #define RNG_BASE (0x5003A000u)\r
+ /** Peripheral RNG base address */\r
+ #define RNG_BASE_NS (0x4003A000u)\r
+ /** Peripheral RNG base pointer */\r
+ #define RNG ((RNG_Type *)RNG_BASE)\r
+ /** Peripheral RNG base pointer */\r
+ #define RNG_NS ((RNG_Type *)RNG_BASE_NS)\r
+ /** Array initializer of RNG peripheral base addresses */\r
+ #define RNG_BASE_ADDRS { RNG_BASE }\r
+ /** Array initializer of RNG peripheral base pointers */\r
+ #define RNG_BASE_PTRS { RNG }\r
+ /** Array initializer of RNG peripheral base addresses */\r
+ #define RNG_BASE_ADDRS_NS { RNG_BASE_NS }\r
+ /** Array initializer of RNG peripheral base pointers */\r
+ #define RNG_BASE_PTRS_NS { RNG_NS }\r
+#else\r
+ /** Peripheral RNG base address */\r
+ #define RNG_BASE (0x4003A000u)\r
+ /** Peripheral RNG base pointer */\r
+ #define RNG ((RNG_Type *)RNG_BASE)\r
+ /** Array initializer of RNG peripheral base addresses */\r
+ #define RNG_BASE_ADDRS { RNG_BASE }\r
+ /** Array initializer of RNG peripheral base pointers */\r
+ #define RNG_BASE_PTRS { RNG }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RNG_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RTC Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** RTC - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */\r
+ __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */\r
+ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */\r
+ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */\r
+ __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */\r
+ uint8_t RESERVED_0[44];\r
+ __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */\r
+} RTC_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- RTC Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup RTC_Register_Masks RTC Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - RTC control register */\r
+/*! @{ */\r
+#define RTC_CTRL_SWRESET_MASK (0x1U)\r
+#define RTC_CTRL_SWRESET_SHIFT (0U)\r
+/*! SWRESET - Software reset control\r
+ * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC.\r
+ * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared.\r
+ */\r
+#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)\r
+#define RTC_CTRL_ALARM1HZ_MASK (0x4U)\r
+#define RTC_CTRL_ALARM1HZ_SHIFT (2U)\r
+/*! ALARM1HZ - RTC 1 Hz timer alarm flag status.\r
+ * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect.\r
+ * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit.\r
+ */\r
+#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)\r
+#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)\r
+#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)\r
+/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status.\r
+ * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect.\r
+ * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit.\r
+ */\r
+#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)\r
+#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)\r
+#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)\r
+/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down.\r
+ * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.\r
+ * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode.\r
+ */\r
+#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)\r
+#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)\r
+#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)\r
+/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down.\r
+ * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.\r
+ * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode.\r
+ */\r
+#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)\r
+#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)\r
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)\r
+/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).\r
+ * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode.\r
+ * 0b1..Enable. The 1 kHz RTC timer is enabled.\r
+ */\r
+#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)\r
+#define RTC_CTRL_RTC_EN_MASK (0x80U)\r
+#define RTC_CTRL_RTC_EN_SHIFT (7U)\r
+/*! RTC_EN - RTC enable.\r
+ * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register.\r
+ * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register.\r
+ */\r
+#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)\r
+#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)\r
+#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)\r
+/*! RTC_OSC_PD - RTC oscillator power-down control.\r
+ * 0b0..See RTC_OSC_BYPASS\r
+ * 0b1..RTC oscillator is powered-down.\r
+ */\r
+#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)\r
+#define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U)\r
+#define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U)\r
+/*! RTC_OSC_BYPASS - RTC oscillator bypass control.\r
+ * 0b0..The RTC Oscillator operates normally as a crystal oscillator with the crystal connected between the RTC_XTALIN and RTC_XTALOUT pins.\r
+ * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin.\r
+ */\r
+#define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK)\r
+#define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U)\r
+#define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U)\r
+/*! RTC_SUBSEC_ENA - RTC Sub-second counter control.\r
+ * 0b0..The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'.\r
+ * 0b1..The 32 KHz sub-second counter is enabled (if implemented). Counting commences on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) is set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep power-down mode.\r
+ */\r
+#define RTC_CTRL_RTC_SUBSEC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_SUBSEC_ENA_SHIFT)) & RTC_CTRL_RTC_SUBSEC_ENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name MATCH - RTC match register */\r
+/*! @{ */\r
+#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)\r
+#define RTC_MATCH_MATVAL_SHIFT (0U)\r
+#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNT - RTC counter register */\r
+/*! @{ */\r
+#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)\r
+#define RTC_COUNT_VAL_SHIFT (0U)\r
+#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name WAKE - High-resolution/wake-up timer control register */\r
+/*! @{ */\r
+#define RTC_WAKE_VAL_MASK (0xFFFFU)\r
+#define RTC_WAKE_VAL_SHIFT (0U)\r
+#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SUBSEC - RTC Sub-second Counter register */\r
+/*! @{ */\r
+#define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU)\r
+#define RTC_SUBSEC_SUBSEC_SHIFT (0U)\r
+#define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK)\r
+/*! @} */\r
+\r
+/*! @name GPREG - General Purpose register */\r
+/*! @{ */\r
+#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)\r
+#define RTC_GPREG_GPDATA_SHIFT (0U)\r
+#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of RTC_GPREG */\r
+#define RTC_GPREG_COUNT (8U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RTC_Register_Masks */\r
+\r
+\r
+/* RTC - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral RTC base address */\r
+ #define RTC_BASE (0x5002C000u)\r
+ /** Peripheral RTC base address */\r
+ #define RTC_BASE_NS (0x4002C000u)\r
+ /** Peripheral RTC base pointer */\r
+ #define RTC ((RTC_Type *)RTC_BASE)\r
+ /** Peripheral RTC base pointer */\r
+ #define RTC_NS ((RTC_Type *)RTC_BASE_NS)\r
+ /** Array initializer of RTC peripheral base addresses */\r
+ #define RTC_BASE_ADDRS { RTC_BASE }\r
+ /** Array initializer of RTC peripheral base pointers */\r
+ #define RTC_BASE_PTRS { RTC }\r
+ /** Array initializer of RTC peripheral base addresses */\r
+ #define RTC_BASE_ADDRS_NS { RTC_BASE_NS }\r
+ /** Array initializer of RTC peripheral base pointers */\r
+ #define RTC_BASE_PTRS_NS { RTC_NS }\r
+#else\r
+ /** Peripheral RTC base address */\r
+ #define RTC_BASE (0x4002C000u)\r
+ /** Peripheral RTC base pointer */\r
+ #define RTC ((RTC_Type *)RTC_BASE)\r
+ /** Array initializer of RTC peripheral base addresses */\r
+ #define RTC_BASE_ADDRS { RTC_BASE }\r
+ /** Array initializer of RTC peripheral base pointers */\r
+ #define RTC_BASE_PTRS { RTC }\r
+#endif\r
+/** Interrupt vectors for the RTC peripheral type */\r
+#define RTC_IRQS { RTC_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group RTC_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SCT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SCT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */\r
+ __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */\r
+ __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */\r
+ __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */\r
+ __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */\r
+ __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */\r
+ uint8_t RESERVED_0[40];\r
+ __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */\r
+ __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */\r
+ __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */\r
+ __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */\r
+ __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */\r
+ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */\r
+ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */\r
+ __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */\r
+ __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */\r
+ uint8_t RESERVED_1[140];\r
+ __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */\r
+ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */\r
+ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */\r
+ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */\r
+ union { /* offset: 0x100 */\r
+ __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */\r
+ __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_2[216];\r
+ union { /* offset: 0x200 */\r
+ __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */\r
+ __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_3[216];\r
+ struct { /* offset: 0x300, array step: 0x8 */\r
+ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */\r
+ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */\r
+ } EVENT[10];\r
+ uint8_t RESERVED_4[432];\r
+ struct { /* offset: 0x500, array step: 0x8 */\r
+ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */\r
+ __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */\r
+ } OUT[10];\r
+} SCT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SCT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SCT_Register_Masks SCT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CONFIG - SCT configuration register */\r
+/*! @{ */\r
+#define SCT_CONFIG_UNIFY_MASK (0x1U)\r
+#define SCT_CONFIG_UNIFY_SHIFT (0U)\r
+/*! UNIFY - SCT operation\r
+ * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H.\r
+ * 0b1..The SCT operates as a unified 32-bit counter.\r
+ */\r
+#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)\r
+#define SCT_CONFIG_CLKMODE_MASK (0x6U)\r
+#define SCT_CONFIG_CLKMODE_SHIFT (1U)\r
+/*! CLKMODE - SCT clock mode\r
+ * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers.\r
+ * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode.\r
+ * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode.\r
+ * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock.\r
+ */\r
+#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)\r
+#define SCT_CONFIG_CKSEL_MASK (0x78U)\r
+#define SCT_CONFIG_CKSEL_SHIFT (3U)\r
+/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register.\r
+ * 0b0000..Rising edges on input 0.\r
+ * 0b0001..Falling edges on input 0.\r
+ * 0b0010..Rising edges on input 1.\r
+ * 0b0011..Falling edges on input 1.\r
+ * 0b0100..Rising edges on input 2.\r
+ * 0b0101..Falling edges on input 2.\r
+ * 0b0110..Rising edges on input 3.\r
+ * 0b0111..Falling edges on input 3.\r
+ */\r
+#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)\r
+#define SCT_CONFIG_NORELAOD_L_MASK (0x80U)\r
+#define SCT_CONFIG_NORELAOD_L_SHIFT (7U)\r
+#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)\r
+#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)\r
+#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)\r
+#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)\r
+#define SCT_CONFIG_INSYNC_MASK (0x1E00U)\r
+#define SCT_CONFIG_INSYNC_SHIFT (9U)\r
+#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)\r
+#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)\r
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)\r
+#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)\r
+#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)\r
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)\r
+#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL - SCT control register */\r
+/*! @{ */\r
+#define SCT_CTRL_DOWN_L_MASK (0x1U)\r
+#define SCT_CTRL_DOWN_L_SHIFT (0U)\r
+#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)\r
+#define SCT_CTRL_STOP_L_MASK (0x2U)\r
+#define SCT_CTRL_STOP_L_SHIFT (1U)\r
+#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)\r
+#define SCT_CTRL_HALT_L_MASK (0x4U)\r
+#define SCT_CTRL_HALT_L_SHIFT (2U)\r
+#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)\r
+#define SCT_CTRL_CLRCTR_L_MASK (0x8U)\r
+#define SCT_CTRL_CLRCTR_L_SHIFT (3U)\r
+#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)\r
+#define SCT_CTRL_BIDIR_L_MASK (0x10U)\r
+#define SCT_CTRL_BIDIR_L_SHIFT (4U)\r
+/*! BIDIR_L - L or unified counter direction select\r
+ * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero.\r
+ * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0.\r
+ */\r
+#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)\r
+#define SCT_CTRL_PRE_L_MASK (0x1FE0U)\r
+#define SCT_CTRL_PRE_L_SHIFT (5U)\r
+#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)\r
+#define SCT_CTRL_DOWN_H_MASK (0x10000U)\r
+#define SCT_CTRL_DOWN_H_SHIFT (16U)\r
+#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)\r
+#define SCT_CTRL_STOP_H_MASK (0x20000U)\r
+#define SCT_CTRL_STOP_H_SHIFT (17U)\r
+#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)\r
+#define SCT_CTRL_HALT_H_MASK (0x40000U)\r
+#define SCT_CTRL_HALT_H_SHIFT (18U)\r
+#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)\r
+#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)\r
+#define SCT_CTRL_CLRCTR_H_SHIFT (19U)\r
+#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)\r
+#define SCT_CTRL_BIDIR_H_MASK (0x100000U)\r
+#define SCT_CTRL_BIDIR_H_SHIFT (20U)\r
+/*! BIDIR_H - Direction select\r
+ * 0b0..The H counter counts up to its limit condition, then is cleared to zero.\r
+ * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0.\r
+ */\r
+#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)\r
+#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)\r
+#define SCT_CTRL_PRE_H_SHIFT (21U)\r
+#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name LIMIT - SCT limit event select register */\r
+/*! @{ */\r
+#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)\r
+#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)\r
+#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)\r
+#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)\r
+#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name HALT - SCT halt event select register */\r
+/*! @{ */\r
+#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)\r
+#define SCT_HALT_HALTMSK_L_SHIFT (0U)\r
+#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)\r
+#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_HALT_HALTMSK_H_SHIFT (16U)\r
+#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name STOP - SCT stop event select register */\r
+/*! @{ */\r
+#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)\r
+#define SCT_STOP_STOPMSK_L_SHIFT (0U)\r
+#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)\r
+#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_STOP_STOPMSK_H_SHIFT (16U)\r
+#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name START - SCT start event select register */\r
+/*! @{ */\r
+#define SCT_START_STARTMSK_L_MASK (0xFFFFU)\r
+#define SCT_START_STARTMSK_L_SHIFT (0U)\r
+#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)\r
+#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)\r
+#define SCT_START_STARTMSK_H_SHIFT (16U)\r
+#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name COUNT - SCT counter register */\r
+/*! @{ */\r
+#define SCT_COUNT_CTR_L_MASK (0xFFFFU)\r
+#define SCT_COUNT_CTR_L_SHIFT (0U)\r
+#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)\r
+#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)\r
+#define SCT_COUNT_CTR_H_SHIFT (16U)\r
+#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATE - SCT state register */\r
+/*! @{ */\r
+#define SCT_STATE_STATE_L_MASK (0x1FU)\r
+#define SCT_STATE_STATE_L_SHIFT (0U)\r
+#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)\r
+#define SCT_STATE_STATE_H_MASK (0x1F0000U)\r
+#define SCT_STATE_STATE_H_SHIFT (16U)\r
+#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name INPUT - SCT input register */\r
+/*! @{ */\r
+#define SCT_INPUT_AIN0_MASK (0x1U)\r
+#define SCT_INPUT_AIN0_SHIFT (0U)\r
+#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)\r
+#define SCT_INPUT_AIN1_MASK (0x2U)\r
+#define SCT_INPUT_AIN1_SHIFT (1U)\r
+#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)\r
+#define SCT_INPUT_AIN2_MASK (0x4U)\r
+#define SCT_INPUT_AIN2_SHIFT (2U)\r
+#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)\r
+#define SCT_INPUT_AIN3_MASK (0x8U)\r
+#define SCT_INPUT_AIN3_SHIFT (3U)\r
+#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)\r
+#define SCT_INPUT_AIN4_MASK (0x10U)\r
+#define SCT_INPUT_AIN4_SHIFT (4U)\r
+#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)\r
+#define SCT_INPUT_AIN5_MASK (0x20U)\r
+#define SCT_INPUT_AIN5_SHIFT (5U)\r
+#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)\r
+#define SCT_INPUT_AIN6_MASK (0x40U)\r
+#define SCT_INPUT_AIN6_SHIFT (6U)\r
+#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)\r
+#define SCT_INPUT_AIN7_MASK (0x80U)\r
+#define SCT_INPUT_AIN7_SHIFT (7U)\r
+#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)\r
+#define SCT_INPUT_AIN8_MASK (0x100U)\r
+#define SCT_INPUT_AIN8_SHIFT (8U)\r
+#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)\r
+#define SCT_INPUT_AIN9_MASK (0x200U)\r
+#define SCT_INPUT_AIN9_SHIFT (9U)\r
+#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)\r
+#define SCT_INPUT_AIN10_MASK (0x400U)\r
+#define SCT_INPUT_AIN10_SHIFT (10U)\r
+#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)\r
+#define SCT_INPUT_AIN11_MASK (0x800U)\r
+#define SCT_INPUT_AIN11_SHIFT (11U)\r
+#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)\r
+#define SCT_INPUT_AIN12_MASK (0x1000U)\r
+#define SCT_INPUT_AIN12_SHIFT (12U)\r
+#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)\r
+#define SCT_INPUT_AIN13_MASK (0x2000U)\r
+#define SCT_INPUT_AIN13_SHIFT (13U)\r
+#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)\r
+#define SCT_INPUT_AIN14_MASK (0x4000U)\r
+#define SCT_INPUT_AIN14_SHIFT (14U)\r
+#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)\r
+#define SCT_INPUT_AIN15_MASK (0x8000U)\r
+#define SCT_INPUT_AIN15_SHIFT (15U)\r
+#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)\r
+#define SCT_INPUT_SIN0_MASK (0x10000U)\r
+#define SCT_INPUT_SIN0_SHIFT (16U)\r
+#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)\r
+#define SCT_INPUT_SIN1_MASK (0x20000U)\r
+#define SCT_INPUT_SIN1_SHIFT (17U)\r
+#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)\r
+#define SCT_INPUT_SIN2_MASK (0x40000U)\r
+#define SCT_INPUT_SIN2_SHIFT (18U)\r
+#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)\r
+#define SCT_INPUT_SIN3_MASK (0x80000U)\r
+#define SCT_INPUT_SIN3_SHIFT (19U)\r
+#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)\r
+#define SCT_INPUT_SIN4_MASK (0x100000U)\r
+#define SCT_INPUT_SIN4_SHIFT (20U)\r
+#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)\r
+#define SCT_INPUT_SIN5_MASK (0x200000U)\r
+#define SCT_INPUT_SIN5_SHIFT (21U)\r
+#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)\r
+#define SCT_INPUT_SIN6_MASK (0x400000U)\r
+#define SCT_INPUT_SIN6_SHIFT (22U)\r
+#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)\r
+#define SCT_INPUT_SIN7_MASK (0x800000U)\r
+#define SCT_INPUT_SIN7_SHIFT (23U)\r
+#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)\r
+#define SCT_INPUT_SIN8_MASK (0x1000000U)\r
+#define SCT_INPUT_SIN8_SHIFT (24U)\r
+#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)\r
+#define SCT_INPUT_SIN9_MASK (0x2000000U)\r
+#define SCT_INPUT_SIN9_SHIFT (25U)\r
+#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)\r
+#define SCT_INPUT_SIN10_MASK (0x4000000U)\r
+#define SCT_INPUT_SIN10_SHIFT (26U)\r
+#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)\r
+#define SCT_INPUT_SIN11_MASK (0x8000000U)\r
+#define SCT_INPUT_SIN11_SHIFT (27U)\r
+#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)\r
+#define SCT_INPUT_SIN12_MASK (0x10000000U)\r
+#define SCT_INPUT_SIN12_SHIFT (28U)\r
+#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)\r
+#define SCT_INPUT_SIN13_MASK (0x20000000U)\r
+#define SCT_INPUT_SIN13_SHIFT (29U)\r
+#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)\r
+#define SCT_INPUT_SIN14_MASK (0x40000000U)\r
+#define SCT_INPUT_SIN14_SHIFT (30U)\r
+#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)\r
+#define SCT_INPUT_SIN15_MASK (0x80000000U)\r
+#define SCT_INPUT_SIN15_SHIFT (31U)\r
+#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)\r
+/*! @} */\r
+\r
+/*! @name REGMODE - SCT match/capture mode register */\r
+/*! @{ */\r
+#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)\r
+#define SCT_REGMODE_REGMOD_L_SHIFT (0U)\r
+#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)\r
+#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)\r
+#define SCT_REGMODE_REGMOD_H_SHIFT (16U)\r
+#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)\r
+/*! @} */\r
+\r
+/*! @name OUTPUT - SCT output register */\r
+/*! @{ */\r
+#define SCT_OUTPUT_OUT_MASK (0xFFFFU)\r
+#define SCT_OUTPUT_OUT_SHIFT (0U)\r
+#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */\r
+/*! @{ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)\r
+/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)\r
+/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)\r
+/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)\r
+/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)\r
+/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)\r
+/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)\r
+/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)\r
+/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)\r
+/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)\r
+/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)\r
+/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)\r
+/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)\r
+/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)\r
+/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)\r
+/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)\r
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)\r
+/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value.\r
+ * 0b00..Set and clear do not depend on the direction of any counter.\r
+ * 0b01..Set and clear are reversed when counter L or the unified counter is counting down.\r
+ * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.\r
+ */\r
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)\r
+/*! @} */\r
+\r
+/*! @name RES - SCT conflict resolution register */\r
+/*! @{ */\r
+#define SCT_RES_O0RES_MASK (0x3U)\r
+#define SCT_RES_O0RES_SHIFT (0U)\r
+/*! O0RES - Effect of simultaneous set and clear on output 0.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR0 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)\r
+#define SCT_RES_O1RES_MASK (0xCU)\r
+#define SCT_RES_O1RES_SHIFT (2U)\r
+/*! O1RES - Effect of simultaneous set and clear on output 1.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR1 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)\r
+#define SCT_RES_O2RES_MASK (0x30U)\r
+#define SCT_RES_O2RES_SHIFT (4U)\r
+/*! O2RES - Effect of simultaneous set and clear on output 2.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output n (or set based on the SETCLR2 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)\r
+#define SCT_RES_O3RES_MASK (0xC0U)\r
+#define SCT_RES_O3RES_SHIFT (6U)\r
+/*! O3RES - Effect of simultaneous set and clear on output 3.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR3 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)\r
+#define SCT_RES_O4RES_MASK (0x300U)\r
+#define SCT_RES_O4RES_SHIFT (8U)\r
+/*! O4RES - Effect of simultaneous set and clear on output 4.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR4 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)\r
+#define SCT_RES_O5RES_MASK (0xC00U)\r
+#define SCT_RES_O5RES_SHIFT (10U)\r
+/*! O5RES - Effect of simultaneous set and clear on output 5.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR5 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)\r
+#define SCT_RES_O6RES_MASK (0x3000U)\r
+#define SCT_RES_O6RES_SHIFT (12U)\r
+/*! O6RES - Effect of simultaneous set and clear on output 6.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR6 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)\r
+#define SCT_RES_O7RES_MASK (0xC000U)\r
+#define SCT_RES_O7RES_SHIFT (14U)\r
+/*! O7RES - Effect of simultaneous set and clear on output 7.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output n (or set based on the SETCLR7 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)\r
+#define SCT_RES_O8RES_MASK (0x30000U)\r
+#define SCT_RES_O8RES_SHIFT (16U)\r
+/*! O8RES - Effect of simultaneous set and clear on output 8.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR8 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)\r
+#define SCT_RES_O9RES_MASK (0xC0000U)\r
+#define SCT_RES_O9RES_SHIFT (18U)\r
+/*! O9RES - Effect of simultaneous set and clear on output 9.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR9 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)\r
+#define SCT_RES_O10RES_MASK (0x300000U)\r
+#define SCT_RES_O10RES_SHIFT (20U)\r
+/*! O10RES - Effect of simultaneous set and clear on output 10.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR10 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)\r
+#define SCT_RES_O11RES_MASK (0xC00000U)\r
+#define SCT_RES_O11RES_SHIFT (22U)\r
+/*! O11RES - Effect of simultaneous set and clear on output 11.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR11 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)\r
+#define SCT_RES_O12RES_MASK (0x3000000U)\r
+#define SCT_RES_O12RES_SHIFT (24U)\r
+/*! O12RES - Effect of simultaneous set and clear on output 12.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR12 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)\r
+#define SCT_RES_O13RES_MASK (0xC000000U)\r
+#define SCT_RES_O13RES_SHIFT (26U)\r
+/*! O13RES - Effect of simultaneous set and clear on output 13.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR13 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)\r
+#define SCT_RES_O14RES_MASK (0x30000000U)\r
+#define SCT_RES_O14RES_SHIFT (28U)\r
+/*! O14RES - Effect of simultaneous set and clear on output 14.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR14 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)\r
+#define SCT_RES_O15RES_MASK (0xC0000000U)\r
+#define SCT_RES_O15RES_SHIFT (30U)\r
+/*! O15RES - Effect of simultaneous set and clear on output 15.\r
+ * 0b00..No change.\r
+ * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register).\r
+ * 0b10..Clear output (or set based on the SETCLR15 field).\r
+ * 0b11..Toggle output.\r
+ */\r
+#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA0REQUEST - SCT DMA request 0 register */\r
+/*! @{ */\r
+#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU)\r
+#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U)\r
+#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)\r
+#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U)\r
+#define SCT_DMA0REQUEST_DRL0_SHIFT (30U)\r
+#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)\r
+#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U)\r
+#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U)\r
+#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)\r
+/*! @} */\r
+\r
+/*! @name DMA1REQUEST - SCT DMA request 1 register */\r
+/*! @{ */\r
+#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU)\r
+#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U)\r
+#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)\r
+#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U)\r
+#define SCT_DMA1REQUEST_DRL1_SHIFT (30U)\r
+#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)\r
+#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U)\r
+#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U)\r
+#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVEN - SCT event interrupt enable register */\r
+/*! @{ */\r
+#define SCT_EVEN_IEN_MASK (0xFFFFU)\r
+#define SCT_EVEN_IEN_SHIFT (0U)\r
+#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name EVFLAG - SCT event flag register */\r
+/*! @{ */\r
+#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)\r
+#define SCT_EVFLAG_FLAG_SHIFT (0U)\r
+#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONEN - SCT conflict interrupt enable register */\r
+/*! @{ */\r
+#define SCT_CONEN_NCEN_MASK (0xFFFFU)\r
+#define SCT_CONEN_NCEN_SHIFT (0U)\r
+#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CONFLAG - SCT conflict flag register */\r
+/*! @{ */\r
+#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)\r
+#define SCT_CONFLAG_NCFLAG_SHIFT (0U)\r
+#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)\r
+#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)\r
+#define SCT_CONFLAG_BUSERRL_SHIFT (30U)\r
+#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)\r
+#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)\r
+#define SCT_CONFLAG_BUSERRH_SHIFT (31U)\r
+#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCTCAP - SCT capture register of capture channel */\r
+/*! @{ */\r
+#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU)\r
+#define SCT_SCTCAP_CAPn_L_SHIFT (0U)\r
+#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)\r
+#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U)\r
+#define SCT_SCTCAP_CAPn_H_SHIFT (16U)\r
+#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_SCTCAP */\r
+#define SCT_SCTCAP_COUNT (10U)\r
+\r
+/*! @name SCTMATCH - SCT match value register of match channels */\r
+/*! @{ */\r
+#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU)\r
+#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U)\r
+#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)\r
+#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U)\r
+#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U)\r
+#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_SCTMATCH */\r
+#define SCT_SCTMATCH_COUNT (10U)\r
+\r
+/*! @name SCTCAPCTRL - SCT capture control register */\r
+/*! @{ */\r
+#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU)\r
+#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U)\r
+#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)\r
+#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)\r
+#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U)\r
+#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_SCTCAPCTRL */\r
+#define SCT_SCTCAPCTRL_COUNT (10U)\r
+\r
+/*! @name SCTMATCHREL - SCT match reload value register */\r
+/*! @{ */\r
+#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU)\r
+#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U)\r
+#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)\r
+#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U)\r
+#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U)\r
+#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_SCTMATCHREL */\r
+#define SCT_SCTMATCHREL_COUNT (10U)\r
+\r
+/*! @name EVENT_STATE - SCT event state register 0 */\r
+/*! @{ */\r
+#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU)\r
+#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U)\r
+#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_EVENT_STATE */\r
+#define SCT_EVENT_STATE_COUNT (10U)\r
+\r
+/*! @name EVENT_CTRL - SCT event control register 0 */\r
+/*! @{ */\r
+#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU)\r
+#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U)\r
+#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)\r
+#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U)\r
+#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U)\r
+/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1.\r
+ * 0b0..Selects the L state and the L match register selected by MATCHSEL.\r
+ * 0b1..Selects the H state and the H match register selected by MATCHSEL.\r
+ */\r
+#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)\r
+#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U)\r
+#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U)\r
+/*! OUTSEL - Input/output select\r
+ * 0b0..Selects the inputs selected by IOSEL.\r
+ * 0b1..Selects the outputs selected by IOSEL.\r
+ */\r
+#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)\r
+#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U)\r
+#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U)\r
+#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)\r
+#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U)\r
+#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U)\r
+/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period .\r
+ * 0b00..LOW\r
+ * 0b01..Rise\r
+ * 0b10..Fall\r
+ * 0b11..HIGH\r
+ */\r
+#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)\r
+#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U)\r
+#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U)\r
+/*! COMBMODE - Selects how the specified match and I/O condition are used and combined.\r
+ * 0b00..OR. The event occurs when either the specified match or I/O condition occurs.\r
+ * 0b01..MATCH. Uses the specified match only.\r
+ * 0b10..IO. Uses the specified I/O condition only.\r
+ * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously.\r
+ */\r
+#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)\r
+#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U)\r
+#define SCT_EVENT_CTRL_STATELD_SHIFT (14U)\r
+/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state.\r
+ * 0b0..STATEV value is added into STATE (the carry-out is ignored).\r
+ * 0b1..STATEV value is loaded into STATE.\r
+ */\r
+#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)\r
+#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U)\r
+#define SCT_EVENT_CTRL_STATEV_SHIFT (15U)\r
+#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)\r
+#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U)\r
+#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U)\r
+#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)\r
+#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U)\r
+#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U)\r
+/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved.\r
+ * 0b00..Direction independent. This event is triggered regardless of the count direction.\r
+ * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1.\r
+ * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1.\r
+ */\r
+#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_EVENT_CTRL */\r
+#define SCT_EVENT_CTRL_COUNT (10U)\r
+\r
+/*! @name OUT_SET - SCT output 0 set register */\r
+/*! @{ */\r
+#define SCT_OUT_SET_SET_MASK (0xFFFFU)\r
+#define SCT_OUT_SET_SET_SHIFT (0U)\r
+#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_OUT_SET */\r
+#define SCT_OUT_SET_COUNT (10U)\r
+\r
+/*! @name OUT_CLR - SCT output 0 clear register */\r
+/*! @{ */\r
+#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)\r
+#define SCT_OUT_CLR_CLR_SHIFT (0U)\r
+#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of SCT_OUT_CLR */\r
+#define SCT_OUT_CLR_COUNT (10U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SCT_Register_Masks */\r
+\r
+\r
+/* SCT - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral SCT0 base address */\r
+ #define SCT0_BASE (0x50085000u)\r
+ /** Peripheral SCT0 base address */\r
+ #define SCT0_BASE_NS (0x40085000u)\r
+ /** Peripheral SCT0 base pointer */\r
+ #define SCT0 ((SCT_Type *)SCT0_BASE)\r
+ /** Peripheral SCT0 base pointer */\r
+ #define SCT0_NS ((SCT_Type *)SCT0_BASE_NS)\r
+ /** Array initializer of SCT peripheral base addresses */\r
+ #define SCT_BASE_ADDRS { SCT0_BASE }\r
+ /** Array initializer of SCT peripheral base pointers */\r
+ #define SCT_BASE_PTRS { SCT0 }\r
+ /** Array initializer of SCT peripheral base addresses */\r
+ #define SCT_BASE_ADDRS_NS { SCT0_BASE_NS }\r
+ /** Array initializer of SCT peripheral base pointers */\r
+ #define SCT_BASE_PTRS_NS { SCT0_NS }\r
+#else\r
+ /** Peripheral SCT0 base address */\r
+ #define SCT0_BASE (0x40085000u)\r
+ /** Peripheral SCT0 base pointer */\r
+ #define SCT0 ((SCT_Type *)SCT0_BASE)\r
+ /** Array initializer of SCT peripheral base addresses */\r
+ #define SCT_BASE_ADDRS { SCT0_BASE }\r
+ /** Array initializer of SCT peripheral base pointers */\r
+ #define SCT_BASE_PTRS { SCT0 }\r
+#endif\r
+/** Interrupt vectors for the SCT peripheral type */\r
+#define SCT_IRQS { SCT0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SCT_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SDIF Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SDIF - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */\r
+ __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */\r
+ __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */\r
+ __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */\r
+ __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */\r
+ __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */\r
+ __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */\r
+ __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */\r
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */\r
+ __IO uint32_t CMD; /**< Command register, offset: 0x2C */\r
+ __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */\r
+ __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */\r
+ __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */\r
+ __IO uint32_t STATUS; /**< Status register, offset: 0x48 */\r
+ __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */\r
+ __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */\r
+ __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */\r
+ __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */\r
+ __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */\r
+ uint8_t RESERVED_2[16];\r
+ __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */\r
+ __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */\r
+ __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */\r
+ __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */\r
+ __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */\r
+ __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */\r
+ __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */\r
+ uint8_t RESERVED_4[100];\r
+ __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */\r
+ __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */\r
+ uint8_t RESERVED_5[248];\r
+ __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */\r
+} SDIF_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SDIF Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - Control register */\r
+/*! @{ */\r
+#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)\r
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)\r
+#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)\r
+#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)\r
+#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)\r
+#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)\r
+#define SDIF_CTRL_DMA_RESET_MASK (0x4U)\r
+#define SDIF_CTRL_DMA_RESET_SHIFT (2U)\r
+#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)\r
+#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)\r
+#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)\r
+#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)\r
+#define SDIF_CTRL_READ_WAIT_MASK (0x40U)\r
+#define SDIF_CTRL_READ_WAIT_SHIFT (6U)\r
+#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)\r
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)\r
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)\r
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)\r
+#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)\r
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)\r
+#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)\r
+#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)\r
+#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)\r
+#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)\r
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)\r
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)\r
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)\r
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)\r
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)\r
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)\r
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)\r
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)\r
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)\r
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWREN - Power Enable register */\r
+/*! @{ */\r
+#define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U)\r
+#define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U)\r
+#define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK)\r
+#define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U)\r
+#define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U)\r
+#define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKDIV - Clock Divider register */\r
+/*! @{ */\r
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)\r
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)\r
+#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKENA - Clock Enable register */\r
+/*! @{ */\r
+#define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U)\r
+#define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U)\r
+#define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK)\r
+#define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U)\r
+#define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U)\r
+#define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK)\r
+#define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U)\r
+#define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U)\r
+#define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK)\r
+#define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U)\r
+#define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U)\r
+#define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK)\r
+/*! @} */\r
+\r
+/*! @name TMOUT - Time-out register */\r
+/*! @{ */\r
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)\r
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)\r
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)\r
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)\r
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)\r
+#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTYPE - Card Type register */\r
+/*! @{ */\r
+#define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U)\r
+#define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U)\r
+#define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK)\r
+#define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U)\r
+#define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U)\r
+#define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK)\r
+#define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U)\r
+#define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U)\r
+#define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK)\r
+#define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U)\r
+#define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U)\r
+#define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK)\r
+/*! @} */\r
+\r
+/*! @name BLKSIZ - Block Size register */\r
+/*! @{ */\r
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)\r
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)\r
+#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)\r
+/*! @} */\r
+\r
+/*! @name BYTCNT - Byte Count register */\r
+/*! @{ */\r
+#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)\r
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)\r
+#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTMASK - Interrupt Mask register */\r
+/*! @{ */\r
+#define SDIF_INTMASK_CDET_MASK (0x1U)\r
+#define SDIF_INTMASK_CDET_SHIFT (0U)\r
+#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)\r
+#define SDIF_INTMASK_RE_MASK (0x2U)\r
+#define SDIF_INTMASK_RE_SHIFT (1U)\r
+#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)\r
+#define SDIF_INTMASK_CDONE_MASK (0x4U)\r
+#define SDIF_INTMASK_CDONE_SHIFT (2U)\r
+#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)\r
+#define SDIF_INTMASK_DTO_MASK (0x8U)\r
+#define SDIF_INTMASK_DTO_SHIFT (3U)\r
+#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)\r
+#define SDIF_INTMASK_TXDR_MASK (0x10U)\r
+#define SDIF_INTMASK_TXDR_SHIFT (4U)\r
+#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)\r
+#define SDIF_INTMASK_RXDR_MASK (0x20U)\r
+#define SDIF_INTMASK_RXDR_SHIFT (5U)\r
+#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)\r
+#define SDIF_INTMASK_RCRC_MASK (0x40U)\r
+#define SDIF_INTMASK_RCRC_SHIFT (6U)\r
+#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)\r
+#define SDIF_INTMASK_DCRC_MASK (0x80U)\r
+#define SDIF_INTMASK_DCRC_SHIFT (7U)\r
+#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)\r
+#define SDIF_INTMASK_RTO_MASK (0x100U)\r
+#define SDIF_INTMASK_RTO_SHIFT (8U)\r
+#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)\r
+#define SDIF_INTMASK_DRTO_MASK (0x200U)\r
+#define SDIF_INTMASK_DRTO_SHIFT (9U)\r
+#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)\r
+#define SDIF_INTMASK_HTO_MASK (0x400U)\r
+#define SDIF_INTMASK_HTO_SHIFT (10U)\r
+#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)\r
+#define SDIF_INTMASK_FRUN_MASK (0x800U)\r
+#define SDIF_INTMASK_FRUN_SHIFT (11U)\r
+#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)\r
+#define SDIF_INTMASK_HLE_MASK (0x1000U)\r
+#define SDIF_INTMASK_HLE_SHIFT (12U)\r
+#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)\r
+#define SDIF_INTMASK_SBE_MASK (0x2000U)\r
+#define SDIF_INTMASK_SBE_SHIFT (13U)\r
+#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)\r
+#define SDIF_INTMASK_ACD_MASK (0x4000U)\r
+#define SDIF_INTMASK_ACD_SHIFT (14U)\r
+#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)\r
+#define SDIF_INTMASK_EBE_MASK (0x8000U)\r
+#define SDIF_INTMASK_EBE_SHIFT (15U)\r
+#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)\r
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)\r
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)\r
+#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)\r
+/*! @} */\r
+\r
+/*! @name CMDARG - Command Argument register */\r
+/*! @{ */\r
+#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)\r
+#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)\r
+#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CMD - Command register */\r
+/*! @{ */\r
+#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)\r
+#define SDIF_CMD_CMD_INDEX_SHIFT (0U)\r
+#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)\r
+#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)\r
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)\r
+#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)\r
+#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)\r
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)\r
+#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)\r
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)\r
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)\r
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)\r
+#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)\r
+#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)\r
+#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)\r
+#define SDIF_CMD_READ_WRITE_MASK (0x400U)\r
+#define SDIF_CMD_READ_WRITE_SHIFT (10U)\r
+#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)\r
+#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)\r
+#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)\r
+#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)\r
+#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)\r
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)\r
+#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)\r
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)\r
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)\r
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)\r
+#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)\r
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)\r
+#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)\r
+#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)\r
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)\r
+#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)\r
+#define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U)\r
+#define SDIF_CMD_CARD_NUMBER_SHIFT (16U)\r
+/*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed\r
+ * 0b00000..Command will be execute on SDCARD 0\r
+ * 0b00001..Command will be execute on SDCARD 1\r
+ */\r
+#define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK)\r
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)\r
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)\r
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)\r
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)\r
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)\r
+#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)\r
+#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)\r
+#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)\r
+#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)\r
+#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)\r
+#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)\r
+#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)\r
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)\r
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)\r
+#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)\r
+#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)\r
+#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)\r
+#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)\r
+#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)\r
+#define SDIF_CMD_BOOT_MODE_SHIFT (27U)\r
+#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)\r
+#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)\r
+#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)\r
+#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)\r
+#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)\r
+#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)\r
+#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)\r
+#define SDIF_CMD_START_CMD_MASK (0x80000000U)\r
+#define SDIF_CMD_START_CMD_SHIFT (31U)\r
+#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)\r
+/*! @} */\r
+\r
+/*! @name RESP - Response register */\r
+/*! @{ */\r
+#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)\r
+#define SDIF_RESP_RESPONSE_SHIFT (0U)\r
+#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)\r
+/*! @} */\r
+\r
+/* The count of SDIF_RESP */\r
+#define SDIF_RESP_COUNT (4U)\r
+\r
+/*! @name MINTSTS - Masked Interrupt Status register */\r
+/*! @{ */\r
+#define SDIF_MINTSTS_CDET_MASK (0x1U)\r
+#define SDIF_MINTSTS_CDET_SHIFT (0U)\r
+#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)\r
+#define SDIF_MINTSTS_RE_MASK (0x2U)\r
+#define SDIF_MINTSTS_RE_SHIFT (1U)\r
+#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)\r
+#define SDIF_MINTSTS_CDONE_MASK (0x4U)\r
+#define SDIF_MINTSTS_CDONE_SHIFT (2U)\r
+#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)\r
+#define SDIF_MINTSTS_DTO_MASK (0x8U)\r
+#define SDIF_MINTSTS_DTO_SHIFT (3U)\r
+#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)\r
+#define SDIF_MINTSTS_TXDR_MASK (0x10U)\r
+#define SDIF_MINTSTS_TXDR_SHIFT (4U)\r
+#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)\r
+#define SDIF_MINTSTS_RXDR_MASK (0x20U)\r
+#define SDIF_MINTSTS_RXDR_SHIFT (5U)\r
+#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)\r
+#define SDIF_MINTSTS_RCRC_MASK (0x40U)\r
+#define SDIF_MINTSTS_RCRC_SHIFT (6U)\r
+#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)\r
+#define SDIF_MINTSTS_DCRC_MASK (0x80U)\r
+#define SDIF_MINTSTS_DCRC_SHIFT (7U)\r
+#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)\r
+#define SDIF_MINTSTS_RTO_MASK (0x100U)\r
+#define SDIF_MINTSTS_RTO_SHIFT (8U)\r
+#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)\r
+#define SDIF_MINTSTS_DRTO_MASK (0x200U)\r
+#define SDIF_MINTSTS_DRTO_SHIFT (9U)\r
+#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)\r
+#define SDIF_MINTSTS_HTO_MASK (0x400U)\r
+#define SDIF_MINTSTS_HTO_SHIFT (10U)\r
+#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)\r
+#define SDIF_MINTSTS_FRUN_MASK (0x800U)\r
+#define SDIF_MINTSTS_FRUN_SHIFT (11U)\r
+#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)\r
+#define SDIF_MINTSTS_HLE_MASK (0x1000U)\r
+#define SDIF_MINTSTS_HLE_SHIFT (12U)\r
+#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)\r
+#define SDIF_MINTSTS_SBE_MASK (0x2000U)\r
+#define SDIF_MINTSTS_SBE_SHIFT (13U)\r
+#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)\r
+#define SDIF_MINTSTS_ACD_MASK (0x4000U)\r
+#define SDIF_MINTSTS_ACD_SHIFT (14U)\r
+#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)\r
+#define SDIF_MINTSTS_EBE_MASK (0x8000U)\r
+#define SDIF_MINTSTS_EBE_SHIFT (15U)\r
+#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)\r
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)\r
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)\r
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)\r
+/*! @} */\r
+\r
+/*! @name RINTSTS - Raw Interrupt Status register */\r
+/*! @{ */\r
+#define SDIF_RINTSTS_CDET_MASK (0x1U)\r
+#define SDIF_RINTSTS_CDET_SHIFT (0U)\r
+#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)\r
+#define SDIF_RINTSTS_RE_MASK (0x2U)\r
+#define SDIF_RINTSTS_RE_SHIFT (1U)\r
+#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)\r
+#define SDIF_RINTSTS_CDONE_MASK (0x4U)\r
+#define SDIF_RINTSTS_CDONE_SHIFT (2U)\r
+#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)\r
+#define SDIF_RINTSTS_DTO_MASK (0x8U)\r
+#define SDIF_RINTSTS_DTO_SHIFT (3U)\r
+#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)\r
+#define SDIF_RINTSTS_TXDR_MASK (0x10U)\r
+#define SDIF_RINTSTS_TXDR_SHIFT (4U)\r
+#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)\r
+#define SDIF_RINTSTS_RXDR_MASK (0x20U)\r
+#define SDIF_RINTSTS_RXDR_SHIFT (5U)\r
+#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)\r
+#define SDIF_RINTSTS_RCRC_MASK (0x40U)\r
+#define SDIF_RINTSTS_RCRC_SHIFT (6U)\r
+#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)\r
+#define SDIF_RINTSTS_DCRC_MASK (0x80U)\r
+#define SDIF_RINTSTS_DCRC_SHIFT (7U)\r
+#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)\r
+#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)\r
+#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)\r
+#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)\r
+#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)\r
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)\r
+#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)\r
+#define SDIF_RINTSTS_HTO_MASK (0x400U)\r
+#define SDIF_RINTSTS_HTO_SHIFT (10U)\r
+#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)\r
+#define SDIF_RINTSTS_FRUN_MASK (0x800U)\r
+#define SDIF_RINTSTS_FRUN_SHIFT (11U)\r
+#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)\r
+#define SDIF_RINTSTS_HLE_MASK (0x1000U)\r
+#define SDIF_RINTSTS_HLE_SHIFT (12U)\r
+#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)\r
+#define SDIF_RINTSTS_SBE_MASK (0x2000U)\r
+#define SDIF_RINTSTS_SBE_SHIFT (13U)\r
+#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)\r
+#define SDIF_RINTSTS_ACD_MASK (0x4000U)\r
+#define SDIF_RINTSTS_ACD_SHIFT (14U)\r
+#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)\r
+#define SDIF_RINTSTS_EBE_MASK (0x8000U)\r
+#define SDIF_RINTSTS_EBE_SHIFT (15U)\r
+#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)\r
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)\r
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)\r
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - Status register */\r
+/*! @{ */\r
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)\r
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)\r
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)\r
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)\r
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)\r
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)\r
+#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)\r
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)\r
+#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)\r
+#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)\r
+#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)\r
+#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)\r
+#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)\r
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)\r
+#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)\r
+#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)\r
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)\r
+#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)\r
+#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)\r
+#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)\r
+#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)\r
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)\r
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)\r
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)\r
+#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)\r
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)\r
+#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)\r
+#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)\r
+#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)\r
+#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)\r
+#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)\r
+#define SDIF_STATUS_DMA_ACK_SHIFT (30U)\r
+#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)\r
+#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)\r
+#define SDIF_STATUS_DMA_REQ_SHIFT (31U)\r
+#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTH - FIFO Threshold Watermark register */\r
+/*! @{ */\r
+#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)\r
+#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)\r
+#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)\r
+#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)\r
+#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)\r
+#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)\r
+#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)\r
+#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)\r
+#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)\r
+/*! @} */\r
+\r
+/*! @name CDETECT - Card Detect register */\r
+/*! @{ */\r
+#define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U)\r
+#define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U)\r
+#define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK)\r
+#define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U)\r
+#define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U)\r
+#define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WRTPRT - Write Protect register */\r
+/*! @{ */\r
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)\r
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)\r
+#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */\r
+/*! @{ */\r
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)\r
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)\r
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */\r
+/*! @{ */\r
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)\r
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)\r
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBNCE - Debounce Count register */\r
+/*! @{ */\r
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)\r
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)\r
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name RST_N - Hardware Reset */\r
+/*! @{ */\r
+#define SDIF_RST_N_CARD_RESET_MASK (0x1U)\r
+#define SDIF_RST_N_CARD_RESET_SHIFT (0U)\r
+#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)\r
+/*! @} */\r
+\r
+/*! @name BMOD - Bus Mode register */\r
+/*! @{ */\r
+#define SDIF_BMOD_SWR_MASK (0x1U)\r
+#define SDIF_BMOD_SWR_SHIFT (0U)\r
+#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)\r
+#define SDIF_BMOD_FB_MASK (0x2U)\r
+#define SDIF_BMOD_FB_SHIFT (1U)\r
+#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)\r
+#define SDIF_BMOD_DSL_MASK (0x7CU)\r
+#define SDIF_BMOD_DSL_SHIFT (2U)\r
+#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)\r
+#define SDIF_BMOD_DE_MASK (0x80U)\r
+#define SDIF_BMOD_DE_SHIFT (7U)\r
+#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)\r
+#define SDIF_BMOD_PBL_MASK (0x700U)\r
+#define SDIF_BMOD_PBL_SHIFT (8U)\r
+#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLDMND - Poll Demand register */\r
+/*! @{ */\r
+#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)\r
+#define SDIF_PLDMND_PD_SHIFT (0U)\r
+#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)\r
+/*! @} */\r
+\r
+/*! @name DBADDR - Descriptor List Base Address register */\r
+/*! @{ */\r
+#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)\r
+#define SDIF_DBADDR_SDL_SHIFT (0U)\r
+#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDSTS - Internal DMAC Status register */\r
+/*! @{ */\r
+#define SDIF_IDSTS_TI_MASK (0x1U)\r
+#define SDIF_IDSTS_TI_SHIFT (0U)\r
+#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)\r
+#define SDIF_IDSTS_RI_MASK (0x2U)\r
+#define SDIF_IDSTS_RI_SHIFT (1U)\r
+#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)\r
+#define SDIF_IDSTS_FBE_MASK (0x4U)\r
+#define SDIF_IDSTS_FBE_SHIFT (2U)\r
+#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)\r
+#define SDIF_IDSTS_DU_MASK (0x10U)\r
+#define SDIF_IDSTS_DU_SHIFT (4U)\r
+#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)\r
+#define SDIF_IDSTS_CES_MASK (0x20U)\r
+#define SDIF_IDSTS_CES_SHIFT (5U)\r
+#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)\r
+#define SDIF_IDSTS_NIS_MASK (0x100U)\r
+#define SDIF_IDSTS_NIS_SHIFT (8U)\r
+#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)\r
+#define SDIF_IDSTS_AIS_MASK (0x200U)\r
+#define SDIF_IDSTS_AIS_SHIFT (9U)\r
+#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)\r
+#define SDIF_IDSTS_EB_MASK (0x1C00U)\r
+#define SDIF_IDSTS_EB_SHIFT (10U)\r
+#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)\r
+#define SDIF_IDSTS_FSM_MASK (0x1E000U)\r
+#define SDIF_IDSTS_FSM_SHIFT (13U)\r
+#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)\r
+/*! @} */\r
+\r
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */\r
+/*! @{ */\r
+#define SDIF_IDINTEN_TI_MASK (0x1U)\r
+#define SDIF_IDINTEN_TI_SHIFT (0U)\r
+#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)\r
+#define SDIF_IDINTEN_RI_MASK (0x2U)\r
+#define SDIF_IDINTEN_RI_SHIFT (1U)\r
+#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)\r
+#define SDIF_IDINTEN_FBE_MASK (0x4U)\r
+#define SDIF_IDINTEN_FBE_SHIFT (2U)\r
+#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)\r
+#define SDIF_IDINTEN_DU_MASK (0x10U)\r
+#define SDIF_IDINTEN_DU_SHIFT (4U)\r
+#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)\r
+#define SDIF_IDINTEN_CES_MASK (0x20U)\r
+#define SDIF_IDINTEN_CES_SHIFT (5U)\r
+#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)\r
+#define SDIF_IDINTEN_NIS_MASK (0x100U)\r
+#define SDIF_IDINTEN_NIS_SHIFT (8U)\r
+#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)\r
+#define SDIF_IDINTEN_AIS_MASK (0x200U)\r
+#define SDIF_IDINTEN_AIS_SHIFT (9U)\r
+#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)\r
+/*! @} */\r
+\r
+/*! @name DSCADDR - Current Host Descriptor Address register */\r
+/*! @{ */\r
+#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)\r
+#define SDIF_DSCADDR_HDA_SHIFT (0U)\r
+#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)\r
+/*! @} */\r
+\r
+/*! @name BUFADDR - Current Buffer Descriptor Address register */\r
+/*! @{ */\r
+#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)\r
+#define SDIF_BUFADDR_HBA_SHIFT (0U)\r
+#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)\r
+/*! @} */\r
+\r
+/*! @name CARDTHRCTL - Card Threshold Control */\r
+/*! @{ */\r
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)\r
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)\r
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)\r
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)\r
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)\r
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)\r
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)\r
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)\r
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)\r
+/*! @} */\r
+\r
+/*! @name BACKENDPWR - Power control */\r
+/*! @{ */\r
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)\r
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)\r
+#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFO - SDIF FIFO */\r
+/*! @{ */\r
+#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)\r
+#define SDIF_FIFO_DATA_SHIFT (0U)\r
+#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SDIF_FIFO */\r
+#define SDIF_FIFO_COUNT (64U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SDIF_Register_Masks */\r
+\r
+\r
+/* SDIF - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral SDIF base address */\r
+ #define SDIF_BASE (0x5009B000u)\r
+ /** Peripheral SDIF base address */\r
+ #define SDIF_BASE_NS (0x4009B000u)\r
+ /** Peripheral SDIF base pointer */\r
+ #define SDIF ((SDIF_Type *)SDIF_BASE)\r
+ /** Peripheral SDIF base pointer */\r
+ #define SDIF_NS ((SDIF_Type *)SDIF_BASE_NS)\r
+ /** Array initializer of SDIF peripheral base addresses */\r
+ #define SDIF_BASE_ADDRS { SDIF_BASE }\r
+ /** Array initializer of SDIF peripheral base pointers */\r
+ #define SDIF_BASE_PTRS { SDIF }\r
+ /** Array initializer of SDIF peripheral base addresses */\r
+ #define SDIF_BASE_ADDRS_NS { SDIF_BASE_NS }\r
+ /** Array initializer of SDIF peripheral base pointers */\r
+ #define SDIF_BASE_PTRS_NS { SDIF_NS }\r
+#else\r
+ /** Peripheral SDIF base address */\r
+ #define SDIF_BASE (0x4009B000u)\r
+ /** Peripheral SDIF base pointer */\r
+ #define SDIF ((SDIF_Type *)SDIF_BASE)\r
+ /** Array initializer of SDIF peripheral base addresses */\r
+ #define SDIF_BASE_ADDRS { SDIF_BASE }\r
+ /** Array initializer of SDIF peripheral base pointers */\r
+ #define SDIF_BASE_PTRS { SDIF }\r
+#endif\r
+/** Interrupt vectors for the SDIF peripheral type */\r
+#define SDIF_IRQS { SDIO_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SDIF_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SPI Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SPI - Register Layout Typedef */\r
+typedef struct {\r
+ uint8_t RESERVED_0[1024];\r
+ __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */\r
+ __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */\r
+ __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */\r
+ __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */\r
+ __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */\r
+ __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */\r
+ uint8_t RESERVED_2[2516];\r
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */\r
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */\r
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */\r
+ uint8_t RESERVED_3[4];\r
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */\r
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */\r
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */\r
+ uint8_t RESERVED_4[4];\r
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */\r
+ uint8_t RESERVED_5[12];\r
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */\r
+ uint8_t RESERVED_6[12];\r
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */\r
+ uint8_t RESERVED_7[440];\r
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */\r
+} SPI_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SPI Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SPI_Register_Masks SPI Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG - SPI Configuration register */\r
+/*! @{ */\r
+#define SPI_CFG_ENABLE_MASK (0x1U)\r
+#define SPI_CFG_ENABLE_SHIFT (0U)\r
+/*! ENABLE - SPI enable.\r
+ * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset.\r
+ * 0b1..Enabled. The SPI is enabled for operation.\r
+ */\r
+#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)\r
+#define SPI_CFG_MASTER_MASK (0x4U)\r
+#define SPI_CFG_MASTER_SHIFT (2U)\r
+/*! MASTER - Master mode select.\r
+ * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output.\r
+ * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input.\r
+ */\r
+#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)\r
+#define SPI_CFG_LSBF_MASK (0x8U)\r
+#define SPI_CFG_LSBF_SHIFT (3U)\r
+/*! LSBF - LSB First mode enable.\r
+ * 0b0..Standard. Data is transmitted and received in standard MSB first order.\r
+ * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first).\r
+ */\r
+#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)\r
+#define SPI_CFG_CPHA_MASK (0x10U)\r
+#define SPI_CFG_CPHA_SHIFT (4U)\r
+/*! CPHA - Clock Phase select.\r
+ * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge.\r
+ * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge.\r
+ */\r
+#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)\r
+#define SPI_CFG_CPOL_MASK (0x20U)\r
+#define SPI_CFG_CPOL_SHIFT (5U)\r
+/*! CPOL - Clock Polarity select.\r
+ * 0b0..Low. The rest state of the clock (between transfers) is low.\r
+ * 0b1..High. The rest state of the clock (between transfers) is high.\r
+ */\r
+#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)\r
+#define SPI_CFG_LOOP_MASK (0x80U)\r
+#define SPI_CFG_LOOP_SHIFT (7U)\r
+/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing.\r
+ * 0b0..Disabled.\r
+ * 0b1..Enabled.\r
+ */\r
+#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)\r
+#define SPI_CFG_SPOL0_MASK (0x100U)\r
+#define SPI_CFG_SPOL0_SHIFT (8U)\r
+/*! SPOL0 - SSEL0 Polarity select.\r
+ * 0b0..Low. The SSEL0 pin is active low.\r
+ * 0b1..High. The SSEL0 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)\r
+#define SPI_CFG_SPOL1_MASK (0x200U)\r
+#define SPI_CFG_SPOL1_SHIFT (9U)\r
+/*! SPOL1 - SSEL1 Polarity select.\r
+ * 0b0..Low. The SSEL1 pin is active low.\r
+ * 0b1..High. The SSEL1 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)\r
+#define SPI_CFG_SPOL2_MASK (0x400U)\r
+#define SPI_CFG_SPOL2_SHIFT (10U)\r
+/*! SPOL2 - SSEL2 Polarity select.\r
+ * 0b0..Low. The SSEL2 pin is active low.\r
+ * 0b1..High. The SSEL2 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)\r
+#define SPI_CFG_SPOL3_MASK (0x800U)\r
+#define SPI_CFG_SPOL3_SHIFT (11U)\r
+/*! SPOL3 - SSEL3 Polarity select.\r
+ * 0b0..Low. The SSEL3 pin is active low.\r
+ * 0b1..High. The SSEL3 pin is active high.\r
+ */\r
+#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)\r
+/*! @} */\r
+\r
+/*! @name DLY - SPI Delay register */\r
+/*! @{ */\r
+#define SPI_DLY_PRE_DELAY_MASK (0xFU)\r
+#define SPI_DLY_PRE_DELAY_SHIFT (0U)\r
+#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)\r
+#define SPI_DLY_POST_DELAY_MASK (0xF0U)\r
+#define SPI_DLY_POST_DELAY_SHIFT (4U)\r
+#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)\r
+#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)\r
+#define SPI_DLY_FRAME_DELAY_SHIFT (8U)\r
+#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)\r
+#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)\r
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)\r
+#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */\r
+/*! @{ */\r
+#define SPI_STAT_SSA_MASK (0x10U)\r
+#define SPI_STAT_SSA_SHIFT (4U)\r
+#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)\r
+#define SPI_STAT_SSD_MASK (0x20U)\r
+#define SPI_STAT_SSD_SHIFT (5U)\r
+#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)\r
+#define SPI_STAT_STALLED_MASK (0x40U)\r
+#define SPI_STAT_STALLED_SHIFT (6U)\r
+#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)\r
+#define SPI_STAT_ENDTRANSFER_MASK (0x80U)\r
+#define SPI_STAT_ENDTRANSFER_SHIFT (7U)\r
+#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)\r
+#define SPI_STAT_MSTIDLE_MASK (0x100U)\r
+#define SPI_STAT_MSTIDLE_SHIFT (8U)\r
+#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */\r
+/*! @{ */\r
+#define SPI_INTENSET_SSAEN_MASK (0x10U)\r
+#define SPI_INTENSET_SSAEN_SHIFT (4U)\r
+/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.\r
+ * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.\r
+ * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.\r
+ */\r
+#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)\r
+#define SPI_INTENSET_SSDEN_MASK (0x20U)\r
+#define SPI_INTENSET_SSDEN_SHIFT (5U)\r
+/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.\r
+ * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.\r
+ * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.\r
+ */\r
+#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)\r
+#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)\r
+#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)\r
+/*! MSTIDLEEN - Master idle interrupt enable.\r
+ * 0b0..No interrupt will be generated when the SPI master function is idle.\r
+ * 0b1..An interrupt will be generated when the SPI master function is fully idle.\r
+ */\r
+#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */\r
+/*! @{ */\r
+#define SPI_INTENCLR_SSAEN_MASK (0x10U)\r
+#define SPI_INTENCLR_SSAEN_SHIFT (4U)\r
+#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)\r
+#define SPI_INTENCLR_SSDEN_MASK (0x20U)\r
+#define SPI_INTENCLR_SSDEN_SHIFT (5U)\r
+#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)\r
+#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)\r
+#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)\r
+#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DIV - SPI clock Divider */\r
+/*! @{ */\r
+#define SPI_DIV_DIVVAL_MASK (0xFFFFU)\r
+#define SPI_DIV_DIVVAL_SHIFT (0U)\r
+#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - SPI Interrupt Status */\r
+/*! @{ */\r
+#define SPI_INTSTAT_SSA_MASK (0x10U)\r
+#define SPI_INTSTAT_SSA_SHIFT (4U)\r
+#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)\r
+#define SPI_INTSTAT_SSD_MASK (0x20U)\r
+#define SPI_INTSTAT_SSD_SHIFT (5U)\r
+#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)\r
+#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)\r
+#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)\r
+#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOCFG - FIFO configuration and enable register. */\r
+/*! @{ */\r
+#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)\r
+#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)\r
+/*! ENABLETX - Enable the transmit FIFO.\r
+ * 0b0..The transmit FIFO is not enabled.\r
+ * 0b1..The transmit FIFO is enabled.\r
+ */\r
+#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)\r
+#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)\r
+#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)\r
+/*! ENABLERX - Enable the receive FIFO.\r
+ * 0b0..The receive FIFO is not enabled.\r
+ * 0b1..The receive FIFO is enabled.\r
+ */\r
+#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)\r
+#define SPI_FIFOCFG_SIZE_MASK (0x30U)\r
+#define SPI_FIFOCFG_SIZE_SHIFT (4U)\r
+#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)\r
+#define SPI_FIFOCFG_DMATX_MASK (0x1000U)\r
+#define SPI_FIFOCFG_DMATX_SHIFT (12U)\r
+/*! DMATX - DMA configuration for transmit.\r
+ * 0b0..DMA is not used for the transmit function.\r
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)\r
+#define SPI_FIFOCFG_DMARX_MASK (0x2000U)\r
+#define SPI_FIFOCFG_DMARX_SHIFT (13U)\r
+/*! DMARX - DMA configuration for receive.\r
+ * 0b0..DMA is not used for the receive function.\r
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)\r
+#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)\r
+#define SPI_FIFOCFG_WAKETX_SHIFT (14U)\r
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.\r
+ */\r
+#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)\r
+#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)\r
+#define SPI_FIFOCFG_WAKERX_SHIFT (15U)\r
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.\r
+ */\r
+#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)\r
+#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)\r
+#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)\r
+#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)\r
+#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)\r
+#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)\r
+#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)\r
+#define SPI_FIFOCFG_POPDBG_MASK (0x40000U)\r
+#define SPI_FIFOCFG_POPDBG_SHIFT (18U)\r
+/*! POPDBG - Pop FIFO for debug reads.\r
+ * 0b0..Debug reads of the FIFO do not pop the FIFO.\r
+ * 0b1..A debug read will cause the FIFO to pop.\r
+ */\r
+#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOSTAT - FIFO status register. */\r
+/*! @{ */\r
+#define SPI_FIFOSTAT_TXERR_MASK (0x1U)\r
+#define SPI_FIFOSTAT_TXERR_SHIFT (0U)\r
+#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)\r
+#define SPI_FIFOSTAT_RXERR_MASK (0x2U)\r
+#define SPI_FIFOSTAT_RXERR_SHIFT (1U)\r
+#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)\r
+#define SPI_FIFOSTAT_PERINT_MASK (0x8U)\r
+#define SPI_FIFOSTAT_PERINT_SHIFT (3U)\r
+#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)\r
+#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)\r
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)\r
+#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)\r
+#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)\r
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)\r
+#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)\r
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)\r
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)\r
+#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)\r
+#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)\r
+#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)\r
+#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)\r
+#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)\r
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)\r
+#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)\r
+#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)\r
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)\r
+#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */\r
+/*! @{ */\r
+#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)\r
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)\r
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\r
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.\r
+ */\r
+#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)\r
+#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)\r
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)\r
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\r
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.\r
+ */\r
+#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)\r
+#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)\r
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)\r
+#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)\r
+#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)\r
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)\r
+#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */\r
+/*! @{ */\r
+#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)\r
+#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)\r
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a transmit error.\r
+ * 0b1..An interrupt will be generated when a transmit error occurs.\r
+ */\r
+#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)\r
+#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)\r
+#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)\r
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a receive error.\r
+ * 0b1..An interrupt will be generated when a receive error occurs.\r
+ */\r
+#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)\r
+#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)\r
+#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the TX FIFO level.\r
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.\r
+ */\r
+#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)\r
+#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)\r
+#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the RX FIFO level.\r
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.\r
+ */\r
+#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */\r
+/*! @{ */\r
+#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)\r
+#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)\r
+#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)\r
+#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)\r
+#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)\r
+#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)\r
+#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)\r
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)\r
+#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)\r
+#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)\r
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)\r
+#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */\r
+/*! @{ */\r
+#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)\r
+#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)\r
+#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)\r
+#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)\r
+#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)\r
+#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)\r
+#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)\r
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)\r
+#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)\r
+#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)\r
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)\r
+#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)\r
+#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)\r
+#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)\r
+#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR - FIFO write data. */\r
+/*! @{ */\r
+#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)\r
+#define SPI_FIFOWR_TXDATA_SHIFT (0U)\r
+#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)\r
+#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)\r
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)\r
+/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL0 asserted.\r
+ * 0b1..SSEL0 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)\r
+#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)\r
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)\r
+/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL1 asserted.\r
+ * 0b1..SSEL1 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)\r
+#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)\r
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)\r
+/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL2 asserted.\r
+ * 0b1..SSEL2 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)\r
+#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)\r
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)\r
+/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.\r
+ * 0b0..SSEL3 asserted.\r
+ * 0b1..SSEL3 not asserted.\r
+ */\r
+#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)\r
+#define SPI_FIFOWR_EOT_MASK (0x100000U)\r
+#define SPI_FIFOWR_EOT_SHIFT (20U)\r
+/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register.\r
+ * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data.\r
+ * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data.\r
+ */\r
+#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)\r
+#define SPI_FIFOWR_EOF_MASK (0x200000U)\r
+#define SPI_FIFOWR_EOF_SHIFT (21U)\r
+/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits.\r
+ * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame.\r
+ * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted.\r
+ */\r
+#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)\r
+#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)\r
+#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)\r
+/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA.\r
+ * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received.\r
+ * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated.\r
+ */\r
+#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)\r
+#define SPI_FIFOWR_LEN_MASK (0xF000000U)\r
+#define SPI_FIFOWR_LEN_SHIFT (24U)\r
+#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD - FIFO read data. */\r
+/*! @{ */\r
+#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)\r
+#define SPI_FIFORD_RXDATA_SHIFT (0U)\r
+#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)\r
+#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)\r
+#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)\r
+#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)\r
+#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)\r
+#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)\r
+#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)\r
+#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)\r
+#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)\r
+#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)\r
+#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)\r
+#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)\r
+#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)\r
+#define SPI_FIFORD_SOT_MASK (0x100000U)\r
+#define SPI_FIFORD_SOT_SHIFT (20U)\r
+#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */\r
+/*! @{ */\r
+#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)\r
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)\r
+#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)\r
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)\r
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)\r
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)\r
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)\r
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)\r
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)\r
+#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)\r
+#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)\r
+#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Peripheral identification register. */\r
+/*! @{ */\r
+#define SPI_ID_APERTURE_MASK (0xFFU)\r
+#define SPI_ID_APERTURE_SHIFT (0U)\r
+#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)\r
+#define SPI_ID_MINOR_REV_MASK (0xF00U)\r
+#define SPI_ID_MINOR_REV_SHIFT (8U)\r
+#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)\r
+#define SPI_ID_MAJOR_REV_MASK (0xF000U)\r
+#define SPI_ID_MAJOR_REV_SHIFT (12U)\r
+#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)\r
+#define SPI_ID_ID_MASK (0xFFFF0000U)\r
+#define SPI_ID_ID_SHIFT (16U)\r
+#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SPI_Register_Masks */\r
+\r
+\r
+/* SPI - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral SPI0 base address */\r
+ #define SPI0_BASE (0x50086000u)\r
+ /** Peripheral SPI0 base address */\r
+ #define SPI0_BASE_NS (0x40086000u)\r
+ /** Peripheral SPI0 base pointer */\r
+ #define SPI0 ((SPI_Type *)SPI0_BASE)\r
+ /** Peripheral SPI0 base pointer */\r
+ #define SPI0_NS ((SPI_Type *)SPI0_BASE_NS)\r
+ /** Peripheral SPI1 base address */\r
+ #define SPI1_BASE (0x50087000u)\r
+ /** Peripheral SPI1 base address */\r
+ #define SPI1_BASE_NS (0x40087000u)\r
+ /** Peripheral SPI1 base pointer */\r
+ #define SPI1 ((SPI_Type *)SPI1_BASE)\r
+ /** Peripheral SPI1 base pointer */\r
+ #define SPI1_NS ((SPI_Type *)SPI1_BASE_NS)\r
+ /** Peripheral SPI2 base address */\r
+ #define SPI2_BASE (0x50088000u)\r
+ /** Peripheral SPI2 base address */\r
+ #define SPI2_BASE_NS (0x40088000u)\r
+ /** Peripheral SPI2 base pointer */\r
+ #define SPI2 ((SPI_Type *)SPI2_BASE)\r
+ /** Peripheral SPI2 base pointer */\r
+ #define SPI2_NS ((SPI_Type *)SPI2_BASE_NS)\r
+ /** Peripheral SPI3 base address */\r
+ #define SPI3_BASE (0x50089000u)\r
+ /** Peripheral SPI3 base address */\r
+ #define SPI3_BASE_NS (0x40089000u)\r
+ /** Peripheral SPI3 base pointer */\r
+ #define SPI3 ((SPI_Type *)SPI3_BASE)\r
+ /** Peripheral SPI3 base pointer */\r
+ #define SPI3_NS ((SPI_Type *)SPI3_BASE_NS)\r
+ /** Peripheral SPI4 base address */\r
+ #define SPI4_BASE (0x5008A000u)\r
+ /** Peripheral SPI4 base address */\r
+ #define SPI4_BASE_NS (0x4008A000u)\r
+ /** Peripheral SPI4 base pointer */\r
+ #define SPI4 ((SPI_Type *)SPI4_BASE)\r
+ /** Peripheral SPI4 base pointer */\r
+ #define SPI4_NS ((SPI_Type *)SPI4_BASE_NS)\r
+ /** Peripheral SPI5 base address */\r
+ #define SPI5_BASE (0x50096000u)\r
+ /** Peripheral SPI5 base address */\r
+ #define SPI5_BASE_NS (0x40096000u)\r
+ /** Peripheral SPI5 base pointer */\r
+ #define SPI5 ((SPI_Type *)SPI5_BASE)\r
+ /** Peripheral SPI5 base pointer */\r
+ #define SPI5_NS ((SPI_Type *)SPI5_BASE_NS)\r
+ /** Peripheral SPI6 base address */\r
+ #define SPI6_BASE (0x50097000u)\r
+ /** Peripheral SPI6 base address */\r
+ #define SPI6_BASE_NS (0x40097000u)\r
+ /** Peripheral SPI6 base pointer */\r
+ #define SPI6 ((SPI_Type *)SPI6_BASE)\r
+ /** Peripheral SPI6 base pointer */\r
+ #define SPI6_NS ((SPI_Type *)SPI6_BASE_NS)\r
+ /** Peripheral SPI7 base address */\r
+ #define SPI7_BASE (0x50098000u)\r
+ /** Peripheral SPI7 base address */\r
+ #define SPI7_BASE_NS (0x40098000u)\r
+ /** Peripheral SPI7 base pointer */\r
+ #define SPI7 ((SPI_Type *)SPI7_BASE)\r
+ /** Peripheral SPI7 base pointer */\r
+ #define SPI7_NS ((SPI_Type *)SPI7_BASE_NS)\r
+ /** Peripheral SPI8 base address */\r
+ #define SPI8_BASE (0x5009F000u)\r
+ /** Peripheral SPI8 base address */\r
+ #define SPI8_BASE_NS (0x4009F000u)\r
+ /** Peripheral SPI8 base pointer */\r
+ #define SPI8 ((SPI_Type *)SPI8_BASE)\r
+ /** Peripheral SPI8 base pointer */\r
+ #define SPI8_NS ((SPI_Type *)SPI8_BASE_NS)\r
+ /** Array initializer of SPI peripheral base addresses */\r
+ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }\r
+ /** Array initializer of SPI peripheral base pointers */\r
+ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }\r
+ /** Array initializer of SPI peripheral base addresses */\r
+ #define SPI_BASE_ADDRS_NS { SPI0_BASE_NS, SPI1_BASE_NS, SPI2_BASE_NS, SPI3_BASE_NS, SPI4_BASE_NS, SPI5_BASE_NS, SPI6_BASE_NS, SPI7_BASE_NS, SPI8_BASE_NS }\r
+ /** Array initializer of SPI peripheral base pointers */\r
+ #define SPI_BASE_PTRS_NS { SPI0_NS, SPI1_NS, SPI2_NS, SPI3_NS, SPI4_NS, SPI5_NS, SPI6_NS, SPI7_NS, SPI8_NS }\r
+#else\r
+ /** Peripheral SPI0 base address */\r
+ #define SPI0_BASE (0x40086000u)\r
+ /** Peripheral SPI0 base pointer */\r
+ #define SPI0 ((SPI_Type *)SPI0_BASE)\r
+ /** Peripheral SPI1 base address */\r
+ #define SPI1_BASE (0x40087000u)\r
+ /** Peripheral SPI1 base pointer */\r
+ #define SPI1 ((SPI_Type *)SPI1_BASE)\r
+ /** Peripheral SPI2 base address */\r
+ #define SPI2_BASE (0x40088000u)\r
+ /** Peripheral SPI2 base pointer */\r
+ #define SPI2 ((SPI_Type *)SPI2_BASE)\r
+ /** Peripheral SPI3 base address */\r
+ #define SPI3_BASE (0x40089000u)\r
+ /** Peripheral SPI3 base pointer */\r
+ #define SPI3 ((SPI_Type *)SPI3_BASE)\r
+ /** Peripheral SPI4 base address */\r
+ #define SPI4_BASE (0x4008A000u)\r
+ /** Peripheral SPI4 base pointer */\r
+ #define SPI4 ((SPI_Type *)SPI4_BASE)\r
+ /** Peripheral SPI5 base address */\r
+ #define SPI5_BASE (0x40096000u)\r
+ /** Peripheral SPI5 base pointer */\r
+ #define SPI5 ((SPI_Type *)SPI5_BASE)\r
+ /** Peripheral SPI6 base address */\r
+ #define SPI6_BASE (0x40097000u)\r
+ /** Peripheral SPI6 base pointer */\r
+ #define SPI6 ((SPI_Type *)SPI6_BASE)\r
+ /** Peripheral SPI7 base address */\r
+ #define SPI7_BASE (0x40098000u)\r
+ /** Peripheral SPI7 base pointer */\r
+ #define SPI7 ((SPI_Type *)SPI7_BASE)\r
+ /** Peripheral SPI8 base address */\r
+ #define SPI8_BASE (0x4009F000u)\r
+ /** Peripheral SPI8 base pointer */\r
+ #define SPI8 ((SPI_Type *)SPI8_BASE)\r
+ /** Array initializer of SPI peripheral base addresses */\r
+ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE }\r
+ /** Array initializer of SPI peripheral base pointers */\r
+ #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8 }\r
+#endif\r
+/** Interrupt vectors for the SPI peripheral type */\r
+#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, LSPI_HS_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SPI_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SYSCON Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SYSCON - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t MEMORYREMAP; /**< Memory Remap control register, offset: 0x0 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t AHBMATPRIO; /**< AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest, offset: 0x10 */\r
+ uint8_t RESERVED_1[36];\r
+ __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */\r
+ __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */\r
+ __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */\r
+ uint8_t RESERVED_3[180];\r
+ union { /* offset: 0x100 */\r
+ struct { /* offset: 0x100 */\r
+ __IO uint32_t PRESETCTRL0; /**< Peripheral reset control 0, offset: 0x100 */\r
+ __IO uint32_t PRESETCTRL1; /**< Peripheral reset control 1, offset: 0x104 */\r
+ __IO uint32_t PRESETCTRL2; /**< Peripheral reset control 2, offset: 0x108 */\r
+ } PRESETCTRL;\r
+ __IO uint32_t PRESETCTRLX[3]; /**< Peripheral reset control register, array offset: 0x100, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_4[20];\r
+ __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */\r
+ uint8_t RESERVED_5[20];\r
+ __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */\r
+ uint8_t RESERVED_6[20];\r
+ __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */\r
+ uint8_t RESERVED_7[156];\r
+ union { /* offset: 0x200 */\r
+ struct { /* offset: 0x200 */\r
+ __IO uint32_t AHBCLKCTRL0; /**< AHB Clock control 0, offset: 0x200 */\r
+ __IO uint32_t AHBCLKCTRL1; /**< AHB Clock control 1, offset: 0x204 */\r
+ __IO uint32_t AHBCLKCTRL2; /**< AHB Clock control 2, offset: 0x208 */\r
+ } AHBCLKCTRL;\r
+ __IO uint32_t AHBCLKCTRLX[3]; /**< Peripheral reset control register, array offset: 0x200, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_8[20];\r
+ __IO uint32_t AHBCLKCTRLSET[3]; /**< Peripheral reset control register, array offset: 0x220, array step: 0x4 */\r
+ uint8_t RESERVED_9[20];\r
+ __IO uint32_t AHBCLKCTRLCLR[3]; /**< Peripheral reset control register, array offset: 0x240, array step: 0x4 */\r
+ uint8_t RESERVED_10[20];\r
+ union { /* offset: 0x260 */\r
+ struct { /* offset: 0x260 */\r
+ __IO uint32_t SYSTICKCLKSEL0; /**< System Tick Timer for CPU0 source select, offset: 0x260 */\r
+ __IO uint32_t SYSTICKCLKSEL1; /**< System Tick Timer for CPU1 source select, offset: 0x264 */\r
+ } SYSTICKCLKSEL;\r
+ __IO uint32_t SYSTICKCLKSELX[2]; /**< Peripheral reset control register, array offset: 0x260, array step: 0x4 */\r
+ };\r
+ __IO uint32_t TRACECLKSEL; /**< Trace clock source select, offset: 0x268 */\r
+ union { /* offset: 0x26C */\r
+ struct { /* offset: 0x26C */\r
+ __IO uint32_t CTIMERCLKSEL0; /**< CTimer 0 clock source select, offset: 0x26C */\r
+ __IO uint32_t CTIMERCLKSEL1; /**< CTimer 1 clock source select, offset: 0x270 */\r
+ __IO uint32_t CTIMERCLKSEL2; /**< CTimer 2 clock source select, offset: 0x274 */\r
+ __IO uint32_t CTIMERCLKSEL3; /**< CTimer 3 clock source select, offset: 0x278 */\r
+ __IO uint32_t CTIMERCLKSEL4; /**< CTimer 4 clock source select, offset: 0x27C */\r
+ } CTIMERCLKSEL;\r
+ __IO uint32_t CTIMERCLKSELX[5]; /**< Peripheral reset control register, array offset: 0x26C, array step: 0x4 */\r
+ };\r
+ __IO uint32_t MAINCLKSELA; /**< Main clock A source select, offset: 0x280 */\r
+ __IO uint32_t MAINCLKSELB; /**< Main clock source select, offset: 0x284 */\r
+ __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select, offset: 0x288 */\r
+ uint8_t RESERVED_11[4];\r
+ __IO uint32_t PLL0CLKSEL; /**< PLL0 clock source select, offset: 0x290 */\r
+ __IO uint32_t PLL1CLKSEL; /**< PLL1 clock source select, offset: 0x294 */\r
+ uint8_t RESERVED_12[12];\r
+ __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */\r
+ __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */\r
+ __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */\r
+ union { /* offset: 0x2B0 */\r
+ struct { /* offset: 0x2B0 */\r
+ __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */\r
+ __IO uint32_t FCCLKSEL1; /**< Flexcomm Interface 1 clock source select for Fractional Rate Divider, offset: 0x2B4 */\r
+ __IO uint32_t FCCLKSEL2; /**< Flexcomm Interface 2 clock source select for Fractional Rate Divider, offset: 0x2B8 */\r
+ __IO uint32_t FCCLKSEL3; /**< Flexcomm Interface 3 clock source select for Fractional Rate Divider, offset: 0x2BC */\r
+ __IO uint32_t FCCLKSEL4; /**< Flexcomm Interface 4 clock source select for Fractional Rate Divider, offset: 0x2C0 */\r
+ __IO uint32_t FCCLKSEL5; /**< Flexcomm Interface 5 clock source select for Fractional Rate Divider, offset: 0x2C4 */\r
+ __IO uint32_t FCCLKSEL6; /**< Flexcomm Interface 6 clock source select for Fractional Rate Divider, offset: 0x2C8 */\r
+ __IO uint32_t FCCLKSEL7; /**< Flexcomm Interface 7 clock source select for Fractional Rate Divider, offset: 0x2CC */\r
+ } FCCLKSEL;\r
+ __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */\r
+ };\r
+ __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */\r
+ uint8_t RESERVED_13[12];\r
+ __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */\r
+ uint8_t RESERVED_14[12];\r
+ __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */\r
+ uint8_t RESERVED_15[4];\r
+ __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */\r
+ uint8_t RESERVED_16[4];\r
+ __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */\r
+ __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */\r
+ __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */\r
+ uint8_t RESERVED_17[20];\r
+ union { /* offset: 0x320 */\r
+ struct { /* offset: 0x320 */\r
+ __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */\r
+ __IO uint32_t FLEXFRG1CTRL; /**< Fractional rate divider for flexcomm 1, offset: 0x324 */\r
+ __IO uint32_t FLEXFRG2CTRL; /**< Fractional rate divider for flexcomm 2, offset: 0x328 */\r
+ __IO uint32_t FLEXFRG3CTRL; /**< Fractional rate divider for flexcomm 3, offset: 0x32C */\r
+ __IO uint32_t FLEXFRG4CTRL; /**< Fractional rate divider for flexcomm 4, offset: 0x330 */\r
+ __IO uint32_t FLEXFRG5CTRL; /**< Fractional rate divider for flexcomm 5, offset: 0x334 */\r
+ __IO uint32_t FLEXFRG6CTRL; /**< Fractional rate divider for flexcomm 6, offset: 0x338 */\r
+ __IO uint32_t FLEXFRG7CTRL; /**< Fractional rate divider for flexcomm 7, offset: 0x33C */\r
+ } FLEXFRGCTRL;\r
+ __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */\r
+ };\r
+ uint8_t RESERVED_18[64];\r
+ __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */\r
+ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */\r
+ __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */\r
+ __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */\r
+ uint8_t RESERVED_19[4];\r
+ __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */\r
+ __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */\r
+ uint8_t RESERVED_20[16];\r
+ __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */\r
+ uint8_t RESERVED_21[4];\r
+ __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */\r
+ uint8_t RESERVED_22[4];\r
+ __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */\r
+ uint8_t RESERVED_23[4];\r
+ __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */\r
+ uint8_t RESERVED_24[52];\r
+ __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */\r
+ __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */\r
+ uint8_t RESERVED_25[8];\r
+ __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */\r
+ __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */\r
+ uint8_t RESERVED_26[8];\r
+ __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */\r
+ __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */\r
+ __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */\r
+ __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */\r
+ uint8_t RESERVED_27[36];\r
+ __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */\r
+ uint8_t RESERVED_28[12];\r
+ __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */\r
+ uint8_t RESERVED_29[252];\r
+ __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */\r
+ __I uint32_t PLL1STAT; /**< PLL1 550m status, offset: 0x564 */\r
+ __IO uint32_t PLL1NDEC; /**< PLL1 550m N divider, offset: 0x568 */\r
+ __IO uint32_t PLL1MDEC; /**< PLL1 550m M divider, offset: 0x56C */\r
+ __IO uint32_t PLL1PDEC; /**< PLL1 550m P divider, offset: 0x570 */\r
+ uint8_t RESERVED_30[12];\r
+ __IO uint32_t PLL0CTRL; /**< PLL0 550m control, offset: 0x580 */\r
+ __I uint32_t PLL0STAT; /**< PLL0 550m status, offset: 0x584 */\r
+ __IO uint32_t PLL0NDEC; /**< PLL0 550m N divider, offset: 0x588 */\r
+ __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */\r
+ __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */\r
+ __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */\r
+ uint8_t RESERVED_31[52];\r
+ __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */\r
+ uint8_t RESERVED_32[176];\r
+ __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */\r
+ uint8_t RESERVED_33[24];\r
+ __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */\r
+ uint8_t RESERVED_34[24];\r
+ __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */\r
+ uint8_t RESERVED_35[184];\r
+ __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */\r
+ uint8_t RESERVED_36[124];\r
+ __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */\r
+ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */\r
+ __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */\r
+ __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */\r
+ uint8_t RESERVED_37[240];\r
+ __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */\r
+ __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */\r
+ __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */\r
+ __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */\r
+ __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */\r
+ __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */\r
+ __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */\r
+ __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */\r
+ uint8_t RESERVED_38[248];\r
+ __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */\r
+ uint8_t RESERVED_39[244];\r
+ __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */\r
+ __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */\r
+ uint8_t RESERVED_40[748];\r
+ __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */\r
+ __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */\r
+ uint8_t RESERVED_41[404];\r
+ __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */\r
+ __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */\r
+ __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */\r
+ uint8_t RESERVED_42[4];\r
+ __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */\r
+ __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */\r
+ __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */\r
+ __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */\r
+ __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */\r
+ uint8_t RESERVED_43[16];\r
+ __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */\r
+ uint8_t RESERVED_44[20];\r
+ __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */\r
+ uint8_t RESERVED_45[8];\r
+ __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */\r
+ __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */\r
+} SYSCON_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SYSCON Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MEMORYREMAP - Memory Remap control register */\r
+/*! @{ */\r
+#define SYSCON_MEMORYREMAP_MAP_MASK (0x3U)\r
+#define SYSCON_MEMORYREMAP_MAP_SHIFT (0U)\r
+/*! MAP - Select the location of the vector table :.\r
+ * 0b00..Vector Table in ROM.\r
+ * 0b01..Vector Table in RAM.\r
+ * 0b10..Vector Table in Flash.\r
+ * 0b11..Vector Table in Flash.\r
+ */\r
+#define SYSCON_MEMORYREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MEMORYREMAP_MAP_SHIFT)) & SYSCON_MEMORYREMAP_MAP_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */\r
+/*! @{ */\r
+#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U)\r
+#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U)\r
+#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU)\r
+#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U)\r
+#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U)\r
+#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U)\r
+#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U)\r
+#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U)\r
+#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U)\r
+#define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U)\r
+#define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U)\r
+#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U)\r
+#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U)\r
+#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U)\r
+#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U)\r
+#define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U)\r
+#define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U)\r
+#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U)\r
+#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U)\r
+#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U)\r
+#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK)\r
+#define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U)\r
+#define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */\r
+/*! @{ */\r
+#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU)\r
+#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U)\r
+#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK)\r
+#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U)\r
+#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U)\r
+#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK)\r
+#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U)\r
+#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U)\r
+#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */\r
+/*! @{ */\r
+#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU)\r
+#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U)\r
+#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK)\r
+#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U)\r
+#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U)\r
+#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK)\r
+#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U)\r
+#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U)\r
+#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPU1TCKCAL - System tick calibration for CPU1 */\r
+/*! @{ */\r
+#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU)\r
+#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U)\r
+#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK)\r
+#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U)\r
+#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U)\r
+#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK)\r
+#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U)\r
+#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U)\r
+#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK)\r
+/*! @} */\r
+\r
+/*! @name NMISRC - NMI Source Select */\r
+/*! @{ */\r
+#define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU)\r
+#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U)\r
+#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK)\r
+#define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U)\r
+#define SYSCON_NMISRC_IRQCPU1_SHIFT (8U)\r
+#define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK)\r
+#define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U)\r
+#define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U)\r
+#define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK)\r
+#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U)\r
+#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U)\r
+#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRESETCTRL0 - Peripheral reset control 0 */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U)\r
+#define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U)\r
+/*! ROM_RST - ROM reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U)\r
+/*! SRAM_CTRL1_RST - SRAM Controller 1 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U)\r
+/*! SRAM_CTRL2_RST - SRAM Controller 2 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U)\r
+/*! SRAM_CTRL3_RST - SRAM Controller 3 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U)\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U)\r
+/*! SRAM_CTRL4_RST - SRAM Controller 4 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U)\r
+#define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U)\r
+/*! FLASH_RST - Flash controller reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U)\r
+#define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U)\r
+/*! FMC_RST - FMC controller reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U)\r
+#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U)\r
+/*! MUX0_RST - Input Mux 0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U)\r
+#define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U)\r
+/*! IOCON_RST - I/O controller reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U)\r
+#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U)\r
+/*! GPIO0_RST - GPIO0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U)\r
+#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U)\r
+/*! GPIO1_RST - GPIO1 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U)\r
+#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U)\r
+/*! GPIO2_RST - GPIO2 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U)\r
+#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U)\r
+/*! GPIO3_RST - GPIO3 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U)\r
+#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U)\r
+/*! PINT_RST - Pin interrupt (PINT) reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U)\r
+#define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U)\r
+/*! GINT_RST - Group interrupt (GINT) reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U)\r
+#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U)\r
+/*! DMA0_RST - DMA0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U)\r
+#define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U)\r
+/*! CRCGEN_RST - CRCGEN reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U)\r
+#define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U)\r
+/*! WWDT_RST - Watchdog Timer reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U)\r
+#define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U)\r
+/*! RTC_RST - Real Time Clock (RTC) reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U)\r
+#define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U)\r
+/*! MAILBOX_RST - Inter CPU communication Mailbox reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK)\r
+#define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U)\r
+#define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U)\r
+/*! ADC_RST - ADC reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL0_ADC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRESETCTRL1 - Peripheral reset control 1 */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U)\r
+#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U)\r
+/*! MRT_RST - MRT reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U)\r
+#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U)\r
+/*! OSTIMER0_RST - OS Timer 0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U)\r
+#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U)\r
+/*! SCT0_RST - SCT0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U)\r
+#define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U)\r
+/*! SCTIPU_RST - SCTIPU reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U)\r
+#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U)\r
+/*! UTICK0_RST - UTICK0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U)\r
+#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U)\r
+/*! FC0_RST - FC0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U)\r
+#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U)\r
+/*! FC1_RST - FC1 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U)\r
+#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U)\r
+/*! FC2_RST - FC2 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U)\r
+#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U)\r
+/*! FC3_RST - FC3 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U)\r
+#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U)\r
+/*! FC4_RST - FC4 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U)\r
+#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U)\r
+/*! FC5_RST - FC5 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U)\r
+#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U)\r
+/*! FC6_RST - FC6 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U)\r
+#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U)\r
+/*! FC7_RST - FC7 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U)\r
+#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U)\r
+/*! TIMER2_RST - Timer 2 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U)\r
+#define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U)\r
+/*! USB0_DEV_RST - USB0 DEV reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U)\r
+#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U)\r
+/*! TIMER0_RST - Timer 0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U)\r
+#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U)\r
+/*! TIMER1_RST - Timer 1 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U)\r
+#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U)\r
+/*! PVT_RST - PVT reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U)\r
+#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U)\r
+/*! EZHA_RST - EZH a reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK)\r
+#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U)\r
+#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U)\r
+/*! EZHB_RST - EZH b reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRESETCTRL2 - Peripheral reset control 2 */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U)\r
+#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U)\r
+/*! DMA1_RST - DMA1 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U)\r
+#define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U)\r
+/*! COMP_RST - Comparator reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U)\r
+#define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U)\r
+/*! SDIO_RST - SDIO reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U)\r
+#define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U)\r
+/*! USB1_HOST_RST - USB1 Host reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U)\r
+#define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U)\r
+/*! USB1_DEV_RST - USB1 dev reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U)\r
+#define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U)\r
+/*! USB1_RAM_RST - USB1 RAM reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U)\r
+#define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U)\r
+/*! USB1_PHY_RST - USB1 PHY reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U)\r
+#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U)\r
+/*! FREQME_RST - Frequency meter reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U)\r
+#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U)\r
+/*! GPIO4_RST - GPIO4 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U)\r
+#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U)\r
+/*! GPIO5_RST - GPIO5 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U)\r
+#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U)\r
+/*! OTP_RST - OTP reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U)\r
+#define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U)\r
+/*! RNG_RST - RNG reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U)\r
+#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U)\r
+/*! MUX1_RST - Peripheral Input Mux 1 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U)\r
+#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U)\r
+/*! USB0_HOSTM_RST - USB0 Host Master reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U)\r
+#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U)\r
+/*! USB0_HOSTS_RST - USB0 Host Slave reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U)\r
+#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U)\r
+/*! HASH0_RST - HASH0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U)\r
+#define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U)\r
+/*! PQ_RST - Power Quad reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U)\r
+#define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U)\r
+/*! PLULUT_RST - PLU LUT reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U)\r
+#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U)\r
+/*! TIMER3_RST - Timer 3 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U)\r
+#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U)\r
+/*! TIMER4_RST - Timer 4 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U)\r
+#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U)\r
+/*! PUF_RST - PUF reset control reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U)\r
+#define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U)\r
+/*! CASPER_RST - Casper reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U)\r
+#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U)\r
+/*! CAPT0_RST - CAPT0 reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U)\r
+#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U)\r
+/*! ANALOG_CTRL_RST - analog control reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U)\r
+#define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U)\r
+/*! HS_LSPI_RST - HS LSPI reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U)\r
+#define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U)\r
+/*! GPIO_SEC_RST - GPIO secure reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK)\r
+#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U)\r
+#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U)\r
+/*! GPIO_SEC_INT_RST - GPIO secure int reset control.\r
+ * 0b1..Bloc is reset.\r
+ * 0b0..Bloc is not reset.\r
+ */\r
+#define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK)\r
+/*! @} */\r
+\r
+/*! @name PRESETCTRLX - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PRESETCTRLX_DATA_SHIFT (0U)\r
+#define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PRESETCTRLX */\r
+#define SYSCON_PRESETCTRLX_COUNT (3U)\r
+\r
+/*! @name PRESETCTRLSET - Peripheral reset control set register */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U)\r
+#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PRESETCTRLSET */\r
+#define SYSCON_PRESETCTRLSET_COUNT (3U)\r
+\r
+/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */\r
+/*! @{ */\r
+#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U)\r
+#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_PRESETCTRLCLR */\r
+#define SYSCON_PRESETCTRLCLR_COUNT (3U)\r
+\r
+/*! @name SWR_RESET - generate a software_reset */\r
+/*! @{ */\r
+#define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU)\r
+#define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U)\r
+/*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset.\r
+ * 0b01011010000000000000000000000001..Generate a software reset.\r
+ * 0b00000000000000000000000000000000..Bloc is not reset.\r
+ */\r
+#define SYSCON_SWR_RESET_SWR_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWR_RESET_SWR_RESET_SHIFT)) & SYSCON_SWR_RESET_SWR_RESET_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBCLKCTRL0 - AHB Clock control 0 */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U)\r
+#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U)\r
+/*! ROM - Enables the clock for the ROM.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U)\r
+/*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U)\r
+/*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U)\r
+/*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U)\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U)\r
+/*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK)\r
+#define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U)\r
+#define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U)\r
+/*! FLASH - Enables the clock for the Flash controller.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK)\r
+#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U)\r
+#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U)\r
+/*! FMC - Enables the clock for the FMC controller.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK)\r
+#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U)\r
+#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U)\r
+/*! MUX0 - Enables the clock for the Input Mux 0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK)\r
+#define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U)\r
+#define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U)\r
+/*! IOCON - Enables the clock for the I/O controller.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK)\r
+#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U)\r
+#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U)\r
+/*! GPIO0 - Enables the clock for the GPIO0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK)\r
+#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U)\r
+#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U)\r
+/*! GPIO1 - Enables the clock for the GPIO1.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK)\r
+#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U)\r
+#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U)\r
+/*! GPIO2 - Enables the clock for the GPIO2.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK)\r
+#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U)\r
+#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U)\r
+/*! GPIO3 - Enables the clock for the GPIO3.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK)\r
+#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U)\r
+#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U)\r
+/*! PINT - Enables the clock for the Pin interrupt (PINT).\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK)\r
+#define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U)\r
+#define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U)\r
+/*! GINT - Enables the clock for the Group interrupt (GINT).\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK)\r
+#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U)\r
+#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U)\r
+/*! DMA0 - Enables the clock for the DMA0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK)\r
+#define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U)\r
+#define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U)\r
+/*! CRCGEN - Enables the clock for the CRCGEN.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK)\r
+#define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U)\r
+#define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U)\r
+/*! WWDT - Enables the clock for the Watchdog Timer.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK)\r
+#define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U)\r
+#define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U)\r
+/*! RTC - Enables the clock for the Real Time Clock (RTC).\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK)\r
+#define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U)\r
+#define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U)\r
+/*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK)\r
+#define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U)\r
+#define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U)\r
+/*! ADC - Enables the clock for the ADC.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ADC_SHIFT)) & SYSCON_AHBCLKCTRL0_ADC_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBCLKCTRL1 - AHB Clock control 1 */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U)\r
+#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U)\r
+/*! MRT - Enables the clock for the MRT.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK)\r
+#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U)\r
+#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U)\r
+/*! OSTIMER0 - Enables the clock for the OS Timer 0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK)\r
+#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U)\r
+#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U)\r
+/*! SCT0 - Enables the clock for the SCT0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK)\r
+#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U)\r
+#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U)\r
+/*! SCTIPU - Enables the clock for the SCTIPU.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK)\r
+#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U)\r
+#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U)\r
+/*! UTICK0 - Enables the clock for the UTICK0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U)\r
+#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U)\r
+/*! FC0 - Enables the clock for the FC0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U)\r
+#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U)\r
+/*! FC1 - Enables the clock for the FC1.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U)\r
+#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U)\r
+/*! FC2 - Enables the clock for the FC2.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U)\r
+#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U)\r
+/*! FC3 - Enables the clock for the FC3.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U)\r
+#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U)\r
+/*! FC4 - Enables the clock for the FC4.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U)\r
+#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U)\r
+/*! FC5 - Enables the clock for the FC5.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U)\r
+#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U)\r
+/*! FC6 - Enables the clock for the FC6.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK)\r
+#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U)\r
+#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U)\r
+/*! FC7 - Enables the clock for the FC7.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK)\r
+#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U)\r
+#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U)\r
+/*! TIMER2 - Enables the clock for the Timer 2.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK)\r
+#define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U)\r
+#define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U)\r
+/*! USB0_DEV - Enables the clock for the USB0 DEV.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK)\r
+#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U)\r
+#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U)\r
+/*! TIMER0 - Enables the clock for the Timer 0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK)\r
+#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U)\r
+#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U)\r
+/*! TIMER1 - Enables the clock for the Timer 1.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK)\r
+#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U)\r
+#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U)\r
+/*! PVT - Enables the clock for the PVT.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK)\r
+#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U)\r
+#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U)\r
+/*! EZHA - Enables the clock for the EZH a.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK)\r
+#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U)\r
+#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U)\r
+/*! EZHB - Enables the clock for the EZH b.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBCLKCTRL2 - AHB Clock control 2 */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U)\r
+#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U)\r
+/*! DMA1 - Enables the clock for the DMA1.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK)\r
+#define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U)\r
+#define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U)\r
+/*! COMP - Enables the clock for the Comparator.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK)\r
+#define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U)\r
+#define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U)\r
+/*! SDIO - Enables the clock for the SDIO.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK)\r
+#define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U)\r
+#define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U)\r
+/*! USB1_HOST - Enables the clock for the USB1 Host.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK)\r
+#define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U)\r
+#define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U)\r
+/*! USB1_DEV - Enables the clock for the USB1 dev.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK)\r
+#define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U)\r
+#define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U)\r
+/*! USB1_RAM - Enables the clock for the USB1 RAM.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK)\r
+#define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U)\r
+#define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U)\r
+/*! USB1_PHY - Enables the clock for the USB1 PHY.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK)\r
+#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U)\r
+#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U)\r
+/*! FREQME - Enables the clock for the Frequency meter.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK)\r
+#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U)\r
+#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U)\r
+/*! GPIO4 - Enables the clock for the GPIO4.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK)\r
+#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U)\r
+#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U)\r
+/*! GPIO5 - Enables the clock for the GPIO5.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK)\r
+#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U)\r
+#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U)\r
+/*! OTP - Enables the clock for the OTP.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK)\r
+#define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U)\r
+#define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U)\r
+/*! RNG - Enables the clock for the RNG.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK)\r
+#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U)\r
+#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U)\r
+/*! MUX1 - Enables the clock for the Peripheral Input Mux 1.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK)\r
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U)\r
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U)\r
+/*! USB0_HOSTM - Enables the clock for the USB0 Host Master.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK)\r
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U)\r
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U)\r
+/*! USB0_HOSTS - Enables the clock for the USB0 Host Slave.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK)\r
+#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U)\r
+#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U)\r
+/*! HASH0 - Enables the clock for the HASH0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK)\r
+#define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U)\r
+#define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U)\r
+/*! PQ - Enables the clock for the Power Quad.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK)\r
+#define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U)\r
+#define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U)\r
+/*! PLULUT - Enables the clock for the PLU LUT.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK)\r
+#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U)\r
+#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U)\r
+/*! TIMER3 - Enables the clock for the Timer 3.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK)\r
+#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U)\r
+#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U)\r
+/*! TIMER4 - Enables the clock for the Timer 4.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK)\r
+#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U)\r
+#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U)\r
+/*! PUF - Enables the clock for the PUF reset control.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK)\r
+#define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U)\r
+#define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U)\r
+/*! CASPER - Enables the clock for the Casper.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK)\r
+#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U)\r
+#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U)\r
+/*! CAPT0 - Enables the clock for the CAPT0.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK)\r
+#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U)\r
+#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U)\r
+/*! ANALOG_CTRL - Enables the clock for the analog control.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK)\r
+#define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U)\r
+#define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U)\r
+/*! HS_LSPI - Enables the clock for the HS LSPI.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK)\r
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U)\r
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U)\r
+/*! GPIO_SEC - Enables the clock for the GPIO secure.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK)\r
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U)\r
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U)\r
+/*! GPIO_SEC_INT - Enables the clock for the GPIO secure int.\r
+ * 0b1..Enable Clock.\r
+ * 0b0..Disable Clock.\r
+ */\r
+#define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name AHBCLKCTRLX - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U)\r
+#define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_AHBCLKCTRLX */\r
+#define SYSCON_AHBCLKCTRLX_COUNT (3U)\r
+\r
+/*! @name AHBCLKCTRLSET - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U)\r
+#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_AHBCLKCTRLSET */\r
+#define SYSCON_AHBCLKCTRLSET_COUNT (3U)\r
+\r
+/*! @name AHBCLKCTRLCLR - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U)\r
+#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_AHBCLKCTRLCLR */\r
+#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)\r
+\r
+/*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */\r
+/*! @{ */\r
+#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U)\r
+#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U)\r
+/*! SEL - System Tick Timer for CPU0 source select.\r
+ * 0b000..System Tick 0 divided clock.\r
+ * 0b001..FRO 1MHz clock.\r
+ * 0b010..Oscillator 32 kHz clock.\r
+ * 0b011..No clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */\r
+/*! @{ */\r
+#define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U)\r
+#define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U)\r
+/*! SEL - System Tick Timer for CPU1 source select.\r
+ * 0b000..System Tick 1 divided clock.\r
+ * 0b001..FRO 1MHz clock.\r
+ * 0b010..Oscillator 32 kHz clock.\r
+ * 0b011..No clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_SYSTICKCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL1_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL1_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSTICKCLKSELX - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U)\r
+#define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_SYSTICKCLKSELX */\r
+#define SYSCON_SYSTICKCLKSELX_COUNT (2U)\r
+\r
+/*! @name TRACECLKSEL - Trace clock source select */\r
+/*! @{ */\r
+#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - Trace clock source select.\r
+ * 0b000..Trace divided clock.\r
+ * 0b001..FRO 1MHz clock.\r
+ * 0b010..Oscillator 32 kHz clock.\r
+ * 0b011..No clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */\r
+/*! @{ */\r
+#define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U)\r
+#define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U)\r
+/*! SEL - CTimer 0 clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_CTIMERCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL0_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL0_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */\r
+/*! @{ */\r
+#define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U)\r
+#define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U)\r
+/*! SEL - CTimer 1 clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_CTIMERCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL1_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL1_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */\r
+/*! @{ */\r
+#define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U)\r
+#define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U)\r
+/*! SEL - CTimer 2 clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_CTIMERCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL2_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL2_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */\r
+/*! @{ */\r
+#define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U)\r
+#define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U)\r
+/*! SEL - CTimer 3 clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_CTIMERCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL3_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL3_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */\r
+/*! @{ */\r
+#define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U)\r
+#define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U)\r
+/*! SEL - CTimer 4 clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_CTIMERCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL4_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL4_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTIMERCLKSELX - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U)\r
+#define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_CTIMERCLKSELX */\r
+#define SYSCON_CTIMERCLKSELX_COUNT (5U)\r
+\r
+/*! @name MAINCLKSELA - Main clock A source select */\r
+/*! @{ */\r
+#define SYSCON_MAINCLKSELA_SEL_MASK (0x7U)\r
+#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)\r
+/*! SEL - Main clock A source select.\r
+ * 0b000..FRO 12 MHz clock.\r
+ * 0b001..CLKIN clock.\r
+ * 0b010..FRO 1MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MAINCLKSELB - Main clock source select */\r
+/*! @{ */\r
+#define SYSCON_MAINCLKSELB_SEL_MASK (0x7U)\r
+#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)\r
+/*! SEL - Main clock source select.\r
+ * 0b000..Main Clock A.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..PLL1 clock.\r
+ * 0b011..Oscillator 32 kHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKOUTSEL - CLKOUT clock source select */\r
+/*! @{ */\r
+#define SYSCON_CLKOUTSEL_SEL_MASK (0x7U)\r
+#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U)\r
+/*! SEL - CLKOUT clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..CLKIN clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..PLL1 clock.\r
+ * 0b110..Oscillator 32kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0CLKSEL - PLL0 clock source select */\r
+/*! @{ */\r
+#define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - PLL0 clock source select.\r
+ * 0b000..FRO 12 MHz clock.\r
+ * 0b001..CLKIN clock.\r
+ * 0b010..FRO 1MHz clock.\r
+ * 0b011..Oscillator 32kHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_PLL0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKSEL_SEL_SHIFT)) & SYSCON_PLL0CLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL1CLKSEL - PLL1 clock source select */\r
+/*! @{ */\r
+#define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - PLL1 clock source select.\r
+ * 0b000..FRO 12 MHz clock.\r
+ * 0b001..CLKIN clock.\r
+ * 0b010..FRO 1MHz clock.\r
+ * 0b011..Oscillator 32kHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_PLL1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLKSEL_SEL_SHIFT)) & SYSCON_PLL1CLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADCCLKSEL - ADC clock source select */\r
+/*! @{ */\r
+#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - ADC clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..FRO 96 MHz clock.\r
+ * 0b011..No clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKSEL - FS USB clock source select */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - FS USB clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..PLL1 clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - HS USB clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..CLKIN clock.\r
+ * 0b011..No clock.\r
+ * 0b100..No clock.\r
+ * 0b101..PLL1 clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL0_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL0_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL0_SEL_SHIFT)) & SYSCON_FCCLKSEL0_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL1_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL1_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL1_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL1_SEL_SHIFT)) & SYSCON_FCCLKSEL1_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL2_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL2_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL2_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL2_SEL_SHIFT)) & SYSCON_FCCLKSEL2_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL3_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL3_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL3_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL3_SEL_SHIFT)) & SYSCON_FCCLKSEL3_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL4_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL4_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL4_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL4_SEL_SHIFT)) & SYSCON_FCCLKSEL4_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL5_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL5_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL5_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL5_SEL_SHIFT)) & SYSCON_FCCLKSEL5_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL6_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL6_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL6_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL6_SEL_SHIFT)) & SYSCON_FCCLKSEL6_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSEL7_SEL_MASK (0x7U)\r
+#define SYSCON_FCCLKSEL7_SEL_SHIFT (0U)\r
+/*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_FCCLKSEL7_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL7_SEL_SHIFT)) & SYSCON_FCCLKSEL7_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCLKSELX - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_FCCLKSELX_DATA_SHIFT (0U)\r
+#define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_FCCLKSELX */\r
+#define SYSCON_FCCLKSELX_COUNT (8U)\r
+\r
+/*! @name HSLSPICLKSEL - HS LSPI clock source select */\r
+/*! @{ */\r
+#define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - HS LSPI clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..system PLL divided clock.\r
+ * 0b010..FRO 12 MHz clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..FRO 1MHz clock.\r
+ * 0b101..No clock.\r
+ * 0b110..Oscillator 32 kHz clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_HSLSPICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HSLSPICLKSEL_SEL_SHIFT)) & SYSCON_HSLSPICLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCLKCLKSEL - MCLK clock source select */\r
+/*! @{ */\r
+#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - MCLK clock source select.\r
+ * 0b000..FRO 96 MHz clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..No clock.\r
+ * 0b100..No clock.\r
+ * 0b101..No clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */\r
+/*! @{ */\r
+#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - SCTimer/PWM clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..CLKIN clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..MCLK clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIOCLKSEL - SDIO clock source select */\r
+/*! @{ */\r
+#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)\r
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)\r
+/*! SEL - SDIO clock source select.\r
+ * 0b000..Main clock.\r
+ * 0b001..PLL0 clock.\r
+ * 0b010..No clock.\r
+ * 0b011..FRO 96 MHz clock.\r
+ * 0b100..No clock.\r
+ * 0b101..PLL1 clock.\r
+ * 0b110..No clock.\r
+ * 0b111..No clock.\r
+ */\r
+#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */\r
+/*! @{ */\r
+#define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU)\r
+#define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U)\r
+#define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK)\r
+#define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U)\r
+#define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK)\r
+#define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U)\r
+#define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK)\r
+#define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV0_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */\r
+/*! @{ */\r
+#define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU)\r
+#define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U)\r
+#define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK)\r
+#define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U)\r
+#define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK)\r
+#define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U)\r
+#define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK)\r
+#define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_SYSTICKCLKDIV1_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name TRACECLKDIV - TRACE clock divider */\r
+/*! @{ */\r
+#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK)\r
+#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK)\r
+#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK)\r
+#define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_TRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_TRACECLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU)\r
+#define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U)\r
+#define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK)\r
+#define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U)\r
+#define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U)\r
+#define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLEXFRGXCTRL - Peripheral reset control register */\r
+/*! @{ */\r
+#define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU)\r
+#define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U)\r
+#define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_FLEXFRGXCTRL */\r
+#define SYSCON_FLEXFRGXCTRL_COUNT (8U)\r
+\r
+/*! @name AHBCLKDIV - System clock divider */\r
+/*! @{ */\r
+#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)\r
+#define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_AHBCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK)\r
+#define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_AHBCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK)\r
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLKOUTDIV - CLKOUT clock divider */\r
+/*! @{ */\r
+#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)\r
+#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)\r
+#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)\r
+#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)\r
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FROHFDIV - FRO_HF (96MHz) clock divider */\r
+/*! @{ */\r
+#define SYSCON_FROHFDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_FROHFDIV_DIV_SHIFT (0U)\r
+#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK)\r
+#define SYSCON_FROHFDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_FROHFDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK)\r
+#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_FROHFDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK)\r
+#define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_FROHFDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_REQFLAG_SHIFT)) & SYSCON_FROHFDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name WDTCLKDIV - WDT clock divider */\r
+/*! @{ */\r
+#define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU)\r
+#define SYSCON_WDTCLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK)\r
+#define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_WDTCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK)\r
+#define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_WDTCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK)\r
+#define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_WDTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_REQFLAG_SHIFT)) & SYSCON_WDTCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADCCLKDIV - ADC clock divider */\r
+/*! @{ */\r
+#define SYSCON_ADCCLKDIV_DIV_MASK (0x7U)\r
+#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)\r
+#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)\r
+#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)\r
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKDIV - USB0 Clock divider */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)\r
+#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)\r
+#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)\r
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCLKDIV - I2S MCLK clock divider */\r
+/*! @{ */\r
+#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_MCLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)\r
+#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_MCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)\r
+#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_MCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)\r
+#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SCTCLKDIV - SCT/PWM clock divider */\r
+/*! @{ */\r
+#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)\r
+#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)\r
+#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)\r
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIOCLKDIV - SDIO clock divider */\r
+/*! @{ */\r
+#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)\r
+#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)\r
+#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)\r
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0CLKDIV - PLL0 clock divider */\r
+/*! @{ */\r
+#define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU)\r
+#define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U)\r
+#define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK)\r
+#define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U)\r
+#define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U)\r
+/*! RESET - Resets the divider counter.\r
+ * 0b1..Divider is reset.\r
+ * 0b0..Divider is not reset.\r
+ */\r
+#define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK)\r
+#define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U)\r
+#define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U)\r
+/*! HALT - Halts the divider counter.\r
+ * 0b1..Divider clock is stoped.\r
+ * 0b0..Divider clock is running.\r
+ */\r
+#define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK)\r
+#define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U)\r
+#define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U)\r
+/*! REQFLAG - Divider status flag.\r
+ * 0b1..Clock frequency is not stable.\r
+ * 0b0..Divider clock is stable.\r
+ */\r
+#define SYSCON_PLL0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_REQFLAG_SHIFT)) & SYSCON_PLL0CLKDIV_REQFLAG_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */\r
+/*! @{ */\r
+#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U)\r
+/*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL).\r
+ * 0b00000000000000000000000000000001..update all clock configuration.\r
+ * 0b00000000000000000000000000000000..all hardware clock configruration are freeze.\r
+ */\r
+#define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U)\r
+#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U)\r
+/*! FETCHCTL - Fetch control\r
+ * 0b00..No buffering (bypass always used) for Fetch cycles\r
+ * 0b01..One buffer is used for all Fetch cycles\r
+ * 0b10..All buffers can be used for Fetch cycles\r
+ */\r
+#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK)\r
+#define SYSCON_FMCCR_DATACTL_MASK (0xCU)\r
+#define SYSCON_FMCCR_DATACTL_SHIFT (2U)\r
+/*! DATACTL - Data control\r
+ * 0b00..No buffering (bypass always used) for Data cycles\r
+ * 0b01..One buffer is used for all Data cycles\r
+ * 0b10..All buffers can be used for Data cycles\r
+ */\r
+#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK)\r
+#define SYSCON_FMCCR_ACCEL_MASK (0x10U)\r
+#define SYSCON_FMCCR_ACCEL_SHIFT (4U)\r
+#define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK)\r
+#define SYSCON_FMCCR_PREFEN_MASK (0x20U)\r
+#define SYSCON_FMCCR_PREFEN_SHIFT (5U)\r
+#define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK)\r
+#define SYSCON_FMCCR_PREFOVR_MASK (0x40U)\r
+#define SYSCON_FMCCR_PREFOVR_SHIFT (6U)\r
+#define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK)\r
+#define SYSCON_FMCCR_PREFCRI_MASK (0x700U)\r
+#define SYSCON_FMCCR_PREFCRI_SHIFT (8U)\r
+#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK)\r
+#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U)\r
+#define SYSCON_FMCCR_FMCTIM_SHIFT (12U)\r
+#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK)\r
+#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U)\r
+#define SYSCON_FMCCR_PFISLRU_SHIFT (17U)\r
+#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK)\r
+#define SYSCON_FMCCR_PFADAP_MASK (0x40000U)\r
+#define SYSCON_FMCCR_PFADAP_SHIFT (18U)\r
+#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKCTRL - USB0 clock control */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)\r
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)\r
+/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:.\r
+ * 0b0..Under hardware control.\r
+ * 0b1..Forced high.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)\r
+/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.\r
+ * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.\r
+ * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)\r
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)\r
+/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:.\r
+ * 0b0..Under hardware control.\r
+ * 0b1..Forced high.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)\r
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)\r
+/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:.\r
+ * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up.\r
+ * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)\r
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)\r
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)\r
+/*! PU_DISABLE - Internal pull-up disable control.\r
+ * 0b1..Internal pull-up disable.\r
+ * 0b0..Internal pull-up enable.\r
+ */\r
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB0CLKSTAT - USB0 clock status */\r
+/*! @{ */\r
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)\r
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)\r
+/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:.\r
+ * 0b1..USB0 Device clock is high.\r
+ * 0b0..USB0 Device clock is low.\r
+ */\r
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)\r
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)\r
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)\r
+/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:.\r
+ * 0b1..USB0 Host clock is high.\r
+ * 0b0..USB0 Host clock is low.\r
+ */\r
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)\r
+/*! @} */\r
+\r
+/*! @name FMCFLUSH - FMCflush control */\r
+/*! @{ */\r
+#define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U)\r
+#define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U)\r
+#define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK)\r
+/*! @} */\r
+\r
+/*! @name MCLKIO - MCLK control */\r
+/*! @{ */\r
+#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU)\r
+#define SYSCON_MCLKIO_MCLKIO_SHIFT (0U)\r
+/*! MCLKIO - MCLK control.\r
+ * 0b00000000000000000000000000000000..input mode.\r
+ * 0b00000000000000000000000000000001..output mode.\r
+ */\r
+#define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKCTRL - USB1 clock control */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U)\r
+#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U)\r
+/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:.\r
+ * 0b0..Under hardware control.\r
+ * 0b1..Forced high.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U)\r
+#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U)\r
+/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:.\r
+ * 0b0..Falling edge of device need_clock triggers wake-up.\r
+ * 0b1..Rising edge of device need_clock triggers wake-up.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U)\r
+#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U)\r
+/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:.\r
+ * 0b0..Under hardware control.\r
+ * 0b1..Forced high.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U)\r
+#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U)\r
+/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up.\r
+ * 0b0..Falling edge of device need_clock triggers wake-up.\r
+ * 0b1..Rising edge of device need_clock triggers wake-up.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK)\r
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)\r
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)\r
+/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:.\r
+ * 0b0..Forces USB1 PHY to wake-up.\r
+ * 0b1..Normal USB1 PHY behavior.\r
+ */\r
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1CLKSTAT - USB1 clock status */\r
+/*! @{ */\r
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)\r
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)\r
+/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:.\r
+ * 0b1..USB1 Device clock is high.\r
+ * 0b0..USB1 Device clock is low.\r
+ */\r
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)\r
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)\r
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)\r
+/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:.\r
+ * 0b1..USB1 Host clock is high.\r
+ * 0b0..USB1 Host clock is low.\r
+ */\r
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLASHBANKENABLE - Flash Banks control */\r
+/*! @{ */\r
+#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU)\r
+#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U)\r
+/*! BANK0 - Flash Bank0 control.\r
+ * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed).\r
+ * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed).\r
+ */\r
+#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK)\r
+#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U)\r
+#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U)\r
+/*! BANK1 - Flash Bank1 control.\r
+ * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed).\r
+ * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed).\r
+ */\r
+#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK)\r
+#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U)\r
+#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U)\r
+/*! BANK2 - Flash Bank2 control.\r
+ * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed).\r
+ * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed).\r
+ */\r
+#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK)\r
+/*! @} */\r
+\r
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */\r
+/*! @{ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)\r
+/*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in.\r
+ * 0b00..0 degree shift.\r
+ * 0b01..90 degree shift.\r
+ * 0b10..180 degree shift.\r
+ * 0b11..270 degree shift.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)\r
+/*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in.\r
+ * 0b00..0 degree shift.\r
+ * 0b01..90 degree shift.\r
+ * 0b10..180 degree shift.\r
+ * 0b11..270 degree shift.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)\r
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)\r
+/*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE.\r
+ * 0b0..Bypassed.\r
+ * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)\r
+/*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field.\r
+ * 0b1..Enable drive delay.\r
+ * 0b0..Disable drive delay.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)\r
+/*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field.\r
+ * 0b1..Enables sample delay.\r
+ * 0b0..Disables sample delay.\r
+ */\r
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL1CTRL - PLL1 550m control */\r
+/*! @{ */\r
+#define SYSCON_PLL1CTRL_SELR_MASK (0xFU)\r
+#define SYSCON_PLL1CTRL_SELR_SHIFT (0U)\r
+#define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK)\r
+#define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U)\r
+#define SYSCON_PLL1CTRL_SELI_SHIFT (4U)\r
+#define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK)\r
+#define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U)\r
+#define SYSCON_PLL1CTRL_SELP_SHIFT (10U)\r
+#define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK)\r
+#define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U)\r
+#define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U)\r
+/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).\r
+ * 0b1..PLL input clock is sent directly to the PLL output.\r
+ * 0b0..use PLL.\r
+ */\r
+#define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK)\r
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U)\r
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U)\r
+/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.\r
+ * 0b1..bypass of the divide-by-2 divider in the post-divider.\r
+ * 0b0..use the divide-by-2 divider in the post-divider.\r
+ */\r
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)\r
+#define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U)\r
+#define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U)\r
+#define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK)\r
+#define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U)\r
+#define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U)\r
+/*! BWDIRECT - control of the bandwidth of the PLL.\r
+ * 0b1..modify the bandwidth of the PLL directly.\r
+ * 0b0..the bandwidth is changed synchronously with the feedback-divider.\r
+ */\r
+#define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK)\r
+#define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U)\r
+#define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U)\r
+/*! BYPASSPREDIV - bypass of the pre-divider.\r
+ * 0b1..bypass of the pre-divider.\r
+ * 0b0..use the pre-divider.\r
+ */\r
+#define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK)\r
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U)\r
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U)\r
+/*! BYPASSPOSTDIV - bypass of the post-divider.\r
+ * 0b1..bypass of the post-divider.\r
+ * 0b0..use the post-divider.\r
+ */\r
+#define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK)\r
+#define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U)\r
+#define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U)\r
+/*! CLKEN - enable the output clock.\r
+ * 0b1..Enable the output clock.\r
+ * 0b0..Disable the output clock.\r
+ */\r
+#define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK)\r
+#define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U)\r
+#define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U)\r
+#define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK)\r
+#define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U)\r
+#define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U)\r
+#define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK)\r
+#define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U)\r
+#define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U)\r
+/*! SKEWEN - Skew mode.\r
+ * 0b1..skewmode is enable.\r
+ * 0b0..skewmode is disable.\r
+ */\r
+#define SYSCON_PLL1CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SKEWEN_SHIFT)) & SYSCON_PLL1CTRL_SKEWEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL1STAT - PLL1 550m status */\r
+/*! @{ */\r
+#define SYSCON_PLL1STAT_LOCK_MASK (0x1U)\r
+#define SYSCON_PLL1STAT_LOCK_SHIFT (0U)\r
+#define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK)\r
+#define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U)\r
+#define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U)\r
+#define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK)\r
+#define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U)\r
+#define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U)\r
+#define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK)\r
+#define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U)\r
+#define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U)\r
+#define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK)\r
+#define SYSCON_PLL1STAT_FRMDET_MASK (0x10U)\r
+#define SYSCON_PLL1STAT_FRMDET_SHIFT (4U)\r
+#define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL1NDEC - PLL1 550m N divider */\r
+/*! @{ */\r
+#define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU)\r
+#define SYSCON_PLL1NDEC_NDIV_SHIFT (0U)\r
+#define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK)\r
+#define SYSCON_PLL1NDEC_NREQ_MASK (0x100U)\r
+#define SYSCON_PLL1NDEC_NREQ_SHIFT (8U)\r
+#define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL1MDEC - PLL1 550m M divider */\r
+/*! @{ */\r
+#define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU)\r
+#define SYSCON_PLL1MDEC_MDIV_SHIFT (0U)\r
+#define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK)\r
+#define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U)\r
+#define SYSCON_PLL1MDEC_MREQ_SHIFT (16U)\r
+#define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL1PDEC - PLL1 550m P divider */\r
+/*! @{ */\r
+#define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU)\r
+#define SYSCON_PLL1PDEC_PDIV_SHIFT (0U)\r
+#define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK)\r
+#define SYSCON_PLL1PDEC_PREQ_MASK (0x20U)\r
+#define SYSCON_PLL1PDEC_PREQ_SHIFT (5U)\r
+#define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0CTRL - PLL0 550m control */\r
+/*! @{ */\r
+#define SYSCON_PLL0CTRL_SELR_MASK (0xFU)\r
+#define SYSCON_PLL0CTRL_SELR_SHIFT (0U)\r
+#define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK)\r
+#define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U)\r
+#define SYSCON_PLL0CTRL_SELI_SHIFT (4U)\r
+#define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK)\r
+#define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U)\r
+#define SYSCON_PLL0CTRL_SELP_SHIFT (10U)\r
+#define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK)\r
+#define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U)\r
+#define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U)\r
+/*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default).\r
+ * 0b1..Bypass PLL input clock is sent directly to the PLL output.\r
+ * 0b0..use PLL.\r
+ */\r
+#define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK)\r
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U)\r
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U)\r
+/*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider.\r
+ * 0b1..bypass of the divide-by-2 divider in the post-divider.\r
+ * 0b0..use the divide-by-2 divider in the post-divider.\r
+ */\r
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)\r
+#define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U)\r
+#define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U)\r
+#define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK)\r
+#define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U)\r
+#define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U)\r
+/*! BWDIRECT - Control of the bandwidth of the PLL.\r
+ * 0b1..modify the bandwidth of the PLL directly.\r
+ * 0b0..the bandwidth is changed synchronously with the feedback-divider.\r
+ */\r
+#define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK)\r
+#define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U)\r
+#define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U)\r
+/*! BYPASSPREDIV - bypass of the pre-divider.\r
+ * 0b1..bypass of the pre-divider.\r
+ * 0b0..use the pre-divider.\r
+ */\r
+#define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK)\r
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U)\r
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U)\r
+/*! BYPASSPOSTDIV - bypass of the post-divider.\r
+ * 0b1..bypass of the post-divider.\r
+ * 0b0..use the post-divider.\r
+ */\r
+#define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK)\r
+#define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U)\r
+#define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U)\r
+/*! CLKEN - enable the output clock.\r
+ * 0b1..enable the output clock.\r
+ * 0b0..disable the output clock.\r
+ */\r
+#define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK)\r
+#define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U)\r
+#define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U)\r
+/*! FRMEN - free running mode.\r
+ * 0b1..free running mode is enable.\r
+ * 0b0..free running mode is disable.\r
+ */\r
+#define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK)\r
+#define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U)\r
+#define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U)\r
+#define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK)\r
+#define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U)\r
+#define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U)\r
+/*! SKEWEN - skew mode.\r
+ * 0b1..skew mode is enable.\r
+ * 0b0..skew mode is disable.\r
+ */\r
+#define SYSCON_PLL0CTRL_SKEWEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SKEWEN_SHIFT)) & SYSCON_PLL0CTRL_SKEWEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0STAT - PLL0 550m status */\r
+/*! @{ */\r
+#define SYSCON_PLL0STAT_LOCK_MASK (0x1U)\r
+#define SYSCON_PLL0STAT_LOCK_SHIFT (0U)\r
+#define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK)\r
+#define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U)\r
+#define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U)\r
+#define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK)\r
+#define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U)\r
+#define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U)\r
+#define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK)\r
+#define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U)\r
+#define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U)\r
+#define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK)\r
+#define SYSCON_PLL0STAT_FRMDET_MASK (0x10U)\r
+#define SYSCON_PLL0STAT_FRMDET_SHIFT (4U)\r
+#define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0NDEC - PLL0 550m N divider */\r
+/*! @{ */\r
+#define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU)\r
+#define SYSCON_PLL0NDEC_NDIV_SHIFT (0U)\r
+#define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK)\r
+#define SYSCON_PLL0NDEC_NREQ_MASK (0x100U)\r
+#define SYSCON_PLL0NDEC_NREQ_SHIFT (8U)\r
+#define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0PDEC - PLL0 550m P divider */\r
+/*! @{ */\r
+#define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU)\r
+#define SYSCON_PLL0PDEC_PDIV_SHIFT (0U)\r
+#define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK)\r
+#define SYSCON_PLL0PDEC_PREQ_MASK (0x20U)\r
+#define SYSCON_PLL0PDEC_PREQ_SHIFT (5U)\r
+#define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */\r
+/*! @{ */\r
+#define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU)\r
+#define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U)\r
+#define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */\r
+/*! @{ */\r
+#define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U)\r
+#define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U)\r
+#define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK)\r
+#define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U)\r
+#define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U)\r
+#define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK)\r
+#define SYSCON_PLL0SSCG1_MF_MASK (0x1CU)\r
+#define SYSCON_PLL0SSCG1_MF_SHIFT (2U)\r
+#define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)\r
+#define SYSCON_PLL0SSCG1_MR_MASK (0xE0U)\r
+#define SYSCON_PLL0SSCG1_MR_SHIFT (5U)\r
+#define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK)\r
+#define SYSCON_PLL0SSCG1_MC_MASK (0x300U)\r
+#define SYSCON_PLL0SSCG1_MC_SHIFT (8U)\r
+#define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK)\r
+#define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U)\r
+#define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U)\r
+#define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)\r
+#define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U)\r
+#define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U)\r
+#define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK)\r
+#define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U)\r
+#define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U)\r
+#define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK)\r
+#define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U)\r
+#define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U)\r
+#define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK)\r
+/*! @} */\r
+\r
+/*! @name EFUSECLKCTRL - eFUSE controller clock enable */\r
+/*! @{ */\r
+#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U)\r
+#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U)\r
+#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name STARTER - Start logic wake-up enable register */\r
+/*! @{ */\r
+#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U)\r
+#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U)\r
+/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK)\r
+#define SYSCON_STARTER_SYS_MASK (0x1U)\r
+#define SYSCON_STARTER_SYS_SHIFT (0U)\r
+/*! SYS - SYS interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK)\r
+#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U)\r
+#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U)\r
+/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK)\r
+#define SYSCON_STARTER_SDMA0_MASK (0x2U)\r
+#define SYSCON_STARTER_SDMA0_SHIFT (1U)\r
+/*! SDMA0 - SDMA0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK)\r
+#define SYSCON_STARTER_GINT0_MASK (0x4U)\r
+#define SYSCON_STARTER_GINT0_SHIFT (2U)\r
+/*! GINT0 - GINT0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)\r
+#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U)\r
+#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U)\r
+/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK)\r
+#define SYSCON_STARTER_GINT1_MASK (0x8U)\r
+#define SYSCON_STARTER_GINT1_SHIFT (3U)\r
+/*! GINT1 - GINT1 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)\r
+#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U)\r
+#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U)\r
+/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK)\r
+#define SYSCON_STARTER_CTIMER2_MASK (0x10U)\r
+#define SYSCON_STARTER_CTIMER2_SHIFT (4U)\r
+/*! CTIMER2 - CTIMER2 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)\r
+#define SYSCON_STARTER_PIO_INT0_MASK (0x10U)\r
+#define SYSCON_STARTER_PIO_INT0_SHIFT (4U)\r
+/*! PIO_INT0 - PIO_INT0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK)\r
+#define SYSCON_STARTER_CTIMER4_MASK (0x20U)\r
+#define SYSCON_STARTER_CTIMER4_SHIFT (5U)\r
+/*! CTIMER4 - CTIMER4 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)\r
+#define SYSCON_STARTER_PIO_INT1_MASK (0x20U)\r
+#define SYSCON_STARTER_PIO_INT1_SHIFT (5U)\r
+/*! PIO_INT1 - PIO_INT1 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK)\r
+#define SYSCON_STARTER_OS_EVENT_MASK (0x40U)\r
+#define SYSCON_STARTER_OS_EVENT_SHIFT (6U)\r
+/*! OS_EVENT - OS_EVENT interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK)\r
+#define SYSCON_STARTER_PIO_INT2_MASK (0x40U)\r
+#define SYSCON_STARTER_PIO_INT2_SHIFT (6U)\r
+/*! PIO_INT2 - PIO_INT2 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK)\r
+#define SYSCON_STARTER_PIO_INT3_MASK (0x80U)\r
+#define SYSCON_STARTER_PIO_INT3_SHIFT (7U)\r
+/*! PIO_INT3 - PIO_INT3 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK)\r
+#define SYSCON_STARTER_UTICK0_MASK (0x100U)\r
+#define SYSCON_STARTER_UTICK0_SHIFT (8U)\r
+/*! UTICK0 - UTICK0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK)\r
+#define SYSCON_STARTER_MRT0_MASK (0x200U)\r
+#define SYSCON_STARTER_MRT0_SHIFT (9U)\r
+/*! MRT0 - MRT0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK)\r
+#define SYSCON_STARTER_CTIMER0_MASK (0x400U)\r
+#define SYSCON_STARTER_CTIMER0_SHIFT (10U)\r
+/*! CTIMER0 - CTIMER0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)\r
+#define SYSCON_STARTER_SDIO_MASK (0x400U)\r
+#define SYSCON_STARTER_SDIO_SHIFT (10U)\r
+/*! SDIO - SDIO interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK)\r
+#define SYSCON_STARTER_CTIMER1_MASK (0x800U)\r
+#define SYSCON_STARTER_CTIMER1_SHIFT (11U)\r
+/*! CTIMER1 - CTIMER1 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)\r
+#define SYSCON_STARTER_SCT0_MASK (0x1000U)\r
+#define SYSCON_STARTER_SCT0_SHIFT (12U)\r
+/*! SCT0 - SCT0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)\r
+#define SYSCON_STARTER_CTIMER3_MASK (0x2000U)\r
+#define SYSCON_STARTER_CTIMER3_SHIFT (13U)\r
+/*! CTIMER3 - CTIMER3 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)\r
+#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U)\r
+#define SYSCON_STARTER_FLEXINT0_SHIFT (14U)\r
+/*! FLEXINT0 - FLEXINT0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK)\r
+#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U)\r
+#define SYSCON_STARTER_FLEXINT1_SHIFT (15U)\r
+/*! FLEXINT1 - FLEXINT1 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK)\r
+#define SYSCON_STARTER_USB1_MASK (0x8000U)\r
+#define SYSCON_STARTER_USB1_SHIFT (15U)\r
+/*! USB1 - USB1 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)\r
+#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U)\r
+#define SYSCON_STARTER_FLEXINT2_SHIFT (16U)\r
+/*! FLEXINT2 - FLEXINT2 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK)\r
+#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U)\r
+#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U)\r
+/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK)\r
+#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U)\r
+#define SYSCON_STARTER_FLEXINT3_SHIFT (17U)\r
+/*! FLEXINT3 - FLEXINT3 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK)\r
+#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U)\r
+#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U)\r
+/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK)\r
+#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U)\r
+#define SYSCON_STARTER_FLEXINT4_SHIFT (18U)\r
+/*! FLEXINT4 - FLEXINT4 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK)\r
+#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U)\r
+#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U)\r
+/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK)\r
+#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U)\r
+#define SYSCON_STARTER_FLEXINT5_SHIFT (19U)\r
+/*! FLEXINT5 - FLEXINT5 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK)\r
+#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U)\r
+#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U)\r
+/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK)\r
+#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U)\r
+#define SYSCON_STARTER_FLEXINT6_SHIFT (20U)\r
+/*! FLEXINT6 - FLEXINT6 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK)\r
+#define SYSCON_STARTER_PLU_MASK (0x100000U)\r
+#define SYSCON_STARTER_PLU_SHIFT (20U)\r
+/*! PLU - PLU interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK)\r
+#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U)\r
+#define SYSCON_STARTER_FLEXINT7_SHIFT (21U)\r
+/*! FLEXINT7 - FLEXINT7 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK)\r
+#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U)\r
+#define SYSCON_STARTER_SEC_VIO_SHIFT (21U)\r
+/*! SEC_VIO - SEC_VIO interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK)\r
+#define SYSCON_STARTER_ADC0_MASK (0x400000U)\r
+#define SYSCON_STARTER_ADC0_SHIFT (22U)\r
+/*! ADC0 - ADC0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK)\r
+#define SYSCON_STARTER_SHA_MASK (0x400000U)\r
+#define SYSCON_STARTER_SHA_SHIFT (22U)\r
+/*! SHA - SHA interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK)\r
+#define SYSCON_STARTER_CASER_MASK (0x800000U)\r
+#define SYSCON_STARTER_CASER_SHIFT (23U)\r
+/*! CASER - CASER interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK)\r
+#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U)\r
+#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U)\r
+/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK)\r
+#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U)\r
+#define SYSCON_STARTER_QDDKEY_SHIFT (24U)\r
+/*! QDDKEY - QDDKEY interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK)\r
+#define SYSCON_STARTER_PQ_MASK (0x2000000U)\r
+#define SYSCON_STARTER_PQ_SHIFT (25U)\r
+/*! PQ - PQ interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK)\r
+#define SYSCON_STARTER_SDMA1_MASK (0x4000000U)\r
+#define SYSCON_STARTER_SDMA1_SHIFT (26U)\r
+/*! SDMA1 - SDMA1 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK)\r
+#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U)\r
+#define SYSCON_STARTER_LSPI_HS_SHIFT (27U)\r
+/*! LSPI_HS - LSPI_HS interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK)\r
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)\r
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)\r
+/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)\r
+#define SYSCON_STARTER_USB0_MASK (0x10000000U)\r
+#define SYSCON_STARTER_USB0_SHIFT (28U)\r
+/*! USB0 - USB0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)\r
+#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U)\r
+#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U)\r
+/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK)\r
+#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U)\r
+#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U)\r
+/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK)\r
+#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U)\r
+#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U)\r
+#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK)\r
+#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U)\r
+#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U)\r
+/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up.\r
+ * 0b0..Wake-up disabled.\r
+ * 0b1..Wake-up enabled.\r
+ */\r
+#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_STARTER */\r
+#define SYSCON_STARTER_COUNT (2U)\r
+\r
+/*! @name STARTERSET - Set bits in STARTER */\r
+/*! @{ */\r
+#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U)\r
+#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U)\r
+#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK)\r
+#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U)\r
+#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U)\r
+#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U)\r
+#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U)\r
+#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK)\r
+#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U)\r
+#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U)\r
+#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U)\r
+#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U)\r
+#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U)\r
+#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U)\r
+#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U)\r
+#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U)\r
+#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U)\r
+#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U)\r
+#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK)\r
+#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U)\r
+#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U)\r
+#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U)\r
+#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U)\r
+#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK)\r
+#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U)\r
+#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U)\r
+#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U)\r
+#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U)\r
+#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U)\r
+#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U)\r
+#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK)\r
+#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U)\r
+#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U)\r
+#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK)\r
+#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U)\r
+#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U)\r
+#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK)\r
+#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U)\r
+#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U)\r
+#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK)\r
+#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U)\r
+#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U)\r
+#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK)\r
+#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U)\r
+#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U)\r
+#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK)\r
+#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U)\r
+#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U)\r
+#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK)\r
+#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U)\r
+#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U)\r
+#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK)\r
+#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U)\r
+#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U)\r
+#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK)\r
+#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U)\r
+#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U)\r
+#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U)\r
+#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U)\r
+#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U)\r
+#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U)\r
+#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK)\r
+#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U)\r
+#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U)\r
+#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U)\r
+#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U)\r
+#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK)\r
+#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U)\r
+#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U)\r
+#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U)\r
+#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U)\r
+#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK)\r
+#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U)\r
+#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U)\r
+#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U)\r
+#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U)\r
+#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK)\r
+#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U)\r
+#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U)\r
+#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U)\r
+#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U)\r
+#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK)\r
+#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U)\r
+#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U)\r
+#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U)\r
+#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U)\r
+#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK)\r
+#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U)\r
+#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U)\r
+#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK)\r
+#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U)\r
+#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U)\r
+#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK)\r
+#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U)\r
+#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U)\r
+#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK)\r
+#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U)\r
+#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U)\r
+#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK)\r
+#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U)\r
+#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U)\r
+#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK)\r
+#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U)\r
+#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U)\r
+#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK)\r
+#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U)\r
+#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U)\r
+#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK)\r
+#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U)\r
+#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U)\r
+#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK)\r
+#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U)\r
+#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U)\r
+#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK)\r
+#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U)\r
+#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U)\r
+#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK)\r
+#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U)\r
+#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U)\r
+#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK)\r
+#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U)\r
+#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U)\r
+#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK)\r
+#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U)\r
+#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U)\r
+#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK)\r
+#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U)\r
+#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U)\r
+#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK)\r
+#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U)\r
+#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U)\r
+#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK)\r
+#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U)\r
+#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U)\r
+#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK)\r
+#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U)\r
+#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U)\r
+#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_STARTERSET */\r
+#define SYSCON_STARTERSET_COUNT (2U)\r
+\r
+/*! @name STARTERCLR - Clear bits in STARTER */\r
+/*! @{ */\r
+#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U)\r
+#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U)\r
+#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U)\r
+#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U)\r
+#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U)\r
+#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U)\r
+#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U)\r
+#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U)\r
+#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U)\r
+#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U)\r
+#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U)\r
+#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U)\r
+#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U)\r
+#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U)\r
+#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U)\r
+#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U)\r
+#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK)\r
+#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U)\r
+#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U)\r
+#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U)\r
+#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U)\r
+#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK)\r
+#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U)\r
+#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U)\r
+#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U)\r
+#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U)\r
+#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U)\r
+#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U)\r
+#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK)\r
+#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U)\r
+#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U)\r
+#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK)\r
+#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U)\r
+#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U)\r
+#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK)\r
+#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U)\r
+#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U)\r
+#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U)\r
+#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U)\r
+#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U)\r
+#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U)\r
+#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U)\r
+#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U)\r
+#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK)\r
+#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U)\r
+#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U)\r
+#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U)\r
+#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U)\r
+#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U)\r
+#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U)\r
+#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U)\r
+#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U)\r
+#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U)\r
+#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U)\r
+#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK)\r
+#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U)\r
+#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U)\r
+#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U)\r
+#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U)\r
+#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK)\r
+#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U)\r
+#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U)\r
+#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U)\r
+#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U)\r
+#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U)\r
+#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U)\r
+#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U)\r
+#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U)\r
+#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U)\r
+#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U)\r
+#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U)\r
+#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U)\r
+#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U)\r
+#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U)\r
+#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U)\r
+#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U)\r
+#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK)\r
+#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U)\r
+#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U)\r
+#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK)\r
+#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U)\r
+#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U)\r
+#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U)\r
+#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U)\r
+#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK)\r
+#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U)\r
+#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U)\r
+#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U)\r
+#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U)\r
+#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK)\r
+#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U)\r
+#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U)\r
+#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK)\r
+#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U)\r
+#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U)\r
+#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK)\r
+#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U)\r
+#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U)\r
+#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK)\r
+#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U)\r
+#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U)\r
+#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK)\r
+#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U)\r
+#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U)\r
+#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK)\r
+#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U)\r
+#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U)\r
+#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK)\r
+#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U)\r
+#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U)\r
+#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK)\r
+#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U)\r
+#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U)\r
+#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U)\r
+#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U)\r
+#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U)\r
+#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U)\r
+#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK)\r
+#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U)\r
+#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U)\r
+#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK)\r
+#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U)\r
+#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U)\r
+#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCON_STARTERCLR */\r
+#define SYSCON_STARTERCLR_COUNT (2U)\r
+\r
+/*! @name HARDWARESLEEP - Hardware Sleep control */\r
+/*! @{ */\r
+#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U)\r
+#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U)\r
+#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK)\r
+#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U)\r
+#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U)\r
+#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK)\r
+#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U)\r
+#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U)\r
+#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK)\r
+#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U)\r
+#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U)\r
+#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPUCTRL - CPU Control for multiple processors */\r
+/*! @{ */\r
+#define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U)\r
+#define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U)\r
+/*! CPU1CLKEN - CPU1 clock enable.\r
+ * 0b1..The CPU1 clock is enabled.\r
+ * 0b0..The CPU1 clock is not enabled.\r
+ */\r
+#define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK)\r
+#define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U)\r
+#define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U)\r
+/*! CPU1RSTEN - CPU1 reset.\r
+ * 0b1..The CPU1 is being reset.\r
+ * 0b0..The CPU1 is not being reset.\r
+ */\r
+#define SYSCON_CPUCTRL_CPU1RSTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1RSTEN_SHIFT)) & SYSCON_CPUCTRL_CPU1RSTEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPBOOT - Coprocessor Boot Address */\r
+/*! @{ */\r
+#define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CPBOOT_CPBOOT_SHIFT (0U)\r
+#define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPSTACK - Coprocessor Stack Address */\r
+/*! @{ */\r
+#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U)\r
+#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPSTAT - CPU Status */\r
+/*! @{ */\r
+#define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U)\r
+#define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U)\r
+/*! CPU0SLEEPING - The CPU0 sleeping state.\r
+ * 0b1..the CPU is sleeping.\r
+ * 0b0..the CPU is not sleeping.\r
+ */\r
+#define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK)\r
+#define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U)\r
+#define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U)\r
+/*! CPU1SLEEPING - The CPU1 sleeping state.\r
+ * 0b1..the CPU is sleeping.\r
+ * 0b0..the CPU is not sleeping.\r
+ */\r
+#define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK)\r
+#define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U)\r
+#define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U)\r
+/*! CPU0LOCKUP - The CPU0 lockup state.\r
+ * 0b1..the CPU is in lockup.\r
+ * 0b0..the CPU is not in lockup.\r
+ */\r
+#define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK)\r
+#define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U)\r
+#define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U)\r
+/*! CPU1LOCKUP - The CPU1 lockup state.\r
+ * 0b1..the CPU is in lockup.\r
+ * 0b0..the CPU is not in lockup.\r
+ */\r
+#define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG0 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U)\r
+#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG1 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U)\r
+#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG2 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U)\r
+#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG3 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U)\r
+#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG4 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U)\r
+#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG5 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U)\r
+#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG6 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U)\r
+#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK)\r
+/*! @} */\r
+\r
+/*! @name DICE_REG7 - Composite Device Identifier */\r
+/*! @{ */\r
+#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U)\r
+#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK)\r
+/*! @} */\r
+\r
+/*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */\r
+/*! @{ */\r
+#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U)\r
+#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U)\r
+/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U)\r
+#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U)\r
+/*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U)\r
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U)\r
+/*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U)\r
+#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U)\r
+/*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U)\r
+#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U)\r
+/*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U)\r
+#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U)\r
+/*! CLKIN_ENA - Enable clock_in clock for clock module.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U)\r
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U)\r
+/*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U)\r
+#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U)\r
+/*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U)\r
+#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U)\r
+/*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK)\r
+#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U)\r
+#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U)\r
+/*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching.\r
+ * 0b1..The clock is enabled.\r
+ * 0b0..The clock is not enabled.\r
+ */\r
+#define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK)\r
+/*! @} */\r
+\r
+/*! @name COMP_INT_CTRL - Comparator Interrupt control */\r
+/*! @{ */\r
+#define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U)\r
+#define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U)\r
+/*! INT_ENABLE - Analog Comparator interrupt enable control:.\r
+ * 0b1..interrupt enable.\r
+ * 0b0..interrupt disable.\r
+ */\r
+#define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK)\r
+#define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U)\r
+#define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U)\r
+/*! INT_CLEAR - Analog Comparator interrupt clear.\r
+ * 0b0..No effect.\r
+ * 0b1..Clear the interrupt. Self-cleared bit.\r
+ */\r
+#define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK)\r
+#define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU)\r
+#define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U)\r
+/*! INT_CTRL - Comparator interrupt type selector:.\r
+ * 0b000..The analog comparator interrupt edge sensitive is disabled.\r
+ * 0b010..analog comparator interrupt is rising edge sensitive.\r
+ * 0b100..analog comparator interrupt is falling edge sensitive.\r
+ * 0b110..analog comparator interrupt is rising and falling edge sensitive.\r
+ * 0b001..The analog comparator interrupt level sensitive is disabled.\r
+ * 0b011..Analog Comparator interrupt is high level sensitive.\r
+ * 0b101..Analog Comparator interrupt is low level sensitive.\r
+ * 0b111..The analog comparator interrupt level sensitive is disabled.\r
+ */\r
+#define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK)\r
+#define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U)\r
+#define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U)\r
+/*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection.\r
+ * 0b0..Select Analog Comparator filtered output as input for interrupt detection.\r
+ * 0b1..Select Analog Comparator raw output (unfiltered) as input for interrupt detection. Must be used when Analog comparator is used as wake up source in Power down mode.\r
+ */\r
+#define SYSCON_COMP_INT_CTRL_INT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK)\r
+/*! @} */\r
+\r
+/*! @name COMP_INT_STATUS - Comparator Interrupt status */\r
+/*! @{ */\r
+#define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U)\r
+#define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U)\r
+/*! STATUS - Interrupt status BEFORE Interrupt Enable.\r
+ * 0b0..no interrupt pending.\r
+ * 0b1..interrupt pending.\r
+ */\r
+#define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK)\r
+#define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U)\r
+#define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U)\r
+/*! INT_STATUS - Interrupt status AFTER Interrupt Enable.\r
+ * 0b0..no interrupt pending.\r
+ * 0b1..interrupt pending.\r
+ */\r
+#define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK)\r
+#define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U)\r
+#define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U)\r
+/*! VAL - comparator analog output.\r
+ * 0b1..P+ is greater than P-.\r
+ * 0b0..P+ is smaller than P-.\r
+ */\r
+#define SYSCON_COMP_INT_STATUS_VAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_VAL_SHIFT)) & SYSCON_COMP_INT_STATUS_VAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */\r
+/*! @{ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U)\r
+/*! ROM - Control automatic clock gating of ROM controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U)\r
+/*! RAMX_CTRL - Control automatic clock gating of RAMX controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U)\r
+/*! RAM0_CTRL - Control automatic clock gating of RAM0 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U)\r
+/*! RAM1_CTRL - Control automatic clock gating of RAM1 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U)\r
+/*! RAM2_CTRL - Control automatic clock gating of RAM2 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U)\r
+/*! RAM3_CTRL - Control automatic clock gating of RAM3 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U)\r
+/*! RAM4_CTRL - Control automatic clock gating of RAM4 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U)\r
+/*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U)\r
+/*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U)\r
+/*! FLASH - Control automatic clock gating of FLASH controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U)\r
+/*! FMC - Control automatic clock gating of FMC controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U)\r
+/*! CRCGEN - Control automatic clock gating of CRCGEN controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U)\r
+/*! SDMA0 - Control automatic clock gating of DMA0 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U)\r
+/*! SDMA1 - Control automatic clock gating of DMA1 controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U)\r
+/*! USB - Control automatic clock gating of USB controller.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U)\r
+/*! SYSCON - Control automatic clock gating of synchronous system controller registers bank.\r
+ * 0b1..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U)\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U)\r
+/*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect.\r
+ * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled).\r
+ * 0b0000000000000000..Automatic clock gating is not overridden.\r
+ */\r
+#define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK)\r
+/*! @} */\r
+\r
+/*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */\r
+/*! @{ */\r
+#define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U)\r
+#define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U)\r
+/*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module.\r
+ * 0b1..bypass of the first stage of synchonization inside GPIO_INT module.\r
+ * 0b0..use the first stage of synchonization inside GPIO_INT module.\r
+ */\r
+#define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU)\r
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U)\r
+/*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers.\r
+ * 0b1010..1010: Enable write access to all 6 registers.\r
+ * 0b0000..Any other value than b1010: disable write access to all 6 registers.\r
+ */\r
+#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U)\r
+#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U)\r
+/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU)\r
+#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U)\r
+/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U)\r
+#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U)\r
+/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U)\r
+#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U)\r
+/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U)\r
+#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U)\r
+/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U)\r
+#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U)\r
+/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U)\r
+/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U)\r
+/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U)\r
+/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U)\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U)\r
+/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U)\r
+#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U)\r
+/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK)\r
+#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U)\r
+#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U)\r
+/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:.\r
+ * 0b10..10: Invasive debug is enabled.\r
+ * 0b01..Any other value than b10: invasive debug is disable.\r
+ */\r
+#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U)\r
+/*! SEC_CODE - Security code to allow test access : 0x12345678.\r
+ * 0b00010010001101000101011001111000..Security code to allow test access.\r
+ * 0b00000000000000000000000000000000..test access is not allowed.\r
+ */\r
+#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U)\r
+/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678.\r
+ * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP.\r
+ * 0b00000000000000000000000000000000..CPU0 DAP is not allowed.\r
+ */\r
+#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU)\r
+#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U)\r
+/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678.\r
+ * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP.\r
+ * 0b00000000000000000000000000000000..CPU1 DAP is not allowed.\r
+ */\r
+#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU)\r
+#define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U)\r
+#define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU)\r
+#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U)\r
+#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK)\r
+/*! @} */\r
+\r
+/*! @name CPUCFG - CPUs configuration register */\r
+/*! @{ */\r
+#define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U)\r
+#define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U)\r
+/*! CPU1ENABLE - Enable CPU1.\r
+ * 0b0..CPU1 is disable (Processor in reset).\r
+ * 0b1..CPU1 is enable.\r
+ */\r
+#define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */\r
+/*! @{ */\r
+#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U)\r
+#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U)\r
+/*! SCTEN - SCT enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK)\r
+#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U)\r
+#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U)\r
+/*! ADCEN - ADC enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK)\r
+#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U)\r
+#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U)\r
+/*! USB0EN - USB0 enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK)\r
+#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U)\r
+#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U)\r
+/*! PUFFEN - Puff enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK)\r
+#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U)\r
+#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U)\r
+/*! USB1EN - USB1 enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK)\r
+#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U)\r
+#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U)\r
+/*! SDIOEN - SDIO enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK)\r
+#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U)\r
+#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U)\r
+/*! HASHEN - HASH enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK)\r
+#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U)\r
+#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U)\r
+/*! PRINCEEN - PRINCE enable.\r
+ * 0b1..peripheral is enable.\r
+ * 0b0..peripheral is disable.\r
+ */\r
+#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEVICE_ID0 - Device ID */\r
+/*! @{ */\r
+#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU)\r
+#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U)\r
+#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK)\r
+#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U)\r
+#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U)\r
+#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK)\r
+#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U)\r
+#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U)\r
+#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK)\r
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U)\r
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U)\r
+#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK)\r
+#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U)\r
+#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U)\r
+#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK)\r
+/*! @} */\r
+\r
+/*! @name DIEID - Chip revision ID and Number */\r
+/*! @{ */\r
+#define SYSCON_DIEID_REV_ID_MASK (0xFU)\r
+#define SYSCON_DIEID_REV_ID_SHIFT (0U)\r
+#define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK)\r
+#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U)\r
+#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U)\r
+#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SYSCON_Register_Masks */\r
+\r
+\r
+/* SYSCON - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral SYSCON base address */\r
+ #define SYSCON_BASE (0x50000000u)\r
+ /** Peripheral SYSCON base address */\r
+ #define SYSCON_BASE_NS (0x40000000u)\r
+ /** Peripheral SYSCON base pointer */\r
+ #define SYSCON ((SYSCON_Type *)SYSCON_BASE)\r
+ /** Peripheral SYSCON base pointer */\r
+ #define SYSCON_NS ((SYSCON_Type *)SYSCON_BASE_NS)\r
+ /** Array initializer of SYSCON peripheral base addresses */\r
+ #define SYSCON_BASE_ADDRS { SYSCON_BASE }\r
+ /** Array initializer of SYSCON peripheral base pointers */\r
+ #define SYSCON_BASE_PTRS { SYSCON }\r
+ /** Array initializer of SYSCON peripheral base addresses */\r
+ #define SYSCON_BASE_ADDRS_NS { SYSCON_BASE_NS }\r
+ /** Array initializer of SYSCON peripheral base pointers */\r
+ #define SYSCON_BASE_PTRS_NS { SYSCON_NS }\r
+#else\r
+ /** Peripheral SYSCON base address */\r
+ #define SYSCON_BASE (0x40000000u)\r
+ /** Peripheral SYSCON base pointer */\r
+ #define SYSCON ((SYSCON_Type *)SYSCON_BASE)\r
+ /** Array initializer of SYSCON peripheral base addresses */\r
+ #define SYSCON_BASE_ADDRS { SYSCON_BASE }\r
+ /** Array initializer of SYSCON peripheral base pointers */\r
+ #define SYSCON_BASE_PTRS { SYSCON }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SYSCON_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SYSCTL Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SYSCTL_Peripheral_Access_Layer SYSCTL Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** SYSCTL - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t UPDATELCKOUT; /**< update lock out control, offset: 0x0 */\r
+ uint8_t RESERVED_0[60];\r
+ __IO uint32_t FCCTRLSEL[8]; /**< Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7, array offset: 0x40, array step: 0x4 */\r
+ uint8_t RESERVED_1[32];\r
+ __IO uint32_t SHAREDCTRLSET[2]; /**< Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1., array offset: 0x80, array step: 0x4 */\r
+ uint8_t RESERVED_2[120];\r
+ __I uint32_t USB_HS_STATUS; /**< Status register for USB HS, offset: 0x100 */\r
+} SYSCTL_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SYSCTL Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SYSCTL_Register_Masks SYSCTL Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name UPDATELCKOUT - update lock out control */\r
+/*! @{ */\r
+#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U)\r
+#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U)\r
+/*! UPDATELCKOUT - All Registers\r
+ * 0b0..Normal Mode. Can be written to.\r
+ * 0b1..Protected Mode. Cannot be written to.\r
+ */\r
+#define SYSCTL_UPDATELCKOUT_UPDATELCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT)) & SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */\r
+/*! @{ */\r
+#define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U)\r
+#define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U)\r
+/*! SCKINSEL - Selects the source for SCK going into this Flexcomm.\r
+ * 0b00..Selects the dedicated FCn_SCK function for this Flexcomm.\r
+ * 0b01..SCK is taken from shared signal set 0 (defined by SHAREDCTRLSET0).\r
+ * 0b10..SCK is taken from shared signal set 1 (defined by SHAREDCTRLSET1).\r
+ * 0b11..Reserved.\r
+ */\r
+#define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK)\r
+#define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U)\r
+#define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U)\r
+/*! WSINSEL - Selects the source for WS going into this Flexcomm.\r
+ * 0b00..Selects the dedicated (FCn_TXD_SCL_MISO_WS) function for this Flexcomm.\r
+ * 0b01..WS is taken from shared signal set 0 (defined by SHAREDCTRLSET0).\r
+ * 0b10..WS is taken from shared signal set 1 (defined by SHAREDCTRLSET1).\r
+ * 0b11..Reserved.\r
+ */\r
+#define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK)\r
+#define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U)\r
+#define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U)\r
+/*! DATAINSEL - Selects the source for DATA input to this Flexcomm.\r
+ * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA input for this Flexcomm.\r
+ * 0b01..Input data is taken from shared signal set 0 (defined by SHAREDCTRLSET0).\r
+ * 0b10..Input data is taken from shared signal set 1 (defined by SHAREDCTRLSET1).\r
+ * 0b11..Reserved.\r
+ */\r
+#define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK)\r
+#define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U)\r
+#define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U)\r
+/*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm.\r
+ * 0b00..Selects the dedicated FCn_RXD_SDA_MOSI_DATA output from this Flexcomm.\r
+ * 0b01..Output data is taken from shared signal set 0 (defined by SHAREDCTRLSET0).\r
+ * 0b10..Output data is taken from shared signal set 1 (defined by SHAREDCTRLSET1).\r
+ * 0b11..Reserved.\r
+ */\r
+#define SYSCTL_FCCTRLSEL_DATAOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCTL_FCCTRLSEL */\r
+#define SYSCTL_FCCTRLSEL_COUNT (8U)\r
+\r
+/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */\r
+/*! @{ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U)\r
+/*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set.\r
+ * 0b000..SCK for this shared signal set comes from Flexcomm 0.\r
+ * 0b001..SCK for this shared signal set comes from Flexcomm 1.\r
+ * 0b010..SCK for this shared signal set comes from Flexcomm 2.\r
+ * 0b011..SCK for this shared signal set comes from Flexcomm 3.\r
+ * 0b100..SCK for this shared signal set comes from Flexcomm 4.\r
+ * 0b101..SCK for this shared signal set comes from Flexcomm 5.\r
+ * 0b110..SCK for this shared signal set comes from Flexcomm 6.\r
+ * 0b111..SCK for this shared signal set comes from Flexcomm 7.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U)\r
+/*! SHAREDWSSEL - Selects the source for WS of this shared signal set.\r
+ * 0b000..WS for this shared signal set comes from Flexcomm 0.\r
+ * 0b001..WS for this shared signal set comes from Flexcomm 1.\r
+ * 0b010..WS for this shared signal set comes from Flexcomm 2.\r
+ * 0b011..WS for this shared signal set comes from Flexcomm 3.\r
+ * 0b100..WS for this shared signal set comes from Flexcomm 4.\r
+ * 0b101..WS for this shared signal set comes from Flexcomm 5.\r
+ * 0b110..WS for this shared signal set comes from Flexcomm 6.\r
+ * 0b111..WS for this shared signal set comes from Flexcomm 7.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U)\r
+/*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set.\r
+ * 0b000..DATA input for this shared signal set comes from Flexcomm 0.\r
+ * 0b001..DATA input for this shared signal set comes from Flexcomm 1.\r
+ * 0b010..DATA input for this shared signal set comes from Flexcomm 2.\r
+ * 0b011..DATA input for this shared signal set comes from Flexcomm 3.\r
+ * 0b100..DATA input for this shared signal set comes from Flexcomm 4.\r
+ * 0b101..DATA input for this shared signal set comes from Flexcomm 5.\r
+ * 0b110..DATA input for this shared signal set comes from Flexcomm 6.\r
+ * 0b111..DATA input for this shared signal set comes from Flexcomm 7.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U)\r
+/*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC0 does not contribute to this shared set.\r
+ * 0b1..Data output from FC0 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U)\r
+/*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC1 does not contribute to this shared set.\r
+ * 0b1..Data output from FC1 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U)\r
+/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC2 does not contribute to this shared set.\r
+ * 0b1..Data output from FC2 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U)\r
+/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC3 does not contribute to this shared set.\r
+ * 0b1..Data output from FC3 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U)\r
+/*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC4 does not contribute to this shared set.\r
+ * 0b1..Data output from FC4 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U)\r
+/*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC5 does not contribute to this shared set.\r
+ * 0b1..Data output from FC5 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U)\r
+/*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC6 does not contribute to this shared set.\r
+ * 0b1..Data output from FC6 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U)\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U)\r
+/*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set.\r
+ * 0b0..Data output from FC7 does not contribute to this shared set.\r
+ * 0b1..Data output from FC7 does contribute to this shared set.\r
+ */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK)\r
+/*! @} */\r
+\r
+/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */\r
+#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U)\r
+\r
+/*! @name USB_HS_STATUS - Status register for USB HS */\r
+/*! @{ */\r
+#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U)\r
+#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U)\r
+/*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply.\r
+ * 0b0..3v3 supply is good.\r
+ * 0b1..3v3 supply is too low.\r
+ */\r
+#define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT)) & SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SYSCTL_Register_Masks */\r
+\r
+\r
+/* SYSCTL - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral SYSCTL base address */\r
+ #define SYSCTL_BASE (0x50023000u)\r
+ /** Peripheral SYSCTL base address */\r
+ #define SYSCTL_BASE_NS (0x40023000u)\r
+ /** Peripheral SYSCTL base pointer */\r
+ #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE)\r
+ /** Peripheral SYSCTL base pointer */\r
+ #define SYSCTL_NS ((SYSCTL_Type *)SYSCTL_BASE_NS)\r
+ /** Array initializer of SYSCTL peripheral base addresses */\r
+ #define SYSCTL_BASE_ADDRS { SYSCTL_BASE }\r
+ /** Array initializer of SYSCTL peripheral base pointers */\r
+ #define SYSCTL_BASE_PTRS { SYSCTL }\r
+ /** Array initializer of SYSCTL peripheral base addresses */\r
+ #define SYSCTL_BASE_ADDRS_NS { SYSCTL_BASE_NS }\r
+ /** Array initializer of SYSCTL peripheral base pointers */\r
+ #define SYSCTL_BASE_PTRS_NS { SYSCTL_NS }\r
+#else\r
+ /** Peripheral SYSCTL base address */\r
+ #define SYSCTL_BASE (0x40023000u)\r
+ /** Peripheral SYSCTL base pointer */\r
+ #define SYSCTL ((SYSCTL_Type *)SYSCTL_BASE)\r
+ /** Array initializer of SYSCTL peripheral base addresses */\r
+ #define SYSCTL_BASE_ADDRS { SYSCTL_BASE }\r
+ /** Array initializer of SYSCTL peripheral base pointers */\r
+ #define SYSCTL_BASE_PTRS { SYSCTL }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SYSCTL_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USART Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USART - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */\r
+ __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */\r
+ __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */\r
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */\r
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */\r
+ __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */\r
+ __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */\r
+ __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */\r
+ uint8_t RESERVED_1[3536];\r
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */\r
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */\r
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */\r
+ uint8_t RESERVED_2[4];\r
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */\r
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */\r
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */\r
+ uint8_t RESERVED_3[4];\r
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */\r
+ uint8_t RESERVED_4[12];\r
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */\r
+ uint8_t RESERVED_5[12];\r
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */\r
+ uint8_t RESERVED_6[440];\r
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */\r
+} USART_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USART Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USART_Register_Masks USART Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */\r
+/*! @{ */\r
+#define USART_CFG_ENABLE_MASK (0x1U)\r
+#define USART_CFG_ENABLE_SHIFT (0U)\r
+/*! ENABLE - USART Enable.\r
+ * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available.\r
+ * 0b1..Enabled. The USART is enabled for operation.\r
+ */\r
+#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)\r
+#define USART_CFG_DATALEN_MASK (0xCU)\r
+#define USART_CFG_DATALEN_SHIFT (2U)\r
+/*! DATALEN - Selects the data size for the USART.\r
+ * 0b00..7 bit Data length.\r
+ * 0b01..8 bit Data length.\r
+ * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.\r
+ * 0b11..Reserved.\r
+ */\r
+#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)\r
+#define USART_CFG_PARITYSEL_MASK (0x30U)\r
+#define USART_CFG_PARITYSEL_SHIFT (4U)\r
+/*! PARITYSEL - Selects what type of parity is used by the USART.\r
+ * 0b00..No parity.\r
+ * 0b01..Reserved.\r
+ * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.\r
+ * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.\r
+ */\r
+#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)\r
+#define USART_CFG_STOPLEN_MASK (0x40U)\r
+#define USART_CFG_STOPLEN_SHIFT (6U)\r
+/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.\r
+ * 0b0..1 stop bit.\r
+ * 0b1..2 stop bits. This setting should only be used for asynchronous communication.\r
+ */\r
+#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)\r
+#define USART_CFG_MODE32K_MASK (0x80U)\r
+#define USART_CFG_MODE32K_SHIFT (7U)\r
+/*! MODE32K - Selects standard or 32 kHz clocking mode.\r
+ * 0b0..Disabled. USART uses standard clocking.\r
+ * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.\r
+ */\r
+#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)\r
+#define USART_CFG_LINMODE_MASK (0x100U)\r
+#define USART_CFG_LINMODE_SHIFT (8U)\r
+/*! LINMODE - LIN break mode enable.\r
+ * 0b0..Disabled. Break detect and generate is configured for normal operation.\r
+ * 0b1..Enabled. Break detect and generate is configured for LIN bus operation.\r
+ */\r
+#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)\r
+#define USART_CFG_CTSEN_MASK (0x200U)\r
+#define USART_CFG_CTSEN_SHIFT (9U)\r
+/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled.\r
+ * 0b0..No flow control. The transmitter does not receive any automatic flow control signal.\r
+ * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.\r
+ */\r
+#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)\r
+#define USART_CFG_SYNCEN_MASK (0x800U)\r
+#define USART_CFG_SYNCEN_SHIFT (11U)\r
+/*! SYNCEN - Selects synchronous or asynchronous operation.\r
+ * 0b0..Asynchronous mode.\r
+ * 0b1..Synchronous mode.\r
+ */\r
+#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)\r
+#define USART_CFG_CLKPOL_MASK (0x1000U)\r
+#define USART_CFG_CLKPOL_SHIFT (12U)\r
+/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode.\r
+ * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK.\r
+ * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK.\r
+ */\r
+#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)\r
+#define USART_CFG_SYNCMST_MASK (0x4000U)\r
+#define USART_CFG_SYNCMST_SHIFT (14U)\r
+/*! SYNCMST - Synchronous mode Master select.\r
+ * 0b0..Slave. When synchronous mode is enabled, the USART is a slave.\r
+ * 0b1..Master. When synchronous mode is enabled, the USART is a master.\r
+ */\r
+#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)\r
+#define USART_CFG_LOOP_MASK (0x8000U)\r
+#define USART_CFG_LOOP_SHIFT (15U)\r
+/*! LOOP - Selects data loopback mode.\r
+ * 0b0..Normal operation.\r
+ * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.\r
+ */\r
+#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)\r
+#define USART_CFG_OETA_MASK (0x40000U)\r
+#define USART_CFG_OETA_SHIFT (18U)\r
+/*! OETA - Output Enable Turnaround time enable for RS-485 operation.\r
+ * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.\r
+ * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.\r
+ */\r
+#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)\r
+#define USART_CFG_AUTOADDR_MASK (0x80000U)\r
+#define USART_CFG_AUTOADDR_SHIFT (19U)\r
+/*! AUTOADDR - Automatic Address matching enable.\r
+ * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).\r
+ * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.\r
+ */\r
+#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)\r
+#define USART_CFG_OESEL_MASK (0x100000U)\r
+#define USART_CFG_OESEL_SHIFT (20U)\r
+/*! OESEL - Output Enable Select.\r
+ * 0b0..Standard. The RTS signal is used as the standard flow control function.\r
+ * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.\r
+ */\r
+#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)\r
+#define USART_CFG_OEPOL_MASK (0x200000U)\r
+#define USART_CFG_OEPOL_SHIFT (21U)\r
+/*! OEPOL - Output Enable Polarity.\r
+ * 0b0..Low. If selected by OESEL, the output enable is active low.\r
+ * 0b1..High. If selected by OESEL, the output enable is active high.\r
+ */\r
+#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)\r
+#define USART_CFG_RXPOL_MASK (0x400000U)\r
+#define USART_CFG_RXPOL_SHIFT (22U)\r
+/*! RXPOL - Receive data polarity.\r
+ * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.\r
+ * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.\r
+ */\r
+#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)\r
+#define USART_CFG_TXPOL_MASK (0x800000U)\r
+#define USART_CFG_TXPOL_SHIFT (23U)\r
+/*! TXPOL - Transmit data polarity.\r
+ * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.\r
+ * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.\r
+ */\r
+#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */\r
+/*! @{ */\r
+#define USART_CTL_TXBRKEN_MASK (0x2U)\r
+#define USART_CTL_TXBRKEN_SHIFT (1U)\r
+/*! TXBRKEN - Break Enable.\r
+ * 0b0..Normal operation.\r
+ * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN.\r
+ */\r
+#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)\r
+#define USART_CTL_ADDRDET_MASK (0x4U)\r
+#define USART_CTL_ADDRDET_SHIFT (2U)\r
+/*! ADDRDET - Enable address detect mode.\r
+ * 0b0..Disabled. The USART presents all incoming data.\r
+ * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally.\r
+ */\r
+#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)\r
+#define USART_CTL_TXDIS_MASK (0x40U)\r
+#define USART_CTL_TXDIS_SHIFT (6U)\r
+/*! TXDIS - Transmit Disable.\r
+ * 0b0..Not disabled. USART transmitter is not disabled.\r
+ * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control.\r
+ */\r
+#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)\r
+#define USART_CTL_CC_MASK (0x100U)\r
+#define USART_CTL_CC_SHIFT (8U)\r
+/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode.\r
+ * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received.\r
+ * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD).\r
+ */\r
+#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)\r
+#define USART_CTL_CLRCCONRX_MASK (0x200U)\r
+#define USART_CTL_CLRCCONRX_SHIFT (9U)\r
+/*! CLRCCONRX - Clear Continuous Clock.\r
+ * 0b0..No effect. No effect on the CC bit.\r
+ * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time.\r
+ */\r
+#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)\r
+#define USART_CTL_AUTOBAUD_MASK (0x10000U)\r
+#define USART_CTL_AUTOBAUD_SHIFT (16U)\r
+/*! AUTOBAUD - Autobaud enable.\r
+ * 0b0..Disabled. USART is in normal operating mode.\r
+ * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR.\r
+ */\r
+#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */\r
+/*! @{ */\r
+#define USART_STAT_RXIDLE_MASK (0x2U)\r
+#define USART_STAT_RXIDLE_SHIFT (1U)\r
+#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)\r
+#define USART_STAT_TXIDLE_MASK (0x8U)\r
+#define USART_STAT_TXIDLE_SHIFT (3U)\r
+#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)\r
+#define USART_STAT_CTS_MASK (0x10U)\r
+#define USART_STAT_CTS_SHIFT (4U)\r
+#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)\r
+#define USART_STAT_DELTACTS_MASK (0x20U)\r
+#define USART_STAT_DELTACTS_SHIFT (5U)\r
+#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)\r
+#define USART_STAT_TXDISSTAT_MASK (0x40U)\r
+#define USART_STAT_TXDISSTAT_SHIFT (6U)\r
+#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)\r
+#define USART_STAT_RXBRK_MASK (0x400U)\r
+#define USART_STAT_RXBRK_SHIFT (10U)\r
+#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)\r
+#define USART_STAT_DELTARXBRK_MASK (0x800U)\r
+#define USART_STAT_DELTARXBRK_SHIFT (11U)\r
+#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)\r
+#define USART_STAT_START_MASK (0x1000U)\r
+#define USART_STAT_START_SHIFT (12U)\r
+#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)\r
+#define USART_STAT_FRAMERRINT_MASK (0x2000U)\r
+#define USART_STAT_FRAMERRINT_SHIFT (13U)\r
+#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)\r
+#define USART_STAT_PARITYERRINT_MASK (0x4000U)\r
+#define USART_STAT_PARITYERRINT_SHIFT (14U)\r
+#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)\r
+#define USART_STAT_RXNOISEINT_MASK (0x8000U)\r
+#define USART_STAT_RXNOISEINT_SHIFT (15U)\r
+#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)\r
+#define USART_STAT_ABERR_MASK (0x10000U)\r
+#define USART_STAT_ABERR_SHIFT (16U)\r
+#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */\r
+/*! @{ */\r
+#define USART_INTENSET_TXIDLEEN_MASK (0x8U)\r
+#define USART_INTENSET_TXIDLEEN_SHIFT (3U)\r
+#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)\r
+#define USART_INTENSET_DELTACTSEN_MASK (0x20U)\r
+#define USART_INTENSET_DELTACTSEN_SHIFT (5U)\r
+#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)\r
+#define USART_INTENSET_TXDISEN_MASK (0x40U)\r
+#define USART_INTENSET_TXDISEN_SHIFT (6U)\r
+#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)\r
+#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)\r
+#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)\r
+#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)\r
+#define USART_INTENSET_STARTEN_MASK (0x1000U)\r
+#define USART_INTENSET_STARTEN_SHIFT (12U)\r
+#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)\r
+#define USART_INTENSET_FRAMERREN_MASK (0x2000U)\r
+#define USART_INTENSET_FRAMERREN_SHIFT (13U)\r
+#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)\r
+#define USART_INTENSET_PARITYERREN_MASK (0x4000U)\r
+#define USART_INTENSET_PARITYERREN_SHIFT (14U)\r
+#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)\r
+#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)\r
+#define USART_INTENSET_RXNOISEEN_SHIFT (15U)\r
+#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)\r
+#define USART_INTENSET_ABERREN_MASK (0x10000U)\r
+#define USART_INTENSET_ABERREN_SHIFT (16U)\r
+#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */\r
+/*! @{ */\r
+#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)\r
+#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)\r
+#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)\r
+#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)\r
+#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)\r
+#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)\r
+#define USART_INTENCLR_TXDISCLR_MASK (0x40U)\r
+#define USART_INTENCLR_TXDISCLR_SHIFT (6U)\r
+#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)\r
+#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)\r
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)\r
+#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)\r
+#define USART_INTENCLR_STARTCLR_MASK (0x1000U)\r
+#define USART_INTENCLR_STARTCLR_SHIFT (12U)\r
+#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)\r
+#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)\r
+#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)\r
+#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)\r
+#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)\r
+#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)\r
+#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)\r
+#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)\r
+#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)\r
+#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)\r
+#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)\r
+#define USART_INTENCLR_ABERRCLR_SHIFT (16U)\r
+#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)\r
+/*! @} */\r
+\r
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */\r
+/*! @{ */\r
+#define USART_BRG_BRGVAL_MASK (0xFFFFU)\r
+#define USART_BRG_BRGVAL_SHIFT (0U)\r
+#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */\r
+/*! @{ */\r
+#define USART_INTSTAT_TXIDLE_MASK (0x8U)\r
+#define USART_INTSTAT_TXIDLE_SHIFT (3U)\r
+#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)\r
+#define USART_INTSTAT_DELTACTS_MASK (0x20U)\r
+#define USART_INTSTAT_DELTACTS_SHIFT (5U)\r
+#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)\r
+#define USART_INTSTAT_TXDISINT_MASK (0x40U)\r
+#define USART_INTSTAT_TXDISINT_SHIFT (6U)\r
+#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)\r
+#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)\r
+#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)\r
+#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)\r
+#define USART_INTSTAT_START_MASK (0x1000U)\r
+#define USART_INTSTAT_START_SHIFT (12U)\r
+#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)\r
+#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)\r
+#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)\r
+#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)\r
+#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)\r
+#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)\r
+#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)\r
+#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)\r
+#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)\r
+#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)\r
+#define USART_INTSTAT_ABERRINT_MASK (0x10000U)\r
+#define USART_INTSTAT_ABERRINT_SHIFT (16U)\r
+#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name OSR - Oversample selection register for asynchronous communication. */\r
+/*! @{ */\r
+#define USART_OSR_OSRVAL_MASK (0xFU)\r
+#define USART_OSR_OSRVAL_SHIFT (0U)\r
+#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)\r
+/*! @} */\r
+\r
+/*! @name ADDR - Address register for automatic address matching. */\r
+/*! @{ */\r
+#define USART_ADDR_ADDRESS_MASK (0xFFU)\r
+#define USART_ADDR_ADDRESS_SHIFT (0U)\r
+#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOCFG - FIFO configuration and enable register. */\r
+/*! @{ */\r
+#define USART_FIFOCFG_ENABLETX_MASK (0x1U)\r
+#define USART_FIFOCFG_ENABLETX_SHIFT (0U)\r
+/*! ENABLETX - Enable the transmit FIFO.\r
+ * 0b0..The transmit FIFO is not enabled.\r
+ * 0b1..The transmit FIFO is enabled.\r
+ */\r
+#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)\r
+#define USART_FIFOCFG_ENABLERX_MASK (0x2U)\r
+#define USART_FIFOCFG_ENABLERX_SHIFT (1U)\r
+/*! ENABLERX - Enable the receive FIFO.\r
+ * 0b0..The receive FIFO is not enabled.\r
+ * 0b1..The receive FIFO is enabled.\r
+ */\r
+#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)\r
+#define USART_FIFOCFG_SIZE_MASK (0x30U)\r
+#define USART_FIFOCFG_SIZE_SHIFT (4U)\r
+#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)\r
+#define USART_FIFOCFG_DMATX_MASK (0x1000U)\r
+#define USART_FIFOCFG_DMATX_SHIFT (12U)\r
+/*! DMATX - DMA configuration for transmit.\r
+ * 0b0..DMA is not used for the transmit function.\r
+ * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)\r
+#define USART_FIFOCFG_DMARX_MASK (0x2000U)\r
+#define USART_FIFOCFG_DMARX_SHIFT (13U)\r
+/*! DMARX - DMA configuration for receive.\r
+ * 0b0..DMA is not used for the receive function.\r
+ * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled.\r
+ */\r
+#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)\r
+#define USART_FIFOCFG_WAKETX_MASK (0x4000U)\r
+#define USART_FIFOCFG_WAKETX_SHIFT (14U)\r
+/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled.\r
+ */\r
+#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)\r
+#define USART_FIFOCFG_WAKERX_MASK (0x8000U)\r
+#define USART_FIFOCFG_WAKERX_SHIFT (15U)\r
+/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.\r
+ * 0b0..Only enabled interrupts will wake up the device form reduced power modes.\r
+ * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled.\r
+ */\r
+#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)\r
+#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)\r
+#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)\r
+#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)\r
+#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)\r
+#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)\r
+#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)\r
+#define USART_FIFOCFG_POPDBG_MASK (0x40000U)\r
+#define USART_FIFOCFG_POPDBG_SHIFT (18U)\r
+/*! POPDBG - Pop FIFO for debug reads.\r
+ * 0b0..Debug reads of the FIFO do not pop the FIFO.\r
+ * 0b1..A debug read will cause the FIFO to pop.\r
+ */\r
+#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOSTAT - FIFO status register. */\r
+/*! @{ */\r
+#define USART_FIFOSTAT_TXERR_MASK (0x1U)\r
+#define USART_FIFOSTAT_TXERR_SHIFT (0U)\r
+#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)\r
+#define USART_FIFOSTAT_RXERR_MASK (0x2U)\r
+#define USART_FIFOSTAT_RXERR_SHIFT (1U)\r
+#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)\r
+#define USART_FIFOSTAT_PERINT_MASK (0x8U)\r
+#define USART_FIFOSTAT_PERINT_SHIFT (3U)\r
+#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)\r
+#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)\r
+#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)\r
+#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)\r
+#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)\r
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)\r
+#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)\r
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)\r
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)\r
+#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)\r
+#define USART_FIFOSTAT_RXFULL_MASK (0x80U)\r
+#define USART_FIFOSTAT_RXFULL_SHIFT (7U)\r
+#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)\r
+#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)\r
+#define USART_FIFOSTAT_TXLVL_SHIFT (8U)\r
+#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)\r
+#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)\r
+#define USART_FIFOSTAT_RXLVL_SHIFT (16U)\r
+#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */\r
+/*! @{ */\r
+#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)\r
+#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)\r
+/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set.\r
+ * 0b0..Transmit FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register.\r
+ */\r
+#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)\r
+#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)\r
+#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)\r
+/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set.\r
+ * 0b0..Receive FIFO level does not generate a FIFO level trigger.\r
+ * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register.\r
+ */\r
+#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)\r
+#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)\r
+#define USART_FIFOTRIG_TXLVL_SHIFT (8U)\r
+#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)\r
+#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)\r
+#define USART_FIFOTRIG_RXLVL_SHIFT (16U)\r
+#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */\r
+/*! @{ */\r
+#define USART_FIFOINTENSET_TXERR_MASK (0x1U)\r
+#define USART_FIFOINTENSET_TXERR_SHIFT (0U)\r
+/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a transmit error.\r
+ * 0b1..An interrupt will be generated when a transmit error occurs.\r
+ */\r
+#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)\r
+#define USART_FIFOINTENSET_RXERR_MASK (0x2U)\r
+#define USART_FIFOINTENSET_RXERR_SHIFT (1U)\r
+/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register.\r
+ * 0b0..No interrupt will be generated for a receive error.\r
+ * 0b1..An interrupt will be generated when a receive error occurs.\r
+ */\r
+#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)\r
+#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)\r
+#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)\r
+/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the TX FIFO level.\r
+ * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register.\r
+ */\r
+#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)\r
+#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)\r
+#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)\r
+/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register.\r
+ * 0b0..No interrupt will be generated based on the RX FIFO level.\r
+ * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register.\r
+ */\r
+#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */\r
+/*! @{ */\r
+#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)\r
+#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)\r
+#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)\r
+#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)\r
+#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)\r
+#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)\r
+#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)\r
+#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)\r
+#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)\r
+#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)\r
+#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)\r
+#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */\r
+/*! @{ */\r
+#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)\r
+#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)\r
+#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)\r
+#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)\r
+#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)\r
+#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)\r
+#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)\r
+#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)\r
+#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)\r
+#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)\r
+#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)\r
+#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)\r
+#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)\r
+#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)\r
+#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFOWR - FIFO write data. */\r
+/*! @{ */\r
+#define USART_FIFOWR_TXDATA_MASK (0x1FFU)\r
+#define USART_FIFOWR_TXDATA_SHIFT (0U)\r
+#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORD - FIFO read data. */\r
+/*! @{ */\r
+#define USART_FIFORD_RXDATA_MASK (0x1FFU)\r
+#define USART_FIFORD_RXDATA_SHIFT (0U)\r
+#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)\r
+#define USART_FIFORD_FRAMERR_MASK (0x2000U)\r
+#define USART_FIFORD_FRAMERR_SHIFT (13U)\r
+#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)\r
+#define USART_FIFORD_PARITYERR_MASK (0x4000U)\r
+#define USART_FIFORD_PARITYERR_SHIFT (14U)\r
+#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)\r
+#define USART_FIFORD_RXNOISE_MASK (0x8000U)\r
+#define USART_FIFORD_RXNOISE_SHIFT (15U)\r
+#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)\r
+/*! @} */\r
+\r
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */\r
+/*! @{ */\r
+#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)\r
+#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)\r
+#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)\r
+#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)\r
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)\r
+#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)\r
+#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)\r
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)\r
+#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)\r
+#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)\r
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)\r
+#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ID - Peripheral identification register. */\r
+/*! @{ */\r
+#define USART_ID_APERTURE_MASK (0xFFU)\r
+#define USART_ID_APERTURE_SHIFT (0U)\r
+#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)\r
+#define USART_ID_MINOR_REV_MASK (0xF00U)\r
+#define USART_ID_MINOR_REV_SHIFT (8U)\r
+#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)\r
+#define USART_ID_MAJOR_REV_MASK (0xF000U)\r
+#define USART_ID_MAJOR_REV_SHIFT (12U)\r
+#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)\r
+#define USART_ID_ID_MASK (0xFFFF0000U)\r
+#define USART_ID_ID_SHIFT (16U)\r
+#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USART_Register_Masks */\r
+\r
+\r
+/* USART - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral USART0 base address */\r
+ #define USART0_BASE (0x50086000u)\r
+ /** Peripheral USART0 base address */\r
+ #define USART0_BASE_NS (0x40086000u)\r
+ /** Peripheral USART0 base pointer */\r
+ #define USART0 ((USART_Type *)USART0_BASE)\r
+ /** Peripheral USART0 base pointer */\r
+ #define USART0_NS ((USART_Type *)USART0_BASE_NS)\r
+ /** Peripheral USART1 base address */\r
+ #define USART1_BASE (0x50087000u)\r
+ /** Peripheral USART1 base address */\r
+ #define USART1_BASE_NS (0x40087000u)\r
+ /** Peripheral USART1 base pointer */\r
+ #define USART1 ((USART_Type *)USART1_BASE)\r
+ /** Peripheral USART1 base pointer */\r
+ #define USART1_NS ((USART_Type *)USART1_BASE_NS)\r
+ /** Peripheral USART2 base address */\r
+ #define USART2_BASE (0x50088000u)\r
+ /** Peripheral USART2 base address */\r
+ #define USART2_BASE_NS (0x40088000u)\r
+ /** Peripheral USART2 base pointer */\r
+ #define USART2 ((USART_Type *)USART2_BASE)\r
+ /** Peripheral USART2 base pointer */\r
+ #define USART2_NS ((USART_Type *)USART2_BASE_NS)\r
+ /** Peripheral USART3 base address */\r
+ #define USART3_BASE (0x50089000u)\r
+ /** Peripheral USART3 base address */\r
+ #define USART3_BASE_NS (0x40089000u)\r
+ /** Peripheral USART3 base pointer */\r
+ #define USART3 ((USART_Type *)USART3_BASE)\r
+ /** Peripheral USART3 base pointer */\r
+ #define USART3_NS ((USART_Type *)USART3_BASE_NS)\r
+ /** Peripheral USART4 base address */\r
+ #define USART4_BASE (0x5008A000u)\r
+ /** Peripheral USART4 base address */\r
+ #define USART4_BASE_NS (0x4008A000u)\r
+ /** Peripheral USART4 base pointer */\r
+ #define USART4 ((USART_Type *)USART4_BASE)\r
+ /** Peripheral USART4 base pointer */\r
+ #define USART4_NS ((USART_Type *)USART4_BASE_NS)\r
+ /** Peripheral USART5 base address */\r
+ #define USART5_BASE (0x50096000u)\r
+ /** Peripheral USART5 base address */\r
+ #define USART5_BASE_NS (0x40096000u)\r
+ /** Peripheral USART5 base pointer */\r
+ #define USART5 ((USART_Type *)USART5_BASE)\r
+ /** Peripheral USART5 base pointer */\r
+ #define USART5_NS ((USART_Type *)USART5_BASE_NS)\r
+ /** Peripheral USART6 base address */\r
+ #define USART6_BASE (0x50097000u)\r
+ /** Peripheral USART6 base address */\r
+ #define USART6_BASE_NS (0x40097000u)\r
+ /** Peripheral USART6 base pointer */\r
+ #define USART6 ((USART_Type *)USART6_BASE)\r
+ /** Peripheral USART6 base pointer */\r
+ #define USART6_NS ((USART_Type *)USART6_BASE_NS)\r
+ /** Peripheral USART7 base address */\r
+ #define USART7_BASE (0x50098000u)\r
+ /** Peripheral USART7 base address */\r
+ #define USART7_BASE_NS (0x40098000u)\r
+ /** Peripheral USART7 base pointer */\r
+ #define USART7 ((USART_Type *)USART7_BASE)\r
+ /** Peripheral USART7 base pointer */\r
+ #define USART7_NS ((USART_Type *)USART7_BASE_NS)\r
+ /** Array initializer of USART peripheral base addresses */\r
+ #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }\r
+ /** Array initializer of USART peripheral base pointers */\r
+ #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }\r
+ /** Array initializer of USART peripheral base addresses */\r
+ #define USART_BASE_ADDRS_NS { USART0_BASE_NS, USART1_BASE_NS, USART2_BASE_NS, USART3_BASE_NS, USART4_BASE_NS, USART5_BASE_NS, USART6_BASE_NS, USART7_BASE_NS }\r
+ /** Array initializer of USART peripheral base pointers */\r
+ #define USART_BASE_PTRS_NS { USART0_NS, USART1_NS, USART2_NS, USART3_NS, USART4_NS, USART5_NS, USART6_NS, USART7_NS }\r
+#else\r
+ /** Peripheral USART0 base address */\r
+ #define USART0_BASE (0x40086000u)\r
+ /** Peripheral USART0 base pointer */\r
+ #define USART0 ((USART_Type *)USART0_BASE)\r
+ /** Peripheral USART1 base address */\r
+ #define USART1_BASE (0x40087000u)\r
+ /** Peripheral USART1 base pointer */\r
+ #define USART1 ((USART_Type *)USART1_BASE)\r
+ /** Peripheral USART2 base address */\r
+ #define USART2_BASE (0x40088000u)\r
+ /** Peripheral USART2 base pointer */\r
+ #define USART2 ((USART_Type *)USART2_BASE)\r
+ /** Peripheral USART3 base address */\r
+ #define USART3_BASE (0x40089000u)\r
+ /** Peripheral USART3 base pointer */\r
+ #define USART3 ((USART_Type *)USART3_BASE)\r
+ /** Peripheral USART4 base address */\r
+ #define USART4_BASE (0x4008A000u)\r
+ /** Peripheral USART4 base pointer */\r
+ #define USART4 ((USART_Type *)USART4_BASE)\r
+ /** Peripheral USART5 base address */\r
+ #define USART5_BASE (0x40096000u)\r
+ /** Peripheral USART5 base pointer */\r
+ #define USART5 ((USART_Type *)USART5_BASE)\r
+ /** Peripheral USART6 base address */\r
+ #define USART6_BASE (0x40097000u)\r
+ /** Peripheral USART6 base pointer */\r
+ #define USART6 ((USART_Type *)USART6_BASE)\r
+ /** Peripheral USART7 base address */\r
+ #define USART7_BASE (0x40098000u)\r
+ /** Peripheral USART7 base pointer */\r
+ #define USART7 ((USART_Type *)USART7_BASE)\r
+ /** Array initializer of USART peripheral base addresses */\r
+ #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE }\r
+ /** Array initializer of USART peripheral base pointers */\r
+ #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 }\r
+#endif\r
+/** Interrupt vectors for the USART peripheral type */\r
+#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USART_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USB Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USB - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */\r
+ __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */\r
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */\r
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */\r
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */\r
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */\r
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */\r
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */\r
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */\r
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */\r
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */\r
+ uint8_t RESERVED_0[8];\r
+ __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */\r
+} USB_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USB Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USB_Register_Masks USB Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name DEVCMDSTAT - USB Device Command/Status register */\r
+/*! @{ */\r
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)\r
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)\r
+#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)\r
+#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)\r
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)\r
+#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)\r
+#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)\r
+#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)\r
+#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)\r
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)\r
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)\r
+/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:\r
+ * 0b0..USB_NEEDCLK has normal function.\r
+ * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend.\r
+ */\r
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)\r
+#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)\r
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)\r
+/*! LPM_SUP - LPM Supported:\r
+ * 0b0..LPM not supported.\r
+ * 0b1..LPM supported.\r
+ */\r
+#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)\r
+/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)\r
+/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)\r
+/*! INTONNAK_CO - Interrupt on NAK for control OUT EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)\r
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)\r
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)\r
+/*! INTONNAK_CI - Interrupt on NAK for control IN EP\r
+ * 0b0..Only acknowledged packets generate an interrupt\r
+ * 0b1..Both acknowledged and NAKed packets generate interrupts.\r
+ */\r
+#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)\r
+#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)\r
+#define USB_DEVCMDSTAT_DCON_SHIFT (16U)\r
+#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)\r
+#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)\r
+#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)\r
+#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)\r
+#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)\r
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)\r
+#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)\r
+#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)\r
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)\r
+#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)\r
+#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)\r
+#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)\r
+#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)\r
+#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)\r
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)\r
+#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)\r
+#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)\r
+#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)\r
+#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)\r
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)\r
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)\r
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name INFO - USB Info register */\r
+/*! @{ */\r
+#define USB_INFO_FRAME_NR_MASK (0x7FFU)\r
+#define USB_INFO_FRAME_NR_SHIFT (0U)\r
+#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)\r
+#define USB_INFO_ERR_CODE_MASK (0x7800U)\r
+#define USB_INFO_ERR_CODE_SHIFT (11U)\r
+/*! ERR_CODE - The error code which last occurred:\r
+ * 0b0000..No error\r
+ * 0b0001..PID encoding error\r
+ * 0b0010..PID unknown\r
+ * 0b0011..Packet unexpected\r
+ * 0b0100..Token CRC error\r
+ * 0b0101..Data CRC error\r
+ * 0b0110..Time out\r
+ * 0b0111..Babble\r
+ * 0b1000..Truncated EOP\r
+ * 0b1001..Sent/Received NAK\r
+ * 0b1010..Sent Stall\r
+ * 0b1011..Overrun\r
+ * 0b1100..Sent empty packet\r
+ * 0b1101..Bitstuff error\r
+ * 0b1110..Sync error\r
+ * 0b1111..Wrong data toggle\r
+ */\r
+#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)\r
+#define USB_INFO_MINREV_MASK (0xFF0000U)\r
+#define USB_INFO_MINREV_SHIFT (16U)\r
+#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)\r
+#define USB_INFO_MAJREV_MASK (0xFF000000U)\r
+#define USB_INFO_MAJREV_SHIFT (24U)\r
+#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPLISTSTART - USB EP Command/Status List start address */\r
+/*! @{ */\r
+#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)\r
+#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)\r
+#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATABUFSTART - USB Data buffer start address */\r
+/*! @{ */\r
+#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)\r
+#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)\r
+#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name LPM - USB Link Power Management register */\r
+/*! @{ */\r
+#define USB_LPM_HIRD_HW_MASK (0xFU)\r
+#define USB_LPM_HIRD_HW_SHIFT (0U)\r
+#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)\r
+#define USB_LPM_HIRD_SW_MASK (0xF0U)\r
+#define USB_LPM_HIRD_SW_SHIFT (4U)\r
+#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)\r
+#define USB_LPM_DATA_PENDING_MASK (0x100U)\r
+#define USB_LPM_DATA_PENDING_SHIFT (8U)\r
+#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPSKIP - USB Endpoint skip */\r
+/*! @{ */\r
+#define USB_EPSKIP_SKIP_MASK (0x3FFU)\r
+#define USB_EPSKIP_SKIP_SHIFT (0U)\r
+#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPINUSE - USB Endpoint Buffer in use */\r
+/*! @{ */\r
+#define USB_EPINUSE_BUF_MASK (0x3FCU)\r
+#define USB_EPINUSE_BUF_SHIFT (2U)\r
+#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */\r
+/*! @{ */\r
+#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)\r
+#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)\r
+#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - USB interrupt status register */\r
+/*! @{ */\r
+#define USB_INTSTAT_EP0OUT_MASK (0x1U)\r
+#define USB_INTSTAT_EP0OUT_SHIFT (0U)\r
+#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)\r
+#define USB_INTSTAT_EP0IN_MASK (0x2U)\r
+#define USB_INTSTAT_EP0IN_SHIFT (1U)\r
+#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)\r
+#define USB_INTSTAT_EP1OUT_MASK (0x4U)\r
+#define USB_INTSTAT_EP1OUT_SHIFT (2U)\r
+#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)\r
+#define USB_INTSTAT_EP1IN_MASK (0x8U)\r
+#define USB_INTSTAT_EP1IN_SHIFT (3U)\r
+#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)\r
+#define USB_INTSTAT_EP2OUT_MASK (0x10U)\r
+#define USB_INTSTAT_EP2OUT_SHIFT (4U)\r
+#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)\r
+#define USB_INTSTAT_EP2IN_MASK (0x20U)\r
+#define USB_INTSTAT_EP2IN_SHIFT (5U)\r
+#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)\r
+#define USB_INTSTAT_EP3OUT_MASK (0x40U)\r
+#define USB_INTSTAT_EP3OUT_SHIFT (6U)\r
+#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)\r
+#define USB_INTSTAT_EP3IN_MASK (0x80U)\r
+#define USB_INTSTAT_EP3IN_SHIFT (7U)\r
+#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)\r
+#define USB_INTSTAT_EP4OUT_MASK (0x100U)\r
+#define USB_INTSTAT_EP4OUT_SHIFT (8U)\r
+#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)\r
+#define USB_INTSTAT_EP4IN_MASK (0x200U)\r
+#define USB_INTSTAT_EP4IN_SHIFT (9U)\r
+#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)\r
+#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)\r
+#define USB_INTSTAT_FRAME_INT_SHIFT (30U)\r
+#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)\r
+#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)\r
+#define USB_INTSTAT_DEV_INT_SHIFT (31U)\r
+#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTEN - USB interrupt enable register */\r
+/*! @{ */\r
+#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)\r
+#define USB_INTEN_EP_INT_EN_SHIFT (0U)\r
+#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)\r
+#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)\r
+#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)\r
+#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)\r
+#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)\r
+#define USB_INTEN_DEV_INT_EN_SHIFT (31U)\r
+#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSETSTAT - USB set interrupt status register */\r
+/*! @{ */\r
+#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)\r
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)\r
+#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)\r
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)\r
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)\r
+#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)\r
+#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)\r
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)\r
+#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPTOGGLE - USB Endpoint toggle register */\r
+/*! @{ */\r
+#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)\r
+#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)\r
+#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USB_Register_Masks */\r
+\r
+\r
+/* USB - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral USB0 base address */\r
+ #define USB0_BASE (0x50084000u)\r
+ /** Peripheral USB0 base address */\r
+ #define USB0_BASE_NS (0x40084000u)\r
+ /** Peripheral USB0 base pointer */\r
+ #define USB0 ((USB_Type *)USB0_BASE)\r
+ /** Peripheral USB0 base pointer */\r
+ #define USB0_NS ((USB_Type *)USB0_BASE_NS)\r
+ /** Array initializer of USB peripheral base addresses */\r
+ #define USB_BASE_ADDRS { USB0_BASE }\r
+ /** Array initializer of USB peripheral base pointers */\r
+ #define USB_BASE_PTRS { USB0 }\r
+ /** Array initializer of USB peripheral base addresses */\r
+ #define USB_BASE_ADDRS_NS { USB0_BASE_NS }\r
+ /** Array initializer of USB peripheral base pointers */\r
+ #define USB_BASE_PTRS_NS { USB0_NS }\r
+#else\r
+ /** Peripheral USB0 base address */\r
+ #define USB0_BASE (0x40084000u)\r
+ /** Peripheral USB0 base pointer */\r
+ #define USB0 ((USB_Type *)USB0_BASE)\r
+ /** Array initializer of USB peripheral base addresses */\r
+ #define USB_BASE_ADDRS { USB0_BASE }\r
+ /** Array initializer of USB peripheral base pointers */\r
+ #define USB_BASE_PTRS { USB0 }\r
+#endif\r
+/** Interrupt vectors for the USB peripheral type */\r
+#define USB_IRQS { USB0_IRQn }\r
+#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USB_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBFSH Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBFSH - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */\r
+ __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */\r
+ __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */\r
+ __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */\r
+ __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */\r
+ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */\r
+ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */\r
+ __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */\r
+ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */\r
+ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */\r
+ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */\r
+ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */\r
+ __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */\r
+ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */\r
+ __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */\r
+ __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */\r
+ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */\r
+ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */\r
+ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */\r
+ __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */\r
+ __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */\r
+ __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */\r
+} USBFSH_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBFSH Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */\r
+/*! @{ */\r
+#define USBFSH_HCREVISION_REV_MASK (0xFFU)\r
+#define USBFSH_HCREVISION_REV_SHIFT (0U)\r
+#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCONTROL - Defines the operating modes of the HC */\r
+/*! @{ */\r
+#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)\r
+#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)\r
+#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)\r
+#define USBFSH_HCCONTROL_PLE_MASK (0x4U)\r
+#define USBFSH_HCCONTROL_PLE_SHIFT (2U)\r
+#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)\r
+#define USBFSH_HCCONTROL_IE_MASK (0x8U)\r
+#define USBFSH_HCCONTROL_IE_SHIFT (3U)\r
+#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)\r
+#define USBFSH_HCCONTROL_CLE_MASK (0x10U)\r
+#define USBFSH_HCCONTROL_CLE_SHIFT (4U)\r
+#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)\r
+#define USBFSH_HCCONTROL_BLE_MASK (0x20U)\r
+#define USBFSH_HCCONTROL_BLE_SHIFT (5U)\r
+#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)\r
+#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)\r
+#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)\r
+#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)\r
+#define USBFSH_HCCONTROL_IR_MASK (0x100U)\r
+#define USBFSH_HCCONTROL_IR_SHIFT (8U)\r
+#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)\r
+#define USBFSH_HCCONTROL_RWC_MASK (0x200U)\r
+#define USBFSH_HCCONTROL_RWC_SHIFT (9U)\r
+#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)\r
+#define USBFSH_HCCONTROL_RWE_MASK (0x400U)\r
+#define USBFSH_HCCONTROL_RWE_SHIFT (10U)\r
+#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */\r
+/*! @{ */\r
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)\r
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)\r
+#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)\r
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)\r
+#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)\r
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)\r
+#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)\r
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)\r
+#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)\r
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)\r
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)\r
+#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */\r
+/*! @{ */\r
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)\r
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)\r
+#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)\r
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)\r
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)\r
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)\r
+#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)\r
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)\r
+#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)\r
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)\r
+#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)\r
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)\r
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)\r
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)\r
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)\r
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)\r
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)\r
+#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */\r
+/*! @{ */\r
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)\r
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)\r
+#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)\r
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)\r
+#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)\r
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)\r
+#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)\r
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)\r
+#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)\r
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)\r
+#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)\r
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)\r
+#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)\r
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)\r
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)\r
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)\r
+#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)\r
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)\r
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)\r
+#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */\r
+/*! @{ */\r
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)\r
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)\r
+#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)\r
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)\r
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)\r
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)\r
+#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)\r
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)\r
+#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)\r
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)\r
+#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)\r
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)\r
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)\r
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)\r
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)\r
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)\r
+#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)\r
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)\r
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)\r
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */\r
+/*! @{ */\r
+#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)\r
+#define USBFSH_HCHCCA_HCCA_SHIFT (8U)\r
+#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */\r
+/*! @{ */\r
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)\r
+#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */\r
+/*! @{ */\r
+#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)\r
+#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */\r
+/*! @{ */\r
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)\r
+#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */\r
+/*! @{ */\r
+#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)\r
+#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */\r
+/*! @{ */\r
+#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)\r
+#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */\r
+/*! @{ */\r
+#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)\r
+#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)\r
+#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */\r
+/*! @{ */\r
+#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)\r
+#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)\r
+#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)\r
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)\r
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)\r
+#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)\r
+#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)\r
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)\r
+#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */\r
+/*! @{ */\r
+#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)\r
+#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)\r
+#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)\r
+#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)\r
+#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)\r
+#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */\r
+/*! @{ */\r
+#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)\r
+#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)\r
+#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */\r
+/*! @{ */\r
+#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)\r
+#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)\r
+#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */\r
+/*! @{ */\r
+#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)\r
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)\r
+#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */\r
+/*! @{ */\r
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)\r
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)\r
+#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)\r
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)\r
+#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)\r
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)\r
+#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)\r
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)\r
+#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)\r
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)\r
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)\r
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)\r
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)\r
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)\r
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)\r
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */\r
+/*! @{ */\r
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)\r
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)\r
+#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)\r
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)\r
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)\r
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHSTATUS - This register is divided into two parts */\r
+/*! @{ */\r
+#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)\r
+#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)\r
+#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)\r
+#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)\r
+#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)\r
+#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)\r
+#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)\r
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)\r
+#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)\r
+#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)\r
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)\r
+#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)\r
+#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)\r
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)\r
+#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)\r
+#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)\r
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)\r
+#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */\r
+/*! @{ */\r
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)\r
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)\r
+#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)\r
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)\r
+#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)\r
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)\r
+#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)\r
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)\r
+#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)\r
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)\r
+#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)\r
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)\r
+#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)\r
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)\r
+#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)\r
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)\r
+#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)\r
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)\r
+#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)\r
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)\r
+#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)\r
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)\r
+#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)\r
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)\r
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)\r
+#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */\r
+/*! @{ */\r
+#define USBFSH_PORTMODE_ID_MASK (0x1U)\r
+#define USBFSH_PORTMODE_ID_SHIFT (0U)\r
+#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)\r
+#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)\r
+#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)\r
+#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)\r
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)\r
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)\r
+#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBFSH_Register_Masks */\r
+\r
+\r
+/* USBFSH - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral USBFSH base address */\r
+ #define USBFSH_BASE (0x500A2000u)\r
+ /** Peripheral USBFSH base address */\r
+ #define USBFSH_BASE_NS (0x400A2000u)\r
+ /** Peripheral USBFSH base pointer */\r
+ #define USBFSH ((USBFSH_Type *)USBFSH_BASE)\r
+ /** Peripheral USBFSH base pointer */\r
+ #define USBFSH_NS ((USBFSH_Type *)USBFSH_BASE_NS)\r
+ /** Array initializer of USBFSH peripheral base addresses */\r
+ #define USBFSH_BASE_ADDRS { USBFSH_BASE }\r
+ /** Array initializer of USBFSH peripheral base pointers */\r
+ #define USBFSH_BASE_PTRS { USBFSH }\r
+ /** Array initializer of USBFSH peripheral base addresses */\r
+ #define USBFSH_BASE_ADDRS_NS { USBFSH_BASE_NS }\r
+ /** Array initializer of USBFSH peripheral base pointers */\r
+ #define USBFSH_BASE_PTRS_NS { USBFSH_NS }\r
+#else\r
+ /** Peripheral USBFSH base address */\r
+ #define USBFSH_BASE (0x400A2000u)\r
+ /** Peripheral USBFSH base pointer */\r
+ #define USBFSH ((USBFSH_Type *)USBFSH_BASE)\r
+ /** Array initializer of USBFSH peripheral base addresses */\r
+ #define USBFSH_BASE_ADDRS { USBFSH_BASE }\r
+ /** Array initializer of USBFSH peripheral base pointers */\r
+ #define USBFSH_BASE_PTRS { USBFSH }\r
+#endif\r
+/** Interrupt vectors for the USBFSH peripheral type */\r
+#define USBFSH_IRQS { USB0_IRQn }\r
+#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBFSH_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSD Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBHSD - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */\r
+ __I uint32_t INFO; /**< USB Info register, offset: 0x4 */\r
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */\r
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */\r
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */\r
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */\r
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */\r
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */\r
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */\r
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */\r
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */\r
+ uint8_t RESERVED_0[8];\r
+ __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */\r
+ uint8_t RESERVED_1[4];\r
+ __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */\r
+} USBHSD_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSD Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name DEVCMDSTAT - USB Device Command/Status register */\r
+/*! @{ */\r
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)\r
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)\r
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)\r
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)\r
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)\r
+#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)\r
+#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)\r
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)\r
+#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)\r
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)\r
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)\r
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)\r
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)\r
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)\r
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)\r
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)\r
+#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)\r
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)\r
+#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)\r
+#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)\r
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)\r
+#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)\r
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)\r
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)\r
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)\r
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)\r
+#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)\r
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)\r
+#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)\r
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)\r
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)\r
+#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)\r
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)\r
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)\r
+#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)\r
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)\r
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)\r
+#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)\r
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)\r
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)\r
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)\r
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)\r
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)\r
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INFO - USB Info register */\r
+/*! @{ */\r
+#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)\r
+#define USBHSD_INFO_FRAME_NR_SHIFT (0U)\r
+#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)\r
+#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)\r
+#define USBHSD_INFO_ERR_CODE_SHIFT (11U)\r
+#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)\r
+#define USBHSD_INFO_Minrev_MASK (0xFF0000U)\r
+#define USBHSD_INFO_Minrev_SHIFT (16U)\r
+#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)\r
+#define USBHSD_INFO_Majrev_MASK (0xFF000000U)\r
+#define USBHSD_INFO_Majrev_SHIFT (24U)\r
+#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPLISTSTART - USB EP Command/Status List start address */\r
+/*! @{ */\r
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)\r
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)\r
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)\r
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)\r
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)\r
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATABUFSTART - USB Data buffer start address */\r
+/*! @{ */\r
+#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU)\r
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U)\r
+#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name LPM - USB Link Power Management register */\r
+/*! @{ */\r
+#define USBHSD_LPM_HIRD_HW_MASK (0xFU)\r
+#define USBHSD_LPM_HIRD_HW_SHIFT (0U)\r
+#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)\r
+#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)\r
+#define USBHSD_LPM_HIRD_SW_SHIFT (4U)\r
+#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)\r
+#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)\r
+#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)\r
+#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPSKIP - USB Endpoint skip */\r
+/*! @{ */\r
+#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)\r
+#define USBHSD_EPSKIP_SKIP_SHIFT (0U)\r
+#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPINUSE - USB Endpoint Buffer in use */\r
+/*! @{ */\r
+#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)\r
+#define USBHSD_EPINUSE_BUF_SHIFT (2U)\r
+#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */\r
+/*! @{ */\r
+#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)\r
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)\r
+#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSTAT - USB interrupt status register */\r
+/*! @{ */\r
+#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)\r
+#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)\r
+#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)\r
+#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)\r
+#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)\r
+#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)\r
+#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)\r
+#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)\r
+#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)\r
+#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)\r
+#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)\r
+#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)\r
+#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)\r
+#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)\r
+#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)\r
+#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)\r
+#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)\r
+#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)\r
+#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)\r
+#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)\r
+#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)\r
+#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)\r
+#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)\r
+#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)\r
+#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)\r
+#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)\r
+#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)\r
+#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)\r
+#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)\r
+#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)\r
+#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)\r
+#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)\r
+#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)\r
+#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)\r
+#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)\r
+#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)\r
+#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)\r
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)\r
+#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)\r
+#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)\r
+#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)\r
+#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTEN - USB interrupt enable register */\r
+/*! @{ */\r
+#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)\r
+#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)\r
+#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)\r
+#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)\r
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)\r
+#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)\r
+#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)\r
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)\r
+#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)\r
+/*! @} */\r
+\r
+/*! @name INTSETSTAT - USB set interrupt status register */\r
+/*! @{ */\r
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)\r
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)\r
+#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)\r
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)\r
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)\r
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)\r
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)\r
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)\r
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)\r
+/*! @} */\r
+\r
+/*! @name EPTOGGLE - USB Endpoint toggle register */\r
+/*! @{ */\r
+#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)\r
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)\r
+#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ULPIDEBUG - UTMI/ULPI debug register */\r
+/*! @{ */\r
+#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU)\r
+#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U)\r
+#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)\r
+#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U)\r
+#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U)\r
+#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)\r
+#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U)\r
+#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U)\r
+#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)\r
+#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U)\r
+#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U)\r
+#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)\r
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U)\r
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U)\r
+#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)\r
+#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U)\r
+#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U)\r
+#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSD_Register_Masks */\r
+\r
+\r
+/* USBHSD - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral USBHSD base address */\r
+ #define USBHSD_BASE (0x50094000u)\r
+ /** Peripheral USBHSD base address */\r
+ #define USBHSD_BASE_NS (0x40094000u)\r
+ /** Peripheral USBHSD base pointer */\r
+ #define USBHSD ((USBHSD_Type *)USBHSD_BASE)\r
+ /** Peripheral USBHSD base pointer */\r
+ #define USBHSD_NS ((USBHSD_Type *)USBHSD_BASE_NS)\r
+ /** Array initializer of USBHSD peripheral base addresses */\r
+ #define USBHSD_BASE_ADDRS { USBHSD_BASE }\r
+ /** Array initializer of USBHSD peripheral base pointers */\r
+ #define USBHSD_BASE_PTRS { USBHSD }\r
+ /** Array initializer of USBHSD peripheral base addresses */\r
+ #define USBHSD_BASE_ADDRS_NS { USBHSD_BASE_NS }\r
+ /** Array initializer of USBHSD peripheral base pointers */\r
+ #define USBHSD_BASE_PTRS_NS { USBHSD_NS }\r
+#else\r
+ /** Peripheral USBHSD base address */\r
+ #define USBHSD_BASE (0x40094000u)\r
+ /** Peripheral USBHSD base pointer */\r
+ #define USBHSD ((USBHSD_Type *)USBHSD_BASE)\r
+ /** Array initializer of USBHSD peripheral base addresses */\r
+ #define USBHSD_BASE_ADDRS { USBHSD_BASE }\r
+ /** Array initializer of USBHSD peripheral base pointers */\r
+ #define USBHSD_BASE_PTRS { USBHSD }\r
+#endif\r
+/** Interrupt vectors for the USBHSD peripheral type */\r
+#define USBHSD_IRQS { USB1_IRQn }\r
+#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSD_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSH Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBHSH - Register Layout Typedef */\r
+typedef struct {\r
+ __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */\r
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */\r
+ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */\r
+ __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */\r
+ __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */\r
+ __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */\r
+ __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */\r
+ __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */\r
+ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */\r
+ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */\r
+ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */\r
+ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */\r
+ __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */\r
+ __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */\r
+ __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */\r
+ __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */\r
+ __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */\r
+ __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */\r
+ __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */\r
+ __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */\r
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */\r
+} USBHSH_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBHSH Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */\r
+/*! @{ */\r
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)\r
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)\r
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)\r
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)\r
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)\r
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCSPARAMS - Host Controller Structural Parameters */\r
+/*! @{ */\r
+#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)\r
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)\r
+#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)\r
+#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)\r
+#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)\r
+#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)\r
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)\r
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)\r
+#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name HCCPARAMS - Host Controller Capability Parameters */\r
+/*! @{ */\r
+#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)\r
+#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)\r
+#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)\r
+/*! @} */\r
+\r
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */\r
+/*! @{ */\r
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)\r
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)\r
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)\r
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)\r
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)\r
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)\r
+/*! @} */\r
+\r
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */\r
+/*! @{ */\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)\r
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */\r
+/*! @{ */\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)\r
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */\r
+/*! @{ */\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)\r
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */\r
+/*! @{ */\r
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)\r
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)\r
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBCMD - USB Command register */\r
+/*! @{ */\r
+#define USBHSH_USBCMD_RS_MASK (0x1U)\r
+#define USBHSH_USBCMD_RS_SHIFT (0U)\r
+#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)\r
+#define USBHSH_USBCMD_HCRESET_MASK (0x2U)\r
+#define USBHSH_USBCMD_HCRESET_SHIFT (1U)\r
+#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)\r
+#define USBHSH_USBCMD_FLS_MASK (0xCU)\r
+#define USBHSH_USBCMD_FLS_SHIFT (2U)\r
+#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)\r
+#define USBHSH_USBCMD_LHCR_MASK (0x80U)\r
+#define USBHSH_USBCMD_LHCR_SHIFT (7U)\r
+#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)\r
+#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)\r
+#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)\r
+#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)\r
+#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)\r
+#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)\r
+#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)\r
+#define USBHSH_USBCMD_INT_EN_MASK (0x400U)\r
+#define USBHSH_USBCMD_INT_EN_SHIFT (10U)\r
+#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)\r
+#define USBHSH_USBCMD_HIRD_MASK (0xF000000U)\r
+#define USBHSH_USBCMD_HIRD_SHIFT (24U)\r
+#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)\r
+#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U)\r
+#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U)\r
+#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBSTS - USB Interrupt Status register */\r
+/*! @{ */\r
+#define USBHSH_USBSTS_PCD_MASK (0x4U)\r
+#define USBHSH_USBSTS_PCD_SHIFT (2U)\r
+#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)\r
+#define USBHSH_USBSTS_FLR_MASK (0x8U)\r
+#define USBHSH_USBSTS_FLR_SHIFT (3U)\r
+#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)\r
+#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)\r
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)\r
+#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)\r
+#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)\r
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)\r
+#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)\r
+#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)\r
+#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)\r
+#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)\r
+#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)\r
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)\r
+#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)\r
+/*! @} */\r
+\r
+/*! @name USBINTR - USB Interrupt Enable register */\r
+/*! @{ */\r
+#define USBHSH_USBINTR_PCDE_MASK (0x4U)\r
+#define USBHSH_USBINTR_PCDE_SHIFT (2U)\r
+#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)\r
+#define USBHSH_USBINTR_FLRE_MASK (0x8U)\r
+#define USBHSH_USBINTR_FLRE_SHIFT (3U)\r
+#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)\r
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)\r
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)\r
+#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)\r
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)\r
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)\r
+#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)\r
+#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)\r
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)\r
+#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)\r
+#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)\r
+#define USBHSH_USBINTR_SOF_E_SHIFT (19U)\r
+#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORTSC1 - Port Status and Control register */\r
+/*! @{ */\r
+#define USBHSH_PORTSC1_CCS_MASK (0x1U)\r
+#define USBHSH_PORTSC1_CCS_SHIFT (0U)\r
+#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)\r
+#define USBHSH_PORTSC1_CSC_MASK (0x2U)\r
+#define USBHSH_PORTSC1_CSC_SHIFT (1U)\r
+#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)\r
+#define USBHSH_PORTSC1_PED_MASK (0x4U)\r
+#define USBHSH_PORTSC1_PED_SHIFT (2U)\r
+#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)\r
+#define USBHSH_PORTSC1_PEDC_MASK (0x8U)\r
+#define USBHSH_PORTSC1_PEDC_SHIFT (3U)\r
+#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)\r
+#define USBHSH_PORTSC1_OCA_MASK (0x10U)\r
+#define USBHSH_PORTSC1_OCA_SHIFT (4U)\r
+#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)\r
+#define USBHSH_PORTSC1_OCC_MASK (0x20U)\r
+#define USBHSH_PORTSC1_OCC_SHIFT (5U)\r
+#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)\r
+#define USBHSH_PORTSC1_FPR_MASK (0x40U)\r
+#define USBHSH_PORTSC1_FPR_SHIFT (6U)\r
+#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)\r
+#define USBHSH_PORTSC1_SUSP_MASK (0x80U)\r
+#define USBHSH_PORTSC1_SUSP_SHIFT (7U)\r
+#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)\r
+#define USBHSH_PORTSC1_PR_MASK (0x100U)\r
+#define USBHSH_PORTSC1_PR_SHIFT (8U)\r
+#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)\r
+#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)\r
+#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)\r
+#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)\r
+#define USBHSH_PORTSC1_LS_MASK (0xC00U)\r
+#define USBHSH_PORTSC1_LS_SHIFT (10U)\r
+#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)\r
+#define USBHSH_PORTSC1_PP_MASK (0x1000U)\r
+#define USBHSH_PORTSC1_PP_SHIFT (12U)\r
+#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)\r
+#define USBHSH_PORTSC1_PIC_MASK (0xC000U)\r
+#define USBHSH_PORTSC1_PIC_SHIFT (14U)\r
+#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)\r
+#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)\r
+#define USBHSH_PORTSC1_PTC_SHIFT (16U)\r
+#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)\r
+#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)\r
+#define USBHSH_PORTSC1_PSPD_SHIFT (20U)\r
+#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)\r
+#define USBHSH_PORTSC1_WOO_MASK (0x400000U)\r
+#define USBHSH_PORTSC1_WOO_SHIFT (22U)\r
+#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)\r
+#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)\r
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)\r
+#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)\r
+#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)\r
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)\r
+#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)\r
+/*! @} */\r
+\r
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */\r
+/*! @{ */\r
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)\r
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */\r
+/*! @{ */\r
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)\r
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */\r
+/*! @{ */\r
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)\r
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */\r
+/*! @{ */\r
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)\r
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)\r
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */\r
+/*! @{ */\r
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)\r
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)\r
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)\r
+/*! @} */\r
+\r
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */\r
+/*! @{ */\r
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)\r
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)\r
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)\r
+/*! @} */\r
+\r
+/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */\r
+/*! @{ */\r
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU)\r
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U)\r
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)\r
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U)\r
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U)\r
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)\r
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U)\r
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U)\r
+#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)\r
+/*! @} */\r
+\r
+/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */\r
+/*! @{ */\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)\r
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)\r
+/*! @} */\r
+\r
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */\r
+/*! @{ */\r
+#define USBHSH_PORTMODE_ID0_MASK (0x1U)\r
+#define USBHSH_PORTMODE_ID0_SHIFT (0U)\r
+#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)\r
+#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U)\r
+#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U)\r
+#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)\r
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)\r
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)\r
+#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)\r
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)\r
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)\r
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)\r
+#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)\r
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)\r
+#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSH_Register_Masks */\r
+\r
+\r
+/* USBHSH - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral USBHSH base address */\r
+ #define USBHSH_BASE (0x500A3000u)\r
+ /** Peripheral USBHSH base address */\r
+ #define USBHSH_BASE_NS (0x400A3000u)\r
+ /** Peripheral USBHSH base pointer */\r
+ #define USBHSH ((USBHSH_Type *)USBHSH_BASE)\r
+ /** Peripheral USBHSH base pointer */\r
+ #define USBHSH_NS ((USBHSH_Type *)USBHSH_BASE_NS)\r
+ /** Array initializer of USBHSH peripheral base addresses */\r
+ #define USBHSH_BASE_ADDRS { USBHSH_BASE }\r
+ /** Array initializer of USBHSH peripheral base pointers */\r
+ #define USBHSH_BASE_PTRS { USBHSH }\r
+ /** Array initializer of USBHSH peripheral base addresses */\r
+ #define USBHSH_BASE_ADDRS_NS { USBHSH_BASE_NS }\r
+ /** Array initializer of USBHSH peripheral base pointers */\r
+ #define USBHSH_BASE_PTRS_NS { USBHSH_NS }\r
+#else\r
+ /** Peripheral USBHSH base address */\r
+ #define USBHSH_BASE (0x400A3000u)\r
+ /** Peripheral USBHSH base pointer */\r
+ #define USBHSH ((USBHSH_Type *)USBHSH_BASE)\r
+ /** Array initializer of USBHSH peripheral base addresses */\r
+ #define USBHSH_BASE_ADDRS { USBHSH_BASE }\r
+ /** Array initializer of USBHSH peripheral base pointers */\r
+ #define USBHSH_BASE_PTRS { USBHSH }\r
+#endif\r
+/** Interrupt vectors for the USBHSH peripheral type */\r
+#define USBHSH_IRQS { USB1_IRQn }\r
+#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBHSH_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBPHY Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** USBPHY - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */\r
+ __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */\r
+ __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */\r
+ __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */\r
+ __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */\r
+ __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */\r
+ __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */\r
+ __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */\r
+ __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */\r
+ __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */\r
+ __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */\r
+ __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */\r
+ __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */\r
+ __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */\r
+ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */\r
+ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */\r
+ __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */\r
+ uint8_t RESERVED_0[12];\r
+ __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */\r
+ __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */\r
+ __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */\r
+ __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */\r
+ uint8_t RESERVED_1[16];\r
+ __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */\r
+ __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */\r
+ __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */\r
+ __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */\r
+ __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */\r
+ uint8_t RESERVED_2[28];\r
+ __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */\r
+ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */\r
+ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */\r
+ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */\r
+ uint8_t RESERVED_3[16];\r
+ __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */\r
+ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */\r
+ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */\r
+ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */\r
+ __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */\r
+ uint8_t RESERVED_4[12];\r
+ __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */\r
+ __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */\r
+ __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */\r
+ __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */\r
+ __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */\r
+ uint8_t RESERVED_5[12];\r
+ __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */\r
+ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */\r
+ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */\r
+ __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */\r
+} USBPHY_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- USBPHY Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup USBPHY_Register_Masks USBPHY Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name PWD - USB PHY Power-Down Register */\r
+/*! @{ */\r
+#define USBPHY_PWD_TXPWDFS_MASK (0x400U)\r
+#define USBPHY_PWD_TXPWDFS_SHIFT (10U)\r
+/*! TXPWDFS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the\r
+ */\r
+#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)\r
+#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)\r
+#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)\r
+/*! TXPWDIBIAS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the\r
+ */\r
+#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)\r
+#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)\r
+#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)\r
+/*! TXPWDV2I\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror\r
+ */\r
+#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)\r
+#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)\r
+#define USBPHY_PWD_RXPWDENV_SHIFT (17U)\r
+/*! RXPWDENV\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)\r
+ */\r
+#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)\r
+#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)\r
+#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)\r
+/*! RXPWD1PT1\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed differential receiver.\r
+ */\r
+#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)\r
+#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)\r
+#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)\r
+/*! RXPWDDIFF\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed differential receive\r
+ */\r
+#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)\r
+#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)\r
+#define USBPHY_PWD_RXPWDRX_SHIFT (20U)\r
+/*! RXPWDRX\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver\r
+ */\r
+#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWD_SET - USB PHY Power-Down Register */\r
+/*! @{ */\r
+#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)\r
+#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)\r
+/*! TXPWDFS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the\r
+ */\r
+#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)\r
+#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)\r
+#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)\r
+/*! TXPWDIBIAS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the\r
+ */\r
+#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)\r
+#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)\r
+#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)\r
+/*! TXPWDV2I\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror\r
+ */\r
+#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)\r
+#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)\r
+#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)\r
+/*! RXPWDENV\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)\r
+ */\r
+#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)\r
+#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)\r
+#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)\r
+/*! RXPWD1PT1\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed differential receiver.\r
+ */\r
+#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)\r
+#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)\r
+#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)\r
+/*! RXPWDDIFF\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed differential receive\r
+ */\r
+#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)\r
+#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)\r
+#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)\r
+/*! RXPWDRX\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver\r
+ */\r
+#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWD_CLR - USB PHY Power-Down Register */\r
+/*! @{ */\r
+#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)\r
+#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)\r
+/*! TXPWDFS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the\r
+ */\r
+#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)\r
+#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)\r
+#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)\r
+/*! TXPWDIBIAS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the\r
+ */\r
+#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)\r
+#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)\r
+#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)\r
+/*! TXPWDV2I\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror\r
+ */\r
+#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)\r
+#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)\r
+#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)\r
+/*! RXPWDENV\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)\r
+ */\r
+#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)\r
+#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)\r
+#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)\r
+/*! RXPWD1PT1\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed differential receiver.\r
+ */\r
+#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)\r
+#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)\r
+#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)\r
+/*! RXPWDDIFF\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed differential receive\r
+ */\r
+#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)\r
+#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)\r
+#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)\r
+/*! RXPWDRX\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver\r
+ */\r
+#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name PWD_TOG - USB PHY Power-Down Register */\r
+/*! @{ */\r
+#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)\r
+#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)\r
+/*! TXPWDFS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the\r
+ */\r
+#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)\r
+#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)\r
+#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)\r
+/*! TXPWDIBIAS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the\r
+ */\r
+#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)\r
+#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)\r
+#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)\r
+/*! TXPWDV2I\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror\r
+ */\r
+#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)\r
+#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)\r
+#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)\r
+/*! RXPWDENV\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)\r
+ */\r
+#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)\r
+#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)\r
+#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)\r
+/*! RXPWD1PT1\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB full-speed differential receiver.\r
+ */\r
+#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)\r
+#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)\r
+#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)\r
+/*! RXPWDDIFF\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the USB high-speed differential receive\r
+ */\r
+#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)\r
+#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)\r
+#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)\r
+/*! RXPWDRX\r
+ * 0b0..Normal operation.\r
+ * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver\r
+ */\r
+#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)\r
+/*! @} */\r
+\r
+/*! @name TX - USB PHY Transmitter Control Register */\r
+/*! @{ */\r
+#define USBPHY_TX_D_CAL_MASK (0xFU)\r
+#define USBPHY_TX_D_CAL_SHIFT (0U)\r
+/*! D_CAL\r
+ * 0b0000..Maximum current, approximately 19% above nominal.\r
+ * 0b0111..Nominal\r
+ * 0b1111..Minimum current, approximately 19% below nominal.\r
+ */\r
+#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)\r
+#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)\r
+#define USBPHY_TX_TXCAL45DM_SHIFT (8U)\r
+#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)\r
+#define USBPHY_TX_TXENCAL45DN_MASK (0x2000U)\r
+#define USBPHY_TX_TXENCAL45DN_SHIFT (13U)\r
+#define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK)\r
+#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)\r
+#define USBPHY_TX_TXCAL45DP_SHIFT (16U)\r
+#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)\r
+#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U)\r
+#define USBPHY_TX_TXENCAL45DP_SHIFT (21U)\r
+#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TX_SET - USB PHY Transmitter Control Register */\r
+/*! @{ */\r
+#define USBPHY_TX_SET_D_CAL_MASK (0xFU)\r
+#define USBPHY_TX_SET_D_CAL_SHIFT (0U)\r
+/*! D_CAL\r
+ * 0b0000..Maximum current, approximately 19% above nominal.\r
+ * 0b0111..Nominal\r
+ * 0b1111..Minimum current, approximately 19% below nominal.\r
+ */\r
+#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)\r
+#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)\r
+#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)\r
+#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)\r
+#define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U)\r
+#define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U)\r
+#define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK)\r
+#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)\r
+#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)\r
+#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)\r
+#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U)\r
+#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U)\r
+#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TX_CLR - USB PHY Transmitter Control Register */\r
+/*! @{ */\r
+#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)\r
+#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)\r
+/*! D_CAL\r
+ * 0b0000..Maximum current, approximately 19% above nominal.\r
+ * 0b0111..Nominal\r
+ * 0b1111..Minimum current, approximately 19% below nominal.\r
+ */\r
+#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)\r
+#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)\r
+#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)\r
+#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)\r
+#define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U)\r
+#define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U)\r
+#define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK)\r
+#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)\r
+#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)\r
+#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)\r
+#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U)\r
+#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U)\r
+#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK)\r
+/*! @} */\r
+\r
+/*! @name TX_TOG - USB PHY Transmitter Control Register */\r
+/*! @{ */\r
+#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)\r
+#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)\r
+/*! D_CAL\r
+ * 0b0000..Maximum current, approximately 19% above nominal.\r
+ * 0b0111..Nominal\r
+ * 0b1111..Minimum current, approximately 19% below nominal.\r
+ */\r
+#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)\r
+#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)\r
+#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)\r
+#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)\r
+#define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U)\r
+#define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U)\r
+#define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK)\r
+#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)\r
+#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)\r
+#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)\r
+#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U)\r
+#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U)\r
+#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK)\r
+/*! @} */\r
+\r
+/*! @name RX - USB PHY Receiver Control Register */\r
+/*! @{ */\r
+#define USBPHY_RX_ENVADJ_MASK (0x7U)\r
+#define USBPHY_RX_ENVADJ_SHIFT (0U)\r
+/*! ENVADJ\r
+ * 0b000..Trip-Level Voltage is 0.1000 V\r
+ * 0b001..Trip-Level Voltage is 0.1125 V\r
+ * 0b010..Trip-Level Voltage is 0.1250 V\r
+ * 0b011..Trip-Level Voltage is 0.0875 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)\r
+#define USBPHY_RX_DISCONADJ_MASK (0x70U)\r
+#define USBPHY_RX_DISCONADJ_SHIFT (4U)\r
+/*! DISCONADJ\r
+ * 0b000..Trip-Level Voltage is 0.56875 V\r
+ * 0b001..Trip-Level Voltage is 0.55000 V\r
+ * 0b010..Trip-Level Voltage is 0.58125 V\r
+ * 0b011..Trip-Level Voltage is 0.60000 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)\r
+#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)\r
+#define USBPHY_RX_RXDBYPASS_SHIFT (22U)\r
+/*! RXDBYPASS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver\r
+ */\r
+#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)\r
+/*! @} */\r
+\r
+/*! @name RX_SET - USB PHY Receiver Control Register */\r
+/*! @{ */\r
+#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)\r
+#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)\r
+/*! ENVADJ\r
+ * 0b000..Trip-Level Voltage is 0.1000 V\r
+ * 0b001..Trip-Level Voltage is 0.1125 V\r
+ * 0b010..Trip-Level Voltage is 0.1250 V\r
+ * 0b011..Trip-Level Voltage is 0.0875 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)\r
+#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)\r
+#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)\r
+/*! DISCONADJ\r
+ * 0b000..Trip-Level Voltage is 0.56875 V\r
+ * 0b001..Trip-Level Voltage is 0.55000 V\r
+ * 0b010..Trip-Level Voltage is 0.58125 V\r
+ * 0b011..Trip-Level Voltage is 0.60000 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)\r
+#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)\r
+#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)\r
+/*! RXDBYPASS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver\r
+ */\r
+#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)\r
+/*! @} */\r
+\r
+/*! @name RX_CLR - USB PHY Receiver Control Register */\r
+/*! @{ */\r
+#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)\r
+#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)\r
+/*! ENVADJ\r
+ * 0b000..Trip-Level Voltage is 0.1000 V\r
+ * 0b001..Trip-Level Voltage is 0.1125 V\r
+ * 0b010..Trip-Level Voltage is 0.1250 V\r
+ * 0b011..Trip-Level Voltage is 0.0875 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)\r
+#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)\r
+#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)\r
+/*! DISCONADJ\r
+ * 0b000..Trip-Level Voltage is 0.56875 V\r
+ * 0b001..Trip-Level Voltage is 0.55000 V\r
+ * 0b010..Trip-Level Voltage is 0.58125 V\r
+ * 0b011..Trip-Level Voltage is 0.60000 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)\r
+#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)\r
+#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)\r
+/*! RXDBYPASS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver\r
+ */\r
+#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)\r
+/*! @} */\r
+\r
+/*! @name RX_TOG - USB PHY Receiver Control Register */\r
+/*! @{ */\r
+#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)\r
+#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)\r
+/*! ENVADJ\r
+ * 0b000..Trip-Level Voltage is 0.1000 V\r
+ * 0b001..Trip-Level Voltage is 0.1125 V\r
+ * 0b010..Trip-Level Voltage is 0.1250 V\r
+ * 0b011..Trip-Level Voltage is 0.0875 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)\r
+#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)\r
+#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)\r
+/*! DISCONADJ\r
+ * 0b000..Trip-Level Voltage is 0.56875 V\r
+ * 0b001..Trip-Level Voltage is 0.55000 V\r
+ * 0b010..Trip-Level Voltage is 0.58125 V\r
+ * 0b011..Trip-Level Voltage is 0.60000 V\r
+ * 0b100..reserved\r
+ * 0b101..reserved\r
+ * 0b110..reserved\r
+ * 0b111..reserved\r
+ */\r
+#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)\r
+#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)\r
+#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)\r
+/*! RXDBYPASS\r
+ * 0b0..Normal operation.\r
+ * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver\r
+ */\r
+#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL - USB PHY General Control Register */\r
+/*! @{ */\r
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)\r
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)\r
+#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)\r
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)\r
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)\r
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)\r
+#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)\r
+#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)\r
+/*! ENDEVPLUGINDET\r
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)\r
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins\r
+ */\r
+#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)\r
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)\r
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)\r
+#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)\r
+#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U)\r
+#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U)\r
+#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK)\r
+#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)\r
+#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)\r
+#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)\r
+#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)\r
+#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)\r
+#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)\r
+#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)\r
+#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)\r
+#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)\r
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)\r
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)\r
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)\r
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)\r
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)\r
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)\r
+#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)\r
+#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)\r
+#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)\r
+#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)\r
+#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)\r
+#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)\r
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)\r
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)\r
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)\r
+#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)\r
+#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)\r
+#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)\r
+#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_CTRL_CLKGATE_SHIFT (30U)\r
+#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)\r
+#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)\r
+#define USBPHY_CTRL_SFTRST_SHIFT (31U)\r
+#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL_SET - USB PHY General Control Register */\r
+/*! @{ */\r
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)\r
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)\r
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)\r
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)\r
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)\r
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)\r
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)\r
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)\r
+/*! ENDEVPLUGINDET\r
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)\r
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins\r
+ */\r
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)\r
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)\r
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)\r
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)\r
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)\r
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)\r
+#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)\r
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)\r
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)\r
+#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)\r
+#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)\r
+#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)\r
+#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)\r
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)\r
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)\r
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)\r
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)\r
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)\r
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)\r
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)\r
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)\r
+#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)\r
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)\r
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)\r
+#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)\r
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)\r
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)\r
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)\r
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)\r
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)\r
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)\r
+#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)\r
+#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)\r
+#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)\r
+#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)\r
+#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL_CLR - USB PHY General Control Register */\r
+/*! @{ */\r
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)\r
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)\r
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)\r
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)\r
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)\r
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)\r
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)\r
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)\r
+/*! ENDEVPLUGINDET\r
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)\r
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins\r
+ */\r
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)\r
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)\r
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)\r
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)\r
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)\r
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)\r
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)\r
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)\r
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)\r
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)\r
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)\r
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)\r
+#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)\r
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)\r
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)\r
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)\r
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)\r
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)\r
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)\r
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)\r
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)\r
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)\r
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)\r
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)\r
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)\r
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)\r
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)\r
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)\r
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)\r
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)\r
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)\r
+#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)\r
+#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)\r
+#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)\r
+#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)\r
+#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name CTRL_TOG - USB PHY General Control Register */\r
+/*! @{ */\r
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)\r
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)\r
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)\r
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)\r
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)\r
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)\r
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)\r
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)\r
+/*! ENDEVPLUGINDET\r
+ * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)\r
+ * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins\r
+ */\r
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)\r
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)\r
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)\r
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)\r
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)\r
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)\r
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)\r
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)\r
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)\r
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)\r
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)\r
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)\r
+#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)\r
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)\r
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)\r
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)\r
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)\r
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)\r
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)\r
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)\r
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)\r
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)\r
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)\r
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)\r
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)\r
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)\r
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)\r
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)\r
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)\r
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)\r
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)\r
+#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)\r
+#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)\r
+#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)\r
+#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)\r
+#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)\r
+/*! @} */\r
+\r
+/*! @name STATUS - USB PHY Status Register */\r
+/*! @{ */\r
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)\r
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)\r
+/*! HOSTDISCONDETECT_STATUS\r
+ * 0b0..USB cable disconnect has not been detected at the local host\r
+ * 0b1..USB cable disconnect has been detected at the local host\r
+ */\r
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)\r
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)\r
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)\r
+/*! DEVPLUGIN_STATUS\r
+ * 0b0..No attachment to a USB host is detected\r
+ * 0b1..Cable attachment to a USB host is detected\r
+ */\r
+#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)\r
+#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)\r
+#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)\r
+#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)\r
+#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)\r
+#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)\r
+#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG0 - USB PHY Debug Register 0 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U)\r
+#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U)\r
+#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK)\r
+#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U)\r
+#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U)\r
+#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK)\r
+#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU)\r
+#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U)\r
+#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U)\r
+#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U)\r
+#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U)\r
+#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U)\r
+#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U)\r
+#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U)\r
+#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U)\r
+#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U)\r
+#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK)\r
+#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U)\r
+#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U)\r
+#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK)\r
+#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U)\r
+#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U)\r
+#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK)\r
+#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U)\r
+#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U)\r
+#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK)\r
+#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U)\r
+#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG0_SET - USB PHY Debug Register 0 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U)\r
+#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U)\r
+#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK)\r
+#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)\r
+#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)\r
+#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK)\r
+#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU)\r
+#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U)\r
+#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U)\r
+#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U)\r
+#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U)\r
+#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U)\r
+#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U)\r
+#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U)\r
+#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)\r
+#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U)\r
+#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK)\r
+#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U)\r
+#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U)\r
+#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK)\r
+#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)\r
+#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U)\r
+#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK)\r
+#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)\r
+#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U)\r
+#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK)\r
+#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U)\r
+#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U)\r
+#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U)\r
+#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK)\r
+#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)\r
+#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)\r
+#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK)\r
+#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU)\r
+#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U)\r
+#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U)\r
+#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U)\r
+#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U)\r
+#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U)\r
+#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U)\r
+#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U)\r
+#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)\r
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U)\r
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK)\r
+#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U)\r
+#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U)\r
+#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK)\r
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)\r
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U)\r
+#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK)\r
+#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)\r
+#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U)\r
+#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK)\r
+#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U)\r
+#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U)\r
+#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U)\r
+#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK)\r
+#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)\r
+#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)\r
+#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK)\r
+#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU)\r
+#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U)\r
+#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U)\r
+#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U)\r
+#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK)\r
+#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U)\r
+#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U)\r
+#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U)\r
+#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U)\r
+#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK)\r
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)\r
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U)\r
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK)\r
+#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U)\r
+#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U)\r
+#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK)\r
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)\r
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U)\r
+#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK)\r
+#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)\r
+#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U)\r
+#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK)\r
+#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U)\r
+#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U)\r
+#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG1 - UTMI Debug Status Register 1 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)\r
+#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)\r
+/*! ENTAILADJVD\r
+ * 0b00..Delay is nominal\r
+ * 0b01..Delay is +20%\r
+ * 0b10..Delay is -20%\r
+ * 0b11..Delay is -40%\r
+ */\r
+#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)\r
+#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)\r
+#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U)\r
+#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)\r
+#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U)\r
+#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U)\r
+#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)\r
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)\r
+/*! ENTAILADJVD\r
+ * 0b00..Delay is nominal\r
+ * 0b01..Delay is +20%\r
+ * 0b10..Delay is -20%\r
+ * 0b11..Delay is -40%\r
+ */\r
+#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)\r
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)\r
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)\r
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)\r
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U)\r
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)\r
+#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)\r
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)\r
+/*! ENTAILADJVD\r
+ * 0b00..Delay is nominal\r
+ * 0b01..Delay is +20%\r
+ * 0b10..Delay is -20%\r
+ * 0b11..Delay is -40%\r
+ */\r
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)\r
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)\r
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)\r
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)\r
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U)\r
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)\r
+#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)\r
+/*! @} */\r
+\r
+/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */\r
+/*! @{ */\r
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)\r
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)\r
+/*! ENTAILADJVD\r
+ * 0b00..Delay is nominal\r
+ * 0b01..Delay is +20%\r
+ * 0b10..Delay is -20%\r
+ * 0b11..Delay is -40%\r
+ */\r
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)\r
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)\r
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)\r
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)\r
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U)\r
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)\r
+#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)\r
+/*! @} */\r
+\r
+/*! @name VERSION - UTMI RTL Version */\r
+/*! @{ */\r
+#define USBPHY_VERSION_STEP_MASK (0xFFFFU)\r
+#define USBPHY_VERSION_STEP_SHIFT (0U)\r
+#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)\r
+#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)\r
+#define USBPHY_VERSION_MINOR_SHIFT (16U)\r
+#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)\r
+#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)\r
+#define USBPHY_VERSION_MAJOR_SHIFT (24U)\r
+#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL_SIC - USB PHY PLL Control/Status Register */\r
+/*! @{ */\r
+#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U)\r
+#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U)\r
+#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK)\r
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)\r
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)\r
+#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)\r
+#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)\r
+#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)\r
+#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)\r
+#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)\r
+#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)\r
+#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)\r
+#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)\r
+#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)\r
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U)\r
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U)\r
+/*! REFBIAS_PWD_SEL\r
+ * 0b0..Selects PLL_POWER to control the reference bias\r
+ * 0b1..Selects REFBIAS_PWD to control the reference bias\r
+ */\r
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)\r
+#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U)\r
+#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U)\r
+#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)\r
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U)\r
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U)\r
+#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U)\r
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U)\r
+/*! PLL_DIV_SEL\r
+ * 0b000..Divide by 13\r
+ * 0b001..Divide by 15\r
+ * 0b010..Divide by 16\r
+ * 0b011..Divide by 20\r
+ * 0b100..Divide by 22\r
+ * 0b101..Divide by 25\r
+ * 0b110..Divide by 30\r
+ * 0b111..Divide by 240\r
+ */\r
+#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)\r
+#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)\r
+#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)\r
+/*! PLL_LOCK\r
+ * 0b0..PLL is not currently locked\r
+ * 0b1..PLL is currently locked\r
+ */\r
+#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */\r
+/*! @{ */\r
+#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U)\r
+#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U)\r
+#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)\r
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)\r
+#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)\r
+#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)\r
+#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)\r
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)\r
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)\r
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)\r
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)\r
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U)\r
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)\r
+/*! REFBIAS_PWD_SEL\r
+ * 0b0..Selects PLL_POWER to control the reference bias\r
+ * 0b1..Selects REFBIAS_PWD to control the reference bias\r
+ */\r
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)\r
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U)\r
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U)\r
+#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U)\r
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U)\r
+#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U)\r
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U)\r
+/*! PLL_DIV_SEL\r
+ * 0b000..Divide by 13\r
+ * 0b001..Divide by 15\r
+ * 0b010..Divide by 16\r
+ * 0b011..Divide by 20\r
+ * 0b100..Divide by 22\r
+ * 0b101..Divide by 25\r
+ * 0b110..Divide by 30\r
+ * 0b111..Divide by 240\r
+ */\r
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)\r
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)\r
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)\r
+/*! PLL_LOCK\r
+ * 0b0..PLL is not currently locked\r
+ * 0b1..PLL is currently locked\r
+ */\r
+#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */\r
+/*! @{ */\r
+#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U)\r
+#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U)\r
+#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)\r
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U)\r
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)\r
+/*! REFBIAS_PWD_SEL\r
+ * 0b0..Selects PLL_POWER to control the reference bias\r
+ * 0b1..Selects REFBIAS_PWD to control the reference bias\r
+ */\r
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)\r
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U)\r
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U)\r
+#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U)\r
+/*! PLL_DIV_SEL\r
+ * 0b000..Divide by 13\r
+ * 0b001..Divide by 15\r
+ * 0b010..Divide by 16\r
+ * 0b011..Divide by 20\r
+ * 0b100..Divide by 22\r
+ * 0b101..Divide by 25\r
+ * 0b110..Divide by 30\r
+ * 0b111..Divide by 240\r
+ */\r
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)\r
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)\r
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)\r
+/*! PLL_LOCK\r
+ * 0b0..PLL is not currently locked\r
+ * 0b1..PLL is currently locked\r
+ */\r
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */\r
+/*! @{ */\r
+#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U)\r
+#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U)\r
+#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)\r
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U)\r
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)\r
+/*! REFBIAS_PWD_SEL\r
+ * 0b0..Selects PLL_POWER to control the reference bias\r
+ * 0b1..Selects REFBIAS_PWD to control the reference bias\r
+ */\r
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)\r
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U)\r
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U)\r
+#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U)\r
+/*! PLL_DIV_SEL\r
+ * 0b000..Divide by 13\r
+ * 0b001..Divide by 15\r
+ * 0b010..Divide by 16\r
+ * 0b011..Divide by 20\r
+ * 0b100..Divide by 22\r
+ * 0b101..Divide by 25\r
+ * 0b110..Divide by 30\r
+ * 0b111..Divide by 240\r
+ */\r
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)\r
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)\r
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)\r
+/*! PLL_LOCK\r
+ * 0b0..PLL is not currently locked\r
+ * 0b1..PLL is currently locked\r
+ */\r
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)\r
+/*! VBUSVALID_THRESH\r
+ * 0b000..4.0V\r
+ * 0b001..4.1V\r
+ * 0b010..4.2V\r
+ * 0b011..4.3V\r
+ * 0b100..4.4V(Default)\r
+ * 0b101..4.5V\r
+ * 0b110..4.6V\r
+ * 0b111..4.7V\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)\r
+/*! VBUS_OVERRIDE_EN\r
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)\r
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)\r
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)\r
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)\r
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)\r
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)\r
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)\r
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)\r
+/*! VBUSVALID_SEL\r
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)\r
+/*! VBUS_SOURCE_SEL\r
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b11..Reserved, do not use\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)\r
+/*! VBUSVALID_TO_SESSVALID\r
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results\r
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)\r
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)\r
+/*! PWRUP_CMPS\r
+ * 0b0..Powers down the VBUS_VALID comparator\r
+ * 0b1..Enables the VBUS_VALID comparator (default)\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)\r
+/*! DISCHARGE_VBUS\r
+ * 0b0..VBUS discharge resistor is disabled (Default)\r
+ * 0b1..VBUS discharge resistor is enabled\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)\r
+/*! EN_CHARGER_RESISTOR\r
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP\r
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)\r
+/*! VBUSVALID_THRESH\r
+ * 0b000..4.0V\r
+ * 0b001..4.1V\r
+ * 0b010..4.2V\r
+ * 0b011..4.3V\r
+ * 0b100..4.4V(Default)\r
+ * 0b101..4.5V\r
+ * 0b110..4.6V\r
+ * 0b111..4.7V\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)\r
+/*! VBUS_OVERRIDE_EN\r
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)\r
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)\r
+/*! VBUSVALID_SEL\r
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)\r
+/*! VBUS_SOURCE_SEL\r
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b11..Reserved, do not use\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)\r
+/*! VBUSVALID_TO_SESSVALID\r
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results\r
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)\r
+/*! PWRUP_CMPS\r
+ * 0b0..Powers down the VBUS_VALID comparator\r
+ * 0b1..Enables the VBUS_VALID comparator (default)\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)\r
+/*! DISCHARGE_VBUS\r
+ * 0b0..VBUS discharge resistor is disabled (Default)\r
+ * 0b1..VBUS discharge resistor is enabled\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)\r
+/*! EN_CHARGER_RESISTOR\r
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP\r
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)\r
+/*! VBUSVALID_THRESH\r
+ * 0b000..4.0V\r
+ * 0b001..4.1V\r
+ * 0b010..4.2V\r
+ * 0b011..4.3V\r
+ * 0b100..4.4V(Default)\r
+ * 0b101..4.5V\r
+ * 0b110..4.6V\r
+ * 0b111..4.7V\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)\r
+/*! VBUS_OVERRIDE_EN\r
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)\r
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)\r
+/*! VBUSVALID_SEL\r
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)\r
+/*! VBUS_SOURCE_SEL\r
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b11..Reserved, do not use\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)\r
+/*! VBUSVALID_TO_SESSVALID\r
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results\r
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)\r
+/*! PWRUP_CMPS\r
+ * 0b0..Powers down the VBUS_VALID comparator\r
+ * 0b1..Enables the VBUS_VALID comparator (default)\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)\r
+/*! DISCHARGE_VBUS\r
+ * 0b0..VBUS discharge resistor is disabled (Default)\r
+ * 0b1..VBUS discharge resistor is enabled\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)\r
+/*! EN_CHARGER_RESISTOR\r
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP\r
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)\r
+/*! VBUSVALID_THRESH\r
+ * 0b000..4.0V\r
+ * 0b001..4.1V\r
+ * 0b010..4.2V\r
+ * 0b011..4.3V\r
+ * 0b100..4.4V(Default)\r
+ * 0b101..4.5V\r
+ * 0b110..4.6V\r
+ * 0b111..4.7V\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)\r
+/*! VBUS_OVERRIDE_EN\r
+ * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)\r
+ * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)\r
+/*! VBUSVALID_SEL\r
+ * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)\r
+/*! VBUS_SOURCE_SEL\r
+ * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)\r
+ * 0b01..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b10..Use the Session Valid comparator results for signal reported to the USB controller\r
+ * 0b11..Reserved, do not use\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)\r
+/*! VBUSVALID_TO_SESSVALID\r
+ * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results\r
+ * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)\r
+/*! PWRUP_CMPS\r
+ * 0b0..Powers down the VBUS_VALID comparator\r
+ * 0b1..Enables the VBUS_VALID comparator (default)\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)\r
+/*! DISCHARGE_VBUS\r
+ * 0b0..VBUS discharge resistor is disabled (Default)\r
+ * 0b1..VBUS discharge resistor is enabled\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)\r
+/*! EN_CHARGER_RESISTOR\r
+ * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP\r
+ * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP\r
+ */\r
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)\r
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)\r
+/*! SESSEND\r
+ * 0b0..The VBUS voltage is above the Session Valid threshold\r
+ * 0b1..The VBUS voltage is below the Session Valid threshold\r
+ */\r
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)\r
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)\r
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)\r
+/*! BVALID\r
+ * 0b0..The VBUS voltage is below the Session Valid threshold\r
+ * 0b1..The VBUS voltage is above the Session Valid threshold\r
+ */\r
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)\r
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)\r
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)\r
+/*! AVALID\r
+ * 0b0..The VBUS voltage is below the Session Valid threshold\r
+ * 0b1..The VBUS voltage is above the Session Valid threshold\r
+ */\r
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)\r
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)\r
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)\r
+/*! VBUS_VALID\r
+ * 0b0..VBUS is below the comparator threshold\r
+ * 0b1..VBUS is above the comparator threshold\r
+ */\r
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)\r
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)\r
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)\r
+/*! VBUS_VALID_3V\r
+ * 0b0..VBUS voltage is below VBUS_VALID_3V threshold\r
+ * 0b1..VBUS voltage is above VBUS_VALID_3V threshold\r
+ */\r
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U)\r
+#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U)\r
+#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)\r
+#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U)\r
+#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U)\r
+/*! BGR_IBIAS\r
+ * 0b0..Bias current is derived from the USB PHY internal current generator.\r
+ * 0b1..Bias current is derived from the reference generator of the bandgap.\r
+ */\r
+#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)\r
+#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)\r
+#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)\r
+#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U)\r
+#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U)\r
+/*! BGR_IBIAS\r
+ * 0b0..Bias current is derived from the USB PHY internal current generator.\r
+ * 0b1..Bias current is derived from the reference generator of the bandgap.\r
+ */\r
+#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)\r
+#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)\r
+#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)\r
+#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U)\r
+#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U)\r
+/*! BGR_IBIAS\r
+ * 0b0..Bias current is derived from the USB PHY internal current generator.\r
+ * 0b1..Bias current is derived from the reference generator of the bandgap.\r
+ */\r
+#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)\r
+#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)\r
+#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)\r
+#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U)\r
+#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U)\r
+/*! BGR_IBIAS\r
+ * 0b0..Bias current is derived from the USB PHY internal current generator.\r
+ * 0b1..Bias current is derived from the reference generator of the bandgap.\r
+ */\r
+#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK)\r
+/*! @} */\r
+\r
+/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */\r
+/*! @{ */\r
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)\r
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)\r
+/*! PLUG_CONTACT\r
+ * 0b0..No USB cable attachment has been detected\r
+ * 0b1..A USB cable attachment between the device and host has been detected\r
+ */\r
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)\r
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)\r
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)\r
+/*! CHRG_DETECTED\r
+ * 0b0..Standard Downstream Port (SDP) has been detected\r
+ * 0b1..Charging Port has been detected\r
+ */\r
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)\r
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)\r
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)\r
+/*! DM_STATE\r
+ * 0b0..USB_DM pin voltage is < 0.8V\r
+ * 0b1..USB_DM pin voltage is > 2.0V\r
+ */\r
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)\r
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)\r
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)\r
+/*! DP_STATE\r
+ * 0b0..USB_DP pin voltage is < 0.8V\r
+ * 0b1..USB_DP pin voltage is > 2.0V\r
+ */\r
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)\r
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)\r
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)\r
+/*! SECDET_DCP\r
+ * 0b0..Charging Downstream Port (CDP) has been detected\r
+ * 0b1..Downstream Charging Port (DCP) has been detected\r
+ */\r
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)\r
+/*! @} */\r
+\r
+/*! @name ANACTRL - USB PHY Analog Control Register */\r
+/*! @{ */\r
+#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)\r
+#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)\r
+/*! DEV_PULLDOWN\r
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.\r
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.\r
+ */\r
+#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)\r
+/*! @} */\r
+\r
+/*! @name ANACTRL_SET - USB PHY Analog Control Register */\r
+/*! @{ */\r
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)\r
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)\r
+/*! DEV_PULLDOWN\r
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.\r
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.\r
+ */\r
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)\r
+/*! @} */\r
+\r
+/*! @name ANACTRL_CLR - USB PHY Analog Control Register */\r
+/*! @{ */\r
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)\r
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)\r
+/*! DEV_PULLDOWN\r
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.\r
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.\r
+ */\r
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)\r
+/*! @} */\r
+\r
+/*! @name ANACTRL_TOG - USB PHY Analog Control Register */\r
+/*! @{ */\r
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)\r
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)\r
+/*! DEV_PULLDOWN\r
+ * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.\r
+ * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.\r
+ */\r
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBPHY_Register_Masks */\r
+\r
+\r
+/* USBPHY - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral USBPHY base address */\r
+ #define USBPHY_BASE (0x50038000u)\r
+ /** Peripheral USBPHY base address */\r
+ #define USBPHY_BASE_NS (0x40038000u)\r
+ /** Peripheral USBPHY base pointer */\r
+ #define USBPHY ((USBPHY_Type *)USBPHY_BASE)\r
+ /** Peripheral USBPHY base pointer */\r
+ #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS)\r
+ /** Array initializer of USBPHY peripheral base addresses */\r
+ #define USBPHY_BASE_ADDRS { USBPHY_BASE }\r
+ /** Array initializer of USBPHY peripheral base pointers */\r
+ #define USBPHY_BASE_PTRS { USBPHY }\r
+ /** Array initializer of USBPHY peripheral base addresses */\r
+ #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS }\r
+ /** Array initializer of USBPHY peripheral base pointers */\r
+ #define USBPHY_BASE_PTRS_NS { USBPHY_NS }\r
+#else\r
+ /** Peripheral USBPHY base address */\r
+ #define USBPHY_BASE (0x40038000u)\r
+ /** Peripheral USBPHY base pointer */\r
+ #define USBPHY ((USBPHY_Type *)USBPHY_BASE)\r
+ /** Array initializer of USBPHY peripheral base addresses */\r
+ #define USBPHY_BASE_ADDRS { USBPHY_BASE }\r
+ /** Array initializer of USBPHY peripheral base pointers */\r
+ #define USBPHY_BASE_PTRS { USBPHY }\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group USBPHY_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- UTICK Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** UTICK - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t CTRL; /**< Control register., offset: 0x0 */\r
+ __IO uint32_t STAT; /**< Status register., offset: 0x4 */\r
+ __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */\r
+ __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */\r
+ __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */\r
+} UTICK_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- UTICK Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name CTRL - Control register. */\r
+/*! @{ */\r
+#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)\r
+#define UTICK_CTRL_DELAYVAL_SHIFT (0U)\r
+#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)\r
+#define UTICK_CTRL_REPEAT_MASK (0x80000000U)\r
+#define UTICK_CTRL_REPEAT_SHIFT (31U)\r
+#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)\r
+/*! @} */\r
+\r
+/*! @name STAT - Status register. */\r
+/*! @{ */\r
+#define UTICK_STAT_INTR_MASK (0x1U)\r
+#define UTICK_STAT_INTR_SHIFT (0U)\r
+#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)\r
+#define UTICK_STAT_ACTIVE_MASK (0x2U)\r
+#define UTICK_STAT_ACTIVE_SHIFT (1U)\r
+#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)\r
+/*! @} */\r
+\r
+/*! @name CFG - Capture configuration register. */\r
+/*! @{ */\r
+#define UTICK_CFG_CAPEN0_MASK (0x1U)\r
+#define UTICK_CFG_CAPEN0_SHIFT (0U)\r
+#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)\r
+#define UTICK_CFG_CAPEN1_MASK (0x2U)\r
+#define UTICK_CFG_CAPEN1_SHIFT (1U)\r
+#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)\r
+#define UTICK_CFG_CAPEN2_MASK (0x4U)\r
+#define UTICK_CFG_CAPEN2_SHIFT (2U)\r
+#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)\r
+#define UTICK_CFG_CAPEN3_MASK (0x8U)\r
+#define UTICK_CFG_CAPEN3_SHIFT (3U)\r
+#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)\r
+#define UTICK_CFG_CAPPOL0_MASK (0x100U)\r
+#define UTICK_CFG_CAPPOL0_SHIFT (8U)\r
+#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)\r
+#define UTICK_CFG_CAPPOL1_MASK (0x200U)\r
+#define UTICK_CFG_CAPPOL1_SHIFT (9U)\r
+#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)\r
+#define UTICK_CFG_CAPPOL2_MASK (0x400U)\r
+#define UTICK_CFG_CAPPOL2_SHIFT (10U)\r
+#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)\r
+#define UTICK_CFG_CAPPOL3_MASK (0x800U)\r
+#define UTICK_CFG_CAPPOL3_SHIFT (11U)\r
+#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAPCLR - Capture clear register. */\r
+/*! @{ */\r
+#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)\r
+#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)\r
+#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)\r
+#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)\r
+#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)\r
+#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)\r
+#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)\r
+#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)\r
+#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)\r
+#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)\r
+#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)\r
+#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)\r
+/*! @} */\r
+\r
+/*! @name CAP - Capture register . */\r
+/*! @{ */\r
+#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)\r
+#define UTICK_CAP_CAP_VALUE_SHIFT (0U)\r
+#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)\r
+#define UTICK_CAP_VALID_MASK (0x80000000U)\r
+#define UTICK_CAP_VALID_SHIFT (31U)\r
+#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)\r
+/*! @} */\r
+\r
+/* The count of UTICK_CAP */\r
+#define UTICK_CAP_COUNT (4U)\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group UTICK_Register_Masks */\r
+\r
+\r
+/* UTICK - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral UTICK0 base address */\r
+ #define UTICK0_BASE (0x5000E000u)\r
+ /** Peripheral UTICK0 base address */\r
+ #define UTICK0_BASE_NS (0x4000E000u)\r
+ /** Peripheral UTICK0 base pointer */\r
+ #define UTICK0 ((UTICK_Type *)UTICK0_BASE)\r
+ /** Peripheral UTICK0 base pointer */\r
+ #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS)\r
+ /** Array initializer of UTICK peripheral base addresses */\r
+ #define UTICK_BASE_ADDRS { UTICK0_BASE }\r
+ /** Array initializer of UTICK peripheral base pointers */\r
+ #define UTICK_BASE_PTRS { UTICK0 }\r
+ /** Array initializer of UTICK peripheral base addresses */\r
+ #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS }\r
+ /** Array initializer of UTICK peripheral base pointers */\r
+ #define UTICK_BASE_PTRS_NS { UTICK0_NS }\r
+#else\r
+ /** Peripheral UTICK0 base address */\r
+ #define UTICK0_BASE (0x4000E000u)\r
+ /** Peripheral UTICK0 base pointer */\r
+ #define UTICK0 ((UTICK_Type *)UTICK0_BASE)\r
+ /** Array initializer of UTICK peripheral base addresses */\r
+ #define UTICK_BASE_ADDRS { UTICK0_BASE }\r
+ /** Array initializer of UTICK peripheral base pointers */\r
+ #define UTICK_BASE_PTRS { UTICK0 }\r
+#endif\r
+/** Interrupt vectors for the UTICK peripheral type */\r
+#define UTICK_IRQS { UTICK0_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group UTICK_Peripheral_Access_Layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- WWDT Peripheral Access Layer\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer\r
+ * @{\r
+ */\r
+\r
+/** WWDT - Register Layout Typedef */\r
+typedef struct {\r
+ __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */\r
+ __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */\r
+ __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */\r
+ __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */\r
+ uint8_t RESERVED_0[4];\r
+ __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */\r
+ __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */\r
+} WWDT_Type;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- WWDT Register Masks\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks\r
+ * @{\r
+ */\r
+\r
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */\r
+/*! @{ */\r
+#define WWDT_MOD_WDEN_MASK (0x1U)\r
+#define WWDT_MOD_WDEN_SHIFT (0U)\r
+/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently.\r
+ * 0b0..Stop. The watchdog timer is stopped.\r
+ * 0b1..Run. The watchdog timer is running.\r
+ */\r
+#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)\r
+#define WWDT_MOD_WDRESET_MASK (0x2U)\r
+#define WWDT_MOD_WDRESET_SHIFT (1U)\r
+/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0.\r
+ * 0b0..Interrupt. A watchdog time-out will not cause a chip reset.\r
+ * 0b1..Reset. A watchdog time-out will cause a chip reset.\r
+ */\r
+#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)\r
+#define WWDT_MOD_WDTOF_MASK (0x4U)\r
+#define WWDT_MOD_WDTOF_SHIFT (2U)\r
+#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)\r
+#define WWDT_MOD_WDINT_MASK (0x8U)\r
+#define WWDT_MOD_WDINT_SHIFT (3U)\r
+#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)\r
+#define WWDT_MOD_WDPROTECT_MASK (0x10U)\r
+#define WWDT_MOD_WDPROTECT_SHIFT (4U)\r
+/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset.\r
+ * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time.\r
+ * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW.\r
+ */\r
+#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)\r
+/*! @} */\r
+\r
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */\r
+/*! @{ */\r
+#define WWDT_TC_COUNT_MASK (0xFFFFFFU)\r
+#define WWDT_TC_COUNT_SHIFT (0U)\r
+#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */\r
+/*! @{ */\r
+#define WWDT_FEED_FEED_MASK (0xFFU)\r
+#define WWDT_FEED_FEED_SHIFT (0U)\r
+#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)\r
+/*! @} */\r
+\r
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */\r
+/*! @{ */\r
+#define WWDT_TV_COUNT_MASK (0xFFFFFFU)\r
+#define WWDT_TV_COUNT_SHIFT (0U)\r
+#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */\r
+/*! @{ */\r
+#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)\r
+#define WWDT_WARNINT_WARNINT_SHIFT (0U)\r
+#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)\r
+/*! @} */\r
+\r
+/*! @name WINDOW - Watchdog Window compare value. */\r
+/*! @{ */\r
+#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)\r
+#define WWDT_WINDOW_WINDOW_SHIFT (0U)\r
+#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)\r
+/*! @} */\r
+\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group WWDT_Register_Masks */\r
+\r
+\r
+/* WWDT - Peripheral instance base addresses */\r
+#if (__ARM_FEATURE_CMSE & 0x2)\r
+ /** Peripheral WWDT base address */\r
+ #define WWDT_BASE (0x5000C000u)\r
+ /** Peripheral WWDT base address */\r
+ #define WWDT_BASE_NS (0x4000C000u)\r
+ /** Peripheral WWDT base pointer */\r
+ #define WWDT ((WWDT_Type *)WWDT_BASE)\r
+ /** Peripheral WWDT base pointer */\r
+ #define WWDT_NS ((WWDT_Type *)WWDT_BASE_NS)\r
+ /** Array initializer of WWDT peripheral base addresses */\r
+ #define WWDT_BASE_ADDRS { WWDT_BASE }\r
+ /** Array initializer of WWDT peripheral base pointers */\r
+ #define WWDT_BASE_PTRS { WWDT }\r
+ /** Array initializer of WWDT peripheral base addresses */\r
+ #define WWDT_BASE_ADDRS_NS { WWDT_BASE_NS }\r
+ /** Array initializer of WWDT peripheral base pointers */\r
+ #define WWDT_BASE_PTRS_NS { WWDT_NS }\r
+#else\r
+ /** Peripheral WWDT base address */\r
+ #define WWDT_BASE (0x4000C000u)\r
+ /** Peripheral WWDT base pointer */\r
+ #define WWDT ((WWDT_Type *)WWDT_BASE)\r
+ /** Array initializer of WWDT peripheral base addresses */\r
+ #define WWDT_BASE_ADDRS { WWDT_BASE }\r
+ /** Array initializer of WWDT peripheral base pointers */\r
+ #define WWDT_BASE_PTRS { WWDT }\r
+#endif\r
+/** Interrupt vectors for the WWDT peripheral type */\r
+#define WWDT_IRQS { WDT_BOD_IRQn }\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group WWDT_Peripheral_Access_Layer */\r
+\r
+\r
+/*\r
+** End of section using anonymous unions\r
+*/\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #if (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang diagnostic pop\r
+ #else\r
+ #pragma pop\r
+ #endif\r
+#elif defined(__GNUC__)\r
+ /* leave anonymous unions enabled */\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+ #pragma language=default\r
+#else\r
+ #error Not supported compiler type\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Peripheral_access_layer */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).\r
+ * @{\r
+ */\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #if (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header\r
+ #endif\r
+#elif defined(__IAR_SYSTEMS_ICC__)\r
+ #pragma system_include\r
+#endif\r
+\r
+/**\r
+ * @brief Mask and left-shift a bit field value for use in a register bit range.\r
+ * @param field Name of the register bit field.\r
+ * @param value Value of the bit field.\r
+ * @return Masked and shifted value.\r
+ */\r
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))\r
+/**\r
+ * @brief Mask and right-shift a register value to extract a bit field value.\r
+ * @param field Name of the register bit field.\r
+ * @param value Value of the register.\r
+ * @return Masked and shifted bit field value.\r
+ */\r
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group Bit_Field_Generic_Macros */\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SDK Compatibility\r
+ ---------------------------------------------------------------------------- */\r
+\r
+/*!\r
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility\r
+ * @{\r
+ */\r
+\r
+/** EMC CS base address */\r
+#define EMC_CS0_BASE (0x80000000u)\r
+#define EMC_CS1_BASE (0x90000000u)\r
+#define EMC_CS2_BASE (0x98000000u)\r
+#define EMC_CS3_BASE (0x9C000000u)\r
+#define EMC_DYCS0_BASE (0xA0000000u)\r
+#define EMC_DYCS1_BASE (0xB0000000u)\r
+#define EMC_DYCS2_BASE (0xC0000000u)\r
+#define EMC_DYCS3_BASE (0xD0000000u)\r
+#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}\r
+#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}\r
+\r
+/** OTP API */\r
+typedef struct {\r
+ uint32_t (*otpInit)(void); /** Initializes OTP controller */\r
+ uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */\r
+ uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */\r
+ uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,\r
+ uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */\r
+ uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,\r
+ uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */\r
+ uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */\r
+ uint32_t RESERVED_0[5];\r
+ uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */\r
+ uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */\r
+} OTP_API_Type;\r
+\r
+/** ROM API */\r
+typedef struct {\r
+ __I uint32_t usbdApiBase; /** USB API Base */\r
+ uint32_t RESERVED_0[13];\r
+ __I OTP_API_Type *otpApiBase; /** OTP API Base */\r
+ __I uint32_t aesApiBase; /** AES API Base */\r
+ __I uint32_t secureApiBase; /** Secure API Base */\r
+} ROM_API_Type;\r
+\r
+/** ROM API base address */\r
+#define ROM_API_BASE (0x03000200u)\r
+/** ROM API base pointer */\r
+#define ROM_API (*(ROM_API_Type**) ROM_API_BASE)\r
+/** OTP API base pointer */\r
+#define OTP_API (ROM_API->otpApiBase)\r
+\r
+/*!\r
+ * @}\r
+ */ /* end of group SDK_Compatibility_Symbols */\r
+\r
+\r
+#endif /* _LPC55S69_CM33_CORE0_H_ */\r
+\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Version: rev. 1.0, 2018-08-22\r
+** Build: b190122\r
+**\r
+** Abstract:\r
+** Chip specific module features.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2019 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2018-08-22)\r
+** Initial version based on v0.2UM\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+#ifndef _LPC55S69_cm33_core0_FEATURES_H_\r
+#define _LPC55S69_cm33_core0_FEATURES_H_\r
+\r
+/* SOC module features */\r
+\r
+/* @brief CASPER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CASPER_COUNT (1)\r
+/* @brief CRC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CRC_COUNT (1)\r
+/* @brief CTIMER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)\r
+/* @brief DMA availability on the SoC. */\r
+#define FSL_FEATURE_SOC_DMA_COUNT (2)\r
+/* @brief FLASH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)\r
+/* @brief FLEXCOMM availability on the SoC. */\r
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)\r
+/* @brief GINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_GINT_COUNT (2)\r
+/* @brief GPIO availability on the SoC. */\r
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)\r
+/* @brief SECGPIO availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)\r
+/* @brief HASHCRYPT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)\r
+/* @brief I2C availability on the SoC. */\r
+#define FSL_FEATURE_SOC_I2C_COUNT (8)\r
+/* @brief I2S availability on the SoC. */\r
+#define FSL_FEATURE_SOC_I2S_COUNT (8)\r
+/* @brief INPUTMUX availability on the SoC. */\r
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)\r
+/* @brief IOCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)\r
+/* @brief LPADC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)\r
+/* @brief MAILBOX availability on the SoC. */\r
+#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)\r
+/* @brief MRT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_MRT_COUNT (1)\r
+/* @brief OSTIMER availability on the SoC. */\r
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)\r
+/* @brief PINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PINT_COUNT (1)\r
+/* @brief SECPINT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SECPINT_COUNT (1)\r
+/* @brief PMC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PMC_COUNT (1)\r
+/* @brief POWERQUAD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)\r
+/* @brief PUF availability on the SoC. */\r
+#define FSL_FEATURE_SOC_PUF_COUNT (1)\r
+/* @brief RNG1 availability on the SoC. */\r
+#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)\r
+/* @brief RTC availability on the SoC. */\r
+#define FSL_FEATURE_SOC_RTC_COUNT (1)\r
+/* @brief SCT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SCT_COUNT (1)\r
+/* @brief SDIF availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)\r
+/* @brief SPI availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SPI_COUNT (9)\r
+/* @brief SYSCON availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)\r
+/* @brief SYSCTL1 availability on the SoC. */\r
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)\r
+/* @brief USART availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USART_COUNT (8)\r
+/* @brief USB availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USB_COUNT (1)\r
+/* @brief USBFSH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)\r
+/* @brief USBHSD availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)\r
+/* @brief USBHSH availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)\r
+/* @brief USBPHY availability on the SoC. */\r
+#define FSL_FEATURE_SOC_USBPHY_COUNT (1)\r
+/* @brief UTICK availability on the SoC. */\r
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)\r
+/* @brief WWDT availability on the SoC. */\r
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)\r
+\r
+/* LPADC module features */\r
+\r
+/* @brief FIFO availability on the SoC. */\r
+#define FSL_FEATURE_LPADC_FIFO_COUNT (2)\r
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)\r
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)\r
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)\r
+/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)\r
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)\r
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */\r
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)\r
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */\r
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)\r
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */\r
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)\r
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */\r
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)\r
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)\r
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)\r
+/* @brief Has calibration (bitfield CFG[CALOFS]). */\r
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)\r
+/* @brief Has offset trim (register OFSTRIM). */\r
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)\r
+\r
+/* CASPER module features */\r
+\r
+/* @brief Base address of the CASPER dedicated RAM */\r
+#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)\r
+/* @brief Interleaving of the CASPER dedicated RAM */\r
+#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)\r
+\r
+/* DMA module features */\r
+\r
+/* @brief Number of channels */\r
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)\r
+\r
+/* HASHCRYPT module features */\r
+\r
+/* @brief the address of alias offset */\r
+#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)\r
+\r
+/* I2S module features */\r
+\r
+/* @brief I2S support dual channel transfer. */\r
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)\r
+\r
+/* IOCON module features */\r
+\r
+/* @brief Func bit field width */\r
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)\r
+\r
+/* MAILBOX module features */\r
+\r
+/* @brief Mailbox side for current core */\r
+#define FSL_FEATURE_MAILBOX_SIDE_A (1)\r
+\r
+/* MRT module features */\r
+\r
+/* @brief number of channels. */\r
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)\r
+\r
+/* PINT module features */\r
+\r
+/* @brief Number of connected outputs */\r
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)\r
+\r
+/* POWERLIB module features */\r
+\r
+/* @brief Niobe4's Powerlib API is different with other LPC series devices. */\r
+#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)\r
+\r
+/* POWERQUAD module features */\r
+\r
+/* @brief Sine and Cossine fix errata */\r
+#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)\r
+\r
+/* PUF module features */\r
+\r
+/* @brief Number of PUF key slots available on device. */\r
+#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)\r
+/* @brief the shift status value */\r
+#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)\r
+\r
+/* SCT module features */\r
+\r
+/* @brief Number of events */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)\r
+/* @brief Number of states */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)\r
+/* @brief Number of match capture */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)\r
+/* @brief Number of outputs */\r
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)\r
+\r
+/* SDIF module features */\r
+\r
+/* @brief FIFO depth, every location is a WORD */\r
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)\r
+/* @brief Max DMA buffer size */\r
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)\r
+/* @brief Max source clock in HZ */\r
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)\r
+/* @brief support 2 cards */\r
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)\r
+\r
+/* SECPINT module features */\r
+\r
+/* @brief Number of connected outputs */\r
+#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)\r
+\r
+/* SYSCON module features */\r
+\r
+/* @brief Pointer to ROM IAP entry functions */\r
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)\r
+/* @brief Flash page size in bytes */\r
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)\r
+/* @brief Flash sector size in bytes */\r
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)\r
+/* @brief Flash size in bytes */\r
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)\r
+/* @brief Has Power Down mode */\r
+#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)\r
+/* @brief CCM_ANALOG availability on the SoC. */\r
+#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)\r
+\r
+/* USB module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USB_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USB version */\r
+#define FSL_FEATURE_USB_VERSION (200)\r
+/* @brief Number of the endpoint in USB FS */\r
+#define FSL_FEATURE_USB_EP_NUM (5)\r
+\r
+/* USBFSH module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBFSH version */\r
+#define FSL_FEATURE_USBFSH_VERSION (200)\r
+\r
+/* USBHSD module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBHSD version */\r
+#define FSL_FEATURE_USBHSD_VERSION (300)\r
+/* @brief Number of the endpoint in USB HS */\r
+#define FSL_FEATURE_USBHSD_EP_NUM (6)\r
+\r
+/* USBHSH module features */\r
+\r
+/* @brief Size of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)\r
+/* @brief Base address of the USB dedicated RAM */\r
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)\r
+/* @brief USBHSH version */\r
+#define FSL_FEATURE_USBHSH_VERSION (300)\r
+\r
+/* UTICK module features */\r
+\r
+/* @brief UTICK does not support PD configure. */\r
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)\r
+\r
+/* WWDT module features */\r
+\r
+/* @brief WWDT does not support oscillator lock. */\r
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)\r
+/* @brief WWDT does not support power down configure */\r
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)\r
+\r
+#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */\r
+\r
--- /dev/null
+/*\r
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+\r
+#ifndef __FSL_DEVICE_REGISTERS_H__\r
+#define __FSL_DEVICE_REGISTERS_H__\r
+\r
+/*\r
+ * Include the cpu specific register header files.\r
+ *\r
+ * The CPU macro should be declared in the project or makefile.\r
+ */\r
+#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0))\r
+\r
+#define LPC55S69_cm33_core0_SERIES\r
+\r
+/* CMSIS-style register definitions */\r
+#include "LPC55S69_cm33_core0.h"\r
+/* CPU specific feature definitions */\r
+#include "LPC55S69_cm33_core0_features.h"\r
+\r
+#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1))\r
+\r
+#define LPC55S69_cm33_core1_SERIES\r
+\r
+/* CMSIS-style register definitions */\r
+#include "LPC55S69_cm33_core1.h"\r
+/* CPU specific feature definitions */\r
+#include "LPC55S69_cm33_core1_features.h"\r
+\r
+#else\r
+ #error "No valid CPU defined!"\r
+#endif\r
+\r
+#endif /* __FSL_DEVICE_REGISTERS_H__ */\r
+\r
+/*******************************************************************************\r
+ * EOF\r
+ ******************************************************************************/\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Processors: LPC55S69JBD100_cm33_core0\r
+** LPC55S69JET98_cm33_core0\r
+**\r
+** Compilers: GNU C Compiler\r
+** IAR ANSI C/C++ Compiler for ARM\r
+** Keil ARM C/C++ Compiler\r
+** MCUXpresso Compiler\r
+**\r
+** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018\r
+** Version: rev. 1.0, 2018-08-22\r
+** Build: b181219\r
+**\r
+** Abstract:\r
+** Provides a system configuration function and a global variable that\r
+** contains the system frequency. It configures the device and initializes\r
+** the oscillator (PLL) that is part of the microcontroller device.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2018 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2018-08-22)\r
+** Initial version based on v0.2UM\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+/*!\r
+ * @file LPC55S69_cm33_core0\r
+ * @version 1.0\r
+ * @date 2018-08-22\r
+ * @brief Device specific configuration file for LPC55S69_cm33_core0\r
+ * (implementation file)\r
+ *\r
+ * Provides a system configuration function and a global variable that contains\r
+ * the system frequency. It configures the device and initializes the oscillator\r
+ * (PLL) that is part of the microcontroller device.\r
+ */\r
+\r
+#include <stdint.h>\r
+#include "fsl_device_registers.h"\r
+\r
+/* PLL0 SSCG control1 */\r
+#define PLL_SSCG_MD_FRACT_P 0U\r
+#define PLL_SSCG_MD_INT_P 25U\r
+#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P)\r
+#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P)\r
+\r
+/* Get predivider (N) from PLL0 NDEC setting */\r
+static uint32_t findPll0PreDiv(void)\r
+{\r
+ uint32_t preDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)\r
+ {\r
+ preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;\r
+ if (preDiv == 0)\r
+ {\r
+ preDiv = 1;\r
+ }\r
+ }\r
+ return preDiv;\r
+}\r
+\r
+/* Get postdivider (P) from PLL0 PDEC setting */\r
+static uint32_t findPll0PostDiv(void)\r
+{\r
+ uint32_t postDiv = 1;\r
+\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)\r
+ {\r
+ if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)\r
+ {\r
+ postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;\r
+ }\r
+ else\r
+ {\r
+ postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);\r
+ }\r
+ if (postDiv == 0)\r
+ {\r
+ postDiv = 2;\r
+ }\r
+ }\r
+ return postDiv;\r
+}\r
+\r
+/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */\r
+static float findPll0MMult(void)\r
+{\r
+ float mMult = 1;\r
+ float mMult_fract;\r
+ uint32_t mMult_int;\r
+\r
+ if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)\r
+ {\r
+ mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;\r
+ }\r
+ else\r
+ {\r
+ mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);\r
+ mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P));\r
+ mMult = (float)mMult_int + mMult_fract;\r
+ }\r
+ if (mMult == 0)\r
+ {\r
+ mMult = 1;\r
+ }\r
+ return mMult;\r
+}\r
+\r
+/* Get predivider (N) from PLL1 NDEC setting */\r
+static uint32_t findPll1PreDiv(void)\r
+{\r
+ uint32_t preDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)\r
+ {\r
+ preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;\r
+ if (preDiv == 0)\r
+ {\r
+ preDiv = 1;\r
+ }\r
+ }\r
+ return preDiv;\r
+}\r
+\r
+/* Get postdivider (P) from PLL1 PDEC setting */\r
+static uint32_t findPll1PostDiv(void)\r
+{\r
+ uint32_t postDiv = 1;\r
+\r
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)\r
+ {\r
+ if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)\r
+ {\r
+ postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;\r
+ }\r
+ else\r
+ {\r
+ postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);\r
+ }\r
+ if (postDiv == 0)\r
+ {\r
+ postDiv = 2;\r
+ }\r
+ }\r
+ return postDiv;\r
+}\r
+\r
+/* Get multiplier (M) from PLL1 MDEC settings */\r
+static uint32_t findPll1MMult(void)\r
+{\r
+ uint32_t mMult = 1;\r
+\r
+ mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;\r
+\r
+ if (mMult == 0)\r
+ {\r
+ mMult = 1;\r
+ }\r
+ return mMult;\r
+}\r
+\r
+/* Get FRO 12M Clk */\r
+/*! brief Return Frequency of FRO 12MHz\r
+ * return Frequency of FRO 12MHz\r
+ */\r
+static uint32_t CLOCK_GetFro12MFreq(void)\r
+{\r
+ return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
+ 0 :\r
+ (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;\r
+}\r
+\r
+/* Get FRO 1M Clk */\r
+/*! brief Return Frequency of FRO 1MHz\r
+ * return Frequency of FRO 1MHz\r
+ */\r
+static uint32_t CLOCK_GetFro1MFreq(void)\r
+{\r
+ return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;\r
+}\r
+\r
+/* Get EXT OSC Clk */\r
+/*! brief Return Frequency of External Clock\r
+ * return Frequency of External Clock. If no external clock is used returns 0.\r
+ */\r
+static uint32_t CLOCK_GetExtClkFreq(void)\r
+{\r
+ return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;\r
+}\r
+\r
+/* Get HF FRO Clk */\r
+/*! brief Return Frequency of High-Freq output of FRO\r
+ * return Frequency of High-Freq output of FRO\r
+ */\r
+static uint32_t CLOCK_GetFroHfFreq(void)\r
+{\r
+ return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
+ 0 :\r
+ (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;\r
+}\r
+\r
+/* Get RTC OSC Clk */\r
+/*! brief Return Frequency of 32kHz osc\r
+ * return Frequency of 32kHz osc\r
+ */\r
+static uint32_t CLOCK_GetOsc32KFreq(void)\r
+{\r
+ return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?\r
+ CLK_RTC_32K_CLK :\r
+ ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?\r
+ CLK_RTC_32K_CLK :\r
+ 0U;\r
+}\r
+\r
+\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- Core clock\r
+ ---------------------------------------------------------------------------- */\r
+\r
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SystemInit()\r
+ ---------------------------------------------------------------------------- */\r
+\r
+__attribute__ ((weak)) void SystemInit (void) {\r
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))\r
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */\r
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */\r
+\r
+ SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */\r
+\r
+ SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */\r
+\r
+#if defined(__MCUXPRESSO)\r
+ extern void(*const g_pfnVectors[]) (void);\r
+ SCB->VTOR = (uint32_t) &g_pfnVectors;\r
+#else\r
+ extern void *__Vectors;\r
+ SCB->VTOR = (uint32_t) &__Vectors;\r
+#endif\r
+ SYSCON->TRACECLKDIV = 0;\r
+/* Optionally enable RAM banks that may be off by default at reset */\r
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)\r
+ SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK\r
+ | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;\r
+#endif\r
+ SystemInitHook();\r
+}\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SystemCoreClockUpdate()\r
+ ---------------------------------------------------------------------------- */\r
+\r
+void SystemCoreClockUpdate (void) {\r
+ uint32_t clkRate = 0;\r
+ uint32_t prediv, postdiv;\r
+ float workRate;\r
+ uint64_t workRate1;\r
+\r
+ switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)\r
+ {\r
+ case 0x00: /* MAINCLKSELA clock (main_clk_a)*/\r
+ switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)\r
+ {\r
+ case 0x00: /* FRO 12 MHz (fro_12m) */\r
+ clkRate = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 0x01: /* CLKIN (clk_in) */\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+ case 0x02: /* Fro 1MHz (fro_1m) */\r
+ clkRate = CLOCK_GetFro1MFreq();\r
+ break;\r
+ default: /* = 0x03 = FRO 96 MHz (fro_hf) */\r
+ clkRate = CLOCK_GetFroHfFreq();\r
+ break;\r
+ }\r
+ break;\r
+ case 0x01: /* PLL0 clock (pll0_clk)*/\r
+ switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)\r
+ {\r
+ case 0x00: /* FRO 12 MHz (fro_12m) */\r
+ clkRate = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 0x01: /* CLKIN (clk_in) */\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+ case 0x02: /* Fro 1MHz (fro_1m) */\r
+ clkRate = CLOCK_GetFro1MFreq();\r
+ break;\r
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */\r
+ clkRate = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))\r
+ {\r
+ prediv = findPll0PreDiv();\r
+ postdiv = findPll0PostDiv();\r
+ /* Adjust input clock */\r
+ clkRate = clkRate / prediv;\r
+ /* MDEC used for rate */\r
+ workRate = (float)clkRate * (float)findPll0MMult();\r
+ clkRate = (uint32_t)(workRate / ((float)postdiv));\r
+ }\r
+ break;\r
+ case 0x02: /* PLL1 clock (pll1_clk)*/\r
+ switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)\r
+ {\r
+ case 0x00: /* FRO 12 MHz (fro_12m) */\r
+ clkRate = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 0x01: /* CLKIN (clk_in) */\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+ case 0x02: /* Fro 1MHz (fro_1m) */\r
+ clkRate = CLOCK_GetFro1MFreq();\r
+ break;\r
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */\r
+ clkRate = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))\r
+ {\r
+ /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */\r
+ prediv = findPll1PreDiv();\r
+ postdiv = findPll1PostDiv();\r
+ /* Adjust input clock */\r
+ clkRate = clkRate / prediv;\r
+\r
+ /* MDEC used for rate */\r
+ workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();\r
+ clkRate = workRate1 / ((uint64_t)postdiv);\r
+ }\r
+ break;\r
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */\r
+ clkRate = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);\r
+}\r
+\r
+/* ----------------------------------------------------------------------------\r
+ -- SystemInitHook()\r
+ ---------------------------------------------------------------------------- */\r
+\r
+__attribute__ ((weak)) void SystemInitHook (void) {\r
+ /* Void implementation of the weak function. */\r
+}\r
--- /dev/null
+/*\r
+** ###################################################################\r
+** Processors: LPC55S69JBD100_cm33_core0\r
+** LPC55S69JET98_cm33_core0\r
+**\r
+** Compilers: GNU C Compiler\r
+** IAR ANSI C/C++ Compiler for ARM\r
+** Keil ARM C/C++ Compiler\r
+** MCUXpresso Compiler\r
+**\r
+** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018\r
+** Version: rev. 1.0, 2018-08-22\r
+** Build: b181219\r
+**\r
+** Abstract:\r
+** Provides a system configuration function and a global variable that\r
+** contains the system frequency. It configures the device and initializes\r
+** the oscillator (PLL) that is part of the microcontroller device.\r
+**\r
+** Copyright 2016 Freescale Semiconductor, Inc.\r
+** Copyright 2016-2018 NXP\r
+** All rights reserved.\r
+**\r
+** SPDX-License-Identifier: BSD-3-Clause\r
+**\r
+** http: www.nxp.com\r
+** mail: support@nxp.com\r
+**\r
+** Revisions:\r
+** - rev. 1.0 (2018-08-22)\r
+** Initial version based on v0.2UM\r
+**\r
+** ###################################################################\r
+*/\r
+\r
+/*!\r
+ * @file LPC55S69_cm33_core0\r
+ * @version 1.0\r
+ * @date 2018-08-22\r
+ * @brief Device specific configuration file for LPC55S69_cm33_core0 (header\r
+ * file)\r
+ *\r
+ * Provides a system configuration function and a global variable that contains\r
+ * the system frequency. It configures the device and initializes the oscillator\r
+ * (PLL) that is part of the microcontroller device.\r
+ */\r
+\r
+#ifndef _SYSTEM_LPC55S69_cm33_core0_H_\r
+#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdint.h>\r
+\r
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */\r
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */\r
+#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */\r
+#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */\r
+#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */\r
+#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */\r
+\r
+\r
+/**\r
+ * @brief System clock frequency (core clock)\r
+ *\r
+ * The system clock frequency supplied to the SysTick timer and the processor\r
+ * core clock. This variable can be used by the user application to setup the\r
+ * SysTick timer or configure other parameters. It may also be used by debugger to\r
+ * query the frequency of the debug timer or configure the trace clock speed\r
+ * SystemCoreClock is initialized with a correct predefined value.\r
+ */\r
+extern uint32_t SystemCoreClock;\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ *\r
+ * Typically this function configures the oscillator (PLL) that is part of the\r
+ * microcontroller device. For systems with variable clock speed it also updates\r
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.\r
+ */\r
+void SystemInit (void);\r
+\r
+/**\r
+ * @brief Updates the SystemCoreClock variable.\r
+ *\r
+ * It must be called whenever the core clock is changed during program\r
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates\r
+ * the current core clock.\r
+ */\r
+void SystemCoreClockUpdate (void);\r
+\r
+/**\r
+ * @brief SystemInit function hook.\r
+ *\r
+ * This weak function allows to call specific initialization code during the\r
+ * SystemInit() execution.This can be used when an application specific code needs\r
+ * to be called as close to the reset entry as possible (for example the Multicore\r
+ * Manager MCMGR_EarlyInit() function call).\r
+ * NOTE: No global r/w variables can be used in this hook function because the\r
+ * initialization of these variables happens after this function.\r
+ */\r
+void SystemInitHook (void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2017 - 2018 , NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_clock.h"\r
+#include "fsl_power.h"\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.clock"\r
+#endif\r
+#define NVALMAX (0x100U)\r
+#define PVALMAX (0x20U)\r
+#define MVALMAX (0x10000U)\r
+\r
+#define PLL_MAX_N_DIV 0x100U\r
+\r
+/*--------------------------------------------------------------------------\r
+!!! If required these #defines can be moved to chip library file\r
+----------------------------------------------------------------------------*/\r
+\r
+#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 16 downto 0 */\r
+#define PLL_SSCG1_MDEC_VAL_M (0x3FFFC00ULL << PLL_SSCG1_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */\r
+#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */\r
+#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P)\r
+#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */\r
+#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P)\r
+\r
+#define PLL_MIN_CCO_FREQ_MHZ (275000000U)\r
+#define PLL_MAX_CCO_FREQ_MHZ (550000000U)\r
+#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */\r
+#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */\r
+#define PLL_MIN_IN_SSMODE (3000000U)\r
+#define PLL_MAX_IN_SSMODE (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */\r
+\r
+/* PLL NDEC reg */\r
+#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M)\r
+/* PLL PDEC reg */\r
+#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M)\r
+/* SSCG control0 */\r
+#define PLL_SSCG1_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M)\r
+\r
+/* PLL0 SSCG control1 */\r
+#define PLL0_SSCG_MD_FRACT_P 0U\r
+#define PLL0_SSCG_MD_INT_P 25U\r
+#define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P)\r
+#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P)\r
+\r
+#define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M)\r
+#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M)\r
+\r
+/* Saved value of PLL output rate, computed whenever needed to save run-time\r
+ computation on each call to retrive the PLL rate. */\r
+static uint32_t s_Pll0_Freq;\r
+static uint32_t s_Pll1_Freq;\r
+\r
+/** External clock rate on the CLKIN pin in Hz. If not used,\r
+ set this to 0. Otherwise, set it to the exact rate in Hz this pin is\r
+ being driven at. */\r
+static uint32_t s_Ext_Clk_Freq = 16000000U;\r
+static uint32_t s_I2S_Mclk_Freq = 0U;\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */\r
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR);\r
+/* Get predivider (N) from PLL0 NDEC setting */\r
+static uint32_t findPll0PreDiv(void);\r
+/* Get predivider (N) from PLL1 NDEC setting */\r
+static uint32_t findPll1PreDiv(void);\r
+/* Get postdivider (P) from PLL0 PDEC setting */\r
+static uint32_t findPll0PostDiv(void);\r
+/* Get multiplier (M) from PLL0 MDEC and SSCG settings */\r
+static float findPll0MMult(void);\r
+/* Get the greatest common divisor */\r
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);\r
+/* Set PLL output based on desired output rate */\r
+static pll_error_t CLOCK_GetPll0Config(\r
+ uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS);\r
+/* Update local PLL rate variable */\r
+static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup);\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* Clock Selection for IP */\r
+/**\r
+ * brief Configure the clock selection muxes.\r
+ * param connection : Clock to be configured.\r
+ * return Nothing\r
+ */\r
+void CLOCK_AttachClk(clock_attach_id_t connection)\r
+{\r
+ uint8_t mux;\r
+ uint8_t sel;\r
+ uint16_t item;\r
+ uint32_t i;\r
+ volatile uint32_t *pClkSel;\r
+\r
+ pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);\r
+\r
+ if (connection != kNONE_to_NONE)\r
+ {\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ if (connection == 0U)\r
+ {\r
+ break;\r
+ }\r
+ item = (uint16_t)GET_ID_ITEM(connection);\r
+ if (item)\r
+ {\r
+ mux = GET_ID_ITEM_MUX(item);\r
+ sel = GET_ID_ITEM_SEL(item);\r
+ if (mux == CM_RTCOSC32KCLKSEL)\r
+ {\r
+ PMC->RTCOSC32K |= sel;\r
+ }\r
+ else\r
+ {\r
+ pClkSel[mux] = sel;\r
+ }\r
+ }\r
+ connection = GET_ID_NEXT_ITEM(connection); /* pick up next descriptor */\r
+ }\r
+ }\r
+}\r
+\r
+/* Return the actual clock attach id */\r
+/**\r
+ * brief Get the actual clock attach id.\r
+ * This fuction uses the offset in input attach id, then it reads the actual source value in\r
+ * the register and combine the offset to obtain an actual attach id.\r
+ * param attachId : Clock attach id to get.\r
+ * return Clock source value.\r
+ */\r
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId)\r
+{\r
+ uint8_t mux;\r
+ uint8_t actualSel;\r
+ uint32_t i;\r
+ uint32_t actualAttachId = 0U;\r
+ uint32_t selector = GET_ID_SELECTOR(attachId);\r
+ volatile uint32_t *pClkSel;\r
+\r
+ pClkSel = &(SYSCON->SYSTICKCLKSELX[0]);\r
+\r
+ if (attachId == kNONE_to_NONE)\r
+ {\r
+ return kNONE_to_NONE;\r
+ }\r
+\r
+ for (i = 0U; i < 2U; i++)\r
+ {\r
+ mux = GET_ID_ITEM_MUX(attachId);\r
+ if (attachId)\r
+ {\r
+ if (mux == CM_RTCOSC32KCLKSEL)\r
+ {\r
+ actualSel = PMC->RTCOSC32K;\r
+ }\r
+ else\r
+ {\r
+ actualSel = pClkSel[mux];\r
+ }\r
+\r
+ /* Consider the combination of two registers */\r
+ actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i);\r
+ }\r
+ attachId = GET_ID_NEXT_ITEM(attachId); /*!< pick up next descriptor */\r
+ }\r
+\r
+ actualAttachId |= selector;\r
+\r
+ return (clock_attach_id_t)actualAttachId;\r
+}\r
+\r
+/* Set IP Clock Divider */\r
+/**\r
+ * brief Setup peripheral clock dividers.\r
+ * param div_name : Clock divider name\r
+ * param divided_by_value: Value to be divided\r
+ * param reset : Whether to reset the divider counter.\r
+ * return Nothing\r
+ */\r
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset)\r
+{\r
+ volatile uint32_t *pClkDiv;\r
+\r
+ pClkDiv = &(SYSCON->SYSTICKCLKDIV0);\r
+ if (reset)\r
+ {\r
+ pClkDiv[div_name] = 1U << 29U;\r
+ }\r
+ if (divided_by_value == 0U) /*!< halt */\r
+ {\r
+ pClkDiv[div_name] = 1U << 30U;\r
+ }\r
+ else\r
+ {\r
+ pClkDiv[div_name] = (divided_by_value - 1U);\r
+ }\r
+}\r
+\r
+/* Set RTC 1KHz Clock Divider */\r
+/**\r
+ * brief Setup rtc 1khz clock divider.\r
+ * param divided_by_value: Value to be divided\r
+ * return Nothing\r
+ */\r
+void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value)\r
+{\r
+ PMC->RTCOSC32K |= (((divided_by_value - 28U) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT) | PMC_RTCOSC32K_CLK1KHZDIV_MASK);\r
+}\r
+\r
+/* Set RTC 1KHz Clock Divider */\r
+/**\r
+ * brief Setup rtc 1hz clock divider.\r
+ * param divided_by_value: Value to be divided\r
+ * return Nothing\r
+ */\r
+void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value)\r
+{\r
+ if (divided_by_value == 0U) /*!< halt */\r
+ {\r
+ PMC->RTCOSC32K |= (1U << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ PMC->RTCOSC32K |=\r
+ (((divided_by_value - 31744U) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT) | PMC_RTCOSC32K_CLK1HZDIV_MASK);\r
+ }\r
+}\r
+\r
+/* Set FRO Clocking */\r
+/**\r
+ * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).\r
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is\r
+ * enabled.\r
+ * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)\r
+ * return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupFROClocking(uint32_t iFreq)\r
+{\r
+ if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U))\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+ /* Enable Analog Control module */\r
+ SYSCON->PRESETCTRLCLR[2] = (1U << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT);\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK;\r
+ /* Power up the FRO192M */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M);\r
+\r
+ if (iFreq == 96000000U)\r
+ {\r
+ ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1);\r
+ }\r
+ else if (iFreq == 48000000U)\r
+ {\r
+ ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1);\r
+ }\r
+ else\r
+ {\r
+ ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1);\r
+ }\r
+ return 0U;\r
+}\r
+\r
+/* Set the FLASH wait states for the passed frequency */\r
+/**\r
+ * brief Set the flash wait states for the input freuqency.\r
+ * param iFreq : Input frequency\r
+ * return Nothing\r
+ */\r
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)\r
+{\r
+ uint32_t num_wait_states;\r
+ float f_num_wait_states = 0.00000009 * ((float)iFreq);\r
+ /* Rational : timing is closed at 100MHz+10% tolerance, hence the ¡®9¡¯ in the formula above */\r
+ num_wait_states = (uint32_t)f_num_wait_states;\r
+\r
+ /*\r
+ * It is guaranteed by design that "num_wait_states = 8"\r
+ * will fit all frequencies (below and including) 100 MHz.\r
+ */\r
+ if (num_wait_states >= 9)\r
+ {\r
+ num_wait_states = 8;\r
+ }\r
+\r
+ /* Don't alter other bits */\r
+ SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FMCTIM_MASK) |\r
+ ((num_wait_states << SYSCON_FMCCR_FMCTIM_SHIFT) & SYSCON_FMCCR_FMCTIM_MASK);\r
+}\r
+\r
+/* Set EXT OSC Clk */\r
+/**\r
+ * brief Initialize the external osc clock to given frequency.\r
+ * param iFreq : Desired frequency (must be equal to exact rate in Hz)\r
+ * return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupExtClocking(uint32_t iFreq)\r
+{\r
+ if (iFreq >= 32000000U)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+ /* Turn on power for crystal 32 MHz */\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);\r
+ /* Enable clock_in clock for clock module. */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;\r
+\r
+ s_Ext_Clk_Freq = iFreq;\r
+ return 0U;\r
+}\r
+\r
+/* Set I2S MCLK Clk */\r
+/**\r
+ * brief Initialize the I2S MCLK clock to given frequency.\r
+ * param iFreq : Desired frequency (must be equal to exact rate in Hz)\r
+ * return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq)\r
+{\r
+ s_I2S_Mclk_Freq = iFreq;\r
+ return 0U;\r
+}\r
+\r
+/* Get CLOCK OUT Clk */\r
+/*! brief Return Frequency of ClockOut\r
+ * return Frequency of ClockOut\r
+ */\r
+uint32_t CLOCK_GetClockOutClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->CLKOUTSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+\r
+ case 2U:\r
+ freq = CLOCK_GetExtClkFreq();\r
+ break;\r
+\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+\r
+ case 4U:\r
+ freq = CLOCK_GetFro1MFreq();\r
+ break;\r
+\r
+ case 5U:\r
+ freq = CLOCK_GetPll1OutFreq();\r
+ break;\r
+\r
+ case 6U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+ return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get ADC Clk */\r
+/*! brief Return Frequency of Adc Clock\r
+ * return Frequency of Adc.\r
+ */\r
+uint32_t CLOCK_GetAdcClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->ADCCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->ADCCLKDIV & SYSCON_ADCCLKDIV_DIV_MASK) + 1U);\r
+}\r
+\r
+/* Get USB0 Clk */\r
+/*! brief Return Frequency of Usb0 Clock\r
+ * return Frequency of Usb0 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb0ClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->USB0CLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 5U:\r
+ freq = CLOCK_GetPll1OutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get USB1 Clk */\r
+/*! brief Return Frequency of Usb1 Clock\r
+ * return Frequency of Usb1 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb1ClkFreq(void)\r
+{\r
+ return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) ? s_Ext_Clk_Freq : 0U;\r
+}\r
+\r
+/* Get MCLK Clk */\r
+/*! brief Return Frequency of MClk Clock\r
+ * return Frequency of MClk Clock.\r
+ */\r
+uint32_t CLOCK_GetMclkClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->MCLKCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get SCTIMER Clk */\r
+/*! brief Return Frequency of SCTimer Clock\r
+ * return Frequency of SCTimer Clock.\r
+ */\r
+uint32_t CLOCK_GetSctClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->SCTCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetExtClkFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 5U:\r
+ freq = CLOCK_GetI2SMClkFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get SDIO Clk */\r
+/*! brief Return Frequency of SDIO Clock\r
+ * return Frequency of SDIO Clock.\r
+ */\r
+uint32_t CLOCK_GetSdioClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->SDIOCLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 5U:\r
+ freq = CLOCK_GetPll1OutFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U);\r
+}\r
+\r
+/* Get FRO 12M Clk */\r
+/*! brief Return Frequency of FRO 12MHz\r
+ * return Frequency of FRO 12MHz\r
+ */\r
+uint32_t CLOCK_GetFro12MFreq(void)\r
+{\r
+ return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
+ 0 :\r
+ (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;\r
+}\r
+\r
+/* Get FRO 1M Clk */\r
+/*! brief Return Frequency of FRO 1MHz\r
+ * return Frequency of FRO 1MHz\r
+ */\r
+uint32_t CLOCK_GetFro1MFreq(void)\r
+{\r
+ return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;\r
+}\r
+\r
+/* Get EXT OSC Clk */\r
+/*! brief Return Frequency of External Clock\r
+ * return Frequency of External Clock. If no external clock is used returns 0.\r
+ */\r
+uint32_t CLOCK_GetExtClkFreq(void)\r
+{\r
+ return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? s_Ext_Clk_Freq : 0U;\r
+}\r
+\r
+/* Get WATCH DOG Clk */\r
+/*! brief Return Frequency of Watchdog\r
+ * return Frequency of Watchdog\r
+ */\r
+uint32_t CLOCK_GetWdtClkFreq(void)\r
+{\r
+ return CLOCK_GetFro1MFreq() / ((SYSCON->WDTCLKDIV & SYSCON_WDTCLKDIV_DIV_MASK) + 1U);\r
+}\r
+\r
+/* Get HF FRO Clk */\r
+/*! brief Return Frequency of High-Freq output of FRO\r
+ * return Frequency of High-Freq output of FRO\r
+ */\r
+uint32_t CLOCK_GetFroHfFreq(void)\r
+{\r
+ return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?\r
+ 0 :\r
+ (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;\r
+}\r
+\r
+/* Get SYSTEM PLL Clk */\r
+/*! brief Return Frequency of PLL\r
+ * return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPll0OutFreq(void)\r
+{\r
+ return s_Pll0_Freq;\r
+}\r
+\r
+/* Get USB PLL Clk */\r
+/*! brief Return Frequency of USB PLL\r
+ * return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPll1OutFreq(void)\r
+{\r
+ return s_Pll1_Freq;\r
+}\r
+\r
+/* Get RTC OSC Clk */\r
+/*! brief Return Frequency of 32kHz osc\r
+ * return Frequency of 32kHz osc\r
+ */\r
+uint32_t CLOCK_GetOsc32KFreq(void)\r
+{\r
+ return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?\r
+ CLK_RTC_32K_CLK :\r
+ ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?\r
+ CLK_RTC_32K_CLK :\r
+ 0U;\r
+}\r
+\r
+/* Get MAIN Clk */\r
+/*! brief Return Frequency of Core System\r
+ * return Frequency of Core System\r
+ */\r
+uint32_t CLOCK_GetCoreSysClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->MAINCLKSELB)\r
+ {\r
+ case 0U:\r
+ if (SYSCON->MAINCLKSELA == 0U)\r
+ {\r
+ freq = CLOCK_GetFro12MFreq();\r
+ }\r
+ else if (SYSCON->MAINCLKSELA == 1U)\r
+ {\r
+ freq = CLOCK_GetExtClkFreq();\r
+ }\r
+ else if (SYSCON->MAINCLKSELA == 2U)\r
+ {\r
+ freq = CLOCK_GetFro1MFreq();\r
+ }\r
+ else if (SYSCON->MAINCLKSELA == 3U)\r
+ {\r
+ freq = CLOCK_GetFroHfFreq();\r
+ }\r
+ else\r
+ {\r
+ }\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetPll1OutFreq();\r
+ break;\r
+\r
+ case 3U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get I2S MCLK Clk */\r
+/*! brief Return Frequency of I2S MCLK Clock\r
+ * return Frequency of I2S MCLK Clock\r
+ */\r
+uint32_t CLOCK_GetI2SMClkFreq(void)\r
+{\r
+ return s_I2S_Mclk_Freq;\r
+}\r
+\r
+/* Get FLEXCOMM input clock */\r
+/*! brief Return Frequency of flexcomm input clock\r
+ * param id : flexcomm instance id\r
+ * return Frequency value\r
+ */\r
+uint32_t CLOCK_GetFlexCommInputClock(uint32_t id)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->FCCLKSELX[id])\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U);\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U);\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetFro1MFreq();\r
+ break;\r
+ case 5U:\r
+ freq = CLOCK_GetI2SMClkFreq();\r
+ break;\r
+ case 6U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get FLEXCOMM Clk */\r
+uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ freq = CLOCK_GetFlexCommInputClock(id);\r
+ return freq / (1 +\r
+ (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) /\r
+ ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U));\r
+}\r
+\r
+/* Get HS_LPSI Clk */\r
+uint32_t CLOCK_GetHsLspiClkFreq(void)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->HSLSPICLKSEL)\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq() / ((SYSCON->PLL0CLKDIV & 0xffU) + 1U);\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U);\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetFro1MFreq();\r
+ break;\r
+ case 6U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get CTimer Clk */\r
+/*! brief Return Frequency of CTimer functional Clock\r
+ * return Frequency of CTimer functional Clock\r
+ */\r
+uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)\r
+{\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->CTIMERCLKSELX[id])\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case 3U:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case 4U:\r
+ freq = CLOCK_GetFro1MFreq();\r
+ break;\r
+ case 5U:\r
+ freq = CLOCK_GetI2SMClkFreq();\r
+ break;\r
+ case 6U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Get Systick Clk */\r
+/*! brief Return Frequency of SystickClock\r
+ * return Frequency of Systick Clock\r
+ */\r
+uint32_t CLOCK_GetSystickClkFreq(uint32_t id)\r
+{\r
+ volatile uint32_t *pSystickClkDiv;\r
+ pSystickClkDiv = &(SYSCON->SYSTICKCLKDIV0);\r
+ uint32_t freq = 0U;\r
+\r
+ switch (SYSCON->SYSTICKCLKSELX[id])\r
+ {\r
+ case 0U:\r
+ freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U);\r
+ break;\r
+ case 1U:\r
+ freq = CLOCK_GetFro1MFreq();\r
+ break;\r
+ case 2U:\r
+ freq = CLOCK_GetOsc32KFreq();\r
+ break;\r
+ case 7U:\r
+ freq = 0U;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return freq;\r
+}\r
+\r
+/* Set FlexComm Clock */\r
+/**\r
+ * brief Set the flexcomm output frequency.\r
+ * param id : flexcomm instance id\r
+ * freq : output frequency\r
+ * return 0 : the frequency range is out of range.\r
+ * 1 : switch successfully.\r
+ */\r
+uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq)\r
+{\r
+ uint32_t input = CLOCK_GetFlexCommClkFreq(id);\r
+ uint32_t mul;\r
+\r
+ if ((freq > 48000000) || (freq > input) || (input / freq >= 2))\r
+ {\r
+ /* FRG output frequency should be less than equal to 48MHz */\r
+ return 0;\r
+ }\r
+ else\r
+ {\r
+ mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq);\r
+ SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU;\r
+ return 1;\r
+ }\r
+}\r
+\r
+/* Get IP Clk */\r
+/*! brief Return Frequency of selected clock\r
+ * return Frequency of selected clock\r
+ */\r
+uint32_t CLOCK_GetFreq(clock_name_t clockName)\r
+{\r
+ uint32_t freq;\r
+ switch (clockName)\r
+ {\r
+ case kCLOCK_CoreSysClk:\r
+ freq = CLOCK_GetCoreSysClkFreq();\r
+ break;\r
+ case kCLOCK_BusClk:\r
+ freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);\r
+ break;\r
+ case kCLOCK_ClockOut:\r
+ freq = CLOCK_GetClockOutClkFreq();\r
+ break;\r
+ case kCLOCK_Adc:\r
+ freq = CLOCK_GetAdcClkFreq();\r
+ break;\r
+ case kCLOCK_Usb0:\r
+ freq = CLOCK_GetUsb0ClkFreq();\r
+ break;\r
+ case kCLOCK_Usb1:\r
+ freq = CLOCK_GetUsb1ClkFreq();\r
+ break;\r
+ case kCLOCK_Pll1Out:\r
+ freq = CLOCK_GetPll1OutFreq();\r
+ break;\r
+ case kCLOCK_Mclk:\r
+ freq = CLOCK_GetMclkClkFreq();\r
+ break;\r
+ case kCLOCK_FroHf:\r
+ freq = CLOCK_GetFroHfFreq();\r
+ break;\r
+ case kCLOCK_Fro12M:\r
+ freq = CLOCK_GetFro12MFreq();\r
+ break;\r
+ case kCLOCK_ExtClk:\r
+ freq = CLOCK_GetExtClkFreq();\r
+ break;\r
+ case kCLOCK_Pll0Out:\r
+ freq = CLOCK_GetPll0OutFreq();\r
+ break;\r
+ case kCLOCK_WdtClk:\r
+ freq = CLOCK_GetWdtClkFreq();\r
+ break;\r
+ case kCLOCK_Sct:\r
+ freq = CLOCK_GetSctClkFreq();\r
+ break;\r
+ case kCLOCK_SDio:\r
+ freq = CLOCK_GetSdioClkFreq();\r
+ break;\r
+ case kCLOCK_FlexI2S:\r
+ freq = CLOCK_GetI2SMClkFreq();\r
+ break;\r
+ case kCLOCK_Flexcomm0:\r
+ freq = CLOCK_GetFlexCommClkFreq(0U);\r
+ break;\r
+ case kCLOCK_Flexcomm1:\r
+ freq = CLOCK_GetFlexCommClkFreq(1U);\r
+ break;\r
+ case kCLOCK_Flexcomm2:\r
+ freq = CLOCK_GetFlexCommClkFreq(2U);\r
+ break;\r
+ case kCLOCK_Flexcomm3:\r
+ freq = CLOCK_GetFlexCommClkFreq(3U);\r
+ break;\r
+ case kCLOCK_Flexcomm4:\r
+ freq = CLOCK_GetFlexCommClkFreq(4U);\r
+ break;\r
+ case kCLOCK_Flexcomm5:\r
+ freq = CLOCK_GetFlexCommClkFreq(5U);\r
+ break;\r
+ case kCLOCK_Flexcomm6:\r
+ freq = CLOCK_GetFlexCommClkFreq(6U);\r
+ break;\r
+ case kCLOCK_Flexcomm7:\r
+ freq = CLOCK_GetFlexCommClkFreq(7U);\r
+ break;\r
+ case kCLOCK_HsLspi:\r
+ freq = CLOCK_GetHsLspiClkFreq();\r
+ break;\r
+ case kCLOCK_CTmier0:\r
+ freq = CLOCK_GetCTimerClkFreq(0U);\r
+ break;\r
+ case kCLOCK_CTmier1:\r
+ freq = CLOCK_GetCTimerClkFreq(1U);\r
+ break;\r
+ case kCLOCK_CTmier2:\r
+ freq = CLOCK_GetCTimerClkFreq(2U);\r
+ break;\r
+ case kCLOCK_CTmier3:\r
+ freq = CLOCK_GetCTimerClkFreq(3U);\r
+ break;\r
+ case kCLOCK_CTmier4:\r
+ freq = CLOCK_GetCTimerClkFreq(4U);\r
+ break;\r
+ case kCLOCK_Systick0:\r
+ freq = CLOCK_GetSystickClkFreq(0U);\r
+ break;\r
+ case kCLOCK_Systick1:\r
+ freq = CLOCK_GetSystickClkFreq(1U);\r
+ break;\r
+ default:\r
+ freq = 0U;\r
+ break;\r
+ }\r
+ return freq;\r
+}\r
+\r
+/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */\r
+static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR)\r
+{\r
+ uint32_t seli, selp;\r
+ /* bandwidth: compute selP from Multiplier */\r
+ if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK)\r
+ {\r
+ selp = (M >> 2U) + 1U;\r
+ if (selp >= 31U)\r
+ {\r
+ selp = 31U;\r
+ }\r
+ *pSelP = selp;\r
+\r
+ if (M >= 32768)\r
+ {\r
+ seli = 1;\r
+ }\r
+ else if (M >= 16384)\r
+ {\r
+ seli = 2;\r
+ }\r
+ else if (M >= 4096)\r
+ {\r
+ seli = 4;\r
+ }\r
+ else if (M >= 1002)\r
+ {\r
+ seli = 8;\r
+ }\r
+ else if (M >= 120)\r
+ {\r
+ seli = 4 * ((1024/(M/2 + 9)) + 1);\r
+ }\r
+ else\r
+ {\r
+ seli = 4 * (M/8 + 1);\r
+ } \r
+\r
+ if (seli >= 63)\r
+ {\r
+ seli = 63;\r
+ }\r
+ *pSelI = seli;\r
+\r
+ *pSelR = 0U;\r
+ }\r
+ else\r
+ {\r
+ *pSelP = 3U;\r
+ *pSelI = 4U;\r
+ *pSelR = 4U;\r
+ }\r
+}\r
+\r
+/* Get predivider (N) from PLL0 NDEC setting */\r
+static uint32_t findPll0PreDiv(void)\r
+{\r
+ uint32_t preDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)\r
+ {\r
+ preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;\r
+ if (preDiv == 0)\r
+ {\r
+ preDiv = 1;\r
+ }\r
+ }\r
+ return preDiv;\r
+}\r
+\r
+/* Get predivider (N) from PLL1 NDEC setting */\r
+static uint32_t findPll1PreDiv(void)\r
+{\r
+ uint32_t preDiv = 1;\r
+\r
+ /* Direct input is not used? */\r
+ if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)\r
+ {\r
+ preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;\r
+ if (preDiv == 0)\r
+ {\r
+ preDiv = 1;\r
+ }\r
+ }\r
+ return preDiv;\r
+}\r
+\r
+/* Get postdivider (P) from PLL0 PDEC setting */\r
+static uint32_t findPll0PostDiv(void)\r
+{\r
+ uint32_t postDiv = 1;\r
+\r
+ if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)\r
+ {\r
+ if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)\r
+ {\r
+ postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;\r
+ }\r
+ else\r
+ {\r
+ postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);\r
+ }\r
+ if (postDiv == 0)\r
+ {\r
+ postDiv = 2;\r
+ }\r
+ }\r
+ return postDiv;\r
+}\r
+\r
+/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */\r
+static float findPll0MMult(void)\r
+{\r
+ float mMult = 1;\r
+ float mMult_fract;\r
+ uint32_t mMult_int;\r
+\r
+ if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)\r
+ {\r
+ mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;\r
+ }\r
+ else\r
+ {\r
+ mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P);\r
+ mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M)/(1 << PLL0_SSCG_MD_INT_P));\r
+ mMult = (float)mMult_int + mMult_fract;\r
+ }\r
+ if (mMult == 0)\r
+ {\r
+ mMult = 1;\r
+ }\r
+ return mMult;\r
+}\r
+\r
+\r
+/* Find greatest common divisor between m and n */\r
+static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)\r
+{\r
+ uint32_t tmp;\r
+\r
+ while (n != 0U)\r
+ {\r
+ tmp = n;\r
+ n = m % n;\r
+ m = tmp;\r
+ }\r
+\r
+ return m;\r
+}\r
+\r
+/*\r
+ * Set PLL0 output based on desired output rate.\r
+ * In this function, the it calculates the PLL0 setting for output frequency from input clock\r
+ * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently.\r
+ * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function.\r
+ */\r
+static pll_error_t CLOCK_GetPll0ConfigInternal(\r
+ uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)\r
+{\r
+ uint32_t nDivOutHz, fccoHz;\r
+ uint32_t pllPreDivider, pllMultiplier, pllPostDivider;\r
+ uint32_t pllDirectInput, pllDirectOutput;\r
+ uint32_t pllSelP, pllSelI, pllSelR, uplimoff;\r
+\r
+ /* Baseline parameters (no input or output dividers) */\r
+ pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */\r
+ pllPostDivider = 1U; /* 1 implies post-divider will be disabled */\r
+ pllDirectOutput = 1U;\r
+\r
+ /* Verify output rate parameter */\r
+ if (foutHz > PLL_MAX_CCO_FREQ_MHZ)\r
+ {\r
+ /* Maximum PLL output with post divider=1 cannot go above this frequency */\r
+ return kStatus_PLL_OutputTooHigh;\r
+ }\r
+ if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U)))\r
+ {\r
+ /* Minmum PLL output with maximum post divider cannot go below this frequency */\r
+ return kStatus_PLL_OutputTooLow;\r
+ }\r
+\r
+ /* If using SS mode, input clock needs to be between 3MHz and 20MHz */\r
+ if (useSS)\r
+ {\r
+ /* Verify input rate parameter */\r
+ if (finHz < PLL_MIN_IN_SSMODE)\r
+ {\r
+ /* Input clock into the PLL cannot be lower than this */\r
+ return kStatus_PLL_InputTooLow;\r
+ }\r
+ /* PLL input in SS mode must be under 20MHz */\r
+ if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX))\r
+ {\r
+ return kStatus_PLL_InputTooHigh;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Verify input rate parameter */\r
+ if (finHz < PLL_LOWER_IN_LIMIT)\r
+ {\r
+ /* Input clock into the PLL cannot be lower than this */\r
+ return kStatus_PLL_InputTooLow;\r
+ }\r
+ if (finHz > PLL_HIGHER_IN_LIMIT)\r
+ {\r
+ /* Input clock into the PLL cannot be higher than this */\r
+ return kStatus_PLL_InputTooHigh;\r
+ }\r
+ }\r
+\r
+ /* Find the optimal CCO frequency for the output and input that\r
+ will keep it inside the PLL CCO range. This may require\r
+ tweaking the post-divider for the PLL. */\r
+ fccoHz = foutHz;\r
+ while (fccoHz < PLL_MIN_CCO_FREQ_MHZ)\r
+ {\r
+ /* CCO output is less than minimum CCO range, so the CCO output\r
+ needs to be bumped up and the post-divider is used to bring\r
+ the PLL output back down. */\r
+ pllPostDivider++;\r
+ if (pllPostDivider > PVALMAX)\r
+ {\r
+ return kStatus_PLL_OutsideIntLimit;\r
+ }\r
+\r
+ /* Target CCO goes up, PLL output goes down */\r
+ /* divide-by-2 divider in the post-divider is always work*/\r
+ fccoHz = foutHz * (pllPostDivider * 2U);\r
+ pllDirectOutput = 0U;\r
+ }\r
+\r
+ /* Determine if a pre-divider is needed to get the best frequency */\r
+ if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false))\r
+ {\r
+ uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz);\r
+\r
+ if (a > PLL_LOWER_IN_LIMIT)\r
+ {\r
+ a = finHz / a;\r
+ if ((a != 0U) && (a < PLL_MAX_N_DIV))\r
+ {\r
+ pllPreDivider = a;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Bypass pre-divider hardware if pre-divider is 1 */\r
+ if (pllPreDivider > 1U)\r
+ {\r
+ pllDirectInput = 0U;\r
+ }\r
+ else\r
+ {\r
+ pllDirectInput = 1U;\r
+ }\r
+\r
+ /* Determine PLL multipler */\r
+ nDivOutHz = (finHz / pllPreDivider);\r
+ pllMultiplier = (fccoHz / nDivOutHz);\r
+\r
+ /* Find optimal values for filter */\r
+ if (useSS == false)\r
+ {\r
+ /* Will bumping up M by 1 get us closer to the desired CCO frequency? */\r
+ if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U))\r
+ {\r
+ pllMultiplier++;\r
+ }\r
+\r
+ /* Setup filtering */\r
+ pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR);\r
+ uplimoff = 0U;\r
+\r
+ /* Get encoded value for M (mult) and use manual filter, disable SS mode */\r
+ pSetup->pllsscg[1] = (PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1U << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ uint64_t fc;\r
+\r
+ /* Filtering will be handled by SSC */\r
+ pllSelR = pllSelI = pllSelP = 0U;\r
+ uplimoff = 1U;\r
+\r
+ /* The PLL multiplier will get very close and slightly under the\r
+ desired target frequency. A small fractional component can be\r
+ added to fine tune the frequency upwards to the target. */\r
+ fc = ((uint64_t)(fccoHz % nDivOutHz) << 25U) / nDivOutHz;\r
+\r
+ /* Set multiplier */\r
+ pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc));\r
+ pSetup->pllsscg[1] = PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U;\r
+ }\r
+\r
+ /* Get encoded values for N (prediv) and P (postdiv) */\r
+ pSetup->pllndec = PLL_NDEC_VAL_SET(pllPreDivider);\r
+ pSetup->pllpdec = PLL_PDEC_VAL_SET(pllPostDivider);\r
+\r
+ /* PLL control */\r
+ pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */\r
+ (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */\r
+ (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */\r
+ (0 << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */\r
+ (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */\r
+ (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */\r
+ (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */\r
+ (1 << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+/* Alloct the static buffer for cache. */\r
+static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT];\r
+static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
+static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0};\r
+static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false};\r
+static uint32_t s_PllSetupCacheIdx = 0U;\r
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
+\r
+/*\r
+ * Calculate the PLL setting values from input clock freq to output freq.\r
+ */\r
+static pll_error_t CLOCK_GetPll0Config(\r
+ uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS)\r
+{\r
+ pll_error_t retErr;\r
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+ uint32_t i;\r
+\r
+ for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++)\r
+ {\r
+ if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i]))\r
+ {\r
+ /* Hit the target in cache buffer. */\r
+ pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl;\r
+ pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec;\r
+ pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec;\r
+ pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0];\r
+ pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1];\r
+ retErr = kStatus_PLL_Success;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+ {\r
+ return retErr;\r
+ }\r
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
+\r
+ retErr = CLOCK_GetPll0ConfigInternal(finHz, foutHz, pSetup, useSS);\r
+\r
+#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT)\r
+ /* Cache the most recent calulation result into buffer. */\r
+ s_FinHzCache[s_PllSetupCacheIdx] = finHz;\r
+ s_FoutHzCache[s_PllSetupCacheIdx] = foutHz;\r
+ s_UseSSCache[s_PllSetupCacheIdx] = useSS;\r
+\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl;\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec;\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec;\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0];\r
+ s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1];\r
+ /* Update the index for next available buffer. */\r
+ s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT;\r
+#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */\r
+\r
+ return retErr;\r
+}\r
+\r
+/* Update local PLL rate variable */\r
+static void CLOCK_GetPLL0OutFromSetupUpdate(pll_setup_t *pSetup)\r
+{\r
+ s_Pll0_Freq = CLOCK_GetPLL0OutFromSetup(pSetup);\r
+}\r
+\r
+/* Return System PLL input clock rate */\r
+/*! brief Return PLL0 input clock rate\r
+* return PLL0 input clock rate\r
+*/\r
+uint32_t CLOCK_GetPLL0InClockRate(void)\r
+{\r
+ uint32_t clkRate = 0U;\r
+\r
+ switch ((SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK))\r
+ {\r
+ case 0x00U:\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+\r
+ case 0x01U:\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+\r
+ case 0x02U:\r
+ clkRate = CLOCK_GetFro1MFreq();\r
+ break;\r
+\r
+ case 0x03U:\r
+ clkRate = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ default:\r
+ clkRate = 0U;\r
+ break;\r
+ }\r
+\r
+ return clkRate;\r
+}\r
+\r
+/* Return PLL1 input clock rate */\r
+uint32_t CLOCK_GetPLL1InClockRate(void)\r
+{\r
+ uint32_t clkRate = 0U;\r
+\r
+ switch ((SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK))\r
+ {\r
+ case 0x00U:\r
+ clkRate = CLK_FRO_12MHZ;\r
+ break;\r
+\r
+ case 0x01U:\r
+ clkRate = CLOCK_GetExtClkFreq();\r
+ break;\r
+\r
+ case 0x02U:\r
+ clkRate = CLOCK_GetFro1MFreq();\r
+ break;\r
+\r
+ case 0x03U:\r
+ clkRate = CLOCK_GetOsc32KFreq();\r
+ break;\r
+\r
+ default:\r
+ clkRate = 0U;\r
+ break;\r
+ }\r
+\r
+ return clkRate;\r
+}\r
+\r
+/* Return PLL0 output clock rate from setup structure */\r
+/*! brief Return PLL0 output clock rate from setup structure\r
+* param pSetup : Pointer to a PLL setup structure\r
+* return PLL0 output clock rate the setup structure will generate\r
+*/\r
+uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup)\r
+{\r
+ uint32_t clkRate = 0;\r
+ uint32_t prediv, postdiv;\r
+ float workRate = 0;\r
+\r
+ /* Get the input clock frequency of PLL. */\r
+ clkRate = CLOCK_GetPLL0InClockRate();\r
+\r
+ if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))\r
+ {\r
+ prediv = findPll0PreDiv();\r
+ postdiv = findPll0PostDiv();\r
+ /* Adjust input clock */\r
+ clkRate = clkRate / prediv;\r
+ /* MDEC used for rate */\r
+ workRate = (float)clkRate * (float)findPll0MMult();\r
+ clkRate = (uint32_t)(workRate / ((float)postdiv));\r
+ }\r
+\r
+ return (uint32_t)workRate;\r
+}\r
+\r
+/* Set the current PLL0 Rate */\r
+/*! brief Store the current PLL rate\r
+* param rate: Current rate of the PLL\r
+* return Nothing\r
+**/\r
+void CLOCK_SetStoredPLL0ClockRate(uint32_t rate)\r
+{\r
+ s_Pll0_Freq = rate;\r
+}\r
+\r
+/* Return PLL0 output clock rate */\r
+/*! brief Return PLL0 output clock rate\r
+* param recompute : Forces a PLL rate recomputation if true\r
+* return PLL0 output clock rate\r
+* note The PLL rate is cached in the driver in a variable as\r
+* the rate computation function can take some time to perform. It\r
+* is recommended to use 'false' with the 'recompute' parameter.\r
+*/\r
+uint32_t CLOCK_GetPLL0OutClockRate(bool recompute)\r
+{\r
+ pll_setup_t Setup;\r
+ uint32_t rate;\r
+\r
+ if ((recompute) || (s_Pll0_Freq == 0U))\r
+ {\r
+ Setup.pllctrl = SYSCON->PLL0CTRL;\r
+ Setup.pllndec = SYSCON->PLL0NDEC;\r
+ Setup.pllpdec = SYSCON->PLL0PDEC;\r
+ Setup.pllsscg[0] = SYSCON->PLL0SSCG0;\r
+ Setup.pllsscg[1] = SYSCON->PLL0SSCG1;\r
+\r
+ CLOCK_GetPLL0OutFromSetupUpdate(&Setup);\r
+ }\r
+\r
+ rate = s_Pll0_Freq;\r
+\r
+ return rate;\r
+}\r
+\r
+/* Set PLL0 output based on the passed PLL setup data */\r
+/*! brief Set PLL output based on the passed PLL setup data\r
+* param pControl : Pointer to populated PLL control structure to generate setup with\r
+* param pSetup : Pointer to PLL setup structure to be filled\r
+* return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+* note Actual frequency for setup may vary from the desired frequency based on the\r
+* accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+*/\r
+pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup)\r
+{\r
+ uint32_t inRate;\r
+ bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U);\r
+\r
+ pll_error_t pllError;\r
+\r
+ /* Determine input rate for the PLL */\r
+ if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U)\r
+ {\r
+ inRate = pControl->inputRate;\r
+ }\r
+ else\r
+ {\r
+ inRate = CLOCK_GetPLL0InClockRate();\r
+ }\r
+\r
+ /* PLL flag options */\r
+ pllError = CLOCK_GetPll0Config(inRate, pControl->desiredRate, pSetup, useSS);\r
+ if ((useSS) && (pllError == kStatus_PLL_Success))\r
+ {\r
+ /* If using SS mode, then some tweaks are made to the generated setup */\r
+ pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc;\r
+ if (pControl->mfDither)\r
+ {\r
+ pSetup->pllsscg[1] |= (1U << SYSCON_PLL0SSCG1_DITHER_SHIFT);\r
+ }\r
+ }\r
+\r
+ return pllError;\r
+}\r
+\r
+/* Set PLL0 output from PLL setup structure */\r
+/*! brief Set PLL output from PLL setup structure (precise frequency)\r
+* param pSetup : Pointer to populated PLL setup structure\r
+* param flagcfg : Flag configuration for PLL config structure\r
+* return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+* note This function will power off the PLL, setup the PLL with the\r
+* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+* and adjust system voltages to the new PLL rate. The function will not\r
+* alter any source clocks (ie, main systen clock) that may use the PLL,\r
+* so these should be setup prior to and after exiting the function.\r
+*/\r
+pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg)\r
+{ \r
+ uint32_t inRate, clkRate, prediv;\r
+\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_PLL0);\r
+ POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
+\r
+ pSetup->flags = flagcfg;\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->PLL0CTRL = pSetup->pllctrl;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec;\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];\r
+ SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];\r
+ SYSCON->PLL0SSCG1 =\r
+ pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0);\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
+\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ inRate = CLOCK_GetPLL0InClockRate();\r
+ prediv = findPll0PreDiv();\r
+ /* Adjust input clock */\r
+ clkRate = inRate / prediv;\r
+ /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
+ if ((clkRate >= 100000) && (clkRate <= 20000000))\r
+ {\r
+ while (CLOCK_IsPLL0Locked() == false)\r
+ {\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ CLOCK_GetPLL0OutFromSetupUpdate(pSetup);\r
+\r
+ /* System voltage adjustment, occurs prior to setting main system clock */\r
+ if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U)\r
+ {\r
+ POWER_SetVoltageForFreq(s_Pll0_Freq);\r
+ }\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Setup PLL Frequency from pre-calculated value */\r
+/**\r
+* brief Set PLL0 output from PLL setup structure (precise frequency)\r
+* param pSetup : Pointer to populated PLL setup structure\r
+* return kStatus_PLL_Success on success, or PLL setup error code\r
+* note This function will power off the PLL, setup the PLL with the\r
+* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+* and adjust system voltages to the new PLL rate. The function will not\r
+* alter any source clocks (ie, main systen clock) that may use the PLL,\r
+* so these should be setup prior to and after exiting the function.\r
+*/\r
+pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup)\r
+{\r
+ uint32_t inRate, clkRate, prediv;\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_PLL0);\r
+ POWER_EnablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->PLL0CTRL = pSetup->pllctrl;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec;\r
+ SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec;\r
+ SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->PLL0SSCG0 = pSetup->pllsscg[0];\r
+ SYSCON->PLL0SSCG1 = pSetup->pllsscg[1];\r
+ SYSCON->PLL0SSCG1 =\r
+ pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0);\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);\r
+\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ inRate = CLOCK_GetPLL0InClockRate();\r
+ prediv = findPll0PreDiv();\r
+ /* Adjust input clock */\r
+ clkRate = inRate / prediv;\r
+ /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
+ if ((clkRate >= 100000) && (clkRate <= 20000000))\r
+ {\r
+ while (CLOCK_IsPLL0Locked() == false)\r
+ {\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ s_Pll0_Freq = pSetup->pllRate;\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Setup PLL1 Frequency from pre-calculated value */\r
+/**\r
+* brief Set PLL1 output from PLL setup structure (precise frequency)\r
+* param pSetup : Pointer to populated PLL setup structure\r
+* return kStatus_PLL_Success on success, or PLL setup error code\r
+* note This function will power off the PLL, setup the PLL with the\r
+* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+* and adjust system voltages to the new PLL rate. The function will not\r
+* alter any source clocks (ie, main systen clock) that may use the PLL,\r
+* so these should be setup prior to and after exiting the function.\r
+*/\r
+pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)\r
+{\r
+ uint32_t inRate, clkRate, prediv;\r
+ /* Power off PLL during setup changes */\r
+ POWER_EnablePD(kPDRUNCFG_PD_PLL1);\r
+\r
+ /* Write PLL setup data */\r
+ SYSCON->PLL1CTRL = pSetup->pllctrl;\r
+ SYSCON->PLL1NDEC = pSetup->pllndec;\r
+ SYSCON->PLL1NDEC = pSetup->pllndec | (1U << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */\r
+ SYSCON->PLL1PDEC = pSetup->pllpdec;\r
+ SYSCON->PLL1PDEC = pSetup->pllpdec | (1U << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */\r
+ SYSCON->PLL1MDEC = pSetup->pllmdec;\r
+ SYSCON->PLL1MDEC = pSetup->pllmdec | (1U << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
+\r
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)\r
+ {\r
+ inRate = CLOCK_GetPLL1InClockRate();\r
+ prediv = findPll1PreDiv();\r
+ /* Adjust input clock */\r
+ clkRate = inRate / prediv;\r
+ /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */\r
+ if ((clkRate >= 100000) && (clkRate <= 20000000))\r
+ {\r
+ while (CLOCK_IsPLL1Locked() == false)\r
+ {\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Update current programmed PLL rate var */\r
+ s_Pll0_Freq = pSetup->pllRate;\r
+\r
+ return kStatus_PLL_Success;\r
+}\r
+\r
+/* Set PLL0 clock based on the input frequency and multiplier */\r
+/*! brief Set PLL0 output based on the multiplier and input frequency\r
+* param multiply_by : multiplier\r
+* param input_freq : Clock input frequency of the PLL\r
+* return Nothing\r
+* note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+* function does not disable or enable PLL power, wait for PLL lock,\r
+* or adjust system voltages. These must be done in the application.\r
+* The function will not alter any source clocks (ie, main systen clock)\r
+* that may use the PLL, so these should be setup prior to and after\r
+* exiting the function.\r
+*/\r
+void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq)\r
+{\r
+ uint32_t cco_freq = input_freq * multiply_by;\r
+ uint32_t pdec = 1U;\r
+ uint32_t selr;\r
+ uint32_t seli;\r
+ uint32_t selp;\r
+ uint32_t mdec, ndec;\r
+\r
+ while (cco_freq < 275000000U)\r
+ {\r
+ multiply_by <<= 1U; /* double value in each iteration */\r
+ pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */\r
+ cco_freq = input_freq * multiply_by;\r
+ }\r
+\r
+ selr = 0U;\r
+\r
+ if (multiply_by >= 32768)\r
+ {\r
+ seli = 1;\r
+ }\r
+ else if (multiply_by >= 16384)\r
+ {\r
+ seli = 2;\r
+ }\r
+ else if (multiply_by >= 4096)\r
+ {\r
+ seli = 4;\r
+ }\r
+ else if (multiply_by >= 1002)\r
+ {\r
+ seli = 8;\r
+ }\r
+ else if (multiply_by >= 120)\r
+ {\r
+ seli = 4 * ((1024/(multiply_by/2 + 9)) + 1);\r
+ }\r
+ else\r
+ {\r
+ seli = 4 * (multiply_by/8 + 1);\r
+ } \r
+\r
+ if (seli >= 63U)\r
+ {\r
+ seli = 63U;\r
+ }\r
+ selp = (multiply_by >> 2U) + 1U;\r
+ {\r
+ selp = 31U;\r
+ }\r
+\r
+ if (pdec > 1U)\r
+ {\r
+ pdec = pdec / 2U; /* Account for minus 1 encoding */\r
+ /* Translate P value */\r
+ }\r
+\r
+ mdec = PLL_SSCG1_MDEC_VAL_SET(multiply_by);\r
+ ndec = 0x1U; /* pre divide by 1 (hardcoded) */\r
+\r
+ SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK |SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) |\r
+ (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | (seli << SYSCON_PLL0CTRL_SELI_SHIFT) |\r
+ (selp << SYSCON_PLL0CTRL_SELP_SHIFT);\r
+ SYSCON->PLL0PDEC = pdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */\r
+ SYSCON->PLL0NDEC = ndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */\r
+ SYSCON->PLL0SSCG1 = mdec | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */\r
+}\r
+\r
+/* Enable USB DEVICE FULL SPEED clock */\r
+/*! brief Enable USB Device FS clock.\r
+* param src : clock source\r
+* param freq: clock frequency\r
+* Enable USB Device Full Speed clock.\r
+*/\r
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq)\r
+{\r
+ bool ret = true;\r
+\r
+ CLOCK_DisableClock(kCLOCK_Usbd0);\r
+\r
+ if (kCLOCK_UsbfsSrcFro == src)\r
+ {\r
+ switch (freq)\r
+ {\r
+ case 96000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ default:\r
+ ret = false;\r
+ break;\r
+ }\r
+ /* Turn ON FRO HF */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M);\r
+ /* Enable FRO 96MHz output */\r
+ ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;\r
+ /* Select FRO 96 or 48 MHz */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);\r
+ }\r
+ else\r
+ {\r
+ /*Set the USB PLL as the Usb0 CLK*/\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;\r
+\r
+ CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */\r
+\r
+ const pll_setup_t pll1Setup = {\r
+ .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U),\r
+ .pllndec = SYSCON_PLL1NDEC_NDIV(1U),\r
+ .pllpdec = SYSCON_PLL1PDEC_PDIV(4U),\r
+ .pllmdec = SYSCON_PLL1MDEC_MDIV(24U),\r
+ .pllRate = 48000000U,\r
+ .flags = PLL_SETUPFLAG_WAITLOCK,\r
+ };\r
+\r
+ CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */\r
+\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);\r
+ CLOCK_AttachClk(kPLL1_to_USB0_CLK);\r
+ uint32_t delay = 100000;\r
+ while (delay--)\r
+ {\r
+ __asm("nop");\r
+ }\r
+ }\r
+ CLOCK_EnableClock(kCLOCK_Usbd0);\r
+ CLOCK_EnableClock(kCLOCK_UsbRam1);\r
+\r
+ return ret;\r
+}\r
+\r
+/* Enable USB HOST FULL SPEED clock */\r
+/*! brief Enable USB HOST FS clock.\r
+* param src : clock source\r
+* param freq: clock frequency\r
+* Enable USB HOST Full Speed clock.\r
+*/\r
+bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)\r
+{\r
+ bool ret = true;\r
+\r
+ CLOCK_DisableClock(kCLOCK_Usbhmr0);\r
+ CLOCK_DisableClock(kCLOCK_Usbhsl0);\r
+\r
+ if (kCLOCK_UsbfsSrcFro == src)\r
+ {\r
+ switch (freq)\r
+ {\r
+ case 96000000U:\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */\r
+ break;\r
+\r
+ default:\r
+ ret = false;\r
+ break;\r
+ }\r
+ /* Turn ON FRO HF */\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO192M);\r
+ /* Enable FRO 96MHz output */\r
+ ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;\r
+ /* Select FRO 96 MHz */\r
+ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);\r
+ }\r
+ else\r
+ {\r
+ /*Set the USB PLL as the Usb0 CLK*/\r
+ POWER_DisablePD(kPDRUNCFG_PD_PLL1);\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;\r
+\r
+ CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */\r
+\r
+ const pll_setup_t pll1Setup = {\r
+ .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U),\r
+ .pllndec = SYSCON_PLL1NDEC_NDIV(1U),\r
+ .pllpdec = SYSCON_PLL1PDEC_PDIV(4U),\r
+ .pllmdec = SYSCON_PLL1MDEC_MDIV(24U),\r
+ .pllRate = 48000000U,\r
+ .flags = PLL_SETUPFLAG_WAITLOCK,\r
+ };\r
+\r
+ CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */\r
+\r
+ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);\r
+ CLOCK_AttachClk(kPLL1_to_USB0_CLK);\r
+ uint32_t delay = 100000;\r
+ while (delay--)\r
+ {\r
+ __asm("nop");\r
+ }\r
+ }\r
+ CLOCK_EnableClock(kCLOCK_Usbhmr0);\r
+ CLOCK_EnableClock(kCLOCK_Usbhsl0);\r
+ CLOCK_EnableClock(kCLOCK_UsbRam1);\r
+\r
+ return ret;\r
+}\r
+\r
+/* Enable USB PHY clock */\r
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)\r
+{\r
+ volatile uint32_t i;\r
+\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);\r
+ POWER_DisablePD(kPDRUNCFG_PD_FRO32K); /*!< Ensure FRO32k is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_XTAL32K); /*!< Ensure xtal32k is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /*!< Ensure xtal32k is on */\r
+ POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */\r
+\r
+ /* wait to make sure PHY power is fully up */\r
+ i = 100000;\r
+ while (i--)\r
+ {\r
+ __asm("nop");\r
+ }\r
+\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1);\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1);\r
+\r
+ USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;\r
+ USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06);\r
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK;\r
+ USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK;\r
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK;\r
+ USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK;\r
+ USBPHY->PLL_SIC_SET =\r
+ USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK; /* enables auto power down of PHY PLL during suspend */\r
+\r
+ USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;\r
+ USBPHY->PWD_SET = 0x0;\r
+\r
+ return true;\r
+}\r
+\r
+/* Enable USB DEVICE HIGH SPEED clock */\r
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq)\r
+{\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1);\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_DEV(1);\r
+\r
+ /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1);\r
+ return true;\r
+}\r
+\r
+/* Enable USB HOST HIGH SPEED clock */\r
+bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq)\r
+{\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_RAM(1);\r
+ SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_HOST(1);\r
+\r
+ /* 16 MHz will be driven by the tb on the xtal1 pin of XTAL32M */\r
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clock_in clock for clock module. */\r
+ ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(1);\r
+\r
+ return true;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2017 - 2018 , NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_CLOCK_H_\r
+#define _FSL_CLOCK_H_\r
+\r
+#include "fsl_device_registers.h"\r
+#include <stdint.h>\r
+#include <stdbool.h>\r
+#include <assert.h>\r
+\r
+/*! @addtogroup clock */\r
+/*! @{ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ *****************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief CLOCK driver version 2.0.3. */\r
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))\r
+/*@}*/\r
+\r
+/*! @brief Configure whether driver controls clock\r
+ *\r
+ * When set to 0, peripheral drivers will enable clock in initialize function\r
+ * and disable clock in de-initialize function. When set to 1, peripheral\r
+ * driver will not control the clock, application could control the clock out of\r
+ * the driver.\r
+ *\r
+ * @note All drivers share this feature switcher. If it is set to 1, application\r
+ * should handle clock enable and disable for all drivers.\r
+ */\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))\r
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0\r
+#endif\r
+\r
+/*!\r
+ * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.\r
+ *\r
+ * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function\r
+ * would cache the recent calulation and accelerate the execution to get the\r
+ * right settings.\r
+ */\r
+#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT\r
+#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U\r
+#endif\r
+\r
+/*! @brief Clock ip name array for ROM. */\r
+#define ROM_CLOCKS \\r
+ { \\r
+ kCLOCK_Rom \\r
+ }\r
+/*! @brief Clock ip name array for SRAM. */\r
+#define SRAM_CLOCKS \\r
+ { \\r
+ kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4 \\r
+ }\r
+/*! @brief Clock ip name array for FLASH. */\r
+#define FLASH_CLOCKS \\r
+ { \\r
+ kCLOCK_Flash \\r
+ }\r
+/*! @brief Clock ip name array for FMC. */\r
+#define FMC_CLOCKS \\r
+ { \\r
+ kCLOCK_Fmc \\r
+ }\r
+/*! @brief Clock ip name array for INPUTMUX. */\r
+#define INPUTMUX_CLOCKS \\r
+ { \\r
+ kCLOCK_InputMux0, kCLOCK_InputMux1 \\r
+ }\r
+/*! @brief Clock ip name array for IOCON. */\r
+#define IOCON_CLOCKS \\r
+ { \\r
+ kCLOCK_Iocon \\r
+ }\r
+/*! @brief Clock ip name array for GPIO. */\r
+#define GPIO_CLOCKS \\r
+ { \\r
+ kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \\r
+ }\r
+/*! @brief Clock ip name array for PINT. */\r
+#define PINT_CLOCKS \\r
+ { \\r
+ kCLOCK_Pint \\r
+ }\r
+/*! @brief Clock ip name array for GINT. */\r
+#define GINT_CLOCKS \\r
+ { \\r
+ kCLOCK_Gint, kCLOCK_Gint \\r
+ }\r
+/*! @brief Clock ip name array for DMA. */\r
+#define DMA_CLOCKS \\r
+ { \\r
+ kCLOCK_Dma0, kCLOCK_Dma1 \\r
+ }\r
+/*! @brief Clock ip name array for CRC. */\r
+#define CRC_CLOCKS \\r
+ { \\r
+ kCLOCK_Crc \\r
+ }\r
+/*! @brief Clock ip name array for WWDT. */\r
+#define WWDT_CLOCKS \\r
+ { \\r
+ kCLOCK_Wwdt \\r
+ }\r
+/*! @brief Clock ip name array for RTC. */\r
+#define RTC_CLOCKS \\r
+ { \\r
+ kCLOCK_Rtc \\r
+ }\r
+/*! @brief Clock ip name array for Mailbox. */\r
+#define MAILBOX_CLOCKS \\r
+ { \\r
+ kCLOCK_Mailbox \\r
+ }\r
+/*! @brief Clock ip name array for LPADC. */\r
+#define LPADC_CLOCKS \\r
+ { \\r
+ kCLOCK_Adc0 \\r
+ }\r
+/*! @brief Clock ip name array for MRT. */\r
+#define MRT_CLOCKS \\r
+ { \\r
+ kCLOCK_Mrt \\r
+ }\r
+/*! @brief Clock ip name array for OSTIMER. */\r
+#define OSTIMER_CLOCKS \\r
+ { \\r
+ kCLOCK_OsTimer0 \\r
+ }\r
+/*! @brief Clock ip name array for SCT0. */\r
+#define SCT_CLOCKS \\r
+ { \\r
+ kCLOCK_Sct0 \\r
+ }\r
+/*! @brief Clock ip name array for SCTIPU. */\r
+#define SCTIPU_CLOCKS \\r
+ { \\r
+ kCLOCK_Sctipu \\r
+ }\r
+/*! @brief Clock ip name array for UTICK. */\r
+#define UTICK_CLOCKS \\r
+ { \\r
+ kCLOCK_Utick0 \\r
+ }\r
+/*! @brief Clock ip name array for FLEXCOMM. */\r
+#define FLEXCOMM_CLOCKS \\r
+ { \\r
+ kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \\r
+ kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_Hs_Lspi \\r
+ }\r
+/*! @brief Clock ip name array for LPUART. */\r
+#define LPUART_CLOCKS \\r
+ { \\r
+ kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \\r
+ kCLOCK_MinUart6, kCLOCK_MinUart7 \\r
+ }\r
+\r
+/*! @brief Clock ip name array for BI2C. */\r
+#define BI2C_CLOCKS \\r
+ { \\r
+ kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \\r
+ }\r
+/*! @brief Clock ip name array for LSPI. */\r
+#define LPSPI_CLOCKS \\r
+ { \\r
+ kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \\r
+ }\r
+/*! @brief Clock ip name array for FLEXI2S. */\r
+#define FLEXI2S_CLOCKS \\r
+ { \\r
+ kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \\r
+ kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \\r
+ }\r
+/*! @brief Clock ip name array for USBTYPC. */\r
+#define USBTYPC_CLOCKS \\r
+ { \\r
+ kCLOCK_UsbTypc \\r
+ }\r
+/*! @brief Clock ip name array for CTIMER. */\r
+#define CTIMER_CLOCKS \\r
+ { \\r
+ kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \\r
+ }\r
+/*! @brief Clock ip name array for PVT */\r
+#define PVT_CLOCKS \\r
+ { \\r
+ kCLOCK_Pvt \\r
+ }\r
+/*! @brief Clock ip name array for EZHA */\r
+#define EZHA_CLOCKS \\r
+ { \\r
+ kCLOCK_Ezha \\r
+ }\r
+/*! @brief Clock ip name array for EZHB */\r
+#define EZHB_CLOCKS \\r
+ { \\r
+ kCLOCK_Ezhb \\r
+ }\r
+/*! @brief Clock ip name array for COMP */\r
+#define COMP_CLOCKS \\r
+ { \\r
+ kCLOCK_Comp \\r
+ }\r
+/*! @brief Clock ip name array for SDIO. */\r
+#define SDIO_CLOCKS \\r
+ { \\r
+ kCLOCK_Sdio \\r
+ }\r
+/*! @brief Clock ip name array for USB1CLK. */\r
+#define USB1CLK_CLOCKS \\r
+ { \\r
+ kCLOCK_Usb1Clk \\r
+ }\r
+/*! @brief Clock ip name array for FREQME. */\r
+#define FREQME_CLOCKS \\r
+ { \\r
+ kCLOCK_Freqme \\r
+ }\r
+/*! @brief Clock ip name array for USBRAM. */\r
+#define USBRAM_CLOCKS \\r
+ { \\r
+ kCLOCK_UsbRam1 \\r
+ }\r
+/*! @brief Clock ip name array for OTP. */\r
+#define OTP_CLOCKS \\r
+ { \\r
+ kCLOCK_Otp \\r
+ }\r
+/*! @brief Clock ip name array for RNG. */\r
+#define RNG_CLOCKS \\r
+ { \\r
+ kCLOCK_Rng \\r
+ }\r
+/*! @brief Clock ip name array for USBHMR0. */\r
+#define USBHMR0_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbhmr0 \\r
+ }\r
+/*! @brief Clock ip name array for USBHSL0. */\r
+#define USBHSL0_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbhsl0 \\r
+ }\r
+/*! @brief Clock ip name array for HashCrypt. */\r
+#define HASHCRYPT_CLOCKS \\r
+ { \\r
+ kCLOCK_HashCrypt \\r
+ }\r
+/*! @brief Clock ip name array for PowerQuad. */\r
+#define POWERQUAD_CLOCKS \\r
+ { \\r
+ kCLOCK_PowerQuad \\r
+ }\r
+/*! @brief Clock ip name array for PLULUT. */\r
+#define PLULUT_CLOCKS \\r
+ { \\r
+ kCLOCK_PluLut \\r
+ }\r
+/*! @brief Clock ip name array for PUF. */\r
+#define PUF_CLOCKS \\r
+ { \\r
+ kCLOCK_Puf \\r
+ }\r
+/*! @brief Clock ip name array for CASPER. */\r
+#define CASPER_CLOCKS \\r
+ { \\r
+ kCLOCK_Casper \\r
+ }\r
+/*! @brief Clock ip name array for ANALOGCTRL. */\r
+#define ANALOGCTRL_CLOCKS \\r
+ { \\r
+ kCLOCK_AnalogCtrl \\r
+ }\r
+/*! @brief Clock ip name array for HS_LSPI. */\r
+#define HS_LSPI_CLOCKS \\r
+ { \\r
+ kCLOCK_Hs_Lspi \\r
+ }\r
+/*! @brief Clock ip name array for GPIO_SEC. */\r
+#define GPIO_SEC_CLOCKS \\r
+ { \\r
+ kCLOCK_Gpio_Sec \\r
+ }\r
+/*! @brief Clock ip name array for GPIO_SEC_INT. */\r
+#define GPIO_SEC_INT_CLOCKS \\r
+ { \\r
+ kCLOCK_Gpio_Sec_Int \\r
+ }\r
+/*! @brief Clock ip name array for USBD. */\r
+#define USBD_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \\r
+ }\r
+/*! @brief Clock ip name array for USBH. */\r
+#define USBH_CLOCKS \\r
+ { \\r
+ kCLOCK_Usbh1 \\r
+ }\r
+#define PLU_CLOCKS \\r
+ { \\r
+ kCLOCK_PluLut \\r
+ }\r
+#define SYSCTL_CLOCKS \\r
+ { \\r
+ kCLOCK_Sysctl \\r
+ }\r
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
+/*------------------------------------------------------------------------------\r
+ clock_ip_name_t definition:\r
+------------------------------------------------------------------------------*/\r
+\r
+#define CLK_GATE_REG_OFFSET_SHIFT 8U\r
+#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U\r
+#define CLK_GATE_BIT_SHIFT_SHIFT 0U\r
+#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU\r
+\r
+#define CLK_GATE_DEFINE(reg_offset, bit_shift) \\r
+ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \\r
+ (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))\r
+\r
+#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)\r
+#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)\r
+\r
+#define AHB_CLK_CTRL0 0\r
+#define AHB_CLK_CTRL1 1\r
+#define AHB_CLK_CTRL2 2\r
+\r
+/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */\r
+typedef enum _clock_ip_name\r
+{\r
+ kCLOCK_IpInvalid = 0U,\r
+ kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),\r
+ kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),\r
+ kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),\r
+ kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),\r
+ kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),\r
+ kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),\r
+ kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),\r
+ kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),\r
+ kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),\r
+ kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),\r
+ kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),\r
+ kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),\r
+ kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),\r
+ kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),\r
+ kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),\r
+ kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),\r
+ kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),\r
+ kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),\r
+ kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),\r
+ kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),\r
+ kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),\r
+ kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),\r
+ kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),\r
+ kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),\r
+ kCLOCK_Sctipu = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6),\r
+ kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),\r
+ kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),\r
+ kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),\r
+ kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),\r
+ kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),\r
+ kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),\r
+ kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),\r
+ kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),\r
+ kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),\r
+ kCLOCK_UsbTypc = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20),\r
+ kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),\r
+ kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),\r
+ kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),\r
+ kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),\r
+ kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),\r
+ kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30),\r
+ kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),\r
+ kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1),\r
+ kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),\r
+ kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),\r
+ kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),\r
+ kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),\r
+ kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),\r
+ kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),\r
+ kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8),\r
+ kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),\r
+ kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),\r
+ kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),\r
+ kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),\r
+ kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),\r
+ kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), \r
+ kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),\r
+ kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),\r
+ kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),\r
+ kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),\r
+ kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),\r
+ kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21),\r
+ kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22),\r
+ kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23),\r
+ kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24),\r
+ kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27),\r
+ kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28),\r
+ kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29),\r
+ kCLOCK_Gpio_sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30)\r
+} clock_ip_name_t;\r
+\r
+/*! @brief Peripherals clock source definition. */\r
+#define BUS_CLK kCLOCK_BusClk\r
+\r
+#define I2C0_CLK_SRC BUS_CLK\r
+\r
+/*! @brief Clock name used to get clock frequency. */\r
+typedef enum _clock_name\r
+{\r
+ kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */\r
+ kCLOCK_BusClk, /*!< Bus clock (AHB clock) */\r
+ kCLOCK_ClockOut, /*!< CLOCKOUT */\r
+ kCLOCK_FroHf, /*!< FRO48/96 */\r
+ kCLOCK_Adc, /*!< ADC */\r
+ kCLOCK_Usb0, /*!< USB0 */\r
+ kCLOCK_Usb1, /*!< USB1 */\r
+ kCLOCK_Pll1Out, /*!< PLL1 Output */\r
+ kCLOCK_Mclk, /*!< MCLK */\r
+ kCLOCK_Sct, /*!< SCT */\r
+ kCLOCK_SDio, /*!< SDIO */\r
+ kCLOCK_Fro12M, /*!< FRO12M */\r
+ kCLOCK_ExtClk, /*!< External Clock */\r
+ kCLOCK_Pll0Out, /*!< PLL0 Output */\r
+ kCLOCK_WdtClk, /*!< Watchdog clock */\r
+ kCLOCK_FlexI2S, /*!< FlexI2S clock */\r
+ kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */\r
+ kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */\r
+ kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */\r
+ kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */\r
+ kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */\r
+ kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */\r
+ kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */\r
+ kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */\r
+ kCLOCK_HsLspi, /*!< HS LPSPI Clock */\r
+ kCLOCK_CTmier0, /*!< CTmier0Clock */\r
+ kCLOCK_CTmier1, /*!< CTmier1Clock */\r
+ kCLOCK_CTmier2, /*!< CTmier2Clock */\r
+ kCLOCK_CTmier3, /*!< CTmier3Clock */\r
+ kCLOCK_CTmier4, /*!< CTmier4Clock */\r
+ kCLOCK_Systick0, /*!< System Tick 0 Clock */\r
+ kCLOCK_Systick1, /*!< System Tick 1 Clock */\r
+\r
+} clock_name_t;\r
+\r
+/*! @brief Clock Mux Switches\r
+* The encoding is as follows each connection identified is 32bits wide while 24bits are valuable\r
+* starting from LSB upwards\r
+*\r
+* [4 bits for choice, 0 means invalid choice] [8 bits mux ID]*\r
+*\r
+*/\r
+\r
+#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U))\r
+#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U)\r
+#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U))\r
+\r
+#define GET_ID_ITEM(connection) ((connection)&0xFFFU)\r
+#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U)\r
+#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU)\r
+#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U)\r
+#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U)\r
+\r
+#define CM_SYSTICKCLKSEL0 0\r
+#define CM_SYSTICKCLKSEL1 1\r
+#define CM_TRACECLKSEL 2\r
+#define CM_CTIMERCLKSEL0 3\r
+#define CM_CTIMERCLKSEL1 4\r
+#define CM_CTIMERCLKSEL2 5\r
+#define CM_CTIMERCLKSEL3 6\r
+#define CM_CTIMERCLKSEL4 7\r
+#define CM_MAINCLKSELA 8\r
+#define CM_MAINCLKSELB 9\r
+#define CM_CLKOUTCLKSEL 10\r
+#define CM_PLL0CLKSEL 12\r
+#define CM_PLL1CLKSEL 13\r
+#define CM_ADCASYNCCLKSEL 17\r
+#define CM_USB0CLKSEL 18\r
+#define CM_FXCOMCLKSEL0 20\r
+#define CM_FXCOMCLKSEL1 21\r
+#define CM_FXCOMCLKSEL2 22\r
+#define CM_FXCOMCLKSEL3 23\r
+#define CM_FXCOMCLKSEL4 24\r
+#define CM_FXCOMCLKSEL5 25\r
+#define CM_FXCOMCLKSEL6 26\r
+#define CM_FXCOMCLKSEL7 27\r
+#define CM_HSLSPICLKSEL 28\r
+#define CM_MCLKCLKSEL 32\r
+#define CM_SCTCLKSEL 36\r
+#define CM_SDIOCLKSEL 38\r
+\r
+#define CM_RTCOSC32KCLKSEL 63\r
+\r
+typedef enum _clock_attach_id\r
+{\r
+\r
+ kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0),\r
+ kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0),\r
+ kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0),\r
+ kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0),\r
+\r
+ kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0),\r
+ kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1),\r
+ kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2),\r
+ kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3),\r
+ kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4),\r
+ kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5),\r
+ kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6),\r
+ kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7),\r
+\r
+ kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0),\r
+ kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1),\r
+ kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2),\r
+ kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3),\r
+ kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),\r
+ kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),\r
+ kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),\r
+ kFRO1M_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /* Need confirm */\r
+ kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),\r
+ kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),\r
+ kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3),\r
+ kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5),\r
+ kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),\r
+ kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),\r
+ kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),\r
+ kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),\r
+ kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5),\r
+ kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6),\r
+ kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),\r
+ kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),\r
+ kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),\r
+ kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),\r
+ kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5),\r
+ kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6),\r
+ kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),\r
+ kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),\r
+ kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),\r
+ kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),\r
+ kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5),\r
+ kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6),\r
+ kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),\r
+ kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),\r
+ kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),\r
+ kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),\r
+ kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5),\r
+ kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6),\r
+ kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),\r
+ kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),\r
+ kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),\r
+ kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),\r
+ kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5),\r
+ kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6),\r
+ kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),\r
+ kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),\r
+ kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),\r
+ kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),\r
+ kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5),\r
+ kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6),\r
+ kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),\r
+ kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),\r
+ kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),\r
+ kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),\r
+ kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5),\r
+ kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6),\r
+ kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),\r
+\r
+ kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),\r
+ kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),\r
+ kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),\r
+ kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),\r
+ kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),\r
+ kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5),\r
+ kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6),\r
+ kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),\r
+\r
+ kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0),\r
+ kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1),\r
+ kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2),\r
+ kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3),\r
+ kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4),\r
+ kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6),\r
+ kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7),\r
+\r
+ kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),\r
+ kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),\r
+ kFRO1M_to_MCLK = MUX_A(CM_MCLKCLKSEL, 2), /* Need confirm */\r
+ kMAIN_CLK_to_MCLK = MUX_A(CM_MCLKCLKSEL, 3), /* Need confirm */\r
+ kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),\r
+ kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),\r
+ kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),\r
+ kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),\r
+ kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5),\r
+ kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),\r
+ kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),\r
+ kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),\r
+ kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5),\r
+ kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),\r
+\r
+ kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0),\r
+ kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1),\r
+\r
+ kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0),\r
+ kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1),\r
+ kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2),\r
+ kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7),\r
+\r
+ kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0),\r
+ kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1),\r
+ kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2),\r
+ kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7),\r
+\r
+ kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0),\r
+ kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1),\r
+ kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2),\r
+ kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7),\r
+\r
+ kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0),\r
+ kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1),\r
+ kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2),\r
+ kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3),\r
+ kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7),\r
+\r
+ kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0),\r
+ kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1),\r
+ kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3),\r
+ kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4),\r
+ kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5),\r
+ kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6),\r
+ kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7),\r
+\r
+ kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0),\r
+ kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1),\r
+ kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3),\r
+ kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4),\r
+ kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5),\r
+ kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6),\r
+ kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7),\r
+\r
+ kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0),\r
+ kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1),\r
+ kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3),\r
+ kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4),\r
+ kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5),\r
+ kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6),\r
+ kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7),\r
+\r
+ kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0),\r
+ kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1),\r
+ kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3),\r
+ kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4),\r
+ kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5),\r
+ kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6),\r
+ kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7),\r
+\r
+ kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0),\r
+ kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1),\r
+ kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3),\r
+ kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4),\r
+ kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5),\r
+ kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6),\r
+ kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7),\r
+ kNONE_to_NONE = (int)0x80000000U,\r
+} clock_attach_id_t;\r
+\r
+/* Clock dividers */\r
+typedef enum _clock_div_name\r
+{\r
+ kCLOCK_DivSystickClk0 = 0,\r
+ kCLOCK_DivSystickClk1 = 1,\r
+ kCLOCK_DivArmTrClkDiv = 2,\r
+ kCLOCK_DivFlexFrg0 = 8,\r
+ kCLOCK_DivFlexFrg1 = 9,\r
+ kCLOCK_DivFlexFrg2 = 10,\r
+ kCLOCK_DivFlexFrg3 = 11,\r
+ kCLOCK_DivFlexFrg4 = 12,\r
+ kCLOCK_DivFlexFrg5 = 13,\r
+ kCLOCK_DivFlexFrg6 = 14,\r
+ kCLOCK_DivFlexFrg7 = 15,\r
+ kCLOCK_DivAhbClk = 32,\r
+ kCLOCK_DivClkOut = 33,\r
+ kCLOCK_DivFrohfClk = 34,\r
+ kCLOCK_DivWdtClk = 35,\r
+ kCLOCK_DivAdcAsyncClk = 37,\r
+ kCLOCK_DivUsb0Clk = 38,\r
+ kCLOCK_DivMClk = 43,\r
+ kCLOCK_DivSctClk = 45,\r
+ kCLOCK_DivSdioClk = 47,\r
+ kCLOCK_DivPll0Clk = 49\r
+} clock_div_name_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/**\r
+ * @brief Enable the clock for specific IP.\r
+ * @param name : Clock to be enabled.\r
+ * @return Nothing\r
+ */\r
+static inline void CLOCK_EnableClock(clock_ip_name_t clk)\r
+{\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+}\r
+/**\r
+ * @brief Disable the clock for specific IP.\r
+ * @param name : Clock to be Disabled.\r
+ * @return Nothing\r
+ */\r
+static inline void CLOCK_DisableClock(clock_ip_name_t clk)\r
+{\r
+ uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);\r
+ SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));\r
+}\r
+/**\r
+ * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).\r
+ * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is\r
+ * enabled.\r
+ * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)\r
+ * @return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupFROClocking(uint32_t iFreq);\r
+/**\r
+ * @brief Set the flash wait states for the input freuqency.\r
+ * @param iFreq : Input frequency\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);\r
+/**\r
+ * @brief Initialize the external osc clock to given frequency.\r
+ * @param iFreq : Desired frequency (must be equal to exact rate in Hz)\r
+ * @return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupExtClocking(uint32_t iFreq);\r
+/**\r
+ * @brief Initialize the I2S MCLK clock to given frequency.\r
+ * @param iFreq : Desired frequency (must be equal to exact rate in Hz)\r
+ * @return returns success or fail status.\r
+ */\r
+status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq);\r
+/**\r
+ * @brief Configure the clock selection muxes.\r
+ * @param connection : Clock to be configured.\r
+ * @return Nothing\r
+ */\r
+void CLOCK_AttachClk(clock_attach_id_t connection);\r
+/**\r
+ * @brief Get the actual clock attach id.\r
+ * This fuction uses the offset in input attach id, then it reads the actual source value in\r
+ * the register and combine the offset to obtain an actual attach id.\r
+ * @param attachId : Clock attach id to get.\r
+ * @return Clock source value.\r
+ */\r
+clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId);\r
+/**\r
+ * @brief Setup peripheral clock dividers.\r
+ * @param div_name : Clock divider name\r
+ * @param divided_by_value: Value to be divided\r
+ * @param reset : Whether to reset the divider counter.\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);\r
+/**\r
+ * @brief Setup rtc 1khz clock divider.\r
+ * @param divided_by_value: Value to be divided\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetRtc1khzClkDiv(uint32_t divided_by_value);\r
+/**\r
+ * @brief Setup rtc 1hz clock divider.\r
+ * @param divided_by_value: Value to be divided\r
+ * @return Nothing\r
+ */\r
+void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value);\r
+\r
+/**\r
+ * @brief Set the flexcomm output frequency.\r
+ * @param id : flexcomm instance id\r
+ * freq : output frequency\r
+ * @return 0 : the frequency range is out of range.\r
+ * 1 : switch successfully.\r
+ */\r
+uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq);\r
+\r
+/*! @brief Return Frequency of flexcomm input clock\r
+ * @param id : flexcomm instance id\r
+ * @return Frequency value\r
+ */\r
+uint32_t CLOCK_GetFlexCommInputClock(uint32_t id);\r
+\r
+/*! @brief Return Frequency of selected clock\r
+ * @return Frequency of selected clock\r
+ */\r
+uint32_t CLOCK_GetFreq(clock_name_t clockName);\r
+/*! @brief Return Frequency of FRO 12MHz\r
+ * @return Frequency of FRO 12MHz\r
+ */\r
+uint32_t CLOCK_GetFro12MFreq(void);\r
+/*! @brief Return Frequency of FRO 1MHz\r
+ * @return Frequency of FRO 1MHz\r
+ */\r
+uint32_t CLOCK_GetFro1MFreq(void);\r
+/*! @brief Return Frequency of ClockOut\r
+ * @return Frequency of ClockOut\r
+ */\r
+uint32_t CLOCK_GetClockOutClkFreq(void);\r
+/*! @brief Return Frequency of Adc Clock\r
+ * @return Frequency of Adc.\r
+ */\r
+uint32_t CLOCK_GetAdcClkFreq(void);\r
+/*! @brief Return Frequency of Usb0 Clock\r
+ * @return Frequency of Usb0 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb0ClkFreq(void);\r
+/*! @brief Return Frequency of Usb1 Clock\r
+ * @return Frequency of Usb1 Clock.\r
+ */\r
+uint32_t CLOCK_GetUsb1ClkFreq(void);\r
+/*! @brief Return Frequency of MClk Clock\r
+ * @return Frequency of MClk Clock.\r
+ */\r
+uint32_t CLOCK_GetMclkClkFreq(void);\r
+/*! @brief Return Frequency of SCTimer Clock\r
+ * @return Frequency of SCTimer Clock.\r
+ */\r
+uint32_t CLOCK_GetSctClkFreq(void);\r
+/*! @brief Return Frequency of SDIO Clock\r
+ * @return Frequency of SDIO Clock.\r
+ */\r
+uint32_t CLOCK_GetSdioClkFreq(void);\r
+/*! @brief Return Frequency of External Clock\r
+ * @return Frequency of External Clock. If no external clock is used returns 0.\r
+ */\r
+uint32_t CLOCK_GetExtClkFreq(void);\r
+/*! @brief Return Frequency of Watchdog\r
+ * @return Frequency of Watchdog\r
+ */\r
+uint32_t CLOCK_GetWdtClkFreq(void);\r
+/*! @brief Return Frequency of High-Freq output of FRO\r
+ * @return Frequency of High-Freq output of FRO\r
+ */\r
+uint32_t CLOCK_GetFroHfFreq(void);\r
+/*! @brief Return Frequency of PLL\r
+ * @return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPll0OutFreq(void);\r
+/*! @brief Return Frequency of USB PLL\r
+ * @return Frequency of PLL\r
+ */\r
+uint32_t CLOCK_GetPll1OutFreq(void);\r
+/*! @brief Return Frequency of 32kHz osc\r
+ * @return Frequency of 32kHz osc\r
+ */\r
+uint32_t CLOCK_GetOsc32KFreq(void);\r
+/*! @brief Return Frequency of Core System\r
+ * @return Frequency of Core System\r
+ */\r
+uint32_t CLOCK_GetCoreSysClkFreq(void);\r
+/*! @brief Return Frequency of I2S MCLK Clock\r
+ * @return Frequency of I2S MCLK Clock\r
+ */\r
+uint32_t CLOCK_GetI2SMClkFreq(void);\r
+/*! @brief Return Frequency of CTimer functional Clock\r
+ * @return Frequency of CTimer functional Clock\r
+ */\r
+uint32_t CLOCK_GetCTimerClkFreq(uint32_t id);\r
+/*! @brief Return Frequency of SystickClock\r
+ * @return Frequency of Systick Clock\r
+ */\r
+uint32_t CLOCK_GetSystickClkFreq(uint32_t id);\r
+\r
+/*! @brief Return PLL0 input clock rate\r
+* @return PLL0 input clock rate\r
+*/\r
+uint32_t CLOCK_GetPLL0InClockRate(void);\r
+\r
+/*! @brief Return PLL1 input clock rate\r
+* @return PLL1 input clock rate\r
+*/\r
+uint32_t CLOCK_GetPLL1InClockRate(void);\r
+\r
+/*! @brief Return PLL0 output clock rate\r
+* @param recompute : Forces a PLL rate recomputation if true\r
+* @return PLL0 output clock rate\r
+* @note The PLL rate is cached in the driver in a variable as\r
+* the rate computation function can take some time to perform. It\r
+* is recommended to use 'false' with the 'recompute' parameter.\r
+*/\r
+uint32_t CLOCK_GetPLL0OutClockRate(bool recompute);\r
+\r
+/*! @brief Return PLL1 output clock rate\r
+* @param recompute : Forces a PLL rate recomputation if true\r
+* @return PLL1 output clock rate\r
+* @note The PLL rate is cached in the driver in a variable as\r
+* the rate computation function can take some time to perform. It\r
+* is recommended to use 'false' with the 'recompute' parameter.\r
+*/\r
+uint32_t CLOCK_GetPLL1OutClockRate(bool recompute);\r
+\r
+/*! @brief Enables and disables PLL0 bypass mode\r
+* @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass\r
+* @return PLL0 output clock rate\r
+*/\r
+__STATIC_INLINE void CLOCK_SetBypassPLL0(bool bypass)\r
+{\r
+ if (bypass)\r
+ {\r
+ SYSCON->PLL0CTRL |= (1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ SYSCON->PLL0CTRL &= ~(1UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT);\r
+ }\r
+}\r
+\r
+/*! @brief Enables and disables PLL1 bypass mode\r
+* @brief bypass : true to bypass PLL1 (PLL1 output = PLL1 input, false to disable bypass\r
+* @return PLL1 output clock rate\r
+*/\r
+__STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass)\r
+{\r
+ if (bypass)\r
+ {\r
+ SYSCON->PLL1CTRL |= (1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ SYSCON->PLL1CTRL &= ~(1UL << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT);\r
+ }\r
+}\r
+\r
+/*! @brief Check if PLL is locked or not\r
+* @return true if the PLL is locked, false if not locked\r
+*/\r
+__STATIC_INLINE bool CLOCK_IsPLL0Locked(void)\r
+{\r
+ return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0);\r
+}\r
+\r
+/*! @brief Check if PLL1 is locked or not\r
+ * @return true if the PLL1 is locked, false if not locked\r
+ */\r
+__STATIC_INLINE bool CLOCK_IsPLL1Locked(void)\r
+{\r
+ return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0);\r
+}\r
+\r
+/*! @brief Store the current PLL0 rate\r
+* @param rate: Current rate of the PLL0\r
+* @return Nothing\r
+**/\r
+void CLOCK_SetStoredPLL0ClockRate(uint32_t rate);\r
+\r
+/*! @brief PLL configuration structure flags for 'flags' field\r
+* These flags control how the PLL configuration function sets up the PLL setup structure.<br>\r
+*\r
+* When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the\r
+* configuration structure must be assigned with the expected PLL frequency. If the\r
+* PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration\r
+* function and the driver will determine the PLL rate from the currently selected\r
+* PLL source. This flag might be used to configure the PLL input clock more accurately\r
+* when using the WDT oscillator or a more dyanmic CLKIN source.<br>\r
+*\r
+* When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the\r
+* automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider\r
+* are not used.<br>\r
+*/\r
+#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */\r
+#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2)\r
+/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */\r
+\r
+/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency\r
+ * See (MF) field in the PLL0SSCG1 register in the UM.\r
+ */\r
+typedef enum _ss_progmodfm\r
+{\r
+ kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */\r
+ kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */\r
+ kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */\r
+ kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */\r
+ kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */\r
+ kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */\r
+ kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */\r
+ kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */\r
+} ss_progmodfm_t;\r
+\r
+/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth\r
+ * See (MR) field in the PLL0SSCG1 register in the UM.\r
+ */\r
+typedef enum _ss_progmoddp\r
+{\r
+ kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */\r
+ kSS_MR_K1 = (1 << 23), /*!< k = 1 */\r
+ kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */\r
+ kSS_MR_K2 = (3 << 23), /*!< k = 2 */\r
+ kSS_MR_K3 = (4 << 23), /*!< k = 3 */\r
+ kSS_MR_K4 = (5 << 23), /*!< k = 4 */\r
+ kSS_MR_K6 = (6 << 23), /*!< k = 6 */\r
+ kSS_MR_K8 = (7 << 23) /*!< k = 8 */\r
+} ss_progmoddp_t;\r
+\r
+/*! @brief PLL Spread Spectrum (SS) Modulation waveform control\r
+ * See (MC) field in the PLL0SSCG1 register in the UM.<br>\r
+ * Compensation for low pass filtering of the PLL to get a triangular\r
+ * modulation at the output of the PLL, giving a flat frequency spectrum.\r
+ */\r
+typedef enum _ss_modwvctrl\r
+{\r
+ kSS_MC_NOC = (0 << 26), /*!< no compensation */\r
+ kSS_MC_RECC = (2 << 26), /*!< recommended setting */\r
+ kSS_MC_MAXC = (3 << 26), /*!< max. compensation */\r
+} ss_modwvctrl_t;\r
+\r
+/*! @brief PLL configuration structure\r
+*\r
+* This structure can be used to configure the settings for a PLL\r
+* setup structure. Fill in the desired configuration for the PLL\r
+* and call the PLL setup function to fill in a PLL setup structure.\r
+*/\r
+typedef struct _pll_config\r
+{\r
+ uint32_t desiredRate; /*!< Desired PLL rate in Hz */\r
+ uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */\r
+ uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */\r
+ ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using\r
+ PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+ ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using\r
+ PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+ ss_modwvctrl_t\r
+ ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+ bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using\r
+ PLL_CONFIGFLAG_FORCENOFRACT flag */\r
+\r
+} pll_config_t;\r
+\r
+/*! @brief PLL setup structure flags for 'flags' field\r
+* These flags control how the PLL setup function sets up the PLL\r
+*/\r
+#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */\r
+#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */\r
+#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */\r
+#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */\r
+\r
+/*! @brief PLL0 setup structure\r
+* This structure can be used to pre-build a PLL setup configuration\r
+* at run-time and quickly set the PLL to the configuration. It can be\r
+* populated with the PLL setup function. If powering up or waiting\r
+* for PLL lock, the PLL input clock source should be configured prior\r
+* to PLL setup.\r
+*/\r
+typedef struct _pll_setup\r
+{\r
+ uint32_t pllctrl; /*!< PLL control register PLL0CTRL */\r
+ uint32_t pllndec; /*!< PLL NDEC register PLL0NDEC */\r
+ uint32_t pllpdec; /*!< PLL PDEC register PLL0PDEC */\r
+ uint32_t pllmdec; /*!< PLL MDEC registers PLL0PDEC */\r
+ uint32_t pllsscg[2]; /*!< PLL SSCTL registers PLL0SSCG*/\r
+ uint32_t pllRate; /*!< Acutal PLL rate */\r
+ uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */\r
+} pll_setup_t;\r
+\r
+/*! @brief PLL status definitions\r
+*/\r
+typedef enum _pll_error\r
+{\r
+ kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */\r
+ kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */\r
+ kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */\r
+ kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */\r
+ kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */\r
+ kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */\r
+ kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */\r
+ kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */\r
+} pll_error_t;\r
+\r
+/*! @brief USB FS clock source definition. */\r
+typedef enum _clock_usbfs_src\r
+{\r
+ kCLOCK_UsbfsSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 MHz. */\r
+ kCLOCK_UsbfsSrcPll0 = (uint32_t)kCLOCK_Pll0Out, /*!< Use PLL0 output. */\r
+ kCLOCK_UsbfsSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */\r
+ kCLOCK_UsbfsSrcPll1 = (uint32_t)kCLOCK_Pll1Out, /*!< Use PLL1 clock. */\r
+\r
+ kCLOCK_UsbfsSrcNone =\r
+ SYSCON_USB0CLKSEL_SEL(7) /*!<this may be selected in order to reduce power when no output is needed. */\r
+} clock_usbfs_src_t;\r
+\r
+/*! @brief USBhs clock source definition. */\r
+typedef enum _clock_usbhs_src\r
+{\r
+ kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not\r
+ care the clock source. */\r
+} clock_usbhs_src_t;\r
+\r
+/*! @brief Source of the USB HS PHY. */\r
+typedef enum _clock_usb_phy_src\r
+{\r
+ kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */\r
+} clock_usb_phy_src_t;\r
+\r
+/*! @brief Return PLL0 output clock rate from setup structure\r
+* @param pSetup : Pointer to a PLL setup structure\r
+* @return System PLL output clock rate the setup structure will generate\r
+*/\r
+uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL0 output based on the passed PLL setup data\r
+* @param pControl : Pointer to populated PLL control structure to generate setup with\r
+* @param pSetup : Pointer to PLL setup structure to be filled\r
+* @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+* @note Actual frequency for setup may vary from the desired frequency based on the\r
+* accuracy of input clocks, rounding, non-fractional PLL mode, etc.\r
+*/\r
+pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL output from PLL setup structure (precise frequency)\r
+* @param pSetup : Pointer to populated PLL setup structure\r
+* @param flagcfg : Flag configuration for PLL config structure\r
+* @return PLL_ERROR_SUCCESS on success, or PLL setup error code\r
+* @note This function will power off the PLL, setup the PLL with the\r
+* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+* and adjust system voltages to the new PLL rate. The function will not\r
+* alter any source clocks (ie, main systen clock) that may use the PLL,\r
+* so these should be setup prior to and after exiting the function.\r
+*/\r
+pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg);\r
+\r
+/**\r
+* @brief Set PLL output from PLL setup structure (precise frequency)\r
+* @param pSetup : Pointer to populated PLL setup structure\r
+* @return kStatus_PLL_Success on success, or PLL setup error code\r
+* @note This function will power off the PLL, setup the PLL with the\r
+* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+* and adjust system voltages to the new PLL rate. The function will not\r
+* alter any source clocks (ie, main systen clock) that may use the PLL,\r
+* so these should be setup prior to and after exiting the function.\r
+*/\r
+pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup);\r
+\r
+/**\r
+* @brief Set PLL output from PLL setup structure (precise frequency)\r
+* @param pSetup : Pointer to populated PLL setup structure\r
+* @return kStatus_PLL_Success on success, or PLL setup error code\r
+* @note This function will power off the PLL, setup the PLL with the\r
+* new setup data, and then optionally powerup the PLL, wait for PLL lock,\r
+* and adjust system voltages to the new PLL rate. The function will not\r
+* alter any source clocks (ie, main systen clock) that may use the PLL,\r
+* so these should be setup prior to and after exiting the function.\r
+*/\r
+pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup);\r
+\r
+/*! @brief Set PLL0 output based on the multiplier and input frequency\r
+* @param multiply_by : multiplier\r
+* @param input_freq : Clock input frequency of the PLL\r
+* @return Nothing\r
+* @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this\r
+* function does not disable or enable PLL power, wait for PLL lock,\r
+* or adjust system voltages. These must be done in the application.\r
+* The function will not alter any source clocks (ie, main systen clock)\r
+* that may use the PLL, so these should be setup prior to and after\r
+* exiting the function.\r
+*/\r
+void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq);\r
+\r
+/*! @brief Disable USB clock.\r
+*\r
+* Disable USB clock.\r
+*/\r
+static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)\r
+{\r
+ CLOCK_DisableClock(clk);\r
+}\r
+\r
+/*! @brief Enable USB Device FS clock.\r
+* @param src : clock source\r
+* @param freq: clock frequency\r
+* Enable USB Device Full Speed clock.\r
+*/\r
+bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq);\r
+\r
+/*! @brief Enable USB HOST FS clock.\r
+* @param src : clock source\r
+* @param freq: clock frequency\r
+* Enable USB HOST Full Speed clock.\r
+*/\r
+bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq);\r
+\r
+/*! @brief Enable USB phy clock.\r
+* Enable USB phy clock.\r
+*/\r
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);\r
+\r
+/*! @brief Enable USB Device HS clock.\r
+* Enable USB Device High Speed clock.\r
+*/\r
+bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq);\r
+\r
+/*! @brief Enable USB HOST HS clock.\r
+* Enable USB HOST High Speed clock.\r
+*/\r
+bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_CLOCK_H_ */\r
--- /dev/null
+/*\r
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+* All rights reserved.\r
+*\r
+*\r
+* SPDX-License-Identifier: BSD-3-Clause\r
+*/\r
+\r
+#include "fsl_common.h"\r
+#define SDK_MEM_MAGIC_NUMBER 12345U\r
+\r
+typedef struct _mem_align_control_block\r
+{\r
+ uint16_t identifier; /*!< Identifier for the memory control block. */\r
+ uint16_t offset; /*!< offset from aligned address to real address */\r
+} mem_align_cb_t;\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.common"\r
+#endif\r
+\r
+#ifndef __GIC_PRIO_BITS\r
+#if defined(ENABLE_RAM_VECTOR_TABLE)\r
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)\r
+{\r
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */\r
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+ extern uint32_t Image$$VECTOR_ROM$$Base[];\r
+ extern uint32_t Image$$VECTOR_RAM$$Base[];\r
+ extern uint32_t Image$$RW_m_data$$Base[];\r
+\r
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base\r
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base\r
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))\r
+#elif defined(__ICCARM__)\r
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE[];\r
+ extern uint32_t __VECTOR_TABLE[];\r
+ extern uint32_t __VECTOR_RAM[];\r
+#elif defined(__GNUC__)\r
+ extern uint32_t __VECTOR_TABLE[];\r
+ extern uint32_t __VECTOR_RAM[];\r
+ extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];\r
+ uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);\r
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */\r
+ uint32_t n;\r
+ uint32_t ret;\r
+ uint32_t irqMaskValue;\r
+\r
+ irqMaskValue = DisableGlobalIRQ();\r
+ if (SCB->VTOR != (uint32_t)__VECTOR_RAM)\r
+ {\r
+ /* Copy the vector table from ROM to RAM */\r
+ for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)\r
+ {\r
+ __VECTOR_RAM[n] = __VECTOR_TABLE[n];\r
+ }\r
+ /* Point the VTOR to the position of vector table */\r
+ SCB->VTOR = (uint32_t)__VECTOR_RAM;\r
+ }\r
+\r
+ ret = __VECTOR_RAM[irq + 16];\r
+ /* make sure the __VECTOR_RAM is noncachable */\r
+ __VECTOR_RAM[irq + 16] = irqHandler;\r
+\r
+ EnableGlobalIRQ(irqMaskValue);\r
+\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+\r
+ return ret;\r
+}\r
+#endif /* ENABLE_RAM_VECTOR_TABLE. */\r
+#endif /* __GIC_PRIO_BITS. */\r
+\r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)\r
+\r
+void EnableDeepSleepIRQ(IRQn_Type interrupt)\r
+{\r
+ uint32_t intNumber = (uint32_t)interrupt;\r
+\r
+ uint32_t index = 0;\r
+\r
+ while (intNumber >= 32u)\r
+ {\r
+ index++;\r
+ intNumber -= 32u;\r
+ }\r
+\r
+ SYSCON->STARTERSET[index] = 1u << intNumber;\r
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */\r
+}\r
+\r
+void DisableDeepSleepIRQ(IRQn_Type interrupt)\r
+{\r
+ uint32_t intNumber = (uint32_t)interrupt;\r
+\r
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */\r
+ uint32_t index = 0;\r
+\r
+ while (intNumber >= 32u)\r
+ {\r
+ index++;\r
+ intNumber -= 32u;\r
+ }\r
+\r
+ SYSCON->STARTERCLR[index] = 1u << intNumber;\r
+}\r
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */\r
+\r
+void *SDK_Malloc(size_t size, size_t alignbytes)\r
+{\r
+ mem_align_cb_t *p_cb = NULL;\r
+ uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);\r
+ void *p_align_addr, *p_addr = malloc(alignedsize);\r
+\r
+ if (!p_addr)\r
+ {\r
+ return NULL;\r
+ }\r
+\r
+ p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);\r
+\r
+ p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4);\r
+ p_cb->identifier = SDK_MEM_MAGIC_NUMBER;\r
+ p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr;\r
+\r
+ return (void *)p_align_addr;\r
+}\r
+\r
+void SDK_Free(void *ptr)\r
+{\r
+ mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4);\r
+\r
+ if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)\r
+ {\r
+ return;\r
+ }\r
+\r
+ free((void *)((uint32_t)ptr - p_cb->offset));\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ * \r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_COMMON_H_\r
+#define _FSL_COMMON_H_\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include <stdlib.h>\r
+\r
+#if defined(__ICCARM__)\r
+#include <stddef.h>\r
+#endif\r
+\r
+#include "fsl_device_registers.h"\r
+\r
+/*!\r
+ * @addtogroup ksdk_common\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief Construct a status code value from a group and code number. */\r
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))\r
+\r
+/*! @brief Construct the version number for drivers. */\r
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief common driver version 2.0.1. */\r
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))\r
+/*@}*/\r
+\r
+/* Debug console type definition. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */\r
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */\r
+\r
+/*! @brief Status group numbers. */\r
+enum _status_groups\r
+{\r
+ kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */\r
+ kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */\r
+ kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */\r
+ kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */\r
+ kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */\r
+ kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */\r
+ kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */\r
+ kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */\r
+ kStatusGroup_UART = 10, /*!< Group number for UART status codes. */\r
+ kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */\r
+ kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */\r
+ kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */\r
+ kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/\r
+ kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/\r
+ kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/\r
+ kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */\r
+ kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */\r
+ kStatusGroup_SAI = 19, /*!< Group number for SAI status code */\r
+ kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */\r
+ kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */\r
+ kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */\r
+ kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */\r
+ kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */\r
+ kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */\r
+ kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */\r
+ kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */\r
+ kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */\r
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */\r
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */\r
+ kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */\r
+ kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */\r
+ kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */\r
+ kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */\r
+ kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */\r
+ kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */\r
+ kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */\r
+ kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */\r
+ kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */\r
+ kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */\r
+ kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */\r
+ kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */\r
+ kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */\r
+ kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */\r
+ kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */\r
+ kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */\r
+ kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */\r
+ kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/\r
+ kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */\r
+ kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */\r
+ kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */\r
+ kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */\r
+ kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */\r
+ kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/\r
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/\r
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/\r
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/\r
+ kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */\r
+ kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */\r
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */\r
+ kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */\r
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */\r
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */\r
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */\r
+ kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */\r
+ kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */\r
+ kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */\r
+ kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */\r
+ kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */\r
+ kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */\r
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ \r
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */\r
+ kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */\r
+\r
+ kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */\r
+ kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */\r
+ kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */\r
+ kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */\r
+ kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */\r
+ kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */\r
+ kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */\r
+ kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */\r
+ kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */\r
+ kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */\r
+ kStatusGroup_LED = 137, /*!< Group number for LED status codes. */\r
+ kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */\r
+ kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */\r
+ kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */\r
+ kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */\r
+ kStatusGroup_LIST = 142, /*!< Group number for List status codes. */\r
+ kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */\r
+ kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */\r
+ kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */\r
+};\r
+\r
+/*! @brief Generic status return codes. */\r
+enum _generic_status\r
+{\r
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),\r
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),\r
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),\r
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),\r
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),\r
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),\r
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),\r
+};\r
+\r
+/*! @brief Type used for all status and error return values. */\r
+typedef int32_t status_t;\r
+\r
+/*\r
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t\r
+ * defined in previous of this file.\r
+ */\r
+#include "fsl_clock.h"\r
+\r
+/*\r
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral\r
+ */\r
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \\r
+ (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))\r
+#include "fsl_reset.h"\r
+#endif\r
+\r
+/*\r
+ * Macro guard for whether to use default weak IRQ implementation in drivers\r
+ */\r
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ\r
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1\r
+#endif\r
+\r
+/*! @name Min/max macros */\r
+/* @{ */\r
+#if !defined(MIN)\r
+#define MIN(a, b) ((a) < (b) ? (a) : (b))\r
+#endif\r
+\r
+#if !defined(MAX)\r
+#define MAX(a, b) ((a) > (b) ? (a) : (b))\r
+#endif\r
+/* @} */\r
+\r
+/*! @brief Computes the number of elements in an array. */\r
+#if !defined(ARRAY_SIZE)\r
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\r
+#endif\r
+\r
+/*! @name UINT16_MAX/UINT32_MAX value */\r
+/* @{ */\r
+#if !defined(UINT16_MAX)\r
+#define UINT16_MAX ((uint16_t)-1)\r
+#endif\r
+\r
+#if !defined(UINT32_MAX)\r
+#define UINT32_MAX ((uint32_t)-1)\r
+#endif\r
+/* @} */\r
+\r
+/*! @name Timer utilities */\r
+/* @{ */\r
+/*! Macro to convert a microsecond period to raw count value */\r
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)\r
+/*! Macro to convert a raw count value to microsecond */\r
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)\r
+\r
+/*! Macro to convert a millisecond period to raw count value */\r
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)\r
+/*! Macro to convert a raw count value to millisecond */\r
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)\r
+/* @} */\r
+\r
+/*! @name Alignment variable definition macros */\r
+/* @{ */\r
+#if (defined(__ICCARM__))\r
+/**\r
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.\r
+ * http://supp.iar.com/Support/?note=24725\r
+ */\r
+_Pragma("diag_suppress=Pm120")\r
+#define SDK_PRAGMA(x) _Pragma(#x)\r
+ _Pragma("diag_error=Pm120")\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var\r
+#endif\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var\r
+#endif\r
+#elif defined(__GNUC__)\r
+/*! Macro to define a variable with alignbytes alignment */\r
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+/*! Macro to define a variable with L1 d-cache line size alignment */\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))\r
+#endif\r
+/*! Macro to define a variable with L2 cache line size alignment */\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))\r
+#endif\r
+#else\r
+#error Toolchain not supported\r
+#define SDK_ALIGN(var, alignbytes) var\r
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)\r
+#define SDK_L1DCACHE_ALIGN(var) var\r
+#endif\r
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)\r
+#define SDK_L2CACHE_ALIGN(var) var\r
+#endif\r
+#endif\r
+\r
+/*! Macro to change a value to a given size aligned value */\r
+#define SDK_SIZEALIGN(var, alignbytes) \\r
+ ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))\r
+/* @} */\r
+\r
+/*! @name Non-cacheable region definition macros */\r
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or\r
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,\r
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables\r
+ * will be initialized to zero in system startup.\r
+ */\r
+/* @{ */\r
+#if (defined(__ICCARM__))\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var\r
+#endif\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var\r
+#endif\r
+#elif(defined(__GNUC__))\r
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"\r
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.\r
+ */\r
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \\r
+ __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \\r
+ __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))\r
+#else\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))\r
+#endif\r
+#else\r
+#error Toolchain not supported.\r
+#define AT_NONCACHEABLE_SECTION(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var\r
+#define AT_NONCACHEABLE_SECTION_INIT(var) var\r
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var\r
+#endif\r
+/* @} */\r
+\r
+/*! @name Time sensitive region */\r
+/* @{ */\r
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE\r
+#if (defined(__ICCARM__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func\r
+#elif(defined(__GNUC__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif /* defined(__ICCARM__) */\r
+#else\r
+#if (defined(__ICCARM__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#elif(defined(__GNUC__))\r
+#define AT_QUICKACCESS_SECTION_CODE(func) func\r
+#define AT_QUICKACCESS_SECTION_DATA(func) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif \r
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */\r
+/* @} */\r
+\r
+/*! @name Ram Function */\r
+#if (defined(__ICCARM__))\r
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"\r
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))\r
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func\r
+#elif(defined(__GNUC__))\r
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func\r
+#else\r
+#error Toolchain not supported.\r
+#endif /* defined(__ICCARM__) */\r
+/* @} */\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+ extern "C"\r
+{\r
+#endif\r
+\r
+ /*!\r
+ * @brief Enable specific interrupt.\r
+ *\r
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt\r
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected\r
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.\r
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed\r
+ * to NVIC first then routed to core.\r
+ *\r
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts\r
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ * @retval kStatus_Success Interrupt enabled successfully\r
+ * @retval kStatus_Fail Failed to enable the interrupt\r
+ */\r
+ static inline status_t EnableIRQ(IRQn_Type interrupt)\r
+ {\r
+ if (NotAvail_IRQn == interrupt)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)\r
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+ GIC_EnableIRQ(interrupt);\r
+#else\r
+ NVIC_EnableIRQ(interrupt);\r
+#endif\r
+ return kStatus_Success;\r
+ }\r
+\r
+ /*!\r
+ * @brief Disable specific interrupt.\r
+ *\r
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt\r
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected\r
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.\r
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed\r
+ * to NVIC first then routed to core.\r
+ *\r
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts\r
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ * @retval kStatus_Success Interrupt disabled successfully\r
+ * @retval kStatus_Fail Failed to disable the interrupt\r
+ */\r
+ static inline status_t DisableIRQ(IRQn_Type interrupt)\r
+ {\r
+ if (NotAvail_IRQn == interrupt)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)\r
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+\r
+#if defined(__GIC_PRIO_BITS)\r
+ GIC_DisableIRQ(interrupt);\r
+#else\r
+ NVIC_DisableIRQ(interrupt);\r
+#endif\r
+ return kStatus_Success;\r
+ }\r
+\r
+ /*!\r
+ * @brief Disable the global IRQ\r
+ *\r
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask\r
+ * register for the EnableGlobalIRQ().\r
+ *\r
+ * @return Current primask value.\r
+ */\r
+ static inline uint32_t DisableGlobalIRQ(void)\r
+ {\r
+#if defined(CPSR_I_Msk)\r
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;\r
+\r
+ __disable_irq();\r
+\r
+ return cpsr;\r
+#else\r
+ uint32_t regPrimask = __get_PRIMASK();\r
+\r
+ __disable_irq();\r
+\r
+ return regPrimask;\r
+#endif\r
+ }\r
+\r
+ /*!\r
+ * @brief Enable the global IRQ\r
+ *\r
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the\r
+ * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to\r
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.\r
+ *\r
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the\r
+ * DisableGlobalIRQ().\r
+ */\r
+ static inline void EnableGlobalIRQ(uint32_t primask)\r
+ {\r
+#if defined(CPSR_I_Msk)\r
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);\r
+#else\r
+ __set_PRIMASK(primask);\r
+#endif\r
+ }\r
+\r
+#if defined(ENABLE_RAM_VECTOR_TABLE)\r
+ /*!\r
+ * @brief install IRQ handler\r
+ *\r
+ * @param irq IRQ number\r
+ * @param irqHandler IRQ handler address\r
+ * @return The old IRQ handler address\r
+ */\r
+ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);\r
+#endif /* ENABLE_RAM_VECTOR_TABLE. */\r
+ \r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+ /*!\r
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.\r
+ *\r
+ * Enable the interrupt for wake-up from deep sleep mode.\r
+ * Some interrupts are typically used in sleep mode only and will not occur during\r
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable\r
+ * those clocks (significantly increasing power consumption in the reduced power mode),\r
+ * making these wake-ups possible.\r
+ *\r
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ */\r
+ void EnableDeepSleepIRQ(IRQn_Type interrupt);\r
+\r
+ /*!\r
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.\r
+ *\r
+ * Disable the interrupt for wake-up from deep sleep mode.\r
+ * Some interrupts are typically used in sleep mode only and will not occur during\r
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable\r
+ * those clocks (significantly increasing power consumption in the reduced power mode),\r
+ * making these wake-ups possible.\r
+ *\r
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).\r
+ *\r
+ * @param interrupt The IRQ number.\r
+ */\r
+ void DisableDeepSleepIRQ(IRQn_Type interrupt);\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */\r
+\r
+ /*!\r
+ * @brief Allocate memory with given alignment and aligned size.\r
+ *\r
+ * This is provided to support the dynamically allocated memory\r
+ * used in cache-able region.\r
+ * @param size The length required to malloc.\r
+ * @param alignbytes The alignment size.\r
+ * @retval The allocated memory.\r
+ */ \r
+ void *SDK_Malloc(size_t size, size_t alignbytes);\r
+ \r
+ /*!\r
+ * @brief Free memory.\r
+ *\r
+ * @param ptr The memory to be release.\r
+ */ \r
+ void SDK_Free(void *ptr); \r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_COMMON_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_flexcomm.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*! @brief Set the FLEXCOMM mode . */\r
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);\r
+\r
+/*! @brief check whether flexcomm supports peripheral type */\r
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */\r
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];\r
+\r
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */\r
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];\r
+\r
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */\r
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;\r
+\r
+/*! @brief Array to map FLEXCOMM instance number to base address. */\r
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;\r
+\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+/*! @brief IDs of clock for each FLEXCOMM module */\r
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)\r
+/*! @brief Pointers to FLEXCOMM resets for each instance. */\r
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* check whether flexcomm supports peripheral type */\r
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)\r
+{\r
+ if (periph == FLEXCOMM_PERIPH_NONE)\r
+ {\r
+ return true;\r
+ }\r
+ else if (periph <= FLEXCOMM_PERIPH_I2S_TX)\r
+ {\r
+ return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false;\r
+ }\r
+ else if (periph == FLEXCOMM_PERIPH_I2S_RX)\r
+ {\r
+ return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false;\r
+ }\r
+ else\r
+ {\r
+ return false;\r
+ }\r
+}\r
+\r
+/* Get the index corresponding to the FLEXCOMM */\r
+/*! brief Returns instance number for FLEXCOMM module with given base address. */\r
+uint32_t FLEXCOMM_GetInstance(void *base)\r
+{\r
+ int i;\r
+\r
+ for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)\r
+ {\r
+ if ((uint32_t)base == s_flexcommBaseAddrs[i])\r
+ {\r
+ return i;\r
+ }\r
+ }\r
+\r
+ assert(false);\r
+ return 0;\r
+}\r
+\r
+/* Changes FLEXCOMM mode */\r
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)\r
+{\r
+ /* Check whether peripheral type is present */\r
+ if (!FLEXCOMM_PeripheralIsPresent(base, periph))\r
+ {\r
+ return kStatus_OutOfRange;\r
+ }\r
+\r
+ /* Flexcomm is locked to different peripheral type than expected */\r
+ if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph))\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+ /* Check if we are asked to lock */\r
+ if (lock)\r
+ {\r
+ base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->PSELID = (uint32_t)periph;\r
+ }\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */\r
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)\r
+{\r
+ int idx = FLEXCOMM_GetInstance(base);\r
+\r
+ if (idx < 0)\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ /* Enable the peripheral clock */\r
+ CLOCK_EnableClock(s_flexcommClocks[idx]);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)\r
+ /* Reset the FLEXCOMM module */\r
+ RESET_PeripheralReset(s_flexcommResets[idx]);\r
+#endif\r
+\r
+ /* Set the FLEXCOMM to given peripheral */\r
+ return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);\r
+}\r
+\r
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM\r
+ * mode */\r
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(base);\r
+\r
+ /* Clear handler first to avoid execution of the handler with wrong handle */\r
+ s_flexcommIrqHandler[instance] = NULL;\r
+ s_flexcommHandle[instance] = handle;\r
+ s_flexcommIrqHandler[instance] = handler;\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+\r
+/* IRQ handler functions overloading weak symbols in the startup */\r
+#if defined(FLEXCOMM0)\r
+void FLEXCOMM0_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[0]);\r
+ s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM1)\r
+void FLEXCOMM1_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[1]);\r
+ s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM2)\r
+void FLEXCOMM2_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[2]);\r
+ s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM3)\r
+void FLEXCOMM3_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[3]);\r
+ s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM4)\r
+void FLEXCOMM4_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[4]);\r
+ s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+\r
+#endif\r
+\r
+#if defined(FLEXCOMM5)\r
+void FLEXCOMM5_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[5]);\r
+ s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM6)\r
+void FLEXCOMM6_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[6]);\r
+ s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM7)\r
+void FLEXCOMM7_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[7]);\r
+ s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM8)\r
+void FLEXCOMM8_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[8]);\r
+ s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM9)\r
+void FLEXCOMM9_DriverIRQHandler(void)\r
+{\r
+ assert(s_flexcommIrqHandler[9]);\r
+ s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM14)\r
+void FLEXCOMM14_DriverIRQHandler(void)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(FLEXCOMM14);\r
+ assert(s_flexcommIrqHandler[instance]);\r
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
+\r
+#if defined(FLEXCOMM15)\r
+void FLEXCOMM15_DriverIRQHandler(void)\r
+{\r
+ uint32_t instance;\r
+\r
+ /* Look up instance number */\r
+ instance = FLEXCOMM_GetInstance(FLEXCOMM14);\r
+ assert(s_flexcommIrqHandler[instance]);\r
+ s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);\r
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping\r
+ exception return operation might vector to incorrect interrupt */\r
+#if defined __CORTEX_M && (__CORTEX_M == 4U)\r
+ __DSB();\r
+#endif\r
+}\r
+#endif\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2017 NXP\r
+ * All rights reserved.\r
+ * \r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_FLEXCOMM_H_\r
+#define _FSL_FLEXCOMM_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup flexcomm_driver\r
+ * @{\r
+ */\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief FlexCOMM driver version 2.0.0. */\r
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))\r
+/*@}*/\r
+\r
+/*! @brief FLEXCOMM peripheral modes. */\r
+typedef enum\r
+{\r
+ FLEXCOMM_PERIPH_NONE, /*!< No peripheral */\r
+ FLEXCOMM_PERIPH_USART, /*!< USART peripheral */\r
+ FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */\r
+ FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */\r
+ FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */\r
+ FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */\r
+} FLEXCOMM_PERIPH_T;\r
+\r
+/*! @brief Typedef for interrupt handler. */\r
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);\r
+\r
+/*! @brief Array with IRQ number for each FLEXCOMM module. */\r
+extern IRQn_Type const kFlexcommIrqs[];\r
+\r
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */\r
+uint32_t FLEXCOMM_GetInstance(void *base);\r
+\r
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */\r
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);\r
+\r
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM\r
+ * mode */\r
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);\r
+\r
+/*@}*/\r
+\r
+#endif /* _FSL_FLEXCOMM_H_*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_gpio.h"\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+/*! @brief Array to map FGPIO instance number to clock name. */\r
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+\r
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)\r
+/*! @brief Pointers to GPIO resets for each instance. */\r
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;\r
+#endif\r
+/*******************************************************************************\r
+* Prototypes\r
+************ ******************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+/*!\r
+ * brief Initializes the GPIO peripheral.\r
+ *\r
+ * This function ungates the GPIO clock.\r
+ *\r
+ * param base GPIO peripheral base pointer.\r
+ * param port GPIO port number.\r
+ */\r
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)\r
+{\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ assert(port < ARRAY_SIZE(s_gpioClockName));\r
+\r
+ /* Upgate the GPIO clock */\r
+ CLOCK_EnableClock(s_gpioClockName[port]);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)\r
+ /* Reset the GPIO module */\r
+ RESET_PeripheralReset(s_gpioResets[port]);\r
+#endif\r
+}\r
+\r
+/*!\r
+ * brief Initializes a GPIO pin used by the board.\r
+ *\r
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.\r
+ * Then, call the GPIO_PinInit() function.\r
+ *\r
+ * This is an example to define an input pin or output pin configuration:\r
+ * code\r
+ * // Define a digital input pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalInput,\r
+ * 0,\r
+ * }\r
+ * //Define a digital output pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalOutput,\r
+ * 0,\r
+ * }\r
+ * endcode\r
+ *\r
+ * param base GPIO peripheral base pointer(Typically GPIO)\r
+ * param port GPIO port number\r
+ * param pin GPIO pin number\r
+ * param config GPIO pin configuration pointer\r
+ */\r
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)\r
+{\r
+ if (config->pinDirection == kGPIO_DigitalInput)\r
+ {\r
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)\r
+ base->DIRCLR[port] = 1U << pin;\r
+#else\r
+ base->DIR[port] &= ~(1U << pin);\r
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/\r
+ }\r
+ else\r
+ {\r
+ /* Set default output value */\r
+ if (config->outputLogic == 0U)\r
+ {\r
+ base->CLR[port] = (1U << pin);\r
+ }\r
+ else\r
+ {\r
+ base->SET[port] = (1U << pin);\r
+ }\r
+/* Set pin direction */\r
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)\r
+ base->DIRSET[port] = 1U << pin;\r
+#else\r
+ base->DIR[port] |= 1U << pin;\r
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _LPC_GPIO_H_\r
+#define _LPC_GPIO_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup lpc_gpio\r
+ * @{\r
+ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief LPC GPIO driver version 2.1.3. */\r
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))\r
+/*@}*/\r
+\r
+/*! @brief LPC GPIO direction definition */\r
+typedef enum _gpio_pin_direction\r
+{\r
+ kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/\r
+ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/\r
+} gpio_pin_direction_t;\r
+\r
+/*!\r
+ * @brief The GPIO pin configuration structure.\r
+ *\r
+ * Every pin can only be configured as either output pin or input pin at a time.\r
+ * If configured as a input pin, then leave the outputConfig unused.\r
+ */\r
+typedef struct _gpio_pin_config\r
+{\r
+ gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */\r
+ /* Output configurations, please ignore if configured as a input one */\r
+ uint8_t outputLogic; /*!< Set default output logic, no use in input */\r
+} gpio_pin_config_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*! @name GPIO Configuration */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Initializes the GPIO peripheral.\r
+ *\r
+ * This function ungates the GPIO clock.\r
+ *\r
+ * @param base GPIO peripheral base pointer.\r
+ * @param port GPIO port number.\r
+ */\r
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);\r
+\r
+/*!\r
+ * @brief Initializes a GPIO pin used by the board.\r
+ *\r
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.\r
+ * Then, call the GPIO_PinInit() function.\r
+ *\r
+ * This is an example to define an input pin or output pin configuration:\r
+ * @code\r
+ * // Define a digital input pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalInput,\r
+ * 0,\r
+ * }\r
+ * //Define a digital output pin configuration,\r
+ * gpio_pin_config_t config =\r
+ * {\r
+ * kGPIO_DigitalOutput,\r
+ * 0,\r
+ * }\r
+ * @endcode\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number\r
+ * @param config GPIO pin configuration pointer\r
+ */\r
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);\r
+\r
+/*@}*/\r
+\r
+/*! @name GPIO Output Operations */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number\r
+ * @param output GPIO pin output logic level.\r
+ * - 0: corresponding pin output low-logic level.\r
+ * - 1: corresponding pin output high-logic level.\r
+ */\r
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)\r
+{\r
+ base->B[port][pin] = output;\r
+}\r
+\r
+/*@}*/\r
+/*! @name GPIO Input Operations */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Reads the current input value of the GPIO PIN.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param pin GPIO pin number\r
+ * @retval GPIO port input value\r
+ * - 0: corresponding pin input low-logic level.\r
+ * - 1: corresponding pin input high-logic level.\r
+ */\r
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)\r
+{\r
+ return (uint32_t)base->B[port][pin];\r
+}\r
+\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->SET[port] = mask;\r
+}\r
+\r
+/*!\r
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->CLR[port] = mask;\r
+}\r
+\r
+/*!\r
+ * @brief Reverses current output logic of the multiple GPIO pins.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->NOT[port] = mask;\r
+}\r
+\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Reads the current input value of the whole GPIO port.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ */\r
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)\r
+{\r
+ return (uint32_t)base->PIN[port];\r
+}\r
+\r
+/*@}*/\r
+/*! @name GPIO Mask Operations */\r
+/*@{*/\r
+\r
+/*!\r
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param mask GPIO pin number macro\r
+ */\r
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)\r
+{\r
+ base->MASK[port] = mask;\r
+}\r
+\r
+/*!\r
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @param output GPIO port output value.\r
+ */\r
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)\r
+{\r
+ base->MPIN[port] = output;\r
+}\r
+\r
+/*!\r
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be\r
+ * affected.\r
+ *\r
+ * @param base GPIO peripheral base pointer(Typically GPIO)\r
+ * @param port GPIO port number\r
+ * @retval masked GPIO port value\r
+ */\r
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)\r
+{\r
+ return (uint32_t)base->MPIN[port];\r
+}\r
+\r
+/*@}*/\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */\r
+\r
+#endif /* _LPC_GPIO_H_*/\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_IOCON_H_\r
+#define _FSL_IOCON_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup lpc_iocon\r
+ * @{\r
+ */\r
+\r
+/*! @file */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon"\r
+#endif\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief IOCON driver version 2.0.0. */\r
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))\r
+/*@}*/\r
+\r
+/**\r
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format\r
+ */\r
+typedef struct _iocon_group\r
+{\r
+ uint32_t port : 8; /* Pin port */\r
+ uint32_t pin : 8; /* Pin number */\r
+ uint32_t ionumber : 8; /* IO number */\r
+ uint32_t modefunc : 16; /* Function and mode */\r
+} iocon_group_t;\r
+\r
+/**\r
+ * @brief IOCON function and mode selection definitions\r
+ * @note See the User Manual for specific modes and functions supported by the various pins.\r
+ */\r
+#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)\r
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */\r
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */\r
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */\r
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */\r
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */\r
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */\r
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */\r
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */\r
+#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */\r
+#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */\r
+#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */\r
+#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */\r
+#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */\r
+#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */\r
+#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */\r
+#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */\r
+#if defined(IOCON_PIO_MODE_SHIFT)\r
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */\r
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */\r
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */\r
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_EGP_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_SLEW_SHIFT)\r
+#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */\r
+#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_INVERT_SHIFT)\r
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)\r
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */\r
+#define IOCON_DIGITAL_EN \\r
+ (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)\r
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */\r
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)\r
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */\r
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_OD_SHIFT)\r
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)\r
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */\r
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_ASW_SHIFT)\r
+#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_SSEL_SHIFT)\r
+#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */\r
+#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_ECS_SHIFT)\r
+#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */\r
+#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_S_MODE_SHIFT)\r
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */\r
+#define IOCON_S_MODE_1CLK \\r
+ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_2CLK \\r
+ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_3CLK \\r
+ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)\r
+#define IOCON_CLKDIV(div) \\r
+ ((div) \\r
+ << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */\r
+#endif\r
+\r
+#else\r
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */\r
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */\r
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */\r
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */\r
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */\r
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */\r
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */\r
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */\r
+\r
+#if defined(IOCON_PIO_MODE_SHIFT)\r
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */\r
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */\r
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */\r
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_EGP_SHIFT)\r
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */\r
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_INVERT_SHIFT)\r
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)\r
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */\r
+#define IOCON_DIGITAL_EN \\r
+ (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)\r
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */\r
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)\r
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */\r
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_OD_SHIFT)\r
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)\r
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */\r
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_S_MODE_SHIFT)\r
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */\r
+#define IOCON_S_MODE_1CLK \\r
+ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_2CLK \\r
+ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE_3CLK \\r
+ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \\r
+ */\r
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */\r
+#endif\r
+\r
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)\r
+#define IOCON_CLKDIV(div) \\r
+ ((div) \\r
+ << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */\r
+#endif\r
+\r
+#endif\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))\r
+/**\r
+ * @brief Sets I/O Control pin mux\r
+ * @param base : The base of IOCON peripheral on the chip\r
+ * @param ionumber : GPIO number to mux\r
+ * @param modefunc : OR'ed values of type IOCON_*\r
+ * @return Nothing\r
+ */\r
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc)\r
+{\r
+ base->PIO[ionumber] = modefunc;\r
+}\r
+#else\r
+/**\r
+ * @brief Sets I/O Control pin mux\r
+ * @param base : The base of IOCON peripheral on the chip\r
+ * @param port : GPIO port to mux\r
+ * @param pin : GPIO pin to mux\r
+ * @param modefunc : OR'ed values of type IOCON_*\r
+ * @return Nothing\r
+ */\r
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)\r
+{\r
+ base->PIO[port][pin] = modefunc;\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Set all I/O Control pin muxing\r
+ * @param base : The base of IOCON peripheral on the chip\r
+ * @param pinArray : Pointer to array of pin mux selections\r
+ * @param arrayLength : Number of entries in pinArray\r
+ * @return Nothing\r
+ */\r
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)\r
+{\r
+ uint32_t i;\r
+\r
+ for (i = 0; i < arrayLength; i++)\r
+ {\r
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))\r
+ IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc);\r
+#else\r
+ IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);\r
+#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */\r
+ }\r
+}\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+#endif /* _FSL_IOCON_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright (c) 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#include "fsl_common.h"\r
+#include "fsl_power.h"\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.power"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* Empty file since implementation is in header file and power library */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2017, NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_POWER_H_\r
+#define _FSL_POWER_H_\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_device_registers.h"\r
+#include <stdint.h>\r
+\r
+/*!\r
+ * @addtogroup power\r
+ * @{\r
+ */\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief power driver version 1.0.0. */\r
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))\r
+/*@}*/\r
+\r
+\r
+/** @brief Low Power main structure */\r
+typedef enum\r
+{\r
+ VD_AON = 0x0, /*!< Digital Always On power domain */\r
+ VD_MEM = 0x1, /*!< Memories (SRAM) power domain */\r
+ VD_DCDC = 0x2, /*!< Core logic power domain */\r
+ VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */\r
+} LPC_POWER_DOMAIN_T;\r
+\r
+/** @brief Low Power main structure */\r
+typedef struct\r
+{ /* */\r
+ __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */\r
+ __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules\r
+ in the different Low power modes, including ROM */\r
+ __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances\r
+ in the different Low power modes */\r
+ __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */\r
+ __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */\r
+ __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */\r
+ __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */\r
+ __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes\r
+ in case an interrupt is pending when the processor request deepsleep */\r
+ __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */\r
+ __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */\r
+ __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/\r
+ __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some\r
+ interrupt handlers)*/\r
+} LPC_LOWPOWER_T;\r
+\r
+/* */\r
+#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBA /*!< */\r
+\r
+/* Low Power modes */\r
+#define LOWPOWER_CFG_LPMODE_INDEX 0\r
+#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX)\r
+#define LOWPOWER_CFG_SELCLOCK_INDEX 2\r
+#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX)\r
+#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3\r
+#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX)\r
+#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4\r
+#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX)\r
+#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5\r
+#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX)\r
+\r
+#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */\r
+#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */\r
+#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */\r
+#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */\r
+#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */\r
+\r
+#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */\r
+#define LOWPOWER_CFG_SELCLOCK_12MHZ 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/\r
+\r
+#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */\r
+#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */\r
+\r
+#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible -- 1.1V typical -- during low power mode) */\r
+#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible -- down to 0.7V -- during low power mode) */\r
+\r
+#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */\r
+#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */\r
+\r
+/* CPU Retention Control*/\r
+#define LOWPOWER_CPURETCTRL_ENA_INDEX 0\r
+#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX)\r
+#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1\r
+#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX)\r
+#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14\r
+#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX)\r
+\r
+#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */\r
+#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */\r
+\r
+/**\r
+ * @brief Analog components power modes control during low power modes\r
+ */\r
+typedef enum pd_bits\r
+{\r
+ kPDRUNCFG_PD_DCDC = (1UL << 0),\r
+ kPDRUNCFG_PD_BIAS = (1UL << 1),\r
+ kPDRUNCFG_PD_BODCORE = (1UL << 2),\r
+ kPDRUNCFG_PD_BODVBAT = (1UL << 3),\r
+ kPDRUNCFG_PD_FRO1M = (1UL << 4),\r
+ kPDRUNCFG_PD_FRO192M = (1UL << 5),\r
+ kPDRUNCFG_PD_FRO32K = (1UL << 6),\r
+ kPDRUNCFG_PD_XTAL32K = (1UL << 7),\r
+ kPDRUNCFG_PD_XTAL32M = (1UL << 8),\r
+ kPDRUNCFG_PD_PLL0 = (1UL << 9),\r
+ kPDRUNCFG_PD_PLL1 = (1UL << 10),\r
+ kPDRUNCFG_PD_USB0_PHY = (1UL << 11),\r
+ kPDRUNCFG_PD_USB1_PHY = (1UL << 12),\r
+ kPDRUNCFG_PD_COMP = (1UL << 13),\r
+ kPDRUNCFG_PD_TEMPSENS = (1UL << 14),\r
+ kPDRUNCFG_PD_GPADC = (1UL << 15),\r
+ kPDRUNCFG_PD_LDOMEM = (1UL << 16),\r
+ kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17),\r
+ kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),\r
+ kPDRUNCFG_PD_LDOGPADC = (1UL << 19),\r
+ kPDRUNCFG_PD_LDOXO32M = (1UL << 20),\r
+ kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),\r
+ kPDRUNCFG_PD_RNG = (1UL << 22),\r
+ kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),\r
+ kPDRUNCFG_PD_ROM = (1UL << 24),\r
+\r
+ /*\r
+ This enum member has no practical meaning,it is used to avoid MISRA issue,\r
+ user should not trying to use it.\r
+ */\r
+ kPDRUNCFG_ForceUnsigned = 0x80000000U,\r
+} pd_bit_t;\r
+\r
+/**\r
+ * @brief SRAM instances retention control during low power modes\r
+ */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */\r
+#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */\r
+\r
+/**\r
+ * @brief SRAM Low Power Modes\r
+ */\r
+\r
+#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL)\r
+#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */\r
+#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */\r
+#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */\r
+#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */\r
+#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */\r
+\r
+/*@brief BOD VBAT level */\r
+typedef enum _power_bod_vbat_level\r
+{\r
+ kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */\r
+ kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */\r
+ kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */\r
+ kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */\r
+ kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */\r
+ kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */\r
+ kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */\r
+ kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */\r
+ kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */\r
+ kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */\r
+ kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */\r
+ kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */\r
+ kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */\r
+ kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */\r
+ kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */\r
+ kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */\r
+ kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */\r
+ kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */\r
+ kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */\r
+ kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */\r
+ kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */\r
+ kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */\r
+ kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */\r
+ kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */\r
+ kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */\r
+ kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */\r
+} power_bod_vbat_level_t;\r
+\r
+/*@brief BOD core level */\r
+typedef enum _power_bod_core_level\r
+{\r
+ kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */\r
+ kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */\r
+ kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */\r
+ kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */\r
+ kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */\r
+ kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */\r
+ kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */\r
+ kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */\r
+} power_bod_core_level_t;\r
+\r
+/*@brief BOD Hysteresis control */\r
+typedef enum _power_bod_hyst\r
+{\r
+ kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */\r
+ kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */\r
+ kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */\r
+ kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */\r
+} power_bod_hyst_t;\r
+\r
+/**\r
+ * @brief LDO Voltage control in Low Power Modes\r
+ */\r
+#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0\r
+#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX)\r
+#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5\r
+#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX)\r
+#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10\r
+#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX)\r
+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19\r
+#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX)\r
+#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24\r
+#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)\r
+#define LOWPOWER_VOLTAGE_DCDC_INDEX 29\r
+#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX)\r
+\r
+/**\r
+ * @brief Always On and Memories LDO voltage settings\r
+ */\r
+\r
+typedef enum _v_ao\r
+{\r
+ // V_AO_1P220 1.22 = 0, /*!< 1.22 V */\r
+ V_AO_0P700 = 1, /*!< 0.7 V */\r
+ V_AO_0P725 = 2, /*!< 0.725 V */\r
+ V_AO_0P750 = 3, /*!< 0.75 V */\r
+ V_AO_0P775 = 4, /*!< 0.775 V */\r
+ V_AO_0P800 = 5, /*!< 0.8 V */\r
+ V_AO_0P825 = 6, /*!< 0.825 V */\r
+ V_AO_0P850 = 7, /*!< 0.85 V */\r
+ V_AO_0P875 = 8, /*!< 0.875 V */\r
+ V_AO_0P900 = 9, /*!< 0.9 V */\r
+ V_AO_0P960 = 10, /*!< 0.96 V */\r
+ V_AO_0P970 = 11, /*!< 0.97 V */\r
+ V_AO_0P980 = 12, /*!< 0.98 V */\r
+ V_AO_0P990 = 13, /*!< 0.99 V */\r
+ V_AO_1P000 = 14, /*!< 1 V */\r
+ V_AO_1P010 = 15, /*!< 1.01 V */\r
+ V_AO_1P020 = 16, /*!< 1.02 V */\r
+ V_AO_1P030 = 17, /*!< 1.03 V */\r
+ V_AO_1P040 = 18, /*!< 1.04 V */\r
+ V_AO_1P050 = 19, /*!< 1.05 V */\r
+ V_AO_1P060 = 20, /*!< 1.06 V */\r
+ V_AO_1P070 = 21, /*!< 1.07 V */\r
+ V_AO_1P080 = 22, /*!< 1.08 V */\r
+ V_AO_1P090 = 23, /*!< 1.09 V */\r
+ V_AO_1P100 = 24, /*!< 1.1 V */\r
+ V_AO_1P110 = 25, /*!< 1.11 V */\r
+ V_AO_1P120 = 26, /*!< 1.12 V */\r
+ V_AO_1P130 = 27, /*!< 1.13 V */\r
+ V_AO_1P140 = 28, /*!< 1.14 V */\r
+ V_AO_1P150 = 29, /*!< 1.15 V */\r
+ V_AO_1P160 = 30, /*!< 1.16 V */\r
+ V_AO_1P220 = 31 /*!< 1.22 V */\r
+} v_ao_t;\r
+\r
+/**\r
+ * @brief Deep Sleep LDO voltage settings\r
+ */\r
+typedef enum _v_deepsleep\r
+{\r
+ V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */\r
+ V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */\r
+ V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */\r
+ V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */\r
+ V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */\r
+ V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */\r
+ V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */\r
+ V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */\r
+} v_deepsleep_t;\r
+\r
+/**\r
+ * @brief DCDC voltage settings\r
+ */\r
+typedef enum _v_dcdc\r
+{\r
+ V_DCDC_0P950 = 0, /*!< 0.95 V */\r
+ V_DCDC_0P975 = 1, /*!< 0.975 V */\r
+ V_DCDC_1P000 = 2, /*!< 1 V */\r
+ V_DCDC_1P025 = 3, /*!< 1.025 V */\r
+ V_DCDC_1P050 = 4, /*!< 1.050 V */\r
+ V_DCDC_1P075 = 5, /*!< 1.075 V */\r
+ V_DCDC_1P100 = 6, /*!< 1.1 V */\r
+ V_DCDC_1P125 = 7, /*!< 1.125 V */\r
+ V_DCDC_1P150 = 8, /*!< 1.150 V */\r
+ V_DCDC_1P175 = 9, /*!< 1.175 V */\r
+ V_DCDC_1P200 = 10 /*!< 1.2 V */\r
+} v_dcdc_t;\r
+/**\r
+ * @brief LDO_FLASH_NV & LDO_USB voltage settings\r
+ */\r
+typedef enum _v_flashnv\r
+{\r
+ V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */\r
+ V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */\r
+ V_LDOFLASHNV_1P750 = 2, /*!< 1 V */\r
+ V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */\r
+ V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */\r
+ V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */\r
+ V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */\r
+ V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */\r
+} v_flashnv_t;\r
+\r
+/**\r
+ * @brief Low Power Modes Wake up sources\r
+ */\r
+\r
+#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/\r
+#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */\r
+#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */\r
+#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */\r
+#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */\r
+// reserved (1ULL << 23) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+// reserved (1ULL << 25)\r
+// reserved (1ULL << 26)\r
+#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */\r
+#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */\r
+#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */\r
+#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */\r
+// reserved (1ULL << 39)\r
+// reserved (1ULL << 40)\r
+// reserved (1ULL << 41)\r
+#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */\r
+// reserved (1ULL << 43)\r
+// reserved (1ULL << 44)\r
+// reserved (1ULL << 45)\r
+// reserved (1ULL << 46)\r
+#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */\r
+#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_SEC_VIO (1ULL << 53)\r
+#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */\r
+#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */\r
+#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */\r
+#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */\r
+#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */\r
+#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */\r
+// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60)\r
+// reserved WAKEUP_PVTVF0_RED (1ULL << 61)\r
+// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62)\r
+#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */\r
+\r
+\r
+/**\r
+ * @brief Sleep Postpone\r
+ */\r
+#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */\r
+#define LOWPOWER_HWWAKE_PERIPHERALS (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted */\r
+#define LOWPOWER_HWWAKE_SDMA0 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */\r
+#define LOWPOWER_HWWAKE_SDMA1 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */\r
+#define LOWPOWER_HWWAKE_ENABLE_FRO192M (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */\r
+\r
+/**\r
+ * @brief Wake up I/O sources\r
+ */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */\r
+#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */\r
+\r
+#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */\r
+#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */\r
+#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */\r
+#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */\r
+\r
+/**\r
+ * @brief Wake up timers configuration in Low Power Modes\r
+ */\r
+#define LOWPOWER_TIMERCFG_CTRL_INDEX 0\r
+#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX)\r
+#define LOWPOWER_TIMERCFG_TIMER_INDEX 1\r
+#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX)\r
+#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4\r
+#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX)\r
+\r
+#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */\r
+#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */\r
+\r
+/**\r
+ * @brief Primary Wake up timers configuration in Low Power Modes\r
+ */\r
+#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */\r
+#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */\r
+#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */\r
+\r
+#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */\r
+#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */\r
+\r
+//! @brief Interface for lowpower functions\r
+typedef struct LowpowerDriverInterface\r
+{\r
+ void (*power_cycle_cpu_and_flash)(void);\r
+ void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg);\r
+} lowpower_driver_interface_t;\r
+\r
+/* Power mode configuration API parameter */\r
+typedef enum _power_mode_config\r
+{\r
+ kPmu_Sleep = 0U,\r
+ kPmu_Deep_Sleep = 1U,\r
+ kPmu_PowerDown = 2U,\r
+ kPmu_Deep_PowerDown = 3U,\r
+} power_mode_cfg_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral\r
+ *\r
+ * @param en peripheral for which to enable the PDRUNCFG bit\r
+ * @return none\r
+ */\r
+static inline void POWER_EnablePD(pd_bit_t en)\r
+{\r
+ /* PDRUNCFGSET */\r
+ PMC->PDRUNCFGSET0 = en;\r
+}\r
+\r
+/*!\r
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral\r
+ *\r
+ * @param en peripheral for which to disable the PDRUNCFG bit\r
+ * @return none\r
+ */\r
+static inline void POWER_DisablePD(pd_bit_t en)\r
+{\r
+ /* PDRUNCFGCLR */\r
+ PMC->PDRUNCFGCLR0 = en;\r
+}\r
+\r
+/*!\r
+ * @brief set BOD VBAT level.\r
+ *\r
+ * @param level BOD detect level\r
+ * @param hyst BoD Hysteresis control\r
+ * @param enBodVbatReset VBAT brown out detect reset\r
+ */\r
+static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset)\r
+{\r
+ PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) |\r
+ PMC_BODVBAT_HYST(hyst);\r
+ PMC->RESETCTRL =\r
+ (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset);\r
+}\r
+\r
+/*!\r
+ * @brief set BOD core level.\r
+ *\r
+ * @param level BOD detect level\r
+ * @param hyst BoD Hysteresis control\r
+ * @param enBodCoreReset core brown out detect reset\r
+ */\r
+static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset)\r
+{\r
+ PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) |\r
+ PMC_BODCORE_HYST(hyst);\r
+ PMC->RESETCTRL =\r
+ (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset);\r
+}\r
+\r
+/*!\r
+ * @brief API to enable deep sleep bit in the ARM Core.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+static inline void POWER_EnableDeepSleep(void)\r
+{\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\r
+}\r
+\r
+/*!\r
+ * @brief API to disable deep sleep bit in the ARM Core.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+static inline void POWER_DisableDeepSleep(void)\r
+{\r
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;\r
+}\r
+\r
+/*!\r
+ * @brief API to power down flash controller.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+static inline void POWER_PowerDownFlash(void)\r
+{\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */\r
+ CLOCK_DisableClock(kCLOCK_Flash);\r
+\r
+ /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */\r
+ CLOCK_DisableClock(kCLOCK_Fmc);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+}\r
+\r
+/*!\r
+ * @brief API to power up flash controller.\r
+ *\r
+ * @param none\r
+ * @return none\r
+ */\r
+static inline void POWER_PowerUpFlash(void)\r
+{\r
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)\r
+ /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */\r
+ CLOCK_EnableClock(kCLOCK_Fmc);\r
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */\r
+}\r
+\r
+/**\r
+ * @brief Configures and enters in low power mode\r
+ * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters\r
+ * @return Nothing\r
+ *\r
+ * !!! IMPORTANT NOTES :\r
+ * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the\r
+ * API.\r
+ * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk\r
+ * of Dead Lock).\r
+ * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip\r
+ * reset)\r
+ */\r
+void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg);\r
+\r
+/**\r
+ * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event\r
+ * This MUST BE EXECUTED outside the Flash:\r
+ * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is\r
+ * preferable to have all functions defined in this file implemented in ROM.\r
+ * @param None\r
+ * @return Nothing\r
+ */\r
+void POWER_CycleCpuAndFlash(void);\r
+\r
+/**\r
+ * @brief Configures and enters in DEEP-SLEEP low power mode\r
+ * @param exclude_from_pd:\r
+ * @param sram_retention_ctrl:\r
+ * @param wakeup_interrupts:\r
+ * @param hardware_wake_ctrl:\r
+\r
+ * @return Nothing\r
+ *\r
+ * !!! IMPORTANT NOTES :\r
+ 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.\r
+ * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).\r
+ * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)\r
+ reset)\r
+ */\r
+void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts,uint32_t hardware_wake_ctrl);\r
+\r
+/**\r
+ * @brief Configures and enters in POWERDOWN low power mode\r
+ * @param exclude_from_pd:\r
+ * @param sram_retention_ctrl:\r
+ * @param wakeup_interrupts:\r
+ * @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are\r
+ RESERVED.\r
+\r
+ * @return Nothing\r
+ *\r
+ * !!! IMPORTANT NOTES :\r
+ 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.\r
+ * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).\r
+ * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl")\r
+ * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)\r
+ reset)\r
+ */\r
+void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl);\r
+\r
+/**\r
+ * @brief Configures and enters in DEEPPOWERDOWN low power mode\r
+ * @param exclude_from_pd:\r
+ * @param sram_retention_ctrl:\r
+ * @param wakeup_interrupts:\r
+ * @param wakeup_io_ctrl:\r
+\r
+ * @return Nothing\r
+ *\r
+ * !!! IMPORTANT NOTES :\r
+ 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.\r
+ * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).\r
+ * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)\r
+ */\r
+void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl);\r
+\r
+/**\r
+ * @brief Configures and enters in SLEEP low power mode\r
+ * @param :\r
+ * @return Nothing\r
+ */\r
+void POWER_EnterSleep(void);\r
+\r
+/*!\r
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.\r
+ *\r
+ * @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate,\r
+ * note that the voltage and flash wait states should be set before changing frequency\r
+ * @return none\r
+ */\r
+void POWER_SetVoltageForFreq(uint32_t system_freq_hz);\r
+\r
+/*!\r
+ * @brief Power Library API to return the library version.\r
+ *\r
+ * @param none\r
+ * @return version number of the power library\r
+ */\r
+uint32_t POWER_GetLibVersion(void);\r
+\r
+/**\r
+ * @brief Sets board-specific trim values for 16MHz XTAL\r
+ * @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @return none\r
+ * @note Following default Values can be used:\r
+ * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600\r
+ * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20\r
+ * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40\r
+ */\r
+extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100);\r
+/**\r
+ * @brief Sets board-specific trim values for 32kHz XTAL\r
+ * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+ * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120\r
+\r
+ * @return none\r
+ * @note Following default Values can be used:\r
+ * pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600\r
+ * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40\r
+ * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40\r
+ */\r
+extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100);\r
+/**\r
+ * @brief Enables and sets LDO for 16MHz XTAL\r
+ * @param none\r
+ * @return none\r
+ */\r
+extern void POWER_SetXtal16mhzLdo(void);\r
+/**\r
+ * @brief Set up 16-MHz XTAL Trimmings\r
+ * @param amp Amplitude\r
+ * @param gm Transconductance\r
+ * @return none\r
+ */\r
+extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);\r
+#ifdef __cplusplus\r
+ }\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* _FSL_POWER_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright (c) 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_reset.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.reset"\r
+#endif\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))\r
+\r
+/*!\r
+ * brief Assert reset to peripheral.\r
+ *\r
+ * Asserts reset signal to specified peripheral module.\r
+ *\r
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)\r
+{\r
+ const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;\r
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);\r
+ const uint32_t bitMask = 1u << bitPos;\r
+\r
+ assert(bitPos < 32u);\r
+\r
+ /* reset register is in SYSCON */\r
+ /* set bit */\r
+ SYSCON->PRESETCTRLSET[regIndex] = bitMask;\r
+ /* wait until it reads 0b1 */\r
+ while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask))\r
+ {\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Clear reset to peripheral.\r
+ *\r
+ * Clears reset signal to specified peripheral module, allows it to operate.\r
+ *\r
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)\r
+{\r
+ const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;\r
+ const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);\r
+ const uint32_t bitMask = 1u << bitPos;\r
+\r
+ assert(bitPos < 32u);\r
+\r
+ /* reset register is in SYSCON */\r
+\r
+ /* clear bit */\r
+ SYSCON->PRESETCTRLCLR[regIndex] = bitMask;\r
+ /* wait until it reads 0b0 */\r
+ while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask))\r
+ {\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Reset peripheral module.\r
+ *\r
+ * Reset peripheral module.\r
+ *\r
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_PeripheralReset(reset_ip_name_t peripheral)\r
+{\r
+ RESET_SetPeripheralReset(peripheral);\r
+ RESET_ClearPeripheralReset(peripheral);\r
+}\r
+\r
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright (c) 2016, NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#ifndef _FSL_RESET_H_\r
+#define _FSL_RESET_H_\r
+\r
+#include <assert.h>\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include <string.h>\r
+#include "fsl_device_registers.h"\r
+\r
+/*!\r
+ * @addtogroup ksdk_common\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief reset driver version 2.0.0. */\r
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))\r
+/*@}*/\r
+\r
+/*!\r
+ * @brief Enumeration for peripheral reset control bits\r
+ *\r
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers\r
+ */\r
+typedef enum _SYSCON_RSTn\r
+{\r
+ kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */\r
+ kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */\r
+ kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */\r
+ kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */\r
+ kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */\r
+ kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */\r
+ kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */\r
+ kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */\r
+ kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */\r
+ kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */\r
+ kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */\r
+ kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */\r
+ kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */\r
+ kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */\r
+ kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */\r
+ kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */\r
+ kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */\r
+ kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */\r
+ kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */\r
+ kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */\r
+ kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */\r
+ kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */\r
+\r
+ kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */\r
+ kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */\r
+ kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */\r
+ kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */\r
+ kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */\r
+ kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */\r
+ kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */\r
+ kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */\r
+ kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */\r
+ kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */\r
+ kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */\r
+ kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */\r
+ kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */\r
+ kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */\r
+ kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */\r
+ kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */\r
+ kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */\r
+ kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */\r
+ kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */\r
+ kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */\r
+\r
+ kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */\r
+ kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */\r
+ kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */\r
+ kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */\r
+ kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */\r
+ kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */\r
+ kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */\r
+ kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */\r
+ kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */\r
+ kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */\r
+ kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */\r
+ kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */\r
+ kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */\r
+ kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */\r
+ kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */\r
+ kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */\r
+ kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */\r
+ kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */\r
+ kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */\r
+ kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */\r
+ kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */\r
+ kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */\r
+ kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */\r
+ kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */\r
+ kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */\r
+ kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */\r
+ kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */\r
+ kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */\r
+ kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */\r
+} SYSCON_RSTn_t;\r
+\r
+/** Array initializers with peripheral reset bits **/\r
+#define ADC_RSTS \\r
+ { \\r
+ kADC0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for ADC peripheral */\r
+#define AES_RSTS \\r
+ { \\r
+ kAES_RST_SHIFT_RSTn \\r
+ } /* Reset bits for AES peripheral */\r
+#define CRC_RSTS \\r
+ { \\r
+ kCRC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CRC peripheral */\r
+#define CTIMER_RSTS \\r
+ { \\r
+ kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \\r
+ kCTIMER4_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CTIMER peripheral */\r
+#define DMA_RSTS_N \\r
+ { \\r
+ kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \\r
+ } /* Reset bits for DMA peripheral */\r
+\r
+#define FLEXCOMM_RSTS \\r
+ { \\r
+ kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \\r
+ kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \\r
+ } /* Reset bits for FLEXCOMM peripheral */\r
+#define GINT_RSTS \\r
+ { \\r
+ kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */\r
+#define GPIO_RSTS_N \\r
+ { \\r
+ kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \\r
+ kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \\r
+ } /* Reset bits for GPIO peripheral */\r
+#define INPUTMUX_RSTS \\r
+ { \\r
+ kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \\r
+ } /* Reset bits for INPUTMUX peripheral */\r
+#define IOCON_RSTS \\r
+ { \\r
+ kIOCON_RST_SHIFT_RSTn \\r
+ } /* Reset bits for IOCON peripheral */\r
+#define FLASH_RSTS \\r
+ { \\r
+ kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \\r
+ } /* Reset bits for Flash peripheral */\r
+#define MRT_RSTS \\r
+ { \\r
+ kMRT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for MRT peripheral */\r
+#define OTP_RSTS \\r
+ { \\r
+ kOTP_RST_SHIFT_RSTn \\r
+ } /* Reset bits for OTP peripheral */\r
+#define PINT_RSTS \\r
+ { \\r
+ kPINT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for PINT peripheral */\r
+#define RNG_RSTS \\r
+ { \\r
+ kRNG_RST_SHIFT_RSTn \\r
+ } /* Reset bits for RNG peripheral */\r
+#define SDIO_RST \\r
+ { \\r
+ kSDIO_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SDIO peripheral */\r
+#define SCT_RSTS \\r
+ { \\r
+ kSCT0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SCT peripheral */\r
+#define SPIFI_RSTS \\r
+ { \\r
+ kSPIFI_RST_SHIFT_RSTn \\r
+ } /* Reset bits for SPIFI peripheral */\r
+#define USB0D_RST \\r
+ { \\r
+ kUSB0D_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0D peripheral */\r
+#define USB0HMR_RST \\r
+ { \\r
+ kUSB0HMR_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0HMR peripheral */\r
+#define USB0HSL_RST \\r
+ { \\r
+ kUSB0HSL_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB0HSL peripheral */\r
+#define USB1H_RST \\r
+ { \\r
+ kUSB1H_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1H peripheral */\r
+#define USB1D_RST \\r
+ { \\r
+ kUSB1D_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1D peripheral */\r
+#define USB1RAM_RST \\r
+ { \\r
+ kUSB1RAM_RST_SHIFT_RSTn \\r
+ } /* Reset bits for USB1RAM peripheral */\r
+#define UTICK_RSTS \\r
+ { \\r
+ kUTICK_RST_SHIFT_RSTn \\r
+ } /* Reset bits for UTICK peripheral */\r
+#define WWDT_RSTS \\r
+ { \\r
+ kWWDT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for WWDT peripheral */\r
+#define CAPT_RSTS_N \\r
+ { \\r
+ kCAP0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for CAPT peripheral */\r
+#define PLU_RSTS_N \\r
+ { \\r
+ kPLULUT_RST_SHIFT_RSTn \\r
+ } /* Reset bits for PLU peripheral */\r
+#define OSTIMER_RSTS \\r
+ { \\r
+ kOSTIMER0_RST_SHIFT_RSTn \\r
+ } /* Reset bits for OSTIMER peripheral */\r
+typedef SYSCON_RSTn_t reset_ip_name_t;\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/*!\r
+ * @brief Assert reset to peripheral.\r
+ *\r
+ * Asserts reset signal to specified peripheral module.\r
+ *\r
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);\r
+\r
+/*!\r
+ * @brief Clear reset to peripheral.\r
+ *\r
+ * Clears reset signal to specified peripheral module, allows it to operate.\r
+ *\r
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);\r
+\r
+/*!\r
+ * @brief Reset peripheral module.\r
+ *\r
+ * Reset peripheral module.\r
+ *\r
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register\r
+ * and reset bit position in the reset register.\r
+ */\r
+void RESET_PeripheralReset(reset_ip_name_t peripheral);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_RESET_H_ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_usart.h"\r
+#include "fsl_device_registers.h"\r
+#include "fsl_flexcomm.h"\r
+\r
+/* Component ID definition, used by tools. */\r
+#ifndef FSL_COMPONENT_ID\r
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"\r
+#endif\r
+\r
+enum _usart_transfer_states\r
+{\r
+ kUSART_TxIdle, /* TX idle. */\r
+ kUSART_TxBusy, /* TX busy. */\r
+ kUSART_RxIdle, /* RX idle. */\r
+ kUSART_RxBusy /* RX busy. */\r
+};\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*! @brief IRQ name array */\r
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;\r
+\r
+/*! @brief Array to map USART instance number to base address. */\r
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+/* Get the index corresponding to the USART */\r
+/*! brief Returns instance number for USART peripheral base address. */\r
+uint32_t USART_GetInstance(USART_Type *base)\r
+{\r
+ int i;\r
+\r
+ for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++)\r
+ {\r
+ if ((uint32_t)base == s_usartBaseAddrs[i])\r
+ {\r
+ return i;\r
+ }\r
+ }\r
+\r
+ assert(false);\r
+ return 0;\r
+}\r
+\r
+/*!\r
+ * brief Get the length of received data in RX ring buffer.\r
+ *\r
+ * param handle USART handle pointer.\r
+ * return Length of received data in RX ring buffer.\r
+ */\r
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)\r
+{\r
+ size_t size;\r
+\r
+ /* Check arguments */\r
+ assert(NULL != handle);\r
+\r
+ if (handle->rxRingBufferTail > handle->rxRingBufferHead)\r
+ {\r
+ size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail);\r
+ }\r
+ else\r
+ {\r
+ size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail);\r
+ }\r
+ return size;\r
+}\r
+\r
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)\r
+{\r
+ bool full;\r
+\r
+ /* Check arguments */\r
+ assert(NULL != handle);\r
+\r
+ if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))\r
+ {\r
+ full = true;\r
+ }\r
+ else\r
+ {\r
+ full = false;\r
+ }\r
+ return full;\r
+}\r
+\r
+/*!\r
+ * brief Sets up the RX ring buffer.\r
+ *\r
+ * This function sets up the RX ring buffer to a specific USART handle.\r
+ *\r
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the\r
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received\r
+ * in the ring buffer, the user can get the received data from the ring buffer directly.\r
+ *\r
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other\r
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.\r
+ * param ringBufferSize size of the ring buffer.\r
+ */\r
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != base);\r
+ assert(NULL != handle);\r
+ assert(NULL != ringBuffer);\r
+\r
+ /* Setup the ringbuffer address */\r
+ handle->rxRingBuffer = ringBuffer;\r
+ handle->rxRingBufferSize = ringBufferSize;\r
+ handle->rxRingBufferHead = 0U;\r
+ handle->rxRingBufferTail = 0U;\r
+ /* ring buffer is ready we can start receiving data */\r
+ base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;\r
+}\r
+\r
+/*!\r
+ * brief Aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * This function aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != base);\r
+ assert(NULL != handle);\r
+\r
+ if (handle->rxState == kUSART_RxIdle)\r
+ {\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;\r
+ }\r
+ handle->rxRingBuffer = NULL;\r
+ handle->rxRingBufferSize = 0U;\r
+ handle->rxRingBufferHead = 0U;\r
+ handle->rxRingBufferTail = 0U;\r
+}\r
+\r
+/*!\r
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.\r
+ *\r
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration\r
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.\r
+ * Example below shows how to use this API to configure USART.\r
+ * code\r
+ * usart_config_t usartConfig;\r
+ * usartConfig.baudRate_Bps = 115200U;\r
+ * usartConfig.parityMode = kUSART_ParityDisabled;\r
+ * usartConfig.stopBitCount = kUSART_OneStopBit;\r
+ * USART_Init(USART1, &usartConfig, 20000000U);\r
+ * endcode\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param config Pointer to user-defined configuration structure.\r
+ * param srcClock_Hz USART clock source frequency in HZ.\r
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * retval kStatus_InvalidArgument USART base address is not valid\r
+ * retval kStatus_Success Status USART initialize succeed\r
+ */\r
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)\r
+{\r
+ int result;\r
+\r
+ /* check arguments */\r
+ assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz)));\r
+ if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* initialize flexcomm to USART mode */\r
+ result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);\r
+ if (kStatus_Success != result)\r
+ {\r
+ return result;\r
+ }\r
+\r
+ /* setup baudrate */\r
+ result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);\r
+ if (kStatus_Success != result)\r
+ {\r
+ return result;\r
+ }\r
+\r
+ if (config->enableTx)\r
+ {\r
+ /* empty and enable txFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;\r
+ /* setup trigger level */\r
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);\r
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);\r
+ /* enable trigger interrupt */\r
+ base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;\r
+ }\r
+\r
+ /* empty and enable rxFIFO */\r
+ if (config->enableRx)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;\r
+ /* setup trigger level */\r
+ base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);\r
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);\r
+ /* enable trigger interrupt */\r
+ base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;\r
+ }\r
+ /* setup configuration and enable USART */\r
+ base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |\r
+ USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | USART_CFG_ENABLE_MASK;\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Deinitializes a USART instance.\r
+ *\r
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.\r
+ *\r
+ * param base USART peripheral base address.\r
+ */\r
+void USART_Deinit(USART_Type *base)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != base);\r
+ while (!(base->STAT & USART_STAT_TXIDLE_MASK))\r
+ {\r
+ }\r
+ /* Disable interrupts, disable dma requests, disable peripheral */\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |\r
+ USART_FIFOINTENCLR_RXLVL_MASK;\r
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);\r
+ base->CFG &= ~(USART_CFG_ENABLE_MASK);\r
+}\r
+\r
+/*!\r
+ * brief Gets the default configuration structure.\r
+ *\r
+ * This function initializes the USART configuration structure to a default value. The default\r
+ * values are:\r
+ * usartConfig->baudRate_Bps = 115200U;\r
+ * usartConfig->parityMode = kUSART_ParityDisabled;\r
+ * usartConfig->stopBitCount = kUSART_OneStopBit;\r
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;\r
+ * usartConfig->loopback = false;\r
+ * usartConfig->enableTx = false;\r
+ * usartConfig->enableRx = false;\r
+ *\r
+ * param config Pointer to configuration structure.\r
+ */\r
+void USART_GetDefaultConfig(usart_config_t *config)\r
+{\r
+ /* Check arguments */\r
+ assert(NULL != config);\r
+\r
+ /* Initializes the configure structure to zero. */\r
+ memset(config, 0, sizeof(*config));\r
+\r
+ /* Set always all members ! */\r
+ config->baudRate_Bps = 115200U;\r
+ config->parityMode = kUSART_ParityDisabled;\r
+ config->stopBitCount = kUSART_OneStopBit;\r
+ config->bitCountPerChar = kUSART_8BitsPerChar;\r
+ config->loopback = false;\r
+ config->enableRx = false;\r
+ config->enableTx = false;\r
+ config->txWatermark = kUSART_TxFifo0;\r
+ config->rxWatermark = kUSART_RxFifo1;\r
+}\r
+\r
+/*!\r
+ * brief Sets the USART instance baud rate.\r
+ *\r
+ * This function configures the USART module baud rate. This function is used to update\r
+ * the USART module baud rate after the USART module is initialized by the USART_Init.\r
+ * code\r
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);\r
+ * endcode\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param baudrate_Bps USART baudrate to be set.\r
+ * param srcClock_Hz USART clock source freqency in HZ.\r
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * retval kStatus_Success Set baudrate succeed.\r
+ * retval kStatus_InvalidArgument One or more arguments are invalid.\r
+ */\r
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)\r
+{\r
+ uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;\r
+ uint32_t osrval, brgval, diff, baudrate;\r
+\r
+ /* check arguments */\r
+ assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));\r
+ if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /*\r
+ * Smaller values of OSR can make the sampling position within a data bit less accurate and may\r
+ * potentially cause more noise errors or incorrect data.\r
+ */\r
+ for (osrval = best_osrval; osrval >= 8; osrval--)\r
+ {\r
+ brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1;\r
+ if (brgval > 0xFFFF)\r
+ {\r
+ continue;\r
+ }\r
+ baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1));\r
+ diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;\r
+ if (diff < best_diff)\r
+ {\r
+ best_diff = diff;\r
+ best_osrval = osrval;\r
+ best_brgval = brgval;\r
+ }\r
+ }\r
+\r
+ /* value over range */\r
+ if (best_brgval > 0xFFFF)\r
+ {\r
+ return kStatus_USART_BaudrateNotSupport;\r
+ }\r
+\r
+ base->OSR = best_osrval;\r
+ base->BRG = best_brgval;\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Writes to the TX register using a blocking method.\r
+ *\r
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO\r
+ * to have room and writes data to the TX buffer.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param data Start address of the data to write.\r
+ * param length Size of the data to write.\r
+ */\r
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)\r
+{\r
+ /* Check arguments */\r
+ assert(!((NULL == base) || (NULL == data)));\r
+ if ((NULL == base) || (NULL == data))\r
+ {\r
+ return;\r
+ }\r
+ /* Check whether txFIFO is enabled */\r
+ if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))\r
+ {\r
+ return;\r
+ }\r
+ for (; length > 0; length--)\r
+ {\r
+ /* Loop until txFIFO get some space for new data */\r
+ while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))\r
+ {\r
+ }\r
+ base->FIFOWR = *data;\r
+ data++;\r
+ }\r
+ /* Wait to finish transfer */\r
+ while (!(base->STAT & USART_STAT_TXIDLE_MASK))\r
+ {\r
+ }\r
+}\r
+\r
+/*!\r
+ * brief Read RX data register using a blocking method.\r
+ *\r
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to\r
+ * have data and read data from the TX register.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param data Start address of the buffer to store the received data.\r
+ * param length Size of the buffer.\r
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.\r
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.\r
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.\r
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.\r
+ * retval kStatus_Success Successfully received all data.\r
+ */\r
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)\r
+{\r
+ uint32_t status;\r
+\r
+ /* check arguments */\r
+ assert(!((NULL == base) || (NULL == data)));\r
+ if ((NULL == base) || (NULL == data))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* Check whether rxFIFO is enabled */\r
+ if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK))\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+ for (; length > 0; length--)\r
+ {\r
+ /* loop until rxFIFO have some data to read */\r
+ while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))\r
+ {\r
+ }\r
+ /* check receive status */\r
+ status = base->STAT;\r
+ if (status & USART_STAT_FRAMERRINT_MASK)\r
+ {\r
+ base->STAT |= USART_STAT_FRAMERRINT_MASK;\r
+ return kStatus_USART_FramingError;\r
+ }\r
+ if (status & USART_STAT_PARITYERRINT_MASK)\r
+ {\r
+ base->STAT |= USART_STAT_PARITYERRINT_MASK;\r
+ return kStatus_USART_ParityError;\r
+ }\r
+ if (status & USART_STAT_RXNOISEINT_MASK)\r
+ {\r
+ base->STAT |= USART_STAT_RXNOISEINT_MASK;\r
+ return kStatus_USART_NoiseError;\r
+ }\r
+ /* check rxFIFO status */\r
+ if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
+ return kStatus_USART_RxError;\r
+ }\r
+\r
+ *data = base->FIFORD;\r
+ data++;\r
+ }\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Initializes the USART handle.\r
+ *\r
+ * This function initializes the USART handle which can be used for other USART\r
+ * transactional APIs. Usually, for a specified USART instance,\r
+ * call this API once to get the initialized handle.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param callback The callback function.\r
+ * param userData The parameter of the callback function.\r
+ */\r
+status_t USART_TransferCreateHandle(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_callback_t callback,\r
+ void *userData)\r
+{\r
+ int32_t instance = 0;\r
+\r
+ /* Check 'base' */\r
+ assert(!((NULL == base) || (NULL == handle)));\r
+ if ((NULL == base) || (NULL == handle))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ instance = USART_GetInstance(base);\r
+\r
+ memset(handle, 0, sizeof(*handle));\r
+ /* Set the TX/RX state. */\r
+ handle->rxState = kUSART_RxIdle;\r
+ handle->txState = kUSART_TxIdle;\r
+ /* Set the callback and user data. */\r
+ handle->callback = callback;\r
+ handle->userData = userData;\r
+ handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base);\r
+ handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base);\r
+\r
+ FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle);\r
+\r
+ /* Enable interrupt in NVIC. */\r
+ EnableIRQ(s_usartIRQ[instance]);\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback\r
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.\r
+ *\r
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written\r
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,\r
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param xfer USART transfer structure. See #usart_transfer_t.\r
+ * retval kStatus_Success Successfully start the data transmission.\r
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.\r
+ * retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)\r
+{\r
+ /* Check arguments */\r
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));\r
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+ /* Check xfer members */\r
+ assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));\r
+ if ((0 == xfer->dataSize) || (NULL == xfer->data))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* Return error if current TX busy. */\r
+ if (kUSART_TxBusy == handle->txState)\r
+ {\r
+ return kStatus_USART_TxBusy;\r
+ }\r
+ else\r
+ {\r
+ handle->txData = xfer->data;\r
+ handle->txDataSize = xfer->dataSize;\r
+ handle->txDataSizeAll = xfer->dataSize;\r
+ handle->txState = kUSART_TxBusy;\r
+ /* Enable transmiter interrupt. */\r
+ base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;\r
+ }\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Aborts the interrupt-driven data transmit.\r
+ *\r
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out\r
+ * how many bytes are still not sent out.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ assert(NULL != handle);\r
+\r
+ /* Disable interrupts */\r
+ USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable);\r
+ /* Empty txFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;\r
+\r
+ handle->txDataSize = 0;\r
+ handle->txState = kUSART_TxIdle;\r
+}\r
+\r
+/*!\r
+ * brief Get the number of bytes that have been written to USART TX register.\r
+ *\r
+ * This function gets the number of bytes that have been written to USART TX\r
+ * register by interrupt method.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param count Send bytes count.\r
+ * retval kStatus_NoTransferInProgress No send in progress.\r
+ * retval kStatus_InvalidArgument Parameter is invalid.\r
+ * retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)\r
+{\r
+ assert(NULL != handle);\r
+ assert(NULL != count);\r
+\r
+ if (kUSART_TxIdle == handle->txState)\r
+ {\r
+ return kStatus_NoTransferInProgress;\r
+ }\r
+\r
+ *count = handle->txDataSizeAll - handle->txDataSize;\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns without waiting for all data to be received.\r
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and\r
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.\r
+ * After copying, if the data in the ring buffer is not enough to read, the receive\r
+ * request is saved by the USART driver. When the new data arrives, the receive request\r
+ * is serviced first. When all data is received, the USART driver notifies the upper layer\r
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.\r
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.\r
+ * The 5 bytes are copied to the xfer->data and this function returns with the\r
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is\r
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.\r
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt\r
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param xfer USART transfer structure, see #usart_transfer_t.\r
+ * param receivedBytes Bytes received from the ring buffer directly.\r
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.\r
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.\r
+ * retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_t *xfer,\r
+ size_t *receivedBytes)\r
+{\r
+ uint32_t i;\r
+ /* How many bytes to copy from ring buffer to user memory. */\r
+ size_t bytesToCopy = 0U;\r
+ /* How many bytes to receive. */\r
+ size_t bytesToReceive;\r
+ /* How many bytes currently have received. */\r
+ size_t bytesCurrentReceived;\r
+ uint32_t regPrimask = 0U;\r
+\r
+ /* Check arguments */\r
+ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));\r
+ if ((NULL == base) || (NULL == handle) || (NULL == xfer))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+ /* Check xfer members */\r
+ assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));\r
+ if ((0 == xfer->dataSize) || (NULL == xfer->data))\r
+ {\r
+ return kStatus_InvalidArgument;\r
+ }\r
+\r
+ /* How to get data:\r
+ 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize\r
+ to uart handle, enable interrupt to store received data to xfer->data. When\r
+ all data received, trigger callback.\r
+ 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.\r
+ If there are enough data in ring buffer, copy them to xfer->data and return.\r
+ If there are not enough data in ring buffer, copy all of them to xfer->data,\r
+ save the xfer->data remained empty space to uart handle, receive data\r
+ to this empty space and trigger callback when finished. */\r
+ if (kUSART_RxBusy == handle->rxState)\r
+ {\r
+ return kStatus_USART_RxBusy;\r
+ }\r
+ else\r
+ {\r
+ bytesToReceive = xfer->dataSize;\r
+ bytesCurrentReceived = 0U;\r
+ /* If RX ring buffer is used. */\r
+ if (handle->rxRingBuffer)\r
+ {\r
+ /* Disable IRQ, protect ring buffer. */\r
+ regPrimask = DisableGlobalIRQ();\r
+ /* How many bytes in RX ring buffer currently. */\r
+ bytesToCopy = USART_TransferGetRxRingBufferLength(handle);\r
+ if (bytesToCopy)\r
+ {\r
+ bytesToCopy = MIN(bytesToReceive, bytesToCopy);\r
+ bytesToReceive -= bytesToCopy;\r
+ /* Copy data from ring buffer to user memory. */\r
+ for (i = 0U; i < bytesToCopy; i++)\r
+ {\r
+ xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];\r
+ /* Wrap to 0. Not use modulo (%) because it might be large and slow. */\r
+ if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
+ {\r
+ handle->rxRingBufferTail = 0U;\r
+ }\r
+ else\r
+ {\r
+ handle->rxRingBufferTail++;\r
+ }\r
+ }\r
+ }\r
+ /* If ring buffer does not have enough data, still need to read more data. */\r
+ if (bytesToReceive)\r
+ {\r
+ /* No data in ring buffer, save the request to UART handle. */\r
+ handle->rxData = xfer->data + bytesCurrentReceived;\r
+ handle->rxDataSize = bytesToReceive;\r
+ handle->rxDataSizeAll = bytesToReceive;\r
+ handle->rxState = kUSART_RxBusy;\r
+ }\r
+ /* Enable IRQ if previously enabled. */\r
+ EnableGlobalIRQ(regPrimask);\r
+ /* Call user callback since all data are received. */\r
+ if (0 == bytesToReceive)\r
+ {\r
+ if (handle->callback)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);\r
+ }\r
+ }\r
+ }\r
+ /* Ring buffer not used. */\r
+ else\r
+ {\r
+ handle->rxData = xfer->data + bytesCurrentReceived;\r
+ handle->rxDataSize = bytesToReceive;\r
+ handle->rxDataSizeAll = bytesToReceive;\r
+ handle->rxState = kUSART_RxBusy;\r
+\r
+ /* Enable RX interrupt. */\r
+ base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;\r
+ }\r
+ /* Return the how many bytes have read. */\r
+ if (receivedBytes)\r
+ {\r
+ *receivedBytes = bytesCurrentReceived;\r
+ }\r
+ }\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out\r
+ * how many bytes not received yet.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ assert(NULL != handle);\r
+\r
+ /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */\r
+ if (!handle->rxRingBuffer)\r
+ {\r
+ /* Disable interrupts */\r
+ USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable);\r
+ /* Empty rxFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ }\r
+\r
+ handle->rxDataSize = 0U;\r
+ handle->rxState = kUSART_RxIdle;\r
+}\r
+\r
+/*!\r
+ * brief Get the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ * param count Receive bytes count.\r
+ * retval kStatus_NoTransferInProgress No receive in progress.\r
+ * retval kStatus_InvalidArgument Parameter is invalid.\r
+ * retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)\r
+{\r
+ assert(NULL != handle);\r
+ assert(NULL != count);\r
+\r
+ if (kUSART_RxIdle == handle->rxState)\r
+ {\r
+ return kStatus_NoTransferInProgress;\r
+ }\r
+\r
+ *count = handle->rxDataSizeAll - handle->rxDataSize;\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+/*!\r
+ * brief USART IRQ handle function.\r
+ *\r
+ * This function handles the USART transmit and receive IRQ request.\r
+ *\r
+ * param base USART peripheral base address.\r
+ * param handle USART handle pointer.\r
+ */\r
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)\r
+{\r
+ /* Check arguments */\r
+ assert((NULL != base) && (NULL != handle));\r
+\r
+ bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer);\r
+ bool sendEnabled = handle->txDataSize;\r
+\r
+ /* If RX overrun. */\r
+ if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK)\r
+ {\r
+ /* Clear rx error state. */\r
+ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;\r
+ /* clear rxFIFO */\r
+ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;\r
+ /* Trigger callback. */\r
+ if (handle->callback)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxError, handle->userData);\r
+ }\r
+ }\r
+ while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) ||\r
+ (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)))\r
+ {\r
+ /* Receive data */\r
+ if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK))\r
+ {\r
+ /* Receive to app bufffer if app buffer is present */\r
+ if (handle->rxDataSize)\r
+ {\r
+ *handle->rxData = base->FIFORD;\r
+ handle->rxDataSize--;\r
+ handle->rxData++;\r
+ receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer));\r
+ if (!handle->rxDataSize)\r
+ {\r
+ if (!handle->rxRingBuffer)\r
+ {\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;\r
+ }\r
+ handle->rxState = kUSART_RxIdle;\r
+ if (handle->callback)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);\r
+ }\r
+ }\r
+ }\r
+ /* Otherwise receive to ring buffer if ring buffer is present */\r
+ else\r
+ {\r
+ if (handle->rxRingBuffer)\r
+ {\r
+ /* If RX ring buffer is full, trigger callback to notify over run. */\r
+ if (USART_TransferIsRxRingBufferFull(handle))\r
+ {\r
+ if (handle->callback)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);\r
+ }\r
+ }\r
+ /* If ring buffer is still full after callback function, the oldest data is overrided. */\r
+ if (USART_TransferIsRxRingBufferFull(handle))\r
+ {\r
+ /* Increase handle->rxRingBufferTail to make room for new data. */\r
+ if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)\r
+ {\r
+ handle->rxRingBufferTail = 0U;\r
+ }\r
+ else\r
+ {\r
+ handle->rxRingBufferTail++;\r
+ }\r
+ }\r
+ /* Read data. */\r
+ handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD;\r
+ /* Increase handle->rxRingBufferHead. */\r
+ if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)\r
+ {\r
+ handle->rxRingBufferHead = 0U;\r
+ }\r
+ else\r
+ {\r
+ handle->rxRingBufferHead++;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ /* Send data */\r
+ if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))\r
+ {\r
+ base->FIFOWR = *handle->txData;\r
+ handle->txDataSize--;\r
+ handle->txData++;\r
+ sendEnabled = handle->txDataSize != 0;\r
+ if (!sendEnabled)\r
+ {\r
+ base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;\r
+ handle->txState = kUSART_TxIdle;\r
+ if (handle->callback)\r
+ {\r
+ handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ /* ring buffer is not used */\r
+ if (NULL == handle->rxRingBuffer)\r
+ {\r
+ /* restore if rx transfer ends and rxLevel is different from default value */\r
+ if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))\r
+ {\r
+ base->FIFOTRIG =\r
+ (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);\r
+ }\r
+ /* decrease level if rx transfer is bellow */\r
+ if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1)))\r
+ {\r
+ base->FIFOTRIG =\r
+ (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1));\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_USART_H_\r
+#define _FSL_USART_H_\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup usart_driver\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @name Driver version */\r
+/*@{*/\r
+/*! @brief USART driver version 2.0.3. */\r
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))\r
+/*@}*/\r
+\r
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)\r
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)\r
+\r
+/*! @brief Error codes for the USART driver. */\r
+enum _usart_status\r
+{\r
+ kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */\r
+ kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */\r
+ kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */\r
+ kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */\r
+ kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */\r
+ kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */\r
+ kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */\r
+ kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */\r
+ kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */\r
+ kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */\r
+ kStatus_USART_BaudrateNotSupport =\r
+ MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */\r
+};\r
+\r
+/*! @brief USART parity mode. */\r
+typedef enum _usart_parity_mode\r
+{\r
+ kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */\r
+ kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */\r
+ kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */\r
+} usart_parity_mode_t;\r
+\r
+/*! @brief USART stop bit count. */\r
+typedef enum _usart_stop_bit_count\r
+{\r
+ kUSART_OneStopBit = 0U, /*!< One stop bit */\r
+ kUSART_TwoStopBit = 1U, /*!< Two stop bits */\r
+} usart_stop_bit_count_t;\r
+\r
+/*! @brief USART data size. */\r
+typedef enum _usart_data_len\r
+{\r
+ kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */\r
+ kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */\r
+} usart_data_len_t;\r
+\r
+/*! @brief txFIFO watermark values */\r
+typedef enum _usart_txfifo_watermark\r
+{\r
+ kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */\r
+ kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */\r
+ kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */\r
+ kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */\r
+ kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */\r
+ kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */\r
+ kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */\r
+ kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */\r
+} usart_txfifo_watermark_t;\r
+\r
+/*! @brief rxFIFO watermark values */\r
+typedef enum _usart_rxfifo_watermark\r
+{\r
+ kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */\r
+ kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */\r
+ kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */\r
+ kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */\r
+ kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */\r
+ kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */\r
+ kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */\r
+ kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */\r
+} usart_rxfifo_watermark_t;\r
+\r
+/*!\r
+ * @brief USART interrupt configuration structure, default settings all disabled.\r
+ */\r
+enum _usart_interrupt_enable\r
+{\r
+ kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),\r
+ kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),\r
+ kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),\r
+ kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),\r
+};\r
+\r
+/*!\r
+ * @brief USART status flags.\r
+ *\r
+ * This provides constants for the USART status flags for use in the USART functions.\r
+ */\r
+enum _usart_flags\r
+{\r
+ kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */\r
+ kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */\r
+ kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */\r
+ kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */\r
+ kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */\r
+ kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */\r
+};\r
+\r
+/*! @brief USART configuration structure. */\r
+typedef struct _usart_config\r
+{\r
+ uint32_t baudRate_Bps; /*!< USART baud rate */\r
+ usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */\r
+ usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */\r
+ usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */\r
+ bool loopback; /*!< Enable peripheral loopback */\r
+ bool enableRx; /*!< Enable RX */\r
+ bool enableTx; /*!< Enable TX */\r
+ usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */\r
+ usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */\r
+} usart_config_t;\r
+\r
+/*! @brief USART transfer structure. */\r
+typedef struct _usart_transfer\r
+{\r
+ uint8_t *data; /*!< The buffer of data to be transfer.*/\r
+ size_t dataSize; /*!< The byte count to be transfer. */\r
+} usart_transfer_t;\r
+\r
+/* Forward declaration of the handle typedef. */\r
+typedef struct _usart_handle usart_handle_t;\r
+\r
+/*! @brief USART transfer callback function. */\r
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);\r
+\r
+/*! @brief USART handle structure. */\r
+struct _usart_handle\r
+{\r
+ uint8_t *volatile txData; /*!< Address of remaining data to send. */\r
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */\r
+ size_t txDataSizeAll; /*!< Size of the data to send out. */\r
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */\r
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */\r
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */\r
+\r
+ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */\r
+ size_t rxRingBufferSize; /*!< Size of the ring buffer. */\r
+ volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */\r
+ volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */\r
+\r
+ usart_transfer_callback_t callback; /*!< Callback function. */\r
+ void *userData; /*!< USART callback function parameter.*/\r
+\r
+ volatile uint8_t txState; /*!< TX transfer state. */\r
+ volatile uint8_t rxState; /*!< RX transfer state */\r
+\r
+ usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */\r
+ usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */\r
+};\r
+\r
+/*******************************************************************************\r
+ * API\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* _cplusplus */\r
+\r
+/*! @brief Returns instance number for USART peripheral base address. */\r
+uint32_t USART_GetInstance(USART_Type *base);\r
+\r
+/*!\r
+ * @name Initialization and deinitialization\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.\r
+ *\r
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration\r
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.\r
+ * Example below shows how to use this API to configure USART.\r
+ * @code\r
+ * usart_config_t usartConfig;\r
+ * usartConfig.baudRate_Bps = 115200U;\r
+ * usartConfig.parityMode = kUSART_ParityDisabled;\r
+ * usartConfig.stopBitCount = kUSART_OneStopBit;\r
+ * USART_Init(USART1, &usartConfig, 20000000U);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param config Pointer to user-defined configuration structure.\r
+ * @param srcClock_Hz USART clock source frequency in HZ.\r
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * @retval kStatus_InvalidArgument USART base address is not valid\r
+ * @retval kStatus_Success Status USART initialize succeed\r
+ */\r
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);\r
+\r
+/*!\r
+ * @brief Deinitializes a USART instance.\r
+ *\r
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ */\r
+void USART_Deinit(USART_Type *base);\r
+\r
+/*!\r
+ * @brief Gets the default configuration structure.\r
+ *\r
+ * This function initializes the USART configuration structure to a default value. The default\r
+ * values are:\r
+ * usartConfig->baudRate_Bps = 115200U;\r
+ * usartConfig->parityMode = kUSART_ParityDisabled;\r
+ * usartConfig->stopBitCount = kUSART_OneStopBit;\r
+ * usartConfig->bitCountPerChar = kUSART_8BitsPerChar;\r
+ * usartConfig->loopback = false;\r
+ * usartConfig->enableTx = false;\r
+ * usartConfig->enableRx = false;\r
+ *\r
+ * @param config Pointer to configuration structure.\r
+ */\r
+void USART_GetDefaultConfig(usart_config_t *config);\r
+\r
+/*!\r
+ * @brief Sets the USART instance baud rate.\r
+ *\r
+ * This function configures the USART module baud rate. This function is used to update\r
+ * the USART module baud rate after the USART module is initialized by the USART_Init.\r
+ * @code\r
+ * USART_SetBaudRate(USART1, 115200U, 20000000U);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param baudrate_Bps USART baudrate to be set.\r
+ * @param srcClock_Hz USART clock source freqency in HZ.\r
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.\r
+ * @retval kStatus_Success Set baudrate succeed.\r
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.\r
+ */\r
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Status\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Get USART status flags.\r
+ *\r
+ * This function get all USART status flags, the flags are returned as the logical\r
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,\r
+ * compare the return value with enumerators in @ref _usart_flags.\r
+ * For example, to check whether the TX is empty:\r
+ * @code\r
+ * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))\r
+ * {\r
+ * ...\r
+ * }\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.\r
+ */\r
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)\r
+{\r
+ return base->FIFOSTAT;\r
+}\r
+\r
+/*!\r
+ * @brief Clear USART status flags.\r
+ *\r
+ * This function clear supported USART status flags\r
+ * Flags that can be cleared or set are:\r
+ * kUSART_TxError\r
+ * kUSART_RxError\r
+ * For example:\r
+ * @code\r
+ * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param mask status flags to be cleared.\r
+ */\r
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)\r
+{\r
+ /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */\r
+ base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);\r
+}\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Interrupts\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Enables USART interrupts according to the provided mask.\r
+ *\r
+ * This function enables the USART interrupts according to the provided mask. The mask\r
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.\r
+ * For example, to enable TX empty interrupt and RX full interrupt:\r
+ * @code\r
+ * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.\r
+ */\r
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)\r
+{\r
+ base->FIFOINTENSET = mask & 0xF;\r
+}\r
+\r
+/*!\r
+ * @brief Disables USART interrupts according to a provided mask.\r
+ *\r
+ * This function disables the USART interrupts according to a provided mask. The mask\r
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.\r
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:\r
+ * @code\r
+ * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);\r
+ * @endcode\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.\r
+ */\r
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)\r
+{\r
+ base->FIFOINTENCLR = mask & 0xF;\r
+}\r
+\r
+/*!\r
+ * @brief Returns enabled USART interrupts.\r
+ *\r
+ * This function returns the enabled USART interrupts.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ */\r
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)\r
+{\r
+ return base->FIFOINTENSET;\r
+}\r
+\r
+/*!\r
+* @brief Enable DMA for Tx\r
+*/\r
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);\r
+ }\r
+}\r
+\r
+/*!\r
+* @brief Enable DMA for Rx\r
+*/\r
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);\r
+ }\r
+}\r
+\r
+/*!\r
+ * @brief Enable CTS.\r
+ * This function will determine whether CTS is used for flow control.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param enable Enable CTS or not, true for enable and false for disable.\r
+ */\r
+static inline void USART_EnableCTS(USART_Type *base, bool enable)\r
+{\r
+ if (enable)\r
+ {\r
+ base->CFG |= USART_CFG_CTSEN_MASK;\r
+ }\r
+ else\r
+ {\r
+ base->CFG &= ~USART_CFG_CTSEN_MASK;\r
+ }\r
+}\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Bus Operations\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Writes to the FIFOWR register.\r
+ *\r
+ * This function writes data to the txFIFO directly. The upper layer must ensure\r
+ * that txFIFO has space for data to write before calling this function.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param data The byte to write.\r
+ */\r
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)\r
+{\r
+ base->FIFOWR = data;\r
+}\r
+\r
+/*!\r
+ * @brief Reads the FIFORD register directly.\r
+ *\r
+ * This function reads data from the rxFIFO directly. The upper layer must\r
+ * ensure that the rxFIFO is not empty before calling this function.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @return The byte read from USART data register.\r
+ */\r
+static inline uint8_t USART_ReadByte(USART_Type *base)\r
+{\r
+ return base->FIFORD;\r
+}\r
+\r
+/*!\r
+ * @brief Writes to the TX register using a blocking method.\r
+ *\r
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO\r
+ * to have room and writes data to the TX buffer.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param data Start address of the data to write.\r
+ * @param length Size of the data to write.\r
+ */\r
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);\r
+\r
+/*!\r
+ * @brief Read RX data register using a blocking method.\r
+ *\r
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to\r
+ * have data and read data from the TX register.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param data Start address of the buffer to store the received data.\r
+ * @param length Size of the buffer.\r
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.\r
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.\r
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.\r
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.\r
+ * @retval kStatus_Success Successfully received all data.\r
+ */\r
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);\r
+\r
+/* @} */\r
+\r
+/*!\r
+ * @name Transactional\r
+ * @{\r
+ */\r
+\r
+/*!\r
+ * @brief Initializes the USART handle.\r
+ *\r
+ * This function initializes the USART handle which can be used for other USART\r
+ * transactional APIs. Usually, for a specified USART instance,\r
+ * call this API once to get the initialized handle.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param callback The callback function.\r
+ * @param userData The parameter of the callback function.\r
+ */\r
+status_t USART_TransferCreateHandle(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_callback_t callback,\r
+ void *userData);\r
+\r
+/*!\r
+ * @brief Transmits a buffer of data using the interrupt method.\r
+ *\r
+ * This function sends data using an interrupt method. This is a non-blocking function, which\r
+ * returns directly without waiting for all data to be written to the TX register. When\r
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback\r
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.\r
+ *\r
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written\r
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,\r
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param xfer USART transfer structure. See #usart_transfer_t.\r
+ * @retval kStatus_Success Successfully start the data transmission.\r
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.\r
+ * @retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);\r
+\r
+/*!\r
+ * @brief Sets up the RX ring buffer.\r
+ *\r
+ * This function sets up the RX ring buffer to a specific USART handle.\r
+ *\r
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the\r
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received\r
+ * in the ring buffer, the user can get the received data from the ring buffer directly.\r
+ *\r
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other\r
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.\r
+ * @param ringBufferSize size of the ring buffer.\r
+ */\r
+void USART_TransferStartRingBuffer(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ uint8_t *ringBuffer,\r
+ size_t ringBufferSize);\r
+\r
+/*!\r
+ * @brief Aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * This function aborts the background transfer and uninstalls the ring buffer.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Get the length of received data in RX ring buffer.\r
+ *\r
+ * @param handle USART handle pointer.\r
+ * @return Length of received data in RX ring buffer.\r
+ */\r
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data transmit.\r
+ *\r
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out\r
+ * how many bytes are still not sent out.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Get the number of bytes that have been written to USART TX register.\r
+ *\r
+ * This function gets the number of bytes that have been written to USART TX\r
+ * register by interrupt method.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param count Send bytes count.\r
+ * @retval kStatus_NoTransferInProgress No send in progress.\r
+ * @retval kStatus_InvalidArgument Parameter is invalid.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief Receives a buffer of data using an interrupt method.\r
+ *\r
+ * This function receives data using an interrupt method. This is a non-blocking function, which\r
+ * returns without waiting for all data to be received.\r
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and\r
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.\r
+ * After copying, if the data in the ring buffer is not enough to read, the receive\r
+ * request is saved by the USART driver. When the new data arrives, the receive request\r
+ * is serviced first. When all data is received, the USART driver notifies the upper layer\r
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.\r
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.\r
+ * The 5 bytes are copied to the xfer->data and this function returns with the\r
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is\r
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.\r
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt\r
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param xfer USART transfer structure, see #usart_transfer_t.\r
+ * @param receivedBytes Bytes received from the ring buffer directly.\r
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.\r
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.\r
+ * @retval kStatus_InvalidArgument Invalid argument.\r
+ */\r
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,\r
+ usart_handle_t *handle,\r
+ usart_transfer_t *xfer,\r
+ size_t *receivedBytes);\r
+\r
+/*!\r
+ * @brief Aborts the interrupt-driven data receiving.\r
+ *\r
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out\r
+ * how many bytes not received yet.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);\r
+\r
+/*!\r
+ * @brief Get the number of bytes that have been received.\r
+ *\r
+ * This function gets the number of bytes that have been received.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ * @param count Receive bytes count.\r
+ * @retval kStatus_NoTransferInProgress No receive in progress.\r
+ * @retval kStatus_InvalidArgument Parameter is invalid.\r
+ * @retval kStatus_Success Get successfully through the parameter \p count;\r
+ */\r
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);\r
+\r
+/*!\r
+ * @brief USART IRQ handle function.\r
+ *\r
+ * This function handles the USART transmit and receive IRQ request.\r
+ *\r
+ * @param base USART peripheral base address.\r
+ * @param handle USART handle pointer.\r
+ */\r
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);\r
+\r
+/* @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*! @}*/\r
+\r
+#endif /* _FSL_USART_H_ */\r
--- /dev/null
+// ****************************************************************************
+// semihost_hardfault.c
+// - Provides hard fault handler to allow semihosting code not
+// to hang application when debugger not connected.
+//
+// ****************************************************************************
+// Copyright 2017-2018 NXP
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any
+// warranties of any kind, and NXP Semiconductors and its licensor disclaim any
+// and all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights. NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under
+// any patent, copyright, mask work right, or any other intellectual property
+// rights in or to any products. NXP Semiconductors reserves the right to make
+// changes in the software without notification. NXP Semiconductors also makes
+// no representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers. This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+// ****************************************************************************
+//
+// ===== DESCRIPTION =====
+//
+// One of the issues with applications that make use of semihosting operations
+// (such as printf calls) is that the code will not execute correctly when the
+// debugger is not connected. Generally this will show up with the application
+// appearing to just hang. This may include the application running from reset
+// or powering up the board (with the application already in FLASH), and also
+// as the application failing to continue to execute after a debug session is
+// terminated.
+//
+// The problem here is that the "bottom layer" of the semihosted variants of
+// the C library, semihosting is implemented by a "BKPT 0xAB" instruction.
+// When the debug tools are not connected, this instruction triggers a hard
+// fault - and the default hard fault handler within an application will
+// typically just contains an infinite loop - causing the application to
+// appear to have hang when no debugger is connected.
+//
+// The below code provides an example hard fault handler which instead looks
+// to see what the instruction that caused the hard fault was - and if it
+// was a "BKPT 0xAB", then it instead returns back to the user application.
+//
+// In most cases this will allow applications containing semihosting
+// operations to execute (to some degree) when the debugger is not connected.
+//
+// == NOTE ==
+//
+// Correct execution of the application containing semihosted operations
+// which are vectored onto this hard fault handler cannot be guaranteed. This
+// is because the handler may not return data or return codes that the higher
+// level C library code or application code expects. This hard fault handler
+// is meant as a development aid, and it is not recommended to leave
+// semihosted code in a production build of your application!
+//
+// ****************************************************************************
+
+// Allow handler to be removed by setting a define (via command line)
+#if !defined (__SEMIHOST_HARDFAULT_DISABLE)
+
+__attribute__((naked))
+void HardFault_Handler(void){
+ __asm( ".syntax unified\n"
+ // Check which stack is in use
+ "MOVS R0, #4 \n"
+ "MOV R1, LR \n"
+ "TST R0, R1 \n"
+ "BEQ _MSP \n"
+ "MRS R0, PSP \n"
+ "B _process \n"
+ "_MSP: \n"
+ "MRS R0, MSP \n"
+ // Load the instruction that triggered hard fault
+ "_process: \n"
+ "LDR R1,[R0,#24] \n"
+ "LDRH R2,[r1] \n"
+ // Semihosting instruction is "BKPT 0xAB" (0xBEAB)
+ "LDR R3,=0xBEAB \n"
+ "CMP R2,R3 \n"
+ "BEQ _semihost_return \n"
+ // Wasn't semihosting instruction so enter infinite loop
+ "B . \n"
+ // Was semihosting instruction, so adjust location to
+ // return to by 1 instruction (2 bytes), then exit function
+ "_semihost_return: \n"
+ "ADDS R1,#2 \n"
+ "STR R1,[R0,#24] \n"
+ // Set a return value from semihosting operation.
+ // 32 is slightly arbitrary, but appears to allow most
+ // C Library IO functions sitting on top of semihosting to
+ // continue to operate to some degree
+ "MOVS R1,#32 \n"
+ "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack
+ // Return from hard fault handler to application
+ "BX LR \n"
+ ".syntax divided\n") ;
+}
+
+#endif
+
--- /dev/null
+//*****************************************************************************\r
+// boot_multicore_slave.c\r
+//\r
+// Provides functions to boot slave core in LPC55xx multicore system\r
+//\r
+// Version : 190215\r
+//\r
+//*****************************************************************************\r
+//\r
+// Copyright(C) NXP Semiconductors, 2019\r
+// All rights reserved.\r
+//\r
+// Software that is described herein is for illustrative purposes only\r
+// which provides customers with programming information regarding the\r
+// LPC products. This software is supplied "AS IS" without any warranties of\r
+// any kind, and NXP Semiconductors and its licensor disclaim any and\r
+// all warranties, express or implied, including all implied warranties of\r
+// merchantability, fitness for a particular purpose and non-infringement of\r
+// intellectual property rights. NXP Semiconductors assumes no responsibility\r
+// or liability for the use of the software, conveys no license or rights under any\r
+// patent, copyright, mask work right, or any other intellectual property rights in\r
+// or to any products. NXP Semiconductors reserves the right to make changes\r
+// in the software without notification. NXP Semiconductors also makes no\r
+// representation or warranty that such application will be suitable for the\r
+// specified use without further testing or modification.\r
+//\r
+// Permission to use, copy, modify, and distribute this software and its\r
+// documentation is hereby granted, under NXP Semiconductors' and its\r
+// licensor's relevant copyrights in the software, without fee, provided that it\r
+// is used in conjunction with NXP Semiconductors microcontrollers. This\r
+// copyright, permission, and disclaimer notice must appear in all copies of\r
+// this code.\r
+//*****************************************************************************\r
+\r
+#if defined (__MULTICORE_MASTER)\r
+\r
+#include <stdint.h>\r
+\r
+// ==================================================================\r
+// Define registers related to multicore CPU Control and setup\r
+// ==================================================================\r
+#define SYSCON_BASE ((uint32_t) 0x50000000)\r
+#define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x800)))\r
+#define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x804)))\r
+#define CPSTACK (((volatile uint32_t *) (SYSCON_BASE + 0x808)))\r
+#define CPSTAT (((volatile uint32_t *) (SYSCON_BASE + 0x80C)))\r
+#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))\r
+#define CORE1_CLK_ENA (1<<3)\r
+#define CORE1_RESET_ENA (1<<5)\r
+\r
+\r
+// ==================================================================\r
+// Function to boot the slave (core 1)\r
+// ==================================================================\r
+void slave_core1_boot(uint32_t *coentry, uint32_t *costackptr) {\r
+\r
+ volatile uint32_t *u32REG, u32Val;\r
+\r
+ // Load the slave's stack pointer value\r
+ *CPSTACK = (uint32_t) costackptr;\r
+ // Load address of the slave code in memory (for slave's VTOR)\r
+ *CPBOOT = (uint32_t) coentry;\r
+\r
+ // Read CPU control register and update to start slave execution\r
+ u32REG = (uint32_t *) CPUCTRL;\r
+ u32Val = *u32REG;\r
+ // Enable slave clock and reset\r
+ u32Val |= (CPUCTRL_KEY | ((CORE1_CLK_ENA | CORE1_RESET_ENA) & 0x7F));\r
+ *u32REG = u32Val;\r
+ // Clear slave reset\r
+ u32Val &= ~CORE1_RESET_ENA;\r
+ *u32REG = u32Val;\r
+ // Slave is now executing\r
+}\r
+\r
+// ==================================================================\r
+// Address of slave code in memory - provided by linker script\r
+extern uint8_t __core_m33slave_START__;\r
+// ==================================================================\r
+\r
+// ==================================================================\r
+// Top level function to boot the slave core\r
+// ==================================================================\r
+void boot_multicore_slave(void) {\r
+\r
+ // Get the address of the slave code in memory\r
+ uint32_t *slavevectortable_ptr = (uint32_t *)&__core_m33slave_START__;\r
+\r
+ // Get initial address for slave's stack pointer\r
+ volatile unsigned int spaddr;\r
+ spaddr = *slavevectortable_ptr;\r
+\r
+ // Boot the slave - passing address of code and stack pointer\r
+ slave_core1_boot(slavevectortable_ptr, (uint32_t *)spaddr);\r
+\r
+}\r
+#endif //defined (__MULTICORE_MASTER)\r
--- /dev/null
+//*****************************************************************************\r
+// boot_multicore_slave.h\r
+//\r
+// Header for functions used for booting of slave core in multicore system\r
+//*****************************************************************************\r
+//\r
+// Copyright(C) NXP Semiconductors, 2019\r
+// All rights reserved.\r
+//\r
+// Software that is described herein is for illustrative purposes only\r
+// which provides customers with programming information regarding the\r
+// LPC products. This software is supplied "AS IS" without any warranties of\r
+// any kind, and NXP Semiconductors and its licensor disclaim any and\r
+// all warranties, express or implied, including all implied warranties of\r
+// merchantability, fitness for a particular purpose and non-infringement of\r
+// intellectual property rights. NXP Semiconductors assumes no responsibility\r
+// or liability for the use of the software, conveys no license or rights under any\r
+// patent, copyright, mask work right, or any other intellectual property rights in\r
+// or to any products. NXP Semiconductors reserves the right to make changes\r
+// in the software without notification. NXP Semiconductors also makes no\r
+// representation or warranty that such application will be suitable for the\r
+// specified use without further testing or modification.\r
+//\r
+// Permission to use, copy, modify, and distribute this software and its\r
+// documentation is hereby granted, under NXP Semiconductors' and its\r
+// licensor's relevant copyrights in the software, without fee, provided that it\r
+// is used in conjunction with NXP Semiconductors microcontrollers. This\r
+// copyright, permission, and disclaimer notice must appear in all copies of\r
+// this code.\r
+//*****************************************************************************\r
+\r
+#ifndef BOOT_MULTICORE_SLAVE_H_\r
+#define BOOT_MULTICORE_SLAVE_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+void boot_multicore_slave(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* BOOT_MULTICORE_SLAVE_H_ */\r
--- /dev/null
+//*****************************************************************************\r
+// LPC55S69_cm33_core0 startup code for use with MCUXpresso IDE\r
+//\r
+// Version : 220119\r
+//*****************************************************************************\r
+//\r
+// Copyright 2016-2019 NXP\r
+// All rights reserved.\r
+//\r
+// SPDX-License-Identifier: BSD-3-Clause\r
+//*****************************************************************************\r
+\r
+#if defined (DEBUG)\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("Og")\r
+#endif // (DEBUG)\r
+\r
+#if defined (__cplusplus)\r
+#ifdef __REDLIB__\r
+#error Redlib does not support C++\r
+#else\r
+//*****************************************************************************\r
+//\r
+// The entry point for the C++ library startup\r
+//\r
+//*****************************************************************************\r
+extern "C" {\r
+ extern void __libc_init_array(void);\r
+}\r
+#endif\r
+#endif\r
+\r
+#define WEAK __attribute__ ((weak))\r
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))\r
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))\r
+\r
+//*****************************************************************************\r
+#if defined (__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+//*****************************************************************************\r
+// Variable to store CRP value in. Will be placed automatically\r
+// by the linker when "Enable Code Read Protect" selected.\r
+// See crp.h header for more information\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+// Declaration of external SystemInit function\r
+//*****************************************************************************\r
+#if defined (__USE_CMSIS)\r
+extern void SystemInit(void);\r
+#endif // (__USE_CMSIS)\r
+\r
+//*****************************************************************************\r
+// Forward declaration of the core exception handlers.\r
+// When the application defines a handler (with the same name), this will\r
+// automatically take precedence over these weak definitions.\r
+// If your application is a C++ one, then any interrupt handlers defined\r
+// in C++ files within in your main application will need to have C linkage\r
+// rather than C++ linkage. To do this, make sure that you are using extern "C"\r
+// { .... } around the interrupt handler within your main application code.\r
+//*****************************************************************************\r
+ void ResetISR(void);\r
+WEAK void NMI_Handler(void);\r
+WEAK void HardFault_Handler(void);\r
+WEAK void MemManage_Handler(void);\r
+WEAK void BusFault_Handler(void);\r
+WEAK void UsageFault_Handler(void);\r
+WEAK void SVC_Handler(void);\r
+WEAK void DebugMon_Handler(void);\r
+WEAK void PendSV_Handler(void);\r
+WEAK void SysTick_Handler(void);\r
+WEAK void IntDefaultHandler(void);\r
+\r
+//*****************************************************************************\r
+// Forward declaration of the application IRQ handlers. When the application\r
+// defines a handler (with the same name), this will automatically take\r
+// precedence over weak definitions below\r
+//*****************************************************************************\r
+WEAK void WDT_BOD_IRQHandler(void);\r
+WEAK void DMA0_IRQHandler(void);\r
+WEAK void GINT0_IRQHandler(void);\r
+WEAK void GINT1_IRQHandler(void);\r
+WEAK void PIN_INT0_IRQHandler(void);\r
+WEAK void PIN_INT1_IRQHandler(void);\r
+WEAK void PIN_INT2_IRQHandler(void);\r
+WEAK void PIN_INT3_IRQHandler(void);\r
+WEAK void UTICK0_IRQHandler(void);\r
+WEAK void MRT0_IRQHandler(void);\r
+WEAK void CTIMER0_IRQHandler(void);\r
+WEAK void CTIMER1_IRQHandler(void);\r
+WEAK void SCT0_IRQHandler(void);\r
+WEAK void CTIMER3_IRQHandler(void);\r
+WEAK void FLEXCOMM0_IRQHandler(void);\r
+WEAK void FLEXCOMM1_IRQHandler(void);\r
+WEAK void FLEXCOMM2_IRQHandler(void);\r
+WEAK void FLEXCOMM3_IRQHandler(void);\r
+WEAK void FLEXCOMM4_IRQHandler(void);\r
+WEAK void FLEXCOMM5_IRQHandler(void);\r
+WEAK void FLEXCOMM6_IRQHandler(void);\r
+WEAK void FLEXCOMM7_IRQHandler(void);\r
+WEAK void ADC0_IRQHandler(void);\r
+WEAK void Reserved39_IRQHandler(void);\r
+WEAK void ACMP_IRQHandler(void);\r
+WEAK void Reserved41_IRQHandler(void);\r
+WEAK void Reserved42_IRQHandler(void);\r
+WEAK void USB0_NEEDCLK_IRQHandler(void);\r
+WEAK void USB0_IRQHandler(void);\r
+WEAK void RTC_IRQHandler(void);\r
+WEAK void Reserved46_IRQHandler(void);\r
+WEAK void MAILBOX_IRQHandler(void);\r
+WEAK void PIN_INT4_IRQHandler(void);\r
+WEAK void PIN_INT5_IRQHandler(void);\r
+WEAK void PIN_INT6_IRQHandler(void);\r
+WEAK void PIN_INT7_IRQHandler(void);\r
+WEAK void CTIMER2_IRQHandler(void);\r
+WEAK void CTIMER4_IRQHandler(void);\r
+WEAK void OS_EVENT_IRQHandler(void);\r
+WEAK void Reserved55_IRQHandler(void);\r
+WEAK void Reserved56_IRQHandler(void);\r
+WEAK void Reserved57_IRQHandler(void);\r
+WEAK void SDIO_IRQHandler(void);\r
+WEAK void Reserved59_IRQHandler(void);\r
+WEAK void Reserved60_IRQHandler(void);\r
+WEAK void Reserved61_IRQHandler(void);\r
+WEAK void USB1_UTMI_IRQHandler(void);\r
+WEAK void USB1_IRQHandler(void);\r
+WEAK void USB1_NEEDCLK_IRQHandler(void);\r
+WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void);\r
+WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void);\r
+WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void);\r
+WEAK void PLU_IRQHandler(void);\r
+WEAK void SEC_VIO_IRQHandler(void);\r
+WEAK void HASHCRYPT_IRQHandler(void);\r
+WEAK void CASER_IRQHandler(void);\r
+WEAK void PUF_IRQHandler(void);\r
+WEAK void PQ_IRQHandler(void);\r
+WEAK void DMA1_IRQHandler(void);\r
+WEAK void LSPI_HS_IRQHandler(void);\r
+\r
+//*****************************************************************************\r
+// Forward declaration of the driver IRQ handlers. These are aliased\r
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver\r
+// defines a handler (with the same name), this will automatically take\r
+// precedence over these weak definitions\r
+//*****************************************************************************\r
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void ACMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void MAILBOX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void OS_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PLU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void SEC_VIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void HASHCRYPT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void CASER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PUF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void PQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+void LSPI_HS_DriverIRQHandler(void) ALIAS(IntDefaultHandler);\r
+\r
+//*****************************************************************************\r
+// The entry point for the application.\r
+// __main() is the entry point for Redlib based applications\r
+// main() is the entry point for Newlib based applications\r
+//*****************************************************************************\r
+#if defined (__REDLIB__)\r
+extern void __main(void);\r
+#endif\r
+extern int main(void);\r
+\r
+//*****************************************************************************\r
+// External declaration for the pointer to the stack top from the Linker Script\r
+//*****************************************************************************\r
+extern void _vStackTop(void);\r
+//*****************************************************************************\r
+// External declaration for LPC MCU vector table checksum from Linker Script\r
+//*****************************************************************************\r
+WEAK extern void __valid_user_code_checksum();\r
+\r
+//*****************************************************************************\r
+//*****************************************************************************\r
+#if defined (__cplusplus)\r
+} // extern "C"\r
+#endif\r
+//*****************************************************************************\r
+// The vector table.\r
+// This relies on the linker script to place at correct location in memory.\r
+//*****************************************************************************\r
+extern void (* const g_pfnVectors[])(void);\r
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));\r
+\r
+__attribute__ ((used, section(".isr_vector")))\r
+void (* const g_pfnVectors[])(void) = {\r
+ // Core Level - CM33\r
+ &_vStackTop, // The initial stack pointer\r
+ ResetISR, // The reset handler\r
+ NMI_Handler, // The NMI handler\r
+ HardFault_Handler, // The hard fault handler\r
+ MemManage_Handler, // The MPU fault handler\r
+ BusFault_Handler, // The bus fault handler\r
+ UsageFault_Handler, // The usage fault handler\r
+ __valid_user_code_checksum, // LPC MCU checksum\r
+ 0, // ECRP\r
+ 0, // Reserved\r
+ 0, // Reserved\r
+ SVC_Handler, // SVCall handler\r
+ DebugMon_Handler, // Debug monitor handler\r
+ 0, // Reserved\r
+ PendSV_Handler, // The PendSV handler\r
+ SysTick_Handler, // The SysTick handler\r
+\r
+ // Chip Level - LPC55S69_cm33_core0\r
+ WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect, Flash interrupt\r
+ DMA0_IRQHandler, // 17: DMA0 controller\r
+ GINT0_IRQHandler, // 18: GPIO group 0\r
+ GINT1_IRQHandler, // 19: GPIO group 1\r
+ PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0\r
+ PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1\r
+ PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2\r
+ PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3\r
+ UTICK0_IRQHandler, // 24: Micro-tick Timer\r
+ MRT0_IRQHandler, // 25: Multi-rate timer\r
+ CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0\r
+ CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1\r
+ SCT0_IRQHandler, // 28: SCTimer/PWM\r
+ CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3\r
+ FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM)\r
+ ADC0_IRQHandler, // 38: ADC0\r
+ Reserved39_IRQHandler, // 39: Reserved interrupt\r
+ ACMP_IRQHandler, // 40: ACMP interrupts\r
+ Reserved41_IRQHandler, // 41: Reserved interrupt\r
+ Reserved42_IRQHandler, // 42: Reserved interrupt\r
+ USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt\r
+ USB0_IRQHandler, // 44: USB device\r
+ RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts\r
+ Reserved46_IRQHandler, // 46: Reserved interrupt\r
+ MAILBOX_IRQHandler, // 47: WAKEUP,Mailbox interrupt (present on selected devices)\r
+ PIN_INT4_IRQHandler, // 48: Pin interrupt 4 or pattern match engine slice 4 int\r
+ PIN_INT5_IRQHandler, // 49: Pin interrupt 5 or pattern match engine slice 5 int\r
+ PIN_INT6_IRQHandler, // 50: Pin interrupt 6 or pattern match engine slice 6 int\r
+ PIN_INT7_IRQHandler, // 51: Pin interrupt 7 or pattern match engine slice 7 int\r
+ CTIMER2_IRQHandler, // 52: Standard counter/timer CTIMER2\r
+ CTIMER4_IRQHandler, // 53: Standard counter/timer CTIMER4\r
+ OS_EVENT_IRQHandler, // 54: OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts\r
+ Reserved55_IRQHandler, // 55: Reserved interrupt\r
+ Reserved56_IRQHandler, // 56: Reserved interrupt\r
+ Reserved57_IRQHandler, // 57: Reserved interrupt\r
+ SDIO_IRQHandler, // 58: SD/MMC\r
+ Reserved59_IRQHandler, // 59: Reserved interrupt\r
+ Reserved60_IRQHandler, // 60: Reserved interrupt\r
+ Reserved61_IRQHandler, // 61: Reserved interrupt\r
+ USB1_UTMI_IRQHandler, // 62: USB1_UTMI\r
+ USB1_IRQHandler, // 63: USB1 interrupt\r
+ USB1_NEEDCLK_IRQHandler, // 64: USB1 activity\r
+ SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt\r
+ SEC_GPIO_INT0_IRQ0_IRQHandler, // 66: SEC_GPIO_INT0_IRQ0 interrupt\r
+ SEC_GPIO_INT0_IRQ1_IRQHandler, // 67: SEC_GPIO_INT0_IRQ1 interrupt\r
+ PLU_IRQHandler, // 68: PLU interrupt\r
+ SEC_VIO_IRQHandler, // 69: SEC_VIO interrupt\r
+ HASHCRYPT_IRQHandler, // 70: HASHCRYPT interrupt\r
+ CASER_IRQHandler, // 71: CASPER interrupt\r
+ PUF_IRQHandler, // 72: PUF interrupt\r
+ PQ_IRQHandler, // 73: PQ interrupt\r
+ DMA1_IRQHandler, // 74: DMA1 interrupt\r
+ LSPI_HS_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM)\r
+\r
+}; /* End of g_pfnVectors */\r
+\r
+//*****************************************************************************\r
+// Functions to carry out the initialization of RW and BSS data sections. These\r
+// are written as separate functions rather than being inlined within the\r
+// ResetISR() function in order to cope with MCUs with multiple banks of\r
+// memory.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors.init_data")))\r
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {\r
+ unsigned int *pulDest = (unsigned int*) start;\r
+ unsigned int *pulSrc = (unsigned int*) romstart;\r
+ unsigned int loop;\r
+ for (loop = 0; loop < len; loop = loop + 4)\r
+ *pulDest++ = *pulSrc++;\r
+}\r
+\r
+__attribute__ ((section(".after_vectors.init_bss")))\r
+void bss_init(unsigned int start, unsigned int len) {\r
+ unsigned int *pulDest = (unsigned int*) start;\r
+ unsigned int loop;\r
+ for (loop = 0; loop < len; loop = loop + 4)\r
+ *pulDest++ = 0;\r
+}\r
+\r
+//*****************************************************************************\r
+// The following symbols are constructs generated by the linker, indicating\r
+// the location of various points in the "Global Section Table". This table is\r
+// created by the linker via the Code Red managed linker script mechanism. It\r
+// contains the load address, execution address and length of each RW data\r
+// section and the execution and length of each BSS (zero initialized) section.\r
+//*****************************************************************************\r
+extern unsigned int __data_section_table;\r
+extern unsigned int __data_section_table_end;\r
+extern unsigned int __bss_section_table;\r
+extern unsigned int __bss_section_table_end;\r
+\r
+//*****************************************************************************\r
+// Reset entry point for your code.\r
+// Sets up a simple runtime environment and initializes the C/C++\r
+// library.\r
+//*****************************************************************************\r
+__attribute__ ((section(".after_vectors.reset")))\r
+void ResetISR(void) {\r
+\r
+ // Disable interrupts\r
+ __asm volatile ("cpsid i");\r
+\r
+#if defined (__USE_CMSIS)\r
+// If __USE_CMSIS defined, then call CMSIS SystemInit code\r
+ SystemInit();\r
+\r
+#endif // (__USE_CMSIS)\r
+\r
+ //\r
+ // Copy the data sections from flash to SRAM.\r
+ //\r
+ unsigned int LoadAddr, ExeAddr, SectionLen;\r
+ unsigned int *SectionTableAddr;\r
+\r
+ // Load base address of Global Section Table\r
+ SectionTableAddr = &__data_section_table;\r
+\r
+ // Copy the data sections from flash to SRAM.\r
+ while (SectionTableAddr < &__data_section_table_end) {\r
+ LoadAddr = *SectionTableAddr++;\r
+ ExeAddr = *SectionTableAddr++;\r
+ SectionLen = *SectionTableAddr++;\r
+ data_init(LoadAddr, ExeAddr, SectionLen);\r
+ }\r
+\r
+ // At this point, SectionTableAddr = &__bss_section_table;\r
+ // Zero fill the bss segment\r
+ while (SectionTableAddr < &__bss_section_table_end) {\r
+ ExeAddr = *SectionTableAddr++;\r
+ SectionLen = *SectionTableAddr++;\r
+ bss_init(ExeAddr, SectionLen);\r
+ }\r
+\r
+\r
+#if !defined (__USE_CMSIS)\r
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code\r
+// will setup the VTOR register\r
+\r
+ // Check to see if we are running the code from a non-zero\r
+ // address (eg RAM, external flash), in which case we need\r
+ // to modify the VTOR register to tell the CPU that the\r
+ // vector table is located at a non-0x0 address.\r
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;\r
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {\r
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;\r
+ }\r
+#endif // (__USE_CMSIS)\r
+#if defined (__cplusplus)\r
+ //\r
+ // Call C++ library initialisation\r
+ //\r
+ __libc_init_array();\r
+#endif\r
+\r
+ // Reenable interrupts\r
+ __asm volatile ("cpsie i");\r
+\r
+#if defined (__REDLIB__)\r
+ // Call the Redlib library, which in turn calls main()\r
+ __main();\r
+#else\r
+ main();\r
+#endif\r
+\r
+ //\r
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop\r
+ //\r
+ while (1) {\r
+ ;\r
+ }\r
+}\r
+\r
+//*****************************************************************************\r
+// Default core exception handlers. Override the ones here by defining your own\r
+// handler routines in your application code.\r
+//*****************************************************************************\r
+WEAK_AV void NMI_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void HardFault_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void MemManage_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void BusFault_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void UsageFault_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void SVC_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void DebugMon_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void PendSV_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+WEAK_AV void SysTick_Handler(void)\r
+{ while(1) {}\r
+}\r
+\r
+//*****************************************************************************\r
+// Processor ends up here if an unexpected interrupt occurs or a specific\r
+// handler is not present in the application code.\r
+//*****************************************************************************\r
+WEAK_AV void IntDefaultHandler(void)\r
+{ while(1) {}\r
+}\r
+\r
+//*****************************************************************************\r
+// Default application exception handlers. Override the ones here by defining\r
+// your own handler routines in your application code. These routines call\r
+// driver exception handlers or IntDefaultHandler() if no driver exception\r
+// handler is included.\r
+//*****************************************************************************\r
+WEAK void WDT_BOD_IRQHandler(void)\r
+{ WDT_BOD_DriverIRQHandler();\r
+}\r
+\r
+WEAK void DMA0_IRQHandler(void)\r
+{ DMA0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void GINT0_IRQHandler(void)\r
+{ GINT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void GINT1_IRQHandler(void)\r
+{ GINT1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT0_IRQHandler(void)\r
+{ PIN_INT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT1_IRQHandler(void)\r
+{ PIN_INT1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT2_IRQHandler(void)\r
+{ PIN_INT2_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT3_IRQHandler(void)\r
+{ PIN_INT3_DriverIRQHandler();\r
+}\r
+\r
+WEAK void UTICK0_IRQHandler(void)\r
+{ UTICK0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void MRT0_IRQHandler(void)\r
+{ MRT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER0_IRQHandler(void)\r
+{ CTIMER0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER1_IRQHandler(void)\r
+{ CTIMER1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SCT0_IRQHandler(void)\r
+{ SCT0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER3_IRQHandler(void)\r
+{ CTIMER3_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM0_IRQHandler(void)\r
+{ FLEXCOMM0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM1_IRQHandler(void)\r
+{ FLEXCOMM1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM2_IRQHandler(void)\r
+{ FLEXCOMM2_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM3_IRQHandler(void)\r
+{ FLEXCOMM3_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM4_IRQHandler(void)\r
+{ FLEXCOMM4_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM5_IRQHandler(void)\r
+{ FLEXCOMM5_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM6_IRQHandler(void)\r
+{ FLEXCOMM6_DriverIRQHandler();\r
+}\r
+\r
+WEAK void FLEXCOMM7_IRQHandler(void)\r
+{ FLEXCOMM7_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ADC0_IRQHandler(void)\r
+{ ADC0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved39_IRQHandler(void)\r
+{ Reserved39_DriverIRQHandler();\r
+}\r
+\r
+WEAK void ACMP_IRQHandler(void)\r
+{ ACMP_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved41_IRQHandler(void)\r
+{ Reserved41_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved42_IRQHandler(void)\r
+{ Reserved42_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB0_NEEDCLK_IRQHandler(void)\r
+{ USB0_NEEDCLK_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB0_IRQHandler(void)\r
+{ USB0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void RTC_IRQHandler(void)\r
+{ RTC_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved46_IRQHandler(void)\r
+{ Reserved46_DriverIRQHandler();\r
+}\r
+\r
+WEAK void MAILBOX_IRQHandler(void)\r
+{ MAILBOX_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT4_IRQHandler(void)\r
+{ PIN_INT4_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT5_IRQHandler(void)\r
+{ PIN_INT5_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT6_IRQHandler(void)\r
+{ PIN_INT6_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PIN_INT7_IRQHandler(void)\r
+{ PIN_INT7_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER2_IRQHandler(void)\r
+{ CTIMER2_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CTIMER4_IRQHandler(void)\r
+{ CTIMER4_DriverIRQHandler();\r
+}\r
+\r
+WEAK void OS_EVENT_IRQHandler(void)\r
+{ OS_EVENT_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved55_IRQHandler(void)\r
+{ Reserved55_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved56_IRQHandler(void)\r
+{ Reserved56_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved57_IRQHandler(void)\r
+{ Reserved57_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SDIO_IRQHandler(void)\r
+{ SDIO_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved59_IRQHandler(void)\r
+{ Reserved59_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved60_IRQHandler(void)\r
+{ Reserved60_DriverIRQHandler();\r
+}\r
+\r
+WEAK void Reserved61_IRQHandler(void)\r
+{ Reserved61_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB1_UTMI_IRQHandler(void)\r
+{ USB1_UTMI_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB1_IRQHandler(void)\r
+{ USB1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void USB1_NEEDCLK_IRQHandler(void)\r
+{ USB1_NEEDCLK_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void)\r
+{ SEC_HYPERVISOR_CALL_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SEC_GPIO_INT0_IRQ0_IRQHandler(void)\r
+{ SEC_GPIO_INT0_IRQ0_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SEC_GPIO_INT0_IRQ1_IRQHandler(void)\r
+{ SEC_GPIO_INT0_IRQ1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PLU_IRQHandler(void)\r
+{ PLU_DriverIRQHandler();\r
+}\r
+\r
+WEAK void SEC_VIO_IRQHandler(void)\r
+{ SEC_VIO_DriverIRQHandler();\r
+}\r
+\r
+WEAK void HASHCRYPT_IRQHandler(void)\r
+{ HASHCRYPT_DriverIRQHandler();\r
+}\r
+\r
+WEAK void CASER_IRQHandler(void)\r
+{ CASER_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PUF_IRQHandler(void)\r
+{ PUF_DriverIRQHandler();\r
+}\r
+\r
+WEAK void PQ_IRQHandler(void)\r
+{ PQ_DriverIRQHandler();\r
+}\r
+\r
+WEAK void DMA1_IRQHandler(void)\r
+{ DMA1_DriverIRQHandler();\r
+}\r
+\r
+WEAK void LSPI_HS_IRQHandler(void)\r
+{ LSPI_HS_DriverIRQHandler();\r
+}\r
+\r
+//*****************************************************************************\r
+\r
+#if defined (DEBUG)\r
+#pragma GCC pop_options\r
+#endif // (DEBUG)\r
--- /dev/null
+/*\r
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.\r
+* Copyright 2016-2017 NXP\r
+* All rights reserved.\r
+*\r
+*\r
+* SPDX-License-Identifier: BSD-3-Clause\r
+*/\r
+\r
+#include "fsl_common.h"\r
+#include "fsl_debug_console.h"\r
+\r
+#ifndef NDEBUG\r
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))\r
+void __aeabi_assert(const char *failedExpr, const char *file, int line)\r
+{\r
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);\r
+ for (;;)\r
+ {\r
+ __BKPT(0);\r
+ }\r
+}\r
+#elif(defined(__GNUC__))\r
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)\r
+{\r
+ PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);\r
+ for (;;)\r
+ {\r
+ __BKPT(0);\r
+ }\r
+}\r
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */\r
+#endif /* NDEBUG */\r
--- /dev/null
+/*\r
+ * This is a modified version of the file printf.c, which was distributed\r
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize\r
+ * the M5407C3 evaluation board.\r
+ *\r
+ * Copyright:\r
+ * 1999-2000 MOTOROLA, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Motorola, Inc. This\r
+ * software is provided on an "AS IS" basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, MOTOROLA\r
+ * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING\r
+ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR\r
+ * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE\r
+ * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY\r
+ * ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING\r
+ * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS\r
+ * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY\r
+ * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Motorola assumes no responsibility for the maintenance and support\r
+ * of this software\r
+\r
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include <stdarg.h>\r
+#include <stdlib.h>\r
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+#include <stdio.h>\r
+#endif\r
+\r
+#ifdef FSL_RTOS_FREE_RTOS\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "semphr.h"\r
+#endif\r
+\r
+#include "fsl_debug_console_conf.h"\r
+#include "fsl_str.h"\r
+\r
+#include "fsl_common.h"\r
+#include "serial_manager.h"\r
+\r
+#include "fsl_debug_console.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#ifndef NDEBUG\r
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))\r
+#undef assert\r
+#define assert(n)\r
+#endif\r
+#endif\r
+\r
+/*! @brief character backspace ASCII value */\r
+#define DEBUG_CONSOLE_BACKSPACE 127\r
+\r
+/* lock definition */\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)\r
+\r
+static SemaphoreHandle_t s_debugConsoleReadSemaphore;\r
+static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;\r
+\r
+#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_BM)\r
+\r
+static volatile uint8_t s_debugConsoleReadWaitSemaphore;\r
+\r
+#else\r
+\r
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */\r
+\r
+/*! @brief get current runing environment is ISR or not */\r
+#ifdef __CA7_REV\r
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()\r
+#else\r
+#define IS_RUNNING_IN_ISR() __get_IPSR()\r
+#endif /* __CA7_REV */\r
+\r
+/* semaphore definition */\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)\r
+\r
+/* mutex semaphore */\r
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) (mutex = xSemaphoreCreateMutex())\r
+\r
+/* clang-format off */\r
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \\r
+{ \\r
+ if (IS_RUNNING_IN_ISR() == 0U) \\r
+ { \\r
+ xSemaphoreGive(mutex); \\r
+ } \\r
+}\r
+\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \\r
+{ \\r
+ if (IS_RUNNING_IN_ISR() == 0U) \\r
+ { \\r
+ xSemaphoreTake(mutex, portMAX_DELAY); \\r
+ } \\r
+}\r
+\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \\r
+{ \\r
+ if (IS_RUNNING_IN_ISR() == 0U) \\r
+ { \\r
+ result = xSemaphoreTake(mutex, 0U); \\r
+ } \\r
+ else \\r
+ { \\r
+ result = 1U; \\r
+ } \\r
+}\r
+/* clang-format on */\r
+\r
+/* Binary semaphore */\r
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) (binary = xSemaphoreCreateBinary())\r
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (xSemaphoreTake(binary, portMAX_DELAY))\r
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (xSemaphoreGiveFromISR(binary, NULL))\r
+\r
+#elif(DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)\r
+\r
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)\r
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)\r
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)\r
+\r
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \\r
+ { \\r
+ while (!binary) \\r
+ { \\r
+ } \\r
+ binary = false; \\r
+ }\r
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)\r
+#else\r
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)\r
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+\r
+/* add other implementation here\r
+*such as :\r
+* #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx)\r
+*/\r
+\r
+#else\r
+\r
+#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE.\r
+\r
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/* receive state structure */\r
+typedef struct _debug_console_write_ring_buffer\r
+{\r
+ uint32_t ringBufferSize;\r
+ volatile uint32_t ringHead;\r
+ volatile uint32_t ringTail;\r
+ uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN];\r
+} debug_console_write_ring_buffer_t;\r
+#endif\r
+\r
+typedef struct _debug_console_state_struct\r
+{\r
+ uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE];\r
+ serial_handle_t serialHandle; /*!< serial manager handle */\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+ debug_console_write_ring_buffer_t writeRingBuffer;\r
+ uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN];\r
+#endif\r
+ uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE];\r
+ uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE];\r
+} debug_console_state_struct_t;\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+\r
+/*! @brief Debug console state information. */\r
+static debug_console_state_struct_t s_debugConsoleState;\r
+serial_handle_t g_serialHandle; /*!< serial manager handle */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*!\r
+ * @brief This is a printf call back function which is used to relocate the log to buffer\r
+ * or print the log immediately when the local buffer is full.\r
+ *\r
+ * @param[in] buf Buffer to store log.\r
+ * @param[in] indicator Buffer index.\r
+ * @param[in] val Target character to store.\r
+ * @param[in] len length of the character\r
+ *\r
+ */\r
+#if SDK_DEBUGCONSOLE\r
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char val, int len);\r
+#endif\r
+\r
+int DbgConsole_SendData(uint8_t *ch, size_t size);\r
+\r
+/*******************************************************************************\r
+ * Code\r
+ ******************************************************************************/\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+\r
+static void DbgConsole_SerialManagerTxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ debug_console_state_struct_t *ioState;\r
+ uint32_t sendDataLength;\r
+\r
+ if ((NULL == callbackParam) || (NULL == message))\r
+ {\r
+ return;\r
+ }\r
+\r
+ ioState = (debug_console_state_struct_t *)callbackParam;\r
+\r
+ ioState->writeRingBuffer.ringTail += message->length;\r
+ if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize)\r
+ {\r
+ ioState->writeRingBuffer.ringTail = 0U;\r
+ }\r
+\r
+ if (kStatus_SerialManager_Success == status)\r
+ {\r
+ if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead)\r
+ {\r
+ if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail)\r
+ {\r
+ sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail;\r
+ }\r
+\r
+ SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]),\r
+ &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail],\r
+ sendDataLength);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ }\r
+}\r
+\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+\r
+static void DbgConsole_SerialManagerRxCallback(void *callbackParam,\r
+ serial_manager_callback_message_t *message,\r
+ serial_manager_status_t status)\r
+{\r
+ if ((NULL == callbackParam) || (NULL == message))\r
+ {\r
+ return;\r
+ }\r
+\r
+ if (kStatus_SerialManager_Notify == status)\r
+ {\r
+ }\r
+ else if (kStatus_SerialManager_Success == status)\r
+ {\r
+ /* release s_debugConsoleReadWaitSemaphore from RX callback */\r
+ DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore);\r
+ }\r
+ else\r
+ {\r
+ }\r
+}\r
+#endif\r
+\r
+#endif\r
+\r
+status_t DbgConsole_ReadOneCharacter(uint8_t *ch)\r
+{\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \\r
+ (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)\r
+ return kStatus_Fail;\r
+#else\r
+ status_t status = kStatus_SerialManager_Error;\r
+\r
+/* recieve one char every time */\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ status =\r
+ SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);\r
+#else\r
+ status = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1);\r
+#endif\r
+ if (kStatus_SerialManager_Success != status)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+ /* wait s_debugConsoleReadWaitSemaphore from RX callback */\r
+ DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore);\r
+\r
+ return kStatus_Success;\r
+#endif\r
+\r
+#else\r
+\r
+ return kStatus_Fail;\r
+\r
+#endif\r
+}\r
+\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)\r
+{\r
+ /* Due to scanf take \n and \r as end of string,should not echo */\r
+ if (((*ch != '\r') && (*ch != '\n')) || (isGetChar))\r
+ {\r
+ /* recieve one char every time */\r
+ if (1 != DbgConsole_SendData(ch, 1U))\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+ }\r
+\r
+ if ((!isGetChar) && (index))\r
+ {\r
+ if (DEBUG_CONSOLE_BACKSPACE == *ch)\r
+ {\r
+ if ((*index >= 2))\r
+ {\r
+ *index -= 2;\r
+ }\r
+ else\r
+ {\r
+ *index = 0;\r
+ }\r
+ }\r
+ }\r
+\r
+ return kStatus_Success;\r
+}\r
+#endif\r
+\r
+int DbgConsole_SendData(uint8_t *ch, size_t size)\r
+{\r
+ status_t status = kStatus_SerialManager_Error;\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ uint32_t sendDataLength;\r
+ int txBusy = 0;\r
+#endif\r
+ assert(NULL != ch);\r
+ assert(0 != size);\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ uint32_t regPrimask = DisableGlobalIRQ();\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ txBusy = 1;\r
+ sendDataLength =\r
+ (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize -\r
+ s_debugConsoleState.writeRingBuffer.ringTail) %\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength = 0U;\r
+ }\r
+ sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength;\r
+ if (sendDataLength <= size)\r
+ {\r
+ EnableGlobalIRQ(regPrimask);\r
+ return -1;\r
+ }\r
+ for (int i = 0; i < size; i++)\r
+ {\r
+ s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i];\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize)\r
+ {\r
+ s_debugConsoleState.writeRingBuffer.ringHead = 0U;\r
+ }\r
+ }\r
+\r
+ status = kStatus_SerialManager_Success;\r
+\r
+ if (!txBusy)\r
+ {\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ sendDataLength =\r
+ s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail;\r
+ }\r
+ else\r
+ {\r
+ sendDataLength =\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail;\r
+ }\r
+\r
+ status = (status_t)SerialManager_WriteNonBlocking(\r
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),\r
+ &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail],\r
+ sendDataLength);\r
+ }\r
+ EnableGlobalIRQ(regPrimask);\r
+#else\r
+ status = (status_t)SerialManager_WriteBlocking(\r
+ ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size);\r
+#endif\r
+ return ((kStatus_Success == status) ? (int)size : -1);\r
+}\r
+\r
+int DbgConsole_ReadLine(uint8_t *buf, size_t size)\r
+{\r
+ int i;\r
+\r
+ assert(buf != NULL);\r
+\r
+ /* take mutex lock function */\r
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);\r
+\r
+ for (i = 0; i < size; i++)\r
+ {\r
+ /* recieve one char every time */\r
+ if (kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))\r
+ {\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+ return -1;\r
+ }\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+ DbgConsole_EchoCharacter(&buf[i], false, &i);\r
+#endif\r
+ /* analysis data */\r
+ if (('\r' == buf[i]) || ('\n' == buf[i]))\r
+ {\r
+ /* End of Line. */\r
+ if (0 == i)\r
+ {\r
+ buf[i] = '\0';\r
+ i = -1;\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+\r
+ return i + 1;\r
+}\r
+\r
+int DbgConsole_ReadCharacter(uint8_t *ch)\r
+{\r
+ int ret;\r
+\r
+ assert(ch);\r
+\r
+ /* take mutex lock function */\r
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);\r
+ /* read one character */\r
+ if (kStatus_Success == DbgConsole_ReadOneCharacter(ch))\r
+ {\r
+ ret = 1;\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+ DbgConsole_EchoCharacter(ch, true, NULL);\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ ret = -1;\r
+ }\r
+\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+\r
+ return ret;\r
+}\r
+\r
+#if SDK_DEBUGCONSOLE\r
+static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char val, int len)\r
+{\r
+ int i = 0;\r
+\r
+ for (i = 0; i < len; i++)\r
+ {\r
+ if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)\r
+ {\r
+ DbgConsole_SendData((uint8_t *)buf, *indicator);\r
+ *indicator = 0U;\r
+ }\r
+\r
+ buf[*indicator] = val;\r
+ (*indicator)++;\r
+ }\r
+}\r
+#endif\r
+\r
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq)\r
+{\r
+ serial_manager_config_t serialConfig;\r
+ status_t status = kStatus_SerialManager_Error;\r
+\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ serial_port_uart_config_t uartConfig = {\r
+ .instance = instance,\r
+ .clockRate = clkSrcFreq,\r
+ .baudRate = baudRate,\r
+ .parityMode = kSerialManager_UartParityDisabled,\r
+ .stopBitCount = kSerialManager_UartOneStopBit,\r
+ .enableRx = 1,\r
+ .enableTx = 1,\r
+ };\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ serial_port_usb_cdc_config_t usbCdcConfig = {\r
+ .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance,\r
+ };\r
+#endif\r
+\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ serial_port_swo_config_t swoConfig = {\r
+ .clockRate = clkSrcFreq, .baudRate = baudRate, .port = instance, .protocol = kSerialManager_SwoProtocolNrz,\r
+ };\r
+#endif\r
+\r
+ serialConfig.type = device;\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0];\r
+ serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN;\r
+#endif\r
+\r
+ if (kSerialPort_Uart == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))\r
+ serialConfig.portConfig = &uartConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else if (kSerialPort_UsbCdc == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))\r
+ serialConfig.portConfig = &usbCdcConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else if (kSerialPort_Swo == device)\r
+ {\r
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))\r
+ serialConfig.portConfig = &swoConfig;\r
+#else\r
+ return status;\r
+#endif\r
+ }\r
+ else\r
+ {\r
+ return status;\r
+ }\r
+\r
+ memset(&s_debugConsoleState, 0U, sizeof(s_debugConsoleState));\r
+\r
+ s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0];\r
+ g_serialHandle = s_debugConsoleState.serialHandle;\r
+ status = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig);\r
+\r
+ assert(kStatus_SerialManager_Success == status);\r
+\r
+ DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+ DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);\r
+\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN;\r
+#endif\r
+\r
+ {\r
+ status = SerialManager_OpenWriteHandle(\r
+ s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));\r
+ assert(kStatus_SerialManager_Success == status);\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]),\r
+ DbgConsole_SerialManagerTxCallback, &s_debugConsoleState);\r
+#endif\r
+ }\r
+\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ {\r
+ status = SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle,\r
+ ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));\r
+ assert(kStatus_SerialManager_Success == status);\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+ SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]),\r
+ DbgConsole_SerialManagerRxCallback, &s_debugConsoleState);\r
+#endif\r
+ }\r
+#endif\r
+ return kStatus_Success;\r
+}\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+status_t DbgConsole_Deinit(void)\r
+{\r
+ {\r
+ SerialManager_CloseWriteHandle(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]));\r
+ }\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ {\r
+ SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]));\r
+ }\r
+#endif\r
+\r
+ return kStatus_Success;\r
+}\r
+\r
+status_t DbgConsole_Flush(void)\r
+{\r
+#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)\r
+\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)\r
+\r
+ if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+\r
+#else\r
+\r
+ while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail)\r
+ {\r
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)\r
+ if (IS_RUNNING_IN_ISR() == 0U)\r
+ {\r
+ vTaskDelay(1);\r
+ }\r
+ else\r
+ {\r
+ return kStatus_Fail;\r
+ }\r
+#endif\r
+ }\r
+\r
+#endif\r
+\r
+#endif\r
+ return kStatus_Success;\r
+}\r
+\r
+#if SDK_DEBUGCONSOLE\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Printf(const char *formatString, ...)\r
+{\r
+ va_list ap;\r
+ int logLength = 0U, result = 0U;\r
+ char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U};\r
+\r
+ if (NULL == g_serialHandle)\r
+ {\r
+ return 0;\r
+ }\r
+\r
+ va_start(ap, formatString);\r
+ /* format print log first */\r
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);\r
+ /* print log */\r
+ result = DbgConsole_SendData((uint8_t *)printBuf, logLength);\r
+\r
+ va_end(ap);\r
+\r
+ return result;\r
+}\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Putchar(int ch)\r
+{\r
+ /* print char */\r
+ return DbgConsole_SendData((uint8_t *)&ch, 1U);\r
+}\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Scanf(char *formatString, ...)\r
+{\r
+ va_list ap;\r
+ int result;\r
+ char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U};\r
+\r
+ /* scanf log */\r
+ DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);\r
+ /* get va_list */\r
+ va_start(ap, formatString);\r
+ /* format scanf log */\r
+ result = StrFormatScanf(scanfBuf, formatString, ap);\r
+\r
+ va_end(ap);\r
+\r
+ return result;\r
+}\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+status_t DbgConsole_TryGetchar(char *ch)\r
+{\r
+#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))\r
+ uint32_t length = 0;\r
+ status_t status = kStatus_Fail;\r
+\r
+ assert(ch);\r
+\r
+ /* take mutex lock function */\r
+ DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);\r
+\r
+ if (kStatus_SerialManager_Success ==\r
+ SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,\r
+ &length))\r
+ {\r
+ if (length)\r
+ {\r
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION\r
+ DbgConsole_EchoCharacter(ch, true, NULL);\r
+#endif\r
+ status = kStatus_Success;\r
+ }\r
+ }\r
+ /* release mutex lock function */\r
+ DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);\r
+ return status;\r
+#else\r
+ return kStatus_Fail;\r
+#endif\r
+}\r
+#endif\r
+\r
+/* See fsl_debug_console.h for documentation of this function. */\r
+int DbgConsole_Getchar(void)\r
+{\r
+ uint8_t ch = 0U;\r
+\r
+ /* Get char */\r
+ DbgConsole_ReadCharacter(&ch);\r
+\r
+ return (int)ch;\r
+}\r
+\r
+#endif /* SDK_DEBUGCONSOLE */\r
+\r
+/*************Code to support toolchain's printf, scanf *******************************/\r
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/\r
+#if (defined(__ICCARM__))\r
+#if defined(SDK_DEBUGCONSOLE_UART)\r
+#pragma weak __write\r
+size_t __write(int handle, const unsigned char *buffer, size_t size)\r
+{\r
+ if (buffer == 0)\r
+ {\r
+ /*\r
+ * This means that we should flush internal buffers. Since we don't we just return.\r
+ * (Remember, "handle" == -1 means that all handles should be flushed.)\r
+ */\r
+ return 0;\r
+ }\r
+\r
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */\r
+ if ((handle != 1) && (handle != 2))\r
+ {\r
+ return ((size_t)-1);\r
+ }\r
+\r
+ /* Send data. */\r
+ DbgConsole_SendData((uint8_t *)buffer, size);\r
+\r
+ return size;\r
+}\r
+\r
+#pragma weak __read\r
+size_t __read(int handle, unsigned char *buffer, size_t size)\r
+{\r
+ uint8_t ch = 0U;\r
+ size_t actualSize = 0U;\r
+ /* This function only reads from "standard in", for all other file handles it returns failure. */\r
+ if (handle != 0)\r
+ {\r
+ return ((size_t)-1);\r
+ }\r
+\r
+ /* Receive data.*/\r
+ for (; size > 0; size--)\r
+ {\r
+ DbgConsole_ReadCharacter(&ch);\r
+ if (ch == 0)\r
+ {\r
+ break;\r
+ }\r
+\r
+ *buffer++ = ch;\r
+ actualSize++;\r
+ }\r
+\r
+ return actualSize;\r
+}\r
+#endif /* SDK_DEBUGCONSOLE_UART */\r
+\r
+/* support LPC Xpresso with RedLib */\r
+#elif(defined(__REDLIB__))\r
+\r
+#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))\r
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)\r
+{\r
+ if (buffer == 0)\r
+ {\r
+ /* return -1 if error. */\r
+ return -1;\r
+ }\r
+\r
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */\r
+ if ((handle != 1) && (handle != 2))\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Send data. */\r
+ DbgConsole_SendData((uint8_t *)buffer, size);\r
+\r
+ return 0;\r
+}\r
+\r
+int __attribute__((weak)) __sys_readc(void)\r
+{\r
+ char tmp;\r
+\r
+ /* Receive data. */\r
+ DbgConsole_ReadCharacter((uint8_t *)&tmp);\r
+\r
+ return tmp;\r
+}\r
+#endif\r
+\r
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/\r
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)\r
+#if defined(SDK_DEBUGCONSOLE_UART)\r
+#if defined(__CC_ARM)\r
+struct __FILE\r
+{\r
+ int handle;\r
+ /*\r
+ * Whatever you require here. If the only file you are using is standard output using printf() for debugging,\r
+ * no file handling is required.\r
+ */\r
+};\r
+#endif\r
+\r
+/* FILE is typedef in stdio.h. */\r
+#pragma weak __stdout\r
+#pragma weak __stdin\r
+FILE __stdout;\r
+FILE __stdin;\r
+\r
+#pragma weak fputc\r
+int fputc(int ch, FILE *f)\r
+{\r
+ /* Send data. */\r
+ return DbgConsole_SendData((uint8_t *)(&ch), 1);\r
+}\r
+\r
+#pragma weak fgetc\r
+int fgetc(FILE *f)\r
+{\r
+ char ch;\r
+\r
+ /* Receive data. */\r
+ DbgConsole_ReadCharacter((uint8_t *)&ch);\r
+\r
+ return ch;\r
+}\r
+\r
+/*\r
+ * Terminate the program, passing a return code back to the user.\r
+ * This function may not return.\r
+ */\r
+void _sys_exit(int returncode)\r
+{\r
+ while (1)\r
+ {\r
+ }\r
+}\r
+\r
+/*\r
+ * Writes a character to the output channel. This function is used\r
+ * for last-resort error message output.\r
+ */\r
+void _ttywrch(int ch)\r
+{\r
+ char ench = ch;\r
+ DbgConsole_SendData((uint8_t *)(&ench), 1);\r
+}\r
+\r
+char *_sys_command_string(char *cmd, int len)\r
+{\r
+ return (cmd);\r
+}\r
+#endif /* SDK_DEBUGCONSOLE_UART */\r
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/\r
+#elif(defined(__GNUC__))\r
+\r
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \\r
+ (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))))\r
+\r
+int __attribute__((weak)) _write(int handle, char *buffer, int size)\r
+{\r
+ if (buffer == 0)\r
+ {\r
+ /* return -1 if error. */\r
+ return -1;\r
+ }\r
+\r
+ /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */\r
+ if ((handle != 1) && (handle != 2))\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Send data. */\r
+ DbgConsole_SendData((uint8_t *)buffer, size);\r
+\r
+ return size;\r
+}\r
+\r
+int __attribute__((weak)) _read(int handle, char *buffer, int size)\r
+{\r
+ uint8_t ch = 0U;\r
+ int actualSize = 0U;\r
+\r
+ /* This function only reads from "standard in", for all other file handles it returns failure. */\r
+ if (handle != 0)\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ for (; size > 0; size--)\r
+ {\r
+ DbgConsole_ReadCharacter(&ch);\r
+\r
+ *buffer++ = ch;\r
+ actualSize++;\r
+\r
+ if ((ch == 0) || (ch == '\n') || (ch == '\r'))\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return actualSize;\r
+}\r
+#endif\r
+#endif /* __ICCARM__ */\r
--- /dev/null
+/*\r
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.\r
+ * Copyright 2016-2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ * Debug console shall provide input and output functions to scan and print formatted data.\r
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"\r
+ * - [flags] :'-', '+', '#', ' ', '0'\r
+ * - [width]: number (0,1...)\r
+ * - [.precision]: number (0,1...)\r
+ * - [length]: do not support\r
+ * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'\r
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"\r
+ * - [*]: is supported.\r
+ * - [width]: number (0,1...)\r
+ * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')\r
+ * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'\r
+ */\r
+\r
+#ifndef _FSL_DEBUGCONSOLE_H_\r
+#define _FSL_DEBUGCONSOLE_H_\r
+\r
+#include "fsl_common.h"\r
+#include "serial_manager.h"\r
+\r
+/*!\r
+ * @addtogroup debugconsole\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */\r
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */\r
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */\r
+#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */\r
+\r
+/*! @brief Definition to select sdk or toolchain printf, scanf. */\r
+#ifndef SDK_DEBUGCONSOLE\r
+#define SDK_DEBUGCONSOLE 1U\r
+#endif\r
+\r
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */\r
+#ifndef SDK_DEBUGCONSOLE_UART\r
+/* mcux will handle this macro, not define it here */\r
+#if (!defined(__MCUXPRESSO))\r
+#define SDK_DEBUGCONSOLE_UART\r
+#endif\r
+#endif\r
+\r
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)\r
+#include <stdio.h>\r
+#endif\r
+\r
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.\r
+ *\r
+ * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.\r
+ * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.\r
+ * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.\r
+*/\r
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */\r
+#define PRINTF\r
+#define SCANF\r
+#define PUTCHAR\r
+#define GETCHAR\r
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */\r
+#define PRINTF DbgConsole_Printf\r
+#define SCANF DbgConsole_Scanf\r
+#define PUTCHAR DbgConsole_Putchar\r
+#define GETCHAR DbgConsole_Getchar\r
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \\r
+ */\r
+#define PRINTF printf\r
+#define SCANF scanf\r
+#define PUTCHAR putchar\r
+#define GETCHAR getchar\r
+#endif /* SDK_DEBUGCONSOLE */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/*! @name Initialization*/\r
+/* @{ */\r
+\r
+/*!\r
+ * @brief Initializes the peripheral used for debug messages.\r
+ *\r
+ * Call this function to enable debug log messages to be output via the specified peripheral\r
+ * initialized by the serial manager module.\r
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.\r
+ *\r
+ * @param instance The instance of the module.\r
+ * @param baudRate The desired baud rate in bits per second.\r
+ * @param device Low level device type for the debug console, can be one of the following.\r
+ * @arg kSerialPort_Uart,\r
+ * @arg kSerialPort_UsbCdc.\r
+ * @param clkSrcFreq Frequency of peripheral source clock.\r
+ *\r
+ * @return Indicates whether initialization was successful or not.\r
+ * @retval kStatus_Success Execution successfully\r
+ */\r
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);\r
+\r
+/*!\r
+ * @brief De-initializes the peripheral used for debug messages.\r
+ *\r
+ * Call this function to disable debug log messages to be output via the specified peripheral\r
+ * initialized by the serial manager module.\r
+ *\r
+ * @return Indicates whether de-initialization was successful or not.\r
+ */\r
+status_t DbgConsole_Deinit(void);\r
+\r
+#if SDK_DEBUGCONSOLE\r
+/*!\r
+ * @brief Writes formatted output to the standard output stream.\r
+ *\r
+ * Call this function to write a formatted output to the standard output stream.\r
+ *\r
+ * @param formatString Format control string.\r
+ * @return Returns the number of characters printed or a negative value if an error occurs.\r
+ */\r
+int DbgConsole_Printf(const char *formatString, ...);\r
+\r
+/*!\r
+ * @brief Writes a character to stdout.\r
+ *\r
+ * Call this function to write a character to stdout.\r
+ *\r
+ * @param ch Character to be written.\r
+ * @return Returns the character written.\r
+ */\r
+int DbgConsole_Putchar(int ch);\r
+\r
+/*!\r
+ * @brief Reads formatted data from the standard input stream.\r
+ *\r
+ * Call this function to read formatted data from the standard input stream.\r
+ *\r
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,\r
+ * other tasks will not be scheduled), the function cannot be used when the\r
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.\r
+ * And an error is returned when the function called in this case. The suggestion\r
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.\r
+ *\r
+ * @param formatString Format control string.\r
+ * @return Returns the number of fields successfully converted and assigned.\r
+ */\r
+int DbgConsole_Scanf(char *formatString, ...);\r
+\r
+/*!\r
+ * @brief Reads a character from standard input.\r
+ *\r
+ * Call this function to read a character from standard input.\r
+ *\r
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,\r
+ * other tasks will not be scheduled), the function cannot be used when the\r
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.\r
+ * And an error is returned when the function called in this case. The suggestion\r
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.\r
+ *\r
+ * @return Returns the character read.\r
+ */\r
+int DbgConsole_Getchar(void);\r
+\r
+/*!\r
+ * @brief Debug console flush.\r
+ *\r
+ * Call this function to wait the tx buffer empty.\r
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function\r
+ * This function should be called when\r
+ * 1, before enter power down mode\r
+ * 2, log is required to print to terminal immediately\r
+ * @return Indicates whether wait idle was successful or not.\r
+ */\r
+status_t DbgConsole_Flush(void);\r
+\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/*!\r
+ * @brief Debug console try to get char\r
+ * This function provides a API which will not block current task, if character is\r
+ * available return it, otherwise return fail.\r
+ * @param ch the address of char to receive\r
+ * @return Indicates get char was successful or not.\r
+ */\r
+status_t DbgConsole_TryGetchar(char *ch);\r
+#endif\r
+\r
+#endif /* SDK_DEBUGCONSOLE */\r
+\r
+/*! @} */\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_DEBUGCONSOLE_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017 - 2018 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_\r
+#define _FSL_DEBUG_CONSOLE_CONF_H_\r
+\r
+/****************Debug console configuration********************/\r
+\r
+/*! @brief If Non-blocking mode is needed, please define it at project setting,\r
+* otherwise blocking mode is the default transfer mode.\r
+* Warning: If you want to use non-blocking transfer,please make sure the corresponding\r
+* IO interrupt is enable, otherwise there is no output.\r
+* And non-blocking is combine with buffer, no matter bare-metal or rtos.\r
+*/\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically\r
+* when\r
+* non-blocking transfer is using,\r
+* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.\r
+* If it is configured too small, log maybe missed , because the log will not be\r
+* buffered if the buffer is full, and the print will return immediately with -1.\r
+* And this value should be multiple of 4 to meet memory alignment.\r
+*\r
+*/\r
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN\r
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)\r
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */\r
+\r
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when\r
+* non-blocking transfer is using,\r
+* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.\r
+* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.\r
+* And this value should be multiple of 4 to meet memory alignment.\r
+*\r
+*/\r
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN\r
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U)\r
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */\r
+\r
+#else\r
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+\r
+/*!@ brief Whether enable the RX function\r
+* If the macro is zero, the receive function of the debug console is disabled.\r
+*/\r
+#ifndef DEBUG_CONSOLE_RX_ENABLE\r
+#define DEBUG_CONSOLE_RX_ENABLE (1U)\r
+#endif /* DEBUG_CONSOLE_RX_ENABLE */\r
+\r
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log\r
+* length can not bigger than this value.\r
+* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if\r
+* the buffer is too big and current task stack size not big enough.\r
+*/\r
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN\r
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)\r
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */\r
+\r
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log\r
+* length can not bigger than this value.\r
+* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.\r
+*/\r
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN\r
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)\r
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */\r
+\r
+/*! @brief Debug console synchronization\r
+* User should not change these macro for synchronization mode, but add the\r
+* corresponding synchronization mechanism per different software environment.\r
+* Such as, if another RTOS is used,\r
+* add:\r
+* #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3\r
+* in this configuration file and implement the synchronization in fsl.log.c.\r
+*/\r
+/*! @brief synchronization for baremetal software */\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0\r
+/*! @brief synchronization for freertos software */\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1\r
+\r
+/*! @brief RTOS synchronization mechanism disable\r
+* If not defined, default is enable, to avoid multitask log print mess.\r
+* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c\r
+* If synchronization is disabled, log maybe messed on terminal.\r
+*/\r
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION\r
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING\r
+#ifdef FSL_RTOS_FREE_RTOS\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS\r
+#else\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM\r
+#endif /* FSL_RTOS_FREE_RTOS */\r
+#else\r
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM\r
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */\r
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */\r
+\r
+/*! @brief echo function support\r
+* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO\r
+* at your project setting.\r
+*/\r
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO\r
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0\r
+#else\r
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1\r
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */\r
+\r
+/*********************************************************************/\r
+\r
+/***************Debug console other configuration*********************/\r
+/*! @brief Definition to printf the float number. */\r
+#ifndef PRINTF_FLOAT_ENABLE\r
+#define PRINTF_FLOAT_ENABLE 0U\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+/*! @brief Definition to scanf the float number. */\r
+#ifndef SCANF_FLOAT_ENABLE\r
+#define SCANF_FLOAT_ENABLE 0U\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+\r
+/*! @brief Definition to support advanced format specifier for printf. */\r
+#ifndef PRINTF_ADVANCED_ENABLE\r
+#define PRINTF_ADVANCED_ENABLE 0U\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+/*! @brief Definition to support advanced format specifier for scanf. */\r
+#ifndef SCANF_ADVANCED_ENABLE\r
+#define SCANF_ADVANCED_ENABLE 0U\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+\r
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */\r
+#ifndef BOARD_USE_VIRTUALCOM\r
+#define BOARD_USE_VIRTUALCOM 0U\r
+#endif\r
+/*******************************************************************/\r
+\r
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */\r
--- /dev/null
+/*\r
+ * Copyright 2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+#include <math.h>\r
+#include <stdarg.h>\r
+#include <stdlib.h>\r
+#include "fsl_str.h"\r
+#include "fsl_debug_console_conf.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+\r
+/*! @brief The overflow value.*/\r
+#ifndef HUGE_VAL\r
+#define HUGE_VAL (99.e99)\r
+#endif /* HUGE_VAL */\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+/*! @brief Specification modifier flags for printf. */\r
+enum _debugconsole_printf_flag\r
+{\r
+ kPRINTF_Minus = 0x01U, /*!< Minus FLag. */\r
+ kPRINTF_Plus = 0x02U, /*!< Plus Flag. */\r
+ kPRINTF_Space = 0x04U, /*!< Space Flag. */\r
+ kPRINTF_Zero = 0x08U, /*!< Zero Flag. */\r
+ kPRINTF_Pound = 0x10U, /*!< Pound Flag. */\r
+ kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */\r
+ kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */\r
+ kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */\r
+ kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */\r
+};\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+/*! @brief Specification modifier flags for scanf. */\r
+enum _debugconsole_scanf_flag\r
+{\r
+ kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */\r
+ kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */\r
+ kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */\r
+ kSCANF_DestString = 0x8U, /*!< Destination String FLag. */\r
+ kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */\r
+ kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */\r
+ kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */\r
+ kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */\r
+#if SCANF_ADVANCED_ENABLE\r
+ kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */\r
+ kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */\r
+ kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */\r
+ kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+#if SCANF_FLOAT_ENABLE\r
+ kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */\r
+#endif /*PRINTF_FLOAT_ENABLE */\r
+ kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */\r
+};\r
+\r
+/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */\r
+#if defined(__CC_ARM)\r
+#pragma diag_suppress 1256\r
+#endif /* __CC_ARM */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+/*!\r
+ * @brief Scanline function which ignores white spaces.\r
+ *\r
+ * @param[in] s The address of the string pointer to update.\r
+ * @return String without white spaces.\r
+ */\r
+static uint32_t ScanIgnoreWhiteSpace(const char **s);\r
+\r
+/*!\r
+ * @brief Converts a radix number to a string and return its length.\r
+ *\r
+ * @param[in] numstr Converted string of the number.\r
+ * @param[in] nump Pointer to the number.\r
+ * @param[in] neg Polarity of the number.\r
+ * @param[in] radix The radix to be converted to.\r
+ * @param[in] use_caps Used to identify %x/X output format.\r
+\r
+ * @return Length of the converted string.\r
+ */\r
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps);\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+/*!\r
+ * @brief Converts a floating radix number to a string and return its length.\r
+ *\r
+ * @param[in] numstr Converted string of the number.\r
+ * @param[in] nump Pointer to the number.\r
+ * @param[in] radix The radix to be converted to.\r
+ * @param[in] precision_width Specify the precision width.\r
+\r
+ * @return Length of the converted string.\r
+ */\r
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width);\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+/*!\r
+*\r
+ */\r
+double modf(double input_dbl, double *intpart_ptr);\r
+\r
+/*************Code for process formatted data*******************************/\r
+\r
+static uint32_t ScanIgnoreWhiteSpace(const char **s)\r
+{\r
+ uint8_t count = 0;\r
+ uint8_t c;\r
+\r
+ c = **s;\r
+ while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f'))\r
+ {\r
+ count++;\r
+ (*s)++;\r
+ c = **s;\r
+ }\r
+ return count;\r
+}\r
+\r
+static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps)\r
+{\r
+#if PRINTF_ADVANCED_ENABLE\r
+ int64_t a;\r
+ int64_t b;\r
+ int64_t c;\r
+\r
+ uint64_t ua;\r
+ uint64_t ub;\r
+ uint64_t uc;\r
+#else\r
+ int32_t a;\r
+ int32_t b;\r
+ int32_t c;\r
+\r
+ uint32_t ua;\r
+ uint32_t ub;\r
+ uint32_t uc;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+ int32_t nlen;\r
+ char *nstrp;\r
+\r
+ nlen = 0;\r
+ nstrp = numstr;\r
+ *nstrp++ = '\0';\r
+\r
+ if (neg)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ a = *(int64_t *)nump;\r
+#else\r
+ a = *(int32_t *)nump;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ if (a == 0)\r
+ {\r
+ *nstrp = '0';\r
+ ++nlen;\r
+ return nlen;\r
+ }\r
+ while (a != 0)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ b = (int64_t)a / (int64_t)radix;\r
+ c = (int64_t)a - ((int64_t)b * (int64_t)radix);\r
+ if (c < 0)\r
+ {\r
+ uc = (uint64_t)c;\r
+ c = (int64_t)(~uc) + 1 + '0';\r
+ }\r
+#else\r
+ b = a / radix;\r
+ c = a - (b * radix);\r
+ if (c < 0)\r
+ {\r
+ uc = (uint32_t)c;\r
+ c = (uint32_t)(~uc) + 1 + '0';\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ else\r
+ {\r
+ c = c + '0';\r
+ }\r
+ a = b;\r
+ *nstrp++ = (char)c;\r
+ ++nlen;\r
+ }\r
+ }\r
+ else\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ ua = *(uint64_t *)nump;\r
+#else\r
+ ua = *(uint32_t *)nump;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ if (ua == 0)\r
+ {\r
+ *nstrp = '0';\r
+ ++nlen;\r
+ return nlen;\r
+ }\r
+ while (ua != 0)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ ub = (uint64_t)ua / (uint64_t)radix;\r
+ uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix);\r
+#else\r
+ ub = ua / (uint32_t)radix;\r
+ uc = ua - (ub * (uint32_t)radix);\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+ if (uc < 10)\r
+ {\r
+ uc = uc + '0';\r
+ }\r
+ else\r
+ {\r
+ uc = uc - 10 + (use_caps ? 'A' : 'a');\r
+ }\r
+ ua = ub;\r
+ *nstrp++ = (char)uc;\r
+ ++nlen;\r
+ }\r
+ }\r
+ return nlen;\r
+}\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width)\r
+{\r
+ int32_t a;\r
+ int32_t b;\r
+ int32_t c;\r
+ int32_t i;\r
+ uint32_t uc;\r
+ double fa;\r
+ double dc;\r
+ double fb;\r
+ double r;\r
+ double fractpart;\r
+ double intpart;\r
+\r
+ int32_t nlen;\r
+ char *nstrp;\r
+ nlen = 0;\r
+ nstrp = numstr;\r
+ *nstrp++ = '\0';\r
+ r = *(double *)nump;\r
+ if (!r)\r
+ {\r
+ *nstrp = '0';\r
+ ++nlen;\r
+ return nlen;\r
+ }\r
+ fractpart = modf((double)r, (double *)&intpart);\r
+ /* Process fractional part. */\r
+ for (i = 0; i < precision_width; i++)\r
+ {\r
+ fractpart *= radix;\r
+ }\r
+ if (r >= 0)\r
+ {\r
+ fa = fractpart + (double)0.5;\r
+ if (fa >= pow(10, precision_width))\r
+ {\r
+ intpart++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ fa = fractpart - (double)0.5;\r
+ if (fa <= -pow(10, precision_width))\r
+ {\r
+ intpart--;\r
+ }\r
+ }\r
+ for (i = 0; i < precision_width; i++)\r
+ {\r
+ fb = fa / (int32_t)radix;\r
+ dc = (fa - (int64_t)fb * (int32_t)radix);\r
+ c = (int32_t)dc;\r
+ if (c < 0)\r
+ {\r
+ uc = (uint32_t)c;\r
+ c = (int32_t)(~uc) + 1 + '0';\r
+ }\r
+ else\r
+ {\r
+ c = c + '0';\r
+ }\r
+ fa = fb;\r
+ *nstrp++ = (char)c;\r
+ ++nlen;\r
+ }\r
+ *nstrp++ = (char)'.';\r
+ ++nlen;\r
+ a = (int32_t)intpart;\r
+ if (a == 0)\r
+ {\r
+ *nstrp++ = '0';\r
+ ++nlen;\r
+ }\r
+ else\r
+ {\r
+ while (a != 0)\r
+ {\r
+ b = (int32_t)a / (int32_t)radix;\r
+ c = (int32_t)a - ((int32_t)b * (int32_t)radix);\r
+ if (c < 0)\r
+ {\r
+ uc = (uint32_t)c;\r
+ c = (int32_t)(~uc) + 1 + '0';\r
+ }\r
+ else\r
+ {\r
+ c = c + '0';\r
+ }\r
+ a = b;\r
+ *nstrp++ = (char)c;\r
+ ++nlen;\r
+ }\r
+ }\r
+ return nlen;\r
+}\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+/*!\r
+ * brief This function outputs its parameters according to a formatted string.\r
+ *\r
+ * note I/O is performed by calling given function pointer using following\r
+ * (*func_ptr)(c);\r
+ *\r
+ * param[in] fmt_ptr Format string for printf.\r
+ * param[in] args_ptr Arguments to printf.\r
+ * param[in] buf pointer to the buffer\r
+ * param cb print callback function pointer\r
+ *\r
+ * return Number of characters to be print\r
+ */\r
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb)\r
+{\r
+ /* va_list ap; */\r
+ char *p;\r
+ int32_t c;\r
+\r
+ char vstr[33];\r
+ char *vstrp = NULL;\r
+ int32_t vlen = 0;\r
+\r
+ int32_t done;\r
+ int32_t count = 0;\r
+\r
+ uint32_t field_width;\r
+ uint32_t precision_width;\r
+ char *sval;\r
+ int32_t cval;\r
+ bool use_caps;\r
+ uint8_t radix = 0;\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ uint32_t flags_used;\r
+ int32_t schar, dschar;\r
+ int64_t ival;\r
+ uint64_t uval = 0;\r
+ bool valid_precision_width;\r
+#else\r
+ int32_t ival;\r
+ uint32_t uval = 0;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+ double fval;\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+\r
+ /* Start parsing apart the format string and display appropriate formats and data. */\r
+ for (p = (char *)fmt; (c = *p) != 0; p++)\r
+ {\r
+ /*\r
+ * All formats begin with a '%' marker. Special chars like\r
+ * '\n' or '\t' are normally converted to the appropriate\r
+ * character by the __compiler__. Thus, no need for this\r
+ * routine to account for the '\' character.\r
+ */\r
+ if (c != '%')\r
+ {\r
+ cb(buf, &count, c, 1);\r
+ /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */\r
+ continue;\r
+ }\r
+\r
+ use_caps = true;\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ /* First check for specification modifier flags. */\r
+ flags_used = 0;\r
+ done = false;\r
+ while (!done)\r
+ {\r
+ switch (*++p)\r
+ {\r
+ case '-':\r
+ flags_used |= kPRINTF_Minus;\r
+ break;\r
+ case '+':\r
+ flags_used |= kPRINTF_Plus;\r
+ break;\r
+ case ' ':\r
+ flags_used |= kPRINTF_Space;\r
+ break;\r
+ case '0':\r
+ flags_used |= kPRINTF_Zero;\r
+ break;\r
+ case '#':\r
+ flags_used |= kPRINTF_Pound;\r
+ break;\r
+ default:\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ done = true;\r
+ break;\r
+ }\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+ /* Next check for minimum field width. */\r
+ field_width = 0;\r
+ done = false;\r
+ while (!done)\r
+ {\r
+ c = *++p;\r
+ if ((c >= '0') && (c <= '9'))\r
+ {\r
+ field_width = (field_width * 10) + (c - '0');\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ else if (c == '*')\r
+ {\r
+ field_width = (uint32_t)va_arg(ap, uint32_t);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ else\r
+ {\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ done = true;\r
+ }\r
+ }\r
+ /* Next check for the width and precision field separator. */\r
+ precision_width = 6;\r
+#if PRINTF_ADVANCED_ENABLE\r
+ valid_precision_width = false;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ if (*++p == '.')\r
+ {\r
+ /* Must get precision field width, if present. */\r
+ precision_width = 0;\r
+ done = false;\r
+ while (!done)\r
+ {\r
+ c = *++p;\r
+ if ((c >= '0') && (c <= '9'))\r
+ {\r
+ precision_width = (precision_width * 10) + (c - '0');\r
+#if PRINTF_ADVANCED_ENABLE\r
+ valid_precision_width = true;\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ else if (c == '*')\r
+ {\r
+ precision_width = (uint32_t)va_arg(ap, uint32_t);\r
+ valid_precision_width = true;\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ else\r
+ {\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ done = true;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* We've gone one char too far. */\r
+ --p;\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ /*\r
+ * Check for the length modifier.\r
+ */\r
+ switch (/* c = */ *++p)\r
+ {\r
+ case 'h':\r
+ if (*++p != 'h')\r
+ {\r
+ flags_used |= kPRINTF_LengthShortInt;\r
+ --p;\r
+ }\r
+ else\r
+ {\r
+ flags_used |= kPRINTF_LengthChar;\r
+ }\r
+ break;\r
+ case 'l':\r
+ if (*++p != 'l')\r
+ {\r
+ flags_used |= kPRINTF_LengthLongInt;\r
+ --p;\r
+ }\r
+ else\r
+ {\r
+ flags_used |= kPRINTF_LengthLongLongInt;\r
+ }\r
+ break;\r
+ default:\r
+ /* we've gone one char too far */\r
+ --p;\r
+ break;\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ /* Now we're ready to examine the format. */\r
+ c = *++p;\r
+ {\r
+ if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') ||\r
+ (c == 'b') || (c == 'p') || (c == 'u'))\r
+ {\r
+ if ((c == 'd') || (c == 'i'))\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_LengthLongLongInt)\r
+ {\r
+ ival = (int64_t)va_arg(ap, int64_t);\r
+ }\r
+ else\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ ival = (int32_t)va_arg(ap, int32_t);\r
+ }\r
+ vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps);\r
+ vstrp = &vstr[vlen];\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (ival < 0)\r
+ {\r
+ schar = '-';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Plus)\r
+ {\r
+ schar = '+';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Space)\r
+ {\r
+ schar = ' ';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ schar = 0;\r
+ }\r
+ }\r
+ }\r
+ dschar = false;\r
+ /* Do the ZERO pad. */\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+ }\r
+ }\r
+ /* The string was built in reverse order, now display in correct order. */\r
+ if ((!dschar) && schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+\r
+#if PRINTF_FLOAT_ENABLE\r
+ if ((c == 'f') || (c == 'F'))\r
+ {\r
+ fval = (double)va_arg(ap, double);\r
+ vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width);\r
+ vstrp = &vstr[vlen];\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (fval < 0)\r
+ {\r
+ schar = '-';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Plus)\r
+ {\r
+ schar = '+';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ if (flags_used & kPRINTF_Space)\r
+ {\r
+ schar = ' ';\r
+ ++vlen;\r
+ }\r
+ else\r
+ {\r
+ schar = 0;\r
+ }\r
+ }\r
+ }\r
+ dschar = false;\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ if (schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+ dschar = true;\r
+ }\r
+ }\r
+ if ((!dschar) && schar)\r
+ {\r
+ cb(buf, &count, schar, 1);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+#endif /* PRINTF_FLOAT_ENABLE */\r
+ if ((c == 'X') || (c == 'x'))\r
+ {\r
+ if (c == 'x')\r
+ {\r
+ use_caps = false;\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_LengthLongLongInt)\r
+ {\r
+ uval = (uint64_t)va_arg(ap, uint64_t);\r
+ }\r
+ else\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ uval = (uint32_t)va_arg(ap, uint32_t);\r
+ }\r
+ vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps);\r
+ vstrp = &vstr[vlen];\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ dschar = false;\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ if (flags_used & kPRINTF_Pound)\r
+ {\r
+ cb(buf, &count, '0', 1);\r
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);\r
+ dschar = true;\r
+ }\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ if (flags_used & kPRINTF_Pound)\r
+ {\r
+ vlen += 2;\r
+ }\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ if (flags_used & kPRINTF_Pound)\r
+ {\r
+ cb(buf, &count, '0', 1);\r
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);\r
+ dschar = true;\r
+ }\r
+ }\r
+ }\r
+\r
+ if ((flags_used & kPRINTF_Pound) && (!dschar))\r
+ {\r
+ cb(buf, &count, '0', 1);\r
+ cb(buf, &count, (use_caps ? 'X' : 'x'), 1);\r
+ vlen += 2;\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+ if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u'))\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_LengthLongLongInt)\r
+ {\r
+ uval = (uint64_t)va_arg(ap, uint64_t);\r
+ }\r
+ else\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ uval = (uint32_t)va_arg(ap, uint32_t);\r
+ }\r
+\r
+ if (c == 'o')\r
+ {\r
+ radix = 8;\r
+ }\r
+ else if (c == 'b')\r
+ {\r
+ radix = 2;\r
+ }\r
+ else if (c == 'p')\r
+ {\r
+ radix = 16;\r
+ }\r
+ else\r
+ {\r
+ radix = 10;\r
+ }\r
+\r
+ vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps);\r
+ vstrp = &vstr[vlen];\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_Zero)\r
+ {\r
+ cb(buf, &count, '0', field_width - vlen);\r
+ vlen = field_width;\r
+ }\r
+ else\r
+ {\r
+ if (!(flags_used & kPRINTF_Minus))\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+#if !PRINTF_ADVANCED_ENABLE\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+#endif /* !PRINTF_ADVANCED_ENABLE */\r
+ if (vstrp != NULL)\r
+ {\r
+ while (*vstrp)\r
+ {\r
+ cb(buf, &count, *vstrp--, 1);\r
+ }\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_Minus)\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+ else if (c == 'c')\r
+ {\r
+ cval = (char)va_arg(ap, uint32_t);\r
+ cb(buf, &count, cval, 1);\r
+ }\r
+ else if (c == 's')\r
+ {\r
+ sval = (char *)va_arg(ap, char *);\r
+ if (sval)\r
+ {\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (valid_precision_width)\r
+ {\r
+ vlen = precision_width;\r
+ }\r
+ else\r
+ {\r
+ vlen = strlen(sval);\r
+ }\r
+#else\r
+ vlen = strlen(sval);\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (!(flags_used & kPRINTF_Minus))\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (valid_precision_width)\r
+ {\r
+ while ((*sval) && (vlen > 0))\r
+ {\r
+ cb(buf, &count, *sval++, 1);\r
+ vlen--;\r
+ }\r
+ /* In case that vlen sval is shorter than vlen */\r
+ vlen = precision_width - vlen;\r
+ }\r
+ else\r
+ {\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ while (*sval)\r
+ {\r
+ cb(buf, &count, *sval++, 1);\r
+ }\r
+#if PRINTF_ADVANCED_ENABLE\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+\r
+#if PRINTF_ADVANCED_ENABLE\r
+ if (flags_used & kPRINTF_Minus)\r
+ {\r
+ cb(buf, &count, ' ', field_width - vlen);\r
+ }\r
+#endif /* PRINTF_ADVANCED_ENABLE */\r
+ }\r
+ }\r
+ else\r
+ {\r
+ cb(buf, &count, c, 1);\r
+ }\r
+ }\r
+ }\r
+\r
+ return count;\r
+}\r
+\r
+/*!\r
+ * brief Converts an input line of ASCII characters based upon a provided\r
+ * string format.\r
+ *\r
+ * param[in] line_ptr The input line of ASCII data.\r
+ * param[in] format Format first points to the format string.\r
+ * param[in] args_ptr The list of parameters.\r
+ *\r
+ * return Number of input items converted and assigned.\r
+ * retval IO_EOF When line_ptr is empty string "".\r
+ */\r
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr)\r
+{\r
+ uint8_t base;\r
+ int8_t neg;\r
+ /* Identifier for the format string. */\r
+ char *c = format;\r
+ char temp;\r
+ char *buf;\r
+ /* Flag telling the conversion specification. */\r
+ uint32_t flag = 0;\r
+ /* Filed width for the matching input streams. */\r
+ uint32_t field_width;\r
+ /* How many arguments are assigned except the suppress. */\r
+ uint32_t nassigned = 0;\r
+ /* How many characters are read from the input streams. */\r
+ uint32_t n_decode = 0;\r
+\r
+ int32_t val;\r
+\r
+ const char *s;\r
+ /* Identifier for the input string. */\r
+ const char *p = line_ptr;\r
+\r
+#if SCANF_FLOAT_ENABLE\r
+ double fnum = 0.0;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ /* Return EOF error before any conversion. */\r
+ if (*p == '\0')\r
+ {\r
+ return -1;\r
+ }\r
+\r
+ /* Decode directives. */\r
+ while ((*c) && (*p))\r
+ {\r
+ /* Ignore all white-spaces in the format strings. */\r
+ if (ScanIgnoreWhiteSpace((const char **)&c))\r
+ {\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ }\r
+ else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%')))\r
+ {\r
+ /* Ordinary characters. */\r
+ c++;\r
+ if (*p == *c)\r
+ {\r
+ n_decode++;\r
+ p++;\r
+ c++;\r
+ }\r
+ else\r
+ {\r
+ /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream.\r
+ * However, it is deserted now. */\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* convernsion specification */\r
+ c++;\r
+ /* Reset. */\r
+ flag = 0;\r
+ field_width = 0;\r
+ base = 0;\r
+\r
+ /* Loop to get full conversion specification. */\r
+ while ((*c) && (!(flag & kSCANF_DestMask)))\r
+ {\r
+ switch (*c)\r
+ {\r
+#if SCANF_ADVANCED_ENABLE\r
+ case '*':\r
+ if (flag & kSCANF_Suppress)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+ flag |= kSCANF_Suppress;\r
+ c++;\r
+ break;\r
+ case 'h':\r
+ if (flag & kSCANF_LengthMask)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+\r
+ if (c[1] == 'h')\r
+ {\r
+ flag |= kSCANF_LengthChar;\r
+ c++;\r
+ }\r
+ else\r
+ {\r
+ flag |= kSCANF_LengthShortInt;\r
+ }\r
+ c++;\r
+ break;\r
+ case 'l':\r
+ if (flag & kSCANF_LengthMask)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+\r
+ if (c[1] == 'l')\r
+ {\r
+ flag |= kSCANF_LengthLongLongInt;\r
+ c++;\r
+ }\r
+ else\r
+ {\r
+ flag |= kSCANF_LengthLongInt;\r
+ }\r
+ c++;\r
+ break;\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+#if SCANF_FLOAT_ENABLE\r
+ case 'L':\r
+ if (flag & kSCANF_LengthMask)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+ flag |= kSCANF_LengthLongLongDouble;\r
+ c++;\r
+ break;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ case '0':\r
+ case '1':\r
+ case '2':\r
+ case '3':\r
+ case '4':\r
+ case '5':\r
+ case '6':\r
+ case '7':\r
+ case '8':\r
+ case '9':\r
+ if (field_width)\r
+ {\r
+ /* Match failure. */\r
+ return nassigned;\r
+ }\r
+ do\r
+ {\r
+ field_width = field_width * 10 + *c - '0';\r
+ c++;\r
+ } while ((*c >= '0') && (*c <= '9'));\r
+ break;\r
+ case 'd':\r
+ base = 10;\r
+ flag |= kSCANF_TypeSinged;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'u':\r
+ base = 10;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'o':\r
+ base = 8;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'x':\r
+ case 'X':\r
+ base = 16;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+ case 'i':\r
+ base = 0;\r
+ flag |= kSCANF_DestInt;\r
+ c++;\r
+ break;\r
+#if SCANF_FLOAT_ENABLE\r
+ case 'a':\r
+ case 'A':\r
+ case 'e':\r
+ case 'E':\r
+ case 'f':\r
+ case 'F':\r
+ case 'g':\r
+ case 'G':\r
+ flag |= kSCANF_DestFloat;\r
+ c++;\r
+ break;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ case 'c':\r
+ flag |= kSCANF_DestChar;\r
+ if (!field_width)\r
+ {\r
+ field_width = 1;\r
+ }\r
+ c++;\r
+ break;\r
+ case 's':\r
+ flag |= kSCANF_DestString;\r
+ c++;\r
+ break;\r
+ default:\r
+ return nassigned;\r
+ }\r
+ }\r
+\r
+ if (!(flag & kSCANF_DestMask))\r
+ {\r
+ /* Format strings are exhausted. */\r
+ return nassigned;\r
+ }\r
+\r
+ if (!field_width)\r
+ {\r
+ /* Large than length of a line. */\r
+ field_width = 99;\r
+ }\r
+\r
+ /* Matching strings in input streams and assign to argument. */\r
+ switch (flag & kSCANF_DestMask)\r
+ {\r
+ case kSCANF_DestChar:\r
+ s = (const char *)p;\r
+ buf = va_arg(args_ptr, char *);\r
+ while ((field_width--) && (*p))\r
+ {\r
+ if (!(flag & kSCANF_Suppress))\r
+ {\r
+ *buf++ = *p++;\r
+ }\r
+ else\r
+ {\r
+ p++;\r
+ }\r
+ n_decode++;\r
+ }\r
+\r
+ if ((!(flag & kSCANF_Suppress)) && (s != p))\r
+ {\r
+ nassigned++;\r
+ }\r
+ break;\r
+ case kSCANF_DestString:\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ s = p;\r
+ buf = va_arg(args_ptr, char *);\r
+ while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') &&\r
+ (*p != '\r') && (*p != '\v') && (*p != '\f'))\r
+ {\r
+ if (flag & kSCANF_Suppress)\r
+ {\r
+ p++;\r
+ }\r
+ else\r
+ {\r
+ *buf++ = *p++;\r
+ }\r
+ n_decode++;\r
+ }\r
+\r
+ if ((!(flag & kSCANF_Suppress)) && (s != p))\r
+ {\r
+ /* Add NULL to end of string. */\r
+ *buf = '\0';\r
+ nassigned++;\r
+ }\r
+ break;\r
+ case kSCANF_DestInt:\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ s = p;\r
+ val = 0;\r
+ if ((base == 0) || (base == 16))\r
+ {\r
+ if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X')))\r
+ {\r
+ base = 16;\r
+ if (field_width >= 1)\r
+ {\r
+ p += 2;\r
+ n_decode += 2;\r
+ field_width -= 2;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (base == 0)\r
+ {\r
+ if (s[0] == '0')\r
+ {\r
+ base = 8;\r
+ }\r
+ else\r
+ {\r
+ base = 10;\r
+ }\r
+ }\r
+\r
+ neg = 1;\r
+ switch (*p)\r
+ {\r
+ case '-':\r
+ neg = -1;\r
+ n_decode++;\r
+ p++;\r
+ field_width--;\r
+ break;\r
+ case '+':\r
+ neg = 1;\r
+ n_decode++;\r
+ p++;\r
+ field_width--;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ while ((*p) && (field_width--))\r
+ {\r
+ if ((*p <= '9') && (*p >= '0'))\r
+ {\r
+ temp = *p - '0';\r
+ }\r
+ else if ((*p <= 'f') && (*p >= 'a'))\r
+ {\r
+ temp = *p - 'a' + 10;\r
+ }\r
+ else if ((*p <= 'F') && (*p >= 'A'))\r
+ {\r
+ temp = *p - 'A' + 10;\r
+ }\r
+ else\r
+ {\r
+ temp = base;\r
+ }\r
+\r
+ if (temp >= base)\r
+ {\r
+ break;\r
+ }\r
+ else\r
+ {\r
+ val = base * val + temp;\r
+ }\r
+ p++;\r
+ n_decode++;\r
+ }\r
+ val *= neg;\r
+ if (!(flag & kSCANF_Suppress))\r
+ {\r
+#if SCANF_ADVANCED_ENABLE\r
+ switch (flag & kSCANF_LengthMask)\r
+ {\r
+ case kSCANF_LengthChar:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed char *) = (signed char)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned char *) = (unsigned char)val;\r
+ }\r
+ break;\r
+ case kSCANF_LengthShortInt:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed short *) = (signed short)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned short *) = (unsigned short)val;\r
+ }\r
+ break;\r
+ case kSCANF_LengthLongInt:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed long int *) = (signed long int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val;\r
+ }\r
+ break;\r
+ case kSCANF_LengthLongLongInt:\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed long long int *) = (signed long long int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val;\r
+ }\r
+ break;\r
+ default:\r
+ /* The default type is the type int. */\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed int *) = (signed int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;\r
+ }\r
+ break;\r
+ }\r
+#else\r
+ /* The default type is the type int. */\r
+ if (flag & kSCANF_TypeSinged)\r
+ {\r
+ *va_arg(args_ptr, signed int *) = (signed int)val;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, unsigned int *) = (unsigned int)val;\r
+ }\r
+#endif /* SCANF_ADVANCED_ENABLE */\r
+ nassigned++;\r
+ }\r
+ break;\r
+#if SCANF_FLOAT_ENABLE\r
+ case kSCANF_DestFloat:\r
+ n_decode += ScanIgnoreWhiteSpace(&p);\r
+ fnum = strtod(p, (char **)&s);\r
+\r
+ if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL))\r
+ {\r
+ break;\r
+ }\r
+\r
+ n_decode += (int)(s) - (int)(p);\r
+ p = s;\r
+ if (!(flag & kSCANF_Suppress))\r
+ {\r
+ if (flag & kSCANF_LengthLongLongDouble)\r
+ {\r
+ *va_arg(args_ptr, double *) = fnum;\r
+ }\r
+ else\r
+ {\r
+ *va_arg(args_ptr, float *) = (float)fnum;\r
+ }\r
+ nassigned++;\r
+ }\r
+ break;\r
+#endif /* SCANF_FLOAT_ENABLE */\r
+ default:\r
+ return nassigned;\r
+ }\r
+ }\r
+ }\r
+ return nassigned;\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2017 NXP\r
+ * All rights reserved.\r
+ *\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ *\r
+ */\r
+\r
+#ifndef _FSL_STR_H\r
+#define _FSL_STR_H\r
+\r
+#include "fsl_common.h"\r
+\r
+/*!\r
+ * @addtogroup debugconsole\r
+ * @{\r
+ */\r
+\r
+/*******************************************************************************\r
+ * Prototypes\r
+ ******************************************************************************/\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/*!\r
+ * @brief A function pointer which is used when format printf log.\r
+ */\r
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);\r
+\r
+/*!\r
+ * @brief This function outputs its parameters according to a formatted string.\r
+ *\r
+ * @note I/O is performed by calling given function pointer using following\r
+ * (*func_ptr)(c);\r
+ *\r
+ * @param[in] fmt Format string for printf.\r
+ * @param[in] ap Arguments to printf.\r
+ * @param[in] buf pointer to the buffer\r
+ * @param cb print callbck function pointer\r
+ *\r
+ * @return Number of characters to be print\r
+ */\r
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);\r
+\r
+/*!\r
+ * @brief Converts an input line of ASCII characters based upon a provided\r
+ * string format.\r
+ *\r
+ * @param[in] line_ptr The input line of ASCII data.\r
+ * @param[in] format Format first points to the format string.\r
+ * @param[in] args_ptr The list of parameters.\r
+ *\r
+ * @return Number of input items converted and assigned.\r
+ * @retval IO_EOF When line_ptr is empty string "".\r
+ */\r
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif /* __cplusplus */\r
+\r
+/*! @} */\r
+\r
+#endif /* _FSL_STR_H */\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/******************************************************************************\r
+ See http://www.freertos.org/a00110.html for an explanation of the\r
+ definitions contained in this file.\r
+******************************************************************************/\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ * http://www.freertos.org/a00110.html\r
+ *----------------------------------------------------------*/\r
+\r
+extern uint32_t SystemCoreClock;\r
+\r
+/* Cortex M33 port configuration. */\r
+#define configENABLE_MPU 1\r
+#define configENABLE_FPU 1\r
+#define configENABLE_TRUSTZONE 1\r
+\r
+/* Constants related to the behaviour or the scheduler. */\r
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_TIME_SLICING 1\r
+#define configMAX_PRIORITIES ( 5 )\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */\r
+\r
+/* Constants that describe the hardware and memory usage. */\r
+#define configCPU_CLOCK_HZ SystemCoreClock\r
+#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 )\r
+#define configMINIMAL_SECURE_STACK_SIZE ( 1024 )\r
+#define configMAX_TASK_NAME_LEN ( 12 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) )\r
+\r
+/* Constants that build features in or out. */\r
+#define configUSE_MUTEXES 1\r
+#define configUSE_TICKLESS_IDLE 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_NEWLIB_REENTRANT 0\r
+#define configUSE_CO_ROUTINES 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_QUEUE_SETS 0\r
+#define configUSE_TASK_NOTIFICATIONS 1\r
+#define configUSE_TRACE_FACILITY 1\r
+\r
+/* Constants that define which hook (callback) functions should be used. */\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configUSE_MALLOC_FAILED_HOOK 0\r
+\r
+/* Constants provided for debugging and optimisation assistance. */\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+#define configQUEUE_REGISTRY_SIZE 0\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 3 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+ * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is\r
+ * only necessary if the linker does not automatically remove functions that are\r
+ * not referenced anyway. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 0\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+#define INCLUDE_uxTaskGetStackHighWaterMark 0\r
+#define INCLUDE_xTaskGetIdleTaskHandle 0\r
+#define INCLUDE_eTaskGetState 1\r
+#define INCLUDE_xTaskResumeFromISR 0\r
+#define INCLUDE_xTaskGetCurrentTaskHandle 1\r
+#define INCLUDE_xTaskGetSchedulerState 0\r
+#define INCLUDE_xSemaphoreGetMutexHolder 0\r
+#define INCLUDE_xTimerPendFunctionCall 1\r
+\r
+/* This demo makes use of one or more example stats formatting functions. These\r
+ * format the raw data provided by the uxTaskGetSystemState() function in to\r
+ * human readable ASCII form. See the notes in the implementation of vTaskList()\r
+ * within FreeRTOS/Source/tasks.c for limitations. */\r
+#define configUSE_STATS_FORMATTING_FUNCTIONS 1\r
+\r
+/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter.\r
+ * See the FreeRTOS+CLI documentation for more information:\r
+ * http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */\r
+#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048\r
+\r
+/* Interrupt priority configuration follows...................... */\r
+\r
+/* Use the system definition, if there is one. */\r
+#ifdef __NVIC_PRIO_BITS\r
+ #define configPRIO_BITS __NVIC_PRIO_BITS\r
+#else\r
+ #define configPRIO_BITS 3 /* 8 priority levels. */\r
+#endif\r
+\r
+/* The lowest interrupt priority that can be used in a call to a "set priority"\r
+ * function. */\r
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07\r
+\r
+/* The highest interrupt priority that can be used by any interrupt service\r
+ * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT\r
+ * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A\r
+ * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */\r
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\r
+\r
+/* Interrupt priorities used by the kernel port layer itself. These are generic\r
+ * to all Cortex-M ports, and do not rely on any particular library functions. */\r
+#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\r
+ * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\r
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) )\r
+\r
+/* The #ifdef guards against the file being included from IAR assembly files. */\r
+#ifndef __IASMARM__\r
+\r
+ /* Constants related to the generation of run time stats. */\r
+ #define configGENERATE_RUN_TIME_STATS 0\r
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\r
+ #define portGET_RUN_TIME_COUNTER_VALUE() 0\r
+ #define configTICK_RATE_HZ ( ( TickType_t ) 100 )\r
+\r
+#endif /* __IASMARM__ */\r
+\r
+/* Enable static allocation. */\r
+#define configSUPPORT_STATIC_ALLOCATION 1\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
--- /dev/null
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+<peripheralInstance derived_from="I2S0" id="I2S6" location="0x40097000"/> \r
+<peripheralInstance derived_from="I2S0" id="I2S7" location="0x40098000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI0" location="0x40086000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI1" location="0x40087000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI2" location="0x40088000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI3" location="0x40089000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI4" location="0x4008A000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI5" location="0x40096000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI6" location="0x40097000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI7" location="0x40098000"/> \r
+<peripheralInstance derived_from="SPI0" id="SPI8" location="0x4009F000"/> \r
+<peripheralInstance derived_from="USART0" id="USART0" location="0x40086000"/> \r
+<peripheralInstance derived_from="USART0" id="USART1" location="0x40087000"/> \r
+<peripheralInstance derived_from="USART0" id="USART2" location="0x40088000"/> \r
+<peripheralInstance derived_from="USART0" id="USART3" location="0x40089000"/> \r
+<peripheralInstance derived_from="USART0" id="USART4" location="0x4008A000"/> \r
+<peripheralInstance derived_from="USART0" id="USART5" location="0x40096000"/> \r
+<peripheralInstance derived_from="USART0" id="USART6" location="0x40097000"/> \r
+<peripheralInstance derived_from="USART0" id="USART7" location="0x40098000"/> \r
+<peripheralInstance derived_from="MAILBOX" id="MAILBOX" location="0x4008B000"/> \r
+<peripheralInstance derived_from="GPIO" id="GPIO" location="0x4008C000"/> \r
+<peripheralInstance derived_from="GPIO" id="SECGPIO" location="0x400A8000"/> \r
+<peripheralInstance derived_from="USBHSD" id="USBHSD" location="0x40094000"/> \r
+<peripheralInstance derived_from="CRC-ENGINE" id="CRC-ENGINE" location="0x40095000"/> \r
+<peripheralInstance derived_from="SDIF" id="SDIF" location="0x4009B000"/> \r
+<peripheralInstance derived_from="DGBMAILBOX" id="DGBMAILBOX" location="0x4009C000"/> \r
+<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400A0000"/> \r
+<peripheralInstance derived_from="USBFSH" id="USBFSH" location="0x400A2000"/> \r
+<peripheralInstance derived_from="USBHSH" id="USBHSH" location="0x400A3000"/> \r
+<peripheralInstance derived_from="HASHCRYPT" id="HASHCRYPT" location="0x400A4000"/> \r
+<peripheralInstance derived_from="CASPER" id="CASPER" location="0x400A5000"/> \r
+<peripheralInstance derived_from="POWERQUAD" id="POWERQUAD" location="0x400A6000"/> \r
+<peripheralInstance derived_from="AHB-SECURE-CTRL" id="AHB-SECURE-CTRL" location="0x400AC000"/> \r
+</chip> \r
+<processor> \r
+<name gcc_name="cortex-m33">Cortex-M33</name> \r
+<family>Cortex-M</family> \r
+</processor> \r
+<processor> \r
+<name gcc_name="cortex-m33-nodsp">Cortex-M33 (No DSP)</name> \r
+<family>Cortex-M</family> \r
+</processor> \r
+<link href="LPC55S69_cm33_core0_internal_peripheral.xml" show="embed" type="simple"/> \r
+</info> \r
+</infoList> \r
+</TargetConfig></projectStorage>\r
+ </storageModule>\r
+ <storageModule moduleId="refreshScope" versionNumber="2">\r
+ <configuration configurationName="Debug">\r
+ <resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo_ns"/>\r
+ </configuration>\r
+ <configuration configurationName="Release">\r
+ <resource resourceType="PROJECT" workspacePath="/FreeRTOSDemo_ns"/>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>FreeRTOSDemo_ns</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Config</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-1-PROJECT_LOC/Config</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demos</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>NXP_Code</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-3-PROJECT_LOC/NXP_Code</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>User</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demos/mpu_demo.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/mpu_demo/mpu_demo.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demos/mpu_demo.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/mpu_demo/mpu_demo.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demos/tz_demo.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/tz_demo/tz_demo.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Demos/tz_demo.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/tz_demo/tz_demo.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>User/main_ns.c</name>\r
+ <type>1</type>\r
+ <locationURI>PROJECT_LOC/main_ns.c</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <filteredResources>\r
+ <filter>\r
+ <id>1557021723682</id>\r
+ <name></name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-*.c</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1557021723695</id>\r
+ <name></name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-*.h</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1554600764705</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-GCC</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1554600764705</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-MemMang</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1554600764721</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-*.txt</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1554600764721</id>\r
+ <name>FreeRTOS/portable</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-Common</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1553579192808</id>\r
+ <name>FreeRTOS/portable/GCC</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-ARM_CM33</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1553579168285</id>\r
+ <name>FreeRTOS/portable/MemMang</name>\r
+ <type>5</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-heap_4.c</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1553579213167</id>\r
+ <name>FreeRTOS/portable/GCC/ARM_CM33</name>\r
+ <type>9</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-non_secure</arguments>\r
+ </matcher>\r
+ </filter>\r
+ </filteredResources>\r
+</projectDescription>\r
--- /dev/null
+GROUP (\r
+ "libgcc.a"\r
+ "libc_nano.a"\r
+ "libm.a"\r
+ "libcr_newlib_semihost.a"\r
+)\r
+\r
+MEMORY\r
+{\r
+ /* Define each memory region. */\r
+ PROGRAM_FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 0x72000 /* 456K bytes (alias Flash). */\r
+ Ram0 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x2b000 /* 172K bytes (alias RAM). */\r
+}\r
+\r
+/* Define a symbol for the top of each memory region. */\r
+__base_PROGRAM_FLASH = 0x00010000; /* PROGRAM_FLASH. */\r
+__base_Flash = 0x00010000; /* Flash. */\r
+__top_PROGRAM_FLASH = 0x00010000 + 0x72000; /* 456K bytes. */\r
+__top_Flash = 0x00010000 + 0x72000; /* 456K bytes. */\r
+\r
+__base_Ram0 = 0x20008000; /* Ram0. */\r
+__base_RAM = 0x20008000; /* RAM. */\r
+__top_Ram0 = 0x20008000 + 0x2b000; /* 172K bytes. */\r
+__top_RAM = 0x20008000 + 0x2b000; /* 172K bytes. */\r
+\r
+/* Entry point. */\r
+ENTRY(ResetISR)\r
+\r
+SECTIONS\r
+{\r
+ /* Vector Table Section. */\r
+ .text : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ __vectors_start__ = ABSOLUTE(.);\r
+ KEEP(*(.isr_vector))\r
+\r
+ /* Global Section Table. */\r
+ . = ALIGN(4);\r
+ __section_table_start = .;\r
+\r
+ __data_section_table = .;\r
+ LONG(LOADADDR(.data));\r
+ LONG( ADDR(.data));\r
+ LONG( SIZEOF(.data));\r
+ __data_section_table_end = .;\r
+\r
+ __bss_section_table = .;\r
+ LONG( ADDR(.bss));\r
+ LONG( SIZEOF(.bss));\r
+ __bss_section_table_end = .;\r
+\r
+ __section_table_end = .;\r
+ /* End of Global Section Table. */\r
+\r
+ *(.after_vectors*)\r
+ } > PROGRAM_FLASH\r
+\r
+ /* Privileged functions - Section needs to be 32 byte aligned to satisfy MPU requirements. */\r
+ .privileged_functions : ALIGN(32)\r
+ {\r
+ . = ALIGN(32);\r
+ __privileged_functions_start__ = .;\r
+ *(privileged_functions)\r
+ . = ALIGN(32);\r
+ /* End address must be the last address in the region, therefore, -1. */\r
+ __privileged_functions_end__ = . - 1;\r
+ } > PROGRAM_FLASH\r
+\r
+ /* FreeRTOS System calls - Section needs to be 32 byte aligned to satisfy MPU requirements. */\r
+ .freertos_system_calls : ALIGN(32)\r
+ {\r
+ . = ALIGN(32);\r
+ __syscalls_flash_start__ = .;\r
+ *(freertos_system_calls)\r
+ . = ALIGN(32);\r
+ /* End address must be the last address in the region, therefore, -1. */\r
+ __syscalls_flash_end__ = . - 1;\r
+ } > PROGRAM_FLASH\r
+\r
+ /* Main Text Section - Section needs to be 32 byte aligned to satisfy MPU requirements. */\r
+ .text : ALIGN(32)\r
+ {\r
+ . = ALIGN(32);\r
+ __unprivileged_flash_start__ = .;\r
+ *(.text*)\r
+ *(.rodata .rodata.* .constdata .constdata.*)\r
+ . = ALIGN(32);\r
+ /* End address must be the last address in the region, therefore, -1. */\r
+ __unprivileged_flash_end__ = . - 1;\r
+ } > PROGRAM_FLASH\r
+\r
+ /* For exception handling/unwind - some Newlib functions (in common\r
+ * with C++ and StdC++) use this. */\r
+ .ARM.extab : ALIGN(4)\r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > PROGRAM_FLASH\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx : ALIGN(4)\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > PROGRAM_FLASH\r
+ __exidx_end = .;\r
+\r
+ /* Text Section End. */\r
+ _etext = .;\r
+\r
+ /* Uninit Reserved Section. */\r
+ .uninit_RESERVED : ALIGN(4)\r
+ {\r
+ KEEP(*(.bss.$RESERVED*))\r
+ . = ALIGN(4);\r
+ _end_uninit_RESERVED = .;\r
+ } > Ram0\r
+\r
+ /* Main Data section (Ram0). */\r
+ .data : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ _data = .;\r
+\r
+ /* Privileged data - It needs to be 32 byte aligned to satisfy MPU requirements. */\r
+ . = ALIGN(32);\r
+ __privileged_sram_start__ = .;\r
+ *(privileged_data);\r
+ . = ALIGN(32);\r
+ /* End address must be the last address in the region, therefore, -1. */\r
+ __privileged_sram_end__ = . - 1;\r
+\r
+ *(vtable)\r
+ *(.ramfunc*)\r
+ *(.data*)\r
+ _edata = .;\r
+ } > Ram0 AT>PROGRAM_FLASH\r
+\r
+ /* Main BSS Section. */\r
+ .bss : ALIGN(4)\r
+ {\r
+ _bss = .;\r
+ *(.bss*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = .;\r
+ PROVIDE(end = .);\r
+ } > Ram0\r
+\r
+ /* Default Noinit Section. */\r
+ .noinit (NOLOAD) : ALIGN(4)\r
+ {\r
+ _noinit = .;\r
+ *(.noinit*)\r
+ . = ALIGN(4);\r
+ _end_noinit = .;\r
+ } > Ram0\r
+\r
+ /* Reserve space and place heap in memory map. */\r
+ _HeapSize = 0x1000;\r
+ .heap : ALIGN(4)\r
+ {\r
+ _pvHeapStart = .;\r
+ . += _HeapSize;\r
+ . = ALIGN(4);\r
+ _pvHeapLimit = .;\r
+ } > Ram0\r
+\r
+ /* Reserve space for stack in memory. */\r
+ _StackSize = 0x1000;\r
+ .heap2stackfill :\r
+ {\r
+ . += _StackSize;\r
+ } > Ram0\r
+\r
+ /* Place actual stack in memory map. */\r
+ .stack ORIGIN(Ram0) + LENGTH(Ram0) - _StackSize - 0 : ALIGN(4)\r
+ {\r
+ _vStackBase = .;\r
+ . = ALIGN(4);\r
+ _vStackTop = . + _StackSize;\r
+ } > Ram0\r
+\r
+ /* Create checksum value (used in startup). */\r
+ PROVIDE(__valid_user_code_checksum = 0 -\r
+ (_vStackTop\r
+ + (ResetISR + 1)\r
+ + (NMI_Handler + 1)\r
+ + (HardFault_Handler + 1)\r
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined. */\r
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined. */\r
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined. */\r
+ ) );\r
+\r
+ /* Provide basic symbols giving location and size of main text block,\r
+ * including initial values of RW data sections. Note that these will need\r
+ * extending to give a complete picture with complex images\r
+ * (e.g multiple Flash banks). */\r
+ _image_start = LOADADDR(.text);\r
+ _image_end = LOADADDR(.data) + SIZEOF(.data);\r
+ _image_size = _image_end - _image_start;\r
+}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS include. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Device includes. */\r
+#include "fsl_device_registers.h"\r
+#include "fsl_debug_console.h"\r
+#include "pin_mux.h"\r
+#include "board.h"\r
+#include "clock_config.h"\r
+\r
+/* Demo includes. */\r
+#include "tz_demo.h"\r
+#include "mpu_demo.h"\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Create all demo tasks.\r
+ */\r
+static void prvCreateTasks( void );\r
+\r
+/**\r
+ * @brief Application-specific implementation of the SystemInit() weak\r
+ * function.\r
+ */\r
+void SystemInit( void );\r
+\r
+/**\r
+ * @brief The mem fault handler.\r
+ *\r
+ * It calls a function called vHandleMemoryFault.\r
+ */\r
+void MemManage_Handler( void ) __attribute__ ( ( naked ) );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvCreateTasks( void )\r
+{\r
+ /* Create tasks for the MPU Demo. */\r
+ vStartMPUDemo();\r
+\r
+ /* Create tasks for the TZ Demo. */\r
+ vStartTZDemo();\r
+\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SystemInit( void )\r
+{\r
+ /* Nothing needs to be initialized for Non-Secure project. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Stack overflow hook. */\r
+void vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName )\r
+{\r
+ /* Force an assert. */\r
+ configASSERT( pcTaskName == 0 );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Non-Secure main. */\r
+int main( void )\r
+{\r
+ /* Create tasks. */\r
+ prvCreateTasks();\r
+\r
+ /* Start scheduler. */\r
+ vTaskStartScheduler();\r
+\r
+ /* Should not reach here as the scheduler is already started. */\r
+ for( ; ; )\r
+ {\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an\r
+ * implementation of vApplicationGetIdleTaskMemory() to provide the memory that\r
+ * is used by the Idle task. */\r
+void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,\r
+ StackType_t ** ppxIdleTaskStackBuffer,\r
+ uint32_t * pulIdleTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Idle task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xIdleTaskTCB;\r
+ static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Idle\r
+ * task's state will be stored. */\r
+ *ppxIdleTaskTCBBuffer = &xIdleTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Idle task's stack. */\r
+ *ppxIdleTaskStackBuffer = uxIdleTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configMINIMAL_STACK_SIZE is specified in words, not bytes. */\r
+ *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the\r
+ * application must provide an implementation of vApplicationGetTimerTaskMemory()\r
+ * to provide the memory that is used by the Timer service task. */\r
+void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,\r
+ StackType_t ** ppxTimerTaskStackBuffer,\r
+ uint32_t * pulTimerTaskStackSize )\r
+{\r
+ /* If the buffers to be provided to the Timer task are declared inside this\r
+ * function then they must be declared static - otherwise they will be\r
+ * allocated on the stack and so not exists after this function exits. */\r
+ static StaticTask_t xTimerTaskTCB;\r
+ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ] __attribute__( ( aligned( 32 ) ) );\r
+\r
+ /* Pass out a pointer to the StaticTask_t structure in which the Timer\r
+ * task's state will be stored. */\r
+ *ppxTimerTaskTCBBuffer = &xTimerTaskTCB;\r
+\r
+ /* Pass out the array that will be used as the Timer task's stack. */\r
+ *ppxTimerTaskStackBuffer = uxTimerTaskStack;\r
+\r
+ /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.\r
+ * Note that, as the array is necessarily of type StackType_t,\r
+ * configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */\r
+ *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void MemManage_Handler( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ " tst lr, #4 \n"\r
+ " ite eq \n"\r
+ " mrseq r0, msp \n"\r
+ " mrsne r0, psp \n"\r
+ " ldr r1, handler_address_const \n"\r
+ " bx r1 \n"\r
+ " \n"\r
+ " handler_address_const: .word vHandleMemoryFault \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
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--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>FreeRTOSDemo_s</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Config</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-1-PROJECT_LOC/Config</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>NSCFunctions</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>NXP_Code</name>\r
+ <type>2</type>\r
+ <locationURI>PARENT-3-PROJECT_LOC/NXP_Code</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureContext</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureHeap</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureInit</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>User</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>NSCFunctions/nsc_functions.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/tz_demo/nsc_functions.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>NSCFunctions/nsc_functions.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-4-PROJECT_LOC/Common/ARMv8M/tz_demo/nsc_functions.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureContext/secure_context.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_context.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureContext/secure_context.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_context.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureContext/secure_context_port.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureContext/secure_port_macros.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureHeap/secure_heap.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_heap.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureHeap/secure_heap.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_heap.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureInit/secure_init.c</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_init.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>SecureInit/secure_init.h</name>\r
+ <type>1</type>\r
+ <locationURI>PARENT-5-PROJECT_LOC/Source/portable/GCC/ARM_CM33/secure/secure_init.h</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>User/main_s.c</name>\r
+ <type>1</type>\r
+ <locationURI>PROJECT_LOC/main_s.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>User/tzm_config.c</name>\r
+ <type>1</type>\r
+ <locationURI>PROJECT_LOC/tzm_config.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>User/tzm_config.h</name>\r
+ <type>1</type>\r
+ <locationURI>PROJECT_LOC/tzm_config.h</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <filteredResources>\r
+ <filter>\r
+ <id>1557015461042</id>\r
+ <name></name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-*.c</arguments>\r
+ </matcher>\r
+ </filter>\r
+ <filter>\r
+ <id>1557015461050</id>\r
+ <name></name>\r
+ <type>6</type>\r
+ <matcher>\r
+ <id>org.eclipse.ui.ide.multiFilter</id>\r
+ <arguments>1.0-name-matches-false-false-*.h</arguments>\r
+ </matcher>\r
+ </filter>\r
+ </filteredResources>\r
+</projectDescription>\r
--- /dev/null
+GROUP (\r
+ "libgcc.a"\r
+ "libc_nano.a"\r
+ "libm.a"\r
+ "libcr_newlib_semihost.a"\r
+)\r
+\r
+MEMORY\r
+{\r
+ /* Define each memory region. */\r
+ PROGRAM_FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0xfe00 /* 63.5K bytes (alias Flash). */\r
+ veneer_table (rx) : ORIGIN = 0x1000fe00, LENGTH = 0x200 /* 0.5K bytes (alias Flash2). */\r
+ Ram0 (rwx) : ORIGIN = 0x30000000, LENGTH = 0x8000 /* 32K bytes (alias RAM). */\r
+}\r
+\r
+/* Define a symbol for the top of each memory region. */\r
+__base_PROGRAM_FLASH = 0x10000000; /* PROGRAM_FLASH. */\r
+__base_Flash = 0x10000000; /* Flash. */\r
+__top_PROGRAM_FLASH = 0x10000000 + 0xfe00; /* 63.5K bytes */\r
+__top_Flash = 0x10000000 + 0xfe00; /* 63.5K bytes */\r
+\r
+__base_veneer_table = 0x1000fe00; /* veneer_table. */\r
+__base_Flash2 = 0x1000fe00; /* Flash2. */\r
+__top_veneer_table = 0x1000fe00 + 0x200; /* 0.5K bytes. */\r
+__top_Flash2 = 0x1000fe00 + 0x200; /* 0.5K bytes. */\r
+\r
+__base_Ram0 = 0x30000000; /* Ram0. */\r
+__base_RAM = 0x30000000; /* RAM. */\r
+__top_Ram0 = 0x30000000 + 0x8000; /* 32K bytes. */\r
+__top_RAM = 0x30000000 + 0x8000; /* 32K bytes. */\r
+\r
+/* Entry point. */\r
+ENTRY(ResetISR)\r
+\r
+SECTIONS\r
+{\r
+ /* Veneer Table Section (Non-Secure Callable). */\r
+ .text_Flash2 : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ *(.text_Flash2*) /* For compatibility with previous releases. */\r
+ *(.text_veneer_table*) /* For compatibility with previous releases. */\r
+ *(.text.$Flash2*)\r
+ *(.text.$veneer_table*)\r
+ *(.rodata.$Flash2*)\r
+ *(.rodata.$veneer_table*)\r
+ } > veneer_table\r
+\r
+ /* Vector Table Section. */\r
+ .text : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ __vectors_start__ = ABSOLUTE(.);\r
+ KEEP(*(.isr_vector))\r
+\r
+ /* Global Section Table. */\r
+ . = ALIGN(4);\r
+ __section_table_start = .;\r
+\r
+ __data_section_table = .;\r
+ LONG(LOADADDR(.data));\r
+ LONG( ADDR(.data));\r
+ LONG( SIZEOF(.data));\r
+ __data_section_table_end = .;\r
+\r
+ __bss_section_table = .;\r
+ LONG( ADDR(.bss));\r
+ LONG( SIZEOF(.bss));\r
+ __bss_section_table_end = .;\r
+\r
+ __section_table_end = .;\r
+ /* End of Global Section Table. */\r
+\r
+ *(.after_vectors*)\r
+ } > PROGRAM_FLASH\r
+\r
+ /* Main Text Section. */\r
+ .text : ALIGN(4)\r
+ {\r
+ *(.text*)\r
+ *(.rodata .rodata.* .constdata .constdata.*)\r
+ . = ALIGN(4);\r
+ } > PROGRAM_FLASH\r
+\r
+ /* For exception handling/unwind - some Newlib functions (in common\r
+ * with C++ and STDC++) use this. */\r
+ .ARM.extab : ALIGN(4)\r
+ {\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ } > PROGRAM_FLASH\r
+\r
+ __exidx_start = .;\r
+ .ARM.exidx : ALIGN(4)\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > PROGRAM_FLASH\r
+ __exidx_end = .;\r
+\r
+ /* TrustZone Secure Gateway Stubs Section. */\r
+ .gnu.sgstubs : ALIGN (32)\r
+ {\r
+ . = ALIGN(32);\r
+ _start_sg = .;\r
+ *(.gnu.sgstubs*)\r
+ . = ALIGN(32);\r
+ _end_sg = .;\r
+ } > PROGRAM_FLASH\r
+\r
+ /* Text Section End. */\r
+ _etext = .;\r
+\r
+ /* Uninit Reserved Section. */\r
+ .uninit_RESERVED : ALIGN(4)\r
+ {\r
+ KEEP(*(.bss.$RESERVED*))\r
+ . = ALIGN(4);\r
+ _end_uninit_RESERVED = .;\r
+ } > Ram0\r
+\r
+ /* Main Data section (Ram0). */\r
+ .data : ALIGN(4)\r
+ {\r
+ FILL(0xff)\r
+ _data = .;\r
+ *(vtable)\r
+ *(.ramfunc*)\r
+ *(.data*)\r
+ . = ALIGN(4);\r
+ _edata = .;\r
+ } > Ram0 AT>PROGRAM_FLASH\r
+\r
+ /* Main BSS Section. */\r
+ .bss : ALIGN(4)\r
+ {\r
+ _bss = .;\r
+ *(.bss*)\r
+ *(COMMON)\r
+ . = ALIGN(4);\r
+ _ebss = .;\r
+ PROVIDE(end = .);\r
+ } > Ram0\r
+\r
+ /* Default Noinit Section. */\r
+ .noinit (NOLOAD) : ALIGN(4)\r
+ {\r
+ _noinit = .;\r
+ *(.noinit*)\r
+ . = ALIGN(4);\r
+ _end_noinit = .;\r
+ } > Ram0\r
+\r
+ /* Reserve space and place heap in memory map. */\r
+ _HeapSize = 0x800;\r
+ .heap : ALIGN(4)\r
+ {\r
+ _pvHeapStart = .;\r
+ . += _HeapSize;\r
+ . = ALIGN(4);\r
+ _pvHeapLimit = .;\r
+ } > Ram0\r
+\r
+ /* Reserve space for stack in memory. */\r
+ _StackSize = 0x800;\r
+ .heap2stackfill :\r
+ {\r
+ . += _StackSize;\r
+ } > Ram0\r
+\r
+ /* Place actual stack in memory map. */\r
+ .stack ORIGIN(Ram0) + LENGTH(Ram0) - _StackSize - 0 : ALIGN(4)\r
+ {\r
+ _vStackBase = .;\r
+ . = ALIGN(4);\r
+ _vStackTop = . + _StackSize;\r
+ } > Ram0\r
+\r
+ /* Create checksum value (used in startup). */\r
+ PROVIDE(__valid_user_code_checksum = 0 -\r
+ (_vStackTop\r
+ + (ResetISR + 1)\r
+ + (NMI_Handler + 1)\r
+ + (HardFault_Handler + 1)\r
+ + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined. */\r
+ + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined. */\r
+ + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined. */\r
+ ) );\r
+\r
+ /* Provide basic symbols giving location and size of main text block,\r
+ * including initial values of RW data sections. Note that these will need\r
+ * extending to give a complete picture with complex images\r
+ * (e.g multiple Flash banks). */\r
+ _image_start = LOADADDR(.text);\r
+ _image_end = LOADADDR(.data) + SIZEOF(.data);\r
+ _image_size = _image_end - _image_start;\r
+}\r
--- /dev/null
+/*\r
+ * FreeRTOS Kernel V10.2.0\r
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.\r
+ *\r
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
+ * this software and associated documentation files (the "Software"), to deal in\r
+ * the Software without restriction, including without limitation the rights to\r
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
+ * the Software, and to permit persons to whom the Software is furnished to do so,\r
+ * subject to the following conditions:\r
+ *\r
+ * The above copyright notice and this permission notice shall be included in all\r
+ * copies or substantial portions of the Software.\r
+ *\r
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
+ *\r
+ * http://www.FreeRTOS.org\r
+ * http://aws.amazon.com/freertos\r
+ *\r
+ * 1 tab == 4 spaces!\r
+ */\r
+\r
+/* FreeRTOS includes. */\r
+#include "secure_port_macros.h"\r
+\r
+/* Device includes. */\r
+#include "fsl_device_registers.h"\r
+#include "fsl_debug_console.h"\r
+#include "arm_cmse.h"\r
+#include "board.h"\r
+#include "tzm_config.h"\r
+#include "pin_mux.h"\r
+#include "clock_config.h"\r
+\r
+#if ( __ARM_FEATURE_CMSE & 1 ) == 0\r
+ #error "Need ARMv8-M security extensions"\r
+#elif ( __ARM_FEATURE_CMSE & 2 ) == 0\r
+ #error "Compile with --cmse"\r
+#endif\r
+\r
+/* Start address of non-secure application. */\r
+#define mainNONSECURE_APP_START_ADDRESS ( 0x00010000UL )\r
+\r
+/* typedef for non-secure Reset Handler. */\r
+typedef void ( *NonSecureResetHandler_t ) ( void ) __attribute__( ( cmse_nonsecure_call ) );\r
+/*-----------------------------------------------------------*/\r
+\r
+/**\r
+ * @brief Boots into the non-secure code.\r
+ *\r
+ * @param[in] ulNonSecureStartAddress Start address of the non-secure application.\r
+ */\r
+static void prvBootNonSecure( uint32_t ulNonSecureStartAddress );\r
+\r
+/**\r
+ * @brief Application-specific implementation of the SystemInitHook() weak\r
+ * function.\r
+ */\r
+void SystemInitHook( void );\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvBootNonSecure( uint32_t ulNonSecureStartAddress )\r
+{\r
+ NonSecureResetHandler_t pxNonSecureResetHandler;\r
+\r
+ /* Setup the non-secure vector table. */\r
+ SCB_NS->VTOR = ulNonSecureStartAddress;\r
+\r
+ /* Main Stack Pointer value for the non-secure side is the first entry in\r
+ * the non-secure vector table. Read the first entry and assign the same to\r
+ * the non-secure main stack pointer(MSP_NS). */\r
+ secureportSET_MSP_NS( *( ( uint32_t * )( ulNonSecureStartAddress ) ) );\r
+\r
+ /* Reset Handler for the non-secure side is the second entry in the\r
+ * non-secure vector table. Read the second entry to get the non-secure\r
+ * Reset Handler. */\r
+ pxNonSecureResetHandler = ( NonSecureResetHandler_t )( * ( ( uint32_t * ) ( ( ulNonSecureStartAddress ) + 4U ) ) );\r
+\r
+ /* Start non-secure state software application by jumping to the non-secure\r
+ * Reset Handler. */\r
+ pxNonSecureResetHandler();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void SystemInitHook( void )\r
+{\r
+ /* Set CP10 and CP11 full access from Non-Secure code. */\r
+ SCB_NS->CPACR |= ( ( 3UL << 10 * 2 ) | ( 3UL << 11 * 2 ) );\r
+\r
+ /* The TrustZone should be configured as early as possible after RESET.\r
+ * Therefore it is called from SystemInit() during startup. The\r
+ * SystemInitHook() weak function overloading is used for this purpose.\r
+ */\r
+ BOARD_InitTrustZone();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* Secure main(). */\r
+int main(void)\r
+{\r
+ PRINTF( "Booting Secure World.\r\n" );\r
+\r
+ /* Attach main clock divide to FLEXCOMM0 (debug console). */\r
+ CLOCK_AttachClk( BOARD_DEBUG_UART_CLK_ATTACH );\r
+\r
+ /* Init board hardware. */\r
+ BOARD_InitPins();\r
+ BOARD_BootClockFROHF96M();\r
+ BOARD_InitDebugConsole();\r
+\r
+ /* Boot the non-secure code. */\r
+ PRINTF( "Booting Non-Secure World.\r\n" );\r
+ prvBootNonSecure( mainNONSECURE_APP_START_ADDRESS );\r
+\r
+ /* Non-secure software does not return, this code is not executed. */\r
+ for( ; ; )\r
+ {\r
+ /* Should not reach here. */\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+#include "fsl_common.h"\r
+#include "tzm_config.h"\r
+\r
+/*******************************************************************************\r
+ * Definitions\r
+ ******************************************************************************/\r
+#define CODE_FLASH_START_NS 0x00010000 \r
+#define CODE_FLASH_SIZE_NS 0x00072000\r
+#define CODE_FLASH_START_NSC 0x1000FE00\r
+#define CODE_FLASH_SIZE_NSC 0x200\r
+#define DATA_RAM_START_NS 0x20008000\r
+#define DATA_RAM_SIZE_NS 0x0002B000\r
+#define PERIPH_START_NS 0x40000000\r
+#define PERIPH_SIZE_NS 0x00100000\r
+\r
+/*******************************************************************************\r
+ * Variables\r
+ ******************************************************************************/\r
+#if defined(__MCUXPRESSO)\r
+extern unsigned char _start_sg[];\r
+#endif\r
+\r
+/*!\r
+ * @brief TrustZone initialization\r
+ *\r
+ * SAU Configuration\r
+ * This function configures 3 regions:\r
+ * 0x00010000 - 0x00081FFF - non-secure for code execution\r
+ * 0x1000FE00 - 0x1000FFFF - secure, non-secure callable for veneer table\r
+ * 0x20000000 - 0x20032FFF - non-secure for data\r
+ *\r
+ * AHB secure controller settings\r
+ * After RESET all memories and peripherals are set to user:non-secure access\r
+ * This function configures following memories and peripherals as secure:\r
+ * 0x00000000 - 0x0000FFFF - for secure code execution (this is physical FLASH address)\r
+ * 0x00008000 - 0x20032FFF - for secure data (this is physical RAM address)\r
+ *\r
+ * Secure peripherals: SYSCON, IOCON, FLEXCOMM0\r
+ * NOTE: This example configures necessary peripherals for this example. \r
+ * User should configure all peripherals, which shouldn't be accessible\r
+ * from normal world.\r
+*/\r
+void BOARD_InitTrustZone()\r
+{\r
+ /* Disable SAU */\r
+ SAU->CTRL = 0U;\r
+ \r
+ /* Configure SAU region 0 - Non-secure RAM for CODE execution*/\r
+ /* Set SAU region number */\r
+ SAU->RNR = 0;\r
+ /* Region base address */ \r
+ SAU->RBAR = (CODE_FLASH_START_NS & SAU_RBAR_BADDR_Msk);\r
+ /* Region end address */\r
+ SAU->RLAR = ((CODE_FLASH_START_NS + CODE_FLASH_SIZE_NS-1) & SAU_RLAR_LADDR_Msk) | \r
+ /* Region memory attribute index */\r
+ ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |\r
+ /* Enable region */\r
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); \r
+ \r
+ /* Configure SAU region 1 - Non-secure RAM for DATA */\r
+ /* Set SAU region number */\r
+ SAU->RNR = 1;\r
+ /* Region base address */ \r
+ SAU->RBAR = (DATA_RAM_START_NS & SAU_RBAR_BADDR_Msk);\r
+ /* Region end address */\r
+ SAU->RLAR = ((DATA_RAM_START_NS + DATA_RAM_SIZE_NS-1) & SAU_RLAR_LADDR_Msk) | \r
+ /* Region memory attribute index */\r
+ ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |\r
+ /* Enable region */\r
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); \r
+ \r
+ /* Configure SAU region 2 - Non-secure callable FLASH for CODE veneer table*/\r
+ /* Set SAU region number */\r
+ SAU->RNR = 2;\r
+ /* Region base address */ \r
+#if defined(__MCUXPRESSO)\r
+ SAU->RBAR = ((uint32_t)&_start_sg & SAU_RBAR_BADDR_Msk);\r
+#else\r
+ SAU->RBAR = (CODE_FLASH_START_NSC & SAU_RBAR_BADDR_Msk);\r
+#endif\r
+ /* Region end address */\r
+#if defined(__MCUXPRESSO)\r
+ SAU->RLAR = (((uint32_t)&_start_sg + CODE_FLASH_SIZE_NSC-1) & SAU_RLAR_LADDR_Msk) |\r
+ /* Region memory attribute index */\r
+ ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |\r
+ /* Enable region */\r
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);\r
+#else\r
+ SAU->RLAR = ((CODE_FLASH_START_NSC + CODE_FLASH_SIZE_NSC-1) & SAU_RLAR_LADDR_Msk) | \r
+ /* Region memory attribute index */\r
+ ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |\r
+ /* Enable region */\r
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); \r
+#endif\r
+\r
+ /* Configure SAU region 3 - Non-secure peripherals address space */\r
+ /* Set SAU region number */\r
+ SAU->RNR = 3;\r
+ /* Region base address */\r
+ SAU->RBAR = (PERIPH_START_NS & SAU_RBAR_BADDR_Msk);\r
+ /* Region end address */\r
+ SAU->RLAR = ((PERIPH_START_NS + PERIPH_SIZE_NS-1) & SAU_RLAR_LADDR_Msk) |\r
+ /* Region memory attribute index */\r
+ ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) |\r
+ /* Enable region */\r
+ ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk);\r
+\r
+ /* Force memory writes before continuing */\r
+ __DSB();\r
+ /* Flush and refill pipeline with updated permissions */\r
+ __ISB(); \r
+ /* Enable SAU */\r
+ SAU->CTRL = 1U; \r
+\r
+ /*Configuration of AHB Secure Controller \r
+ * Possible values for every memory sector or peripheral rule: \r
+ * 0b00 Non-secure and Non-priviledge user access allowed.\r
+ * 0b01 Non-secure and Privilege access allowed.\r
+ * 0b10 Secure and Non-priviledge user access allowed.\r
+ * 0b11 Secure and Priviledge user access allowed. */\r
+\r
+ /* FLASH memory configuration from 0x00000000 to 0x0000FFFF, sector size is 32kB */\r
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x00000033U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0x00000000U;\r
+ /* RAM memory configuration from 0x20000000 to 0x20007FFF, sector size is 4kB */\r
+ /* Memory settings for user non-secure access (0x0U) is mentioned for completness only. It is default RESET value. */ \r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] = 0x33333333U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] = 0x00000000U;\r
+ AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] = 0x00000000U;\r
+ \r
+ /* Set SYSCON and IOCON as secure */\r
+ AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(0x3U) |\r
+ AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(0x3U);\r
+\r
+ /* Set FLEXCOMM0 as secure */\r
+ AHB_SECURE_CTRL->SEC_CTRL_AHB0_0_SLAVE_RULE = AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(0x3U);\r
+\r
+ /* Enable AHB secure controller check and lock all rule registers */\r
+ AHB_SECURE_CTRL->MISC_CTRL_DP_REG = (AHB_SECURE_CTRL->MISC_CTRL_DP_REG & ~(AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK | \r
+ AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK)) |\r
+ AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(0x1U) |\r
+ AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(0x1U);\r
+}\r
--- /dev/null
+/*\r
+ * Copyright 2018 NXP\r
+ *\r
+ * SPDX-License-Identifier: BSD-3-Clause\r
+ */\r
+\r
+\r
+#ifndef _TZM_CONFIG_H_\r
+#define _TZM_CONFIG_H_\r
+\r
+/***********************************************************************************************************************\r
+ * Definitions\r
+ **********************************************************************************************************************/\r
+\r
+\r
+\r
+/***********************************************************************************************************************\r
+ * API\r
+ **********************************************************************************************************************/\r
+\r
+#if defined(__cplusplus)\r
+extern "C" {\r
+#endif\r
+\r
+/* Initialize TrustZone */\r
+void BOARD_InitTrustZone();\r
+\r
+#if defined(__cplusplus)\r
+}\r
+#endif\r
+\r
+/*!\r
+ * @}\r
+ */\r
+#endif /* _TZM_CONFIG_H_ */\r
+\r
+/***********************************************************************************************************************\r
+ * EOF\r
+ **********************************************************************************************************************/\r
projects / freertos / commitdiff