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+++ /dev/null
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+++ /dev/null
-BOARD=XMC1200_Boot_Kit\r
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-MCU=XMC1200-T038F0200\r
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+++ /dev/null
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+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-void vRegTest1Task( void ) __attribute__((naked));\r
-void vRegTest2Task( void ) __attribute__((naked));\r
-\r
-void vRegTest1Task( void )\r
-{\r
- __asm volatile\r
- (\r
- ".extern ulRegTest1LoopCounter \n"\r
- " \n"\r
- " /* Fill the core registers with known values. */ \n"\r
- " movs r1, #101 \n"\r
- " movs r2, #102 \n"\r
- " movs r3, #103 \n"\r
- " movs r4, #104 \n"\r
- " movs r5, #105 \n"\r
- " movs r6, #106 \n"\r
- " movs r7, #107 \n"\r
- " movs r0, #108 \n"\r
- " mov r8, r0 \n"\r
- " movs r0, #109 \n"\r
- " mov r9, r0 \n"\r
- " movs r0, #110 \n"\r
- " mov r10, r0 \n"\r
- " movs r0, #111 \n"\r
- " mov r11, r0 \n"\r
- " movs r0, #112 \n"\r
- " mov r12, r0 \n"\r
- " movs r0, #100 \n"\r
- " \n"\r
- "reg1_loop: \n"\r
- " \n"\r
- " cmp r0, #100 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r1, #101 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r2, #102 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r3, #103 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r4, #104 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r5, #105 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r6, #106 \n"\r
- " bne reg1_error_loop \n"\r
- " cmp r7, #107 \n"\r
- " bne reg1_error_loop \n"\r
- " movs r0, #108 \n"\r
- " cmp r8, r0 \n"\r
- " bne reg1_error_loop \n"\r
- " movs r0, #109 \n"\r
- " cmp r9, r0 \n"\r
- " bne reg1_error_loop \n"\r
- " movs r0, #110 \n"\r
- " cmp r10, r0 \n"\r
- " bne reg1_error_loop \n"\r
- " movs r0, #111 \n"\r
- " cmp r11, r0 \n"\r
- " bne reg1_error_loop \n"\r
- " movs r0, #112 \n"\r
- " cmp r12, r0 \n"\r
- " bne reg1_error_loop \n"\r
- " \n"\r
- " /* Everything passed, increment the loop counter. */ \n"\r
- " push { r1 } \n"\r
- " ldr r0, =ulRegTest1LoopCounter \n"\r
- " ldr r1, [r0] \n"\r
- " add r1, r1, #1 \n"\r
- " str r1, [r0] \n"\r
- " pop { r1 } \n"\r
- " \n"\r
- " /* Start again. */ \n"\r
- " movs r0, #100 \n"\r
- " b reg1_loop \n"\r
- " \n"\r
- "reg1_error_loop: \n"\r
- " /* If this line is hit then there was an error in a core register value. \n"\r
- " The loop ensures the loop counter stops incrementing. */ \n"\r
- " b reg1_error_loop \n"\r
- " nop \n"\r
- );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vRegTest2Task( void )\r
-{\r
- __asm volatile\r
- (\r
- ".extern ulRegTest2LoopCounter \n"\r
- " \n"\r
- " /* Fill the core registers with known values. */ \n"\r
- " movs r1, #1 \n"\r
- " movs r2, #2 \n"\r
- " movs r3, #3 \n"\r
- " movs r4, #4 \n"\r
- " movs r5, #5 \n"\r
- " movs r6, #6 \n"\r
- " movs r7, #7 \n"\r
- " movs r0, #8 \n"\r
- " movs r8, r0 \n"\r
- " movs r0, #9 \n"\r
- " mov r9, r0 \n"\r
- " movs r0, #10 \n"\r
- " mov r10, r0 \n"\r
- " movs r0, #11 \n"\r
- " mov r11, r0 \n"\r
- " movs r0, #12 \n"\r
- " mov r12, r0 \n"\r
- " movs r0, #10 \n"\r
- " \n"\r
- "reg2_loop: \n"\r
- " \n"\r
- " cmp r0, #10 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r1, #1 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r2, #2 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r3, #3 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r4, #4 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r5, #5 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r6, #6 \n"\r
- " bne reg2_error_loop \n"\r
- " cmp r7, #7 \n"\r
- " bne reg2_error_loop \n"\r
- " movs r0, #8 \n"\r
- " cmp r8, r0 \n"\r
- " bne reg2_error_loop \n"\r
- " movs r0, #9 \n"\r
- " cmp r9, r0 \n"\r
- " bne reg2_error_loop \n"\r
- " movs r0, #10 \n"\r
- " cmp r10, r0 \n"\r
- " bne reg2_error_loop \n"\r
- " movs r0, #11 \n"\r
- " cmp r11, r0 \n"\r
- " bne reg2_error_loop \n"\r
- " movs r0, #12 \n"\r
- " cmp r12, r0 \n"\r
- " bne reg2_error_loop \n"\r
- " \n"\r
- " /* Everything passed, increment the loop counter. */ \n"\r
- " push { r1 } \n"\r
- " ldr r0, =ulRegTest2LoopCounter \n"\r
- " ldr r1, [r0] \n"\r
- " add r1, r1, #1 \n"\r
- " str r1, [r0] \n"\r
- " pop { r1 } \n"\r
- " \n"\r
- " /* Start again. */ \n"\r
- " movs r0, #10 \n"\r
- " b reg2_loop \n"\r
- " \n"\r
- "reg2_error_loop: \n"\r
- " /* If this line is hit then there was an error in a core register value. \n"\r
- " The loop ensures the loop counter stops incrementing. */ \n"\r
- " b reg2_error_loop \n"\r
- " nop \n"\r
- );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/**
-*****************************************************************************
-**
-** File : startup_XMC1200.s
-**
-** Abstract : This assembler file contains interrupt vector and
-** startup code for ARM.
-**
-** Functions : Reset_Handler
-** Default_Handler
-** XMCVeneer code
-**
-** Target : Infineon $(DEVICE) Device
-**
-** Environment : Atollic TrueSTUDIO(R)
-**
-** Distribution: The file is distributed \93as is,\94 without any warranty
-** of any kind.
-**
-** (c)Copyright Atollic AB.
-** You may use this file as-is or modify it according to the needs of your
-** project. This file may only be built (assembled or compiled and linked)
-** using the Atollic TrueSTUDIO(R) product. The use of this file together
-** with other tools than Atollic TrueSTUDIO(R) is not permitted.
-**
-*****************************************************************************
-*/
-
-#ifdef DAVE_CE
-#include <Device_Data.h>
-#else
-#define CLKVAL1_SSW 0x80000000
-#define CLKVAL2_SSW 0x80000000
-#endif
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global Reset_Handler
-.global InterruptVector
-.global Default_Handler
-
-/* Linker script definitions */
-/* start address for the initialization values of the .data section */
-.word _sidata
-/* start address for the .data section */
-.word _sdata
-/* end address for the .data section */
-.word _edata
-/* start address for the .bss section */
-.word _sbss
-/* end address for the .bss section */
-.word _ebss
-
-.word VeneerLoadAddr
-.word VeneerStart
-.word VeneerSize
-
-
-/**
-**===========================================================================
-** Program - Reset_Handler
-** Abstract: This code gets called after reset.
-**===========================================================================
-*/
- .section .text.Reset_Handler,"ax", %progbits
- .type Reset_Handler, %function
-Reset_Handler:
- /* Set stack pointer */
- ldr r0, =_estack
- mov sp, r0
-
- /* Branch to SystemInit function */
- bl SystemInit
-
- /* Copy data initialization values */
- ldr r1,=_sidata
- ldr r2,=_sdata
- ldr r3,=_edata
- b cmpdata
-CopyLoop:
- ldr r0, [r1]
- str r0, [r2]
- adds r1, r1, #4
- adds r2, r2, #4
-cmpdata:
- cmp r2, r3
- blt CopyLoop
-
- /* Clear BSS section */
- movs r0, #0
- ldr r2,=_sbss
- ldr r3,=_ebss
- b cmpbss
-ClearLoop:
- str r0, [r2]
- adds r2, r2, #4
-cmpbss:
- cmp r2, r3
- blt ClearLoop
-
- /* VENEER COPY */
- /* R0 = Start address, R1 = Destination address, R2 = Size */
- ldr r0, =VeneerLoadAddr
- ldr r1, =VeneerStart
- ldr r2, =VeneerSize
-
-STARTVENEERCOPY:
- /* R2 contains byte count. Change it to word count. It is ensured in the
- linker script that the length is always word aligned.
- */
- lsrs r2,r2,#2 /* Divide by 4 to obtain word count */
- beq SKIPVENEERCOPY
-
- /* The proverbial loop from the schooldays */
-VENEERCOPYLOOP:
- ldr r3,[R0]
- str r3,[R1]
- subs r2,#1
- beq SKIPVENEERCOPY
- adds r0,#4
- adds r1,#4
- b VENEERCOPYLOOP
-
-SKIPVENEERCOPY:
- /* Update System Clock */
- ldr r0,=SystemCoreClockUpdate
- blx r0
-
- /* Call static constructors */
- bl __libc_init_array
-
- /* Branch to main */
- bl main
-
- /* If main returns, branch to Default_Handler. */
- b Default_Handler
-
- .size Reset_Handler, .-Reset_Handler
-
-/**
-**===========================================================================
-** Program - Default_Handler
-** Abstract: This code gets called when the processor receives an
-** unexpected interrupt.
-**===========================================================================
-*/
- .section .text.Default_Handler,"ax", %progbits
-Default_Handler:
- b Default_Handler
-
- .size Default_Handler, .-Default_Handler
-
-/**
-**===========================================================================
-** Interrupt vector table
-**===========================================================================
-*/
- .section .isr_vector,"a", %progbits
- .globl InterruptVector
- .type InterruptVector, %object
-
-InterruptVector:
- .word _estack /* 0 - Stack pointer */
- .word Reset_Handler /* 1 - Reset */
- .word NMI_Handler /* 2 - NMI */
- .word HardFault_Handler /* 3 - Hard fault */
- .word CLKVAL1_SSW /* Clock configuration value */
- .word CLKVAL2_SSW /* Clock gating configuration */
-
- .size InterruptVector, . - InterruptVector
-
-/**
-**===========================================================================
-** Weak interrupt handlers redirected to Default_Handler. These can be
-** overridden in user code.
-**===========================================================================
-*/
- .weak NMI_Handler
- .thumb_set NMI_Handler, Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler, Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler, Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler, Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler, Default_Handler
-
-/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
-
-/* IRQ Handlers */
- .weak SCU_0_IRQHandler
- .type SCU_0_IRQHandler, %function
-SCU_0_IRQHandler:
- B .
- .size SCU_0_IRQHandler, . - SCU_0_IRQHandler
-/* ======================================================================== */
- .weak SCU_1_IRQHandler
- .type SCU_1_IRQHandler, %function
-SCU_1_IRQHandler:
- B .
- .size SCU_1_IRQHandler, . - SCU_1_IRQHandler
-/* ======================================================================== */
- .weak SCU_2_IRQHandler
- .type SCU_2_IRQHandler, %function
-SCU_2_IRQHandler:
- B .
- .size SCU_2_IRQHandler, . - SCU_2_IRQHandler
-/* ======================================================================== */
- .weak ERU0_0_IRQHandler
- .type ERU0_0_IRQHandler, %function
-ERU0_0_IRQHandler:
- B .
- .size ERU0_0_IRQHandler, . - ERU0_0_IRQHandler
-/* ======================================================================== */
- .weak ERU0_1_IRQHandler
- .type ERU0_1_IRQHandler, %function
-ERU0_1_IRQHandler:
- B .
- .size ERU0_1_IRQHandler, . - ERU0_1_IRQHandler
-/* ======================================================================== */
- .weak ERU0_2_IRQHandler
- .type ERU0_2_IRQHandler, %function
-ERU0_2_IRQHandler:
- B .
- .size ERU0_2_IRQHandler, . - ERU0_2_IRQHandler
-/* ======================================================================== */
- .weak ERU0_3_IRQHandler
- .type ERU0_3_IRQHandler, %function
-ERU0_3_IRQHandler:
- B .
- .size ERU0_3_IRQHandler, . - ERU0_3_IRQHandler
-/* ======================================================================== */
- .weak MATH0_0_IRQHandler
- .type MATH0_0_IRQHandler, %function
-MATH0_0_IRQHandler:
- B .
- .size MATH0_0_IRQHandler, . - MATH0_0_IRQHandler
-/* ======================================================================== */
- .weak VADC0_C0_0_IRQHandler
- .type VADC0_C0_0_IRQHandler , %function
-VADC0_C0_0_IRQHandler:
- B .
- .size VADC0_C0_0_IRQHandler , . - VADC0_C0_0_IRQHandler
-/* ======================================================================== */
- .weak VADC0_C0_1_IRQHandler
- .type VADC0_C0_1_IRQHandler , %function
-VADC0_C0_1_IRQHandler:
- B .
- .size VADC0_C0_1_IRQHandler , . - VADC0_C0_1_IRQHandler
-/* ======================================================================== */
- .weak VADC0_G0_0_IRQHandler
- .type VADC0_G0_0_IRQHandler, %function
-VADC0_G0_0_IRQHandler:
- B .
- .size VADC0_G0_0_IRQHandler, . - VADC0_G0_0_IRQHandler
-/* ======================================================================== */
- .weak VADC0_G0_1_IRQHandler
- .type VADC0_G0_1_IRQHandler, %function
-VADC0_G0_1_IRQHandler:
- B .
- .size VADC0_G0_1_IRQHandler, . - VADC0_G0_1_IRQHandler
-/* ======================================================================== */
- .weak VADC0_G1_0_IRQHandler
- .type VADC0_G1_0_IRQHandler, %function
-VADC0_G1_0_IRQHandler:
- B .
- .size VADC0_G1_0_IRQHandler, . - VADC0_G1_0_IRQHandler
-/* ======================================================================== */
- .weak VADC0_G1_1_IRQHandler
- .type VADC0_G1_1_IRQHandler, %function
-VADC0_G1_1_IRQHandler:
- B .
- .size VADC0_G1_1_IRQHandler, . - VADC0_G1_1_IRQHandler
-/* ======================================================================== */
- .weak CCU40_0_IRQHandler
- .type CCU40_0_IRQHandler, %function
-CCU40_0_IRQHandler:
- B .
- .size CCU40_0_IRQHandler, . - CCU40_0_IRQHandler
-/* ======================================================================== */
- .weak CCU40_1_IRQHandler
- .type CCU40_1_IRQHandler, %function
-
-CCU40_1_IRQHandler:
- B .
- .size CCU40_1_IRQHandler, . - CCU40_1_IRQHandler
-/* ======================================================================== */
- .weak CCU40_2_IRQHandler
- .type CCU40_2_IRQHandler, %function
-CCU40_2_IRQHandler:
- B .
- .size CCU40_2_IRQHandler, . - CCU40_2_IRQHandler
-/* ======================================================================== */
- .weak CCU40_3_IRQHandler
- .type CCU40_3_IRQHandler, %function
-CCU40_3_IRQHandler:
- B .
- .size CCU40_3_IRQHandler, . - CCU40_3_IRQHandler
-/* ======================================================================== */
- .weak CCU80_0_IRQHandler
- .type CCU80_0_IRQHandler, %function
-CCU80_0_IRQHandler:
- B .
- .size CCU80_0_IRQHandler, . - CCU80_0_IRQHandler
-/* ======================================================================== */
- .weak CCU80_1_IRQHandler
- .type CCU80_1_IRQHandler, %function
-CCU80_1_IRQHandler:
- B .
- .size CCU80_1_IRQHandler, . - CCU80_1_IRQHandler
-/* ======================================================================== */
- .weak POSIF0_0_IRQHandler
- .type POSIF0_0_IRQHandler, %function
-
-POSIF0_0_IRQHandler:
- B .
- .size POSIF0_0_IRQHandler, . - POSIF0_0_IRQHandler
-/* ======================================================================== */
- .weak POSIF0_1_IRQHandler
- .type POSIF0_1_IRQHandler, %function
-POSIF0_1_IRQHandler:
- B .
- .size POSIF0_1_IRQHandler, . - POSIF0_1_IRQHandler
-/* ======================================================================== */
- .weak USIC0_0_IRQHandler
- .type USIC0_0_IRQHandler, %function
-USIC0_0_IRQHandler:
- B .
- .size USIC0_0_IRQHandler, . - USIC0_0_IRQHandler
-/* ======================================================================== */
- .weak USIC0_1_IRQHandler
- .type USIC0_1_IRQHandler, %function
-USIC0_1_IRQHandler:
- B .
- .size USIC0_1_IRQHandler, . - USIC0_1_IRQHandler
-/* ======================================================================== */
- .weak USIC0_2_IRQHandler
- .type USIC0_2_IRQHandler, %function
-USIC0_2_IRQHandler:
- B .
- .size USIC0_2_IRQHandler, . - USIC0_2_IRQHandler
-/* ======================================================================== */
- .weak USIC0_3_IRQHandler
- .type USIC0_3_IRQHandler, %function
-USIC0_3_IRQHandler:
- B .
- .size USIC0_3_IRQHandler, . - USIC0_3_IRQHandler
-/* ======================================================================== */
- .weak USIC0_4_IRQHandler
- .type USIC0_4_IRQHandler, %function
-USIC0_4_IRQHandler:
- B .
- .size USIC0_4_IRQHandler, . - USIC0_4_IRQHandler
-/* ======================================================================== */
- .weak USIC0_5_IRQHandler
- .type USIC0_5_IRQHandler, %function
-USIC0_5_IRQHandler:
- B .
- .size USIC0_5_IRQHandler, . - USIC0_5_IRQHandler
-/* ======================================================================== */
- .weak LEDTS0_0_IRQHandler
- .type LEDTS0_0_IRQHandler, %function
-LEDTS0_0_IRQHandler:
- B .
- .size LEDTS0_0_IRQHandler, . - LEDTS0_0_IRQHandler
-/* ======================================================================== */
- .weak LEDTS1_0_IRQHandler
- .type LEDTS1_0_IRQHandler, %function
-LEDTS1_0_IRQHandler:
- B .
- .size LEDTS1_0_IRQHandler, . - LEDTS1_0_IRQHandler
-/* ======================================================================== */
- .weak BCCU0_0_IRQHandler
- .type BCCU0_0_IRQHandler, %function
-BCCU0_0_IRQHandler:
- B .
- .size BCCU0_0_IRQHandler, . - BCCU0_0_IRQHandler
-/* ======================================================================== */
-/* ======================================================================== */
-
-/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
- .section ".XmcVeneerCode","ax",%progbits
-.globl HardFault_Veneer
-HardFault_Veneer:
- LDR R0, =HardFault_Handler
- MOV PC,R0
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
- .long 0
-
-/* ======================================================================== */
-.globl SVC_Veneer
-SVC_Veneer:
- LDR R0, =SVC_Handler
- MOV PC,R0
- .long 0
- .long 0
-/* ======================================================================== */
-.globl PendSV_Veneer
-PendSV_Veneer:
- LDR R0, =PendSV_Handler
- MOV PC,R0
-/* ======================================================================== */
-.globl SysTick_Veneer
-SysTick_Veneer:
- LDR R0, =SysTick_Handler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_0_Veneer
-SCU_0_Veneer:
- LDR R0, =SCU_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_1_Veneer
-SCU_1_Veneer:
- LDR R0, =SCU_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_2_Veneer
-SCU_2_Veneer:
- LDR R0, =SCU_2_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_3_Veneer
-SCU_3_Veneer:
- LDR R0, =ERU0_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_4_Veneer
-SCU_4_Veneer:
- LDR R0, =ERU0_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_5_Veneer
-SCU_5_Veneer:
- LDR R0, =ERU0_2_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_6_Veneer
-SCU_6_Veneer:
- LDR R0, =ERU0_3_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl SCU_7_Veneer
-SCU_7_Veneer:
- LDR R0, =MATH0_0_IRQHandler
- MOV PC,R0
- .long 0
-/* ======================================================================== */
-.globl VADC0_C0_0_Veneer
-VADC0_C0_0_Veneer:
- LDR R0, =VADC0_C0_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl VADC0_C0_1_Veneer
-VADC0_C0_1_Veneer:
- LDR R0, =VADC0_C0_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl VADC0_G0_0_Veneer
-VADC0_G0_0_Veneer:
- LDR R0, =VADC0_G0_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl VADC0_G0_1_Veneer
-VADC0_G0_1_Veneer:
- LDR R0, =VADC0_G0_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl VADC0_G1_0_Veneer
-VADC0_G1_0_Veneer:
- LDR R0, =VADC0_G1_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl VADC0_G1_1_Veneer
-VADC0_G1_1_Veneer:
- LDR R0, =VADC0_G1_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl CCU40_0_Veneer
-CCU40_0_Veneer:
- LDR R0, =CCU40_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl CCU40_1_Veneer
-CCU40_1_Veneer:
- LDR R0, =CCU40_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl CCU40_2_Veneer
-CCU40_2_Veneer:
- LDR R0, =CCU40_2_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl CCU40_3_Veneer
-CCU40_3_Veneer:
- LDR R0, =CCU40_3_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl CCU80_0_Veneer
-CCU80_0_Veneer:
- LDR R0, =CCU80_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl CCU80_1_Veneer
-CCU80_1_Veneer:
- LDR R0, =CCU80_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl POSIF0_0_Veneer
-POSIF0_0_Veneer:
- LDR R0, =POSIF0_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl POSIF0_1_Veneer
-POSIF0_1_Veneer:
- LDR R0, =POSIF0_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl USIC0_0_Veneer
-USIC0_0_Veneer:
- LDR R0, =USIC0_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl USIC0_1_Veneer
-USIC0_1_Veneer:
- LDR R0, =USIC0_1_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl USIC0_2_Veneer
-USIC0_2_Veneer:
- LDR R0, =USIC0_2_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl USIC0_3_Veneer
-USIC0_3_Veneer:
- LDR R0, =USIC0_3_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl USIC0_4_Veneer
-USIC0_4_Veneer:
- LDR R0, =USIC0_4_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl USIC0_5_Veneer
-USIC0_5_Veneer:
- LDR R0, =USIC0_5_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl LEDTS0_0_Veneer
-LEDTS0_0_Veneer:
- LDR R0, =LEDTS0_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
-.globl LEDTS1_0_Veneer
-LEDTS1_0_Veneer:
- LDR R0, =LEDTS1_0_IRQHandler
- MOV PC,R0
-/* ======================================================================== */
- .globl BCCU0_0_Veneer
-BCCU0_0_Veneer:
- LDR R0, =BCCU0_0_IRQHandler
- MOV PC,R0
-
-/* ======================================================================== */
-
-/* ===== Decision function queried by CMSIS startup for Clock tree setup === */
-/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
- tree setup.
-
- This decision routine defined here will always return TRUE.
-
- When overridden by a definition defined in DAVE code engine, this routine
- returns FALSE indicating that the code engine has performed the clock setup
-*/
- .section ".XmcStartup"
- .weak AllowClkInitByStartup
- .type AllowClkInitByStartup, %function
-AllowClkInitByStartup:
- MOVS R0,#1
- BX LR
- .size AllowClkInitByStartup, . - AllowClkInitByStartup
-
-/* ====== Definition of the default weak SystemInit_DAVE3 function =========
-If DAVE3 requires an extended SystemInit it will create its own version of
-SystemInit_DAVE3 which overrides this weak definition. Example includes
-setting up of external memory interfaces.
-*/
- .weak SystemInit_DAVE3
- .type SystemInit_DAVE3, %function
-SystemInit_DAVE3:
- NOP
- BX LR
- .size SystemInit_DAVE3, . - SystemInit_DAVE3
-
- .end
+++ /dev/null
-/*
-*****************************************************************************
-**
-** File : xmc1000_flash.ld
-**
-** Abstract : Linker script for XMC1200-T038F0200 Device with
-** 200KByte FLASH, 16KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Target : Infineon XMC1000 Microcontrollers
-**
-** Environment : Atollic TrueSTUDIO(R)
-**
-** Distribution: The file is distributed \93as is,\94 without any warranty
-** of any kind.
-**
-** (c)Copyright Atollic AB.
-** You may use this file as-is or modify it according to the needs of your
-** project. This file may only be built (assembled or compiled and linked)
-** using the Atollic TrueSTUDIO(R) product. The use of this file together
-** with other tools than Atollic TrueSTUDIO(R) is not permitted.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20004000; /* end of 16K RAM */
-
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0; /* required amount of heap */
-_Min_Stack_Size = 0x80; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x10001000, LENGTH = 200K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
- MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data goes into FLASH */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.XmcStartup);
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
- /* Constant data goes into FLASH */
- .rodata :
- {
- . = ALIGN(4);
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- . = ALIGN(4);
- } >FLASH
-
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
- .ARM : {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } >FLASH
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH
-
- . = ALIGN(4);
- eROData = . ;
-
- /* Initialize XMC Veneer interrupt code */
- VeneerLoadAddr = ABSOLUTE(eROData);
- .VENEER_Code ABSOLUTE(0x2000000C) :
- {
- VeneerStart = .;
- KEEP(*(.XmcVeneerCode)) /* Keep the VeneerCode */
- *(.XmcVeneerCode);
- . = ALIGN(4);
- VeneerEnd = .;
-
- } >RAM AT> FLASH
-
- VeneerSize = ABSOLUTE(VeneerEnd) - ABSOLUTE(VeneerStart);
-
- /* used by the startup to initialize data */
- _sidata = LOADADDR(.data);
-
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
- } >RAM AT> FLASH
-
- /* Uninitialized data section */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(4);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(4);
- } >RAM
-
- /* MEMORY_bank1 section, code must be located here explicitly */
- /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
- .memory_b1_text :
- {
- *(.mb1text) /* .mb1text sections (code) */
- *(.mb1text*) /* .mb1text* sections (code) */
- *(.mb1rodata) /* read-only data (constants) */
- *(.mb1rodata*)
- } >MEMORY_B1
-
- /* Remove information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-}
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm0.h\r
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#endif\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#ifndef __CORE_CM0_H_GENERIC\r
-#define __CORE_CM0_H_GENERIC\r
-\r
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/** \ingroup Cortex_M0\r
- @{\r
- */\r
-\r
-/* CMSIS CM0 definitions */\r
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-#endif\r
-\r
-#include <stdint.h> /* standard types definitions */\r
-#include <core_cmInstr.h> /* Core Instruction Access */\r
-#include <core_cmFunc.h> /* Core Function Access */\r
-\r
-#endif /* __CORE_CM0_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0_H_DEPENDANT\r
-#define __CORE_CM0_H_DEPENDANT\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM0_REV\r
- #define __CM0_REV 0x0000\r
- #warning "__CM0_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/*@} end of group Cortex_M0 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31];\r
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31];\r
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31];\r
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31];\r
- uint32_t RESERVED4[64];\r
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- uint32_t RESERVED0;\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED1;\r
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
- are only accessible over DAP and not via processor. Therefore\r
- they are not covered by the Cortex-M0 header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M0 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
-\r
-\r
-/** \brief Enable External Interrupt\r
-\r
- The function enables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
-}\r
-\r
-\r
-/** \brief Disable External Interrupt\r
-\r
- The function disables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
-}\r
-\r
-\r
-/** \brief Get Pending Interrupt\r
-\r
- The function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
-}\r
-\r
-\r
-/** \brief Set Pending Interrupt\r
-\r
- The function sets the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
-}\r
-\r
-\r
-/** \brief Clear Pending Interrupt\r
-\r
- The function clears the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-\r
-/** \brief Set Interrupt Priority\r
-\r
- The function sets the priority of an interrupt.\r
-\r
- \note The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
- else {\r
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
-}\r
-\r
-\r
-/** \brief Get Interrupt Priority\r
-\r
- The function reads the priority of an interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
-\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented\r
- priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
- else {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/** \brief System Reset\r
-\r
- The function initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts.\r
-\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
-\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#endif /* __CORE_CM0_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmFunc.h\r
- * @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CORE_CMFUNC_H\r
-#define __CORE_CMFUNC_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/** \brief Enable IRQ Interrupts\r
-\r
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable IRQ Interrupts\r
-\r
- This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- uint32_t result;\r
-\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-#endif /* __CORE_CMFUNC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmInstr.h\r
- * @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V3.20\r
- * @date 05. March 2013\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CORE_CMINSTR_H\r
-#define __CORE_CMINSTR_H\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-#define __ISB() __isb(0xF)\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __dsb(0xF)\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __dmb(0xF)\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __RBIT __rbit\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constrant "l"\r
- * Otherwise, use general registers, specified by constrant "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb");\r
-}\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb");\r
-}\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb");\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32 - op2)); \r
-}\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-#endif /* __CORE_CMINSTR_H */\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-\r
-#ifndef FREERTOS_CONFIG_H\r
-#define FREERTOS_CONFIG_H\r
-\r
-/*-----------------------------------------------------------\r
- * Application specific definitions.\r
- *\r
- * These definitions should be adjusted for your particular hardware and\r
- * application requirements.\r
- *\r
- * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
- * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
- *\r
- * See http://www.freertos.org/a00110.html.\r
- *----------------------------------------------------------*/\r
-\r
-/* Prevent C code being included by the IAR assembler. */\r
-#ifndef __IASMARM__\r
- #include <stdint.h>\r
- extern uint32_t SystemCoreClock;\r
-#endif\r
-\r
-#define configUSE_PREEMPTION 1\r
-#define configUSE_IDLE_HOOK 0\r
-#define configUSE_TICK_HOOK 0\r
-#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
-#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
-#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
-#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 )\r
-#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6000 ) )\r
-#define configMAX_TASK_NAME_LEN ( 5 )\r
-#define configUSE_TRACE_FACILITY 1\r
-#define configUSE_16_BIT_TICKS 0\r
-#define configIDLE_SHOULD_YIELD 1\r
-#define configUSE_MUTEXES 1\r
-#define configQUEUE_REGISTRY_SIZE 8\r
-#define configCHECK_FOR_STACK_OVERFLOW 2\r
-#define configUSE_RECURSIVE_MUTEXES 1\r
-#define configUSE_MALLOC_FAILED_HOOK 1\r
-#define configUSE_APPLICATION_TASK_TAG 0\r
-#define configUSE_COUNTING_SEMAPHORES 1\r
-#define configGENERATE_RUN_TIME_STATS 0\r
-\r
-/* Co-routine definitions. */\r
-#define configUSE_CO_ROUTINES 0\r
-#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
-\r
-/* Software timer definitions. */\r
-#define configUSE_TIMERS 1\r
-#define configTIMER_TASK_PRIORITY ( 2 )\r
-#define configTIMER_QUEUE_LENGTH 5\r
-#define configTIMER_TASK_STACK_DEPTH ( 80 )\r
-\r
-/* Set the following definitions to 1 to include the API function, or zero\r
-to exclude the API function. */\r
-#define INCLUDE_vTaskPrioritySet 1\r
-#define INCLUDE_uxTaskPriorityGet 1\r
-#define INCLUDE_vTaskDelete 1\r
-#define INCLUDE_vTaskCleanUpResources 1\r
-#define INCLUDE_vTaskSuspend 1\r
-#define INCLUDE_vTaskDelayUntil 1\r
-#define INCLUDE_vTaskDelay 1\r
-\r
-/* Normal assert() semantics without relying on the provision of an assert.h\r
-header file. */\r
-#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
-\r
-/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
-standard names - or at least those used in the unmodified vector table. */\r
-#define vPortSVCHandler SVC_Handler\r
-#define xPortPendSVHandler PendSV_Handler\r
-#define xPortSysTickHandler SysTick_Handler\r
-\r
-#endif /* FREERTOS_CONFIG_H */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
- RSEG CODE:CODE(2)\r
- thumb\r
-\r
-\r
- EXTERN ulRegTest1LoopCounter\r
- EXTERN ulRegTest2LoopCounter\r
-\r
- PUBLIC vRegTest1Task\r
- PUBLIC vRegTest2Task\r
-\r
-/*-----------------------------------------------------------*/\r
-vRegTest1Task\r
-\r
- /* Fill the core registers with known values. This is only done once. */\r
- movs r1, #101\r
- movs r2, #102\r
- movs r3, #103\r
- movs r4, #104\r
- movs r5, #105\r
- movs r6, #106\r
- movs r7, #107\r
- movs r0, #108\r
- mov r8, r0\r
- movs r0, #109\r
- mov r9, r0\r
- movs r0, #110\r
- mov r10, r0\r
- movs r0, #111\r
- mov r11, r0\r
- movs r0, #112\r
- mov r12, r0\r
- movs r0, #100\r
-\r
-reg1_loop\r
- /* Repeatedly check that each register still contains the value written to\r
- it when the task started. */\r
- cmp r0, #100\r
- bne reg1_error_loop\r
- cmp r1, #101\r
- bne reg1_error_loop\r
- cmp r2, #102\r
- bne reg1_error_loop\r
- cmp r3, #103\r
- bne reg1_error_loop\r
- cmp r4, #104\r
- bne reg1_error_loop\r
- cmp r5, #105\r
- bne reg1_error_loop\r
- cmp r6, #106\r
- bne reg1_error_loop\r
- cmp r7, #107\r
- bne reg1_error_loop\r
- movs r0, #108\r
- cmp r8, r0\r
- bne reg1_error_loop\r
- movs r0, #109\r
- cmp r9, r0\r
- bne reg1_error_loop\r
- movs r0, #110\r
- cmp r10, r0\r
- bne reg1_error_loop\r
- movs r0, #111\r
- cmp r11, r0\r
- bne reg1_error_loop\r
- movs r0, #112\r
- cmp r12, r0\r
- bne reg1_error_loop\r
-\r
- /* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest1LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- /* Start again. */\r
- movs r0, #100\r
- b reg1_loop\r
-\r
-reg1_error_loop\r
- /* If this line is hit then there was an error in a core register value.\r
- The loop ensures the loop counter stops incrementing. */\r
- b reg1_error_loop\r
- nop\r
-\r
-\r
-\r
-vRegTest2Task\r
-\r
- /* Fill the core registers with known values. This is only done once. */\r
- movs r1, #1\r
- movs r2, #2\r
- movs r3, #3\r
- movs r4, #4\r
- movs r5, #5\r
- movs r6, #6\r
- movs r7, #7\r
- movs r0, #8\r
- mov r8, r0\r
- movs r0, #9\r
- mov r9, r0\r
- movs r0, #10\r
- mov r10, r0\r
- movs r0, #11\r
- mov r11, r0\r
- movs r0, #12\r
- mov r12, r0\r
- movs r0, #10\r
-\r
-reg2_loop\r
- /* Repeatedly check that each register still contains the value written to\r
- it when the task started. */\r
- cmp r0, #10\r
- bne reg2_error_loop\r
- cmp r1, #1\r
- bne reg2_error_loop\r
- cmp r2, #2\r
- bne reg2_error_loop\r
- cmp r3, #3\r
- bne reg2_error_loop\r
- cmp r4, #4\r
- bne reg2_error_loop\r
- cmp r5, #5\r
- bne reg2_error_loop\r
- cmp r6, #6\r
- bne reg2_error_loop\r
- cmp r7, #7\r
- bne reg2_error_loop\r
- movs r0, #8\r
- cmp r8, r0\r
- bne reg2_error_loop\r
- movs r0, #9\r
- cmp r9, r0\r
- bne reg2_error_loop\r
- movs r0, #10\r
- cmp r10, r0\r
- bne reg2_error_loop\r
- movs r0, #11\r
- cmp r11, r0\r
- bne reg2_error_loop\r
- movs r0, #12\r
- cmp r12, r0\r
- bne reg2_error_loop\r
-\r
- /* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest2LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- /* Start again. */\r
- movs r0, #10\r
- b reg2_loop\r
-\r
-reg2_error_loop\r
- ;/* If this line is hit then there was an error in a core register value.\r
- ;The loop ensures the loop counter stops incrementing. */\r
- b reg2_error_loop\r
- nop\r
-\r
- END\r
+++ /dev/null
-;************************************************\r
-;*\r
-;* Part one of the system initialization code, contains low-level\r
-;* initialization, plain thumb variant.\r
-;*\r
-;* Copyright 2013 IAR Systems. All rights reserved.\r
-;*\r
-;* $Revision: 64600 $\r
-;*\r
-;******************* Version History **********************************************\r
-;\r
-; V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc\r
-;\r
-;**********************************************************************************\r
-;\r
-; The modules in this file are included in the libraries, and may be replaced\r
-; by any user-defined modules that define the PUBLIC symbol _program_start or\r
-; a user defined start symbol.\r
-; To override the cstartup defined in the library, simply add your modified\r
-; version to the workbench project.\r
-;\r
-; Cortex-M version\r
-;\r
-\r
- MODULE ?cstartup\r
-#ifdef DAVE_CE\r
-#include "XMC1200_SCU.inc"\r
-#include "Device_Data.h"\r
-#else\r
-#define CLKVAL1_SSW 0x00000100\r
-#define CLKVAL2_SSW 0x00000000\r
-#endif\r
-\r
- ;; Forward declaration of sections.\r
- SECTION CSTACK:DATA:NOROOT(3)\r
- SECTION .intvec:CODE:NOROOT(2)\r
-\r
- EXTERN __iar_program_start\r
- PUBLIC __vector_table\r
-\r
- DATA\r
-__vector_table\r
- DCD sfe(CSTACK)\r
- DCD Reset_Handler ; Reset Handler\r
- DCD 0 ; 0x8\r
- DCD 0 ; 0xC\r
- DCD CLKVAL1_SSW ; 0x10 CLK_VAL1 - (CLKCR default)\r
- DCD CLKVAL2_SSW ; 0x14 CLK_VAL2 - (CGATCLR0 default)\r
-\r
- SECTION .vect_table:CODE:ROOT(2)\r
- THUMB\r
- LDR R0,=HardFault_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=SVC_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=PendSV_Handler\r
- BX R0\r
- LDR R0,=SysTick_Handler\r
- BX R0\r
-\r
- ; External Interrupts\r
- LDR R0,=SCU_0_IRQHandler ; Handler name for SR SCU_0\r
- BX R0\r
- LDR R0,=SCU_1_IRQHandler ; Handler name for SR SCU_1\r
- BX R0\r
- LDR R0,=SCU_2_IRQHandler ; Handler name for SR SCU_2\r
- BX R0\r
- LDR R0,=ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
- BX R0\r
- LDR R0,=ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
- BX R0\r
- LDR R0,=ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
- BX R0\r
- LDR R0,=ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
- BX R0\r
- LDR R0,=USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
- BX R0\r
- LDR R0,=USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
- BX R0\r
- LDR R0,=USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
- BX R0\r
- LDR R0,=USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
- BX R0\r
- LDR R0,=USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
- BX R0\r
- LDR R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
- BX R0\r
- LDR R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
- BX R0\r
- LDR R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
- BX R0\r
- LDR R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
- BX R0\r
- LDR R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
- BX R0\r
- LDR R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
- BX R0\r
- LDR R0,=CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
- BX R0\r
- LDR R0,=CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
- BX R0\r
- LDR R0,=CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
- BX R0\r
- LDR R0,=CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
- BX R0\r
- LDR R0,=LEDTS1_0_IRQHandler ; Handler name for SR LEDTS1_0\r
- BX R0\r
- LDR R0,=BCCU0_0_IRQHandler ; Handler name for SR BCCU0_0\r
- BX R0\r
-\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-;;\r
-;; Default interrupt handlers.\r
-;;\r
- EXTERN SystemInit\r
- SECTION .text:CODE:NOROOT(2)\r
-\r
- THUMB\r
-\r
- PUBWEAK Reset_Handler\r
- SECTION .text:CODE:REORDER(2)\r
-Reset_Handler\r
- LDR R0, =SystemInit\r
- BLX R0\r
- LDR R0, =SystemInit_DAVE3\r
- BLX R0\r
- LDR R0, =__iar_program_start\r
- BX R0\r
-\r
- PUBWEAK Undef_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-Undef_Handler\r
- B Undef_Handler\r
-\r
-\r
- PUBWEAK HardFault_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-HardFault_Handler\r
- B HardFault_Handler\r
-\r
-\r
- PUBWEAK SVC_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SVC_Handler\r
- B SVC_Handler\r
-\r
-\r
- PUBWEAK PendSV_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-PendSV_Handler\r
- B PendSV_Handler\r
-\r
-\r
- PUBWEAK SysTick_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SysTick_Handler\r
- B SysTick_Handler\r
-\r
-\r
- PUBWEAK SCU_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SCU_0_IRQHandler\r
- B SCU_0_IRQHandler\r
-\r
- PUBWEAK SCU_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SCU_1_IRQHandler\r
- B SCU_1_IRQHandler\r
-\r
-\r
- PUBWEAK SCU_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SCU_2_IRQHandler\r
- B SCU_2_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_0_IRQHandler\r
- B ERU0_0_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_1_IRQHandler\r
- B ERU0_1_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_2_IRQHandler\r
- B ERU0_2_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_3_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_3_IRQHandler\r
- B ERU0_3_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_0_IRQHandler\r
- B USIC0_0_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_1_IRQHandler\r
- B USIC0_1_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_2_IRQHandler\r
- B USIC0_2_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_3_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_3_IRQHandler\r
- B USIC0_3_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_4_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_4_IRQHandler\r
- B USIC0_4_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_5_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_5_IRQHandler\r
- B USIC0_5_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_C0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_C0_0_IRQHandler\r
- B VADC0_C0_0_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_C0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_C0_1_IRQHandler\r
- B VADC0_C0_1_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G0_0_IRQHandler\r
- B VADC0_G0_0_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G0_1_IRQHandler\r
- B VADC0_G0_1_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G1_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G1_0_IRQHandler\r
- B VADC0_G1_0_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G1_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G1_1_IRQHandler\r
- B VADC0_G1_1_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_0_IRQHandler\r
- B CCU40_0_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_1_IRQHandler\r
- B CCU40_1_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_2_IRQHandler\r
- B CCU40_2_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_3_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_3_IRQHandler\r
- B CCU40_3_IRQHandler\r
-\r
-\r
- PUBWEAK LEDTS0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-LEDTS0_0_IRQHandler\r
- B LEDTS0_0_IRQHandler\r
-\r
-\r
- PUBWEAK LEDTS1_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-LEDTS1_0_IRQHandler\r
- B LEDTS1_0_IRQHandler\r
-\r
-\r
- PUBWEAK BCCU0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-BCCU0_0_IRQHandler\r
- B BCCU0_0_IRQHandler\r
-\r
-; Definition of the default weak SystemInit_DAVE3 function\r
-;If DAVE3 requires an extended SystemInit it will create its own version of\r
-;SystemInit_DAVE3 which overrides this weak definition. Example includes\r
-;setting up of external memory interfaces.\r
-\r
- PUBWEAK SystemInit_DAVE3\r
- SECTION .text:CODE:REORDER:NOROOT(2)\r
-SystemInit_DAVE3\r
- NOP\r
- BX LR\r
-\r
-;Decision function queried by CMSIS startup for Clock tree setup ======== */\r
-;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.\r
-;This decision routine defined here will always return TRUE.\r
-;When overridden by a definition defined in DAVE code engine, this routine\r
-;returns FALSE indicating that the code engine has performed the clock setup\r
-\r
- PUBWEAK AllowClkInitByStartup\r
- SECTION .text:CODE:REORDER:NOROOT(2)\r
-AllowClkInitByStartup\r
- MOVS R0,#1\r
- BX LR\r
-\r
- END\r
+++ /dev/null
-[BREAKPOINTS]\r
-ShowInfoWin = 1\r
-EnableFlashBP = 2\r
-BPDuringExecution = 0\r
-[CFI]\r
-CFISize = 0x00\r
-CFIAddr = 0x00\r
-[CPU]\r
-OverrideMemMap = 0\r
-AllowSimulation = 1\r
-ScriptFile=""\r
-[FLASH]\r
-CacheExcludeSize = 0x00\r
-CacheExcludeAddr = 0x00\r
-MinNumBytesFlashDL = 0\r
-SkipProgOnCRCMatch = 1\r
-VerifyDownload = 1\r
-AllowCaching = 1\r
-EnableFlashDL = 2\r
-Override = 0\r
-Device="UNSPECIFIED"\r
-[GENERAL]\r
-WorkRAMSize = 0x00\r
-WorkRAMAddr = 0x00\r
-RAMUsageLimit = 0x00\r
-[SWO]\r
-SWOLogFile=""\r
-[MEM]\r
-RdOverrideOrMask = 0x00\r
-RdOverrideAndMask = 0xFFFFFFFF\r
-RdOverrideAddr = 0xFFFFFFFF\r
-WrOverrideOrMask = 0x00\r
-WrOverrideAndMask = 0xFFFFFFFF\r
-WrOverrideAddr = 0xFFFFFFFF\r
+++ /dev/null
-;/*\r
-; FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-;\r
-; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * FreeRTOS provides completely free yet professionally developed, *\r
-; * robust, strictly quality controlled, supported, and cross *\r
-; * platform software that has become a de facto standard. *\r
-; * *\r
-; * Help yourself get started quickly and support the FreeRTOS *\r
-; * project by purchasing a FreeRTOS tutorial book, reference *\r
-; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
-; * *\r
-; * Thank you! *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; This file is part of the FreeRTOS distribution.\r
-;\r
-; FreeRTOS is free software; you can redistribute it and/or modify it under\r
-; the terms of the GNU General Public License (version 2) as published by the\r
-; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-;\r
-; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
-; >>! a combined work that includes FreeRTOS without being obliged to provide\r
-; >>! the source code for proprietary components outside of the FreeRTOS\r
-; >>! kernel.\r
-;\r
-; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
-; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
-; link: http://www.freertos.org/a00114.html\r
-;\r
-; 1 tab == 4 spaces!\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * Having a problem? Start by reading the FAQ "My application does *\r
-; * not run, what could be wrong?" *\r
-; * *\r
-; * http://www.FreeRTOS.org/FAQHelp.html *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
-; license and Real Time Engineers Ltd. contact details.\r
-;\r
-; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
-; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
-; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-;\r
-; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
-; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
-; licenses offer ticketed support, indemnification and middleware.\r
-;\r
-; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
-; engineered and independently SIL3 certified version for use in safety and\r
-; mission critical applications that require provable dependability.\r
-;\r
-; 1 tab == 4 spaces!\r
-;*/\r
-\r
- PRESERVE8\r
- THUMB\r
- \r
-\r
- IMPORT ulRegTest1LoopCounter\r
- IMPORT ulRegTest2LoopCounter\r
-\r
- EXTERN vPortYield ;////////////////////////////////////////////////////////////////////////////////////////\r
-\r
- EXPORT vRegTest1Task\r
- EXPORT vRegTest2Task\r
- \r
- AREA |.text|, CODE, READONLY\r
-\r
-;/*-----------------------------------------------------------*/\r
-vRegTest1Task PROC\r
-\r
- ;/* Fill the core registers with known values. This is only done once. */\r
- movs r1, #101\r
- movs r2, #102\r
- movs r3, #103\r
- movs r4, #104\r
- movs r5, #105\r
- movs r6, #106\r
- movs r7, #107\r
- movs r0, #108\r
- mov r8, r0\r
- movs r0, #109\r
- mov r9, r0\r
- movs r0, #110\r
- mov r10, r0\r
- movs r0, #111\r
- mov r11, r0\r
- movs r0, #112\r
- mov r12, r0\r
- movs r0, #100\r
-\r
-reg1_loop\r
- ;/* Repeatedly check that each register still contains the value written to\r
- ;it when the task started. */\r
- cmp r0, #100\r
- bne reg1_error_loop\r
- cmp r1, #101\r
- bne reg1_error_loop\r
- cmp r2, #102\r
- bne reg1_error_loop\r
- cmp r3, #103\r
- bne reg1_error_loop\r
- cmp r4, #104\r
- bne reg1_error_loop\r
- cmp r5, #105\r
- bne reg1_error_loop\r
- cmp r6, #106\r
- bne reg1_error_loop\r
- cmp r7, #107\r
- bne reg1_error_loop\r
- movs r0, #108\r
- cmp r8, r0\r
- bne reg1_error_loop\r
- movs r0, #109\r
- cmp r9, r0\r
- bne reg1_error_loop\r
- movs r0, #110\r
- cmp r10, r0\r
- bne reg1_error_loop\r
- movs r0, #111\r
- cmp r11, r0\r
- bne reg1_error_loop\r
- movs r0, #112\r
- cmp r12, r0\r
- bne reg1_error_loop\r
-\r
- ;/* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest1LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- ;/* Start again. */\r
- movs r0, #100\r
- \r
- push {r0-r1}\r
- bl vPortYield ;;///////////////////////////////////////////////////////////////////////////////////////////////////\r
- pop {r0-r1}\r
- \r
- b reg1_loop\r
-\r
-reg1_error_loop\r
- ;/* If this line is hit then there was an error in a core register value.\r
- ;The loop ensures the loop counter stops incrementing. */\r
- b reg1_error_loop\r
- nop\r
- ENDP\r
-\r
-\r
-\r
-vRegTest2Task PROC\r
-\r
- ;/* Fill the core registers with known values. This is only done once. */\r
- movs r1, #1\r
- movs r2, #2\r
- movs r3, #3\r
- movs r4, #4\r
- movs r5, #5\r
- movs r6, #6\r
- movs r7, #7\r
- movs r0, #8\r
- mov r8, r0\r
- movs r0, #9\r
- mov r9, r0\r
- movs r0, #10\r
- mov r10, r0\r
- movs r0, #11\r
- mov r11, r0\r
- movs r0, #12\r
- mov r12, r0\r
- movs r0, #10\r
-\r
-reg2_loop\r
- ;/* Repeatedly check that each register still contains the value written to\r
- ;it when the task started. */\r
- cmp r0, #10\r
- bne reg2_error_loop\r
- cmp r1, #1\r
- bne reg2_error_loop\r
- cmp r2, #2\r
- bne reg2_error_loop\r
- cmp r3, #3\r
- bne reg2_error_loop\r
- cmp r4, #4\r
- bne reg2_error_loop\r
- cmp r5, #5\r
- bne reg2_error_loop\r
- cmp r6, #6\r
- bne reg2_error_loop\r
- cmp r7, #7\r
- bne reg2_error_loop\r
- movs r0, #8\r
- cmp r8, r0\r
- bne reg2_error_loop\r
- movs r0, #9\r
- cmp r9, r0\r
- bne reg2_error_loop\r
- movs r0, #10\r
- cmp r10, r0\r
- bne reg2_error_loop\r
- movs r0, #11\r
- cmp r11, r0\r
- bne reg2_error_loop\r
- movs r0, #12\r
- cmp r12, r0\r
- bne reg2_error_loop\r
-\r
- ;/* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest2LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- ;/* Start again. */\r
- movs r0, #10\r
- b reg2_loop\r
-\r
-reg2_error_loop\r
- ;/* If this line is hit then there was an error in a core register value.\r
- ;The loop ensures the loop counter stops incrementing. */\r
- b reg2_error_loop\r
- nop\r
- ENDP\r
-\r
- END\r
+++ /dev/null
-;*****************************************************************************/\r
-; * @file startup_XMC1300.s\r
-; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
-; * Infineon XMC1300 Device Series\r
-; * @version V1.00\r
-; * @date 21. Jan. 2013\r
-; *\r
-; * @note\r
-; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
-; *\r
-; * @par\r
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
-; * processor based microcontrollers. This file can be freely distributed\r
-; * within development tools that are supporting such ARM based processors.\r
-; *\r
-; * @par\r
-; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
-; *\r
-; ******************************************************************************/\r
-\r
-\r
-;* <<< Use Configuration Wizard in Context Menu >>>\r
-\r
-; Amount of memory (in bytes) allocated for Stack\r
-; Tailor this value to your application needs\r
-; <h> Stack Configuration\r
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Stack_Size EQU 0x00000400\r
-\r
- AREA STACK, NOINIT, READWRITE, ALIGN=3\r
-Stack_Mem SPACE Stack_Size\r
-__initial_sp\r
-\r
-\r
-; <h> Heap Configuration\r
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Heap_Size EQU 0x00000000\r
-\r
- AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
-__heap_base\r
-Heap_Mem SPACE Heap_Size\r
-__heap_limit\r
-\r
-; <h> Clock system handling by SSW\r
-; <h> CLK_VAL1 Configuration\r
-; <o0.0..7> FDIV Fractional Divider Selection\r
-; <o0.8..15> IDIV Divider Selection\r
-; <0=> Divider is bypassed\r
-; <1=> MCLK = 32 MHz\r
-; <2=> MCLK = 16 MHz\r
-; <3=> MCLK = 10.67 MHz\r
-; <4=> MCLK = 8 MHz\r
-; <254=> MCLK = 126 kHz\r
-; <255=> MCLK = 125.5 kHz\r
-; <o0.16> PCLKSEL PCLK Clock Select\r
-; <0=> PCLK = MCLK\r
-; <1=> PCLK = 2 x MCLK\r
-; <o0.17..19> RTCCLKSEL RTC Clock Select\r
-; <0=> 32.768kHz standby clock\r
-; <1=> 32.768kHz external clock from ERU0.IOUT0\r
-; <2=> 32.768kHz external clock from ACMP0.OUT\r
-; <3=> 32.768kHz external clock from ACMP1.OUT\r
-; <4=> 32.768kHz external clock from ACMP2.OUT\r
-; <5=> Reserved\r
-; <6=> Reserved\r
-; <7=> Reserved\r
-; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
-; </h>\r
-CLK_VAL1_Val EQU 0x00000100 ; 0xF0000000\r
-\r
-; <h> CLK_VAL2 Configuration\r
-; <o0.0> disable VADC and SHS Gating\r
-; <o0.1> disable CCU80 Gating\r
-; <o0.2> disable CCU40 Gating\r
-; <o0.3> disable USIC0 Gating\r
-; <o0.4> disable BCCU0 Gating\r
-; <o0.5> disable LEDTS0 Gating\r
-; <o0.6> disable LEDTS1 Gating\r
-; <o0.7> disable POSIF0 Gating\r
-; <o0.8> disable MATH Gating\r
-; <o0.9> disable WDT Gating\r
-; <o0.10> disable RTC Gating\r
-; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
-; </h>\r
-CLK_VAL2_Val EQU 0x00000000 ; 0xF0000000\r
-; </h>\r
-\r
- PRESERVE8\r
- THUMB\r
-\r
-;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
-;* Vector Table Mapped to Address 0 at Reset\r
- AREA RESET, DATA, READONLY\r
- EXPORT __Vectors\r
- EXPORT __Vectors_End\r
- EXPORT __Vectors_Size\r
-\r
-\r
-\r
-__Vectors\r
- DCD __initial_sp ;* Top of Stack\r
- DCD Reset_Handler ;* Reset Handler\r
- DCD 0 ;* Not used\r
- DCD 0 ;* Not Used\r
- DCD CLK_VAL1_Val ;* CLK_VAL1\r
- DCD CLK_VAL2_Val ;* CLK_VAL2\r
-__Vectors_End\r
-\r
-__Vectors_Size EQU __Vectors_End - __Vectors\r
-\r
-;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
-\r
-\r
-;* ================== START OF VECTOR ROUTINES ============================== */\r
- AREA |.text|, CODE, READONLY\r
-\r
-;* Reset Handler\r
-Reset_Handler PROC\r
- EXPORT Reset_Handler [WEAK]\r
- IMPORT __main\r
- IMPORT SystemInit\r
-\r
- ;* C routines are likely to be called. Setup the stack now\r
- LDR R0, =__initial_sp\r
- MOV SP, R0\r
-\r
- ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
- ; The real veneers will be copied later from the scatter loader before reaching main.\r
- ; This init code should handle an exception before the real veneers are copied.\r
-SRAM_BASE EQU 0x20000000\r
-VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
-\r
- LDR R1, =SRAM_BASE\r
- LDR R2, =VENEER_INIT_CODE \r
- MOVS R0, #48 ; Veneer 0..47\r
-Init_Veneers\r
- STR R2, [R1]\r
- ADDS R1, #4\r
- SUBS R0, R0, #1\r
- BNE Init_Veneers\r
-\r
-\r
- LDR R0, =SystemInit\r
- BLX R0\r
-\r
-\r
- ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
- ; weakly defined here though for a potential override.\r
-\r
- LDR R0, = SystemInit_DAVE3\r
- BLX R0\r
-\r
-\r
- LDR R0, =__main\r
- BX R0\r
-\r
-\r
- ALIGN\r
- ENDP\r
-\r
-;* ========================================================================== */\r
-\r
-\r
-\r
-;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
-;* Default exception Handlers - Users may override this default functionality\r
-\r
-NMI_Handler PROC\r
- EXPORT NMI_Handler [WEAK]\r
- B .\r
- ENDP\r
-HardFault_Handler\\r
- PROC\r
- EXPORT HardFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-SVC_Handler\\r
- PROC\r
- EXPORT SVC_Handler [WEAK]\r
- B .\r
- ENDP\r
-PendSV_Handler\\r
- PROC\r
- EXPORT PendSV_Handler [WEAK]\r
- B .\r
- ENDP\r
-SysTick_Handler\\r
- PROC\r
- EXPORT SysTick_Handler [WEAK]\r
- B .\r
- ENDP\r
-\r
-;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
-\r
-\r
-;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
-;* IRQ Handlers\r
-\r
-Default_Handler PROC\r
- EXPORT SCU_0_IRQHandler [WEAK]\r
- EXPORT SCU_1_IRQHandler [WEAK]\r
- EXPORT SCU_2_IRQHandler [WEAK]\r
- EXPORT ERU0_0_IRQHandler [WEAK]\r
- EXPORT ERU0_1_IRQHandler [WEAK]\r
- EXPORT ERU0_2_IRQHandler [WEAK]\r
- EXPORT ERU0_3_IRQHandler [WEAK]\r
- EXPORT MATH0_0_IRQHandler [WEAK]\r
- EXPORT USIC0_0_IRQHandler [WEAK]\r
- EXPORT USIC0_1_IRQHandler [WEAK]\r
- EXPORT USIC0_2_IRQHandler [WEAK]\r
- EXPORT USIC0_3_IRQHandler [WEAK]\r
- EXPORT USIC0_4_IRQHandler [WEAK]\r
- EXPORT USIC0_5_IRQHandler [WEAK]\r
- EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
- EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
- EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
- EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
- EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
- EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
- EXPORT CCU40_0_IRQHandler [WEAK]\r
- EXPORT CCU40_1_IRQHandler [WEAK]\r
- EXPORT CCU40_2_IRQHandler [WEAK]\r
- EXPORT CCU40_3_IRQHandler [WEAK]\r
- EXPORT CCU80_0_IRQHandler [WEAK]\r
- EXPORT CCU80_1_IRQHandler [WEAK]\r
- EXPORT POSIF0_0_IRQHandler [WEAK]\r
- EXPORT POSIF0_1_IRQHandler [WEAK]\r
- EXPORT LEDTS0_0_IRQHandler [WEAK]\r
- EXPORT LEDTS1_0_IRQHandler [WEAK]\r
- EXPORT BCCU0_0_IRQHandler [WEAK]\r
-\r
-SCU_0_IRQHandler\r
-SCU_1_IRQHandler\r
-SCU_2_IRQHandler\r
-ERU0_0_IRQHandler\r
-ERU0_1_IRQHandler\r
-ERU0_2_IRQHandler\r
-ERU0_3_IRQHandler\r
-MATH0_0_IRQHandler\r
-USIC0_0_IRQHandler\r
-USIC0_1_IRQHandler\r
-USIC0_2_IRQHandler\r
-USIC0_3_IRQHandler\r
-USIC0_4_IRQHandler\r
-USIC0_5_IRQHandler\r
-VADC0_C0_0_IRQHandler\r
-VADC0_C0_1_IRQHandler\r
-VADC0_G0_0_IRQHandler\r
-VADC0_G0_1_IRQHandler\r
-VADC0_G1_0_IRQHandler\r
-VADC0_G1_1_IRQHandler\r
-CCU40_0_IRQHandler\r
-CCU40_1_IRQHandler\r
-CCU40_2_IRQHandler\r
-CCU40_3_IRQHandler\r
-CCU80_0_IRQHandler\r
-CCU80_1_IRQHandler\r
-POSIF0_0_IRQHandler\r
-POSIF0_1_IRQHandler\r
-LEDTS0_0_IRQHandler\r
-LEDTS1_0_IRQHandler\r
-BCCU0_0_IRQHandler\r
-\r
- B .\r
-\r
- ENDP\r
-\r
- ALIGN\r
-\r
-;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
-\r
-;* Definition of the default weak SystemInit_DAVE3 function.\r
-;* This function will be called by the CMSIS SystemInit function.\r
-;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
-;* which will overule this weak definition\r
-SystemInit_DAVE3 PROC\r
- EXPORT SystemInit_DAVE3 [WEAK]\r
- NOP\r
- BX LR\r
- ENDP\r
-\r
-;* Definition of the default weak DAVE3 function for clock App usage.\r
-;* AllowClkInitByStartup Handler */\r
-AllowClkInitByStartup PROC\r
- EXPORT AllowClkInitByStartup [WEAK]\r
- MOVS R0,#1\r
- BX LR\r
- ENDP\r
-\r
-\r
-;*******************************************************************************\r
-; User Stack and Heap initialization\r
-;*******************************************************************************\r
- IF :DEF:__MICROLIB\r
-\r
- EXPORT __initial_sp\r
- EXPORT __heap_base\r
- EXPORT __heap_limit\r
-\r
- ELSE\r
-\r
- IMPORT __use_two_region_memory\r
- EXPORT __user_initial_stackheap\r
-\r
-__user_initial_stackheap\r
-\r
- LDR R0, = Heap_Mem\r
- LDR R1, =(Stack_Mem + Stack_Size)\r
- LDR R2, = (Heap_Mem + Heap_Size)\r
- LDR R3, = Stack_Mem\r
- BX LR\r
-\r
- ALIGN\r
-\r
- ENDIF\r
-\r
-\r
-;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
-; Veneers are located to fix SRAM Address 0x2000'0000\r
- AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
-\r
-; Each Veneer has exactly a lengs of 4 Byte\r
-\r
- MACRO\r
- STAYHERE $IrqNumber\r
- LDR R0, =$IrqNumber\r
- B .\r
- MEND\r
-\r
- MACRO\r
- JUMPTO $Handler\r
- LDR R0, =$Handler\r
- BX R0\r
- MEND\r
-\r
- STAYHERE 0x0 ;* Reserved\r
- STAYHERE 0x1 ;* Reserved \r
- STAYHERE 0x2 ;* Reserved \r
- JUMPTO HardFault_Handler ;* HardFault Veneer \r
- STAYHERE 0x4 ;* Reserved \r
- STAYHERE 0x5 ;* Reserved \r
- STAYHERE 0x6 ;* Reserved \r
- STAYHERE 0x7 ;* Reserved \r
- STAYHERE 0x8 ;* Reserved \r
- STAYHERE 0x9 ;* Reserved \r
- STAYHERE 0xA ;* Reserved\r
- JUMPTO SVC_Handler ;* SVC Veneer \r
- STAYHERE 0xC ;* Reserved\r
- STAYHERE 0xD ;* Reserved\r
- JUMPTO PendSV_Handler ;* PendSV Veneer \r
- JUMPTO SysTick_Handler ;* SysTick Veneer \r
- JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
- JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
- JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
- JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
- JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
- JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
- JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
- JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
- STAYHERE 0x18 ;* Reserved\r
- JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
- JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
- JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
- JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
- JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
- JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
- JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
- JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
- JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
- JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
- JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
- JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
- JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
- JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
- JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
- JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
- JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
- JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
- JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
- JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
- JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
- JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
- JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
-\r
- ALIGN\r
-\r
-;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
-\r
- END\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1100.c\r
- * @brief Device specific initialization for the XMC1100-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * *************************** Change history ********************************\r
- * V1.2, 13 Dec 2012, PKB : Created change history table\r
- */\r
-\r
-#include "system_XMC1100.h"\r
-#include <XMC1100.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1200.c\r
- * @brief Device specific initialization for the XMC1200-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * *************************** Change history ********************************\r
- * V1.2, 13 Dec 2012, PKB : Created change history table\r
- */\r
-\r
-#include "System_XMC1200.h"\r
-#include <XMC1200.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1300.c\r
- * @brief Device specific initialization for the XMC1300-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * ************************** Change history *********************************\r
- * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_\r
- */\r
-\r
-#include "system_XMC1300.h"\r
-#include <XMC1300.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/*-----------------------------------------------------------\r
- * Simple GPIO (parallel port) IO routines.\r
- *-----------------------------------------------------------*/\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Hardware includes. */\r
-#include <XMC1200.h>\r
-\r
-/* Standard demo include. */\r
-#include "partest.h"\r
-\r
-/* The port bits on which LEDs are connected. */\r
-static const unsigned long ulLEDBits[] = \r
-{ \r
- 1UL << 0, /* P0.0 */\r
- 1UL << 2, /* P0.2 */\r
- 1UL << 5, /* P0.5 */\r
- 1UL << 6, /* P0.6 */\r
- 1UL << 7 /* P0.7 */\r
-};\r
-\r
-#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) )\r
-\r
-/* Shift the LED bit into the correct position within the POW register to\r
-perform the desired operation. */\r
-#define partstON_SHIFT ( 16UL )\r
-#define partstOFF_SHIFT ( 0UL )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestInitialise( void )\r
-{\r
- /* Configure relevant port P0 to push pull output to drive LEDs. */\r
- \r
- /* P0.0 */\r
- PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) );\r
- PORT0->IOCR0 |= ( 0x80UL << 0 );\r
- vParTestSetLED( 0, pdFALSE );\r
-\r
- /* P0.2 */\r
- PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) );\r
- PORT0->IOCR0 |= ( 0x80UL << 16 );\r
- vParTestSetLED( 1, pdFALSE );\r
-\r
- /* P0.5 */\r
- PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) );\r
- PORT0->IOCR4 |= ( 0x80UL << 8 );\r
- vParTestSetLED( 2, pdFALSE );\r
-\r
- /* P0.6 */\r
- PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) );\r
- PORT0->IOCR4 |= ( 0x80UL << 16 );\r
- vParTestSetLED( 3, pdFALSE );\r
-\r
- /* P0.7 */\r
- PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) );\r
- PORT0->IOCR4 |= ( 0x80UL << 24 );\r
- vParTestSetLED( 4, pdFALSE );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )\r
-{\r
- if( ulLED < partstNUM_LEDS )\r
- {\r
- if( xValue == pdTRUE )\r
- {\r
- /* Turn the LED on. */ \r
- PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT );\r
- }\r
- else\r
- {\r
- /* Turn the LED off. */ \r
- PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vParTestToggleLED( unsigned long ulLED )\r
-{\r
- if( ulLED < partstNUM_LEDS )\r
- {\r
- /* Setting both the ON and OFF bits simultaneously results in the bit\r
- being toggled. */\r
- PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-<?xml version="1.0" encoding="iso-8859-1"?>\r
-\r
-<project>\r
- <fileVersion>2</fileVersion>\r
- <configuration>\r
- <name>Debug</name>\r
- <toolchain>\r
- <name>ARM</name>\r
- </toolchain>\r
- <debug>1</debug>\r
- <settings>\r
- <name>C-SPY</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>25</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CInput</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CEndian</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCVariant</name>\r
- <state>0</state>\r
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- <state></state>\r
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- <state>0</state>\r
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- <option>\r
- <name>MemFile</name>\r
- <state>$TOOLKIT_DIR$\CONFIG\debugger\Infineon\xmc1200.ddf</state>\r
- </option>\r
- <option>\r
- <name>RunToEnable</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>RunToName</name>\r
- <state>main</state>\r
- </option>\r
- <option>\r
- <name>CExtraOptionsCheck</name>\r
- <state>0</state>\r
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- <option>\r
- <name>CExtraOptions</name>\r
- <state></state>\r
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- <option>\r
- <name>CFpuProcessor</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCDDFArgumentProducer</name>\r
- <state></state>\r
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- <name>OCDownloadVerifyAll</name>\r
- <state>1</state>\r
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- <name>OCProductVersion</name>\r
- <state>6.50.2.4581</state>\r
- </option>\r
- <option>\r
- <name>OCDynDriverList</name>\r
- <state>JLINK_ID</state>\r
- </option>\r
- <option>\r
- <name>OCLastSavedByProductVersion</name>\r
- <state>6.60.1.5099</state>\r
- </option>\r
- <option>\r
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- <name>UseFlashLoader</name>\r
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- <name>CLowLevel</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCBE8Slave</name>\r
- <state>1</state>\r
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- <name>CDevice</name>\r
- <state>1</state>\r
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- <option>\r
- <name>FlashLoadersV3</name>\r
- <state>$TOOLKIT_DIR$\config\flashloader\Infineon\FlashXMC1200.board</state>\r
- </option>\r
- <option>\r
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- <state>0</state>\r
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- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCImagesPath3</name>\r
- <state></state>\r
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- <option>\r
- <name>OCImagesOffset1</name>\r
- <state></state>\r
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- <option>\r
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- <name>OCImagesOffset3</name>\r
- <state></state>\r
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- </option>\r
- <option>\r
- <name>OCDeviceConfigMacroFile</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCDebuggerExtraOption</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCAllMTBOptions</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ARMSIM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OCSimDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCSimEnablePSP</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspOverrideConfig</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>OCSimPspConfigFile</name>\r
- <state></state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>ANGEL_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>CCAngelHeartbeat</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommunication</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommBaud</name>\r
- <version>0</version>\r
- <state>3</state>\r
- </option>\r
- <option>\r
- <name>CAngelCommPort</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>ANGELTCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
- <option>\r
- <name>DoAngelLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>AngelLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>CMSISDAP_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPAttachSlave</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>OCIarProbeScriptFile</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPResetList</name>\r
- <version>1</version>\r
- <state>10</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPHWResetDuration</name>\r
- <state>300</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPHWResetDelay</name>\r
- <state>200</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPDoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPLogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPInterfaceRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPInterfaceCmdLine</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPMultiTargetEnable</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPMultiTarget</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPJtagSpeedList</name>\r
- <version>0</version>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPBreakpointRadio</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPRestoreBreakpointsCheck</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPUpdateBreakpointsEdit</name>\r
- <state>_call_main</state>\r
- </option>\r
- <option>\r
- <name>RDICatchReset</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>RDICatchUndef</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>RDICatchSWI</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>RDICatchData</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>RDICatchPrefetch</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>RDICatchIRQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>RDICatchFIQ</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchCORERESET</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchMMERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchNOCPERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchCHKERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchSTATERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchBUSERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchINTERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchHARDERR</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CatchDummy</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPMultiCPUEnable</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>CMSISDAPMultiCPUNumber</name>\r
- <state>0</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>GDBSERVER_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
- <data>\r
- <version>0</version>\r
- <wantNonLocal>1</wantNonLocal>\r
- <debug>1</debug>\r
- <option>\r
- <name>OCDriverInfo</name>\r
- <state>1</state>\r
- </option>\r
- <option>\r
- <name>TCPIP</name>\r
- <state>aaa.bbb.ccc.ddd</state>\r
- </option>\r
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- <name>DoLogfile</name>\r
- <state>0</state>\r
- </option>\r
- <option>\r
- <name>LogFile</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
- </option>\r
- <option>\r
- <name>CCJTagBreakpointRadio</name>\r
- <state>0</state>\r
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- <option>\r
- <name>CCJTagDoUpdateBreakpoints</name>\r
- <state>0</state>\r
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- <option>\r
- <name>CCJTagUpdateBreakpoints</name>\r
- <state>_call_main</state>\r
- </option>\r
- </data>\r
- </settings>\r
- <settings>\r
- <name>IARROM_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
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- <version>1</version>\r
- <wantNonLocal>1</wantNonLocal>\r
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- <option>\r
- <name>CRomLogFileCheck</name>\r
- <state>0</state>\r
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- <name>CRomLogFileEditB</name>\r
- <state>$PROJ_DIR$\cspycomm.log</state>\r
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- <name>CRomCommPort</name>\r
- <version>0</version>\r
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- <state>7</state>\r
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- <name>OCDriverInfo</name>\r
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- <name>IJET_ID</name>\r
- <archiveVersion>2</archiveVersion>\r
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- <state>1</state>\r
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- <option>\r
- <name>IjetAttachSlave</name>\r
- <state>1</state>\r
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- <name>OCIarProbeScriptFile</name>\r
- <state>1</state>\r
- </option>\r
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- <name>IjetResetList</name>\r
- <version>1</version>\r
- <state>10</state>\r
- </option>\r
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-<h1>µVision Build Log</h1>\r
-<h2>Project:</h2>\r
-C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil\RTOSDemo.uvproj\r
-Project File Date: 08/24/2013\r
-\r
-<h2>Output:</h2>\r
-Build target 'XMC1300'\r
-assembling startup_XMC1300.s...\r
-compiling timers.c...\r
-compiling list.c...\r
-compiling queue.c...\r
-compiling tasks.c...\r
-compiling port.c...\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(101): warning: #1207-D: attribute "naked" ignored\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(103): warning: #1207-D: attribute "naked" ignored\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(108): warning: #1207-D: attribute "naked" ignored\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(155): warning: #1267-D: Implicit physical register R3 should be defined as a variable\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error: #1086: Operand is wrong type\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error: #114: label "pxCurrentTCBConst2" was referenced but not defined\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(168): warning: #1267-D: Implicit physical register R0 should be defined as a variable\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning: #1267-D: Implicit physical register R0 should be defined as a variable\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning: #1267-D: Implicit physical register R3 should be defined as a variable\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error: #1086: Operand is wrong type\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error: #114: label "pxCurrentTCBConst" was referenced but not defined\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(306): error: #20: identifier "SystemCoreClock" is undefined\r
-compiling ParTest.c...\r
-compiling main.c...\r
-compiling main-blinky.c...\r
-".\RTOSDemo.axf" - 5 Errors, 7 Warning(s).\r
-Target not created\r
-Clean started: Project: 'RTOSDemo'\r
- deleting intermediate output files for target 'XMC1300'\r
-Build target 'XMC1300'\r
-assembling startup_XMC1300.s...\r
-compiling timers.c...\r
-compiling list.c...\r
-compiling queue.c...\r
-compiling tasks.c...\r
-compiling port.c...\r
-..\..\Source\portable\RVDS\ARM_CM0\port.c(305): error: #20: identifier "SystemCoreClock" is undefined\r
-compiling ParTest.c...\r
-compiling main.c...\r
-compiling main-blinky.c...\r
-".\Output\RTOSDemo.axf" - 1 Errors, 0 Warning(s).\r
-Target not created\r
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- <AdsLszi>1</AdsLszi>
- <AdsLtoi>1</AdsLtoi>
- <AdsLsun>1</AdsLsun>
- <AdsLven>1</AdsLven>
- <AdsLsxf>1</AdsLsxf>
- <RvctClst>0</RvctClst>
- <GenPPlst>0</GenPPlst>
- <AdsCpuType>"Cortex-M0"</AdsCpuType>
- <RvctDeviceName></RvctDeviceName>
- <mOS>0</mOS>
- <uocRom>0</uocRom>
- <uocRam>0</uocRam>
- <hadIROM>1</hadIROM>
- <hadIRAM>1</hadIRAM>
- <hadXRAM>0</hadXRAM>
- <uocXRam>0</uocXRam>
- <RvdsVP>0</RvdsVP>
- <hadIRAM2>0</hadIRAM2>
- <hadIROM2>0</hadIROM2>
- <StupSel>8</StupSel>
- <useUlib>0</useUlib>
- <EndSel>0</EndSel>
- <uLtcg>0</uLtcg>
- <RoSelD>3</RoSelD>
- <RwSelD>3</RwSelD>
- <CodeSel>0</CodeSel>
- <OptFeed>0</OptFeed>
- <NoZi1>0</NoZi1>
- <NoZi2>0</NoZi2>
- <NoZi3>0</NoZi3>
- <NoZi4>0</NoZi4>
- <NoZi5>0</NoZi5>
- <Ro1Chk>0</Ro1Chk>
- <Ro2Chk>0</Ro2Chk>
- <Ro3Chk>0</Ro3Chk>
- <Ir1Chk>1</Ir1Chk>
- <Ir2Chk>0</Ir2Chk>
- <Ra1Chk>0</Ra1Chk>
- <Ra2Chk>0</Ra2Chk>
- <Ra3Chk>0</Ra3Chk>
- <Im1Chk>1</Im1Chk>
- <Im2Chk>0</Im2Chk>
- <OnChipMemories>
- <Ocm1>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm1>
- <Ocm2>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm2>
- <Ocm3>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm3>
- <Ocm4>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm4>
- <Ocm5>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm5>
- <Ocm6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm6>
- <IRAM>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x4000</Size>
- </IRAM>
- <IROM>
- <Type>1</Type>
- <StartAddress>0x10001000</StartAddress>
- <Size>0x32000</Size>
- </IROM>
- <XRAM>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </XRAM>
- <OCR_RVCT1>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT1>
- <OCR_RVCT2>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT2>
- <OCR_RVCT3>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT3>
- <OCR_RVCT4>
- <Type>1</Type>
- <StartAddress>0x10001000</StartAddress>
- <Size>0x32000</Size>
- </OCR_RVCT4>
- <OCR_RVCT5>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT5>
- <OCR_RVCT6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT6>
- <OCR_RVCT7>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT7>
- <OCR_RVCT8>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT8>
- <OCR_RVCT9>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x4000</Size>
- </OCR_RVCT9>
- <OCR_RVCT10>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT10>
- </OnChipMemories>
- <RvctStartVector></RvctStartVector>
- </ArmAdsMisc>
- <Cads>
- <interw>1</interw>
- <Optim>1</Optim>
- <oTime>0</oTime>
- <SplitLS>0</SplitLS>
- <OneElfS>0</OneElfS>
- <Strict>0</Strict>
- <EnumInt>0</EnumInt>
- <PlainCh>0</PlainCh>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>0</uThumb>
- <uSurpInc>0</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath>..\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include</IncludePath>
- </VariousControls>
- </Cads>
- <Aads>
- <interw>1</interw>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <thumb>0</thumb>
- <SplitLS>0</SplitLS>
- <SwStkChk>0</SwStkChk>
- <NoWarn>0</NoWarn>
- <uSurpInc>0</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Aads>
- <LDads>
- <umfTarg>1</umfTarg>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <noStLib>0</noStLib>
- <RepFail>1</RepFail>
- <useFile>0</useFile>
- <TextAddressRange>0x10001000</TextAddressRange>
- <DataAddressRange>0x20000000</DataAddressRange>
- <ScatterFile></ScatterFile>
- <IncludeLibs></IncludeLibs>
- <IncludeLibsPath></IncludeLibsPath>
- <Misc></Misc>
- <LinkerInputFile></LinkerInputFile>
- <DisabledWarnings></DisabledWarnings>
- </LDads>
- </TargetArmAds>
- </TargetOption>
- <Groups>
- <Group>
- <GroupName>System</GroupName>
- <Files>
- <File>
- <FileName>system_XMC1200.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\system_XMC1200.c</FilePath>
- </File>
- <File>
- <FileName>startup_XMC1300.s</FileName>
- <FileType>2</FileType>
- <FilePath>.\Keil_Specific\startup_XMC1300.s</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>FreeRTOS source</GroupName>
- <Files>
- <File>
- <FileName>timers.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\timers.c</FilePath>
- </File>
- <File>
- <FileName>list.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\list.c</FilePath>
- </File>
- <File>
- <FileName>queue.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\queue.c</FilePath>
- </File>
- <File>
- <FileName>tasks.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\tasks.c</FilePath>
- </File>
- <File>
- <FileName>port.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\portable\RVDS\ARM_CM0\port.c</FilePath>
- </File>
- <File>
- <FileName>heap_4.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>Demo App Source</GroupName>
- <Files>
- <File>
- <FileName>main.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\main.c</FilePath>
- </File>
- <File>
- <FileName>main-blinky.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\main-blinky.c</FilePath>
- </File>
- <File>
- <FileName>FreeRTOSConfig.h</FileName>
- <FileType>5</FileType>
- <FilePath>.\FreeRTOSConfig.h</FilePath>
- </File>
- <File>
- <FileName>main-full.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\main-full.c</FilePath>
- </File>
- <File>
- <FileName>ParTest_XMC1200.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\ParTest_XMC1200.c</FilePath>
- <FileOption>
- <CommonProperty>
- <UseCPPCompiler>2</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>0</IncludeInBuild>
- <AlwaysBuild>2</AlwaysBuild>
- <GenerateAssemblyFile>2</GenerateAssemblyFile>
- <AssembleAssemblyFile>2</AssembleAssemblyFile>
- <PublicsOnly>2</PublicsOnly>
- <StopOnExitCode>11</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- </CommonProperty>
- <FileArmAds>
- <Cads>
- <interw>2</interw>
- <Optim>0</Optim>
- <oTime>2</oTime>
- <SplitLS>2</SplitLS>
- <OneElfS>2</OneElfS>
- <Strict>2</Strict>
- <EnumInt>2</EnumInt>
- <PlainCh>2</PlainCh>
- <Ropi>2</Ropi>
- <Rwpi>2</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>2</uThumb>
- <uSurpInc>2</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Cads>
- </FileArmAds>
- </FileOption>
- </File>
- <File>
- <FileName>RegTest_Keil.s</FileName>
- <FileType>2</FileType>
- <FilePath>.\Keil_Specific\RegTest_Keil.s</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>Common Demo Tasks</GroupName>
- <Files>
- <File>
- <FileName>dynamic.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\dynamic.c</FilePath>
- </File>
- <File>
- <FileName>recmutex.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\recmutex.c</FilePath>
- </File>
- <File>
- <FileName>blocktim.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\blocktim.c</FilePath>
- </File>
- <File>
- <FileName>countsem.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\countsem.c</FilePath>
- </File>
- </Files>
- </Group>
- </Groups>
- </Target>
- <Target>
- <TargetName>XMC1200</TargetName>
- <ToolsetNumber>0x4</ToolsetNumber>
- <ToolsetName>ARM-ADS</ToolsetName>
- <TargetOption>
- <TargetCommonOption>
- <Device>XMC1200-200</Device>
- <Vendor>Infineon</Vendor>
- <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
- <FlashUtilSpec></FlashUtilSpec>
- <StartupFile>"STARTUP\Infineon\XMC1200\startup_XMC1200.s" ("Infineon XMC1200 Startup Code")</StartupFile>
- <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000)</FlashDriverDll>
- <DeviceId>6777</DeviceId>
- <RegisterFile>XMC1200.h</RegisterFile>
- <MemoryEnv></MemoryEnv>
- <Cmp></Cmp>
- <Asm></Asm>
- <Linker></Linker>
- <OHString></OHString>
- <InfinionOptionDll></InfinionOptionDll>
- <SLE66CMisc></SLE66CMisc>
- <SLE66AMisc></SLE66AMisc>
- <SLE66LinkerMisc></SLE66LinkerMisc>
- <SFDFile>SFD\Infineon\XMC1200\xmc1200.SFR</SFDFile>
- <UseEnv>0</UseEnv>
- <BinPath></BinPath>
- <IncludePath></IncludePath>
- <LibPath></LibPath>
- <RegisterFilePath>Infineon\XMC1200\</RegisterFilePath>
- <DBRegisterFilePath>Infineon\XMC1200\</DBRegisterFilePath>
- <TargetStatus>
- <Error>0</Error>
- <ExitCodeStop>0</ExitCodeStop>
- <ButtonStop>0</ButtonStop>
- <NotGenerated>0</NotGenerated>
- <InvalidFlash>1</InvalidFlash>
- </TargetStatus>
- <OutputDirectory>.\Output\</OutputDirectory>
- <OutputName>RTOSDemo</OutputName>
- <CreateExecutable>1</CreateExecutable>
- <CreateLib>0</CreateLib>
- <CreateHexFile>0</CreateHexFile>
- <DebugInformation>1</DebugInformation>
- <BrowseInformation>1</BrowseInformation>
- <ListingPath>.\</ListingPath>
- <HexFormatSelection>1</HexFormatSelection>
- <Merge32K>0</Merge32K>
- <CreateBatchFile>0</CreateBatchFile>
- <BeforeCompile>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- <nStopU1X>0</nStopU1X>
- <nStopU2X>0</nStopU2X>
- </BeforeCompile>
- <BeforeMake>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- </BeforeMake>
- <AfterMake>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- </AfterMake>
- <SelectedForBatchBuild>0</SelectedForBatchBuild>
- <SVCSIdString></SVCSIdString>
- </TargetCommonOption>
- <CommonProperty>
- <UseCPPCompiler>0</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>1</IncludeInBuild>
- <AlwaysBuild>0</AlwaysBuild>
- <GenerateAssemblyFile>0</GenerateAssemblyFile>
- <AssembleAssemblyFile>0</AssembleAssemblyFile>
- <PublicsOnly>0</PublicsOnly>
- <StopOnExitCode>3</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- </CommonProperty>
- <DllOption>
- <SimDllName>SARMCM3.DLL</SimDllName>
- <SimDllArguments></SimDllArguments>
- <SimDlgDll>DARMCM1.DLL</SimDlgDll>
- <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
- <TargetDllName>SARMCM3.DLL</TargetDllName>
- <TargetDllArguments></TargetDllArguments>
- <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
- <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
- </DllOption>
- <DebugOption>
- <OPTHX>
- <HexSelection>1</HexSelection>
- <HexRangeLowAddress>0</HexRangeLowAddress>
- <HexRangeHighAddress>0</HexRangeHighAddress>
- <HexOffset>0</HexOffset>
- <Oh166RecLen>16</Oh166RecLen>
- </OPTHX>
- <Simulator>
- <UseSimulator>0</UseSimulator>
- <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
- <RunToMain>0</RunToMain>
- <RestoreBreakpoints>1</RestoreBreakpoints>
- <RestoreWatchpoints>1</RestoreWatchpoints>
- <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
- <RestoreFunctions>1</RestoreFunctions>
- <RestoreToolbox>1</RestoreToolbox>
- <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
- </Simulator>
- <Target>
- <UseTarget>1</UseTarget>
- <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
- <RunToMain>1</RunToMain>
- <RestoreBreakpoints>1</RestoreBreakpoints>
- <RestoreWatchpoints>1</RestoreWatchpoints>
- <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
- <RestoreFunctions>0</RestoreFunctions>
- <RestoreToolbox>1</RestoreToolbox>
- <RestoreTracepoints>1</RestoreTracepoints>
- </Target>
- <RunDebugAfterBuild>0</RunDebugAfterBuild>
- <TargetSelection>7</TargetSelection>
- <SimDlls>
- <CpuDll></CpuDll>
- <CpuDllArguments></CpuDllArguments>
- <PeripheralDll></PeripheralDll>
- <PeripheralDllArguments></PeripheralDllArguments>
- <InitializationFile></InitializationFile>
- </SimDlls>
- <TargetDlls>
- <CpuDll></CpuDll>
- <CpuDllArguments></CpuDllArguments>
- <PeripheralDll></PeripheralDll>
- <PeripheralDllArguments></PeripheralDllArguments>
- <InitializationFile></InitializationFile>
- <Driver>Segger\JL2CM3.dll</Driver>
- </TargetDlls>
- </DebugOption>
- <Utilities>
- <Flash1>
- <UseTargetDll>1</UseTargetDll>
- <UseExternalTool>0</UseExternalTool>
- <RunIndependent>0</RunIndependent>
- <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
- <Capability>1</Capability>
- <DriverSelection>4100</DriverSelection>
- </Flash1>
- <bUseTDR>0</bUseTDR>
- <Flash2>Segger\JL2CM3.dll</Flash2>
- <Flash3>"" ()</Flash3>
- <Flash4></Flash4>
- </Utilities>
- <TargetArmAds>
- <ArmAdsMisc>
- <GenerateListings>0</GenerateListings>
- <asHll>1</asHll>
- <asAsm>1</asAsm>
- <asMacX>1</asMacX>
- <asSyms>1</asSyms>
- <asFals>1</asFals>
- <asDbgD>1</asDbgD>
- <asForm>1</asForm>
- <ldLst>0</ldLst>
- <ldmm>1</ldmm>
- <ldXref>1</ldXref>
- <BigEnd>0</BigEnd>
- <AdsALst>1</AdsALst>
- <AdsACrf>1</AdsACrf>
- <AdsANop>0</AdsANop>
- <AdsANot>0</AdsANot>
- <AdsLLst>1</AdsLLst>
- <AdsLmap>1</AdsLmap>
- <AdsLcgr>1</AdsLcgr>
- <AdsLsym>1</AdsLsym>
- <AdsLszi>1</AdsLszi>
- <AdsLtoi>1</AdsLtoi>
- <AdsLsun>1</AdsLsun>
- <AdsLven>1</AdsLven>
- <AdsLsxf>1</AdsLsxf>
- <RvctClst>0</RvctClst>
- <GenPPlst>0</GenPPlst>
- <AdsCpuType>"Cortex-M0"</AdsCpuType>
- <RvctDeviceName></RvctDeviceName>
- <mOS>0</mOS>
- <uocRom>0</uocRom>
- <uocRam>0</uocRam>
- <hadIROM>1</hadIROM>
- <hadIRAM>1</hadIRAM>
- <hadXRAM>0</hadXRAM>
- <uocXRam>0</uocXRam>
- <RvdsVP>0</RvdsVP>
- <hadIRAM2>0</hadIRAM2>
- <hadIROM2>0</hadIROM2>
- <StupSel>8</StupSel>
- <useUlib>1</useUlib>
- <EndSel>0</EndSel>
- <uLtcg>0</uLtcg>
- <RoSelD>3</RoSelD>
- <RwSelD>3</RwSelD>
- <CodeSel>0</CodeSel>
- <OptFeed>0</OptFeed>
- <NoZi1>0</NoZi1>
- <NoZi2>0</NoZi2>
- <NoZi3>0</NoZi3>
- <NoZi4>0</NoZi4>
- <NoZi5>0</NoZi5>
- <Ro1Chk>0</Ro1Chk>
- <Ro2Chk>0</Ro2Chk>
- <Ro3Chk>0</Ro3Chk>
- <Ir1Chk>1</Ir1Chk>
- <Ir2Chk>0</Ir2Chk>
- <Ra1Chk>0</Ra1Chk>
- <Ra2Chk>0</Ra2Chk>
- <Ra3Chk>0</Ra3Chk>
- <Im1Chk>1</Im1Chk>
- <Im2Chk>0</Im2Chk>
- <OnChipMemories>
- <Ocm1>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm1>
- <Ocm2>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm2>
- <Ocm3>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm3>
- <Ocm4>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm4>
- <Ocm5>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm5>
- <Ocm6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm6>
- <IRAM>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x4000</Size>
- </IRAM>
- <IROM>
- <Type>1</Type>
- <StartAddress>0x10001000</StartAddress>
- <Size>0x32000</Size>
- </IROM>
- <XRAM>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </XRAM>
- <OCR_RVCT1>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT1>
- <OCR_RVCT2>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT2>
- <OCR_RVCT3>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT3>
- <OCR_RVCT4>
- <Type>1</Type>
- <StartAddress>0x10001000</StartAddress>
- <Size>0x32000</Size>
- </OCR_RVCT4>
- <OCR_RVCT5>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT5>
- <OCR_RVCT6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT6>
- <OCR_RVCT7>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT7>
- <OCR_RVCT8>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT8>
- <OCR_RVCT9>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x4000</Size>
- </OCR_RVCT9>
- <OCR_RVCT10>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT10>
- </OnChipMemories>
- <RvctStartVector></RvctStartVector>
- </ArmAdsMisc>
- <Cads>
- <interw>1</interw>
- <Optim>1</Optim>
- <oTime>0</oTime>
- <SplitLS>0</SplitLS>
- <OneElfS>0</OneElfS>
- <Strict>0</Strict>
- <EnumInt>0</EnumInt>
- <PlainCh>0</PlainCh>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>0</uThumb>
- <uSurpInc>0</uSurpInc>
- <VariousControls>
- <MiscControls>--c99</MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath>.;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;.\CMSIS</IncludePath>
- </VariousControls>
- </Cads>
- <Aads>
- <interw>1</interw>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <thumb>0</thumb>
- <SplitLS>0</SplitLS>
- <SwStkChk>0</SwStkChk>
- <NoWarn>0</NoWarn>
- <uSurpInc>0</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Aads>
- <LDads>
- <umfTarg>1</umfTarg>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <noStLib>0</noStLib>
- <RepFail>1</RepFail>
- <useFile>0</useFile>
- <TextAddressRange>0x10001000</TextAddressRange>
- <DataAddressRange>0x20000000</DataAddressRange>
- <ScatterFile>.\Output\RTOSDemo.sct</ScatterFile>
- <IncludeLibs></IncludeLibs>
- <IncludeLibsPath></IncludeLibsPath>
- <Misc></Misc>
- <LinkerInputFile></LinkerInputFile>
- <DisabledWarnings></DisabledWarnings>
- </LDads>
- </TargetArmAds>
- </TargetOption>
- <Groups>
- <Group>
- <GroupName>System</GroupName>
- <Files>
- <File>
- <FileName>system_XMC1200.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\system_XMC1200.c</FilePath>
- </File>
- <File>
- <FileName>startup_XMC1300.s</FileName>
- <FileType>2</FileType>
- <FilePath>.\Keil_Specific\startup_XMC1300.s</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>FreeRTOS source</GroupName>
- <Files>
- <File>
- <FileName>timers.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\timers.c</FilePath>
- </File>
- <File>
- <FileName>list.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\list.c</FilePath>
- </File>
- <File>
- <FileName>queue.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\queue.c</FilePath>
- </File>
- <File>
- <FileName>tasks.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\tasks.c</FilePath>
- </File>
- <File>
- <FileName>port.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\portable\RVDS\ARM_CM0\port.c</FilePath>
- </File>
- <File>
- <FileName>heap_4.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>Demo App Source</GroupName>
- <Files>
- <File>
- <FileName>main.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\main.c</FilePath>
- </File>
- <File>
- <FileName>main-blinky.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\main-blinky.c</FilePath>
- </File>
- <File>
- <FileName>FreeRTOSConfig.h</FileName>
- <FileType>5</FileType>
- <FilePath>.\FreeRTOSConfig.h</FilePath>
- </File>
- <File>
- <FileName>main-full.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\main-full.c</FilePath>
- </File>
- <File>
- <FileName>ParTest_XMC1200.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\ParTest_XMC1200.c</FilePath>
- <FileOption>
- <CommonProperty>
- <UseCPPCompiler>2</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>1</IncludeInBuild>
- <AlwaysBuild>2</AlwaysBuild>
- <GenerateAssemblyFile>2</GenerateAssemblyFile>
- <AssembleAssemblyFile>2</AssembleAssemblyFile>
- <PublicsOnly>2</PublicsOnly>
- <StopOnExitCode>11</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- </CommonProperty>
- <FileArmAds>
- <Cads>
- <interw>2</interw>
- <Optim>0</Optim>
- <oTime>2</oTime>
- <SplitLS>2</SplitLS>
- <OneElfS>2</OneElfS>
- <Strict>2</Strict>
- <EnumInt>2</EnumInt>
- <PlainCh>2</PlainCh>
- <Ropi>2</Ropi>
- <Rwpi>2</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>2</uThumb>
- <uSurpInc>2</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Cads>
- </FileArmAds>
- </FileOption>
- </File>
- <File>
- <FileName>RegTest_Keil.s</FileName>
- <FileType>2</FileType>
- <FilePath>.\Keil_Specific\RegTest_Keil.s</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>Common Demo Tasks</GroupName>
- <Files>
- <File>
- <FileName>dynamic.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\dynamic.c</FilePath>
- </File>
- <File>
- <FileName>recmutex.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\recmutex.c</FilePath>
- </File>
- <File>
- <FileName>blocktim.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\blocktim.c</FilePath>
- </File>
- <File>
- <FileName>countsem.c</FileName>
- <FileType>1</FileType>
- <FilePath>..\Common\Minimal\countsem.c</FilePath>
- </File>
- </Files>
- </Group>
- </Groups>
- </Target>
- </Targets>
-
-</Project>
+++ /dev/null
-\r
-/****************************************************************************************************//**\r
- * @file XMC1200.h\r
- *\r
- * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for\r
- * XMC1200 from Infineon.\r
- *\r
- * @version V1.0.6 (Reference Manual v1.0)\r
- * @date 26. March 2013\r
- *\r
- * @note Generated with SVDConv V2.78b \r
- * from CMSIS SVD File 'XMC1200_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),\r
- *******************************************************************************************************/\r
-\r
-\r
-\r
-/** @addtogroup Infineon\r
- * @{\r
- */\r
-\r
-/** @addtogroup XMC1200\r
- * @{\r
- */\r
-\r
-#ifndef XMC1200_H\r
-#define XMC1200_H\r
-\r
-#ifdef __cplusplus\r
-extern "C" {\r
-#endif\r
-\r
-\r
-/* ------------------------- Interrupt Number Definition ------------------------ */\r
-\r
-typedef enum {\r
-/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */\r
- Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
- HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
- SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
- DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
- PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
- SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
-/* --------------------- XMC1200 Specific Interrupt Numbers --------------------- */\r
- SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */\r
- SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */\r
- SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */\r
- ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */\r
- ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */\r
- ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */\r
- ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */\r
- \r
- USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */\r
- USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */\r
- USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */\r
- USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */\r
- USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */\r
- USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */\r
- \r
- VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */\r
- VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */\r
- VADC0_G0_0_IRQn = 17, /*!< VADC SR2 Interrupt */\r
- VADC0_G0_1_IRQn = 18, /*!< VADC SR3 Interrupt */\r
- VADC0_G1_0_IRQn = 19, /*!< VADC SR4 Interrupt */\r
- VADC0_G1_1_IRQn = 20, /*!< VADC SR5 Interrupt */\r
- \r
- CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */\r
- CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */\r
- CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */\r
- CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */\r
- \r
- LEDTS0_0_IRQn = 29, /*!< LEDTS0 SR0 Interrupt */\r
- LEDTS1_0_IRQn = 30, /*!< LEDTS1 SR0 Interrupt */\r
- \r
- BCCU0_0_IRQn = 31, /*!< BCCU0 SR0 Interrupt */\r
-} IRQn_Type;\r
-\r
-\r
-/** @addtogroup Configuration_of_CMSIS\r
- * @{\r
- */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Processor and Core Peripheral Section ================ */\r
-/* ================================================================================ */\r
-\r
-/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */\r
-#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */\r
-#define __MPU_PRESENT 0 /*!< MPU present or not */\r
-#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-/** @} */ /* End of group Configuration_of_CMSIS */\r
-\r
-#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */\r
-#include "system_XMC1200.h" /*!< XMC1200 System */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Device Specific Peripheral Section ================ */\r
-/* ================================================================================ */\r
-/* Macro to modify desired bitfields of a register */\r
-#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \\r
- ((uint32_t)mask)) | \\r
- (reg & ((uint32_t)~((uint32_t)mask)))\r
-\r
-/* Macro to modify desired bitfields of a register */\r
-#define WR_REG_SIZE(reg, mask, pos, val, size) { \\r
-uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \\r
-uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \\r
-uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \\r
-uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \\r
-reg = (uint##size##_t) (VAL2 | VAL4);\\r
-}\r
-\r
-/** Macro to read bitfields from a register */\r
-#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)\r
-\r
-/** Macro to read bitfields from a register */\r
-#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \\r
- (uint32_t)mask) >> pos) )\r
-\r
-/** Macro to set a bit in register */\r
-#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))\r
-\r
-/** Macro to clear a bit in register */\r
-#define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )\r
-/*\r
-* ==========================================================================\r
-* ---------- Interrupt Handler Definition ----------------------------------\r
-* ==========================================================================\r
-*/\r
-#define IRQ_Hdlr_0 SCU_0_IRQHandler\r
-#define IRQ_Hdlr_1 SCU_1_IRQHandler\r
-#define IRQ_Hdlr_2 SCU_2_IRQHandler\r
-#define IRQ_Hdlr_3 ERU0_0_IRQHandler\r
-#define IRQ_Hdlr_4 ERU0_1_IRQHandler\r
-#define IRQ_Hdlr_5 ERU0_2_IRQHandler\r
-#define IRQ_Hdlr_6 ERU0_3_IRQHandler\r
-\r
-#define IRQ_Hdlr_9 USIC0_0_IRQHandler\r
-#define IRQ_Hdlr_10 USIC0_1_IRQHandler\r
-#define IRQ_Hdlr_11 USIC0_2_IRQHandler\r
-#define IRQ_Hdlr_12 USIC0_3_IRQHandler\r
-#define IRQ_Hdlr_13 USIC0_4_IRQHandler\r
-#define IRQ_Hdlr_14 USIC0_5_IRQHandler\r
-#define IRQ_Hdlr_15 VADC0_C0_0_IRQHandler\r
-#define IRQ_Hdlr_16 VADC0_C0_1_IRQHandler\r
-#define IRQ_Hdlr_17 VADC0_G0_0_IRQHandler\r
-#define IRQ_Hdlr_18 VADC0_G0_1_IRQHandler\r
-#define IRQ_Hdlr_19 VADC0_G1_0_IRQHandler\r
-#define IRQ_Hdlr_20 VADC0_G1_1_IRQHandler\r
-#define IRQ_Hdlr_21 CCU40_0_IRQHandler\r
-#define IRQ_Hdlr_22 CCU40_1_IRQHandler\r
-#define IRQ_Hdlr_23 CCU40_2_IRQHandler\r
-#define IRQ_Hdlr_24 CCU40_3_IRQHandler\r
-#define IRQ_Hdlr_29 LEDTS0_0_IRQHandler\r
-#define IRQ_Hdlr_30 LEDTS1_0_IRQHandler\r
-#define IRQ_Hdlr_31 BCCU0_0_IRQHandler\r
-\r
-/*\r
-* ==========================================================================\r
-* ---------- Interrupt Handler retrieval macro -----------------------------\r
-* ==========================================================================\r
-*/\r
-#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N\r
-\r
-\r
-/** @addtogroup Device_Peripheral_Registers\r
- * @{\r
- */\r
-\r
-\r
-/* ------------------- Start of section using anonymous unions ------------------ */\r
-#if defined(__CC_ARM)\r
- #pragma push\r
- #pragma anon_unions\r
-#elif defined(__ICCARM__)\r
- #pragma language=extended\r
-#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__TMS470__)\r
-/* anonymous unions are enabled by default */\r
-#elif defined(__TASKING__)\r
- #pragma warning 586\r
-#else\r
- #warning Not supported compiler type\r
-#endif\r
-\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PPB ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Cortex-M0 Private Peripheral Block (PPB)\r
- */\r
-\r
-typedef struct { /*!< (@ 0xE000E000) PPB Structure */\r
- __I uint32_t RESERVED0[4];\r
- __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */\r
- __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */\r
- __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */\r
- __I uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register */\r
- __I uint32_t RESERVED1[56];\r
- __IO uint32_t NVIC_ISER; /*!< (@ 0xE000E100) Interrupt Set-enable Register */\r
- __I uint32_t RESERVED2[31];\r
- __IO uint32_t NVIC_ICER; /*!< (@ 0xE000E180) IInterrupt Clear-enable Register */\r
- __I uint32_t RESERVED3[31];\r
- __IO uint32_t NVIC_ISPR; /*!< (@ 0xE000E200) Interrupt Set-pending Register */\r
- __I uint32_t RESERVED4[31];\r
- __IO uint32_t NVIC_ICPR; /*!< (@ 0xE000E280) Interrupt Clear-pending Register */\r
- __I uint32_t RESERVED5[95];\r
- __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */\r
- __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */\r
- __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */\r
- __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */\r
- __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */\r
- __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */\r
- __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */\r
- __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */\r
- __I uint32_t RESERVED6[568];\r
- __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */\r
- __I uint32_t RESERVED7;\r
- __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */\r
- __I uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */\r
- __I uint32_t RESERVED8;\r
- __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */\r
- __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */\r
- __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */\r
-} PPB_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ ERU [ERU0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Event Request Unit 0 (ERU)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010600) ERU Structure */\r
- __IO uint32_t EXISEL; /*!< (@ 0x40010600) Event Input Select */\r
- __I uint32_t RESERVED0[3];\r
- __IO uint32_t EXICON[4]; /*!< (@ 0x40010610) Event Input Control */\r
- __IO uint32_t EXOCON[4]; /*!< (@ 0x40010620) Event Output Trigger Control */\r
-} ERU_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PAU ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief PAU Unit (PAU)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40000000) PAU Structure */\r
- __I uint32_t RESERVED0[16];\r
- __I uint32_t AVAIL0; /*!< (@ 0x40000040) Peripheral Availability Register 0 */\r
- __I uint32_t AVAIL1; /*!< (@ 0x40000044) Peripheral Availability Register 1 */\r
- __I uint32_t AVAIL2; /*!< (@ 0x40000048) Peripheral Availability Register 2 */\r
- __I uint32_t RESERVED1[13];\r
- __IO uint32_t PRIVDIS0; /*!< (@ 0x40000080) Peripheral Privilege Access Register 0 */\r
- __IO uint32_t PRIVDIS1; /*!< (@ 0x40000084) Peripheral Privilege Access Register 1 */\r
- __IO uint32_t PRIVDIS2; /*!< (@ 0x40000088) Peripheral Privilege Access Register 2 */\r
- __I uint32_t RESERVED2[221];\r
- __I uint32_t ROMSIZE; /*!< (@ 0x40000400) ROM Size Register */\r
- __I uint32_t FLSIZE; /*!< (@ 0x40000404) Flash Size Register */\r
- __I uint32_t RESERVED3[2];\r
- __I uint32_t RAM0SIZE; /*!< (@ 0x40000410) RAM0 Size Register */\r
-} PAU_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ NVM ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief NVM Unit (NVM)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40050000) NVM Structure */\r
- __I uint16_t NVMSTATUS; /*!< (@ 0x40050000) NVM Status Register */\r
- __I uint16_t RESERVED0;\r
- __IO uint16_t NVMPROG; /*!< (@ 0x40050004) NVM Programming Control Register */\r
- __I uint16_t RESERVED1;\r
- __IO uint16_t NVMCONF; /*!< (@ 0x40050008) NVM Configuration Register */\r
-} NVM_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ WDT ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Watch Dog Timer (WDT)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40020000) WDT Structure */\r
- __I uint32_t ID; /*!< (@ 0x40020000) WDT Module ID Register */\r
- __IO uint32_t CTR; /*!< (@ 0x40020004) WDT Control Register */\r
- __O uint32_t SRV; /*!< (@ 0x40020008) WDT Service Register */\r
- __I uint32_t TIM; /*!< (@ 0x4002000C) WDT Timer Register */\r
- __IO uint32_t WLB; /*!< (@ 0x40020010) WDT Window Lower Bound Register */\r
- __IO uint32_t WUB; /*!< (@ 0x40020014) WDT Window Upper Bound Register */\r
- __I uint32_t WDTSTS; /*!< (@ 0x40020018) WDT Status Register */\r
- __O uint32_t WDTCLR; /*!< (@ 0x4002001C) WDT Clear Register */\r
-} WDT_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ RTC ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Real Time Clock (RTC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010A00) RTC Structure */\r
- __I uint32_t ID; /*!< (@ 0x40010A00) RTC Module ID Register */\r
- __IO uint32_t CTR; /*!< (@ 0x40010A04) RTC Control Register */\r
- __I uint32_t RAWSTAT; /*!< (@ 0x40010A08) RTC Raw Service Request Register */\r
- __I uint32_t STSSR; /*!< (@ 0x40010A0C) RTC Service Request Status Register */\r
- __IO uint32_t MSKSR; /*!< (@ 0x40010A10) RTC Service Request Mask Register */\r
- __O uint32_t CLRSR; /*!< (@ 0x40010A14) RTC Clear Service Request Register */\r
- __IO uint32_t ATIM0; /*!< (@ 0x40010A18) RTC Alarm Time Register 0 */\r
- __IO uint32_t ATIM1; /*!< (@ 0x40010A1C) RTC Alarm Time Register 1 */\r
- __IO uint32_t TIM0; /*!< (@ 0x40010A20) RTC Time Register 0 */\r
- __IO uint32_t TIM1; /*!< (@ 0x40010A24) RTC Time Register 1 */\r
-} RTC_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PRNG ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief PRNG Unit (PRNG)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48020000) PRNG Structure */\r
- __IO uint16_t WORD; /*!< (@ 0x48020000) Pseudo RNG Word Register */\r
- __I uint16_t RESERVED0;\r
- __I uint16_t CHK; /*!< (@ 0x48020004) Pseudo RNG Status Check Register */\r
- __I uint16_t RESERVED1[3];\r
- __IO uint16_t CTRL; /*!< (@ 0x4802000C) Pseudo RNG Control Register */\r
-} PRNG_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ LEDTS [LEDTS0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief LED and Touch Sense Unit 0 (LEDTS)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x50020000) LEDTS Structure */\r
- __I uint32_t ID; /*!< (@ 0x50020000) Module Identification Register */\r
- __IO uint32_t GLOBCTL; /*!< (@ 0x50020004) Global Control Register */\r
- __IO uint32_t FNCTL; /*!< (@ 0x50020008) Function Control Register */\r
- __O uint32_t EVFR; /*!< (@ 0x5002000C) Event Flag Register */\r
- __IO uint32_t TSVAL; /*!< (@ 0x50020010) Touch-sense TS-Counter Value */\r
- __IO uint32_t LINE0; /*!< (@ 0x50020014) Line Pattern Register 0 */\r
- __IO uint32_t LINE1; /*!< (@ 0x50020018) Line Pattern Register 1 */\r
- __IO uint32_t LDCMP0; /*!< (@ 0x5002001C) LED Compare Register 0 */\r
- __IO uint32_t LDCMP1; /*!< (@ 0x50020020) LED Compare Register 1 */\r
- __IO uint32_t TSCMP0; /*!< (@ 0x50020024) Touch-sense Compare Register 0 */\r
- __IO uint32_t TSCMP1; /*!< (@ 0x50020028) Touch-sense Compare Register 1 */\r
-} LEDTS0_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ USIC [USIC0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Universal Serial Interface Controller 0 (USIC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48000008) USIC Structure */\r
- __I uint32_t ID; /*!< (@ 0x48000008) Module Identification Register */\r
-} USIC_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ USIC_CH [USIC0_CH0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Universal Serial Interface Controller 0 (USIC_CH)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48000000) USIC_CH Structure */\r
- __I uint32_t RESERVED0;\r
- __I uint32_t CCFG; /*!< (@ 0x48000004) Channel Configuration Register */\r
- __I uint32_t RESERVED1;\r
- __IO uint32_t KSCFG; /*!< (@ 0x4800000C) Kernel State Configuration Register */\r
- __IO uint32_t FDR; /*!< (@ 0x48000010) Fractional Divider Register */\r
- __IO uint32_t BRG; /*!< (@ 0x48000014) Baud Rate Generator Register */\r
- __IO uint32_t INPR; /*!< (@ 0x48000018) Interrupt Node Pointer Register */\r
- __IO uint32_t DX0CR; /*!< (@ 0x4800001C) Input Control Register 0 */\r
- __IO uint32_t DX1CR; /*!< (@ 0x48000020) Input Control Register 1 */\r
- __IO uint32_t DX2CR; /*!< (@ 0x48000024) Input Control Register 2 */\r
- __IO uint32_t DX3CR; /*!< (@ 0x48000028) Input Control Register 3 */\r
- __IO uint32_t DX4CR; /*!< (@ 0x4800002C) Input Control Register 4 */\r
- __IO uint32_t DX5CR; /*!< (@ 0x48000030) Input Control Register 5 */\r
- __IO uint32_t SCTR; /*!< (@ 0x48000034) Shift Control Register */\r
- __IO uint32_t TCSR; /*!< (@ 0x48000038) Transmit Control/Status Register */\r
- \r
- union {\r
- __IO uint32_t PCR_IICMode; /*!< (@ 0x4800003C) Protocol Control Register [IIC Mode] */\r
- __IO uint32_t PCR_IISMode; /*!< (@ 0x4800003C) Protocol Control Register [IIS Mode] */\r
- __IO uint32_t PCR_SSCMode; /*!< (@ 0x4800003C) Protocol Control Register [SSC Mode] */\r
- __IO uint32_t PCR; /*!< (@ 0x4800003C) Protocol Control Register */\r
- __IO uint32_t PCR_ASCMode; /*!< (@ 0x4800003C) Protocol Control Register [ASC Mode] */\r
- };\r
- __IO uint32_t CCR; /*!< (@ 0x48000040) Channel Control Register */\r
- __IO uint32_t CMTR; /*!< (@ 0x48000044) Capture Mode Timer Register */\r
- \r
- union {\r
- __IO uint32_t PSR_IICMode; /*!< (@ 0x48000048) Protocol Status Register [IIC Mode] */\r
- __IO uint32_t PSR_IISMode; /*!< (@ 0x48000048) Protocol Status Register [IIS Mode] */\r
- __IO uint32_t PSR_SSCMode; /*!< (@ 0x48000048) Protocol Status Register [SSC Mode] */\r
- __IO uint32_t PSR; /*!< (@ 0x48000048) Protocol Status Register */\r
- __IO uint32_t PSR_ASCMode; /*!< (@ 0x48000048) Protocol Status Register [ASC Mode] */\r
- };\r
- __O uint32_t PSCR; /*!< (@ 0x4800004C) Protocol Status Clear Register */\r
- __I uint32_t RBUFSR; /*!< (@ 0x48000050) Receiver Buffer Status Register */\r
- __I uint32_t RBUF; /*!< (@ 0x48000054) Receiver Buffer Register */\r
- __I uint32_t RBUFD; /*!< (@ 0x48000058) Receiver Buffer Register for Debugger */\r
- __I uint32_t RBUF0; /*!< (@ 0x4800005C) Receiver Buffer Register 0 */\r
- __I uint32_t RBUF1; /*!< (@ 0x48000060) Receiver Buffer Register 1 */\r
- __I uint32_t RBUF01SR; /*!< (@ 0x48000064) Receiver Buffer 01 Status Register */\r
- __O uint32_t FMR; /*!< (@ 0x48000068) Flag Modification Register */\r
- __I uint32_t RESERVED2[5];\r
- __IO uint32_t TBUF[32]; /*!< (@ 0x48000080) Transmit Buffer */\r
- __IO uint32_t BYP; /*!< (@ 0x48000100) Bypass Data Register */\r
- __IO uint32_t BYPCR; /*!< (@ 0x48000104) Bypass Control Register */\r
- __IO uint32_t TBCTR; /*!< (@ 0x48000108) Transmitter Buffer Control Register */\r
- __IO uint32_t RBCTR; /*!< (@ 0x4800010C) Receiver Buffer Control Register */\r
- __I uint32_t TRBPTR; /*!< (@ 0x48000110) Transmit/Receive Buffer Pointer Register */\r
- __IO uint32_t TRBSR; /*!< (@ 0x48000114) Transmit/Receive Buffer Status Register */\r
- __O uint32_t TRBSCR; /*!< (@ 0x48000118) Transmit/Receive Buffer Status Clear Register */\r
- __I uint32_t OUTR; /*!< (@ 0x4800011C) Receiver Buffer Output Register */\r
- __I uint32_t OUTDR; /*!< (@ 0x48000120) Receiver Buffer Output Register L for Debugger */\r
- __I uint32_t RESERVED3[23];\r
- __O uint32_t IN[32]; /*!< (@ 0x48000180) Transmit FIFO Buffer */\r
-} USIC_CH_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SCU_GENERAL ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (SCU_GENERAL)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010000) SCU_GENERAL Structure */\r
- __I uint32_t DBGROMID; /*!< (@ 0x40010000) Debug System ROM ID Register */\r
- __I uint32_t IDCHIP; /*!< (@ 0x40010004) Chip ID Register */\r
- __I uint32_t ID; /*!< (@ 0x40010008) SCU Module ID Register */\r
- __I uint32_t RESERVED0[2];\r
- __IO uint32_t SSW0; /*!< (@ 0x40010014) SSW Register 0 */\r
- __I uint32_t RESERVED1[3];\r
- __IO uint32_t PASSWD; /*!< (@ 0x40010024) Password Register */\r
- __I uint32_t RESERVED2[2];\r
- __IO uint32_t CCUCON; /*!< (@ 0x40010030) CCU Control Register */\r
- __I uint32_t RESERVED3[5];\r
- __I uint32_t MIRRSTS; /*!< (@ 0x40010048) Mirror Update Status Register */\r
- __I uint32_t RESERVED4[2];\r
- __IO uint32_t PMTSR; /*!< (@ 0x40010054) Parity Memory Test Select Register */\r
-} SCU_GENERAL_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SCU_INTERRUPT ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (SCU_INTERRUPT)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010038) SCU_INTERRUPT Structure */\r
- __I uint32_t SRRAW; /*!< (@ 0x40010038) SCU Raw Service Request Status */\r
- __IO uint32_t SRMSK; /*!< (@ 0x4001003C) SCU Service Request Mask */\r
- __O uint32_t SRCLR; /*!< (@ 0x40010040) SCU Service Request Clear */\r
- __O uint32_t SRSET; /*!< (@ 0x40010044) SCU Service Request Set */\r
-} SCU_INTERRUPT_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SCU_POWER ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (SCU_POWER)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010200) SCU_POWER Structure */\r
- __I uint32_t VDESR; /*!< (@ 0x40010200) Voltage Detector Status Register */\r
-} SCU_POWER_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SCU_CLK ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (SCU_CLK)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010300) SCU_CLK Structure */\r
- __IO uint32_t CLKCR; /*!< (@ 0x40010300) Clock Control Register */\r
- __IO uint32_t PWRSVCR; /*!< (@ 0x40010304) Power Save Control Register */\r
- __I uint32_t CGATSTAT0; /*!< (@ 0x40010308) Peripheral 0 Clock Gating Status */\r
- __O uint32_t CGATSET0; /*!< (@ 0x4001030C) Peripheral 0 Clock Gating Set */\r
- __O uint32_t CGATCLR0; /*!< (@ 0x40010310) Peripheral 0 Clock Gating Clear */\r
- __IO uint32_t OSCCSR; /*!< (@ 0x40010314) Oscillator Control and Status Register */\r
-} SCU_CLK_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SCU_RESET ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (SCU_RESET)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010400) SCU_RESET Structure */\r
- __I uint32_t RSTSTAT; /*!< (@ 0x40010400) RCU Reset Status */\r
- __O uint32_t RSTSET; /*!< (@ 0x40010404) RCU Reset Set Register */\r
- __O uint32_t RSTCLR; /*!< (@ 0x40010408) RCU Reset Clear Register */\r
- __IO uint32_t RSTCON; /*!< (@ 0x4001040C) RCU Reset Control Register */\r
-} SCU_RESET_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ COMPARATOR ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (COMPARATOR)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40010500) COMPARATOR Structure */\r
- __IO uint32_t ORCCTRL; /*!< (@ 0x40010500) Out Of Range Comparator Control Register */\r
- __I uint32_t RESERVED0[726];\r
- __IO uint16_t ANACMP0; /*!< (@ 0x4001105C) Analog Comparator 0 Control Register */\r
- __I uint16_t RESERVED1;\r
- __IO uint16_t ANACMP1; /*!< (@ 0x40011060) Analog Comparator 1 Control Register */\r
- __I uint16_t RESERVED2;\r
- __IO uint16_t ANACMP2; /*!< (@ 0x40011064) Analog Comparator 2 Control Register */\r
-} COMPARATOR_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SCU_ANALOG ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief System Control Unit (SCU_ANALOG)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40011000) SCU_ANALOG Structure */\r
- __I uint32_t RESERVED0[9];\r
- __IO uint16_t ANATSECTRL; /*!< (@ 0x40011024) Temperature Sensor Control Register */\r
- __I uint16_t RESERVED1[5];\r
- __IO uint16_t ANATSEIH; /*!< (@ 0x40011030) Temperature Sensor High Temperature Interrupt\r
- Register */\r
- __I uint16_t RESERVED2;\r
- __IO uint16_t ANATSEIL; /*!< (@ 0x40011034) Temperature Sensor Low Temperature Interrupt\r
- Register */\r
- __I uint16_t RESERVED3[5];\r
- __I uint16_t ANATSEMON; /*!< (@ 0x40011040) Temperature Sensor Counter2 Monitor Register */\r
- __I uint16_t RESERVED4[7];\r
- __IO uint16_t ANAVDEL; /*!< (@ 0x40011050) Voltage Detector Control Register */\r
- __I uint16_t RESERVED5[13];\r
- __IO uint16_t ANAOFFSET; /*!< (@ 0x4001106C) DCO1 Offset Register */\r
-} SCU_ANALOG_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ CCU4 [CCU40] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Capture Compare Unit 4 - Unit 0 (CCU4)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48040000) CCU4 Structure */\r
- __IO uint32_t GCTRL; /*!< (@ 0x48040000) Global Control Register */\r
- __I uint32_t GSTAT; /*!< (@ 0x48040004) Global Status Register */\r
- __O uint32_t GIDLS; /*!< (@ 0x48040008) Global Idle Set */\r
- __O uint32_t GIDLC; /*!< (@ 0x4804000C) Global Idle Clear */\r
- __O uint32_t GCSS; /*!< (@ 0x48040010) Global Channel Set */\r
- __O uint32_t GCSC; /*!< (@ 0x48040014) Global Channel Clear */\r
- __I uint32_t GCST; /*!< (@ 0x48040018) Global Channel Status */\r
- __I uint32_t RESERVED0[25];\r
- __I uint32_t MIDR; /*!< (@ 0x48040080) Module Identification */\r
-} CCU4_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ CCU4_CC4 [CCU40_CC40] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48040100) CCU4_CC4 Structure */\r
- __IO uint32_t INS; /*!< (@ 0x48040100) Input Selector Configuration */\r
- __IO uint32_t CMC; /*!< (@ 0x48040104) Connection Matrix Control */\r
- __I uint32_t TCST; /*!< (@ 0x48040108) Slice Timer Status */\r
- __O uint32_t TCSET; /*!< (@ 0x4804010C) Slice Timer Run Set */\r
- __O uint32_t TCCLR; /*!< (@ 0x48040110) Slice Timer Clear */\r
- __IO uint32_t TC; /*!< (@ 0x48040114) Slice Timer Control */\r
- __IO uint32_t PSL; /*!< (@ 0x48040118) Passive Level Config */\r
- __I uint32_t DIT; /*!< (@ 0x4804011C) Dither Config */\r
- __IO uint32_t DITS; /*!< (@ 0x48040120) Dither Shadow Register */\r
- __IO uint32_t PSC; /*!< (@ 0x48040124) Prescaler Control */\r
- __IO uint32_t FPC; /*!< (@ 0x48040128) Floating Prescaler Control */\r
- __IO uint32_t FPCS; /*!< (@ 0x4804012C) Floating Prescaler Shadow */\r
- __I uint32_t PR; /*!< (@ 0x48040130) Timer Period Value */\r
- __IO uint32_t PRS; /*!< (@ 0x48040134) Timer Shadow Period Value */\r
- __I uint32_t CR; /*!< (@ 0x48040138) Timer Compare Value */\r
- __IO uint32_t CRS; /*!< (@ 0x4804013C) Timer Shadow Compare Value */\r
- __I uint32_t RESERVED0[12];\r
- __IO uint32_t TIMER; /*!< (@ 0x48040170) Timer Value */\r
- __I uint32_t CV[4]; /*!< (@ 0x48040174) Capture Register 0 */\r
- __I uint32_t RESERVED1[7];\r
- __I uint32_t INTS; /*!< (@ 0x480401A0) Interrupt Status */\r
- __IO uint32_t INTE; /*!< (@ 0x480401A4) Interrupt Enable Control */\r
- __IO uint32_t SRS; /*!< (@ 0x480401A8) Service Request Selector */\r
- __O uint32_t SWS; /*!< (@ 0x480401AC) Interrupt Status Set */\r
- __O uint32_t SWR; /*!< (@ 0x480401B0) Interrupt Status Clear */\r
- __I uint32_t RESERVED2;\r
- __I uint32_t ECRD0; /*!< (@ 0x480401B8) Extended Read Back 0 */\r
- __I uint32_t ECRD1; /*!< (@ 0x480401BC) Extended Read Back 1 */\r
-} CCU4_CC4_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ VADC [VADC] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Analog to Digital Converter (VADC)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48030000) VADC Structure */\r
- __IO uint32_t CLC; /*!< (@ 0x48030000) Clock Control Register */\r
- __I uint32_t RESERVED0;\r
- __I uint32_t ID; /*!< (@ 0x48030008) Module Identification Register */\r
- __I uint32_t RESERVED1[7];\r
- __IO uint32_t OCS; /*!< (@ 0x48030028) OCDS Control and Status Register */\r
- __I uint32_t RESERVED2[21];\r
- __IO uint32_t GLOBCFG; /*!< (@ 0x48030080) Global Configuration Register */\r
- __I uint32_t RESERVED3;\r
- __IO uint32_t ACCPROT0; /*!< (@ 0x48030088) Access Protection Register */\r
- __IO uint32_t ACCPROT1; /*!< (@ 0x4803008C) Access Protection Register */\r
- __I uint32_t RESERVED4[4];\r
- __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x480300A0) Input Class Register, Global */\r
- __I uint32_t RESERVED5[4];\r
- __IO uint32_t GLOBBOUND; /*!< (@ 0x480300B8) Global Boundary Select Register */\r
- __I uint32_t RESERVED6[9];\r
- __IO uint32_t GLOBEFLAG; /*!< (@ 0x480300E0) Global Event Flag Register */\r
- __I uint32_t RESERVED7[23];\r
- __IO uint32_t GLOBEVNP; /*!< (@ 0x48030140) Global Event Node Pointer Register */\r
- __I uint32_t RESERVED8[15];\r
- __IO uint32_t BRSSEL[2]; /*!< (@ 0x48030180) Background Request Source Channel Select Register */\r
- __I uint32_t RESERVED9[14];\r
- __IO uint32_t BRSPND[2]; /*!< (@ 0x480301C0) Background Request Source Pending Register */\r
- __I uint32_t RESERVED10[14];\r
- __IO uint32_t BRSCTRL; /*!< (@ 0x48030200) Background Request Source Control Register */\r
- __IO uint32_t BRSMR; /*!< (@ 0x48030204) Background Request Source Mode Register */\r
- __I uint32_t RESERVED11[30];\r
- __IO uint32_t GLOBRCR; /*!< (@ 0x48030280) Global Result Control Register */\r
- __I uint32_t RESERVED12[31];\r
- __IO uint32_t GLOBRES; /*!< (@ 0x48030300) Global Result Register */\r
- __I uint32_t RESERVED13[31];\r
- __IO uint32_t GLOBRESD; /*!< (@ 0x48030380) Global Result Register, Debug */\r
- __I uint32_t RESERVED14[27];\r
- __IO uint32_t EMUXSEL; /*!< (@ 0x480303F0) External Multiplexer Select Register */\r
-} VADC_GLOBAL_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ VADC_G [VADC_G0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Analog to Digital Converter (VADC_G)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48030400) VADC_G Structure */\r
- __I uint32_t RESERVED0[32];\r
- __IO uint32_t ARBCFG; /*!< (@ 0x48030480) Arbitration Configuration Register */\r
- __IO uint32_t ARBPR; /*!< (@ 0x48030484) Arbitration Priority Register */\r
- __IO uint32_t CHASS; /*!< (@ 0x48030488) Channel Assignment Register */\r
- __IO uint32_t RRASS; /*!< (@ 0x4803048C) Result Assignment Register */\r
- __I uint32_t RESERVED1[4];\r
- __IO uint32_t ICLASS[2]; /*!< (@ 0x480304A0) Input Class Register 0 */\r
- __I uint32_t RESERVED2[2];\r
- __IO uint32_t ALIAS; /*!< (@ 0x480304B0) Alias Register */\r
- __I uint32_t RESERVED3;\r
- __IO uint32_t BOUND; /*!< (@ 0x480304B8) Boundary Select Register */\r
- __I uint32_t RESERVED4;\r
- __IO uint32_t SYNCTR; /*!< (@ 0x480304C0) Synchronization Control Register */\r
- __I uint32_t RESERVED5;\r
- __IO uint32_t BFL; /*!< (@ 0x480304C8) Boundary Flag Register */\r
- __O uint32_t BFLS; /*!< (@ 0x480304CC) Boundary Flag Software Register */\r
- __IO uint32_t BFLC; /*!< (@ 0x480304D0) Boundary Flag Control Register */\r
- __IO uint32_t BFLNP; /*!< (@ 0x480304D4) Boundary Flag Node Pointer Register */\r
- __I uint32_t RESERVED6[10];\r
- __IO uint32_t QCTRL0; /*!< (@ 0x48030500) Queue 0 Source Control Register */\r
- __IO uint32_t QMR0; /*!< (@ 0x48030504) Queue 0 Mode Register */\r
- __I uint32_t QSR0; /*!< (@ 0x48030508) Queue 0 Status Register */\r
- __I uint32_t Q0R0; /*!< (@ 0x4803050C) Queue 0 Register 0 */\r
- \r
- union {\r
- __I uint32_t QBUR0; /*!< (@ 0x48030510) Queue 0 Backup Register */\r
- __O uint32_t QINR0; /*!< (@ 0x48030510) Queue 0 Input Register */\r
- };\r
- __I uint32_t RESERVED7[3];\r
- __IO uint32_t ASCTRL; /*!< (@ 0x48030520) Autoscan Source Control Register */\r
- __IO uint32_t ASMR; /*!< (@ 0x48030524) Autoscan Source Mode Register */\r
- __IO uint32_t ASSEL; /*!< (@ 0x48030528) Autoscan Source Channel Select Register */\r
- __IO uint32_t ASPND; /*!< (@ 0x4803052C) Autoscan Source Pending Register */\r
- __I uint32_t RESERVED8[20];\r
- __IO uint32_t CEFLAG; /*!< (@ 0x48030580) Channel Event Flag Register */\r
- __IO uint32_t REFLAG; /*!< (@ 0x48030584) Result Event Flag Register */\r
- __IO uint32_t SEFLAG; /*!< (@ 0x48030588) Source Event Flag Register */\r
- __I uint32_t RESERVED9;\r
- __O uint32_t CEFCLR; /*!< (@ 0x48030590) Channel Event Flag Clear Register */\r
- __O uint32_t REFCLR; /*!< (@ 0x48030594) Result Event Flag Clear Register */\r
- __O uint32_t SEFCLR; /*!< (@ 0x48030598) Source Event Flag Clear Register */\r
- __I uint32_t RESERVED10;\r
- __IO uint32_t CEVNP0; /*!< (@ 0x480305A0) Channel Event Node Pointer Register 0 */\r
- __I uint32_t RESERVED11[3];\r
- __IO uint32_t REVNP0; /*!< (@ 0x480305B0) Result Event Node Pointer Register 0 */\r
- __IO uint32_t REVNP1; /*!< (@ 0x480305B4) Result Event Node Pointer Register 1 */\r
- __I uint32_t RESERVED12[2];\r
- __IO uint32_t SEVNP; /*!< (@ 0x480305C0) Source Event Node Pointer Register */\r
- __I uint32_t RESERVED13;\r
- __O uint32_t SRACT; /*!< (@ 0x480305C8) Service Request Software Activation Trigger */\r
- __I uint32_t RESERVED14[9];\r
- __IO uint32_t EMUXCTR; /*!< (@ 0x480305F0) E0ternal Multiplexer Control Register, Group\r
- x */\r
- __I uint32_t RESERVED15;\r
- __IO uint32_t VFR; /*!< (@ 0x480305F8) Valid Flag Register, Group 0 */\r
- __I uint32_t RESERVED16;\r
- __IO uint32_t CHCTR[8]; /*!< (@ 0x48030600) Channel Ctrl. Reg. */\r
- __I uint32_t RESERVED17[24];\r
- __IO uint32_t RCR[16]; /*!< (@ 0x48030680) Result Control Reg. */\r
- __I uint32_t RESERVED18[16];\r
- __IO uint32_t RES[16]; /*!< (@ 0x48030700) Result Register */\r
- __I uint32_t RESERVED19[16];\r
- __I uint32_t RESD[16]; /*!< (@ 0x48030780) Result Register, Debug */\r
-} VADC_G_TypeDef;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ SHS [SHS0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Sample and Hold ADC Sequencer (SHS)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x48034000) SHS Structure */\r
- __I uint32_t RESERVED0[2];\r
- __I uint32_t ID; /*!< (@ 0x48034008) Module Identification Register */\r
- __I uint32_t RESERVED1[13];\r
- __IO uint32_t SHSCFG; /*!< (@ 0x48034040) SHS Configuration Register */\r
- __IO uint32_t STEPCFG; /*!< (@ 0x48034044) Stepper Configuration Register */\r
- __I uint32_t RESERVED2[2];\r
- __IO uint32_t LOOP; /*!< (@ 0x48034050) Loop Control Register */\r
- __I uint32_t RESERVED3[11];\r
- __IO uint32_t TIMCFG0; /*!< (@ 0x48034080) Timing Configuration Register 0 */\r
- __IO uint32_t TIMCFG1; /*!< (@ 0x48034084) Timing Configuration Register 1 */\r
- __I uint32_t RESERVED4[13];\r
- __IO uint32_t CALCTR; /*!< (@ 0x480340BC) Calibration Control Register */\r
- __IO uint32_t CALGC0; /*!< (@ 0x480340C0) Gain Calibration Control Register 0 */\r
- __IO uint32_t CALGC1; /*!< (@ 0x480340C4) Gain Calibration Control Register 1 */\r
- __I uint32_t RESERVED5[46];\r
- __IO uint32_t GNCTR00; /*!< (@ 0x48034180) Gain Control Register 00 */\r
- __I uint32_t RESERVED6[3];\r
- __IO uint32_t GNCTR10; /*!< (@ 0x48034190) Gain Control Register 10 */\r
-} SHS_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ BCCU [BCCU0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief BCCU Unit 0 (BCCU)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x50030000) BCCU Structure */\r
- __IO uint32_t GLOBCON; /*!< (@ 0x50030000) Global Control */\r
- __IO uint32_t GLOBCLK; /*!< (@ 0x50030004) Global Clock */\r
- __I uint32_t ID; /*!< (@ 0x50030008) Module Identification */\r
- __IO uint32_t CHEN; /*!< (@ 0x5003000C) Channel Enable */\r
- __IO uint32_t CHOCON; /*!< (@ 0x50030010) Channel Output Control */\r
- __IO uint32_t CHTRIG; /*!< (@ 0x50030014) Channel Trigger */\r
- __IO uint32_t CHSTRCON; /*!< (@ 0x50030018) Channel Shadow Transfer */\r
- __I uint32_t LTCHOL; /*!< (@ 0x5003001C) Last Trigger Channel Output Level */\r
- __IO uint32_t DEEN; /*!< (@ 0x50030020) Dimming Engine Enable */\r
- __IO uint32_t DESTRCON; /*!< (@ 0x50030024) Dimming Shadow Transfer */\r
- __IO uint32_t GLOBDIM; /*!< (@ 0x50030028) Global Dimming Level */\r
- __IO uint32_t EVIER; /*!< (@ 0x5003002C) Event Interrupt Enable */\r
- __I uint32_t EVFR; /*!< (@ 0x50030030) Event Flag */\r
- __O uint32_t EVFSR; /*!< (@ 0x50030034) Event Flag Set */\r
- __O uint32_t EVFCR; /*!< (@ 0x50030038) Event Flag Clear */\r
-} BCCU_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ BCCU_CH [BCCU0_CH0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief BCCU Unit 0 (BCCU_CH)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x5003003C) BCCU_CH Structure */\r
- __IO uint32_t INTS; /*!< (@ 0x5003003C) Channel Intensit0 Shadow */\r
- __I uint32_t INT; /*!< (@ 0x50030040) Channel Intensit0 */\r
- __IO uint32_t CHCONFIG; /*!< (@ 0x50030044) Channel Configuration */\r
- __IO uint32_t PKCMP; /*!< (@ 0x50030048) Packer Compare */\r
- __IO uint32_t PKCNTR; /*!< (@ 0x5003004C) Packer Counter */\r
-} BCCU_CH_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ BCCU_DE [BCCU0_DE0] ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief BCCU Unit 0 (BCCU_DE)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x5003017C) BCCU_DE Structure */\r
- __IO uint32_t DLS; /*!< (@ 0x5003017C) Dimming Level Shadow */\r
- __I uint32_t DL; /*!< (@ 0x50030180) Dimming Level */\r
- __IO uint32_t DTT; /*!< (@ 0x50030184) Dimming Transition Time */\r
-} BCCU_DE_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PORT0 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Port 0 (PORT0)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40040000) PORT0 Structure */\r
- __IO uint32_t OUT; /*!< (@ 0x40040000) Port 0 Output Register */\r
- __O uint32_t OMR; /*!< (@ 0x40040004) Port 0 Output Modification Register */\r
- __I uint32_t RESERVED0[2];\r
- __IO uint32_t IOCR0; /*!< (@ 0x40040010) Port 0 Input/Output Control Register 0 */\r
- __IO uint32_t IOCR4; /*!< (@ 0x40040014) Port 0 Input/Output Control Register 4 */\r
- __IO uint32_t IOCR8; /*!< (@ 0x40040018) Port 0 Input/Output Control Register 8 */\r
- __IO uint32_t IOCR12; /*!< (@ 0x4004001C) Port 0 Input/Output Control Register 12 */\r
- __I uint32_t RESERVED1;\r
- __I uint32_t IN; /*!< (@ 0x40040024) Port 0 Input Register */\r
- __I uint32_t RESERVED2[6];\r
- __IO uint32_t PHCR0; /*!< (@ 0x40040040) Port 0 Pad Hysteresis Control Register 0 */\r
- __IO uint32_t PHCR1; /*!< (@ 0x40040044) Port 0 Pad Hysteresis Control Register 1 */\r
- __I uint32_t RESERVED3[6];\r
- __I uint32_t PDISC; /*!< (@ 0x40040060) Port 0 Pin Function Decision Control Register */\r
- __I uint32_t RESERVED4[3];\r
- __IO uint32_t PPS; /*!< (@ 0x40040070) Port 0 Pin Power Save Register */\r
- __IO uint32_t HWSEL; /*!< (@ 0x40040074) Port 0 Pin Hardware Select Register */\r
-} PORT0_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PORT1 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Port 1 (PORT1)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40040100) PORT1 Structure */\r
- __IO uint32_t OUT; /*!< (@ 0x40040100) Port 1 Output Register */\r
- __O uint32_t OMR; /*!< (@ 0x40040104) Port 1 Output Modification Register */\r
- __I uint32_t RESERVED0[2];\r
- __IO uint32_t IOCR0; /*!< (@ 0x40040110) Port 1 Input/Output Control Register 0 */\r
- __IO uint32_t IOCR4; /*!< (@ 0x40040114) Port 1 Input/Output Control Register 4 */\r
- __I uint32_t RESERVED1[3];\r
- __I uint32_t IN; /*!< (@ 0x40040124) Port 1 Input Register */\r
- __I uint32_t RESERVED2[6];\r
- __IO uint32_t PHCR0; /*!< (@ 0x40040140) Port 1 Pad Hysteresis Control Register 0 */\r
- __I uint32_t RESERVED3[7];\r
- __I uint32_t PDISC; /*!< (@ 0x40040160) Port 1 Pin Function Decision Control Register */\r
- __I uint32_t RESERVED4[3];\r
- __IO uint32_t PPS; /*!< (@ 0x40040170) Port 1 Pin Power Save Register */\r
- __IO uint32_t HWSEL; /*!< (@ 0x40040174) Port 1 Pin Hardware Select Register */\r
-} PORT1_Type;\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ PORT2 ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/**\r
- * @brief Port 2 (PORT2)\r
- */\r
-\r
-typedef struct { /*!< (@ 0x40040200) PORT2 Structure */\r
- __IO uint32_t OUT; /*!< (@ 0x40040200) Port 2 Output Register */\r
- __O uint32_t OMR; /*!< (@ 0x40040204) Port 2 Output Modification Register */\r
- __I uint32_t RESERVED0[2];\r
- __IO uint32_t IOCR0; /*!< (@ 0x40040210) Port 2 Input/Output Control Register 0 */\r
- __IO uint32_t IOCR4; /*!< (@ 0x40040214) Port 2 Input/Output Control Register 4 */\r
- __IO uint32_t IOCR8; /*!< (@ 0x40040218) Port 2 Input/Output Control Register 8 */\r
- __I uint32_t RESERVED1[2];\r
- __I uint32_t IN; /*!< (@ 0x40040224) Port 2 Input Register */\r
- __I uint32_t RESERVED2[6];\r
- __IO uint32_t PHCR0; /*!< (@ 0x40040240) Port 2 Pad Hysteresis Control Register 0 */\r
- __IO uint32_t PHCR1; /*!< (@ 0x40040244) Port 2 Pad Hysteresis Control Register 1 */\r
- __I uint32_t RESERVED3[6];\r
- __IO uint32_t PDISC; /*!< (@ 0x40040260) Port 2 Pin Function Decision Control Register */\r
- __I uint32_t RESERVED4[3];\r
- __IO uint32_t PPS; /*!< (@ 0x40040270) Port 2 Pin Power Save Register */\r
- __IO uint32_t HWSEL; /*!< (@ 0x40040274) Port 2 Pin Hardware Select Register */\r
-} PORT2_Type;\r
-\r
-\r
-/* -------------------- End of section using anonymous unions ------------------- */\r
-#if defined(__CC_ARM)\r
- #pragma pop\r
-#elif defined(__ICCARM__)\r
- /* leave anonymous unions enabled */\r
-#elif defined(__GNUC__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__TMS470__)\r
- /* anonymous unions are enabled by default */\r
-#elif defined(__TASKING__)\r
- #pragma warning restore\r
-#else\r
- #warning Not supported compiler type\r
-#endif\r
-\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PPB' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- PPB_SYST_CSR -------------------------------- */\r
-#define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */\r
-#define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */\r
-#define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */\r
-#define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */\r
-#define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */\r
-#define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */\r
-#define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */\r
-#define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */\r
-\r
-/* -------------------------------- PPB_SYST_RVR -------------------------------- */\r
-#define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */\r
-#define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */\r
-\r
-/* -------------------------------- PPB_SYST_CVR -------------------------------- */\r
-#define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */\r
-#define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */\r
-\r
-/* ------------------------------- PPB_SYST_CALIB ------------------------------- */\r
-#define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */\r
-#define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */\r
-#define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */\r
-#define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */\r
-#define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */\r
-#define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_ISER ------------------------------- */\r
-#define PPB_NVIC_ISER_SETENA_Pos 0 /*!< PPB NVIC_ISER: SETENA Position */\r
-#define PPB_NVIC_ISER_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER_SETENA_Pos) /*!< PPB NVIC_ISER: SETENA Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_ICER ------------------------------- */\r
-#define PPB_NVIC_ICER_CLRENA_Pos 0 /*!< PPB NVIC_ICER: CLRENA Position */\r
-#define PPB_NVIC_ICER_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER_CLRENA_Pos) /*!< PPB NVIC_ICER: CLRENA Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_ISPR ------------------------------- */\r
-#define PPB_NVIC_ISPR_SETPEND_Pos 0 /*!< PPB NVIC_ISPR: SETPEND Position */\r
-#define PPB_NVIC_ISPR_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR_SETPEND_Pos) /*!< PPB NVIC_ISPR: SETPEND Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_ICPR ------------------------------- */\r
-#define PPB_NVIC_ICPR_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR: CLRPEND Position */\r
-#define PPB_NVIC_ICPR_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR_CLRPEND_Pos) /*!< PPB NVIC_ICPR: CLRPEND Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */\r
-#define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */\r
-#define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */\r
-#define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */\r
-#define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */\r
-#define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */\r
-#define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */\r
-#define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */\r
-#define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */\r
-#define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */\r
-#define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */\r
-#define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */\r
-#define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */\r
-#define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */\r
-#define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */\r
-#define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */\r
-#define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */\r
-#define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */\r
-#define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */\r
-#define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */\r
-#define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */\r
-#define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */\r
-#define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */\r
-#define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */\r
-#define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */\r
-#define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */\r
-#define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */\r
-#define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */\r
-#define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */\r
-#define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */\r
-#define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */\r
-#define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */\r
-#define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */\r
-#define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */\r
-#define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */\r
-#define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */\r
-#define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */\r
-#define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */\r
-#define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */\r
-#define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */\r
-#define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */\r
-#define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */\r
-#define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */\r
-#define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */\r
-#define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */\r
-#define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */\r
-#define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */\r
-#define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */\r
-#define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */\r
-#define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */\r
-#define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */\r
-#define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */\r
-#define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */\r
-#define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */\r
-#define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */\r
-#define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */\r
-#define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */\r
-\r
-/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */\r
-#define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */\r
-#define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */\r
-#define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */\r
-#define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */\r
-#define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */\r
-#define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */\r
-#define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */\r
-#define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */\r
-\r
-/* ---------------------------------- PPB_CPUID --------------------------------- */\r
-#define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */\r
-#define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */\r
-#define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */\r
-#define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */\r
-#define PPB_CPUID_Architecture_Pos 16 /*!< PPB CPUID: Architecture Position */\r
-#define PPB_CPUID_Architecture_Msk (0x0fUL << PPB_CPUID_Architecture_Pos) /*!< PPB CPUID: Architecture Mask */\r
-#define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */\r
-#define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */\r
-#define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */\r
-#define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */\r
-\r
-/* ---------------------------------- PPB_ICSR ---------------------------------- */\r
-#define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */\r
-#define PPB_ICSR_VECTACTIVE_Msk (0x3fUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */\r
-#define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */\r
-#define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */\r
-#define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */\r
-#define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */\r
-#define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */\r
-#define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */\r
-#define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */\r
-#define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */\r
-#define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */\r
-#define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */\r
-#define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */\r
-#define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */\r
-\r
-/* ---------------------------------- PPB_AIRCR --------------------------------- */\r
-#define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */\r
-#define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */\r
-#define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */\r
-#define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */\r
-#define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */\r
-#define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */\r
-\r
-/* ----------------------------------- PPB_SCR ---------------------------------- */\r
-#define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */\r
-#define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */\r
-#define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */\r
-#define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */\r
-#define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */\r
-#define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */\r
-\r
-/* ----------------------------------- PPB_CCR ---------------------------------- */\r
-#define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */\r
-#define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */\r
-#define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */\r
-#define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */\r
-\r
-/* ---------------------------------- PPB_SHPR2 --------------------------------- */\r
-#define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */\r
-#define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */\r
-\r
-/* ---------------------------------- PPB_SHPR3 --------------------------------- */\r
-#define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */\r
-#define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */\r
-#define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */\r
-#define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */\r
-\r
-/* ---------------------------------- PPB_SHCSR --------------------------------- */\r
-#define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */\r
-#define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'ERU' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- ERU_EXISEL --------------------------------- */\r
-#define ERU_EXISEL_EXS0A_Pos 0 /*!< ERU EXISEL: EXS0A Position */\r
-#define ERU_EXISEL_EXS0A_Msk (0x03UL << ERU_EXISEL_EXS0A_Pos) /*!< ERU EXISEL: EXS0A Mask */\r
-#define ERU_EXISEL_EXS0B_Pos 2 /*!< ERU EXISEL: EXS0B Position */\r
-#define ERU_EXISEL_EXS0B_Msk (0x03UL << ERU_EXISEL_EXS0B_Pos) /*!< ERU EXISEL: EXS0B Mask */\r
-#define ERU_EXISEL_EXS1A_Pos 4 /*!< ERU EXISEL: EXS1A Position */\r
-#define ERU_EXISEL_EXS1A_Msk (0x03UL << ERU_EXISEL_EXS1A_Pos) /*!< ERU EXISEL: EXS1A Mask */\r
-#define ERU_EXISEL_EXS1B_Pos 6 /*!< ERU EXISEL: EXS1B Position */\r
-#define ERU_EXISEL_EXS1B_Msk (0x03UL << ERU_EXISEL_EXS1B_Pos) /*!< ERU EXISEL: EXS1B Mask */\r
-#define ERU_EXISEL_EXS2A_Pos 8 /*!< ERU EXISEL: EXS2A Position */\r
-#define ERU_EXISEL_EXS2A_Msk (0x03UL << ERU_EXISEL_EXS2A_Pos) /*!< ERU EXISEL: EXS2A Mask */\r
-#define ERU_EXISEL_EXS2B_Pos 10 /*!< ERU EXISEL: EXS2B Position */\r
-#define ERU_EXISEL_EXS2B_Msk (0x03UL << ERU_EXISEL_EXS2B_Pos) /*!< ERU EXISEL: EXS2B Mask */\r
-#define ERU_EXISEL_EXS3A_Pos 12 /*!< ERU EXISEL: EXS3A Position */\r
-#define ERU_EXISEL_EXS3A_Msk (0x03UL << ERU_EXISEL_EXS3A_Pos) /*!< ERU EXISEL: EXS3A Mask */\r
-#define ERU_EXISEL_EXS3B_Pos 14 /*!< ERU EXISEL: EXS3B Position */\r
-#define ERU_EXISEL_EXS3B_Msk (0x03UL << ERU_EXISEL_EXS3B_Pos) /*!< ERU EXISEL: EXS3B Mask */\r
-\r
-/* --------------------------------- ERU_EXICON --------------------------------- */\r
-#define ERU_EXICON_PE_Pos 0 /*!< ERU EXICON: PE Position */\r
-#define ERU_EXICON_PE_Msk (0x01UL << ERU_EXICON_PE_Pos) /*!< ERU EXICON: PE Mask */\r
-#define ERU_EXICON_LD_Pos 1 /*!< ERU EXICON: LD Position */\r
-#define ERU_EXICON_LD_Msk (0x01UL << ERU_EXICON_LD_Pos) /*!< ERU EXICON: LD Mask */\r
-#define ERU_EXICON_RE_Pos 2 /*!< ERU EXICON: RE Position */\r
-#define ERU_EXICON_RE_Msk (0x01UL << ERU_EXICON_RE_Pos) /*!< ERU EXICON: RE Mask */\r
-#define ERU_EXICON_FE_Pos 3 /*!< ERU EXICON: FE Position */\r
-#define ERU_EXICON_FE_Msk (0x01UL << ERU_EXICON_FE_Pos) /*!< ERU EXICON: FE Mask */\r
-#define ERU_EXICON_OCS_Pos 4 /*!< ERU EXICON: OCS Position */\r
-#define ERU_EXICON_OCS_Msk (0x07UL << ERU_EXICON_OCS_Pos) /*!< ERU EXICON: OCS Mask */\r
-#define ERU_EXICON_FL_Pos 7 /*!< ERU EXICON: FL Position */\r
-#define ERU_EXICON_FL_Msk (0x01UL << ERU_EXICON_FL_Pos) /*!< ERU EXICON: FL Mask */\r
-#define ERU_EXICON_SS_Pos 8 /*!< ERU EXICON: SS Position */\r
-#define ERU_EXICON_SS_Msk (0x03UL << ERU_EXICON_SS_Pos) /*!< ERU EXICON: SS Mask */\r
-#define ERU_EXICON_NA_Pos 10 /*!< ERU EXICON: NA Position */\r
-#define ERU_EXICON_NA_Msk (0x01UL << ERU_EXICON_NA_Pos) /*!< ERU EXICON: NA Mask */\r
-#define ERU_EXICON_NB_Pos 11 /*!< ERU EXICON: NB Position */\r
-#define ERU_EXICON_NB_Msk (0x01UL << ERU_EXICON_NB_Pos) /*!< ERU EXICON: NB Mask */\r
-\r
-/* --------------------------------- ERU_EXOCON --------------------------------- */\r
-#define ERU_EXOCON_ISS_Pos 0 /*!< ERU EXOCON: ISS Position */\r
-#define ERU_EXOCON_ISS_Msk (0x03UL << ERU_EXOCON_ISS_Pos) /*!< ERU EXOCON: ISS Mask */\r
-#define ERU_EXOCON_GEEN_Pos 2 /*!< ERU EXOCON: GEEN Position */\r
-#define ERU_EXOCON_GEEN_Msk (0x01UL << ERU_EXOCON_GEEN_Pos) /*!< ERU EXOCON: GEEN Mask */\r
-#define ERU_EXOCON_PDR_Pos 3 /*!< ERU EXOCON: PDR Position */\r
-#define ERU_EXOCON_PDR_Msk (0x01UL << ERU_EXOCON_PDR_Pos) /*!< ERU EXOCON: PDR Mask */\r
-#define ERU_EXOCON_GP_Pos 4 /*!< ERU EXOCON: GP Position */\r
-#define ERU_EXOCON_GP_Msk (0x03UL << ERU_EXOCON_GP_Pos) /*!< ERU EXOCON: GP Mask */\r
-#define ERU_EXOCON_IPEN0_Pos 12 /*!< ERU EXOCON: IPEN0 Position */\r
-#define ERU_EXOCON_IPEN0_Msk (0x01UL << ERU_EXOCON_IPEN0_Pos) /*!< ERU EXOCON: IPEN0 Mask */\r
-#define ERU_EXOCON_IPEN1_Pos 13 /*!< ERU EXOCON: IPEN1 Position */\r
-#define ERU_EXOCON_IPEN1_Msk (0x01UL << ERU_EXOCON_IPEN1_Pos) /*!< ERU EXOCON: IPEN1 Mask */\r
-#define ERU_EXOCON_IPEN2_Pos 14 /*!< ERU EXOCON: IPEN2 Position */\r
-#define ERU_EXOCON_IPEN2_Msk (0x01UL << ERU_EXOCON_IPEN2_Pos) /*!< ERU EXOCON: IPEN2 Mask */\r
-#define ERU_EXOCON_IPEN3_Pos 15 /*!< ERU EXOCON: IPEN3 Position */\r
-#define ERU_EXOCON_IPEN3_Msk (0x01UL << ERU_EXOCON_IPEN3_Pos) /*!< ERU EXOCON: IPEN3 Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PAU' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- PAU_AVAIL0 --------------------------------- */\r
-#define PAU_AVAIL0_AVAIL22_Pos 22 /*!< PAU AVAIL0: AVAIL22 Position */\r
-#define PAU_AVAIL0_AVAIL22_Msk (0x01UL << PAU_AVAIL0_AVAIL22_Pos) /*!< PAU AVAIL0: AVAIL22 Mask */\r
-#define PAU_AVAIL0_AVAIL23_Pos 23 /*!< PAU AVAIL0: AVAIL23 Position */\r
-#define PAU_AVAIL0_AVAIL23_Msk (0x01UL << PAU_AVAIL0_AVAIL23_Pos) /*!< PAU AVAIL0: AVAIL23 Mask */\r
-#define PAU_AVAIL0_AVAIL24_Pos 24 /*!< PAU AVAIL0: AVAIL24 Position */\r
-#define PAU_AVAIL0_AVAIL24_Msk (0x01UL << PAU_AVAIL0_AVAIL24_Pos) /*!< PAU AVAIL0: AVAIL24 Mask */\r
-\r
-/* --------------------------------- PAU_AVAIL1 --------------------------------- */\r
-#define PAU_AVAIL1_AVAIL0_Pos 0 /*!< PAU AVAIL1: AVAIL0 Position */\r
-#define PAU_AVAIL1_AVAIL0_Msk (0x01UL << PAU_AVAIL1_AVAIL0_Pos) /*!< PAU AVAIL1: AVAIL0 Mask */\r
-#define PAU_AVAIL1_AVAIL1_Pos 1 /*!< PAU AVAIL1: AVAIL1 Position */\r
-#define PAU_AVAIL1_AVAIL1_Msk (0x01UL << PAU_AVAIL1_AVAIL1_Pos) /*!< PAU AVAIL1: AVAIL1 Mask */\r
-#define PAU_AVAIL1_AVAIL4_Pos 4 /*!< PAU AVAIL1: AVAIL4 Position */\r
-#define PAU_AVAIL1_AVAIL4_Msk (0x01UL << PAU_AVAIL1_AVAIL4_Pos) /*!< PAU AVAIL1: AVAIL4 Mask */\r
-#define PAU_AVAIL1_AVAIL5_Pos 5 /*!< PAU AVAIL1: AVAIL5 Position */\r
-#define PAU_AVAIL1_AVAIL5_Msk (0x01UL << PAU_AVAIL1_AVAIL5_Pos) /*!< PAU AVAIL1: AVAIL5 Mask */\r
-#define PAU_AVAIL1_AVAIL6_Pos 6 /*!< PAU AVAIL1: AVAIL6 Position */\r
-#define PAU_AVAIL1_AVAIL6_Msk (0x01UL << PAU_AVAIL1_AVAIL6_Pos) /*!< PAU AVAIL1: AVAIL6 Mask */\r
-#define PAU_AVAIL1_AVAIL7_Pos 7 /*!< PAU AVAIL1: AVAIL7 Position */\r
-#define PAU_AVAIL1_AVAIL7_Msk (0x01UL << PAU_AVAIL1_AVAIL7_Pos) /*!< PAU AVAIL1: AVAIL7 Mask */\r
-#define PAU_AVAIL1_AVAIL8_Pos 8 /*!< PAU AVAIL1: AVAIL8 Position */\r
-#define PAU_AVAIL1_AVAIL8_Msk (0x01UL << PAU_AVAIL1_AVAIL8_Pos) /*!< PAU AVAIL1: AVAIL8 Mask */\r
-#define PAU_AVAIL1_AVAIL9_Pos 9 /*!< PAU AVAIL1: AVAIL9 Position */\r
-#define PAU_AVAIL1_AVAIL9_Msk (0x01UL << PAU_AVAIL1_AVAIL9_Pos) /*!< PAU AVAIL1: AVAIL9 Mask */\r
-#define PAU_AVAIL1_AVAIL10_Pos 10 /*!< PAU AVAIL1: AVAIL10 Position */\r
-#define PAU_AVAIL1_AVAIL10_Msk (0x01UL << PAU_AVAIL1_AVAIL10_Pos) /*!< PAU AVAIL1: AVAIL10 Mask */\r
-#define PAU_AVAIL1_AVAIL11_Pos 11 /*!< PAU AVAIL1: AVAIL11 Position */\r
-#define PAU_AVAIL1_AVAIL11_Msk (0x01UL << PAU_AVAIL1_AVAIL11_Pos) /*!< PAU AVAIL1: AVAIL11 Mask */\r
-#define PAU_AVAIL1_AVAIL12_Pos 12 /*!< PAU AVAIL1: AVAIL12 Position */\r
-#define PAU_AVAIL1_AVAIL12_Msk (0x01UL << PAU_AVAIL1_AVAIL12_Pos) /*!< PAU AVAIL1: AVAIL12 Mask */\r
-\r
-/* --------------------------------- PAU_AVAIL2 --------------------------------- */\r
-#define PAU_AVAIL2_AVAIL13_Pos 13 /*!< PAU AVAIL2: AVAIL13 Position */\r
-#define PAU_AVAIL2_AVAIL13_Msk (0x01UL << PAU_AVAIL2_AVAIL13_Pos) /*!< PAU AVAIL2: AVAIL13 Mask */\r
-#define PAU_AVAIL2_AVAIL14_Pos 14 /*!< PAU AVAIL2: AVAIL14 Position */\r
-#define PAU_AVAIL2_AVAIL14_Msk (0x01UL << PAU_AVAIL2_AVAIL14_Pos) /*!< PAU AVAIL2: AVAIL14 Mask */\r
-#define PAU_AVAIL2_AVAIL15_Pos 15 /*!< PAU AVAIL2: AVAIL15 Position */\r
-#define PAU_AVAIL2_AVAIL15_Msk (0x01UL << PAU_AVAIL2_AVAIL15_Pos) /*!< PAU AVAIL2: AVAIL15 Mask */\r
-\r
-/* -------------------------------- PAU_PRIVDIS0 -------------------------------- */\r
-#define PAU_PRIVDIS0_PDIS2_Pos 2 /*!< PAU PRIVDIS0: PDIS2 Position */\r
-#define PAU_PRIVDIS0_PDIS2_Msk (0x01UL << PAU_PRIVDIS0_PDIS2_Pos) /*!< PAU PRIVDIS0: PDIS2 Mask */\r
-#define PAU_PRIVDIS0_PDIS5_Pos 5 /*!< PAU PRIVDIS0: PDIS5 Position */\r
-#define PAU_PRIVDIS0_PDIS5_Msk (0x01UL << PAU_PRIVDIS0_PDIS5_Pos) /*!< PAU PRIVDIS0: PDIS5 Mask */\r
-#define PAU_PRIVDIS0_PDIS6_Pos 6 /*!< PAU PRIVDIS0: PDIS6 Position */\r
-#define PAU_PRIVDIS0_PDIS6_Msk (0x01UL << PAU_PRIVDIS0_PDIS6_Pos) /*!< PAU PRIVDIS0: PDIS6 Mask */\r
-#define PAU_PRIVDIS0_PDIS7_Pos 7 /*!< PAU PRIVDIS0: PDIS7 Position */\r
-#define PAU_PRIVDIS0_PDIS7_Msk (0x01UL << PAU_PRIVDIS0_PDIS7_Pos) /*!< PAU PRIVDIS0: PDIS7 Mask */\r
-#define PAU_PRIVDIS0_PDIS19_Pos 19 /*!< PAU PRIVDIS0: PDIS19 Position */\r
-#define PAU_PRIVDIS0_PDIS19_Msk (0x01UL << PAU_PRIVDIS0_PDIS19_Pos) /*!< PAU PRIVDIS0: PDIS19 Mask */\r
-#define PAU_PRIVDIS0_PDIS22_Pos 22 /*!< PAU PRIVDIS0: PDIS22 Position */\r
-#define PAU_PRIVDIS0_PDIS22_Msk (0x01UL << PAU_PRIVDIS0_PDIS22_Pos) /*!< PAU PRIVDIS0: PDIS22 Mask */\r
-#define PAU_PRIVDIS0_PDIS23_Pos 23 /*!< PAU PRIVDIS0: PDIS23 Position */\r
-#define PAU_PRIVDIS0_PDIS23_Msk (0x01UL << PAU_PRIVDIS0_PDIS23_Pos) /*!< PAU PRIVDIS0: PDIS23 Mask */\r
-#define PAU_PRIVDIS0_PDIS24_Pos 24 /*!< PAU PRIVDIS0: PDIS24 Position */\r
-#define PAU_PRIVDIS0_PDIS24_Msk (0x01UL << PAU_PRIVDIS0_PDIS24_Pos) /*!< PAU PRIVDIS0: PDIS24 Mask */\r
-\r
-/* -------------------------------- PAU_PRIVDIS1 -------------------------------- */\r
-#define PAU_PRIVDIS1_PDIS0_Pos 0 /*!< PAU PRIVDIS1: PDIS0 Position */\r
-#define PAU_PRIVDIS1_PDIS0_Msk (0x01UL << PAU_PRIVDIS1_PDIS0_Pos) /*!< PAU PRIVDIS1: PDIS0 Mask */\r
-#define PAU_PRIVDIS1_PDIS1_Pos 1 /*!< PAU PRIVDIS1: PDIS1 Position */\r
-#define PAU_PRIVDIS1_PDIS1_Msk (0x01UL << PAU_PRIVDIS1_PDIS1_Pos) /*!< PAU PRIVDIS1: PDIS1 Mask */\r
-#define PAU_PRIVDIS1_PDIS5_Pos 5 /*!< PAU PRIVDIS1: PDIS5 Position */\r
-#define PAU_PRIVDIS1_PDIS5_Msk (0x01UL << PAU_PRIVDIS1_PDIS5_Pos) /*!< PAU PRIVDIS1: PDIS5 Mask */\r
-#define PAU_PRIVDIS1_PDIS6_Pos 6 /*!< PAU PRIVDIS1: PDIS6 Position */\r
-#define PAU_PRIVDIS1_PDIS6_Msk (0x01UL << PAU_PRIVDIS1_PDIS6_Pos) /*!< PAU PRIVDIS1: PDIS6 Mask */\r
-#define PAU_PRIVDIS1_PDIS7_Pos 7 /*!< PAU PRIVDIS1: PDIS7 Position */\r
-#define PAU_PRIVDIS1_PDIS7_Msk (0x01UL << PAU_PRIVDIS1_PDIS7_Pos) /*!< PAU PRIVDIS1: PDIS7 Mask */\r
-#define PAU_PRIVDIS1_PDIS8_Pos 8 /*!< PAU PRIVDIS1: PDIS8 Position */\r
-#define PAU_PRIVDIS1_PDIS8_Msk (0x01UL << PAU_PRIVDIS1_PDIS8_Pos) /*!< PAU PRIVDIS1: PDIS8 Mask */\r
-#define PAU_PRIVDIS1_PDIS9_Pos 9 /*!< PAU PRIVDIS1: PDIS9 Position */\r
-#define PAU_PRIVDIS1_PDIS9_Msk (0x01UL << PAU_PRIVDIS1_PDIS9_Pos) /*!< PAU PRIVDIS1: PDIS9 Mask */\r
-#define PAU_PRIVDIS1_PDIS10_Pos 10 /*!< PAU PRIVDIS1: PDIS10 Position */\r
-#define PAU_PRIVDIS1_PDIS10_Msk (0x01UL << PAU_PRIVDIS1_PDIS10_Pos) /*!< PAU PRIVDIS1: PDIS10 Mask */\r
-#define PAU_PRIVDIS1_PDIS11_Pos 11 /*!< PAU PRIVDIS1: PDIS11 Position */\r
-#define PAU_PRIVDIS1_PDIS11_Msk (0x01UL << PAU_PRIVDIS1_PDIS11_Pos) /*!< PAU PRIVDIS1: PDIS11 Mask */\r
-#define PAU_PRIVDIS1_PDIS12_Pos 12 /*!< PAU PRIVDIS1: PDIS12 Position */\r
-#define PAU_PRIVDIS1_PDIS12_Msk (0x01UL << PAU_PRIVDIS1_PDIS12_Pos) /*!< PAU PRIVDIS1: PDIS12 Mask */\r
-\r
-/* -------------------------------- PAU_PRIVDIS2 -------------------------------- */\r
-#define PAU_PRIVDIS2_PDIS13_Pos 13 /*!< PAU PRIVDIS2: PDIS13 Position */\r
-#define PAU_PRIVDIS2_PDIS13_Msk (0x01UL << PAU_PRIVDIS2_PDIS13_Pos) /*!< PAU PRIVDIS2: PDIS13 Mask */\r
-#define PAU_PRIVDIS2_PDIS14_Pos 14 /*!< PAU PRIVDIS2: PDIS14 Position */\r
-#define PAU_PRIVDIS2_PDIS14_Msk (0x01UL << PAU_PRIVDIS2_PDIS14_Pos) /*!< PAU PRIVDIS2: PDIS14 Mask */\r
-#define PAU_PRIVDIS2_PDIS15_Pos 15 /*!< PAU PRIVDIS2: PDIS15 Position */\r
-#define PAU_PRIVDIS2_PDIS15_Msk (0x01UL << PAU_PRIVDIS2_PDIS15_Pos) /*!< PAU PRIVDIS2: PDIS15 Mask */\r
-\r
-/* --------------------------------- PAU_ROMSIZE -------------------------------- */\r
-#define PAU_ROMSIZE_ADDR_Pos 8 /*!< PAU ROMSIZE: ADDR Position */\r
-#define PAU_ROMSIZE_ADDR_Msk (0x3fUL << PAU_ROMSIZE_ADDR_Pos) /*!< PAU ROMSIZE: ADDR Mask */\r
-\r
-/* --------------------------------- PAU_FLSIZE --------------------------------- */\r
-#define PAU_FLSIZE_ADDR_Pos 12 /*!< PAU FLSIZE: ADDR Position */\r
-#define PAU_FLSIZE_ADDR_Msk (0x3fUL << PAU_FLSIZE_ADDR_Pos) /*!< PAU FLSIZE: ADDR Mask */\r
-\r
-/* -------------------------------- PAU_RAM0SIZE -------------------------------- */\r
-#define PAU_RAM0SIZE_ADDR_Pos 8 /*!< PAU RAM0SIZE: ADDR Position */\r
-#define PAU_RAM0SIZE_ADDR_Msk (0x1fUL << PAU_RAM0SIZE_ADDR_Pos) /*!< PAU RAM0SIZE: ADDR Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'NVM' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- NVM_NVMSTATUS ------------------------------- */\r
-#define NVM_NVMSTATUS_BUSY_Pos 0 /*!< NVM NVMSTATUS: BUSY Position */\r
-#define NVM_NVMSTATUS_BUSY_Msk (0x01UL << NVM_NVMSTATUS_BUSY_Pos) /*!< NVM NVMSTATUS: BUSY Mask */\r
-#define NVM_NVMSTATUS_SLEEP_Pos 1 /*!< NVM NVMSTATUS: SLEEP Position */\r
-#define NVM_NVMSTATUS_SLEEP_Msk (0x01UL << NVM_NVMSTATUS_SLEEP_Pos) /*!< NVM NVMSTATUS: SLEEP Mask */\r
-#define NVM_NVMSTATUS_VERR_Pos 2 /*!< NVM NVMSTATUS: VERR Position */\r
-#define NVM_NVMSTATUS_VERR_Msk (0x03UL << NVM_NVMSTATUS_VERR_Pos) /*!< NVM NVMSTATUS: VERR Mask */\r
-#define NVM_NVMSTATUS_ECC1READ_Pos 4 /*!< NVM NVMSTATUS: ECC1READ Position */\r
-#define NVM_NVMSTATUS_ECC1READ_Msk (0x01UL << NVM_NVMSTATUS_ECC1READ_Pos) /*!< NVM NVMSTATUS: ECC1READ Mask */\r
-#define NVM_NVMSTATUS_ECC2READ_Pos 5 /*!< NVM NVMSTATUS: ECC2READ Position */\r
-#define NVM_NVMSTATUS_ECC2READ_Msk (0x01UL << NVM_NVMSTATUS_ECC2READ_Pos) /*!< NVM NVMSTATUS: ECC2READ Mask */\r
-#define NVM_NVMSTATUS_WRPERR_Pos 6 /*!< NVM NVMSTATUS: WRPERR Position */\r
-#define NVM_NVMSTATUS_WRPERR_Msk (0x01UL << NVM_NVMSTATUS_WRPERR_Pos) /*!< NVM NVMSTATUS: WRPERR Mask */\r
-\r
-/* --------------------------------- NVM_NVMPROG -------------------------------- */\r
-#define NVM_NVMPROG_ACTION_Pos 0 /*!< NVM NVMPROG: ACTION Position */\r
-#define NVM_NVMPROG_ACTION_Msk (0x000000ffUL << NVM_NVMPROG_ACTION_Pos) /*!< NVM NVMPROG: ACTION Mask */\r
-#define NVM_NVMPROG_RSTVERR_Pos 12 /*!< NVM NVMPROG: RSTVERR Position */\r
-#define NVM_NVMPROG_RSTVERR_Msk (0x01UL << NVM_NVMPROG_RSTVERR_Pos) /*!< NVM NVMPROG: RSTVERR Mask */\r
-#define NVM_NVMPROG_RSTECC_Pos 13 /*!< NVM NVMPROG: RSTECC Position */\r
-#define NVM_NVMPROG_RSTECC_Msk (0x01UL << NVM_NVMPROG_RSTECC_Pos) /*!< NVM NVMPROG: RSTECC Mask */\r
-\r
-/* --------------------------------- NVM_NVMCONF -------------------------------- */\r
-#define NVM_NVMCONF_HRLEV_Pos 1 /*!< NVM NVMCONF: HRLEV Position */\r
-#define NVM_NVMCONF_HRLEV_Msk (0x03UL << NVM_NVMCONF_HRLEV_Pos) /*!< NVM NVMCONF: HRLEV Mask */\r
-#define NVM_NVMCONF_SECPROT_Pos 4 /*!< NVM NVMCONF: SECPROT Position */\r
-#define NVM_NVMCONF_SECPROT_Msk (0x000000ffUL << NVM_NVMCONF_SECPROT_Pos) /*!< NVM NVMCONF: SECPROT Mask */\r
-#define NVM_NVMCONF_INT_ON_Pos 14 /*!< NVM NVMCONF: INT_ON Position */\r
-#define NVM_NVMCONF_INT_ON_Msk (0x01UL << NVM_NVMCONF_INT_ON_Pos) /*!< NVM NVMCONF: INT_ON Mask */\r
-#define NVM_NVMCONF_NVM_ON_Pos 15 /*!< NVM NVMCONF: NVM_ON Position */\r
-#define NVM_NVMCONF_NVM_ON_Msk (0x01UL << NVM_NVMCONF_NVM_ON_Pos) /*!< NVM NVMCONF: NVM_ON Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'WDT' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------------- WDT_ID ----------------------------------- */\r
-#define WDT_ID_MOD_REV_Pos 0 /*!< WDT ID: MOD_REV Position */\r
-#define WDT_ID_MOD_REV_Msk (0x000000ffUL << WDT_ID_MOD_REV_Pos) /*!< WDT ID: MOD_REV Mask */\r
-#define WDT_ID_MOD_TYPE_Pos 8 /*!< WDT ID: MOD_TYPE Position */\r
-#define WDT_ID_MOD_TYPE_Msk (0x000000ffUL << WDT_ID_MOD_TYPE_Pos) /*!< WDT ID: MOD_TYPE Mask */\r
-#define WDT_ID_MOD_NUMBER_Pos 16 /*!< WDT ID: MOD_NUMBER Position */\r
-#define WDT_ID_MOD_NUMBER_Msk (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos) /*!< WDT ID: MOD_NUMBER Mask */\r
-\r
-/* ----------------------------------- WDT_CTR ---------------------------------- */\r
-#define WDT_CTR_ENB_Pos 0 /*!< WDT CTR: ENB Position */\r
-#define WDT_CTR_ENB_Msk (0x01UL << WDT_CTR_ENB_Pos) /*!< WDT CTR: ENB Mask */\r
-#define WDT_CTR_PRE_Pos 1 /*!< WDT CTR: PRE Position */\r
-#define WDT_CTR_PRE_Msk (0x01UL << WDT_CTR_PRE_Pos) /*!< WDT CTR: PRE Mask */\r
-#define WDT_CTR_DSP_Pos 4 /*!< WDT CTR: DSP Position */\r
-#define WDT_CTR_DSP_Msk (0x01UL << WDT_CTR_DSP_Pos) /*!< WDT CTR: DSP Mask */\r
-#define WDT_CTR_SPW_Pos 8 /*!< WDT CTR: SPW Position */\r
-#define WDT_CTR_SPW_Msk (0x000000ffUL << WDT_CTR_SPW_Pos) /*!< WDT CTR: SPW Mask */\r
-\r
-/* ----------------------------------- WDT_SRV ---------------------------------- */\r
-#define WDT_SRV_SRV_Pos 0 /*!< WDT SRV: SRV Position */\r
-#define WDT_SRV_SRV_Msk (0xffffffffUL << WDT_SRV_SRV_Pos) /*!< WDT SRV: SRV Mask */\r
-\r
-/* ----------------------------------- WDT_TIM ---------------------------------- */\r
-#define WDT_TIM_TIM_Pos 0 /*!< WDT TIM: TIM Position */\r
-#define WDT_TIM_TIM_Msk (0xffffffffUL << WDT_TIM_TIM_Pos) /*!< WDT TIM: TIM Mask */\r
-\r
-/* ----------------------------------- WDT_WLB ---------------------------------- */\r
-#define WDT_WLB_WLB_Pos 0 /*!< WDT WLB: WLB Position */\r
-#define WDT_WLB_WLB_Msk (0xffffffffUL << WDT_WLB_WLB_Pos) /*!< WDT WLB: WLB Mask */\r
-\r
-/* ----------------------------------- WDT_WUB ---------------------------------- */\r
-#define WDT_WUB_WUB_Pos 0 /*!< WDT WUB: WUB Position */\r
-#define WDT_WUB_WUB_Msk (0xffffffffUL << WDT_WUB_WUB_Pos) /*!< WDT WUB: WUB Mask */\r
-\r
-/* --------------------------------- WDT_WDTSTS --------------------------------- */\r
-#define WDT_WDTSTS_ALMS_Pos 0 /*!< WDT WDTSTS: ALMS Position */\r
-#define WDT_WDTSTS_ALMS_Msk (0x01UL << WDT_WDTSTS_ALMS_Pos) /*!< WDT WDTSTS: ALMS Mask */\r
-\r
-/* --------------------------------- WDT_WDTCLR --------------------------------- */\r
-#define WDT_WDTCLR_ALMC_Pos 0 /*!< WDT WDTCLR: ALMC Position */\r
-#define WDT_WDTCLR_ALMC_Msk (0x01UL << WDT_WDTCLR_ALMC_Pos) /*!< WDT WDTCLR: ALMC Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'RTC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------------- RTC_ID ----------------------------------- */\r
-#define RTC_ID_MOD_REV_Pos 0 /*!< RTC ID: MOD_REV Position */\r
-#define RTC_ID_MOD_REV_Msk (0x000000ffUL << RTC_ID_MOD_REV_Pos) /*!< RTC ID: MOD_REV Mask */\r
-#define RTC_ID_MOD_TYPE_Pos 8 /*!< RTC ID: MOD_TYPE Position */\r
-#define RTC_ID_MOD_TYPE_Msk (0x000000ffUL << RTC_ID_MOD_TYPE_Pos) /*!< RTC ID: MOD_TYPE Mask */\r
-#define RTC_ID_MOD_NUMBER_Pos 16 /*!< RTC ID: MOD_NUMBER Position */\r
-#define RTC_ID_MOD_NUMBER_Msk (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos) /*!< RTC ID: MOD_NUMBER Mask */\r
-\r
-/* ----------------------------------- RTC_CTR ---------------------------------- */\r
-#define RTC_CTR_ENB_Pos 0 /*!< RTC CTR: ENB Position */\r
-#define RTC_CTR_ENB_Msk (0x01UL << RTC_CTR_ENB_Pos) /*!< RTC CTR: ENB Mask */\r
-#define RTC_CTR_SUS_Pos 1 /*!< RTC CTR: SUS Position */\r
-#define RTC_CTR_SUS_Msk (0x01UL << RTC_CTR_SUS_Pos) /*!< RTC CTR: SUS Mask */\r
-#define RTC_CTR_DIV_Pos 16 /*!< RTC CTR: DIV Position */\r
-#define RTC_CTR_DIV_Msk (0x0000ffffUL << RTC_CTR_DIV_Pos) /*!< RTC CTR: DIV Mask */\r
-\r
-/* --------------------------------- RTC_RAWSTAT -------------------------------- */\r
-#define RTC_RAWSTAT_RPSE_Pos 0 /*!< RTC RAWSTAT: RPSE Position */\r
-#define RTC_RAWSTAT_RPSE_Msk (0x01UL << RTC_RAWSTAT_RPSE_Pos) /*!< RTC RAWSTAT: RPSE Mask */\r
-#define RTC_RAWSTAT_RPMI_Pos 1 /*!< RTC RAWSTAT: RPMI Position */\r
-#define RTC_RAWSTAT_RPMI_Msk (0x01UL << RTC_RAWSTAT_RPMI_Pos) /*!< RTC RAWSTAT: RPMI Mask */\r
-#define RTC_RAWSTAT_RPHO_Pos 2 /*!< RTC RAWSTAT: RPHO Position */\r
-#define RTC_RAWSTAT_RPHO_Msk (0x01UL << RTC_RAWSTAT_RPHO_Pos) /*!< RTC RAWSTAT: RPHO Mask */\r
-#define RTC_RAWSTAT_RPDA_Pos 3 /*!< RTC RAWSTAT: RPDA Position */\r
-#define RTC_RAWSTAT_RPDA_Msk (0x01UL << RTC_RAWSTAT_RPDA_Pos) /*!< RTC RAWSTAT: RPDA Mask */\r
-#define RTC_RAWSTAT_RPMO_Pos 5 /*!< RTC RAWSTAT: RPMO Position */\r
-#define RTC_RAWSTAT_RPMO_Msk (0x01UL << RTC_RAWSTAT_RPMO_Pos) /*!< RTC RAWSTAT: RPMO Mask */\r
-#define RTC_RAWSTAT_RPYE_Pos 6 /*!< RTC RAWSTAT: RPYE Position */\r
-#define RTC_RAWSTAT_RPYE_Msk (0x01UL << RTC_RAWSTAT_RPYE_Pos) /*!< RTC RAWSTAT: RPYE Mask */\r
-#define RTC_RAWSTAT_RAI_Pos 8 /*!< RTC RAWSTAT: RAI Position */\r
-#define RTC_RAWSTAT_RAI_Msk (0x01UL << RTC_RAWSTAT_RAI_Pos) /*!< RTC RAWSTAT: RAI Mask */\r
-\r
-/* ---------------------------------- RTC_STSSR --------------------------------- */\r
-#define RTC_STSSR_SPSE_Pos 0 /*!< RTC STSSR: SPSE Position */\r
-#define RTC_STSSR_SPSE_Msk (0x01UL << RTC_STSSR_SPSE_Pos) /*!< RTC STSSR: SPSE Mask */\r
-#define RTC_STSSR_SPMI_Pos 1 /*!< RTC STSSR: SPMI Position */\r
-#define RTC_STSSR_SPMI_Msk (0x01UL << RTC_STSSR_SPMI_Pos) /*!< RTC STSSR: SPMI Mask */\r
-#define RTC_STSSR_SPHO_Pos 2 /*!< RTC STSSR: SPHO Position */\r
-#define RTC_STSSR_SPHO_Msk (0x01UL << RTC_STSSR_SPHO_Pos) /*!< RTC STSSR: SPHO Mask */\r
-#define RTC_STSSR_SPDA_Pos 3 /*!< RTC STSSR: SPDA Position */\r
-#define RTC_STSSR_SPDA_Msk (0x01UL << RTC_STSSR_SPDA_Pos) /*!< RTC STSSR: SPDA Mask */\r
-#define RTC_STSSR_SPMO_Pos 5 /*!< RTC STSSR: SPMO Position */\r
-#define RTC_STSSR_SPMO_Msk (0x01UL << RTC_STSSR_SPMO_Pos) /*!< RTC STSSR: SPMO Mask */\r
-#define RTC_STSSR_SPYE_Pos 6 /*!< RTC STSSR: SPYE Position */\r
-#define RTC_STSSR_SPYE_Msk (0x01UL << RTC_STSSR_SPYE_Pos) /*!< RTC STSSR: SPYE Mask */\r
-#define RTC_STSSR_SAI_Pos 8 /*!< RTC STSSR: SAI Position */\r
-#define RTC_STSSR_SAI_Msk (0x01UL << RTC_STSSR_SAI_Pos) /*!< RTC STSSR: SAI Mask */\r
-\r
-/* ---------------------------------- RTC_MSKSR --------------------------------- */\r
-#define RTC_MSKSR_MPSE_Pos 0 /*!< RTC MSKSR: MPSE Position */\r
-#define RTC_MSKSR_MPSE_Msk (0x01UL << RTC_MSKSR_MPSE_Pos) /*!< RTC MSKSR: MPSE Mask */\r
-#define RTC_MSKSR_MPMI_Pos 1 /*!< RTC MSKSR: MPMI Position */\r
-#define RTC_MSKSR_MPMI_Msk (0x01UL << RTC_MSKSR_MPMI_Pos) /*!< RTC MSKSR: MPMI Mask */\r
-#define RTC_MSKSR_MPHO_Pos 2 /*!< RTC MSKSR: MPHO Position */\r
-#define RTC_MSKSR_MPHO_Msk (0x01UL << RTC_MSKSR_MPHO_Pos) /*!< RTC MSKSR: MPHO Mask */\r
-#define RTC_MSKSR_MPDA_Pos 3 /*!< RTC MSKSR: MPDA Position */\r
-#define RTC_MSKSR_MPDA_Msk (0x01UL << RTC_MSKSR_MPDA_Pos) /*!< RTC MSKSR: MPDA Mask */\r
-#define RTC_MSKSR_MPMO_Pos 5 /*!< RTC MSKSR: MPMO Position */\r
-#define RTC_MSKSR_MPMO_Msk (0x01UL << RTC_MSKSR_MPMO_Pos) /*!< RTC MSKSR: MPMO Mask */\r
-#define RTC_MSKSR_MPYE_Pos 6 /*!< RTC MSKSR: MPYE Position */\r
-#define RTC_MSKSR_MPYE_Msk (0x01UL << RTC_MSKSR_MPYE_Pos) /*!< RTC MSKSR: MPYE Mask */\r
-#define RTC_MSKSR_MAI_Pos 8 /*!< RTC MSKSR: MAI Position */\r
-#define RTC_MSKSR_MAI_Msk (0x01UL << RTC_MSKSR_MAI_Pos) /*!< RTC MSKSR: MAI Mask */\r
-\r
-/* ---------------------------------- RTC_CLRSR --------------------------------- */\r
-#define RTC_CLRSR_RPSE_Pos 0 /*!< RTC CLRSR: RPSE Position */\r
-#define RTC_CLRSR_RPSE_Msk (0x01UL << RTC_CLRSR_RPSE_Pos) /*!< RTC CLRSR: RPSE Mask */\r
-#define RTC_CLRSR_RPMI_Pos 1 /*!< RTC CLRSR: RPMI Position */\r
-#define RTC_CLRSR_RPMI_Msk (0x01UL << RTC_CLRSR_RPMI_Pos) /*!< RTC CLRSR: RPMI Mask */\r
-#define RTC_CLRSR_RPHO_Pos 2 /*!< RTC CLRSR: RPHO Position */\r
-#define RTC_CLRSR_RPHO_Msk (0x01UL << RTC_CLRSR_RPHO_Pos) /*!< RTC CLRSR: RPHO Mask */\r
-#define RTC_CLRSR_RPDA_Pos 3 /*!< RTC CLRSR: RPDA Position */\r
-#define RTC_CLRSR_RPDA_Msk (0x01UL << RTC_CLRSR_RPDA_Pos) /*!< RTC CLRSR: RPDA Mask */\r
-#define RTC_CLRSR_RPMO_Pos 5 /*!< RTC CLRSR: RPMO Position */\r
-#define RTC_CLRSR_RPMO_Msk (0x01UL << RTC_CLRSR_RPMO_Pos) /*!< RTC CLRSR: RPMO Mask */\r
-#define RTC_CLRSR_RPYE_Pos 6 /*!< RTC CLRSR: RPYE Position */\r
-#define RTC_CLRSR_RPYE_Msk (0x01UL << RTC_CLRSR_RPYE_Pos) /*!< RTC CLRSR: RPYE Mask */\r
-#define RTC_CLRSR_RAI_Pos 8 /*!< RTC CLRSR: RAI Position */\r
-#define RTC_CLRSR_RAI_Msk (0x01UL << RTC_CLRSR_RAI_Pos) /*!< RTC CLRSR: RAI Mask */\r
-\r
-/* ---------------------------------- RTC_ATIM0 --------------------------------- */\r
-#define RTC_ATIM0_ASE_Pos 0 /*!< RTC ATIM0: ASE Position */\r
-#define RTC_ATIM0_ASE_Msk (0x3fUL << RTC_ATIM0_ASE_Pos) /*!< RTC ATIM0: ASE Mask */\r
-#define RTC_ATIM0_AMI_Pos 8 /*!< RTC ATIM0: AMI Position */\r
-#define RTC_ATIM0_AMI_Msk (0x3fUL << RTC_ATIM0_AMI_Pos) /*!< RTC ATIM0: AMI Mask */\r
-#define RTC_ATIM0_AHO_Pos 16 /*!< RTC ATIM0: AHO Position */\r
-#define RTC_ATIM0_AHO_Msk (0x1fUL << RTC_ATIM0_AHO_Pos) /*!< RTC ATIM0: AHO Mask */\r
-#define RTC_ATIM0_ADA_Pos 24 /*!< RTC ATIM0: ADA Position */\r
-#define RTC_ATIM0_ADA_Msk (0x1fUL << RTC_ATIM0_ADA_Pos) /*!< RTC ATIM0: ADA Mask */\r
-\r
-/* ---------------------------------- RTC_ATIM1 --------------------------------- */\r
-#define RTC_ATIM1_AMO_Pos 8 /*!< RTC ATIM1: AMO Position */\r
-#define RTC_ATIM1_AMO_Msk (0x0fUL << RTC_ATIM1_AMO_Pos) /*!< RTC ATIM1: AMO Mask */\r
-#define RTC_ATIM1_AYE_Pos 16 /*!< RTC ATIM1: AYE Position */\r
-#define RTC_ATIM1_AYE_Msk (0x0000ffffUL << RTC_ATIM1_AYE_Pos) /*!< RTC ATIM1: AYE Mask */\r
-\r
-/* ---------------------------------- RTC_TIM0 ---------------------------------- */\r
-#define RTC_TIM0_SE_Pos 0 /*!< RTC TIM0: SE Position */\r
-#define RTC_TIM0_SE_Msk (0x3fUL << RTC_TIM0_SE_Pos) /*!< RTC TIM0: SE Mask */\r
-#define RTC_TIM0_MI_Pos 8 /*!< RTC TIM0: MI Position */\r
-#define RTC_TIM0_MI_Msk (0x3fUL << RTC_TIM0_MI_Pos) /*!< RTC TIM0: MI Mask */\r
-#define RTC_TIM0_HO_Pos 16 /*!< RTC TIM0: HO Position */\r
-#define RTC_TIM0_HO_Msk (0x1fUL << RTC_TIM0_HO_Pos) /*!< RTC TIM0: HO Mask */\r
-#define RTC_TIM0_DA_Pos 24 /*!< RTC TIM0: DA Position */\r
-#define RTC_TIM0_DA_Msk (0x1fUL << RTC_TIM0_DA_Pos) /*!< RTC TIM0: DA Mask */\r
-\r
-/* ---------------------------------- RTC_TIM1 ---------------------------------- */\r
-#define RTC_TIM1_DAWE_Pos 0 /*!< RTC TIM1: DAWE Position */\r
-#define RTC_TIM1_DAWE_Msk (0x07UL << RTC_TIM1_DAWE_Pos) /*!< RTC TIM1: DAWE Mask */\r
-#define RTC_TIM1_MO_Pos 8 /*!< RTC TIM1: MO Position */\r
-#define RTC_TIM1_MO_Msk (0x0fUL << RTC_TIM1_MO_Pos) /*!< RTC TIM1: MO Mask */\r
-#define RTC_TIM1_YE_Pos 16 /*!< RTC TIM1: YE Position */\r
-#define RTC_TIM1_YE_Msk (0x0000ffffUL << RTC_TIM1_YE_Pos) /*!< RTC TIM1: YE Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PRNG' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- PRNG_WORD --------------------------------- */\r
-#define PRNG_WORD_RDATA_Pos 0 /*!< PRNG WORD: RDATA Position */\r
-#define PRNG_WORD_RDATA_Msk (0x0000ffffUL << PRNG_WORD_RDATA_Pos) /*!< PRNG WORD: RDATA Mask */\r
-\r
-/* ---------------------------------- PRNG_CHK ---------------------------------- */\r
-#define PRNG_CHK_RDV_Pos 0 /*!< PRNG CHK: RDV Position */\r
-#define PRNG_CHK_RDV_Msk (0x01UL << PRNG_CHK_RDV_Pos) /*!< PRNG CHK: RDV Mask */\r
-\r
-/* ---------------------------------- PRNG_CTRL --------------------------------- */\r
-#define PRNG_CTRL_RDBS_Pos 1 /*!< PRNG CTRL: RDBS Position */\r
-#define PRNG_CTRL_RDBS_Msk (0x03UL << PRNG_CTRL_RDBS_Pos) /*!< PRNG CTRL: RDBS Mask */\r
-#define PRNG_CTRL_KLD_Pos 3 /*!< PRNG CTRL: KLD Position */\r
-#define PRNG_CTRL_KLD_Msk (0x01UL << PRNG_CTRL_KLD_Pos) /*!< PRNG CTRL: KLD Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'LEDTS' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- LEDTS_ID ---------------------------------- */\r
-#define LEDTS_ID_MOD_REV_Pos 0 /*!< LEDTS ID: MOD_REV Position */\r
-#define LEDTS_ID_MOD_REV_Msk (0x000000ffUL << LEDTS_ID_MOD_REV_Pos) /*!< LEDTS ID: MOD_REV Mask */\r
-#define LEDTS_ID_MOD_TYPE_Pos 8 /*!< LEDTS ID: MOD_TYPE Position */\r
-#define LEDTS_ID_MOD_TYPE_Msk (0x000000ffUL << LEDTS_ID_MOD_TYPE_Pos) /*!< LEDTS ID: MOD_TYPE Mask */\r
-#define LEDTS_ID_MOD_NUMBER_Pos 16 /*!< LEDTS ID: MOD_NUMBER Position */\r
-#define LEDTS_ID_MOD_NUMBER_Msk (0x0000ffffUL << LEDTS_ID_MOD_NUMBER_Pos) /*!< LEDTS ID: MOD_NUMBER Mask */\r
-\r
-/* -------------------------------- LEDTS_GLOBCTL ------------------------------- */\r
-#define LEDTS_GLOBCTL_TS_EN_Pos 0 /*!< LEDTS GLOBCTL: TS_EN Position */\r
-#define LEDTS_GLOBCTL_TS_EN_Msk (0x01UL << LEDTS_GLOBCTL_TS_EN_Pos) /*!< LEDTS GLOBCTL: TS_EN Mask */\r
-#define LEDTS_GLOBCTL_LD_EN_Pos 1 /*!< LEDTS GLOBCTL: LD_EN Position */\r
-#define LEDTS_GLOBCTL_LD_EN_Msk (0x01UL << LEDTS_GLOBCTL_LD_EN_Pos) /*!< LEDTS GLOBCTL: LD_EN Mask */\r
-#define LEDTS_GLOBCTL_CMTR_Pos 2 /*!< LEDTS GLOBCTL: CMTR Position */\r
-#define LEDTS_GLOBCTL_CMTR_Msk (0x01UL << LEDTS_GLOBCTL_CMTR_Pos) /*!< LEDTS GLOBCTL: CMTR Mask */\r
-#define LEDTS_GLOBCTL_ENSYNC_Pos 3 /*!< LEDTS GLOBCTL: ENSYNC Position */\r
-#define LEDTS_GLOBCTL_ENSYNC_Msk (0x01UL << LEDTS_GLOBCTL_ENSYNC_Pos) /*!< LEDTS GLOBCTL: ENSYNC Mask */\r
-#define LEDTS_GLOBCTL_SUSCFG_Pos 8 /*!< LEDTS GLOBCTL: SUSCFG Position */\r
-#define LEDTS_GLOBCTL_SUSCFG_Msk (0x01UL << LEDTS_GLOBCTL_SUSCFG_Pos) /*!< LEDTS GLOBCTL: SUSCFG Mask */\r
-#define LEDTS_GLOBCTL_MASKVAL_Pos 9 /*!< LEDTS GLOBCTL: MASKVAL Position */\r
-#define LEDTS_GLOBCTL_MASKVAL_Msk (0x07UL << LEDTS_GLOBCTL_MASKVAL_Pos) /*!< LEDTS GLOBCTL: MASKVAL Mask */\r
-#define LEDTS_GLOBCTL_FENVAL_Pos 12 /*!< LEDTS GLOBCTL: FENVAL Position */\r
-#define LEDTS_GLOBCTL_FENVAL_Msk (0x01UL << LEDTS_GLOBCTL_FENVAL_Pos) /*!< LEDTS GLOBCTL: FENVAL Mask */\r
-#define LEDTS_GLOBCTL_ITS_EN_Pos 13 /*!< LEDTS GLOBCTL: ITS_EN Position */\r
-#define LEDTS_GLOBCTL_ITS_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITS_EN_Pos) /*!< LEDTS GLOBCTL: ITS_EN Mask */\r
-#define LEDTS_GLOBCTL_ITF_EN_Pos 14 /*!< LEDTS GLOBCTL: ITF_EN Position */\r
-#define LEDTS_GLOBCTL_ITF_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITF_EN_Pos) /*!< LEDTS GLOBCTL: ITF_EN Mask */\r
-#define LEDTS_GLOBCTL_ITP_EN_Pos 15 /*!< LEDTS GLOBCTL: ITP_EN Position */\r
-#define LEDTS_GLOBCTL_ITP_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITP_EN_Pos) /*!< LEDTS GLOBCTL: ITP_EN Mask */\r
-#define LEDTS_GLOBCTL_CLK_PS_Pos 16 /*!< LEDTS GLOBCTL: CLK_PS Position */\r
-#define LEDTS_GLOBCTL_CLK_PS_Msk (0x0000ffffUL << LEDTS_GLOBCTL_CLK_PS_Pos) /*!< LEDTS GLOBCTL: CLK_PS Mask */\r
-\r
-/* --------------------------------- LEDTS_FNCTL -------------------------------- */\r
-#define LEDTS_FNCTL_PADT_Pos 0 /*!< LEDTS FNCTL: PADT Position */\r
-#define LEDTS_FNCTL_PADT_Msk (0x07UL << LEDTS_FNCTL_PADT_Pos) /*!< LEDTS FNCTL: PADT Mask */\r
-#define LEDTS_FNCTL_PADTSW_Pos 3 /*!< LEDTS FNCTL: PADTSW Position */\r
-#define LEDTS_FNCTL_PADTSW_Msk (0x01UL << LEDTS_FNCTL_PADTSW_Pos) /*!< LEDTS FNCTL: PADTSW Mask */\r
-#define LEDTS_FNCTL_EPULL_Pos 4 /*!< LEDTS FNCTL: EPULL Position */\r
-#define LEDTS_FNCTL_EPULL_Msk (0x01UL << LEDTS_FNCTL_EPULL_Pos) /*!< LEDTS FNCTL: EPULL Mask */\r
-#define LEDTS_FNCTL_FNCOL_Pos 5 /*!< LEDTS FNCTL: FNCOL Position */\r
-#define LEDTS_FNCTL_FNCOL_Msk (0x07UL << LEDTS_FNCTL_FNCOL_Pos) /*!< LEDTS FNCTL: FNCOL Mask */\r
-#define LEDTS_FNCTL_ACCCNT_Pos 16 /*!< LEDTS FNCTL: ACCCNT Position */\r
-#define LEDTS_FNCTL_ACCCNT_Msk (0x0fUL << LEDTS_FNCTL_ACCCNT_Pos) /*!< LEDTS FNCTL: ACCCNT Mask */\r
-#define LEDTS_FNCTL_TSCCMP_Pos 20 /*!< LEDTS FNCTL: TSCCMP Position */\r
-#define LEDTS_FNCTL_TSCCMP_Msk (0x01UL << LEDTS_FNCTL_TSCCMP_Pos) /*!< LEDTS FNCTL: TSCCMP Mask */\r
-#define LEDTS_FNCTL_TSOEXT_Pos 21 /*!< LEDTS FNCTL: TSOEXT Position */\r
-#define LEDTS_FNCTL_TSOEXT_Msk (0x03UL << LEDTS_FNCTL_TSOEXT_Pos) /*!< LEDTS FNCTL: TSOEXT Mask */\r
-#define LEDTS_FNCTL_TSCTRR_Pos 23 /*!< LEDTS FNCTL: TSCTRR Position */\r
-#define LEDTS_FNCTL_TSCTRR_Msk (0x01UL << LEDTS_FNCTL_TSCTRR_Pos) /*!< LEDTS FNCTL: TSCTRR Mask */\r
-#define LEDTS_FNCTL_TSCTRSAT_Pos 24 /*!< LEDTS FNCTL: TSCTRSAT Position */\r
-#define LEDTS_FNCTL_TSCTRSAT_Msk (0x01UL << LEDTS_FNCTL_TSCTRSAT_Pos) /*!< LEDTS FNCTL: TSCTRSAT Mask */\r
-#define LEDTS_FNCTL_NR_TSIN_Pos 25 /*!< LEDTS FNCTL: NR_TSIN Position */\r
-#define LEDTS_FNCTL_NR_TSIN_Msk (0x07UL << LEDTS_FNCTL_NR_TSIN_Pos) /*!< LEDTS FNCTL: NR_TSIN Mask */\r
-#define LEDTS_FNCTL_COLLEV_Pos 28 /*!< LEDTS FNCTL: COLLEV Position */\r
-#define LEDTS_FNCTL_COLLEV_Msk (0x01UL << LEDTS_FNCTL_COLLEV_Pos) /*!< LEDTS FNCTL: COLLEV Mask */\r
-#define LEDTS_FNCTL_NR_LEDCOL_Pos 29 /*!< LEDTS FNCTL: NR_LEDCOL Position */\r
-#define LEDTS_FNCTL_NR_LEDCOL_Msk (0x07UL << LEDTS_FNCTL_NR_LEDCOL_Pos) /*!< LEDTS FNCTL: NR_LEDCOL Mask */\r
-\r
-/* --------------------------------- LEDTS_EVFR --------------------------------- */\r
-#define LEDTS_EVFR_TSF_Pos 0 /*!< LEDTS EVFR: TSF Position */\r
-#define LEDTS_EVFR_TSF_Msk (0x01UL << LEDTS_EVFR_TSF_Pos) /*!< LEDTS EVFR: TSF Mask */\r
-#define LEDTS_EVFR_TFF_Pos 1 /*!< LEDTS EVFR: TFF Position */\r
-#define LEDTS_EVFR_TFF_Msk (0x01UL << LEDTS_EVFR_TFF_Pos) /*!< LEDTS EVFR: TFF Mask */\r
-#define LEDTS_EVFR_TPF_Pos 2 /*!< LEDTS EVFR: TPF Position */\r
-#define LEDTS_EVFR_TPF_Msk (0x01UL << LEDTS_EVFR_TPF_Pos) /*!< LEDTS EVFR: TPF Mask */\r
-#define LEDTS_EVFR_TSCTROVF_Pos 3 /*!< LEDTS EVFR: TSCTROVF Position */\r
-#define LEDTS_EVFR_TSCTROVF_Msk (0x01UL << LEDTS_EVFR_TSCTROVF_Pos) /*!< LEDTS EVFR: TSCTROVF Mask */\r
-#define LEDTS_EVFR_CTSF_Pos 16 /*!< LEDTS EVFR: CTSF Position */\r
-#define LEDTS_EVFR_CTSF_Msk (0x01UL << LEDTS_EVFR_CTSF_Pos) /*!< LEDTS EVFR: CTSF Mask */\r
-#define LEDTS_EVFR_CTFF_Pos 17 /*!< LEDTS EVFR: CTFF Position */\r
-#define LEDTS_EVFR_CTFF_Msk (0x01UL << LEDTS_EVFR_CTFF_Pos) /*!< LEDTS EVFR: CTFF Mask */\r
-#define LEDTS_EVFR_CTPF_Pos 18 /*!< LEDTS EVFR: CTPF Position */\r
-#define LEDTS_EVFR_CTPF_Msk (0x01UL << LEDTS_EVFR_CTPF_Pos) /*!< LEDTS EVFR: CTPF Mask */\r
-\r
-/* --------------------------------- LEDTS_TSVAL -------------------------------- */\r
-#define LEDTS_TSVAL_TSCTRVALR_Pos 0 /*!< LEDTS TSVAL: TSCTRVALR Position */\r
-#define LEDTS_TSVAL_TSCTRVALR_Msk (0x0000ffffUL << LEDTS_TSVAL_TSCTRVALR_Pos) /*!< LEDTS TSVAL: TSCTRVALR Mask */\r
-#define LEDTS_TSVAL_TSCTRVAL_Pos 16 /*!< LEDTS TSVAL: TSCTRVAL Position */\r
-#define LEDTS_TSVAL_TSCTRVAL_Msk (0x0000ffffUL << LEDTS_TSVAL_TSCTRVAL_Pos) /*!< LEDTS TSVAL: TSCTRVAL Mask */\r
-\r
-/* --------------------------------- LEDTS_LINE0 -------------------------------- */\r
-#define LEDTS_LINE0_LINE_0_Pos 0 /*!< LEDTS LINE0: LINE_0 Position */\r
-#define LEDTS_LINE0_LINE_0_Msk (0x000000ffUL << LEDTS_LINE0_LINE_0_Pos) /*!< LEDTS LINE0: LINE_0 Mask */\r
-#define LEDTS_LINE0_LINE_1_Pos 8 /*!< LEDTS LINE0: LINE_1 Position */\r
-#define LEDTS_LINE0_LINE_1_Msk (0x000000ffUL << LEDTS_LINE0_LINE_1_Pos) /*!< LEDTS LINE0: LINE_1 Mask */\r
-#define LEDTS_LINE0_LINE_2_Pos 16 /*!< LEDTS LINE0: LINE_2 Position */\r
-#define LEDTS_LINE0_LINE_2_Msk (0x000000ffUL << LEDTS_LINE0_LINE_2_Pos) /*!< LEDTS LINE0: LINE_2 Mask */\r
-#define LEDTS_LINE0_LINE_3_Pos 24 /*!< LEDTS LINE0: LINE_3 Position */\r
-#define LEDTS_LINE0_LINE_3_Msk (0x000000ffUL << LEDTS_LINE0_LINE_3_Pos) /*!< LEDTS LINE0: LINE_3 Mask */\r
-\r
-/* --------------------------------- LEDTS_LINE1 -------------------------------- */\r
-#define LEDTS_LINE1_LINE_4_Pos 0 /*!< LEDTS LINE1: LINE_4 Position */\r
-#define LEDTS_LINE1_LINE_4_Msk (0x000000ffUL << LEDTS_LINE1_LINE_4_Pos) /*!< LEDTS LINE1: LINE_4 Mask */\r
-#define LEDTS_LINE1_LINE_5_Pos 8 /*!< LEDTS LINE1: LINE_5 Position */\r
-#define LEDTS_LINE1_LINE_5_Msk (0x000000ffUL << LEDTS_LINE1_LINE_5_Pos) /*!< LEDTS LINE1: LINE_5 Mask */\r
-#define LEDTS_LINE1_LINE_6_Pos 16 /*!< LEDTS LINE1: LINE_6 Position */\r
-#define LEDTS_LINE1_LINE_6_Msk (0x000000ffUL << LEDTS_LINE1_LINE_6_Pos) /*!< LEDTS LINE1: LINE_6 Mask */\r
-#define LEDTS_LINE1_LINE_A_Pos 24 /*!< LEDTS LINE1: LINE_A Position */\r
-#define LEDTS_LINE1_LINE_A_Msk (0x000000ffUL << LEDTS_LINE1_LINE_A_Pos) /*!< LEDTS LINE1: LINE_A Mask */\r
-\r
-/* -------------------------------- LEDTS_LDCMP0 -------------------------------- */\r
-#define LEDTS_LDCMP0_CMP_LD0_Pos 0 /*!< LEDTS LDCMP0: CMP_LD0 Position */\r
-#define LEDTS_LDCMP0_CMP_LD0_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD0_Pos) /*!< LEDTS LDCMP0: CMP_LD0 Mask */\r
-#define LEDTS_LDCMP0_CMP_LD1_Pos 8 /*!< LEDTS LDCMP0: CMP_LD1 Position */\r
-#define LEDTS_LDCMP0_CMP_LD1_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD1_Pos) /*!< LEDTS LDCMP0: CMP_LD1 Mask */\r
-#define LEDTS_LDCMP0_CMP_LD2_Pos 16 /*!< LEDTS LDCMP0: CMP_LD2 Position */\r
-#define LEDTS_LDCMP0_CMP_LD2_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD2_Pos) /*!< LEDTS LDCMP0: CMP_LD2 Mask */\r
-#define LEDTS_LDCMP0_CMP_LD3_Pos 24 /*!< LEDTS LDCMP0: CMP_LD3 Position */\r
-#define LEDTS_LDCMP0_CMP_LD3_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD3_Pos) /*!< LEDTS LDCMP0: CMP_LD3 Mask */\r
-\r
-/* -------------------------------- LEDTS_LDCMP1 -------------------------------- */\r
-#define LEDTS_LDCMP1_CMP_LD4_Pos 0 /*!< LEDTS LDCMP1: CMP_LD4 Position */\r
-#define LEDTS_LDCMP1_CMP_LD4_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD4_Pos) /*!< LEDTS LDCMP1: CMP_LD4 Mask */\r
-#define LEDTS_LDCMP1_CMP_LD5_Pos 8 /*!< LEDTS LDCMP1: CMP_LD5 Position */\r
-#define LEDTS_LDCMP1_CMP_LD5_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD5_Pos) /*!< LEDTS LDCMP1: CMP_LD5 Mask */\r
-#define LEDTS_LDCMP1_CMP_LD6_Pos 16 /*!< LEDTS LDCMP1: CMP_LD6 Position */\r
-#define LEDTS_LDCMP1_CMP_LD6_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD6_Pos) /*!< LEDTS LDCMP1: CMP_LD6 Mask */\r
-#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos 24 /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Position */\r
-#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Mask */\r
-\r
-/* -------------------------------- LEDTS_TSCMP0 -------------------------------- */\r
-#define LEDTS_TSCMP0_CMP_TS0_Pos 0 /*!< LEDTS TSCMP0: CMP_TS0 Position */\r
-#define LEDTS_TSCMP0_CMP_TS0_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS0_Pos) /*!< LEDTS TSCMP0: CMP_TS0 Mask */\r
-#define LEDTS_TSCMP0_CMP_TS1_Pos 8 /*!< LEDTS TSCMP0: CMP_TS1 Position */\r
-#define LEDTS_TSCMP0_CMP_TS1_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS1_Pos) /*!< LEDTS TSCMP0: CMP_TS1 Mask */\r
-#define LEDTS_TSCMP0_CMP_TS2_Pos 16 /*!< LEDTS TSCMP0: CMP_TS2 Position */\r
-#define LEDTS_TSCMP0_CMP_TS2_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS2_Pos) /*!< LEDTS TSCMP0: CMP_TS2 Mask */\r
-#define LEDTS_TSCMP0_CMP_TS3_Pos 24 /*!< LEDTS TSCMP0: CMP_TS3 Position */\r
-#define LEDTS_TSCMP0_CMP_TS3_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS3_Pos) /*!< LEDTS TSCMP0: CMP_TS3 Mask */\r
-\r
-/* -------------------------------- LEDTS_TSCMP1 -------------------------------- */\r
-#define LEDTS_TSCMP1_CMP_TS4_Pos 0 /*!< LEDTS TSCMP1: CMP_TS4 Position */\r
-#define LEDTS_TSCMP1_CMP_TS4_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS4_Pos) /*!< LEDTS TSCMP1: CMP_TS4 Mask */\r
-#define LEDTS_TSCMP1_CMP_TS5_Pos 8 /*!< LEDTS TSCMP1: CMP_TS5 Position */\r
-#define LEDTS_TSCMP1_CMP_TS5_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS5_Pos) /*!< LEDTS TSCMP1: CMP_TS5 Mask */\r
-#define LEDTS_TSCMP1_CMP_TS6_Pos 16 /*!< LEDTS TSCMP1: CMP_TS6 Position */\r
-#define LEDTS_TSCMP1_CMP_TS6_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS6_Pos) /*!< LEDTS TSCMP1: CMP_TS6 Mask */\r
-#define LEDTS_TSCMP1_CMP_TS7_Pos 24 /*!< LEDTS TSCMP1: CMP_TS7 Position */\r
-#define LEDTS_TSCMP1_CMP_TS7_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS7_Pos) /*!< LEDTS TSCMP1: CMP_TS7 Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'USIC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------------- USIC_ID ---------------------------------- */\r
-#define USIC_ID_MOD_REV_Pos 0 /*!< USIC ID: MOD_REV Position */\r
-#define USIC_ID_MOD_REV_Msk (0x000000ffUL << USIC_ID_MOD_REV_Pos) /*!< USIC ID: MOD_REV Mask */\r
-#define USIC_ID_MOD_TYPE_Pos 8 /*!< USIC ID: MOD_TYPE Position */\r
-#define USIC_ID_MOD_TYPE_Msk (0x000000ffUL << USIC_ID_MOD_TYPE_Pos) /*!< USIC ID: MOD_TYPE Mask */\r
-#define USIC_ID_MOD_NUMBER_Pos 16 /*!< USIC ID: MOD_NUMBER Position */\r
-#define USIC_ID_MOD_NUMBER_Msk (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos) /*!< USIC ID: MOD_NUMBER Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'USIC_CH' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- USIC_CH_CCFG -------------------------------- */\r
-#define USIC_CH_CCFG_SSC_Pos 0 /*!< USIC_CH CCFG: SSC Position */\r
-#define USIC_CH_CCFG_SSC_Msk (0x01UL << USIC_CH_CCFG_SSC_Pos) /*!< USIC_CH CCFG: SSC Mask */\r
-#define USIC_CH_CCFG_ASC_Pos 1 /*!< USIC_CH CCFG: ASC Position */\r
-#define USIC_CH_CCFG_ASC_Msk (0x01UL << USIC_CH_CCFG_ASC_Pos) /*!< USIC_CH CCFG: ASC Mask */\r
-#define USIC_CH_CCFG_IIC_Pos 2 /*!< USIC_CH CCFG: IIC Position */\r
-#define USIC_CH_CCFG_IIC_Msk (0x01UL << USIC_CH_CCFG_IIC_Pos) /*!< USIC_CH CCFG: IIC Mask */\r
-#define USIC_CH_CCFG_IIS_Pos 3 /*!< USIC_CH CCFG: IIS Position */\r
-#define USIC_CH_CCFG_IIS_Msk (0x01UL << USIC_CH_CCFG_IIS_Pos) /*!< USIC_CH CCFG: IIS Mask */\r
-#define USIC_CH_CCFG_RB_Pos 6 /*!< USIC_CH CCFG: RB Position */\r
-#define USIC_CH_CCFG_RB_Msk (0x01UL << USIC_CH_CCFG_RB_Pos) /*!< USIC_CH CCFG: RB Mask */\r
-#define USIC_CH_CCFG_TB_Pos 7 /*!< USIC_CH CCFG: TB Position */\r
-#define USIC_CH_CCFG_TB_Msk (0x01UL << USIC_CH_CCFG_TB_Pos) /*!< USIC_CH CCFG: TB Mask */\r
-\r
-/* -------------------------------- USIC_CH_KSCFG ------------------------------- */\r
-#define USIC_CH_KSCFG_MODEN_Pos 0 /*!< USIC_CH KSCFG: MODEN Position */\r
-#define USIC_CH_KSCFG_MODEN_Msk (0x01UL << USIC_CH_KSCFG_MODEN_Pos) /*!< USIC_CH KSCFG: MODEN Mask */\r
-#define USIC_CH_KSCFG_BPMODEN_Pos 1 /*!< USIC_CH KSCFG: BPMODEN Position */\r
-#define USIC_CH_KSCFG_BPMODEN_Msk (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos) /*!< USIC_CH KSCFG: BPMODEN Mask */\r
-#define USIC_CH_KSCFG_NOMCFG_Pos 4 /*!< USIC_CH KSCFG: NOMCFG Position */\r
-#define USIC_CH_KSCFG_NOMCFG_Msk (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos) /*!< USIC_CH KSCFG: NOMCFG Mask */\r
-#define USIC_CH_KSCFG_BPNOM_Pos 7 /*!< USIC_CH KSCFG: BPNOM Position */\r
-#define USIC_CH_KSCFG_BPNOM_Msk (0x01UL << USIC_CH_KSCFG_BPNOM_Pos) /*!< USIC_CH KSCFG: BPNOM Mask */\r
-#define USIC_CH_KSCFG_SUMCFG_Pos 8 /*!< USIC_CH KSCFG: SUMCFG Position */\r
-#define USIC_CH_KSCFG_SUMCFG_Msk (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos) /*!< USIC_CH KSCFG: SUMCFG Mask */\r
-#define USIC_CH_KSCFG_BPSUM_Pos 11 /*!< USIC_CH KSCFG: BPSUM Position */\r
-#define USIC_CH_KSCFG_BPSUM_Msk (0x01UL << USIC_CH_KSCFG_BPSUM_Pos) /*!< USIC_CH KSCFG: BPSUM Mask */\r
-\r
-/* --------------------------------- USIC_CH_FDR -------------------------------- */\r
-#define USIC_CH_FDR_STEP_Pos 0 /*!< USIC_CH FDR: STEP Position */\r
-#define USIC_CH_FDR_STEP_Msk (0x000003ffUL << USIC_CH_FDR_STEP_Pos) /*!< USIC_CH FDR: STEP Mask */\r
-#define USIC_CH_FDR_DM_Pos 14 /*!< USIC_CH FDR: DM Position */\r
-#define USIC_CH_FDR_DM_Msk (0x03UL << USIC_CH_FDR_DM_Pos) /*!< USIC_CH FDR: DM Mask */\r
-#define USIC_CH_FDR_RESULT_Pos 16 /*!< USIC_CH FDR: RESULT Position */\r
-#define USIC_CH_FDR_RESULT_Msk (0x000003ffUL << USIC_CH_FDR_RESULT_Pos) /*!< USIC_CH FDR: RESULT Mask */\r
-\r
-/* --------------------------------- USIC_CH_BRG -------------------------------- */\r
-#define USIC_CH_BRG_CLKSEL_Pos 0 /*!< USIC_CH BRG: CLKSEL Position */\r
-#define USIC_CH_BRG_CLKSEL_Msk (0x03UL << USIC_CH_BRG_CLKSEL_Pos) /*!< USIC_CH BRG: CLKSEL Mask */\r
-#define USIC_CH_BRG_TMEN_Pos 3 /*!< USIC_CH BRG: TMEN Position */\r
-#define USIC_CH_BRG_TMEN_Msk (0x01UL << USIC_CH_BRG_TMEN_Pos) /*!< USIC_CH BRG: TMEN Mask */\r
-#define USIC_CH_BRG_PPPEN_Pos 4 /*!< USIC_CH BRG: PPPEN Position */\r
-#define USIC_CH_BRG_PPPEN_Msk (0x01UL << USIC_CH_BRG_PPPEN_Pos) /*!< USIC_CH BRG: PPPEN Mask */\r
-#define USIC_CH_BRG_CTQSEL_Pos 6 /*!< USIC_CH BRG: CTQSEL Position */\r
-#define USIC_CH_BRG_CTQSEL_Msk (0x03UL << USIC_CH_BRG_CTQSEL_Pos) /*!< USIC_CH BRG: CTQSEL Mask */\r
-#define USIC_CH_BRG_PCTQ_Pos 8 /*!< USIC_CH BRG: PCTQ Position */\r
-#define USIC_CH_BRG_PCTQ_Msk (0x03UL << USIC_CH_BRG_PCTQ_Pos) /*!< USIC_CH BRG: PCTQ Mask */\r
-#define USIC_CH_BRG_DCTQ_Pos 10 /*!< USIC_CH BRG: DCTQ Position */\r
-#define USIC_CH_BRG_DCTQ_Msk (0x1fUL << USIC_CH_BRG_DCTQ_Pos) /*!< USIC_CH BRG: DCTQ Mask */\r
-#define USIC_CH_BRG_PDIV_Pos 16 /*!< USIC_CH BRG: PDIV Position */\r
-#define USIC_CH_BRG_PDIV_Msk (0x000003ffUL << USIC_CH_BRG_PDIV_Pos) /*!< USIC_CH BRG: PDIV Mask */\r
-#define USIC_CH_BRG_SCLKOSEL_Pos 28 /*!< USIC_CH BRG: SCLKOSEL Position */\r
-#define USIC_CH_BRG_SCLKOSEL_Msk (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos) /*!< USIC_CH BRG: SCLKOSEL Mask */\r
-#define USIC_CH_BRG_MCLKCFG_Pos 29 /*!< USIC_CH BRG: MCLKCFG Position */\r
-#define USIC_CH_BRG_MCLKCFG_Msk (0x01UL << USIC_CH_BRG_MCLKCFG_Pos) /*!< USIC_CH BRG: MCLKCFG Mask */\r
-#define USIC_CH_BRG_SCLKCFG_Pos 30 /*!< USIC_CH BRG: SCLKCFG Position */\r
-#define USIC_CH_BRG_SCLKCFG_Msk (0x03UL << USIC_CH_BRG_SCLKCFG_Pos) /*!< USIC_CH BRG: SCLKCFG Mask */\r
-\r
-/* -------------------------------- USIC_CH_INPR -------------------------------- */\r
-#define USIC_CH_INPR_TSINP_Pos 0 /*!< USIC_CH INPR: TSINP Position */\r
-#define USIC_CH_INPR_TSINP_Msk (0x07UL << USIC_CH_INPR_TSINP_Pos) /*!< USIC_CH INPR: TSINP Mask */\r
-#define USIC_CH_INPR_TBINP_Pos 4 /*!< USIC_CH INPR: TBINP Position */\r
-#define USIC_CH_INPR_TBINP_Msk (0x07UL << USIC_CH_INPR_TBINP_Pos) /*!< USIC_CH INPR: TBINP Mask */\r
-#define USIC_CH_INPR_RINP_Pos 8 /*!< USIC_CH INPR: RINP Position */\r
-#define USIC_CH_INPR_RINP_Msk (0x07UL << USIC_CH_INPR_RINP_Pos) /*!< USIC_CH INPR: RINP Mask */\r
-#define USIC_CH_INPR_AINP_Pos 12 /*!< USIC_CH INPR: AINP Position */\r
-#define USIC_CH_INPR_AINP_Msk (0x07UL << USIC_CH_INPR_AINP_Pos) /*!< USIC_CH INPR: AINP Mask */\r
-#define USIC_CH_INPR_PINP_Pos 16 /*!< USIC_CH INPR: PINP Position */\r
-#define USIC_CH_INPR_PINP_Msk (0x07UL << USIC_CH_INPR_PINP_Pos) /*!< USIC_CH INPR: PINP Mask */\r
-\r
-/* -------------------------------- USIC_CH_DX0CR ------------------------------- */\r
-#define USIC_CH_DX0CR_DSEL_Pos 0 /*!< USIC_CH DX0CR: DSEL Position */\r
-#define USIC_CH_DX0CR_DSEL_Msk (0x07UL << USIC_CH_DX0CR_DSEL_Pos) /*!< USIC_CH DX0CR: DSEL Mask */\r
-#define USIC_CH_DX0CR_INSW_Pos 4 /*!< USIC_CH DX0CR: INSW Position */\r
-#define USIC_CH_DX0CR_INSW_Msk (0x01UL << USIC_CH_DX0CR_INSW_Pos) /*!< USIC_CH DX0CR: INSW Mask */\r
-#define USIC_CH_DX0CR_DFEN_Pos 5 /*!< USIC_CH DX0CR: DFEN Position */\r
-#define USIC_CH_DX0CR_DFEN_Msk (0x01UL << USIC_CH_DX0CR_DFEN_Pos) /*!< USIC_CH DX0CR: DFEN Mask */\r
-#define USIC_CH_DX0CR_DSEN_Pos 6 /*!< USIC_CH DX0CR: DSEN Position */\r
-#define USIC_CH_DX0CR_DSEN_Msk (0x01UL << USIC_CH_DX0CR_DSEN_Pos) /*!< USIC_CH DX0CR: DSEN Mask */\r
-#define USIC_CH_DX0CR_DPOL_Pos 8 /*!< USIC_CH DX0CR: DPOL Position */\r
-#define USIC_CH_DX0CR_DPOL_Msk (0x01UL << USIC_CH_DX0CR_DPOL_Pos) /*!< USIC_CH DX0CR: DPOL Mask */\r
-#define USIC_CH_DX0CR_SFSEL_Pos 9 /*!< USIC_CH DX0CR: SFSEL Position */\r
-#define USIC_CH_DX0CR_SFSEL_Msk (0x01UL << USIC_CH_DX0CR_SFSEL_Pos) /*!< USIC_CH DX0CR: SFSEL Mask */\r
-#define USIC_CH_DX0CR_CM_Pos 10 /*!< USIC_CH DX0CR: CM Position */\r
-#define USIC_CH_DX0CR_CM_Msk (0x03UL << USIC_CH_DX0CR_CM_Pos) /*!< USIC_CH DX0CR: CM Mask */\r
-#define USIC_CH_DX0CR_DXS_Pos 15 /*!< USIC_CH DX0CR: DXS Position */\r
-#define USIC_CH_DX0CR_DXS_Msk (0x01UL << USIC_CH_DX0CR_DXS_Pos) /*!< USIC_CH DX0CR: DXS Mask */\r
-\r
-/* -------------------------------- USIC_CH_DX1CR ------------------------------- */\r
-#define USIC_CH_DX1CR_DSEL_Pos 0 /*!< USIC_CH DX1CR: DSEL Position */\r
-#define USIC_CH_DX1CR_DSEL_Msk (0x07UL << USIC_CH_DX1CR_DSEL_Pos) /*!< USIC_CH DX1CR: DSEL Mask */\r
-#define USIC_CH_DX1CR_DCEN_Pos 3 /*!< USIC_CH DX1CR: DCEN Position */\r
-#define USIC_CH_DX1CR_DCEN_Msk (0x01UL << USIC_CH_DX1CR_DCEN_Pos) /*!< USIC_CH DX1CR: DCEN Mask */\r
-#define USIC_CH_DX1CR_INSW_Pos 4 /*!< USIC_CH DX1CR: INSW Position */\r
-#define USIC_CH_DX1CR_INSW_Msk (0x01UL << USIC_CH_DX1CR_INSW_Pos) /*!< USIC_CH DX1CR: INSW Mask */\r
-#define USIC_CH_DX1CR_DFEN_Pos 5 /*!< USIC_CH DX1CR: DFEN Position */\r
-#define USIC_CH_DX1CR_DFEN_Msk (0x01UL << USIC_CH_DX1CR_DFEN_Pos) /*!< USIC_CH DX1CR: DFEN Mask */\r
-#define USIC_CH_DX1CR_DSEN_Pos 6 /*!< USIC_CH DX1CR: DSEN Position */\r
-#define USIC_CH_DX1CR_DSEN_Msk (0x01UL << USIC_CH_DX1CR_DSEN_Pos) /*!< USIC_CH DX1CR: DSEN Mask */\r
-#define USIC_CH_DX1CR_DPOL_Pos 8 /*!< USIC_CH DX1CR: DPOL Position */\r
-#define USIC_CH_DX1CR_DPOL_Msk (0x01UL << USIC_CH_DX1CR_DPOL_Pos) /*!< USIC_CH DX1CR: DPOL Mask */\r
-#define USIC_CH_DX1CR_SFSEL_Pos 9 /*!< USIC_CH DX1CR: SFSEL Position */\r
-#define USIC_CH_DX1CR_SFSEL_Msk (0x01UL << USIC_CH_DX1CR_SFSEL_Pos) /*!< USIC_CH DX1CR: SFSEL Mask */\r
-#define USIC_CH_DX1CR_CM_Pos 10 /*!< USIC_CH DX1CR: CM Position */\r
-#define USIC_CH_DX1CR_CM_Msk (0x03UL << USIC_CH_DX1CR_CM_Pos) /*!< USIC_CH DX1CR: CM Mask */\r
-#define USIC_CH_DX1CR_DXS_Pos 15 /*!< USIC_CH DX1CR: DXS Position */\r
-#define USIC_CH_DX1CR_DXS_Msk (0x01UL << USIC_CH_DX1CR_DXS_Pos) /*!< USIC_CH DX1CR: DXS Mask */\r
-\r
-/* -------------------------------- USIC_CH_DX2CR ------------------------------- */\r
-#define USIC_CH_DX2CR_DSEL_Pos 0 /*!< USIC_CH DX2CR: DSEL Position */\r
-#define USIC_CH_DX2CR_DSEL_Msk (0x07UL << USIC_CH_DX2CR_DSEL_Pos) /*!< USIC_CH DX2CR: DSEL Mask */\r
-#define USIC_CH_DX2CR_INSW_Pos 4 /*!< USIC_CH DX2CR: INSW Position */\r
-#define USIC_CH_DX2CR_INSW_Msk (0x01UL << USIC_CH_DX2CR_INSW_Pos) /*!< USIC_CH DX2CR: INSW Mask */\r
-#define USIC_CH_DX2CR_DFEN_Pos 5 /*!< USIC_CH DX2CR: DFEN Position */\r
-#define USIC_CH_DX2CR_DFEN_Msk (0x01UL << USIC_CH_DX2CR_DFEN_Pos) /*!< USIC_CH DX2CR: DFEN Mask */\r
-#define USIC_CH_DX2CR_DSEN_Pos 6 /*!< USIC_CH DX2CR: DSEN Position */\r
-#define USIC_CH_DX2CR_DSEN_Msk (0x01UL << USIC_CH_DX2CR_DSEN_Pos) /*!< USIC_CH DX2CR: DSEN Mask */\r
-#define USIC_CH_DX2CR_DPOL_Pos 8 /*!< USIC_CH DX2CR: DPOL Position */\r
-#define USIC_CH_DX2CR_DPOL_Msk (0x01UL << USIC_CH_DX2CR_DPOL_Pos) /*!< USIC_CH DX2CR: DPOL Mask */\r
-#define USIC_CH_DX2CR_SFSEL_Pos 9 /*!< USIC_CH DX2CR: SFSEL Position */\r
-#define USIC_CH_DX2CR_SFSEL_Msk (0x01UL << USIC_CH_DX2CR_SFSEL_Pos) /*!< USIC_CH DX2CR: SFSEL Mask */\r
-#define USIC_CH_DX2CR_CM_Pos 10 /*!< USIC_CH DX2CR: CM Position */\r
-#define USIC_CH_DX2CR_CM_Msk (0x03UL << USIC_CH_DX2CR_CM_Pos) /*!< USIC_CH DX2CR: CM Mask */\r
-#define USIC_CH_DX2CR_DXS_Pos 15 /*!< USIC_CH DX2CR: DXS Position */\r
-#define USIC_CH_DX2CR_DXS_Msk (0x01UL << USIC_CH_DX2CR_DXS_Pos) /*!< USIC_CH DX2CR: DXS Mask */\r
-\r
-/* -------------------------------- USIC_CH_DX3CR ------------------------------- */\r
-#define USIC_CH_DX3CR_DSEL_Pos 0 /*!< USIC_CH DX3CR: DSEL Position */\r
-#define USIC_CH_DX3CR_DSEL_Msk (0x07UL << USIC_CH_DX3CR_DSEL_Pos) /*!< USIC_CH DX3CR: DSEL Mask */\r
-#define USIC_CH_DX3CR_INSW_Pos 4 /*!< USIC_CH DX3CR: INSW Position */\r
-#define USIC_CH_DX3CR_INSW_Msk (0x01UL << USIC_CH_DX3CR_INSW_Pos) /*!< USIC_CH DX3CR: INSW Mask */\r
-#define USIC_CH_DX3CR_DFEN_Pos 5 /*!< USIC_CH DX3CR: DFEN Position */\r
-#define USIC_CH_DX3CR_DFEN_Msk (0x01UL << USIC_CH_DX3CR_DFEN_Pos) /*!< USIC_CH DX3CR: DFEN Mask */\r
-#define USIC_CH_DX3CR_DSEN_Pos 6 /*!< USIC_CH DX3CR: DSEN Position */\r
-#define USIC_CH_DX3CR_DSEN_Msk (0x01UL << USIC_CH_DX3CR_DSEN_Pos) /*!< USIC_CH DX3CR: DSEN Mask */\r
-#define USIC_CH_DX3CR_DPOL_Pos 8 /*!< USIC_CH DX3CR: DPOL Position */\r
-#define USIC_CH_DX3CR_DPOL_Msk (0x01UL << USIC_CH_DX3CR_DPOL_Pos) /*!< USIC_CH DX3CR: DPOL Mask */\r
-#define USIC_CH_DX3CR_SFSEL_Pos 9 /*!< USIC_CH DX3CR: SFSEL Position */\r
-#define USIC_CH_DX3CR_SFSEL_Msk (0x01UL << USIC_CH_DX3CR_SFSEL_Pos) /*!< USIC_CH DX3CR: SFSEL Mask */\r
-#define USIC_CH_DX3CR_CM_Pos 10 /*!< USIC_CH DX3CR: CM Position */\r
-#define USIC_CH_DX3CR_CM_Msk (0x03UL << USIC_CH_DX3CR_CM_Pos) /*!< USIC_CH DX3CR: CM Mask */\r
-#define USIC_CH_DX3CR_DXS_Pos 15 /*!< USIC_CH DX3CR: DXS Position */\r
-#define USIC_CH_DX3CR_DXS_Msk (0x01UL << USIC_CH_DX3CR_DXS_Pos) /*!< USIC_CH DX3CR: DXS Mask */\r
-\r
-/* -------------------------------- USIC_CH_DX4CR ------------------------------- */\r
-#define USIC_CH_DX4CR_DSEL_Pos 0 /*!< USIC_CH DX4CR: DSEL Position */\r
-#define USIC_CH_DX4CR_DSEL_Msk (0x07UL << USIC_CH_DX4CR_DSEL_Pos) /*!< USIC_CH DX4CR: DSEL Mask */\r
-#define USIC_CH_DX4CR_INSW_Pos 4 /*!< USIC_CH DX4CR: INSW Position */\r
-#define USIC_CH_DX4CR_INSW_Msk (0x01UL << USIC_CH_DX4CR_INSW_Pos) /*!< USIC_CH DX4CR: INSW Mask */\r
-#define USIC_CH_DX4CR_DFEN_Pos 5 /*!< USIC_CH DX4CR: DFEN Position */\r
-#define USIC_CH_DX4CR_DFEN_Msk (0x01UL << USIC_CH_DX4CR_DFEN_Pos) /*!< USIC_CH DX4CR: DFEN Mask */\r
-#define USIC_CH_DX4CR_DSEN_Pos 6 /*!< USIC_CH DX4CR: DSEN Position */\r
-#define USIC_CH_DX4CR_DSEN_Msk (0x01UL << USIC_CH_DX4CR_DSEN_Pos) /*!< USIC_CH DX4CR: DSEN Mask */\r
-#define USIC_CH_DX4CR_DPOL_Pos 8 /*!< USIC_CH DX4CR: DPOL Position */\r
-#define USIC_CH_DX4CR_DPOL_Msk (0x01UL << USIC_CH_DX4CR_DPOL_Pos) /*!< USIC_CH DX4CR: DPOL Mask */\r
-#define USIC_CH_DX4CR_SFSEL_Pos 9 /*!< USIC_CH DX4CR: SFSEL Position */\r
-#define USIC_CH_DX4CR_SFSEL_Msk (0x01UL << USIC_CH_DX4CR_SFSEL_Pos) /*!< USIC_CH DX4CR: SFSEL Mask */\r
-#define USIC_CH_DX4CR_CM_Pos 10 /*!< USIC_CH DX4CR: CM Position */\r
-#define USIC_CH_DX4CR_CM_Msk (0x03UL << USIC_CH_DX4CR_CM_Pos) /*!< USIC_CH DX4CR: CM Mask */\r
-#define USIC_CH_DX4CR_DXS_Pos 15 /*!< USIC_CH DX4CR: DXS Position */\r
-#define USIC_CH_DX4CR_DXS_Msk (0x01UL << USIC_CH_DX4CR_DXS_Pos) /*!< USIC_CH DX4CR: DXS Mask */\r
-\r
-/* -------------------------------- USIC_CH_DX5CR ------------------------------- */\r
-#define USIC_CH_DX5CR_DSEL_Pos 0 /*!< USIC_CH DX5CR: DSEL Position */\r
-#define USIC_CH_DX5CR_DSEL_Msk (0x07UL << USIC_CH_DX5CR_DSEL_Pos) /*!< USIC_CH DX5CR: DSEL Mask */\r
-#define USIC_CH_DX5CR_INSW_Pos 4 /*!< USIC_CH DX5CR: INSW Position */\r
-#define USIC_CH_DX5CR_INSW_Msk (0x01UL << USIC_CH_DX5CR_INSW_Pos) /*!< USIC_CH DX5CR: INSW Mask */\r
-#define USIC_CH_DX5CR_DFEN_Pos 5 /*!< USIC_CH DX5CR: DFEN Position */\r
-#define USIC_CH_DX5CR_DFEN_Msk (0x01UL << USIC_CH_DX5CR_DFEN_Pos) /*!< USIC_CH DX5CR: DFEN Mask */\r
-#define USIC_CH_DX5CR_DSEN_Pos 6 /*!< USIC_CH DX5CR: DSEN Position */\r
-#define USIC_CH_DX5CR_DSEN_Msk (0x01UL << USIC_CH_DX5CR_DSEN_Pos) /*!< USIC_CH DX5CR: DSEN Mask */\r
-#define USIC_CH_DX5CR_DPOL_Pos 8 /*!< USIC_CH DX5CR: DPOL Position */\r
-#define USIC_CH_DX5CR_DPOL_Msk (0x01UL << USIC_CH_DX5CR_DPOL_Pos) /*!< USIC_CH DX5CR: DPOL Mask */\r
-#define USIC_CH_DX5CR_SFSEL_Pos 9 /*!< USIC_CH DX5CR: SFSEL Position */\r
-#define USIC_CH_DX5CR_SFSEL_Msk (0x01UL << USIC_CH_DX5CR_SFSEL_Pos) /*!< USIC_CH DX5CR: SFSEL Mask */\r
-#define USIC_CH_DX5CR_CM_Pos 10 /*!< USIC_CH DX5CR: CM Position */\r
-#define USIC_CH_DX5CR_CM_Msk (0x03UL << USIC_CH_DX5CR_CM_Pos) /*!< USIC_CH DX5CR: CM Mask */\r
-#define USIC_CH_DX5CR_DXS_Pos 15 /*!< USIC_CH DX5CR: DXS Position */\r
-#define USIC_CH_DX5CR_DXS_Msk (0x01UL << USIC_CH_DX5CR_DXS_Pos) /*!< USIC_CH DX5CR: DXS Mask */\r
-\r
-/* -------------------------------- USIC_CH_SCTR -------------------------------- */\r
-#define USIC_CH_SCTR_SDIR_Pos 0 /*!< USIC_CH SCTR: SDIR Position */\r
-#define USIC_CH_SCTR_SDIR_Msk (0x01UL << USIC_CH_SCTR_SDIR_Pos) /*!< USIC_CH SCTR: SDIR Mask */\r
-#define USIC_CH_SCTR_PDL_Pos 1 /*!< USIC_CH SCTR: PDL Position */\r
-#define USIC_CH_SCTR_PDL_Msk (0x01UL << USIC_CH_SCTR_PDL_Pos) /*!< USIC_CH SCTR: PDL Mask */\r
-#define USIC_CH_SCTR_DSM_Pos 2 /*!< USIC_CH SCTR: DSM Position */\r
-#define USIC_CH_SCTR_DSM_Msk (0x03UL << USIC_CH_SCTR_DSM_Pos) /*!< USIC_CH SCTR: DSM Mask */\r
-#define USIC_CH_SCTR_HPCDIR_Pos 4 /*!< USIC_CH SCTR: HPCDIR Position */\r
-#define USIC_CH_SCTR_HPCDIR_Msk (0x01UL << USIC_CH_SCTR_HPCDIR_Pos) /*!< USIC_CH SCTR: HPCDIR Mask */\r
-#define USIC_CH_SCTR_DOCFG_Pos 6 /*!< USIC_CH SCTR: DOCFG Position */\r
-#define USIC_CH_SCTR_DOCFG_Msk (0x03UL << USIC_CH_SCTR_DOCFG_Pos) /*!< USIC_CH SCTR: DOCFG Mask */\r
-#define USIC_CH_SCTR_TRM_Pos 8 /*!< USIC_CH SCTR: TRM Position */\r
-#define USIC_CH_SCTR_TRM_Msk (0x03UL << USIC_CH_SCTR_TRM_Pos) /*!< USIC_CH SCTR: TRM Mask */\r
-#define USIC_CH_SCTR_FLE_Pos 16 /*!< USIC_CH SCTR: FLE Position */\r
-#define USIC_CH_SCTR_FLE_Msk (0x3fUL << USIC_CH_SCTR_FLE_Pos) /*!< USIC_CH SCTR: FLE Mask */\r
-#define USIC_CH_SCTR_WLE_Pos 24 /*!< USIC_CH SCTR: WLE Position */\r
-#define USIC_CH_SCTR_WLE_Msk (0x0fUL << USIC_CH_SCTR_WLE_Pos) /*!< USIC_CH SCTR: WLE Mask */\r
-\r
-/* -------------------------------- USIC_CH_TCSR -------------------------------- */\r
-#define USIC_CH_TCSR_WLEMD_Pos 0 /*!< USIC_CH TCSR: WLEMD Position */\r
-#define USIC_CH_TCSR_WLEMD_Msk (0x01UL << USIC_CH_TCSR_WLEMD_Pos) /*!< USIC_CH TCSR: WLEMD Mask */\r
-#define USIC_CH_TCSR_SELMD_Pos 1 /*!< USIC_CH TCSR: SELMD Position */\r
-#define USIC_CH_TCSR_SELMD_Msk (0x01UL << USIC_CH_TCSR_SELMD_Pos) /*!< USIC_CH TCSR: SELMD Mask */\r
-#define USIC_CH_TCSR_FLEMD_Pos 2 /*!< USIC_CH TCSR: FLEMD Position */\r
-#define USIC_CH_TCSR_FLEMD_Msk (0x01UL << USIC_CH_TCSR_FLEMD_Pos) /*!< USIC_CH TCSR: FLEMD Mask */\r
-#define USIC_CH_TCSR_WAMD_Pos 3 /*!< USIC_CH TCSR: WAMD Position */\r
-#define USIC_CH_TCSR_WAMD_Msk (0x01UL << USIC_CH_TCSR_WAMD_Pos) /*!< USIC_CH TCSR: WAMD Mask */\r
-#define USIC_CH_TCSR_HPCMD_Pos 4 /*!< USIC_CH TCSR: HPCMD Position */\r
-#define USIC_CH_TCSR_HPCMD_Msk (0x01UL << USIC_CH_TCSR_HPCMD_Pos) /*!< USIC_CH TCSR: HPCMD Mask */\r
-#define USIC_CH_TCSR_SOF_Pos 5 /*!< USIC_CH TCSR: SOF Position */\r
-#define USIC_CH_TCSR_SOF_Msk (0x01UL << USIC_CH_TCSR_SOF_Pos) /*!< USIC_CH TCSR: SOF Mask */\r
-#define USIC_CH_TCSR_EOF_Pos 6 /*!< USIC_CH TCSR: EOF Position */\r
-#define USIC_CH_TCSR_EOF_Msk (0x01UL << USIC_CH_TCSR_EOF_Pos) /*!< USIC_CH TCSR: EOF Mask */\r
-#define USIC_CH_TCSR_TDV_Pos 7 /*!< USIC_CH TCSR: TDV Position */\r
-#define USIC_CH_TCSR_TDV_Msk (0x01UL << USIC_CH_TCSR_TDV_Pos) /*!< USIC_CH TCSR: TDV Mask */\r
-#define USIC_CH_TCSR_TDSSM_Pos 8 /*!< USIC_CH TCSR: TDSSM Position */\r
-#define USIC_CH_TCSR_TDSSM_Msk (0x01UL << USIC_CH_TCSR_TDSSM_Pos) /*!< USIC_CH TCSR: TDSSM Mask */\r
-#define USIC_CH_TCSR_TDEN_Pos 10 /*!< USIC_CH TCSR: TDEN Position */\r
-#define USIC_CH_TCSR_TDEN_Msk (0x03UL << USIC_CH_TCSR_TDEN_Pos) /*!< USIC_CH TCSR: TDEN Mask */\r
-#define USIC_CH_TCSR_TDVTR_Pos 12 /*!< USIC_CH TCSR: TDVTR Position */\r
-#define USIC_CH_TCSR_TDVTR_Msk (0x01UL << USIC_CH_TCSR_TDVTR_Pos) /*!< USIC_CH TCSR: TDVTR Mask */\r
-#define USIC_CH_TCSR_WA_Pos 13 /*!< USIC_CH TCSR: WA Position */\r
-#define USIC_CH_TCSR_WA_Msk (0x01UL << USIC_CH_TCSR_WA_Pos) /*!< USIC_CH TCSR: WA Mask */\r
-#define USIC_CH_TCSR_TSOF_Pos 24 /*!< USIC_CH TCSR: TSOF Position */\r
-#define USIC_CH_TCSR_TSOF_Msk (0x01UL << USIC_CH_TCSR_TSOF_Pos) /*!< USIC_CH TCSR: TSOF Mask */\r
-#define USIC_CH_TCSR_TV_Pos 26 /*!< USIC_CH TCSR: TV Position */\r
-#define USIC_CH_TCSR_TV_Msk (0x01UL << USIC_CH_TCSR_TV_Pos) /*!< USIC_CH TCSR: TV Mask */\r
-#define USIC_CH_TCSR_TVC_Pos 27 /*!< USIC_CH TCSR: TVC Position */\r
-#define USIC_CH_TCSR_TVC_Msk (0x01UL << USIC_CH_TCSR_TVC_Pos) /*!< USIC_CH TCSR: TVC Mask */\r
-#define USIC_CH_TCSR_TE_Pos 28 /*!< USIC_CH TCSR: TE Position */\r
-#define USIC_CH_TCSR_TE_Msk (0x01UL << USIC_CH_TCSR_TE_Pos) /*!< USIC_CH TCSR: TE Mask */\r
-\r
-/* --------------------------------- USIC_CH_PCR -------------------------------- */\r
-#define USIC_CH_PCR_CTR0_Pos 0 /*!< USIC_CH PCR: CTR0 Position */\r
-#define USIC_CH_PCR_CTR0_Msk (0x01UL << USIC_CH_PCR_CTR0_Pos) /*!< USIC_CH PCR: CTR0 Mask */\r
-#define USIC_CH_PCR_CTR1_Pos 1 /*!< USIC_CH PCR: CTR1 Position */\r
-#define USIC_CH_PCR_CTR1_Msk (0x01UL << USIC_CH_PCR_CTR1_Pos) /*!< USIC_CH PCR: CTR1 Mask */\r
-#define USIC_CH_PCR_CTR2_Pos 2 /*!< USIC_CH PCR: CTR2 Position */\r
-#define USIC_CH_PCR_CTR2_Msk (0x01UL << USIC_CH_PCR_CTR2_Pos) /*!< USIC_CH PCR: CTR2 Mask */\r
-#define USIC_CH_PCR_CTR3_Pos 3 /*!< USIC_CH PCR: CTR3 Position */\r
-#define USIC_CH_PCR_CTR3_Msk (0x01UL << USIC_CH_PCR_CTR3_Pos) /*!< USIC_CH PCR: CTR3 Mask */\r
-#define USIC_CH_PCR_CTR4_Pos 4 /*!< USIC_CH PCR: CTR4 Position */\r
-#define USIC_CH_PCR_CTR4_Msk (0x01UL << USIC_CH_PCR_CTR4_Pos) /*!< USIC_CH PCR: CTR4 Mask */\r
-#define USIC_CH_PCR_CTR5_Pos 5 /*!< USIC_CH PCR: CTR5 Position */\r
-#define USIC_CH_PCR_CTR5_Msk (0x01UL << USIC_CH_PCR_CTR5_Pos) /*!< USIC_CH PCR: CTR5 Mask */\r
-#define USIC_CH_PCR_CTR6_Pos 6 /*!< USIC_CH PCR: CTR6 Position */\r
-#define USIC_CH_PCR_CTR6_Msk (0x01UL << USIC_CH_PCR_CTR6_Pos) /*!< USIC_CH PCR: CTR6 Mask */\r
-#define USIC_CH_PCR_CTR7_Pos 7 /*!< USIC_CH PCR: CTR7 Position */\r
-#define USIC_CH_PCR_CTR7_Msk (0x01UL << USIC_CH_PCR_CTR7_Pos) /*!< USIC_CH PCR: CTR7 Mask */\r
-#define USIC_CH_PCR_CTR8_Pos 8 /*!< USIC_CH PCR: CTR8 Position */\r
-#define USIC_CH_PCR_CTR8_Msk (0x01UL << USIC_CH_PCR_CTR8_Pos) /*!< USIC_CH PCR: CTR8 Mask */\r
-#define USIC_CH_PCR_CTR9_Pos 9 /*!< USIC_CH PCR: CTR9 Position */\r
-#define USIC_CH_PCR_CTR9_Msk (0x01UL << USIC_CH_PCR_CTR9_Pos) /*!< USIC_CH PCR: CTR9 Mask */\r
-#define USIC_CH_PCR_CTR10_Pos 10 /*!< USIC_CH PCR: CTR10 Position */\r
-#define USIC_CH_PCR_CTR10_Msk (0x01UL << USIC_CH_PCR_CTR10_Pos) /*!< USIC_CH PCR: CTR10 Mask */\r
-#define USIC_CH_PCR_CTR11_Pos 11 /*!< USIC_CH PCR: CTR11 Position */\r
-#define USIC_CH_PCR_CTR11_Msk (0x01UL << USIC_CH_PCR_CTR11_Pos) /*!< USIC_CH PCR: CTR11 Mask */\r
-#define USIC_CH_PCR_CTR12_Pos 12 /*!< USIC_CH PCR: CTR12 Position */\r
-#define USIC_CH_PCR_CTR12_Msk (0x01UL << USIC_CH_PCR_CTR12_Pos) /*!< USIC_CH PCR: CTR12 Mask */\r
-#define USIC_CH_PCR_CTR13_Pos 13 /*!< USIC_CH PCR: CTR13 Position */\r
-#define USIC_CH_PCR_CTR13_Msk (0x01UL << USIC_CH_PCR_CTR13_Pos) /*!< USIC_CH PCR: CTR13 Mask */\r
-#define USIC_CH_PCR_CTR14_Pos 14 /*!< USIC_CH PCR: CTR14 Position */\r
-#define USIC_CH_PCR_CTR14_Msk (0x01UL << USIC_CH_PCR_CTR14_Pos) /*!< USIC_CH PCR: CTR14 Mask */\r
-#define USIC_CH_PCR_CTR15_Pos 15 /*!< USIC_CH PCR: CTR15 Position */\r
-#define USIC_CH_PCR_CTR15_Msk (0x01UL << USIC_CH_PCR_CTR15_Pos) /*!< USIC_CH PCR: CTR15 Mask */\r
-#define USIC_CH_PCR_CTR16_Pos 16 /*!< USIC_CH PCR: CTR16 Position */\r
-#define USIC_CH_PCR_CTR16_Msk (0x01UL << USIC_CH_PCR_CTR16_Pos) /*!< USIC_CH PCR: CTR16 Mask */\r
-#define USIC_CH_PCR_CTR17_Pos 17 /*!< USIC_CH PCR: CTR17 Position */\r
-#define USIC_CH_PCR_CTR17_Msk (0x01UL << USIC_CH_PCR_CTR17_Pos) /*!< USIC_CH PCR: CTR17 Mask */\r
-#define USIC_CH_PCR_CTR18_Pos 18 /*!< USIC_CH PCR: CTR18 Position */\r
-#define USIC_CH_PCR_CTR18_Msk (0x01UL << USIC_CH_PCR_CTR18_Pos) /*!< USIC_CH PCR: CTR18 Mask */\r
-#define USIC_CH_PCR_CTR19_Pos 19 /*!< USIC_CH PCR: CTR19 Position */\r
-#define USIC_CH_PCR_CTR19_Msk (0x01UL << USIC_CH_PCR_CTR19_Pos) /*!< USIC_CH PCR: CTR19 Mask */\r
-#define USIC_CH_PCR_CTR20_Pos 20 /*!< USIC_CH PCR: CTR20 Position */\r
-#define USIC_CH_PCR_CTR20_Msk (0x01UL << USIC_CH_PCR_CTR20_Pos) /*!< USIC_CH PCR: CTR20 Mask */\r
-#define USIC_CH_PCR_CTR21_Pos 21 /*!< USIC_CH PCR: CTR21 Position */\r
-#define USIC_CH_PCR_CTR21_Msk (0x01UL << USIC_CH_PCR_CTR21_Pos) /*!< USIC_CH PCR: CTR21 Mask */\r
-#define USIC_CH_PCR_CTR22_Pos 22 /*!< USIC_CH PCR: CTR22 Position */\r
-#define USIC_CH_PCR_CTR22_Msk (0x01UL << USIC_CH_PCR_CTR22_Pos) /*!< USIC_CH PCR: CTR22 Mask */\r
-#define USIC_CH_PCR_CTR23_Pos 23 /*!< USIC_CH PCR: CTR23 Position */\r
-#define USIC_CH_PCR_CTR23_Msk (0x01UL << USIC_CH_PCR_CTR23_Pos) /*!< USIC_CH PCR: CTR23 Mask */\r
-#define USIC_CH_PCR_CTR24_Pos 24 /*!< USIC_CH PCR: CTR24 Position */\r
-#define USIC_CH_PCR_CTR24_Msk (0x01UL << USIC_CH_PCR_CTR24_Pos) /*!< USIC_CH PCR: CTR24 Mask */\r
-#define USIC_CH_PCR_CTR25_Pos 25 /*!< USIC_CH PCR: CTR25 Position */\r
-#define USIC_CH_PCR_CTR25_Msk (0x01UL << USIC_CH_PCR_CTR25_Pos) /*!< USIC_CH PCR: CTR25 Mask */\r
-#define USIC_CH_PCR_CTR26_Pos 26 /*!< USIC_CH PCR: CTR26 Position */\r
-#define USIC_CH_PCR_CTR26_Msk (0x01UL << USIC_CH_PCR_CTR26_Pos) /*!< USIC_CH PCR: CTR26 Mask */\r
-#define USIC_CH_PCR_CTR27_Pos 27 /*!< USIC_CH PCR: CTR27 Position */\r
-#define USIC_CH_PCR_CTR27_Msk (0x01UL << USIC_CH_PCR_CTR27_Pos) /*!< USIC_CH PCR: CTR27 Mask */\r
-#define USIC_CH_PCR_CTR28_Pos 28 /*!< USIC_CH PCR: CTR28 Position */\r
-#define USIC_CH_PCR_CTR28_Msk (0x01UL << USIC_CH_PCR_CTR28_Pos) /*!< USIC_CH PCR: CTR28 Mask */\r
-#define USIC_CH_PCR_CTR29_Pos 29 /*!< USIC_CH PCR: CTR29 Position */\r
-#define USIC_CH_PCR_CTR29_Msk (0x01UL << USIC_CH_PCR_CTR29_Pos) /*!< USIC_CH PCR: CTR29 Mask */\r
-#define USIC_CH_PCR_CTR30_Pos 30 /*!< USIC_CH PCR: CTR30 Position */\r
-#define USIC_CH_PCR_CTR30_Msk (0x01UL << USIC_CH_PCR_CTR30_Pos) /*!< USIC_CH PCR: CTR30 Mask */\r
-#define USIC_CH_PCR_CTR31_Pos 31 /*!< USIC_CH PCR: CTR31 Position */\r
-#define USIC_CH_PCR_CTR31_Msk (0x01UL << USIC_CH_PCR_CTR31_Pos) /*!< USIC_CH PCR: CTR31 Mask */\r
-\r
-/* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */\r
-#define USIC_CH_PCR_ASCMode_SMD_Pos 0 /*!< USIC_CH PCR_ASCMode: SMD Position */\r
-#define USIC_CH_PCR_ASCMode_SMD_Msk (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos) /*!< USIC_CH PCR_ASCMode: SMD Mask */\r
-#define USIC_CH_PCR_ASCMode_STPB_Pos 1 /*!< USIC_CH PCR_ASCMode: STPB Position */\r
-#define USIC_CH_PCR_ASCMode_STPB_Msk (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos) /*!< USIC_CH PCR_ASCMode: STPB Mask */\r
-#define USIC_CH_PCR_ASCMode_IDM_Pos 2 /*!< USIC_CH PCR_ASCMode: IDM Position */\r
-#define USIC_CH_PCR_ASCMode_IDM_Msk (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos) /*!< USIC_CH PCR_ASCMode: IDM Mask */\r
-#define USIC_CH_PCR_ASCMode_SBIEN_Pos 3 /*!< USIC_CH PCR_ASCMode: SBIEN Position */\r
-#define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos) /*!< USIC_CH PCR_ASCMode: SBIEN Mask */\r
-#define USIC_CH_PCR_ASCMode_CDEN_Pos 4 /*!< USIC_CH PCR_ASCMode: CDEN Position */\r
-#define USIC_CH_PCR_ASCMode_CDEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos) /*!< USIC_CH PCR_ASCMode: CDEN Mask */\r
-#define USIC_CH_PCR_ASCMode_RNIEN_Pos 5 /*!< USIC_CH PCR_ASCMode: RNIEN Position */\r
-#define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos) /*!< USIC_CH PCR_ASCMode: RNIEN Mask */\r
-#define USIC_CH_PCR_ASCMode_FEIEN_Pos 6 /*!< USIC_CH PCR_ASCMode: FEIEN Position */\r
-#define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos) /*!< USIC_CH PCR_ASCMode: FEIEN Mask */\r
-#define USIC_CH_PCR_ASCMode_FFIEN_Pos 7 /*!< USIC_CH PCR_ASCMode: FFIEN Position */\r
-#define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos) /*!< USIC_CH PCR_ASCMode: FFIEN Mask */\r
-#define USIC_CH_PCR_ASCMode_SP_Pos 8 /*!< USIC_CH PCR_ASCMode: SP Position */\r
-#define USIC_CH_PCR_ASCMode_SP_Msk (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos) /*!< USIC_CH PCR_ASCMode: SP Mask */\r
-#define USIC_CH_PCR_ASCMode_PL_Pos 13 /*!< USIC_CH PCR_ASCMode: PL Position */\r
-#define USIC_CH_PCR_ASCMode_PL_Msk (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos) /*!< USIC_CH PCR_ASCMode: PL Mask */\r
-#define USIC_CH_PCR_ASCMode_RSTEN_Pos 16 /*!< USIC_CH PCR_ASCMode: RSTEN Position */\r
-#define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos) /*!< USIC_CH PCR_ASCMode: RSTEN Mask */\r
-#define USIC_CH_PCR_ASCMode_TSTEN_Pos 17 /*!< USIC_CH PCR_ASCMode: TSTEN Position */\r
-#define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos) /*!< USIC_CH PCR_ASCMode: TSTEN Mask */\r
-#define USIC_CH_PCR_ASCMode_MCLK_Pos 31 /*!< USIC_CH PCR_ASCMode: MCLK Position */\r
-#define USIC_CH_PCR_ASCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos) /*!< USIC_CH PCR_ASCMode: MCLK Mask */\r
-\r
-/* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */\r
-#define USIC_CH_PCR_SSCMode_MSLSEN_Pos 0 /*!< USIC_CH PCR_SSCMode: MSLSEN Position */\r
-#define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSEN Mask */\r
-#define USIC_CH_PCR_SSCMode_SELCTR_Pos 1 /*!< USIC_CH PCR_SSCMode: SELCTR Position */\r
-#define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos) /*!< USIC_CH PCR_SSCMode: SELCTR Mask */\r
-#define USIC_CH_PCR_SSCMode_SELINV_Pos 2 /*!< USIC_CH PCR_SSCMode: SELINV Position */\r
-#define USIC_CH_PCR_SSCMode_SELINV_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos) /*!< USIC_CH PCR_SSCMode: SELINV Mask */\r
-#define USIC_CH_PCR_SSCMode_FEM_Pos 3 /*!< USIC_CH PCR_SSCMode: FEM Position */\r
-#define USIC_CH_PCR_SSCMode_FEM_Msk (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos) /*!< USIC_CH PCR_SSCMode: FEM Mask */\r
-#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos 4 /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position */\r
-#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask */\r
-#define USIC_CH_PCR_SSCMode_PCTQ1_Pos 6 /*!< USIC_CH PCR_SSCMode: PCTQ1 Position */\r
-#define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask */\r
-#define USIC_CH_PCR_SSCMode_DCTQ1_Pos 8 /*!< USIC_CH PCR_SSCMode: DCTQ1 Position */\r
-#define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask */\r
-#define USIC_CH_PCR_SSCMode_PARIEN_Pos 13 /*!< USIC_CH PCR_SSCMode: PARIEN Position */\r
-#define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos) /*!< USIC_CH PCR_SSCMode: PARIEN Mask */\r
-#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos 14 /*!< USIC_CH PCR_SSCMode: MSLSIEN Position */\r
-#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask */\r
-#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_SSCMode: DX2TIEN Position */\r
-#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos) /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask */\r
-#define USIC_CH_PCR_SSCMode_SELO_Pos 16 /*!< USIC_CH PCR_SSCMode: SELO Position */\r
-#define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos) /*!< USIC_CH PCR_SSCMode: SELO Mask */\r
-#define USIC_CH_PCR_SSCMode_TIWEN_Pos 24 /*!< USIC_CH PCR_SSCMode: TIWEN Position */\r
-#define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos) /*!< USIC_CH PCR_SSCMode: TIWEN Mask */\r
-#define USIC_CH_PCR_SSCMode_MCLK_Pos 31 /*!< USIC_CH PCR_SSCMode: MCLK Position */\r
-#define USIC_CH_PCR_SSCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos) /*!< USIC_CH PCR_SSCMode: MCLK Mask */\r
-\r
-/* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */\r
-#define USIC_CH_PCR_IICMode_SLAD_Pos 0 /*!< USIC_CH PCR_IICMode: SLAD Position */\r
-#define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos) /*!< USIC_CH PCR_IICMode: SLAD Mask */\r
-#define USIC_CH_PCR_IICMode_ACK00_Pos 16 /*!< USIC_CH PCR_IICMode: ACK00 Position */\r
-#define USIC_CH_PCR_IICMode_ACK00_Msk (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos) /*!< USIC_CH PCR_IICMode: ACK00 Mask */\r
-#define USIC_CH_PCR_IICMode_STIM_Pos 17 /*!< USIC_CH PCR_IICMode: STIM Position */\r
-#define USIC_CH_PCR_IICMode_STIM_Msk (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos) /*!< USIC_CH PCR_IICMode: STIM Mask */\r
-#define USIC_CH_PCR_IICMode_SCRIEN_Pos 18 /*!< USIC_CH PCR_IICMode: SCRIEN Position */\r
-#define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos) /*!< USIC_CH PCR_IICMode: SCRIEN Mask */\r
-#define USIC_CH_PCR_IICMode_RSCRIEN_Pos 19 /*!< USIC_CH PCR_IICMode: RSCRIEN Position */\r
-#define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos) /*!< USIC_CH PCR_IICMode: RSCRIEN Mask */\r
-#define USIC_CH_PCR_IICMode_PCRIEN_Pos 20 /*!< USIC_CH PCR_IICMode: PCRIEN Position */\r
-#define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos) /*!< USIC_CH PCR_IICMode: PCRIEN Mask */\r
-#define USIC_CH_PCR_IICMode_NACKIEN_Pos 21 /*!< USIC_CH PCR_IICMode: NACKIEN Position */\r
-#define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos) /*!< USIC_CH PCR_IICMode: NACKIEN Mask */\r
-#define USIC_CH_PCR_IICMode_ARLIEN_Pos 22 /*!< USIC_CH PCR_IICMode: ARLIEN Position */\r
-#define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos) /*!< USIC_CH PCR_IICMode: ARLIEN Mask */\r
-#define USIC_CH_PCR_IICMode_SRRIEN_Pos 23 /*!< USIC_CH PCR_IICMode: SRRIEN Position */\r
-#define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos) /*!< USIC_CH PCR_IICMode: SRRIEN Mask */\r
-#define USIC_CH_PCR_IICMode_ERRIEN_Pos 24 /*!< USIC_CH PCR_IICMode: ERRIEN Position */\r
-#define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos) /*!< USIC_CH PCR_IICMode: ERRIEN Mask */\r
-#define USIC_CH_PCR_IICMode_SACKDIS_Pos 25 /*!< USIC_CH PCR_IICMode: SACKDIS Position */\r
-#define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos) /*!< USIC_CH PCR_IICMode: SACKDIS Mask */\r
-#define USIC_CH_PCR_IICMode_HDEL_Pos 26 /*!< USIC_CH PCR_IICMode: HDEL Position */\r
-#define USIC_CH_PCR_IICMode_HDEL_Msk (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos) /*!< USIC_CH PCR_IICMode: HDEL Mask */\r
-#define USIC_CH_PCR_IICMode_ACKIEN_Pos 30 /*!< USIC_CH PCR_IICMode: ACKIEN Position */\r
-#define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos) /*!< USIC_CH PCR_IICMode: ACKIEN Mask */\r
-#define USIC_CH_PCR_IICMode_MCLK_Pos 31 /*!< USIC_CH PCR_IICMode: MCLK Position */\r
-#define USIC_CH_PCR_IICMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos) /*!< USIC_CH PCR_IICMode: MCLK Mask */\r
-\r
-/* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */\r
-#define USIC_CH_PCR_IISMode_WAGEN_Pos 0 /*!< USIC_CH PCR_IISMode: WAGEN Position */\r
-#define USIC_CH_PCR_IISMode_WAGEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos) /*!< USIC_CH PCR_IISMode: WAGEN Mask */\r
-#define USIC_CH_PCR_IISMode_DTEN_Pos 1 /*!< USIC_CH PCR_IISMode: DTEN Position */\r
-#define USIC_CH_PCR_IISMode_DTEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos) /*!< USIC_CH PCR_IISMode: DTEN Mask */\r
-#define USIC_CH_PCR_IISMode_SELINV_Pos 2 /*!< USIC_CH PCR_IISMode: SELINV Position */\r
-#define USIC_CH_PCR_IISMode_SELINV_Msk (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos) /*!< USIC_CH PCR_IISMode: SELINV Mask */\r
-#define USIC_CH_PCR_IISMode_WAFEIEN_Pos 4 /*!< USIC_CH PCR_IISMode: WAFEIEN Position */\r
-#define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos) /*!< USIC_CH PCR_IISMode: WAFEIEN Mask */\r
-#define USIC_CH_PCR_IISMode_WAREIEN_Pos 5 /*!< USIC_CH PCR_IISMode: WAREIEN Position */\r
-#define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos) /*!< USIC_CH PCR_IISMode: WAREIEN Mask */\r
-#define USIC_CH_PCR_IISMode_ENDIEN_Pos 6 /*!< USIC_CH PCR_IISMode: ENDIEN Position */\r
-#define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos) /*!< USIC_CH PCR_IISMode: ENDIEN Mask */\r
-#define USIC_CH_PCR_IISMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_IISMode: DX2TIEN Position */\r
-#define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos) /*!< USIC_CH PCR_IISMode: DX2TIEN Mask */\r
-#define USIC_CH_PCR_IISMode_TDEL_Pos 16 /*!< USIC_CH PCR_IISMode: TDEL Position */\r
-#define USIC_CH_PCR_IISMode_TDEL_Msk (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos) /*!< USIC_CH PCR_IISMode: TDEL Mask */\r
-#define USIC_CH_PCR_IISMode_MCLK_Pos 31 /*!< USIC_CH PCR_IISMode: MCLK Position */\r
-#define USIC_CH_PCR_IISMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos) /*!< USIC_CH PCR_IISMode: MCLK Mask */\r
-\r
-/* --------------------------------- USIC_CH_CCR -------------------------------- */\r
-#define USIC_CH_CCR_MODE_Pos 0 /*!< USIC_CH CCR: MODE Position */\r
-#define USIC_CH_CCR_MODE_Msk (0x0fUL << USIC_CH_CCR_MODE_Pos) /*!< USIC_CH CCR: MODE Mask */\r
-#define USIC_CH_CCR_HPCEN_Pos 6 /*!< USIC_CH CCR: HPCEN Position */\r
-#define USIC_CH_CCR_HPCEN_Msk (0x03UL << USIC_CH_CCR_HPCEN_Pos) /*!< USIC_CH CCR: HPCEN Mask */\r
-#define USIC_CH_CCR_PM_Pos 8 /*!< USIC_CH CCR: PM Position */\r
-#define USIC_CH_CCR_PM_Msk (0x03UL << USIC_CH_CCR_PM_Pos) /*!< USIC_CH CCR: PM Mask */\r
-#define USIC_CH_CCR_RSIEN_Pos 10 /*!< USIC_CH CCR: RSIEN Position */\r
-#define USIC_CH_CCR_RSIEN_Msk (0x01UL << USIC_CH_CCR_RSIEN_Pos) /*!< USIC_CH CCR: RSIEN Mask */\r
-#define USIC_CH_CCR_DLIEN_Pos 11 /*!< USIC_CH CCR: DLIEN Position */\r
-#define USIC_CH_CCR_DLIEN_Msk (0x01UL << USIC_CH_CCR_DLIEN_Pos) /*!< USIC_CH CCR: DLIEN Mask */\r
-#define USIC_CH_CCR_TSIEN_Pos 12 /*!< USIC_CH CCR: TSIEN Position */\r
-#define USIC_CH_CCR_TSIEN_Msk (0x01UL << USIC_CH_CCR_TSIEN_Pos) /*!< USIC_CH CCR: TSIEN Mask */\r
-#define USIC_CH_CCR_TBIEN_Pos 13 /*!< USIC_CH CCR: TBIEN Position */\r
-#define USIC_CH_CCR_TBIEN_Msk (0x01UL << USIC_CH_CCR_TBIEN_Pos) /*!< USIC_CH CCR: TBIEN Mask */\r
-#define USIC_CH_CCR_RIEN_Pos 14 /*!< USIC_CH CCR: RIEN Position */\r
-#define USIC_CH_CCR_RIEN_Msk (0x01UL << USIC_CH_CCR_RIEN_Pos) /*!< USIC_CH CCR: RIEN Mask */\r
-#define USIC_CH_CCR_AIEN_Pos 15 /*!< USIC_CH CCR: AIEN Position */\r
-#define USIC_CH_CCR_AIEN_Msk (0x01UL << USIC_CH_CCR_AIEN_Pos) /*!< USIC_CH CCR: AIEN Mask */\r
-#define USIC_CH_CCR_BRGIEN_Pos 16 /*!< USIC_CH CCR: BRGIEN Position */\r
-#define USIC_CH_CCR_BRGIEN_Msk (0x01UL << USIC_CH_CCR_BRGIEN_Pos) /*!< USIC_CH CCR: BRGIEN Mask */\r
-\r
-/* -------------------------------- USIC_CH_CMTR -------------------------------- */\r
-#define USIC_CH_CMTR_CTV_Pos 0 /*!< USIC_CH CMTR: CTV Position */\r
-#define USIC_CH_CMTR_CTV_Msk (0x000003ffUL << USIC_CH_CMTR_CTV_Pos) /*!< USIC_CH CMTR: CTV Mask */\r
-\r
-/* --------------------------------- USIC_CH_PSR -------------------------------- */\r
-#define USIC_CH_PSR_ST0_Pos 0 /*!< USIC_CH PSR: ST0 Position */\r
-#define USIC_CH_PSR_ST0_Msk (0x01UL << USIC_CH_PSR_ST0_Pos) /*!< USIC_CH PSR: ST0 Mask */\r
-#define USIC_CH_PSR_ST1_Pos 1 /*!< USIC_CH PSR: ST1 Position */\r
-#define USIC_CH_PSR_ST1_Msk (0x01UL << USIC_CH_PSR_ST1_Pos) /*!< USIC_CH PSR: ST1 Mask */\r
-#define USIC_CH_PSR_ST2_Pos 2 /*!< USIC_CH PSR: ST2 Position */\r
-#define USIC_CH_PSR_ST2_Msk (0x01UL << USIC_CH_PSR_ST2_Pos) /*!< USIC_CH PSR: ST2 Mask */\r
-#define USIC_CH_PSR_ST3_Pos 3 /*!< USIC_CH PSR: ST3 Position */\r
-#define USIC_CH_PSR_ST3_Msk (0x01UL << USIC_CH_PSR_ST3_Pos) /*!< USIC_CH PSR: ST3 Mask */\r
-#define USIC_CH_PSR_ST4_Pos 4 /*!< USIC_CH PSR: ST4 Position */\r
-#define USIC_CH_PSR_ST4_Msk (0x01UL << USIC_CH_PSR_ST4_Pos) /*!< USIC_CH PSR: ST4 Mask */\r
-#define USIC_CH_PSR_ST5_Pos 5 /*!< USIC_CH PSR: ST5 Position */\r
-#define USIC_CH_PSR_ST5_Msk (0x01UL << USIC_CH_PSR_ST5_Pos) /*!< USIC_CH PSR: ST5 Mask */\r
-#define USIC_CH_PSR_ST6_Pos 6 /*!< USIC_CH PSR: ST6 Position */\r
-#define USIC_CH_PSR_ST6_Msk (0x01UL << USIC_CH_PSR_ST6_Pos) /*!< USIC_CH PSR: ST6 Mask */\r
-#define USIC_CH_PSR_ST7_Pos 7 /*!< USIC_CH PSR: ST7 Position */\r
-#define USIC_CH_PSR_ST7_Msk (0x01UL << USIC_CH_PSR_ST7_Pos) /*!< USIC_CH PSR: ST7 Mask */\r
-#define USIC_CH_PSR_ST8_Pos 8 /*!< USIC_CH PSR: ST8 Position */\r
-#define USIC_CH_PSR_ST8_Msk (0x01UL << USIC_CH_PSR_ST8_Pos) /*!< USIC_CH PSR: ST8 Mask */\r
-#define USIC_CH_PSR_ST9_Pos 9 /*!< USIC_CH PSR: ST9 Position */\r
-#define USIC_CH_PSR_ST9_Msk (0x01UL << USIC_CH_PSR_ST9_Pos) /*!< USIC_CH PSR: ST9 Mask */\r
-#define USIC_CH_PSR_RSIF_Pos 10 /*!< USIC_CH PSR: RSIF Position */\r
-#define USIC_CH_PSR_RSIF_Msk (0x01UL << USIC_CH_PSR_RSIF_Pos) /*!< USIC_CH PSR: RSIF Mask */\r
-#define USIC_CH_PSR_DLIF_Pos 11 /*!< USIC_CH PSR: DLIF Position */\r
-#define USIC_CH_PSR_DLIF_Msk (0x01UL << USIC_CH_PSR_DLIF_Pos) /*!< USIC_CH PSR: DLIF Mask */\r
-#define USIC_CH_PSR_TSIF_Pos 12 /*!< USIC_CH PSR: TSIF Position */\r
-#define USIC_CH_PSR_TSIF_Msk (0x01UL << USIC_CH_PSR_TSIF_Pos) /*!< USIC_CH PSR: TSIF Mask */\r
-#define USIC_CH_PSR_TBIF_Pos 13 /*!< USIC_CH PSR: TBIF Position */\r
-#define USIC_CH_PSR_TBIF_Msk (0x01UL << USIC_CH_PSR_TBIF_Pos) /*!< USIC_CH PSR: TBIF Mask */\r
-#define USIC_CH_PSR_RIF_Pos 14 /*!< USIC_CH PSR: RIF Position */\r
-#define USIC_CH_PSR_RIF_Msk (0x01UL << USIC_CH_PSR_RIF_Pos) /*!< USIC_CH PSR: RIF Mask */\r
-#define USIC_CH_PSR_AIF_Pos 15 /*!< USIC_CH PSR: AIF Position */\r
-#define USIC_CH_PSR_AIF_Msk (0x01UL << USIC_CH_PSR_AIF_Pos) /*!< USIC_CH PSR: AIF Mask */\r
-#define USIC_CH_PSR_BRGIF_Pos 16 /*!< USIC_CH PSR: BRGIF Position */\r
-#define USIC_CH_PSR_BRGIF_Msk (0x01UL << USIC_CH_PSR_BRGIF_Pos) /*!< USIC_CH PSR: BRGIF Mask */\r
-\r
-/* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */\r
-#define USIC_CH_PSR_ASCMode_TXIDLE_Pos 0 /*!< USIC_CH PSR_ASCMode: TXIDLE Position */\r
-#define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: TXIDLE Mask */\r
-#define USIC_CH_PSR_ASCMode_RXIDLE_Pos 1 /*!< USIC_CH PSR_ASCMode: RXIDLE Position */\r
-#define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: RXIDLE Mask */\r
-#define USIC_CH_PSR_ASCMode_SBD_Pos 2 /*!< USIC_CH PSR_ASCMode: SBD Position */\r
-#define USIC_CH_PSR_ASCMode_SBD_Msk (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos) /*!< USIC_CH PSR_ASCMode: SBD Mask */\r
-#define USIC_CH_PSR_ASCMode_COL_Pos 3 /*!< USIC_CH PSR_ASCMode: COL Position */\r
-#define USIC_CH_PSR_ASCMode_COL_Msk (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos) /*!< USIC_CH PSR_ASCMode: COL Mask */\r
-#define USIC_CH_PSR_ASCMode_RNS_Pos 4 /*!< USIC_CH PSR_ASCMode: RNS Position */\r
-#define USIC_CH_PSR_ASCMode_RNS_Msk (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos) /*!< USIC_CH PSR_ASCMode: RNS Mask */\r
-#define USIC_CH_PSR_ASCMode_FER0_Pos 5 /*!< USIC_CH PSR_ASCMode: FER0 Position */\r
-#define USIC_CH_PSR_ASCMode_FER0_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos) /*!< USIC_CH PSR_ASCMode: FER0 Mask */\r
-#define USIC_CH_PSR_ASCMode_FER1_Pos 6 /*!< USIC_CH PSR_ASCMode: FER1 Position */\r
-#define USIC_CH_PSR_ASCMode_FER1_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos) /*!< USIC_CH PSR_ASCMode: FER1 Mask */\r
-#define USIC_CH_PSR_ASCMode_RFF_Pos 7 /*!< USIC_CH PSR_ASCMode: RFF Position */\r
-#define USIC_CH_PSR_ASCMode_RFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos) /*!< USIC_CH PSR_ASCMode: RFF Mask */\r
-#define USIC_CH_PSR_ASCMode_TFF_Pos 8 /*!< USIC_CH PSR_ASCMode: TFF Position */\r
-#define USIC_CH_PSR_ASCMode_TFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos) /*!< USIC_CH PSR_ASCMode: TFF Mask */\r
-#define USIC_CH_PSR_ASCMode_BUSY_Pos 9 /*!< USIC_CH PSR_ASCMode: BUSY Position */\r
-#define USIC_CH_PSR_ASCMode_BUSY_Msk (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos) /*!< USIC_CH PSR_ASCMode: BUSY Mask */\r
-#define USIC_CH_PSR_ASCMode_RSIF_Pos 10 /*!< USIC_CH PSR_ASCMode: RSIF Position */\r
-#define USIC_CH_PSR_ASCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos) /*!< USIC_CH PSR_ASCMode: RSIF Mask */\r
-#define USIC_CH_PSR_ASCMode_DLIF_Pos 11 /*!< USIC_CH PSR_ASCMode: DLIF Position */\r
-#define USIC_CH_PSR_ASCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos) /*!< USIC_CH PSR_ASCMode: DLIF Mask */\r
-#define USIC_CH_PSR_ASCMode_TSIF_Pos 12 /*!< USIC_CH PSR_ASCMode: TSIF Position */\r
-#define USIC_CH_PSR_ASCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos) /*!< USIC_CH PSR_ASCMode: TSIF Mask */\r
-#define USIC_CH_PSR_ASCMode_TBIF_Pos 13 /*!< USIC_CH PSR_ASCMode: TBIF Position */\r
-#define USIC_CH_PSR_ASCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos) /*!< USIC_CH PSR_ASCMode: TBIF Mask */\r
-#define USIC_CH_PSR_ASCMode_RIF_Pos 14 /*!< USIC_CH PSR_ASCMode: RIF Position */\r
-#define USIC_CH_PSR_ASCMode_RIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos) /*!< USIC_CH PSR_ASCMode: RIF Mask */\r
-#define USIC_CH_PSR_ASCMode_AIF_Pos 15 /*!< USIC_CH PSR_ASCMode: AIF Position */\r
-#define USIC_CH_PSR_ASCMode_AIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos) /*!< USIC_CH PSR_ASCMode: AIF Mask */\r
-#define USIC_CH_PSR_ASCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_ASCMode: BRGIF Position */\r
-#define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos) /*!< USIC_CH PSR_ASCMode: BRGIF Mask */\r
-\r
-/* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */\r
-#define USIC_CH_PSR_SSCMode_MSLS_Pos 0 /*!< USIC_CH PSR_SSCMode: MSLS Position */\r
-#define USIC_CH_PSR_SSCMode_MSLS_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos) /*!< USIC_CH PSR_SSCMode: MSLS Mask */\r
-#define USIC_CH_PSR_SSCMode_DX2S_Pos 1 /*!< USIC_CH PSR_SSCMode: DX2S Position */\r
-#define USIC_CH_PSR_SSCMode_DX2S_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos) /*!< USIC_CH PSR_SSCMode: DX2S Mask */\r
-#define USIC_CH_PSR_SSCMode_MSLSEV_Pos 2 /*!< USIC_CH PSR_SSCMode: MSLSEV Position */\r
-#define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos) /*!< USIC_CH PSR_SSCMode: MSLSEV Mask */\r
-#define USIC_CH_PSR_SSCMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_SSCMode: DX2TEV Position */\r
-#define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos) /*!< USIC_CH PSR_SSCMode: DX2TEV Mask */\r
-#define USIC_CH_PSR_SSCMode_PARERR_Pos 4 /*!< USIC_CH PSR_SSCMode: PARERR Position */\r
-#define USIC_CH_PSR_SSCMode_PARERR_Msk (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos) /*!< USIC_CH PSR_SSCMode: PARERR Mask */\r
-#define USIC_CH_PSR_SSCMode_RSIF_Pos 10 /*!< USIC_CH PSR_SSCMode: RSIF Position */\r
-#define USIC_CH_PSR_SSCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos) /*!< USIC_CH PSR_SSCMode: RSIF Mask */\r
-#define USIC_CH_PSR_SSCMode_DLIF_Pos 11 /*!< USIC_CH PSR_SSCMode: DLIF Position */\r
-#define USIC_CH_PSR_SSCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos) /*!< USIC_CH PSR_SSCMode: DLIF Mask */\r
-#define USIC_CH_PSR_SSCMode_TSIF_Pos 12 /*!< USIC_CH PSR_SSCMode: TSIF Position */\r
-#define USIC_CH_PSR_SSCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos) /*!< USIC_CH PSR_SSCMode: TSIF Mask */\r
-#define USIC_CH_PSR_SSCMode_TBIF_Pos 13 /*!< USIC_CH PSR_SSCMode: TBIF Position */\r
-#define USIC_CH_PSR_SSCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos) /*!< USIC_CH PSR_SSCMode: TBIF Mask */\r
-#define USIC_CH_PSR_SSCMode_RIF_Pos 14 /*!< USIC_CH PSR_SSCMode: RIF Position */\r
-#define USIC_CH_PSR_SSCMode_RIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos) /*!< USIC_CH PSR_SSCMode: RIF Mask */\r
-#define USIC_CH_PSR_SSCMode_AIF_Pos 15 /*!< USIC_CH PSR_SSCMode: AIF Position */\r
-#define USIC_CH_PSR_SSCMode_AIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos) /*!< USIC_CH PSR_SSCMode: AIF Mask */\r
-#define USIC_CH_PSR_SSCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_SSCMode: BRGIF Position */\r
-#define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos) /*!< USIC_CH PSR_SSCMode: BRGIF Mask */\r
-\r
-/* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */\r
-#define USIC_CH_PSR_IICMode_SLSEL_Pos 0 /*!< USIC_CH PSR_IICMode: SLSEL Position */\r
-#define USIC_CH_PSR_IICMode_SLSEL_Msk (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos) /*!< USIC_CH PSR_IICMode: SLSEL Mask */\r
-#define USIC_CH_PSR_IICMode_WTDF_Pos 1 /*!< USIC_CH PSR_IICMode: WTDF Position */\r
-#define USIC_CH_PSR_IICMode_WTDF_Msk (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos) /*!< USIC_CH PSR_IICMode: WTDF Mask */\r
-#define USIC_CH_PSR_IICMode_SCR_Pos 2 /*!< USIC_CH PSR_IICMode: SCR Position */\r
-#define USIC_CH_PSR_IICMode_SCR_Msk (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos) /*!< USIC_CH PSR_IICMode: SCR Mask */\r
-#define USIC_CH_PSR_IICMode_RSCR_Pos 3 /*!< USIC_CH PSR_IICMode: RSCR Position */\r
-#define USIC_CH_PSR_IICMode_RSCR_Msk (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos) /*!< USIC_CH PSR_IICMode: RSCR Mask */\r
-#define USIC_CH_PSR_IICMode_PCR_Pos 4 /*!< USIC_CH PSR_IICMode: PCR Position */\r
-#define USIC_CH_PSR_IICMode_PCR_Msk (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos) /*!< USIC_CH PSR_IICMode: PCR Mask */\r
-#define USIC_CH_PSR_IICMode_NACK_Pos 5 /*!< USIC_CH PSR_IICMode: NACK Position */\r
-#define USIC_CH_PSR_IICMode_NACK_Msk (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos) /*!< USIC_CH PSR_IICMode: NACK Mask */\r
-#define USIC_CH_PSR_IICMode_ARL_Pos 6 /*!< USIC_CH PSR_IICMode: ARL Position */\r
-#define USIC_CH_PSR_IICMode_ARL_Msk (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos) /*!< USIC_CH PSR_IICMode: ARL Mask */\r
-#define USIC_CH_PSR_IICMode_SRR_Pos 7 /*!< USIC_CH PSR_IICMode: SRR Position */\r
-#define USIC_CH_PSR_IICMode_SRR_Msk (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos) /*!< USIC_CH PSR_IICMode: SRR Mask */\r
-#define USIC_CH_PSR_IICMode_ERR_Pos 8 /*!< USIC_CH PSR_IICMode: ERR Position */\r
-#define USIC_CH_PSR_IICMode_ERR_Msk (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos) /*!< USIC_CH PSR_IICMode: ERR Mask */\r
-#define USIC_CH_PSR_IICMode_ACK_Pos 9 /*!< USIC_CH PSR_IICMode: ACK Position */\r
-#define USIC_CH_PSR_IICMode_ACK_Msk (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos) /*!< USIC_CH PSR_IICMode: ACK Mask */\r
-#define USIC_CH_PSR_IICMode_RSIF_Pos 10 /*!< USIC_CH PSR_IICMode: RSIF Position */\r
-#define USIC_CH_PSR_IICMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos) /*!< USIC_CH PSR_IICMode: RSIF Mask */\r
-#define USIC_CH_PSR_IICMode_DLIF_Pos 11 /*!< USIC_CH PSR_IICMode: DLIF Position */\r
-#define USIC_CH_PSR_IICMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos) /*!< USIC_CH PSR_IICMode: DLIF Mask */\r
-#define USIC_CH_PSR_IICMode_TSIF_Pos 12 /*!< USIC_CH PSR_IICMode: TSIF Position */\r
-#define USIC_CH_PSR_IICMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos) /*!< USIC_CH PSR_IICMode: TSIF Mask */\r
-#define USIC_CH_PSR_IICMode_TBIF_Pos 13 /*!< USIC_CH PSR_IICMode: TBIF Position */\r
-#define USIC_CH_PSR_IICMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos) /*!< USIC_CH PSR_IICMode: TBIF Mask */\r
-#define USIC_CH_PSR_IICMode_RIF_Pos 14 /*!< USIC_CH PSR_IICMode: RIF Position */\r
-#define USIC_CH_PSR_IICMode_RIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos) /*!< USIC_CH PSR_IICMode: RIF Mask */\r
-#define USIC_CH_PSR_IICMode_AIF_Pos 15 /*!< USIC_CH PSR_IICMode: AIF Position */\r
-#define USIC_CH_PSR_IICMode_AIF_Msk (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos) /*!< USIC_CH PSR_IICMode: AIF Mask */\r
-#define USIC_CH_PSR_IICMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IICMode: BRGIF Position */\r
-#define USIC_CH_PSR_IICMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos) /*!< USIC_CH PSR_IICMode: BRGIF Mask */\r
-\r
-/* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */\r
-#define USIC_CH_PSR_IISMode_WA_Pos 0 /*!< USIC_CH PSR_IISMode: WA Position */\r
-#define USIC_CH_PSR_IISMode_WA_Msk (0x01UL << USIC_CH_PSR_IISMode_WA_Pos) /*!< USIC_CH PSR_IISMode: WA Mask */\r
-#define USIC_CH_PSR_IISMode_DX2S_Pos 1 /*!< USIC_CH PSR_IISMode: DX2S Position */\r
-#define USIC_CH_PSR_IISMode_DX2S_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos) /*!< USIC_CH PSR_IISMode: DX2S Mask */\r
-#define USIC_CH_PSR_IISMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_IISMode: DX2TEV Position */\r
-#define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos) /*!< USIC_CH PSR_IISMode: DX2TEV Mask */\r
-#define USIC_CH_PSR_IISMode_WAFE_Pos 4 /*!< USIC_CH PSR_IISMode: WAFE Position */\r
-#define USIC_CH_PSR_IISMode_WAFE_Msk (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos) /*!< USIC_CH PSR_IISMode: WAFE Mask */\r
-#define USIC_CH_PSR_IISMode_WARE_Pos 5 /*!< USIC_CH PSR_IISMode: WARE Position */\r
-#define USIC_CH_PSR_IISMode_WARE_Msk (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos) /*!< USIC_CH PSR_IISMode: WARE Mask */\r
-#define USIC_CH_PSR_IISMode_END_Pos 6 /*!< USIC_CH PSR_IISMode: END Position */\r
-#define USIC_CH_PSR_IISMode_END_Msk (0x01UL << USIC_CH_PSR_IISMode_END_Pos) /*!< USIC_CH PSR_IISMode: END Mask */\r
-#define USIC_CH_PSR_IISMode_RSIF_Pos 10 /*!< USIC_CH PSR_IISMode: RSIF Position */\r
-#define USIC_CH_PSR_IISMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos) /*!< USIC_CH PSR_IISMode: RSIF Mask */\r
-#define USIC_CH_PSR_IISMode_DLIF_Pos 11 /*!< USIC_CH PSR_IISMode: DLIF Position */\r
-#define USIC_CH_PSR_IISMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos) /*!< USIC_CH PSR_IISMode: DLIF Mask */\r
-#define USIC_CH_PSR_IISMode_TSIF_Pos 12 /*!< USIC_CH PSR_IISMode: TSIF Position */\r
-#define USIC_CH_PSR_IISMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos) /*!< USIC_CH PSR_IISMode: TSIF Mask */\r
-#define USIC_CH_PSR_IISMode_TBIF_Pos 13 /*!< USIC_CH PSR_IISMode: TBIF Position */\r
-#define USIC_CH_PSR_IISMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos) /*!< USIC_CH PSR_IISMode: TBIF Mask */\r
-#define USIC_CH_PSR_IISMode_RIF_Pos 14 /*!< USIC_CH PSR_IISMode: RIF Position */\r
-#define USIC_CH_PSR_IISMode_RIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos) /*!< USIC_CH PSR_IISMode: RIF Mask */\r
-#define USIC_CH_PSR_IISMode_AIF_Pos 15 /*!< USIC_CH PSR_IISMode: AIF Position */\r
-#define USIC_CH_PSR_IISMode_AIF_Msk (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos) /*!< USIC_CH PSR_IISMode: AIF Mask */\r
-#define USIC_CH_PSR_IISMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IISMode: BRGIF Position */\r
-#define USIC_CH_PSR_IISMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos) /*!< USIC_CH PSR_IISMode: BRGIF Mask */\r
-\r
-/* -------------------------------- USIC_CH_PSCR -------------------------------- */\r
-#define USIC_CH_PSCR_CST0_Pos 0 /*!< USIC_CH PSCR: CST0 Position */\r
-#define USIC_CH_PSCR_CST0_Msk (0x01UL << USIC_CH_PSCR_CST0_Pos) /*!< USIC_CH PSCR: CST0 Mask */\r
-#define USIC_CH_PSCR_CST1_Pos 1 /*!< USIC_CH PSCR: CST1 Position */\r
-#define USIC_CH_PSCR_CST1_Msk (0x01UL << USIC_CH_PSCR_CST1_Pos) /*!< USIC_CH PSCR: CST1 Mask */\r
-#define USIC_CH_PSCR_CST2_Pos 2 /*!< USIC_CH PSCR: CST2 Position */\r
-#define USIC_CH_PSCR_CST2_Msk (0x01UL << USIC_CH_PSCR_CST2_Pos) /*!< USIC_CH PSCR: CST2 Mask */\r
-#define USIC_CH_PSCR_CST3_Pos 3 /*!< USIC_CH PSCR: CST3 Position */\r
-#define USIC_CH_PSCR_CST3_Msk (0x01UL << USIC_CH_PSCR_CST3_Pos) /*!< USIC_CH PSCR: CST3 Mask */\r
-#define USIC_CH_PSCR_CST4_Pos 4 /*!< USIC_CH PSCR: CST4 Position */\r
-#define USIC_CH_PSCR_CST4_Msk (0x01UL << USIC_CH_PSCR_CST4_Pos) /*!< USIC_CH PSCR: CST4 Mask */\r
-#define USIC_CH_PSCR_CST5_Pos 5 /*!< USIC_CH PSCR: CST5 Position */\r
-#define USIC_CH_PSCR_CST5_Msk (0x01UL << USIC_CH_PSCR_CST5_Pos) /*!< USIC_CH PSCR: CST5 Mask */\r
-#define USIC_CH_PSCR_CST6_Pos 6 /*!< USIC_CH PSCR: CST6 Position */\r
-#define USIC_CH_PSCR_CST6_Msk (0x01UL << USIC_CH_PSCR_CST6_Pos) /*!< USIC_CH PSCR: CST6 Mask */\r
-#define USIC_CH_PSCR_CST7_Pos 7 /*!< USIC_CH PSCR: CST7 Position */\r
-#define USIC_CH_PSCR_CST7_Msk (0x01UL << USIC_CH_PSCR_CST7_Pos) /*!< USIC_CH PSCR: CST7 Mask */\r
-#define USIC_CH_PSCR_CST8_Pos 8 /*!< USIC_CH PSCR: CST8 Position */\r
-#define USIC_CH_PSCR_CST8_Msk (0x01UL << USIC_CH_PSCR_CST8_Pos) /*!< USIC_CH PSCR: CST8 Mask */\r
-#define USIC_CH_PSCR_CST9_Pos 9 /*!< USIC_CH PSCR: CST9 Position */\r
-#define USIC_CH_PSCR_CST9_Msk (0x01UL << USIC_CH_PSCR_CST9_Pos) /*!< USIC_CH PSCR: CST9 Mask */\r
-#define USIC_CH_PSCR_CRSIF_Pos 10 /*!< USIC_CH PSCR: CRSIF Position */\r
-#define USIC_CH_PSCR_CRSIF_Msk (0x01UL << USIC_CH_PSCR_CRSIF_Pos) /*!< USIC_CH PSCR: CRSIF Mask */\r
-#define USIC_CH_PSCR_CDLIF_Pos 11 /*!< USIC_CH PSCR: CDLIF Position */\r
-#define USIC_CH_PSCR_CDLIF_Msk (0x01UL << USIC_CH_PSCR_CDLIF_Pos) /*!< USIC_CH PSCR: CDLIF Mask */\r
-#define USIC_CH_PSCR_CTSIF_Pos 12 /*!< USIC_CH PSCR: CTSIF Position */\r
-#define USIC_CH_PSCR_CTSIF_Msk (0x01UL << USIC_CH_PSCR_CTSIF_Pos) /*!< USIC_CH PSCR: CTSIF Mask */\r
-#define USIC_CH_PSCR_CTBIF_Pos 13 /*!< USIC_CH PSCR: CTBIF Position */\r
-#define USIC_CH_PSCR_CTBIF_Msk (0x01UL << USIC_CH_PSCR_CTBIF_Pos) /*!< USIC_CH PSCR: CTBIF Mask */\r
-#define USIC_CH_PSCR_CRIF_Pos 14 /*!< USIC_CH PSCR: CRIF Position */\r
-#define USIC_CH_PSCR_CRIF_Msk (0x01UL << USIC_CH_PSCR_CRIF_Pos) /*!< USIC_CH PSCR: CRIF Mask */\r
-#define USIC_CH_PSCR_CAIF_Pos 15 /*!< USIC_CH PSCR: CAIF Position */\r
-#define USIC_CH_PSCR_CAIF_Msk (0x01UL << USIC_CH_PSCR_CAIF_Pos) /*!< USIC_CH PSCR: CAIF Mask */\r
-#define USIC_CH_PSCR_CBRGIF_Pos 16 /*!< USIC_CH PSCR: CBRGIF Position */\r
-#define USIC_CH_PSCR_CBRGIF_Msk (0x01UL << USIC_CH_PSCR_CBRGIF_Pos) /*!< USIC_CH PSCR: CBRGIF Mask */\r
-\r
-/* ------------------------------- USIC_CH_RBUFSR ------------------------------- */\r
-#define USIC_CH_RBUFSR_WLEN_Pos 0 /*!< USIC_CH RBUFSR: WLEN Position */\r
-#define USIC_CH_RBUFSR_WLEN_Msk (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos) /*!< USIC_CH RBUFSR: WLEN Mask */\r
-#define USIC_CH_RBUFSR_SOF_Pos 6 /*!< USIC_CH RBUFSR: SOF Position */\r
-#define USIC_CH_RBUFSR_SOF_Msk (0x01UL << USIC_CH_RBUFSR_SOF_Pos) /*!< USIC_CH RBUFSR: SOF Mask */\r
-#define USIC_CH_RBUFSR_PAR_Pos 8 /*!< USIC_CH RBUFSR: PAR Position */\r
-#define USIC_CH_RBUFSR_PAR_Msk (0x01UL << USIC_CH_RBUFSR_PAR_Pos) /*!< USIC_CH RBUFSR: PAR Mask */\r
-#define USIC_CH_RBUFSR_PERR_Pos 9 /*!< USIC_CH RBUFSR: PERR Position */\r
-#define USIC_CH_RBUFSR_PERR_Msk (0x01UL << USIC_CH_RBUFSR_PERR_Pos) /*!< USIC_CH RBUFSR: PERR Mask */\r
-#define USIC_CH_RBUFSR_RDV0_Pos 13 /*!< USIC_CH RBUFSR: RDV0 Position */\r
-#define USIC_CH_RBUFSR_RDV0_Msk (0x01UL << USIC_CH_RBUFSR_RDV0_Pos) /*!< USIC_CH RBUFSR: RDV0 Mask */\r
-#define USIC_CH_RBUFSR_RDV1_Pos 14 /*!< USIC_CH RBUFSR: RDV1 Position */\r
-#define USIC_CH_RBUFSR_RDV1_Msk (0x01UL << USIC_CH_RBUFSR_RDV1_Pos) /*!< USIC_CH RBUFSR: RDV1 Mask */\r
-#define USIC_CH_RBUFSR_DS_Pos 15 /*!< USIC_CH RBUFSR: DS Position */\r
-#define USIC_CH_RBUFSR_DS_Msk (0x01UL << USIC_CH_RBUFSR_DS_Pos) /*!< USIC_CH RBUFSR: DS Mask */\r
-\r
-/* -------------------------------- USIC_CH_RBUF -------------------------------- */\r
-#define USIC_CH_RBUF_DSR_Pos 0 /*!< USIC_CH RBUF: DSR Position */\r
-#define USIC_CH_RBUF_DSR_Msk (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos) /*!< USIC_CH RBUF: DSR Mask */\r
-\r
-/* -------------------------------- USIC_CH_RBUFD ------------------------------- */\r
-#define USIC_CH_RBUFD_DSR_Pos 0 /*!< USIC_CH RBUFD: DSR Position */\r
-#define USIC_CH_RBUFD_DSR_Msk (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos) /*!< USIC_CH RBUFD: DSR Mask */\r
-\r
-/* -------------------------------- USIC_CH_RBUF0 ------------------------------- */\r
-#define USIC_CH_RBUF0_DSR0_Pos 0 /*!< USIC_CH RBUF0: DSR0 Position */\r
-#define USIC_CH_RBUF0_DSR0_Msk (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos) /*!< USIC_CH RBUF0: DSR0 Mask */\r
-\r
-/* -------------------------------- USIC_CH_RBUF1 ------------------------------- */\r
-#define USIC_CH_RBUF1_DSR1_Pos 0 /*!< USIC_CH RBUF1: DSR1 Position */\r
-#define USIC_CH_RBUF1_DSR1_Msk (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos) /*!< USIC_CH RBUF1: DSR1 Mask */\r
-\r
-/* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */\r
-#define USIC_CH_RBUF01SR_WLEN0_Pos 0 /*!< USIC_CH RBUF01SR: WLEN0 Position */\r
-#define USIC_CH_RBUF01SR_WLEN0_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos) /*!< USIC_CH RBUF01SR: WLEN0 Mask */\r
-#define USIC_CH_RBUF01SR_SOF0_Pos 6 /*!< USIC_CH RBUF01SR: SOF0 Position */\r
-#define USIC_CH_RBUF01SR_SOF0_Msk (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos) /*!< USIC_CH RBUF01SR: SOF0 Mask */\r
-#define USIC_CH_RBUF01SR_PAR0_Pos 8 /*!< USIC_CH RBUF01SR: PAR0 Position */\r
-#define USIC_CH_RBUF01SR_PAR0_Msk (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos) /*!< USIC_CH RBUF01SR: PAR0 Mask */\r
-#define USIC_CH_RBUF01SR_PERR0_Pos 9 /*!< USIC_CH RBUF01SR: PERR0 Position */\r
-#define USIC_CH_RBUF01SR_PERR0_Msk (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos) /*!< USIC_CH RBUF01SR: PERR0 Mask */\r
-#define USIC_CH_RBUF01SR_RDV00_Pos 13 /*!< USIC_CH RBUF01SR: RDV00 Position */\r
-#define USIC_CH_RBUF01SR_RDV00_Msk (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos) /*!< USIC_CH RBUF01SR: RDV00 Mask */\r
-#define USIC_CH_RBUF01SR_RDV01_Pos 14 /*!< USIC_CH RBUF01SR: RDV01 Position */\r
-#define USIC_CH_RBUF01SR_RDV01_Msk (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos) /*!< USIC_CH RBUF01SR: RDV01 Mask */\r
-#define USIC_CH_RBUF01SR_DS0_Pos 15 /*!< USIC_CH RBUF01SR: DS0 Position */\r
-#define USIC_CH_RBUF01SR_DS0_Msk (0x01UL << USIC_CH_RBUF01SR_DS0_Pos) /*!< USIC_CH RBUF01SR: DS0 Mask */\r
-#define USIC_CH_RBUF01SR_WLEN1_Pos 16 /*!< USIC_CH RBUF01SR: WLEN1 Position */\r
-#define USIC_CH_RBUF01SR_WLEN1_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos) /*!< USIC_CH RBUF01SR: WLEN1 Mask */\r
-#define USIC_CH_RBUF01SR_SOF1_Pos 22 /*!< USIC_CH RBUF01SR: SOF1 Position */\r
-#define USIC_CH_RBUF01SR_SOF1_Msk (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos) /*!< USIC_CH RBUF01SR: SOF1 Mask */\r
-#define USIC_CH_RBUF01SR_PAR1_Pos 24 /*!< USIC_CH RBUF01SR: PAR1 Position */\r
-#define USIC_CH_RBUF01SR_PAR1_Msk (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos) /*!< USIC_CH RBUF01SR: PAR1 Mask */\r
-#define USIC_CH_RBUF01SR_PERR1_Pos 25 /*!< USIC_CH RBUF01SR: PERR1 Position */\r
-#define USIC_CH_RBUF01SR_PERR1_Msk (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos) /*!< USIC_CH RBUF01SR: PERR1 Mask */\r
-#define USIC_CH_RBUF01SR_RDV10_Pos 29 /*!< USIC_CH RBUF01SR: RDV10 Position */\r
-#define USIC_CH_RBUF01SR_RDV10_Msk (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos) /*!< USIC_CH RBUF01SR: RDV10 Mask */\r
-#define USIC_CH_RBUF01SR_RDV11_Pos 30 /*!< USIC_CH RBUF01SR: RDV11 Position */\r
-#define USIC_CH_RBUF01SR_RDV11_Msk (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos) /*!< USIC_CH RBUF01SR: RDV11 Mask */\r
-#define USIC_CH_RBUF01SR_DS1_Pos 31 /*!< USIC_CH RBUF01SR: DS1 Position */\r
-#define USIC_CH_RBUF01SR_DS1_Msk (0x01UL << USIC_CH_RBUF01SR_DS1_Pos) /*!< USIC_CH RBUF01SR: DS1 Mask */\r
-\r
-/* --------------------------------- USIC_CH_FMR -------------------------------- */\r
-#define USIC_CH_FMR_MTDV_Pos 0 /*!< USIC_CH FMR: MTDV Position */\r
-#define USIC_CH_FMR_MTDV_Msk (0x03UL << USIC_CH_FMR_MTDV_Pos) /*!< USIC_CH FMR: MTDV Mask */\r
-#define USIC_CH_FMR_ATVC_Pos 4 /*!< USIC_CH FMR: ATVC Position */\r
-#define USIC_CH_FMR_ATVC_Msk (0x01UL << USIC_CH_FMR_ATVC_Pos) /*!< USIC_CH FMR: ATVC Mask */\r
-#define USIC_CH_FMR_CRDV0_Pos 14 /*!< USIC_CH FMR: CRDV0 Position */\r
-#define USIC_CH_FMR_CRDV0_Msk (0x01UL << USIC_CH_FMR_CRDV0_Pos) /*!< USIC_CH FMR: CRDV0 Mask */\r
-#define USIC_CH_FMR_CRDV1_Pos 15 /*!< USIC_CH FMR: CRDV1 Position */\r
-#define USIC_CH_FMR_CRDV1_Msk (0x01UL << USIC_CH_FMR_CRDV1_Pos) /*!< USIC_CH FMR: CRDV1 Mask */\r
-#define USIC_CH_FMR_SIO0_Pos 16 /*!< USIC_CH FMR: SIO0 Position */\r
-#define USIC_CH_FMR_SIO0_Msk (0x01UL << USIC_CH_FMR_SIO0_Pos) /*!< USIC_CH FMR: SIO0 Mask */\r
-#define USIC_CH_FMR_SIO1_Pos 17 /*!< USIC_CH FMR: SIO1 Position */\r
-#define USIC_CH_FMR_SIO1_Msk (0x01UL << USIC_CH_FMR_SIO1_Pos) /*!< USIC_CH FMR: SIO1 Mask */\r
-#define USIC_CH_FMR_SIO2_Pos 18 /*!< USIC_CH FMR: SIO2 Position */\r
-#define USIC_CH_FMR_SIO2_Msk (0x01UL << USIC_CH_FMR_SIO2_Pos) /*!< USIC_CH FMR: SIO2 Mask */\r
-#define USIC_CH_FMR_SIO3_Pos 19 /*!< USIC_CH FMR: SIO3 Position */\r
-#define USIC_CH_FMR_SIO3_Msk (0x01UL << USIC_CH_FMR_SIO3_Pos) /*!< USIC_CH FMR: SIO3 Mask */\r
-#define USIC_CH_FMR_SIO4_Pos 20 /*!< USIC_CH FMR: SIO4 Position */\r
-#define USIC_CH_FMR_SIO4_Msk (0x01UL << USIC_CH_FMR_SIO4_Pos) /*!< USIC_CH FMR: SIO4 Mask */\r
-#define USIC_CH_FMR_SIO5_Pos 21 /*!< USIC_CH FMR: SIO5 Position */\r
-#define USIC_CH_FMR_SIO5_Msk (0x01UL << USIC_CH_FMR_SIO5_Pos) /*!< USIC_CH FMR: SIO5 Mask */\r
-\r
-/* -------------------------------- USIC_CH_TBUF -------------------------------- */\r
-#define USIC_CH_TBUF_TDATA_Pos 0 /*!< USIC_CH TBUF: TDATA Position */\r
-#define USIC_CH_TBUF_TDATA_Msk (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos) /*!< USIC_CH TBUF: TDATA Mask */\r
-\r
-/* --------------------------------- USIC_CH_BYP -------------------------------- */\r
-#define USIC_CH_BYP_BDATA_Pos 0 /*!< USIC_CH BYP: BDATA Position */\r
-#define USIC_CH_BYP_BDATA_Msk (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos) /*!< USIC_CH BYP: BDATA Mask */\r
-\r
-/* -------------------------------- USIC_CH_BYPCR ------------------------------- */\r
-#define USIC_CH_BYPCR_BWLE_Pos 0 /*!< USIC_CH BYPCR: BWLE Position */\r
-#define USIC_CH_BYPCR_BWLE_Msk (0x0fUL << USIC_CH_BYPCR_BWLE_Pos) /*!< USIC_CH BYPCR: BWLE Mask */\r
-#define USIC_CH_BYPCR_BDSSM_Pos 8 /*!< USIC_CH BYPCR: BDSSM Position */\r
-#define USIC_CH_BYPCR_BDSSM_Msk (0x01UL << USIC_CH_BYPCR_BDSSM_Pos) /*!< USIC_CH BYPCR: BDSSM Mask */\r
-#define USIC_CH_BYPCR_BDEN_Pos 10 /*!< USIC_CH BYPCR: BDEN Position */\r
-#define USIC_CH_BYPCR_BDEN_Msk (0x03UL << USIC_CH_BYPCR_BDEN_Pos) /*!< USIC_CH BYPCR: BDEN Mask */\r
-#define USIC_CH_BYPCR_BDVTR_Pos 12 /*!< USIC_CH BYPCR: BDVTR Position */\r
-#define USIC_CH_BYPCR_BDVTR_Msk (0x01UL << USIC_CH_BYPCR_BDVTR_Pos) /*!< USIC_CH BYPCR: BDVTR Mask */\r
-#define USIC_CH_BYPCR_BPRIO_Pos 13 /*!< USIC_CH BYPCR: BPRIO Position */\r
-#define USIC_CH_BYPCR_BPRIO_Msk (0x01UL << USIC_CH_BYPCR_BPRIO_Pos) /*!< USIC_CH BYPCR: BPRIO Mask */\r
-#define USIC_CH_BYPCR_BDV_Pos 15 /*!< USIC_CH BYPCR: BDV Position */\r
-#define USIC_CH_BYPCR_BDV_Msk (0x01UL << USIC_CH_BYPCR_BDV_Pos) /*!< USIC_CH BYPCR: BDV Mask */\r
-#define USIC_CH_BYPCR_BSELO_Pos 16 /*!< USIC_CH BYPCR: BSELO Position */\r
-#define USIC_CH_BYPCR_BSELO_Msk (0x1fUL << USIC_CH_BYPCR_BSELO_Pos) /*!< USIC_CH BYPCR: BSELO Mask */\r
-#define USIC_CH_BYPCR_BHPC_Pos 21 /*!< USIC_CH BYPCR: BHPC Position */\r
-#define USIC_CH_BYPCR_BHPC_Msk (0x07UL << USIC_CH_BYPCR_BHPC_Pos) /*!< USIC_CH BYPCR: BHPC Mask */\r
-\r
-/* -------------------------------- USIC_CH_TBCTR ------------------------------- */\r
-#define USIC_CH_TBCTR_DPTR_Pos 0 /*!< USIC_CH TBCTR: DPTR Position */\r
-#define USIC_CH_TBCTR_DPTR_Msk (0x3fUL << USIC_CH_TBCTR_DPTR_Pos) /*!< USIC_CH TBCTR: DPTR Mask */\r
-#define USIC_CH_TBCTR_LIMIT_Pos 8 /*!< USIC_CH TBCTR: LIMIT Position */\r
-#define USIC_CH_TBCTR_LIMIT_Msk (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos) /*!< USIC_CH TBCTR: LIMIT Mask */\r
-#define USIC_CH_TBCTR_STBTM_Pos 14 /*!< USIC_CH TBCTR: STBTM Position */\r
-#define USIC_CH_TBCTR_STBTM_Msk (0x01UL << USIC_CH_TBCTR_STBTM_Pos) /*!< USIC_CH TBCTR: STBTM Mask */\r
-#define USIC_CH_TBCTR_STBTEN_Pos 15 /*!< USIC_CH TBCTR: STBTEN Position */\r
-#define USIC_CH_TBCTR_STBTEN_Msk (0x01UL << USIC_CH_TBCTR_STBTEN_Pos) /*!< USIC_CH TBCTR: STBTEN Mask */\r
-#define USIC_CH_TBCTR_STBINP_Pos 16 /*!< USIC_CH TBCTR: STBINP Position */\r
-#define USIC_CH_TBCTR_STBINP_Msk (0x07UL << USIC_CH_TBCTR_STBINP_Pos) /*!< USIC_CH TBCTR: STBINP Mask */\r
-#define USIC_CH_TBCTR_ATBINP_Pos 19 /*!< USIC_CH TBCTR: ATBINP Position */\r
-#define USIC_CH_TBCTR_ATBINP_Msk (0x07UL << USIC_CH_TBCTR_ATBINP_Pos) /*!< USIC_CH TBCTR: ATBINP Mask */\r
-#define USIC_CH_TBCTR_SIZE_Pos 24 /*!< USIC_CH TBCTR: SIZE Position */\r
-#define USIC_CH_TBCTR_SIZE_Msk (0x07UL << USIC_CH_TBCTR_SIZE_Pos) /*!< USIC_CH TBCTR: SIZE Mask */\r
-#define USIC_CH_TBCTR_LOF_Pos 28 /*!< USIC_CH TBCTR: LOF Position */\r
-#define USIC_CH_TBCTR_LOF_Msk (0x01UL << USIC_CH_TBCTR_LOF_Pos) /*!< USIC_CH TBCTR: LOF Mask */\r
-#define USIC_CH_TBCTR_STBIEN_Pos 30 /*!< USIC_CH TBCTR: STBIEN Position */\r
-#define USIC_CH_TBCTR_STBIEN_Msk (0x01UL << USIC_CH_TBCTR_STBIEN_Pos) /*!< USIC_CH TBCTR: STBIEN Mask */\r
-#define USIC_CH_TBCTR_TBERIEN_Pos 31 /*!< USIC_CH TBCTR: TBERIEN Position */\r
-#define USIC_CH_TBCTR_TBERIEN_Msk (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos) /*!< USIC_CH TBCTR: TBERIEN Mask */\r
-\r
-/* -------------------------------- USIC_CH_RBCTR ------------------------------- */\r
-#define USIC_CH_RBCTR_DPTR_Pos 0 /*!< USIC_CH RBCTR: DPTR Position */\r
-#define USIC_CH_RBCTR_DPTR_Msk (0x3fUL << USIC_CH_RBCTR_DPTR_Pos) /*!< USIC_CH RBCTR: DPTR Mask */\r
-#define USIC_CH_RBCTR_LIMIT_Pos 8 /*!< USIC_CH RBCTR: LIMIT Position */\r
-#define USIC_CH_RBCTR_LIMIT_Msk (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos) /*!< USIC_CH RBCTR: LIMIT Mask */\r
-#define USIC_CH_RBCTR_SRBTM_Pos 14 /*!< USIC_CH RBCTR: SRBTM Position */\r
-#define USIC_CH_RBCTR_SRBTM_Msk (0x01UL << USIC_CH_RBCTR_SRBTM_Pos) /*!< USIC_CH RBCTR: SRBTM Mask */\r
-#define USIC_CH_RBCTR_SRBTEN_Pos 15 /*!< USIC_CH RBCTR: SRBTEN Position */\r
-#define USIC_CH_RBCTR_SRBTEN_Msk (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos) /*!< USIC_CH RBCTR: SRBTEN Mask */\r
-#define USIC_CH_RBCTR_SRBINP_Pos 16 /*!< USIC_CH RBCTR: SRBINP Position */\r
-#define USIC_CH_RBCTR_SRBINP_Msk (0x07UL << USIC_CH_RBCTR_SRBINP_Pos) /*!< USIC_CH RBCTR: SRBINP Mask */\r
-#define USIC_CH_RBCTR_ARBINP_Pos 19 /*!< USIC_CH RBCTR: ARBINP Position */\r
-#define USIC_CH_RBCTR_ARBINP_Msk (0x07UL << USIC_CH_RBCTR_ARBINP_Pos) /*!< USIC_CH RBCTR: ARBINP Mask */\r
-#define USIC_CH_RBCTR_RCIM_Pos 22 /*!< USIC_CH RBCTR: RCIM Position */\r
-#define USIC_CH_RBCTR_RCIM_Msk (0x03UL << USIC_CH_RBCTR_RCIM_Pos) /*!< USIC_CH RBCTR: RCIM Mask */\r
-#define USIC_CH_RBCTR_SIZE_Pos 24 /*!< USIC_CH RBCTR: SIZE Position */\r
-#define USIC_CH_RBCTR_SIZE_Msk (0x07UL << USIC_CH_RBCTR_SIZE_Pos) /*!< USIC_CH RBCTR: SIZE Mask */\r
-#define USIC_CH_RBCTR_RNM_Pos 27 /*!< USIC_CH RBCTR: RNM Position */\r
-#define USIC_CH_RBCTR_RNM_Msk (0x01UL << USIC_CH_RBCTR_RNM_Pos) /*!< USIC_CH RBCTR: RNM Mask */\r
-#define USIC_CH_RBCTR_LOF_Pos 28 /*!< USIC_CH RBCTR: LOF Position */\r
-#define USIC_CH_RBCTR_LOF_Msk (0x01UL << USIC_CH_RBCTR_LOF_Pos) /*!< USIC_CH RBCTR: LOF Mask */\r
-#define USIC_CH_RBCTR_ARBIEN_Pos 29 /*!< USIC_CH RBCTR: ARBIEN Position */\r
-#define USIC_CH_RBCTR_ARBIEN_Msk (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos) /*!< USIC_CH RBCTR: ARBIEN Mask */\r
-#define USIC_CH_RBCTR_SRBIEN_Pos 30 /*!< USIC_CH RBCTR: SRBIEN Position */\r
-#define USIC_CH_RBCTR_SRBIEN_Msk (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos) /*!< USIC_CH RBCTR: SRBIEN Mask */\r
-#define USIC_CH_RBCTR_RBERIEN_Pos 31 /*!< USIC_CH RBCTR: RBERIEN Position */\r
-#define USIC_CH_RBCTR_RBERIEN_Msk (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos) /*!< USIC_CH RBCTR: RBERIEN Mask */\r
-\r
-/* ------------------------------- USIC_CH_TRBPTR ------------------------------- */\r
-#define USIC_CH_TRBPTR_TDIPTR_Pos 0 /*!< USIC_CH TRBPTR: TDIPTR Position */\r
-#define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos) /*!< USIC_CH TRBPTR: TDIPTR Mask */\r
-#define USIC_CH_TRBPTR_TDOPTR_Pos 8 /*!< USIC_CH TRBPTR: TDOPTR Position */\r
-#define USIC_CH_TRBPTR_TDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos) /*!< USIC_CH TRBPTR: TDOPTR Mask */\r
-#define USIC_CH_TRBPTR_RDIPTR_Pos 16 /*!< USIC_CH TRBPTR: RDIPTR Position */\r
-#define USIC_CH_TRBPTR_RDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos) /*!< USIC_CH TRBPTR: RDIPTR Mask */\r
-#define USIC_CH_TRBPTR_RDOPTR_Pos 24 /*!< USIC_CH TRBPTR: RDOPTR Position */\r
-#define USIC_CH_TRBPTR_RDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos) /*!< USIC_CH TRBPTR: RDOPTR Mask */\r
-\r
-/* -------------------------------- USIC_CH_TRBSR ------------------------------- */\r
-#define USIC_CH_TRBSR_SRBI_Pos 0 /*!< USIC_CH TRBSR: SRBI Position */\r
-#define USIC_CH_TRBSR_SRBI_Msk (0x01UL << USIC_CH_TRBSR_SRBI_Pos) /*!< USIC_CH TRBSR: SRBI Mask */\r
-#define USIC_CH_TRBSR_RBERI_Pos 1 /*!< USIC_CH TRBSR: RBERI Position */\r
-#define USIC_CH_TRBSR_RBERI_Msk (0x01UL << USIC_CH_TRBSR_RBERI_Pos) /*!< USIC_CH TRBSR: RBERI Mask */\r
-#define USIC_CH_TRBSR_ARBI_Pos 2 /*!< USIC_CH TRBSR: ARBI Position */\r
-#define USIC_CH_TRBSR_ARBI_Msk (0x01UL << USIC_CH_TRBSR_ARBI_Pos) /*!< USIC_CH TRBSR: ARBI Mask */\r
-#define USIC_CH_TRBSR_REMPTY_Pos 3 /*!< USIC_CH TRBSR: REMPTY Position */\r
-#define USIC_CH_TRBSR_REMPTY_Msk (0x01UL << USIC_CH_TRBSR_REMPTY_Pos) /*!< USIC_CH TRBSR: REMPTY Mask */\r
-#define USIC_CH_TRBSR_RFULL_Pos 4 /*!< USIC_CH TRBSR: RFULL Position */\r
-#define USIC_CH_TRBSR_RFULL_Msk (0x01UL << USIC_CH_TRBSR_RFULL_Pos) /*!< USIC_CH TRBSR: RFULL Mask */\r
-#define USIC_CH_TRBSR_RBUS_Pos 5 /*!< USIC_CH TRBSR: RBUS Position */\r
-#define USIC_CH_TRBSR_RBUS_Msk (0x01UL << USIC_CH_TRBSR_RBUS_Pos) /*!< USIC_CH TRBSR: RBUS Mask */\r
-#define USIC_CH_TRBSR_SRBT_Pos 6 /*!< USIC_CH TRBSR: SRBT Position */\r
-#define USIC_CH_TRBSR_SRBT_Msk (0x01UL << USIC_CH_TRBSR_SRBT_Pos) /*!< USIC_CH TRBSR: SRBT Mask */\r
-#define USIC_CH_TRBSR_STBI_Pos 8 /*!< USIC_CH TRBSR: STBI Position */\r
-#define USIC_CH_TRBSR_STBI_Msk (0x01UL << USIC_CH_TRBSR_STBI_Pos) /*!< USIC_CH TRBSR: STBI Mask */\r
-#define USIC_CH_TRBSR_TBERI_Pos 9 /*!< USIC_CH TRBSR: TBERI Position */\r
-#define USIC_CH_TRBSR_TBERI_Msk (0x01UL << USIC_CH_TRBSR_TBERI_Pos) /*!< USIC_CH TRBSR: TBERI Mask */\r
-#define USIC_CH_TRBSR_TEMPTY_Pos 11 /*!< USIC_CH TRBSR: TEMPTY Position */\r
-#define USIC_CH_TRBSR_TEMPTY_Msk (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos) /*!< USIC_CH TRBSR: TEMPTY Mask */\r
-#define USIC_CH_TRBSR_TFULL_Pos 12 /*!< USIC_CH TRBSR: TFULL Position */\r
-#define USIC_CH_TRBSR_TFULL_Msk (0x01UL << USIC_CH_TRBSR_TFULL_Pos) /*!< USIC_CH TRBSR: TFULL Mask */\r
-#define USIC_CH_TRBSR_TBUS_Pos 13 /*!< USIC_CH TRBSR: TBUS Position */\r
-#define USIC_CH_TRBSR_TBUS_Msk (0x01UL << USIC_CH_TRBSR_TBUS_Pos) /*!< USIC_CH TRBSR: TBUS Mask */\r
-#define USIC_CH_TRBSR_STBT_Pos 14 /*!< USIC_CH TRBSR: STBT Position */\r
-#define USIC_CH_TRBSR_STBT_Msk (0x01UL << USIC_CH_TRBSR_STBT_Pos) /*!< USIC_CH TRBSR: STBT Mask */\r
-#define USIC_CH_TRBSR_RBFLVL_Pos 16 /*!< USIC_CH TRBSR: RBFLVL Position */\r
-#define USIC_CH_TRBSR_RBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos) /*!< USIC_CH TRBSR: RBFLVL Mask */\r
-#define USIC_CH_TRBSR_TBFLVL_Pos 24 /*!< USIC_CH TRBSR: TBFLVL Position */\r
-#define USIC_CH_TRBSR_TBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos) /*!< USIC_CH TRBSR: TBFLVL Mask */\r
-\r
-/* ------------------------------- USIC_CH_TRBSCR ------------------------------- */\r
-#define USIC_CH_TRBSCR_CSRBI_Pos 0 /*!< USIC_CH TRBSCR: CSRBI Position */\r
-#define USIC_CH_TRBSCR_CSRBI_Msk (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos) /*!< USIC_CH TRBSCR: CSRBI Mask */\r
-#define USIC_CH_TRBSCR_CRBERI_Pos 1 /*!< USIC_CH TRBSCR: CRBERI Position */\r
-#define USIC_CH_TRBSCR_CRBERI_Msk (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos) /*!< USIC_CH TRBSCR: CRBERI Mask */\r
-#define USIC_CH_TRBSCR_CARBI_Pos 2 /*!< USIC_CH TRBSCR: CARBI Position */\r
-#define USIC_CH_TRBSCR_CARBI_Msk (0x01UL << USIC_CH_TRBSCR_CARBI_Pos) /*!< USIC_CH TRBSCR: CARBI Mask */\r
-#define USIC_CH_TRBSCR_CSTBI_Pos 8 /*!< USIC_CH TRBSCR: CSTBI Position */\r
-#define USIC_CH_TRBSCR_CSTBI_Msk (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos) /*!< USIC_CH TRBSCR: CSTBI Mask */\r
-#define USIC_CH_TRBSCR_CTBERI_Pos 9 /*!< USIC_CH TRBSCR: CTBERI Position */\r
-#define USIC_CH_TRBSCR_CTBERI_Msk (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos) /*!< USIC_CH TRBSCR: CTBERI Mask */\r
-#define USIC_CH_TRBSCR_CBDV_Pos 10 /*!< USIC_CH TRBSCR: CBDV Position */\r
-#define USIC_CH_TRBSCR_CBDV_Msk (0x01UL << USIC_CH_TRBSCR_CBDV_Pos) /*!< USIC_CH TRBSCR: CBDV Mask */\r
-#define USIC_CH_TRBSCR_FLUSHRB_Pos 14 /*!< USIC_CH TRBSCR: FLUSHRB Position */\r
-#define USIC_CH_TRBSCR_FLUSHRB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos) /*!< USIC_CH TRBSCR: FLUSHRB Mask */\r
-#define USIC_CH_TRBSCR_FLUSHTB_Pos 15 /*!< USIC_CH TRBSCR: FLUSHTB Position */\r
-#define USIC_CH_TRBSCR_FLUSHTB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos) /*!< USIC_CH TRBSCR: FLUSHTB Mask */\r
-\r
-/* -------------------------------- USIC_CH_OUTR -------------------------------- */\r
-#define USIC_CH_OUTR_DSR_Pos 0 /*!< USIC_CH OUTR: DSR Position */\r
-#define USIC_CH_OUTR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos) /*!< USIC_CH OUTR: DSR Mask */\r
-#define USIC_CH_OUTR_RCI_Pos 16 /*!< USIC_CH OUTR: RCI Position */\r
-#define USIC_CH_OUTR_RCI_Msk (0x1fUL << USIC_CH_OUTR_RCI_Pos) /*!< USIC_CH OUTR: RCI Mask */\r
-\r
-/* -------------------------------- USIC_CH_OUTDR ------------------------------- */\r
-#define USIC_CH_OUTDR_DSR_Pos 0 /*!< USIC_CH OUTDR: DSR Position */\r
-#define USIC_CH_OUTDR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos) /*!< USIC_CH OUTDR: DSR Mask */\r
-#define USIC_CH_OUTDR_RCI_Pos 16 /*!< USIC_CH OUTDR: RCI Position */\r
-#define USIC_CH_OUTDR_RCI_Msk (0x1fUL << USIC_CH_OUTDR_RCI_Pos) /*!< USIC_CH OUTDR: RCI Mask */\r
-\r
-/* --------------------------------- USIC_CH_IN --------------------------------- */\r
-#define USIC_CH_IN_TDATA_Pos 0 /*!< USIC_CH IN: TDATA Position */\r
-#define USIC_CH_IN_TDATA_Msk (0x0000ffffUL << USIC_CH_IN_TDATA_Pos) /*!< USIC_CH IN: TDATA Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SCU_GENERAL' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------- SCU_GENERAL_DBGROMID ---------------------------- */\r
-#define SCU_GENERAL_DBGROMID_MANUFID_Pos 1 /*!< SCU_GENERAL DBGROMID: MANUFID Position */\r
-#define SCU_GENERAL_DBGROMID_MANUFID_Msk (0x000007ffUL << SCU_GENERAL_DBGROMID_MANUFID_Pos) /*!< SCU_GENERAL DBGROMID: MANUFID Mask */\r
-#define SCU_GENERAL_DBGROMID_PARTNO_Pos 12 /*!< SCU_GENERAL DBGROMID: PARTNO Position */\r
-#define SCU_GENERAL_DBGROMID_PARTNO_Msk (0x0000ffffUL << SCU_GENERAL_DBGROMID_PARTNO_Pos) /*!< SCU_GENERAL DBGROMID: PARTNO Mask */\r
-#define SCU_GENERAL_DBGROMID_VERSION_Pos 28 /*!< SCU_GENERAL DBGROMID: VERSION Position */\r
-#define SCU_GENERAL_DBGROMID_VERSION_Msk (0x0fUL << SCU_GENERAL_DBGROMID_VERSION_Pos) /*!< SCU_GENERAL DBGROMID: VERSION Mask */\r
-\r
-/* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */\r
-#define SCU_GENERAL_IDCHIP_IDCHIP_Pos 0 /*!< SCU_GENERAL IDCHIP: IDCHIP Position */\r
-#define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos) /*!< SCU_GENERAL IDCHIP: IDCHIP Mask */\r
-\r
-/* ------------------------------- SCU_GENERAL_ID ------------------------------- */\r
-#define SCU_GENERAL_ID_MOD_REV_Pos 0 /*!< SCU_GENERAL ID: MOD_REV Position */\r
-#define SCU_GENERAL_ID_MOD_REV_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos) /*!< SCU_GENERAL ID: MOD_REV Mask */\r
-#define SCU_GENERAL_ID_MOD_TYPE_Pos 8 /*!< SCU_GENERAL ID: MOD_TYPE Position */\r
-#define SCU_GENERAL_ID_MOD_TYPE_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos) /*!< SCU_GENERAL ID: MOD_TYPE Mask */\r
-#define SCU_GENERAL_ID_MOD_NUMBER_Pos 16 /*!< SCU_GENERAL ID: MOD_NUMBER Position */\r
-#define SCU_GENERAL_ID_MOD_NUMBER_Msk (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos) /*!< SCU_GENERAL ID: MOD_NUMBER Mask */\r
-\r
-/* ------------------------------ SCU_GENERAL_SSW0 ------------------------------ */\r
-#define SCU_GENERAL_SSW0_DAT_Pos 0 /*!< SCU_GENERAL SSW0: DAT Position */\r
-#define SCU_GENERAL_SSW0_DAT_Msk (0xffffffffUL << SCU_GENERAL_SSW0_DAT_Pos) /*!< SCU_GENERAL SSW0: DAT Mask */\r
-\r
-/* ----------------------------- SCU_GENERAL_PASSWD ----------------------------- */\r
-#define SCU_GENERAL_PASSWD_MODE_Pos 0 /*!< SCU_GENERAL PASSWD: MODE Position */\r
-#define SCU_GENERAL_PASSWD_MODE_Msk (0x03UL << SCU_GENERAL_PASSWD_MODE_Pos) /*!< SCU_GENERAL PASSWD: MODE Mask */\r
-#define SCU_GENERAL_PASSWD_PROTS_Pos 2 /*!< SCU_GENERAL PASSWD: PROTS Position */\r
-#define SCU_GENERAL_PASSWD_PROTS_Msk (0x01UL << SCU_GENERAL_PASSWD_PROTS_Pos) /*!< SCU_GENERAL PASSWD: PROTS Mask */\r
-#define SCU_GENERAL_PASSWD_PASS_Pos 3 /*!< SCU_GENERAL PASSWD: PASS Position */\r
-#define SCU_GENERAL_PASSWD_PASS_Msk (0x1fUL << SCU_GENERAL_PASSWD_PASS_Pos) /*!< SCU_GENERAL PASSWD: PASS Mask */\r
-\r
-/* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */\r
-#define SCU_GENERAL_CCUCON_GSC40_Pos 0 /*!< SCU_GENERAL CCUCON: GSC40 Position */\r
-#define SCU_GENERAL_CCUCON_GSC40_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos) /*!< SCU_GENERAL CCUCON: GSC40 Mask */\r
-\r
-/* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */\r
-#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos 0 /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position */\r
-#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask */\r
-#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos 1 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */\r
-#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask */\r
-#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos 2 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */\r
-#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask */\r
-#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos 3 /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position */\r
-#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask */\r
-#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos 4 /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position */\r
-#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask */\r
-\r
-/* ------------------------------ SCU_GENERAL_PMTSR ----------------------------- */\r
-#define SCU_GENERAL_PMTSR_MTENS_Pos 0 /*!< SCU_GENERAL PMTSR: MTENS Position */\r
-#define SCU_GENERAL_PMTSR_MTENS_Msk (0x01UL << SCU_GENERAL_PMTSR_MTENS_Pos) /*!< SCU_GENERAL PMTSR: MTENS Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */\r
-#define SCU_INTERRUPT_SRRAW_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRRAW: PRWARN Position */\r
-#define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos) /*!< SCU_INTERRUPT SRRAW: PRWARN Mask */\r
-#define SCU_INTERRUPT_SRRAW_PI_Pos 1 /*!< SCU_INTERRUPT SRRAW: PI Position */\r
-#define SCU_INTERRUPT_SRRAW_PI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos) /*!< SCU_INTERRUPT SRRAW: PI Mask */\r
-#define SCU_INTERRUPT_SRRAW_AI_Pos 2 /*!< SCU_INTERRUPT SRRAW: AI Position */\r
-#define SCU_INTERRUPT_SRRAW_AI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos) /*!< SCU_INTERRUPT SRRAW: AI Mask */\r
-#define SCU_INTERRUPT_SRRAW_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRRAW: VDDPI Position */\r
-#define SCU_INTERRUPT_SRRAW_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDDPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDDPI Mask */\r
-#define SCU_INTERRUPT_SRRAW_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRRAW: ACMP0I Position */\r
-#define SCU_INTERRUPT_SRRAW_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP0I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP0I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRRAW: ACMP1I Position */\r
-#define SCU_INTERRUPT_SRRAW_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP1I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP1I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRRAW: ACMP2I Position */\r
-#define SCU_INTERRUPT_SRRAW_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP2I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP2I Mask */\r
-#define SCU_INTERRUPT_SRRAW_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRRAW: VDROPI Position */\r
-#define SCU_INTERRUPT_SRRAW_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDROPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDROPI Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRRAW: ORC0I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC0I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC0I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRRAW: ORC1I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC1I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC1I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRRAW: ORC2I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC2I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC2I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRRAW: ORC3I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC3I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC3I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRRAW: ORC4I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC4I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC4I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRRAW: ORC5I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC5I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC5I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRRAW: ORC6I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC6I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC6I Mask */\r
-#define SCU_INTERRUPT_SRRAW_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRRAW: ORC7I Position */\r
-#define SCU_INTERRUPT_SRRAW_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC7I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC7I Mask */\r
-#define SCU_INTERRUPT_SRRAW_LOCI_Pos 16 /*!< SCU_INTERRUPT SRRAW: LOCI Position */\r
-#define SCU_INTERRUPT_SRRAW_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LOCI_Pos) /*!< SCU_INTERRUPT SRRAW: LOCI Mask */\r
-#define SCU_INTERRUPT_SRRAW_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRRAW: PESRAMI Position */\r
-#define SCU_INTERRUPT_SRRAW_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PESRAMI_Pos) /*!< SCU_INTERRUPT SRRAW: PESRAMI Mask */\r
-#define SCU_INTERRUPT_SRRAW_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRRAW: PEU0I Position */\r
-#define SCU_INTERRUPT_SRRAW_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PEU0I_Pos) /*!< SCU_INTERRUPT SRRAW: PEU0I Mask */\r
-#define SCU_INTERRUPT_SRRAW_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRRAW: FLECC2I Position */\r
-#define SCU_INTERRUPT_SRRAW_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLECC2I_Pos) /*!< SCU_INTERRUPT SRRAW: FLECC2I Mask */\r
-#define SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Position */\r
-#define SCU_INTERRUPT_SRRAW_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Mask */\r
-#define SCU_INTERRUPT_SRRAW_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRRAW: VCLIPI Position */\r
-#define SCU_INTERRUPT_SRRAW_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VCLIPI_Pos) /*!< SCU_INTERRUPT SRRAW: VCLIPI Mask */\r
-#define SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Position */\r
-#define SCU_INTERRUPT_SRRAW_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Mask */\r
-#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position */\r
-#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask */\r
-#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */\r
-#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask */\r
-#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */\r
-#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask */\r
-#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position */\r
-#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask */\r
-#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position */\r
-#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask */\r
-#define SCU_INTERRUPT_SRRAW_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRRAW: TSE_DONE Position */\r
-#define SCU_INTERRUPT_SRRAW_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_DONE Mask */\r
-#define SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Position */\r
-#define SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Mask */\r
-#define SCU_INTERRUPT_SRRAW_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRRAW: TSE_LOW Position */\r
-#define SCU_INTERRUPT_SRRAW_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_LOW Mask */\r
-\r
-/* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */\r
-#define SCU_INTERRUPT_SRMSK_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRMSK: PRWARN Position */\r
-#define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos) /*!< SCU_INTERRUPT SRMSK: PRWARN Mask */\r
-#define SCU_INTERRUPT_SRMSK_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRMSK: VDDPI Position */\r
-#define SCU_INTERRUPT_SRMSK_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDDPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDDPI Mask */\r
-#define SCU_INTERRUPT_SRMSK_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRMSK: ACMP0I Position */\r
-#define SCU_INTERRUPT_SRMSK_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP0I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP0I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRMSK: ACMP1I Position */\r
-#define SCU_INTERRUPT_SRMSK_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP1I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP1I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRMSK: ACMP2I Position */\r
-#define SCU_INTERRUPT_SRMSK_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP2I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP2I Mask */\r
-#define SCU_INTERRUPT_SRMSK_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRMSK: VDROPI Position */\r
-#define SCU_INTERRUPT_SRMSK_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDROPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDROPI Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRMSK: ORC0I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC0I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC0I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRMSK: ORC1I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC1I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC1I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRMSK: ORC2I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC2I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC2I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRMSK: ORC3I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC3I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC3I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRMSK: ORC4I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC4I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC4I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRMSK: ORC5I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC5I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC5I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRMSK: ORC6I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC6I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC6I Mask */\r
-#define SCU_INTERRUPT_SRMSK_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRMSK: ORC7I Position */\r
-#define SCU_INTERRUPT_SRMSK_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC7I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC7I Mask */\r
-#define SCU_INTERRUPT_SRMSK_LOCI_Pos 16 /*!< SCU_INTERRUPT SRMSK: LOCI Position */\r
-#define SCU_INTERRUPT_SRMSK_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LOCI_Pos) /*!< SCU_INTERRUPT SRMSK: LOCI Mask */\r
-#define SCU_INTERRUPT_SRMSK_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRMSK: PESRAMI Position */\r
-#define SCU_INTERRUPT_SRMSK_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PESRAMI_Pos) /*!< SCU_INTERRUPT SRMSK: PESRAMI Mask */\r
-#define SCU_INTERRUPT_SRMSK_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRMSK: PEU0I Position */\r
-#define SCU_INTERRUPT_SRMSK_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PEU0I_Pos) /*!< SCU_INTERRUPT SRMSK: PEU0I Mask */\r
-#define SCU_INTERRUPT_SRMSK_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRMSK: FLECC2I Position */\r
-#define SCU_INTERRUPT_SRMSK_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_FLECC2I_Pos) /*!< SCU_INTERRUPT SRMSK: FLECC2I Mask */\r
-#define SCU_INTERRUPT_SRMSK_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRMSK: VCLIPI Position */\r
-#define SCU_INTERRUPT_SRMSK_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VCLIPI_Pos) /*!< SCU_INTERRUPT SRMSK: VCLIPI Mask */\r
-#define SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Position */\r
-#define SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Mask */\r
-#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position */\r
-#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask */\r
-#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */\r
-#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask */\r
-#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */\r
-#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask */\r
-#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position */\r
-#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask */\r
-#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position */\r
-#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask */\r
-#define SCU_INTERRUPT_SRMSK_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRMSK: TSE_DONE Position */\r
-#define SCU_INTERRUPT_SRMSK_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_DONE Mask */\r
-#define SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Position */\r
-#define SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Mask */\r
-#define SCU_INTERRUPT_SRMSK_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRMSK: TSE_LOW Position */\r
-#define SCU_INTERRUPT_SRMSK_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_LOW Mask */\r
-\r
-/* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */\r
-#define SCU_INTERRUPT_SRCLR_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRCLR: PRWARN Position */\r
-#define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos) /*!< SCU_INTERRUPT SRCLR: PRWARN Mask */\r
-#define SCU_INTERRUPT_SRCLR_PI_Pos 1 /*!< SCU_INTERRUPT SRCLR: PI Position */\r
-#define SCU_INTERRUPT_SRCLR_PI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos) /*!< SCU_INTERRUPT SRCLR: PI Mask */\r
-#define SCU_INTERRUPT_SRCLR_AI_Pos 2 /*!< SCU_INTERRUPT SRCLR: AI Position */\r
-#define SCU_INTERRUPT_SRCLR_AI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos) /*!< SCU_INTERRUPT SRCLR: AI Mask */\r
-#define SCU_INTERRUPT_SRCLR_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRCLR: VDDPI Position */\r
-#define SCU_INTERRUPT_SRCLR_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDDPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDDPI Mask */\r
-#define SCU_INTERRUPT_SRCLR_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRCLR: ACMP0I Position */\r
-#define SCU_INTERRUPT_SRCLR_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP0I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP0I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRCLR: ACMP1I Position */\r
-#define SCU_INTERRUPT_SRCLR_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP1I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP1I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRCLR: ACMP2I Position */\r
-#define SCU_INTERRUPT_SRCLR_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP2I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP2I Mask */\r
-#define SCU_INTERRUPT_SRCLR_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRCLR: VDROPI Position */\r
-#define SCU_INTERRUPT_SRCLR_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDROPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDROPI Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRCLR: ORC0I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC0I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC0I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRCLR: ORC1I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC1I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC1I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRCLR: ORC2I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC2I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC2I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRCLR: ORC3I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC3I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC3I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRCLR: ORC4I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC4I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC4I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRCLR: ORC5I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC5I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC5I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRCLR: ORC6I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC6I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC6I Mask */\r
-#define SCU_INTERRUPT_SRCLR_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRCLR: ORC7I Position */\r
-#define SCU_INTERRUPT_SRCLR_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC7I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC7I Mask */\r
-#define SCU_INTERRUPT_SRCLR_LOCI_Pos 16 /*!< SCU_INTERRUPT SRCLR: LOCI Position */\r
-#define SCU_INTERRUPT_SRCLR_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LOCI_Pos) /*!< SCU_INTERRUPT SRCLR: LOCI Mask */\r
-#define SCU_INTERRUPT_SRCLR_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRCLR: PESRAMI Position */\r
-#define SCU_INTERRUPT_SRCLR_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PESRAMI_Pos) /*!< SCU_INTERRUPT SRCLR: PESRAMI Mask */\r
-#define SCU_INTERRUPT_SRCLR_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRCLR: PEU0I Position */\r
-#define SCU_INTERRUPT_SRCLR_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PEU0I_Pos) /*!< SCU_INTERRUPT SRCLR: PEU0I Mask */\r
-#define SCU_INTERRUPT_SRCLR_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRCLR: FLECC2I Position */\r
-#define SCU_INTERRUPT_SRCLR_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLECC2I_Pos) /*!< SCU_INTERRUPT SRCLR: FLECC2I Mask */\r
-#define SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Position */\r
-#define SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Mask */\r
-#define SCU_INTERRUPT_SRCLR_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRCLR: VCLIPI Position */\r
-#define SCU_INTERRUPT_SRCLR_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VCLIPI_Pos) /*!< SCU_INTERRUPT SRCLR: VCLIPI Mask */\r
-#define SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Position */\r
-#define SCU_INTERRUPT_SRCLR_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Mask */\r
-#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position */\r
-#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask */\r
-#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */\r
-#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask */\r
-#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */\r
-#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask */\r
-#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position */\r
-#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask */\r
-#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position */\r
-#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask */\r
-#define SCU_INTERRUPT_SRCLR_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRCLR: TSE_DONE Position */\r
-#define SCU_INTERRUPT_SRCLR_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_DONE Mask */\r
-#define SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Position */\r
-#define SCU_INTERRUPT_SRCLR_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Mask */\r
-#define SCU_INTERRUPT_SRCLR_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRCLR: TSE_LOW Position */\r
-#define SCU_INTERRUPT_SRCLR_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_LOW Mask */\r
-\r
-/* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */\r
-#define SCU_INTERRUPT_SRSET_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRSET: PRWARN Position */\r
-#define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos) /*!< SCU_INTERRUPT SRSET: PRWARN Mask */\r
-#define SCU_INTERRUPT_SRSET_PI_Pos 1 /*!< SCU_INTERRUPT SRSET: PI Position */\r
-#define SCU_INTERRUPT_SRSET_PI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos) /*!< SCU_INTERRUPT SRSET: PI Mask */\r
-#define SCU_INTERRUPT_SRSET_AI_Pos 2 /*!< SCU_INTERRUPT SRSET: AI Position */\r
-#define SCU_INTERRUPT_SRSET_AI_Msk (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos) /*!< SCU_INTERRUPT SRSET: AI Mask */\r
-#define SCU_INTERRUPT_SRSET_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRSET: VDDPI Position */\r
-#define SCU_INTERRUPT_SRSET_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDDPI_Pos) /*!< SCU_INTERRUPT SRSET: VDDPI Mask */\r
-#define SCU_INTERRUPT_SRSET_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRSET: ACMP0I Position */\r
-#define SCU_INTERRUPT_SRSET_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP0I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP0I Mask */\r
-#define SCU_INTERRUPT_SRSET_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRSET: ACMP1I Position */\r
-#define SCU_INTERRUPT_SRSET_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP1I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP1I Mask */\r
-#define SCU_INTERRUPT_SRSET_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRSET: ACMP2I Position */\r
-#define SCU_INTERRUPT_SRSET_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP2I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP2I Mask */\r
-#define SCU_INTERRUPT_SRSET_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRSET: VDROPI Position */\r
-#define SCU_INTERRUPT_SRSET_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDROPI_Pos) /*!< SCU_INTERRUPT SRSET: VDROPI Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRSET: ORC0I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC0I_Pos) /*!< SCU_INTERRUPT SRSET: ORC0I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRSET: ORC1I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC1I_Pos) /*!< SCU_INTERRUPT SRSET: ORC1I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRSET: ORC2I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC2I_Pos) /*!< SCU_INTERRUPT SRSET: ORC2I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRSET: ORC3I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC3I_Pos) /*!< SCU_INTERRUPT SRSET: ORC3I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRSET: ORC4I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC4I_Pos) /*!< SCU_INTERRUPT SRSET: ORC4I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRSET: ORC5I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC5I_Pos) /*!< SCU_INTERRUPT SRSET: ORC5I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRSET: ORC6I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC6I_Pos) /*!< SCU_INTERRUPT SRSET: ORC6I Mask */\r
-#define SCU_INTERRUPT_SRSET_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRSET: ORC7I Position */\r
-#define SCU_INTERRUPT_SRSET_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC7I_Pos) /*!< SCU_INTERRUPT SRSET: ORC7I Mask */\r
-#define SCU_INTERRUPT_SRSET_LOCI_Pos 16 /*!< SCU_INTERRUPT SRSET: LOCI Position */\r
-#define SCU_INTERRUPT_SRSET_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRSET_LOCI_Pos) /*!< SCU_INTERRUPT SRSET: LOCI Mask */\r
-#define SCU_INTERRUPT_SRSET_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRSET: PESRAMI Position */\r
-#define SCU_INTERRUPT_SRSET_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PESRAMI_Pos) /*!< SCU_INTERRUPT SRSET: PESRAMI Mask */\r
-#define SCU_INTERRUPT_SRSET_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRSET: PEU0I Position */\r
-#define SCU_INTERRUPT_SRSET_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_PEU0I_Pos) /*!< SCU_INTERRUPT SRSET: PEU0I Mask */\r
-#define SCU_INTERRUPT_SRSET_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRSET: FLECC2I Position */\r
-#define SCU_INTERRUPT_SRSET_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLECC2I_Pos) /*!< SCU_INTERRUPT SRSET: FLECC2I Mask */\r
-#define SCU_INTERRUPT_SRSET_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRSET: FLCMPLTI Position */\r
-#define SCU_INTERRUPT_SRSET_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRSET: FLCMPLTI Mask */\r
-#define SCU_INTERRUPT_SRSET_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRSET: VCLIPI Position */\r
-#define SCU_INTERRUPT_SRSET_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VCLIPI_Pos) /*!< SCU_INTERRUPT SRSET: VCLIPI Mask */\r
-#define SCU_INTERRUPT_SRSET_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRSET: SBYCLKFI Position */\r
-#define SCU_INTERRUPT_SRSET_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRSET_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRSET: SBYCLKFI Mask */\r
-#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRSET: RTC_CTR Position */\r
-#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask */\r
-#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */\r
-#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask */\r
-#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */\r
-#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask */\r
-#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position */\r
-#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask */\r
-#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position */\r
-#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask */\r
-#define SCU_INTERRUPT_SRSET_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRSET: TSE_DONE Position */\r
-#define SCU_INTERRUPT_SRSET_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRSET: TSE_DONE Mask */\r
-#define SCU_INTERRUPT_SRSET_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRSET: TSE_HIGH Position */\r
-#define SCU_INTERRUPT_SRSET_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRSET: TSE_HIGH Mask */\r
-#define SCU_INTERRUPT_SRSET_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRSET: TSE_LOW Position */\r
-#define SCU_INTERRUPT_SRSET_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRSET: TSE_LOW Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SCU_POWER' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------- SCU_POWER_VDESR ------------------------------ */\r
-#define SCU_POWER_VDESR_VCLIP_Pos 0 /*!< SCU_POWER VDESR: VCLIP Position */\r
-#define SCU_POWER_VDESR_VCLIP_Msk (0x01UL << SCU_POWER_VDESR_VCLIP_Pos) /*!< SCU_POWER VDESR: VCLIP Mask */\r
-#define SCU_POWER_VDESR_VDDPPW_Pos 1 /*!< SCU_POWER VDESR: VDDPPW Position */\r
-#define SCU_POWER_VDESR_VDDPPW_Msk (0x01UL << SCU_POWER_VDESR_VDDPPW_Pos) /*!< SCU_POWER VDESR: VDDPPW Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SCU_CLK' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- SCU_CLK_CLKCR ------------------------------- */\r
-#define SCU_CLK_CLKCR_FDIV_Pos 0 /*!< SCU_CLK CLKCR: FDIV Position */\r
-#define SCU_CLK_CLKCR_FDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_FDIV_Pos) /*!< SCU_CLK CLKCR: FDIV Mask */\r
-#define SCU_CLK_CLKCR_IDIV_Pos 8 /*!< SCU_CLK CLKCR: IDIV Position */\r
-#define SCU_CLK_CLKCR_IDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_IDIV_Pos) /*!< SCU_CLK CLKCR: IDIV Mask */\r
-#define SCU_CLK_CLKCR_PCLKSEL_Pos 16 /*!< SCU_CLK CLKCR: PCLKSEL Position */\r
-#define SCU_CLK_CLKCR_PCLKSEL_Msk (0x01UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /*!< SCU_CLK CLKCR: PCLKSEL Mask */\r
-#define SCU_CLK_CLKCR_RTCCLKSEL_Pos 17 /*!< SCU_CLK CLKCR: RTCCLKSEL Position */\r
-#define SCU_CLK_CLKCR_RTCCLKSEL_Msk (0x07UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /*!< SCU_CLK CLKCR: RTCCLKSEL Mask */\r
-#define SCU_CLK_CLKCR_CNTADJ_Pos 20 /*!< SCU_CLK CLKCR: CNTADJ Position */\r
-#define SCU_CLK_CLKCR_CNTADJ_Msk (0x000003ffUL << SCU_CLK_CLKCR_CNTADJ_Pos) /*!< SCU_CLK CLKCR: CNTADJ Mask */\r
-#define SCU_CLK_CLKCR_VDDC2LOW_Pos 30 /*!< SCU_CLK CLKCR: VDDC2LOW Position */\r
-#define SCU_CLK_CLKCR_VDDC2LOW_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2LOW_Pos) /*!< SCU_CLK CLKCR: VDDC2LOW Mask */\r
-#define SCU_CLK_CLKCR_VDDC2HIGH_Pos 31 /*!< SCU_CLK CLKCR: VDDC2HIGH Position */\r
-#define SCU_CLK_CLKCR_VDDC2HIGH_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2HIGH_Pos) /*!< SCU_CLK CLKCR: VDDC2HIGH Mask */\r
-\r
-/* ------------------------------- SCU_CLK_PWRSVCR ------------------------------ */\r
-#define SCU_CLK_PWRSVCR_FPD_Pos 0 /*!< SCU_CLK PWRSVCR: FPD Position */\r
-#define SCU_CLK_PWRSVCR_FPD_Msk (0x01UL << SCU_CLK_PWRSVCR_FPD_Pos) /*!< SCU_CLK PWRSVCR: FPD Mask */\r
-\r
-/* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */\r
-#define SCU_CLK_CGATSTAT0_VADC_Pos 0 /*!< SCU_CLK CGATSTAT0: VADC Position */\r
-#define SCU_CLK_CGATSTAT0_VADC_Msk (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos) /*!< SCU_CLK CGATSTAT0: VADC Mask */\r
-#define SCU_CLK_CGATSTAT0_CCU40_Pos 2 /*!< SCU_CLK CGATSTAT0: CCU40 Position */\r
-#define SCU_CLK_CGATSTAT0_CCU40_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos) /*!< SCU_CLK CGATSTAT0: CCU40 Mask */\r
-#define SCU_CLK_CGATSTAT0_USIC0_Pos 3 /*!< SCU_CLK CGATSTAT0: USIC0 Position */\r
-#define SCU_CLK_CGATSTAT0_USIC0_Msk (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos) /*!< SCU_CLK CGATSTAT0: USIC0 Mask */\r
-#define SCU_CLK_CGATSTAT0_BCCU0_Pos 4 /*!< SCU_CLK CGATSTAT0: BCCU0 Position */\r
-#define SCU_CLK_CGATSTAT0_BCCU0_Msk (0x01UL << SCU_CLK_CGATSTAT0_BCCU0_Pos) /*!< SCU_CLK CGATSTAT0: BCCU0 Mask */\r
-#define SCU_CLK_CGATSTAT0_LEDTS0_Pos 5 /*!< SCU_CLK CGATSTAT0: LEDTS0 Position */\r
-#define SCU_CLK_CGATSTAT0_LEDTS0_Msk (0x01UL << SCU_CLK_CGATSTAT0_LEDTS0_Pos) /*!< SCU_CLK CGATSTAT0: LEDTS0 Mask */\r
-#define SCU_CLK_CGATSTAT0_LEDTS1_Pos 6 /*!< SCU_CLK CGATSTAT0: LEDTS1 Position */\r
-#define SCU_CLK_CGATSTAT0_LEDTS1_Msk (0x01UL << SCU_CLK_CGATSTAT0_LEDTS1_Pos) /*!< SCU_CLK CGATSTAT0: LEDTS1 Mask */\r
-#define SCU_CLK_CGATSTAT0_WDT_Pos 9 /*!< SCU_CLK CGATSTAT0: WDT Position */\r
-#define SCU_CLK_CGATSTAT0_WDT_Msk (0x01UL << SCU_CLK_CGATSTAT0_WDT_Pos) /*!< SCU_CLK CGATSTAT0: WDT Mask */\r
-#define SCU_CLK_CGATSTAT0_RTC_Pos 10 /*!< SCU_CLK CGATSTAT0: RTC Position */\r
-#define SCU_CLK_CGATSTAT0_RTC_Msk (0x01UL << SCU_CLK_CGATSTAT0_RTC_Pos) /*!< SCU_CLK CGATSTAT0: RTC Mask */\r
-\r
-/* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */\r
-#define SCU_CLK_CGATSET0_VADC_Pos 0 /*!< SCU_CLK CGATSET0: VADC Position */\r
-#define SCU_CLK_CGATSET0_VADC_Msk (0x01UL << SCU_CLK_CGATSET0_VADC_Pos) /*!< SCU_CLK CGATSET0: VADC Mask */\r
-#define SCU_CLK_CGATSET0_CCU40_Pos 2 /*!< SCU_CLK CGATSET0: CCU40 Position */\r
-#define SCU_CLK_CGATSET0_CCU40_Msk (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos) /*!< SCU_CLK CGATSET0: CCU40 Mask */\r
-#define SCU_CLK_CGATSET0_USIC0_Pos 3 /*!< SCU_CLK CGATSET0: USIC0 Position */\r
-#define SCU_CLK_CGATSET0_USIC0_Msk (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos) /*!< SCU_CLK CGATSET0: USIC0 Mask */\r
-#define SCU_CLK_CGATSET0_BCCU0_Pos 4 /*!< SCU_CLK CGATSET0: BCCU0 Position */\r
-#define SCU_CLK_CGATSET0_BCCU0_Msk (0x01UL << SCU_CLK_CGATSET0_BCCU0_Pos) /*!< SCU_CLK CGATSET0: BCCU0 Mask */\r
-#define SCU_CLK_CGATSET0_LEDTS0_Pos 5 /*!< SCU_CLK CGATSET0: LEDTS0 Position */\r
-#define SCU_CLK_CGATSET0_LEDTS0_Msk (0x01UL << SCU_CLK_CGATSET0_LEDTS0_Pos) /*!< SCU_CLK CGATSET0: LEDTS0 Mask */\r
-#define SCU_CLK_CGATSET0_LEDTS1_Pos 6 /*!< SCU_CLK CGATSET0: LEDTS1 Position */\r
-#define SCU_CLK_CGATSET0_LEDTS1_Msk (0x01UL << SCU_CLK_CGATSET0_LEDTS1_Pos) /*!< SCU_CLK CGATSET0: LEDTS1 Mask */\r
-#define SCU_CLK_CGATSET0_WDT_Pos 9 /*!< SCU_CLK CGATSET0: WDT Position */\r
-#define SCU_CLK_CGATSET0_WDT_Msk (0x01UL << SCU_CLK_CGATSET0_WDT_Pos) /*!< SCU_CLK CGATSET0: WDT Mask */\r
-#define SCU_CLK_CGATSET0_RTC_Pos 10 /*!< SCU_CLK CGATSET0: RTC Position */\r
-#define SCU_CLK_CGATSET0_RTC_Msk (0x01UL << SCU_CLK_CGATSET0_RTC_Pos) /*!< SCU_CLK CGATSET0: RTC Mask */\r
-\r
-/* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */\r
-#define SCU_CLK_CGATCLR0_VADC_Pos 0 /*!< SCU_CLK CGATCLR0: VADC Position */\r
-#define SCU_CLK_CGATCLR0_VADC_Msk (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos) /*!< SCU_CLK CGATCLR0: VADC Mask */\r
-#define SCU_CLK_CGATCLR0_CCU40_Pos 2 /*!< SCU_CLK CGATCLR0: CCU40 Position */\r
-#define SCU_CLK_CGATCLR0_CCU40_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos) /*!< SCU_CLK CGATCLR0: CCU40 Mask */\r
-#define SCU_CLK_CGATCLR0_USIC0_Pos 3 /*!< SCU_CLK CGATCLR0: USIC0 Position */\r
-#define SCU_CLK_CGATCLR0_USIC0_Msk (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos) /*!< SCU_CLK CGATCLR0: USIC0 Mask */\r
-#define SCU_CLK_CGATCLR0_BCCU0_Pos 4 /*!< SCU_CLK CGATCLR0: BCCU0 Position */\r
-#define SCU_CLK_CGATCLR0_BCCU0_Msk (0x01UL << SCU_CLK_CGATCLR0_BCCU0_Pos) /*!< SCU_CLK CGATCLR0: BCCU0 Mask */\r
-#define SCU_CLK_CGATCLR0_LEDTS0_Pos 5 /*!< SCU_CLK CGATCLR0: LEDTS0 Position */\r
-#define SCU_CLK_CGATCLR0_LEDTS0_Msk (0x01UL << SCU_CLK_CGATCLR0_LEDTS0_Pos) /*!< SCU_CLK CGATCLR0: LEDTS0 Mask */\r
-#define SCU_CLK_CGATCLR0_LEDTS1_Pos 6 /*!< SCU_CLK CGATCLR0: LEDTS1 Position */\r
-#define SCU_CLK_CGATCLR0_LEDTS1_Msk (0x01UL << SCU_CLK_CGATCLR0_LEDTS1_Pos) /*!< SCU_CLK CGATCLR0: LEDTS1 Mask */\r
-#define SCU_CLK_CGATCLR0_WDT_Pos 9 /*!< SCU_CLK CGATCLR0: WDT Position */\r
-#define SCU_CLK_CGATCLR0_WDT_Msk (0x01UL << SCU_CLK_CGATCLR0_WDT_Pos) /*!< SCU_CLK CGATCLR0: WDT Mask */\r
-#define SCU_CLK_CGATCLR0_RTC_Pos 10 /*!< SCU_CLK CGATCLR0: RTC Position */\r
-#define SCU_CLK_CGATCLR0_RTC_Msk (0x01UL << SCU_CLK_CGATCLR0_RTC_Pos) /*!< SCU_CLK CGATCLR0: RTC Mask */\r
-\r
-/* ------------------------------- SCU_CLK_OSCCSR ------------------------------- */\r
-#define SCU_CLK_OSCCSR_OSC2L_Pos 0 /*!< SCU_CLK OSCCSR: OSC2L Position */\r
-#define SCU_CLK_OSCCSR_OSC2L_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2L_Pos) /*!< SCU_CLK OSCCSR: OSC2L Mask */\r
-#define SCU_CLK_OSCCSR_OSC2H_Pos 1 /*!< SCU_CLK OSCCSR: OSC2H Position */\r
-#define SCU_CLK_OSCCSR_OSC2H_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2H_Pos) /*!< SCU_CLK OSCCSR: OSC2H Mask */\r
-#define SCU_CLK_OSCCSR_OWDRES_Pos 16 /*!< SCU_CLK OSCCSR: OWDRES Position */\r
-#define SCU_CLK_OSCCSR_OWDRES_Msk (0x01UL << SCU_CLK_OSCCSR_OWDRES_Pos) /*!< SCU_CLK OSCCSR: OWDRES Mask */\r
-#define SCU_CLK_OSCCSR_OWDEN_Pos 17 /*!< SCU_CLK OSCCSR: OWDEN Position */\r
-#define SCU_CLK_OSCCSR_OWDEN_Msk (0x01UL << SCU_CLK_OSCCSR_OWDEN_Pos) /*!< SCU_CLK OSCCSR: OWDEN Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SCU_RESET' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */\r
-#define SCU_RESET_RSTSTAT_RSTSTAT_Pos 0 /*!< SCU_RESET RSTSTAT: RSTSTAT Position */\r
-#define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0x000003ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /*!< SCU_RESET RSTSTAT: RSTSTAT Mask */\r
-#define SCU_RESET_RSTSTAT_LCKEN_Pos 10 /*!< SCU_RESET RSTSTAT: LCKEN Position */\r
-#define SCU_RESET_RSTSTAT_LCKEN_Msk (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos) /*!< SCU_RESET RSTSTAT: LCKEN Mask */\r
-\r
-/* ------------------------------ SCU_RESET_RSTSET ------------------------------ */\r
-#define SCU_RESET_RSTSET_LCKEN_Pos 10 /*!< SCU_RESET RSTSET: LCKEN Position */\r
-#define SCU_RESET_RSTSET_LCKEN_Msk (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos) /*!< SCU_RESET RSTSET: LCKEN Mask */\r
-\r
-/* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */\r
-#define SCU_RESET_RSTCLR_RSCLR_Pos 0 /*!< SCU_RESET RSTCLR: RSCLR Position */\r
-#define SCU_RESET_RSTCLR_RSCLR_Msk (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos) /*!< SCU_RESET RSTCLR: RSCLR Mask */\r
-#define SCU_RESET_RSTCLR_LCKEN_Pos 10 /*!< SCU_RESET RSTCLR: LCKEN Position */\r
-#define SCU_RESET_RSTCLR_LCKEN_Msk (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos) /*!< SCU_RESET RSTCLR: LCKEN Mask */\r
-\r
-/* ------------------------------ SCU_RESET_RSTCON ------------------------------ */\r
-#define SCU_RESET_RSTCON_ECCRSTEN_Pos 0 /*!< SCU_RESET RSTCON: ECCRSTEN Position */\r
-#define SCU_RESET_RSTCON_ECCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_ECCRSTEN_Pos) /*!< SCU_RESET RSTCON: ECCRSTEN Mask */\r
-#define SCU_RESET_RSTCON_LOCRSTEN_Pos 1 /*!< SCU_RESET RSTCON: LOCRSTEN Position */\r
-#define SCU_RESET_RSTCON_LOCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_LOCRSTEN_Pos) /*!< SCU_RESET RSTCON: LOCRSTEN Mask */\r
-#define SCU_RESET_RSTCON_SPERSTEN_Pos 2 /*!< SCU_RESET RSTCON: SPERSTEN Position */\r
-#define SCU_RESET_RSTCON_SPERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_SPERSTEN_Pos) /*!< SCU_RESET RSTCON: SPERSTEN Mask */\r
-#define SCU_RESET_RSTCON_U0PERSTEN_Pos 3 /*!< SCU_RESET RSTCON: U0PERSTEN Position */\r
-#define SCU_RESET_RSTCON_U0PERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_U0PERSTEN_Pos) /*!< SCU_RESET RSTCON: U0PERSTEN Mask */\r
-#define SCU_RESET_RSTCON_MRSTEN_Pos 16 /*!< SCU_RESET RSTCON: MRSTEN Position */\r
-#define SCU_RESET_RSTCON_MRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_MRSTEN_Pos) /*!< SCU_RESET RSTCON: MRSTEN Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'COMPARATOR' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------- COMPARATOR_ORCCTRL ----------------------------- */\r
-#define COMPARATOR_ORCCTRL_ENORC0_Pos 0 /*!< COMPARATOR ORCCTRL: ENORC0 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC0_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC0_Pos) /*!< COMPARATOR ORCCTRL: ENORC0 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC1_Pos 1 /*!< COMPARATOR ORCCTRL: ENORC1 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC1_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC1_Pos) /*!< COMPARATOR ORCCTRL: ENORC1 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC2_Pos 2 /*!< COMPARATOR ORCCTRL: ENORC2 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC2_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC2_Pos) /*!< COMPARATOR ORCCTRL: ENORC2 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC3_Pos 3 /*!< COMPARATOR ORCCTRL: ENORC3 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC3_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC3_Pos) /*!< COMPARATOR ORCCTRL: ENORC3 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC4_Pos 4 /*!< COMPARATOR ORCCTRL: ENORC4 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC4_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC4_Pos) /*!< COMPARATOR ORCCTRL: ENORC4 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC5_Pos 5 /*!< COMPARATOR ORCCTRL: ENORC5 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC5_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC5_Pos) /*!< COMPARATOR ORCCTRL: ENORC5 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC6_Pos 6 /*!< COMPARATOR ORCCTRL: ENORC6 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC6_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC6_Pos) /*!< COMPARATOR ORCCTRL: ENORC6 Mask */\r
-#define COMPARATOR_ORCCTRL_ENORC7_Pos 7 /*!< COMPARATOR ORCCTRL: ENORC7 Position */\r
-#define COMPARATOR_ORCCTRL_ENORC7_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC7_Pos) /*!< COMPARATOR ORCCTRL: ENORC7 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF0_Pos 16 /*!< COMPARATOR ORCCTRL: CNF0 Position */\r
-#define COMPARATOR_ORCCTRL_CNF0_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF0_Pos) /*!< COMPARATOR ORCCTRL: CNF0 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF1_Pos 17 /*!< COMPARATOR ORCCTRL: CNF1 Position */\r
-#define COMPARATOR_ORCCTRL_CNF1_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF1_Pos) /*!< COMPARATOR ORCCTRL: CNF1 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF2_Pos 18 /*!< COMPARATOR ORCCTRL: CNF2 Position */\r
-#define COMPARATOR_ORCCTRL_CNF2_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF2_Pos) /*!< COMPARATOR ORCCTRL: CNF2 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF3_Pos 19 /*!< COMPARATOR ORCCTRL: CNF3 Position */\r
-#define COMPARATOR_ORCCTRL_CNF3_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF3_Pos) /*!< COMPARATOR ORCCTRL: CNF3 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF4_Pos 20 /*!< COMPARATOR ORCCTRL: CNF4 Position */\r
-#define COMPARATOR_ORCCTRL_CNF4_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF4_Pos) /*!< COMPARATOR ORCCTRL: CNF4 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF5_Pos 21 /*!< COMPARATOR ORCCTRL: CNF5 Position */\r
-#define COMPARATOR_ORCCTRL_CNF5_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF5_Pos) /*!< COMPARATOR ORCCTRL: CNF5 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF6_Pos 22 /*!< COMPARATOR ORCCTRL: CNF6 Position */\r
-#define COMPARATOR_ORCCTRL_CNF6_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF6_Pos) /*!< COMPARATOR ORCCTRL: CNF6 Mask */\r
-#define COMPARATOR_ORCCTRL_CNF7_Pos 23 /*!< COMPARATOR ORCCTRL: CNF7 Position */\r
-#define COMPARATOR_ORCCTRL_CNF7_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF7_Pos) /*!< COMPARATOR ORCCTRL: CNF7 Mask */\r
-\r
-/* ----------------------------- COMPARATOR_ANACMP0 ----------------------------- */\r
-#define COMPARATOR_ANACMP0_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP0: CMP_EN Position */\r
-#define COMPARATOR_ANACMP0_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_EN_Pos) /*!< COMPARATOR ANACMP0: CMP_EN Mask */\r
-#define COMPARATOR_ANACMP0_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP0: CMP_FLT_OFF Position */\r
-#define COMPARATOR_ANACMP0_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP0: CMP_FLT_OFF Mask */\r
-#define COMPARATOR_ANACMP0_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP0: CMP_INV_OUT Position */\r
-#define COMPARATOR_ANACMP0_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP0: CMP_INV_OUT Mask */\r
-#define COMPARATOR_ANACMP0_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP0: CMP_HYST_ADJ Position */\r
-#define COMPARATOR_ANACMP0_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP0_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP0: CMP_HYST_ADJ Mask */\r
-#define COMPARATOR_ANACMP0_ACMP0_SEL_Pos 6 /*!< COMPARATOR ANACMP0: ACMP0_SEL Position */\r
-#define COMPARATOR_ANACMP0_ACMP0_SEL_Msk (0x01UL << COMPARATOR_ANACMP0_ACMP0_SEL_Pos) /*!< COMPARATOR ANACMP0: ACMP0_SEL Mask */\r
-#define COMPARATOR_ANACMP0_CMP_LPWR_Pos 8 /*!< COMPARATOR ANACMP0: CMP_LPWR Position */\r
-#define COMPARATOR_ANACMP0_CMP_LPWR_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_LPWR_Pos) /*!< COMPARATOR ANACMP0: CMP_LPWR Mask */\r
-#define COMPARATOR_ANACMP0_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP0: CMP_OUT Position */\r
-#define COMPARATOR_ANACMP0_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_OUT_Pos) /*!< COMPARATOR ANACMP0: CMP_OUT Mask */\r
-\r
-/* ----------------------------- COMPARATOR_ANACMP1 ----------------------------- */\r
-#define COMPARATOR_ANACMP1_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP1: CMP_EN Position */\r
-#define COMPARATOR_ANACMP1_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_EN_Pos) /*!< COMPARATOR ANACMP1: CMP_EN Mask */\r
-#define COMPARATOR_ANACMP1_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP1: CMP_FLT_OFF Position */\r
-#define COMPARATOR_ANACMP1_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP1: CMP_FLT_OFF Mask */\r
-#define COMPARATOR_ANACMP1_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP1: CMP_INV_OUT Position */\r
-#define COMPARATOR_ANACMP1_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP1: CMP_INV_OUT Mask */\r
-#define COMPARATOR_ANACMP1_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP1: CMP_HYST_ADJ Position */\r
-#define COMPARATOR_ANACMP1_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP1_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP1: CMP_HYST_ADJ Mask */\r
-#define COMPARATOR_ANACMP1_REF_DIV_EN_Pos 6 /*!< COMPARATOR ANACMP1: REF_DIV_EN Position */\r
-#define COMPARATOR_ANACMP1_REF_DIV_EN_Msk (0x01UL << COMPARATOR_ANACMP1_REF_DIV_EN_Pos) /*!< COMPARATOR ANACMP1: REF_DIV_EN Mask */\r
-#define COMPARATOR_ANACMP1_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP1: CMP_OUT Position */\r
-#define COMPARATOR_ANACMP1_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_OUT_Pos) /*!< COMPARATOR ANACMP1: CMP_OUT Mask */\r
-\r
-/* ----------------------------- COMPARATOR_ANACMP2 ----------------------------- */\r
-#define COMPARATOR_ANACMP2_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP2: CMP_EN Position */\r
-#define COMPARATOR_ANACMP2_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_EN_Pos) /*!< COMPARATOR ANACMP2: CMP_EN Mask */\r
-#define COMPARATOR_ANACMP2_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP2: CMP_FLT_OFF Position */\r
-#define COMPARATOR_ANACMP2_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP2: CMP_FLT_OFF Mask */\r
-#define COMPARATOR_ANACMP2_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP2: CMP_INV_OUT Position */\r
-#define COMPARATOR_ANACMP2_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP2: CMP_INV_OUT Mask */\r
-#define COMPARATOR_ANACMP2_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP2: CMP_HYST_ADJ Position */\r
-#define COMPARATOR_ANACMP2_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP2_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP2: CMP_HYST_ADJ Mask */\r
-#define COMPARATOR_ANACMP2_ACMP2_SEL_Pos 6 /*!< COMPARATOR ANACMP2: ACMP2_SEL Position */\r
-#define COMPARATOR_ANACMP2_ACMP2_SEL_Msk (0x01UL << COMPARATOR_ANACMP2_ACMP2_SEL_Pos) /*!< COMPARATOR ANACMP2: ACMP2_SEL Mask */\r
-#define COMPARATOR_ANACMP2_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP2: CMP_OUT Position */\r
-#define COMPARATOR_ANACMP2_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_OUT_Pos) /*!< COMPARATOR ANACMP2: CMP_OUT Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'SCU_ANALOG' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------- SCU_ANALOG_ANATSECTRL --------------------------- */\r
-#define SCU_ANALOG_ANATSECTRL_TSE_EN_Pos 0 /*!< SCU_ANALOG ANATSECTRL: TSE_EN Position */\r
-#define SCU_ANALOG_ANATSECTRL_TSE_EN_Msk (0x01UL << SCU_ANALOG_ANATSECTRL_TSE_EN_Pos) /*!< SCU_ANALOG ANATSECTRL: TSE_EN Mask */\r
-\r
-/* ----------------------------- SCU_ANALOG_ANATSEIH ---------------------------- */\r
-#define SCU_ANALOG_ANATSEIH_TSE_IH_Pos 0 /*!< SCU_ANALOG ANATSEIH: TSE_IH Position */\r
-#define SCU_ANALOG_ANATSEIH_TSE_IH_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEIH_TSE_IH_Pos) /*!< SCU_ANALOG ANATSEIH: TSE_IH Mask */\r
-\r
-/* ----------------------------- SCU_ANALOG_ANATSEIL ---------------------------- */\r
-#define SCU_ANALOG_ANATSEIL_TSE_IL_Pos 0 /*!< SCU_ANALOG ANATSEIL: TSE_IL Position */\r
-#define SCU_ANALOG_ANATSEIL_TSE_IL_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEIL_TSE_IL_Pos) /*!< SCU_ANALOG ANATSEIL: TSE_IL Mask */\r
-\r
-/* ---------------------------- SCU_ANALOG_ANATSEMON ---------------------------- */\r
-#define SCU_ANALOG_ANATSEMON_TSE_MON_Pos 0 /*!< SCU_ANALOG ANATSEMON: TSE_MON Position */\r
-#define SCU_ANALOG_ANATSEMON_TSE_MON_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEMON_TSE_MON_Pos) /*!< SCU_ANALOG ANATSEMON: TSE_MON Mask */\r
-\r
-/* ----------------------------- SCU_ANALOG_ANAVDEL ----------------------------- */\r
-#define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos 0 /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Position */\r
-#define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Mask */\r
-#define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos 2 /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Position */\r
-#define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Mask */\r
-#define SCU_ANALOG_ANAVDEL_VDEL_EN_Pos 4 /*!< SCU_ANALOG ANAVDEL: VDEL_EN Position */\r
-#define SCU_ANALOG_ANAVDEL_VDEL_EN_Msk (0x01UL << SCU_ANALOG_ANAVDEL_VDEL_EN_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_EN Mask */\r
-\r
-/* ---------------------------- SCU_ANALOG_ANAOFFSET ---------------------------- */\r
-#define SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Pos 0 /*!< SCU_ANALOG ANAOFFSET: ADJL_OFFSET Position */\r
-#define SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Msk (0x0fUL << SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Pos) /*!< SCU_ANALOG ANAOFFSET: ADJL_OFFSET Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'CCU4' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- CCU4_GCTRL --------------------------------- */\r
-#define CCU4_GCTRL_PRBC_Pos 0 /*!< CCU4 GCTRL: PRBC Position */\r
-#define CCU4_GCTRL_PRBC_Msk (0x07UL << CCU4_GCTRL_PRBC_Pos) /*!< CCU4 GCTRL: PRBC Mask */\r
-#define CCU4_GCTRL_PCIS_Pos 4 /*!< CCU4 GCTRL: PCIS Position */\r
-#define CCU4_GCTRL_PCIS_Msk (0x03UL << CCU4_GCTRL_PCIS_Pos) /*!< CCU4 GCTRL: PCIS Mask */\r
-#define CCU4_GCTRL_SUSCFG_Pos 8 /*!< CCU4 GCTRL: SUSCFG Position */\r
-#define CCU4_GCTRL_SUSCFG_Msk (0x03UL << CCU4_GCTRL_SUSCFG_Pos) /*!< CCU4 GCTRL: SUSCFG Mask */\r
-#define CCU4_GCTRL_MSE0_Pos 10 /*!< CCU4 GCTRL: MSE0 Position */\r
-#define CCU4_GCTRL_MSE0_Msk (0x01UL << CCU4_GCTRL_MSE0_Pos) /*!< CCU4 GCTRL: MSE0 Mask */\r
-#define CCU4_GCTRL_MSE1_Pos 11 /*!< CCU4 GCTRL: MSE1 Position */\r
-#define CCU4_GCTRL_MSE1_Msk (0x01UL << CCU4_GCTRL_MSE1_Pos) /*!< CCU4 GCTRL: MSE1 Mask */\r
-#define CCU4_GCTRL_MSE2_Pos 12 /*!< CCU4 GCTRL: MSE2 Position */\r
-#define CCU4_GCTRL_MSE2_Msk (0x01UL << CCU4_GCTRL_MSE2_Pos) /*!< CCU4 GCTRL: MSE2 Mask */\r
-#define CCU4_GCTRL_MSE3_Pos 13 /*!< CCU4 GCTRL: MSE3 Position */\r
-#define CCU4_GCTRL_MSE3_Msk (0x01UL << CCU4_GCTRL_MSE3_Pos) /*!< CCU4 GCTRL: MSE3 Mask */\r
-#define CCU4_GCTRL_MSDE_Pos 14 /*!< CCU4 GCTRL: MSDE Position */\r
-#define CCU4_GCTRL_MSDE_Msk (0x03UL << CCU4_GCTRL_MSDE_Pos) /*!< CCU4 GCTRL: MSDE Mask */\r
-\r
-/* --------------------------------- CCU4_GSTAT --------------------------------- */\r
-#define CCU4_GSTAT_S0I_Pos 0 /*!< CCU4 GSTAT: S0I Position */\r
-#define CCU4_GSTAT_S0I_Msk (0x01UL << CCU4_GSTAT_S0I_Pos) /*!< CCU4 GSTAT: S0I Mask */\r
-#define CCU4_GSTAT_S1I_Pos 1 /*!< CCU4 GSTAT: S1I Position */\r
-#define CCU4_GSTAT_S1I_Msk (0x01UL << CCU4_GSTAT_S1I_Pos) /*!< CCU4 GSTAT: S1I Mask */\r
-#define CCU4_GSTAT_S2I_Pos 2 /*!< CCU4 GSTAT: S2I Position */\r
-#define CCU4_GSTAT_S2I_Msk (0x01UL << CCU4_GSTAT_S2I_Pos) /*!< CCU4 GSTAT: S2I Mask */\r
-#define CCU4_GSTAT_S3I_Pos 3 /*!< CCU4 GSTAT: S3I Position */\r
-#define CCU4_GSTAT_S3I_Msk (0x01UL << CCU4_GSTAT_S3I_Pos) /*!< CCU4 GSTAT: S3I Mask */\r
-#define CCU4_GSTAT_PRB_Pos 8 /*!< CCU4 GSTAT: PRB Position */\r
-#define CCU4_GSTAT_PRB_Msk (0x01UL << CCU4_GSTAT_PRB_Pos) /*!< CCU4 GSTAT: PRB Mask */\r
-\r
-/* --------------------------------- CCU4_GIDLS --------------------------------- */\r
-#define CCU4_GIDLS_SS0I_Pos 0 /*!< CCU4 GIDLS: SS0I Position */\r
-#define CCU4_GIDLS_SS0I_Msk (0x01UL << CCU4_GIDLS_SS0I_Pos) /*!< CCU4 GIDLS: SS0I Mask */\r
-#define CCU4_GIDLS_SS1I_Pos 1 /*!< CCU4 GIDLS: SS1I Position */\r
-#define CCU4_GIDLS_SS1I_Msk (0x01UL << CCU4_GIDLS_SS1I_Pos) /*!< CCU4 GIDLS: SS1I Mask */\r
-#define CCU4_GIDLS_SS2I_Pos 2 /*!< CCU4 GIDLS: SS2I Position */\r
-#define CCU4_GIDLS_SS2I_Msk (0x01UL << CCU4_GIDLS_SS2I_Pos) /*!< CCU4 GIDLS: SS2I Mask */\r
-#define CCU4_GIDLS_SS3I_Pos 3 /*!< CCU4 GIDLS: SS3I Position */\r
-#define CCU4_GIDLS_SS3I_Msk (0x01UL << CCU4_GIDLS_SS3I_Pos) /*!< CCU4 GIDLS: SS3I Mask */\r
-#define CCU4_GIDLS_CPRB_Pos 8 /*!< CCU4 GIDLS: CPRB Position */\r
-#define CCU4_GIDLS_CPRB_Msk (0x01UL << CCU4_GIDLS_CPRB_Pos) /*!< CCU4 GIDLS: CPRB Mask */\r
-#define CCU4_GIDLS_PSIC_Pos 9 /*!< CCU4 GIDLS: PSIC Position */\r
-#define CCU4_GIDLS_PSIC_Msk (0x01UL << CCU4_GIDLS_PSIC_Pos) /*!< CCU4 GIDLS: PSIC Mask */\r
-\r
-/* --------------------------------- CCU4_GIDLC --------------------------------- */\r
-#define CCU4_GIDLC_CS0I_Pos 0 /*!< CCU4 GIDLC: CS0I Position */\r
-#define CCU4_GIDLC_CS0I_Msk (0x01UL << CCU4_GIDLC_CS0I_Pos) /*!< CCU4 GIDLC: CS0I Mask */\r
-#define CCU4_GIDLC_CS1I_Pos 1 /*!< CCU4 GIDLC: CS1I Position */\r
-#define CCU4_GIDLC_CS1I_Msk (0x01UL << CCU4_GIDLC_CS1I_Pos) /*!< CCU4 GIDLC: CS1I Mask */\r
-#define CCU4_GIDLC_CS2I_Pos 2 /*!< CCU4 GIDLC: CS2I Position */\r
-#define CCU4_GIDLC_CS2I_Msk (0x01UL << CCU4_GIDLC_CS2I_Pos) /*!< CCU4 GIDLC: CS2I Mask */\r
-#define CCU4_GIDLC_CS3I_Pos 3 /*!< CCU4 GIDLC: CS3I Position */\r
-#define CCU4_GIDLC_CS3I_Msk (0x01UL << CCU4_GIDLC_CS3I_Pos) /*!< CCU4 GIDLC: CS3I Mask */\r
-#define CCU4_GIDLC_SPRB_Pos 8 /*!< CCU4 GIDLC: SPRB Position */\r
-#define CCU4_GIDLC_SPRB_Msk (0x01UL << CCU4_GIDLC_SPRB_Pos) /*!< CCU4 GIDLC: SPRB Mask */\r
-\r
-/* ---------------------------------- CCU4_GCSS --------------------------------- */\r
-#define CCU4_GCSS_S0SE_Pos 0 /*!< CCU4 GCSS: S0SE Position */\r
-#define CCU4_GCSS_S0SE_Msk (0x01UL << CCU4_GCSS_S0SE_Pos) /*!< CCU4 GCSS: S0SE Mask */\r
-#define CCU4_GCSS_S0DSE_Pos 1 /*!< CCU4 GCSS: S0DSE Position */\r
-#define CCU4_GCSS_S0DSE_Msk (0x01UL << CCU4_GCSS_S0DSE_Pos) /*!< CCU4 GCSS: S0DSE Mask */\r
-#define CCU4_GCSS_S0PSE_Pos 2 /*!< CCU4 GCSS: S0PSE Position */\r
-#define CCU4_GCSS_S0PSE_Msk (0x01UL << CCU4_GCSS_S0PSE_Pos) /*!< CCU4 GCSS: S0PSE Mask */\r
-#define CCU4_GCSS_S1SE_Pos 4 /*!< CCU4 GCSS: S1SE Position */\r
-#define CCU4_GCSS_S1SE_Msk (0x01UL << CCU4_GCSS_S1SE_Pos) /*!< CCU4 GCSS: S1SE Mask */\r
-#define CCU4_GCSS_S1DSE_Pos 5 /*!< CCU4 GCSS: S1DSE Position */\r
-#define CCU4_GCSS_S1DSE_Msk (0x01UL << CCU4_GCSS_S1DSE_Pos) /*!< CCU4 GCSS: S1DSE Mask */\r
-#define CCU4_GCSS_S1PSE_Pos 6 /*!< CCU4 GCSS: S1PSE Position */\r
-#define CCU4_GCSS_S1PSE_Msk (0x01UL << CCU4_GCSS_S1PSE_Pos) /*!< CCU4 GCSS: S1PSE Mask */\r
-#define CCU4_GCSS_S2SE_Pos 8 /*!< CCU4 GCSS: S2SE Position */\r
-#define CCU4_GCSS_S2SE_Msk (0x01UL << CCU4_GCSS_S2SE_Pos) /*!< CCU4 GCSS: S2SE Mask */\r
-#define CCU4_GCSS_S2DSE_Pos 9 /*!< CCU4 GCSS: S2DSE Position */\r
-#define CCU4_GCSS_S2DSE_Msk (0x01UL << CCU4_GCSS_S2DSE_Pos) /*!< CCU4 GCSS: S2DSE Mask */\r
-#define CCU4_GCSS_S2PSE_Pos 10 /*!< CCU4 GCSS: S2PSE Position */\r
-#define CCU4_GCSS_S2PSE_Msk (0x01UL << CCU4_GCSS_S2PSE_Pos) /*!< CCU4 GCSS: S2PSE Mask */\r
-#define CCU4_GCSS_S3SE_Pos 12 /*!< CCU4 GCSS: S3SE Position */\r
-#define CCU4_GCSS_S3SE_Msk (0x01UL << CCU4_GCSS_S3SE_Pos) /*!< CCU4 GCSS: S3SE Mask */\r
-#define CCU4_GCSS_S3DSE_Pos 13 /*!< CCU4 GCSS: S3DSE Position */\r
-#define CCU4_GCSS_S3DSE_Msk (0x01UL << CCU4_GCSS_S3DSE_Pos) /*!< CCU4 GCSS: S3DSE Mask */\r
-#define CCU4_GCSS_S3PSE_Pos 14 /*!< CCU4 GCSS: S3PSE Position */\r
-#define CCU4_GCSS_S3PSE_Msk (0x01UL << CCU4_GCSS_S3PSE_Pos) /*!< CCU4 GCSS: S3PSE Mask */\r
-#define CCU4_GCSS_S0STS_Pos 16 /*!< CCU4 GCSS: S0STS Position */\r
-#define CCU4_GCSS_S0STS_Msk (0x01UL << CCU4_GCSS_S0STS_Pos) /*!< CCU4 GCSS: S0STS Mask */\r
-#define CCU4_GCSS_S1STS_Pos 17 /*!< CCU4 GCSS: S1STS Position */\r
-#define CCU4_GCSS_S1STS_Msk (0x01UL << CCU4_GCSS_S1STS_Pos) /*!< CCU4 GCSS: S1STS Mask */\r
-#define CCU4_GCSS_S2STS_Pos 18 /*!< CCU4 GCSS: S2STS Position */\r
-#define CCU4_GCSS_S2STS_Msk (0x01UL << CCU4_GCSS_S2STS_Pos) /*!< CCU4 GCSS: S2STS Mask */\r
-#define CCU4_GCSS_S3STS_Pos 19 /*!< CCU4 GCSS: S3STS Position */\r
-#define CCU4_GCSS_S3STS_Msk (0x01UL << CCU4_GCSS_S3STS_Pos) /*!< CCU4 GCSS: S3STS Mask */\r
-\r
-/* ---------------------------------- CCU4_GCSC --------------------------------- */\r
-#define CCU4_GCSC_S0SC_Pos 0 /*!< CCU4 GCSC: S0SC Position */\r
-#define CCU4_GCSC_S0SC_Msk (0x01UL << CCU4_GCSC_S0SC_Pos) /*!< CCU4 GCSC: S0SC Mask */\r
-#define CCU4_GCSC_S0DSC_Pos 1 /*!< CCU4 GCSC: S0DSC Position */\r
-#define CCU4_GCSC_S0DSC_Msk (0x01UL << CCU4_GCSC_S0DSC_Pos) /*!< CCU4 GCSC: S0DSC Mask */\r
-#define CCU4_GCSC_S0PSC_Pos 2 /*!< CCU4 GCSC: S0PSC Position */\r
-#define CCU4_GCSC_S0PSC_Msk (0x01UL << CCU4_GCSC_S0PSC_Pos) /*!< CCU4 GCSC: S0PSC Mask */\r
-#define CCU4_GCSC_S1SC_Pos 4 /*!< CCU4 GCSC: S1SC Position */\r
-#define CCU4_GCSC_S1SC_Msk (0x01UL << CCU4_GCSC_S1SC_Pos) /*!< CCU4 GCSC: S1SC Mask */\r
-#define CCU4_GCSC_S1DSC_Pos 5 /*!< CCU4 GCSC: S1DSC Position */\r
-#define CCU4_GCSC_S1DSC_Msk (0x01UL << CCU4_GCSC_S1DSC_Pos) /*!< CCU4 GCSC: S1DSC Mask */\r
-#define CCU4_GCSC_S1PSC_Pos 6 /*!< CCU4 GCSC: S1PSC Position */\r
-#define CCU4_GCSC_S1PSC_Msk (0x01UL << CCU4_GCSC_S1PSC_Pos) /*!< CCU4 GCSC: S1PSC Mask */\r
-#define CCU4_GCSC_S2SC_Pos 8 /*!< CCU4 GCSC: S2SC Position */\r
-#define CCU4_GCSC_S2SC_Msk (0x01UL << CCU4_GCSC_S2SC_Pos) /*!< CCU4 GCSC: S2SC Mask */\r
-#define CCU4_GCSC_S2DSC_Pos 9 /*!< CCU4 GCSC: S2DSC Position */\r
-#define CCU4_GCSC_S2DSC_Msk (0x01UL << CCU4_GCSC_S2DSC_Pos) /*!< CCU4 GCSC: S2DSC Mask */\r
-#define CCU4_GCSC_S2PSC_Pos 10 /*!< CCU4 GCSC: S2PSC Position */\r
-#define CCU4_GCSC_S2PSC_Msk (0x01UL << CCU4_GCSC_S2PSC_Pos) /*!< CCU4 GCSC: S2PSC Mask */\r
-#define CCU4_GCSC_S3SC_Pos 12 /*!< CCU4 GCSC: S3SC Position */\r
-#define CCU4_GCSC_S3SC_Msk (0x01UL << CCU4_GCSC_S3SC_Pos) /*!< CCU4 GCSC: S3SC Mask */\r
-#define CCU4_GCSC_S3DSC_Pos 13 /*!< CCU4 GCSC: S3DSC Position */\r
-#define CCU4_GCSC_S3DSC_Msk (0x01UL << CCU4_GCSC_S3DSC_Pos) /*!< CCU4 GCSC: S3DSC Mask */\r
-#define CCU4_GCSC_S3PSC_Pos 14 /*!< CCU4 GCSC: S3PSC Position */\r
-#define CCU4_GCSC_S3PSC_Msk (0x01UL << CCU4_GCSC_S3PSC_Pos) /*!< CCU4 GCSC: S3PSC Mask */\r
-#define CCU4_GCSC_S0STC_Pos 16 /*!< CCU4 GCSC: S0STC Position */\r
-#define CCU4_GCSC_S0STC_Msk (0x01UL << CCU4_GCSC_S0STC_Pos) /*!< CCU4 GCSC: S0STC Mask */\r
-#define CCU4_GCSC_S1STC_Pos 17 /*!< CCU4 GCSC: S1STC Position */\r
-#define CCU4_GCSC_S1STC_Msk (0x01UL << CCU4_GCSC_S1STC_Pos) /*!< CCU4 GCSC: S1STC Mask */\r
-#define CCU4_GCSC_S2STC_Pos 18 /*!< CCU4 GCSC: S2STC Position */\r
-#define CCU4_GCSC_S2STC_Msk (0x01UL << CCU4_GCSC_S2STC_Pos) /*!< CCU4 GCSC: S2STC Mask */\r
-#define CCU4_GCSC_S3STC_Pos 19 /*!< CCU4 GCSC: S3STC Position */\r
-#define CCU4_GCSC_S3STC_Msk (0x01UL << CCU4_GCSC_S3STC_Pos) /*!< CCU4 GCSC: S3STC Mask */\r
-\r
-/* ---------------------------------- CCU4_GCST --------------------------------- */\r
-#define CCU4_GCST_S0SS_Pos 0 /*!< CCU4 GCST: S0SS Position */\r
-#define CCU4_GCST_S0SS_Msk (0x01UL << CCU4_GCST_S0SS_Pos) /*!< CCU4 GCST: S0SS Mask */\r
-#define CCU4_GCST_S0DSS_Pos 1 /*!< CCU4 GCST: S0DSS Position */\r
-#define CCU4_GCST_S0DSS_Msk (0x01UL << CCU4_GCST_S0DSS_Pos) /*!< CCU4 GCST: S0DSS Mask */\r
-#define CCU4_GCST_S0PSS_Pos 2 /*!< CCU4 GCST: S0PSS Position */\r
-#define CCU4_GCST_S0PSS_Msk (0x01UL << CCU4_GCST_S0PSS_Pos) /*!< CCU4 GCST: S0PSS Mask */\r
-#define CCU4_GCST_S1SS_Pos 4 /*!< CCU4 GCST: S1SS Position */\r
-#define CCU4_GCST_S1SS_Msk (0x01UL << CCU4_GCST_S1SS_Pos) /*!< CCU4 GCST: S1SS Mask */\r
-#define CCU4_GCST_S1DSS_Pos 5 /*!< CCU4 GCST: S1DSS Position */\r
-#define CCU4_GCST_S1DSS_Msk (0x01UL << CCU4_GCST_S1DSS_Pos) /*!< CCU4 GCST: S1DSS Mask */\r
-#define CCU4_GCST_S1PSS_Pos 6 /*!< CCU4 GCST: S1PSS Position */\r
-#define CCU4_GCST_S1PSS_Msk (0x01UL << CCU4_GCST_S1PSS_Pos) /*!< CCU4 GCST: S1PSS Mask */\r
-#define CCU4_GCST_S2SS_Pos 8 /*!< CCU4 GCST: S2SS Position */\r
-#define CCU4_GCST_S2SS_Msk (0x01UL << CCU4_GCST_S2SS_Pos) /*!< CCU4 GCST: S2SS Mask */\r
-#define CCU4_GCST_S2DSS_Pos 9 /*!< CCU4 GCST: S2DSS Position */\r
-#define CCU4_GCST_S2DSS_Msk (0x01UL << CCU4_GCST_S2DSS_Pos) /*!< CCU4 GCST: S2DSS Mask */\r
-#define CCU4_GCST_S2PSS_Pos 10 /*!< CCU4 GCST: S2PSS Position */\r
-#define CCU4_GCST_S2PSS_Msk (0x01UL << CCU4_GCST_S2PSS_Pos) /*!< CCU4 GCST: S2PSS Mask */\r
-#define CCU4_GCST_S3SS_Pos 12 /*!< CCU4 GCST: S3SS Position */\r
-#define CCU4_GCST_S3SS_Msk (0x01UL << CCU4_GCST_S3SS_Pos) /*!< CCU4 GCST: S3SS Mask */\r
-#define CCU4_GCST_S3DSS_Pos 13 /*!< CCU4 GCST: S3DSS Position */\r
-#define CCU4_GCST_S3DSS_Msk (0x01UL << CCU4_GCST_S3DSS_Pos) /*!< CCU4 GCST: S3DSS Mask */\r
-#define CCU4_GCST_S3PSS_Pos 14 /*!< CCU4 GCST: S3PSS Position */\r
-#define CCU4_GCST_S3PSS_Msk (0x01UL << CCU4_GCST_S3PSS_Pos) /*!< CCU4 GCST: S3PSS Mask */\r
-#define CCU4_GCST_CC40ST_Pos 16 /*!< CCU4 GCST: CC40ST Position */\r
-#define CCU4_GCST_CC40ST_Msk (0x01UL << CCU4_GCST_CC40ST_Pos) /*!< CCU4 GCST: CC40ST Mask */\r
-#define CCU4_GCST_CC41ST_Pos 17 /*!< CCU4 GCST: CC41ST Position */\r
-#define CCU4_GCST_CC41ST_Msk (0x01UL << CCU4_GCST_CC41ST_Pos) /*!< CCU4 GCST: CC41ST Mask */\r
-#define CCU4_GCST_CC42ST_Pos 18 /*!< CCU4 GCST: CC42ST Position */\r
-#define CCU4_GCST_CC42ST_Msk (0x01UL << CCU4_GCST_CC42ST_Pos) /*!< CCU4 GCST: CC42ST Mask */\r
-#define CCU4_GCST_CC43ST_Pos 19 /*!< CCU4 GCST: CC43ST Position */\r
-#define CCU4_GCST_CC43ST_Msk (0x01UL << CCU4_GCST_CC43ST_Pos) /*!< CCU4 GCST: CC43ST Mask */\r
-\r
-/* ---------------------------------- CCU4_MIDR --------------------------------- */\r
-#define CCU4_MIDR_MODR_Pos 0 /*!< CCU4 MIDR: MODR Position */\r
-#define CCU4_MIDR_MODR_Msk (0x000000ffUL << CCU4_MIDR_MODR_Pos) /*!< CCU4 MIDR: MODR Mask */\r
-#define CCU4_MIDR_MODT_Pos 8 /*!< CCU4 MIDR: MODT Position */\r
-#define CCU4_MIDR_MODT_Msk (0x000000ffUL << CCU4_MIDR_MODT_Pos) /*!< CCU4 MIDR: MODT Mask */\r
-#define CCU4_MIDR_MODN_Pos 16 /*!< CCU4 MIDR: MODN Position */\r
-#define CCU4_MIDR_MODN_Msk (0x0000ffffUL << CCU4_MIDR_MODN_Pos) /*!< CCU4 MIDR: MODN Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'CCU4_CC4' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- CCU4_CC4_INS -------------------------------- */\r
-#define CCU4_CC4_INS_EV0IS_Pos 0 /*!< CCU4_CC4 INS: EV0IS Position */\r
-#define CCU4_CC4_INS_EV0IS_Msk (0x0fUL << CCU4_CC4_INS_EV0IS_Pos) /*!< CCU4_CC4 INS: EV0IS Mask */\r
-#define CCU4_CC4_INS_EV1IS_Pos 4 /*!< CCU4_CC4 INS: EV1IS Position */\r
-#define CCU4_CC4_INS_EV1IS_Msk (0x0fUL << CCU4_CC4_INS_EV1IS_Pos) /*!< CCU4_CC4 INS: EV1IS Mask */\r
-#define CCU4_CC4_INS_EV2IS_Pos 8 /*!< CCU4_CC4 INS: EV2IS Position */\r
-#define CCU4_CC4_INS_EV2IS_Msk (0x0fUL << CCU4_CC4_INS_EV2IS_Pos) /*!< CCU4_CC4 INS: EV2IS Mask */\r
-#define CCU4_CC4_INS_EV0EM_Pos 16 /*!< CCU4_CC4 INS: EV0EM Position */\r
-#define CCU4_CC4_INS_EV0EM_Msk (0x03UL << CCU4_CC4_INS_EV0EM_Pos) /*!< CCU4_CC4 INS: EV0EM Mask */\r
-#define CCU4_CC4_INS_EV1EM_Pos 18 /*!< CCU4_CC4 INS: EV1EM Position */\r
-#define CCU4_CC4_INS_EV1EM_Msk (0x03UL << CCU4_CC4_INS_EV1EM_Pos) /*!< CCU4_CC4 INS: EV1EM Mask */\r
-#define CCU4_CC4_INS_EV2EM_Pos 20 /*!< CCU4_CC4 INS: EV2EM Position */\r
-#define CCU4_CC4_INS_EV2EM_Msk (0x03UL << CCU4_CC4_INS_EV2EM_Pos) /*!< CCU4_CC4 INS: EV2EM Mask */\r
-#define CCU4_CC4_INS_EV0LM_Pos 22 /*!< CCU4_CC4 INS: EV0LM Position */\r
-#define CCU4_CC4_INS_EV0LM_Msk (0x01UL << CCU4_CC4_INS_EV0LM_Pos) /*!< CCU4_CC4 INS: EV0LM Mask */\r
-#define CCU4_CC4_INS_EV1LM_Pos 23 /*!< CCU4_CC4 INS: EV1LM Position */\r
-#define CCU4_CC4_INS_EV1LM_Msk (0x01UL << CCU4_CC4_INS_EV1LM_Pos) /*!< CCU4_CC4 INS: EV1LM Mask */\r
-#define CCU4_CC4_INS_EV2LM_Pos 24 /*!< CCU4_CC4 INS: EV2LM Position */\r
-#define CCU4_CC4_INS_EV2LM_Msk (0x01UL << CCU4_CC4_INS_EV2LM_Pos) /*!< CCU4_CC4 INS: EV2LM Mask */\r
-#define CCU4_CC4_INS_LPF0M_Pos 25 /*!< CCU4_CC4 INS: LPF0M Position */\r
-#define CCU4_CC4_INS_LPF0M_Msk (0x03UL << CCU4_CC4_INS_LPF0M_Pos) /*!< CCU4_CC4 INS: LPF0M Mask */\r
-#define CCU4_CC4_INS_LPF1M_Pos 27 /*!< CCU4_CC4 INS: LPF1M Position */\r
-#define CCU4_CC4_INS_LPF1M_Msk (0x03UL << CCU4_CC4_INS_LPF1M_Pos) /*!< CCU4_CC4 INS: LPF1M Mask */\r
-#define CCU4_CC4_INS_LPF2M_Pos 29 /*!< CCU4_CC4 INS: LPF2M Position */\r
-#define CCU4_CC4_INS_LPF2M_Msk (0x03UL << CCU4_CC4_INS_LPF2M_Pos) /*!< CCU4_CC4 INS: LPF2M Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_CMC -------------------------------- */\r
-#define CCU4_CC4_CMC_STRTS_Pos 0 /*!< CCU4_CC4 CMC: STRTS Position */\r
-#define CCU4_CC4_CMC_STRTS_Msk (0x03UL << CCU4_CC4_CMC_STRTS_Pos) /*!< CCU4_CC4 CMC: STRTS Mask */\r
-#define CCU4_CC4_CMC_ENDS_Pos 2 /*!< CCU4_CC4 CMC: ENDS Position */\r
-#define CCU4_CC4_CMC_ENDS_Msk (0x03UL << CCU4_CC4_CMC_ENDS_Pos) /*!< CCU4_CC4 CMC: ENDS Mask */\r
-#define CCU4_CC4_CMC_CAP0S_Pos 4 /*!< CCU4_CC4 CMC: CAP0S Position */\r
-#define CCU4_CC4_CMC_CAP0S_Msk (0x03UL << CCU4_CC4_CMC_CAP0S_Pos) /*!< CCU4_CC4 CMC: CAP0S Mask */\r
-#define CCU4_CC4_CMC_CAP1S_Pos 6 /*!< CCU4_CC4 CMC: CAP1S Position */\r
-#define CCU4_CC4_CMC_CAP1S_Msk (0x03UL << CCU4_CC4_CMC_CAP1S_Pos) /*!< CCU4_CC4 CMC: CAP1S Mask */\r
-#define CCU4_CC4_CMC_GATES_Pos 8 /*!< CCU4_CC4 CMC: GATES Position */\r
-#define CCU4_CC4_CMC_GATES_Msk (0x03UL << CCU4_CC4_CMC_GATES_Pos) /*!< CCU4_CC4 CMC: GATES Mask */\r
-#define CCU4_CC4_CMC_UDS_Pos 10 /*!< CCU4_CC4 CMC: UDS Position */\r
-#define CCU4_CC4_CMC_UDS_Msk (0x03UL << CCU4_CC4_CMC_UDS_Pos) /*!< CCU4_CC4 CMC: UDS Mask */\r
-#define CCU4_CC4_CMC_LDS_Pos 12 /*!< CCU4_CC4 CMC: LDS Position */\r
-#define CCU4_CC4_CMC_LDS_Msk (0x03UL << CCU4_CC4_CMC_LDS_Pos) /*!< CCU4_CC4 CMC: LDS Mask */\r
-#define CCU4_CC4_CMC_CNTS_Pos 14 /*!< CCU4_CC4 CMC: CNTS Position */\r
-#define CCU4_CC4_CMC_CNTS_Msk (0x03UL << CCU4_CC4_CMC_CNTS_Pos) /*!< CCU4_CC4 CMC: CNTS Mask */\r
-#define CCU4_CC4_CMC_OFS_Pos 16 /*!< CCU4_CC4 CMC: OFS Position */\r
-#define CCU4_CC4_CMC_OFS_Msk (0x01UL << CCU4_CC4_CMC_OFS_Pos) /*!< CCU4_CC4 CMC: OFS Mask */\r
-#define CCU4_CC4_CMC_TS_Pos 17 /*!< CCU4_CC4 CMC: TS Position */\r
-#define CCU4_CC4_CMC_TS_Msk (0x01UL << CCU4_CC4_CMC_TS_Pos) /*!< CCU4_CC4 CMC: TS Mask */\r
-#define CCU4_CC4_CMC_MOS_Pos 18 /*!< CCU4_CC4 CMC: MOS Position */\r
-#define CCU4_CC4_CMC_MOS_Msk (0x03UL << CCU4_CC4_CMC_MOS_Pos) /*!< CCU4_CC4 CMC: MOS Mask */\r
-#define CCU4_CC4_CMC_TCE_Pos 20 /*!< CCU4_CC4 CMC: TCE Position */\r
-#define CCU4_CC4_CMC_TCE_Msk (0x01UL << CCU4_CC4_CMC_TCE_Pos) /*!< CCU4_CC4 CMC: TCE Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_TCST ------------------------------- */\r
-#define CCU4_CC4_TCST_TRB_Pos 0 /*!< CCU4_CC4 TCST: TRB Position */\r
-#define CCU4_CC4_TCST_TRB_Msk (0x01UL << CCU4_CC4_TCST_TRB_Pos) /*!< CCU4_CC4 TCST: TRB Mask */\r
-#define CCU4_CC4_TCST_CDIR_Pos 1 /*!< CCU4_CC4 TCST: CDIR Position */\r
-#define CCU4_CC4_TCST_CDIR_Msk (0x01UL << CCU4_CC4_TCST_CDIR_Pos) /*!< CCU4_CC4 TCST: CDIR Mask */\r
-\r
-/* ------------------------------- CCU4_CC4_TCSET ------------------------------- */\r
-#define CCU4_CC4_TCSET_TRBS_Pos 0 /*!< CCU4_CC4 TCSET: TRBS Position */\r
-#define CCU4_CC4_TCSET_TRBS_Msk (0x01UL << CCU4_CC4_TCSET_TRBS_Pos) /*!< CCU4_CC4 TCSET: TRBS Mask */\r
-\r
-/* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */\r
-#define CCU4_CC4_TCCLR_TRBC_Pos 0 /*!< CCU4_CC4 TCCLR: TRBC Position */\r
-#define CCU4_CC4_TCCLR_TRBC_Msk (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos) /*!< CCU4_CC4 TCCLR: TRBC Mask */\r
-#define CCU4_CC4_TCCLR_TCC_Pos 1 /*!< CCU4_CC4 TCCLR: TCC Position */\r
-#define CCU4_CC4_TCCLR_TCC_Msk (0x01UL << CCU4_CC4_TCCLR_TCC_Pos) /*!< CCU4_CC4 TCCLR: TCC Mask */\r
-#define CCU4_CC4_TCCLR_DITC_Pos 2 /*!< CCU4_CC4 TCCLR: DITC Position */\r
-#define CCU4_CC4_TCCLR_DITC_Msk (0x01UL << CCU4_CC4_TCCLR_DITC_Pos) /*!< CCU4_CC4 TCCLR: DITC Mask */\r
-\r
-/* --------------------------------- CCU4_CC4_TC -------------------------------- */\r
-#define CCU4_CC4_TC_TCM_Pos 0 /*!< CCU4_CC4 TC: TCM Position */\r
-#define CCU4_CC4_TC_TCM_Msk (0x01UL << CCU4_CC4_TC_TCM_Pos) /*!< CCU4_CC4 TC: TCM Mask */\r
-#define CCU4_CC4_TC_TSSM_Pos 1 /*!< CCU4_CC4 TC: TSSM Position */\r
-#define CCU4_CC4_TC_TSSM_Msk (0x01UL << CCU4_CC4_TC_TSSM_Pos) /*!< CCU4_CC4 TC: TSSM Mask */\r
-#define CCU4_CC4_TC_CLST_Pos 2 /*!< CCU4_CC4 TC: CLST Position */\r
-#define CCU4_CC4_TC_CLST_Msk (0x01UL << CCU4_CC4_TC_CLST_Pos) /*!< CCU4_CC4 TC: CLST Mask */\r
-#define CCU4_CC4_TC_CMOD_Pos 3 /*!< CCU4_CC4 TC: CMOD Position */\r
-#define CCU4_CC4_TC_CMOD_Msk (0x01UL << CCU4_CC4_TC_CMOD_Pos) /*!< CCU4_CC4 TC: CMOD Mask */\r
-#define CCU4_CC4_TC_ECM_Pos 4 /*!< CCU4_CC4 TC: ECM Position */\r
-#define CCU4_CC4_TC_ECM_Msk (0x01UL << CCU4_CC4_TC_ECM_Pos) /*!< CCU4_CC4 TC: ECM Mask */\r
-#define CCU4_CC4_TC_CAPC_Pos 5 /*!< CCU4_CC4 TC: CAPC Position */\r
-#define CCU4_CC4_TC_CAPC_Msk (0x03UL << CCU4_CC4_TC_CAPC_Pos) /*!< CCU4_CC4 TC: CAPC Mask */\r
-#define CCU4_CC4_TC_ENDM_Pos 8 /*!< CCU4_CC4 TC: ENDM Position */\r
-#define CCU4_CC4_TC_ENDM_Msk (0x03UL << CCU4_CC4_TC_ENDM_Pos) /*!< CCU4_CC4 TC: ENDM Mask */\r
-#define CCU4_CC4_TC_STRM_Pos 10 /*!< CCU4_CC4 TC: STRM Position */\r
-#define CCU4_CC4_TC_STRM_Msk (0x01UL << CCU4_CC4_TC_STRM_Pos) /*!< CCU4_CC4 TC: STRM Mask */\r
-#define CCU4_CC4_TC_SCE_Pos 11 /*!< CCU4_CC4 TC: SCE Position */\r
-#define CCU4_CC4_TC_SCE_Msk (0x01UL << CCU4_CC4_TC_SCE_Pos) /*!< CCU4_CC4 TC: SCE Mask */\r
-#define CCU4_CC4_TC_CCS_Pos 12 /*!< CCU4_CC4 TC: CCS Position */\r
-#define CCU4_CC4_TC_CCS_Msk (0x01UL << CCU4_CC4_TC_CCS_Pos) /*!< CCU4_CC4 TC: CCS Mask */\r
-#define CCU4_CC4_TC_DITHE_Pos 13 /*!< CCU4_CC4 TC: DITHE Position */\r
-#define CCU4_CC4_TC_DITHE_Msk (0x03UL << CCU4_CC4_TC_DITHE_Pos) /*!< CCU4_CC4 TC: DITHE Mask */\r
-#define CCU4_CC4_TC_DIM_Pos 15 /*!< CCU4_CC4 TC: DIM Position */\r
-#define CCU4_CC4_TC_DIM_Msk (0x01UL << CCU4_CC4_TC_DIM_Pos) /*!< CCU4_CC4 TC: DIM Mask */\r
-#define CCU4_CC4_TC_FPE_Pos 16 /*!< CCU4_CC4 TC: FPE Position */\r
-#define CCU4_CC4_TC_FPE_Msk (0x01UL << CCU4_CC4_TC_FPE_Pos) /*!< CCU4_CC4 TC: FPE Mask */\r
-#define CCU4_CC4_TC_TRAPE_Pos 17 /*!< CCU4_CC4 TC: TRAPE Position */\r
-#define CCU4_CC4_TC_TRAPE_Msk (0x01UL << CCU4_CC4_TC_TRAPE_Pos) /*!< CCU4_CC4 TC: TRAPE Mask */\r
-#define CCU4_CC4_TC_TRPSE_Pos 21 /*!< CCU4_CC4 TC: TRPSE Position */\r
-#define CCU4_CC4_TC_TRPSE_Msk (0x01UL << CCU4_CC4_TC_TRPSE_Pos) /*!< CCU4_CC4 TC: TRPSE Mask */\r
-#define CCU4_CC4_TC_TRPSW_Pos 22 /*!< CCU4_CC4 TC: TRPSW Position */\r
-#define CCU4_CC4_TC_TRPSW_Msk (0x01UL << CCU4_CC4_TC_TRPSW_Pos) /*!< CCU4_CC4 TC: TRPSW Mask */\r
-#define CCU4_CC4_TC_EMS_Pos 23 /*!< CCU4_CC4 TC: EMS Position */\r
-#define CCU4_CC4_TC_EMS_Msk (0x01UL << CCU4_CC4_TC_EMS_Pos) /*!< CCU4_CC4 TC: EMS Mask */\r
-#define CCU4_CC4_TC_EMT_Pos 24 /*!< CCU4_CC4 TC: EMT Position */\r
-#define CCU4_CC4_TC_EMT_Msk (0x01UL << CCU4_CC4_TC_EMT_Pos) /*!< CCU4_CC4 TC: EMT Mask */\r
-#define CCU4_CC4_TC_MCME_Pos 25 /*!< CCU4_CC4 TC: MCME Position */\r
-#define CCU4_CC4_TC_MCME_Msk (0x01UL << CCU4_CC4_TC_MCME_Pos) /*!< CCU4_CC4 TC: MCME Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_PSL -------------------------------- */\r
-#define CCU4_CC4_PSL_PSL_Pos 0 /*!< CCU4_CC4 PSL: PSL Position */\r
-#define CCU4_CC4_PSL_PSL_Msk (0x01UL << CCU4_CC4_PSL_PSL_Pos) /*!< CCU4_CC4 PSL: PSL Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_DIT -------------------------------- */\r
-#define CCU4_CC4_DIT_DCV_Pos 0 /*!< CCU4_CC4 DIT: DCV Position */\r
-#define CCU4_CC4_DIT_DCV_Msk (0x0fUL << CCU4_CC4_DIT_DCV_Pos) /*!< CCU4_CC4 DIT: DCV Mask */\r
-#define CCU4_CC4_DIT_DCNT_Pos 8 /*!< CCU4_CC4 DIT: DCNT Position */\r
-#define CCU4_CC4_DIT_DCNT_Msk (0x0fUL << CCU4_CC4_DIT_DCNT_Pos) /*!< CCU4_CC4 DIT: DCNT Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_DITS ------------------------------- */\r
-#define CCU4_CC4_DITS_DCVS_Pos 0 /*!< CCU4_CC4 DITS: DCVS Position */\r
-#define CCU4_CC4_DITS_DCVS_Msk (0x0fUL << CCU4_CC4_DITS_DCVS_Pos) /*!< CCU4_CC4 DITS: DCVS Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_PSC -------------------------------- */\r
-#define CCU4_CC4_PSC_PSIV_Pos 0 /*!< CCU4_CC4 PSC: PSIV Position */\r
-#define CCU4_CC4_PSC_PSIV_Msk (0x0fUL << CCU4_CC4_PSC_PSIV_Pos) /*!< CCU4_CC4 PSC: PSIV Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_FPC -------------------------------- */\r
-#define CCU4_CC4_FPC_PCMP_Pos 0 /*!< CCU4_CC4 FPC: PCMP Position */\r
-#define CCU4_CC4_FPC_PCMP_Msk (0x0fUL << CCU4_CC4_FPC_PCMP_Pos) /*!< CCU4_CC4 FPC: PCMP Mask */\r
-#define CCU4_CC4_FPC_PVAL_Pos 8 /*!< CCU4_CC4 FPC: PVAL Position */\r
-#define CCU4_CC4_FPC_PVAL_Msk (0x0fUL << CCU4_CC4_FPC_PVAL_Pos) /*!< CCU4_CC4 FPC: PVAL Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_FPCS ------------------------------- */\r
-#define CCU4_CC4_FPCS_PCMP_Pos 0 /*!< CCU4_CC4 FPCS: PCMP Position */\r
-#define CCU4_CC4_FPCS_PCMP_Msk (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos) /*!< CCU4_CC4 FPCS: PCMP Mask */\r
-\r
-/* --------------------------------- CCU4_CC4_PR -------------------------------- */\r
-#define CCU4_CC4_PR_PR_Pos 0 /*!< CCU4_CC4 PR: PR Position */\r
-#define CCU4_CC4_PR_PR_Msk (0x0000ffffUL << CCU4_CC4_PR_PR_Pos) /*!< CCU4_CC4 PR: PR Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_PRS -------------------------------- */\r
-#define CCU4_CC4_PRS_PRS_Pos 0 /*!< CCU4_CC4 PRS: PRS Position */\r
-#define CCU4_CC4_PRS_PRS_Msk (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos) /*!< CCU4_CC4 PRS: PRS Mask */\r
-\r
-/* --------------------------------- CCU4_CC4_CR -------------------------------- */\r
-#define CCU4_CC4_CR_CR_Pos 0 /*!< CCU4_CC4 CR: CR Position */\r
-#define CCU4_CC4_CR_CR_Msk (0x0000ffffUL << CCU4_CC4_CR_CR_Pos) /*!< CCU4_CC4 CR: CR Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_CRS -------------------------------- */\r
-#define CCU4_CC4_CRS_CRS_Pos 0 /*!< CCU4_CC4 CRS: CRS Position */\r
-#define CCU4_CC4_CRS_CRS_Msk (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos) /*!< CCU4_CC4 CRS: CRS Mask */\r
-\r
-/* ------------------------------- CCU4_CC4_TIMER ------------------------------- */\r
-#define CCU4_CC4_TIMER_TVAL_Pos 0 /*!< CCU4_CC4 TIMER: TVAL Position */\r
-#define CCU4_CC4_TIMER_TVAL_Msk (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos) /*!< CCU4_CC4 TIMER: TVAL Mask */\r
-\r
-/* --------------------------------- CCU4_CC4_CV -------------------------------- */\r
-#define CCU4_CC4_CV_CAPTV_Pos 0 /*!< CCU4_CC4 CV: CAPTV Position */\r
-#define CCU4_CC4_CV_CAPTV_Msk (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos) /*!< CCU4_CC4 CV: CAPTV Mask */\r
-#define CCU4_CC4_CV_FPCV_Pos 16 /*!< CCU4_CC4 CV: FPCV Position */\r
-#define CCU4_CC4_CV_FPCV_Msk (0x0fUL << CCU4_CC4_CV_FPCV_Pos) /*!< CCU4_CC4 CV: FPCV Mask */\r
-#define CCU4_CC4_CV_FFL_Pos 20 /*!< CCU4_CC4 CV: FFL Position */\r
-#define CCU4_CC4_CV_FFL_Msk (0x01UL << CCU4_CC4_CV_FFL_Pos) /*!< CCU4_CC4 CV: FFL Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_INTS ------------------------------- */\r
-#define CCU4_CC4_INTS_PMUS_Pos 0 /*!< CCU4_CC4 INTS: PMUS Position */\r
-#define CCU4_CC4_INTS_PMUS_Msk (0x01UL << CCU4_CC4_INTS_PMUS_Pos) /*!< CCU4_CC4 INTS: PMUS Mask */\r
-#define CCU4_CC4_INTS_OMDS_Pos 1 /*!< CCU4_CC4 INTS: OMDS Position */\r
-#define CCU4_CC4_INTS_OMDS_Msk (0x01UL << CCU4_CC4_INTS_OMDS_Pos) /*!< CCU4_CC4 INTS: OMDS Mask */\r
-#define CCU4_CC4_INTS_CMUS_Pos 2 /*!< CCU4_CC4 INTS: CMUS Position */\r
-#define CCU4_CC4_INTS_CMUS_Msk (0x01UL << CCU4_CC4_INTS_CMUS_Pos) /*!< CCU4_CC4 INTS: CMUS Mask */\r
-#define CCU4_CC4_INTS_CMDS_Pos 3 /*!< CCU4_CC4 INTS: CMDS Position */\r
-#define CCU4_CC4_INTS_CMDS_Msk (0x01UL << CCU4_CC4_INTS_CMDS_Pos) /*!< CCU4_CC4 INTS: CMDS Mask */\r
-#define CCU4_CC4_INTS_E0AS_Pos 8 /*!< CCU4_CC4 INTS: E0AS Position */\r
-#define CCU4_CC4_INTS_E0AS_Msk (0x01UL << CCU4_CC4_INTS_E0AS_Pos) /*!< CCU4_CC4 INTS: E0AS Mask */\r
-#define CCU4_CC4_INTS_E1AS_Pos 9 /*!< CCU4_CC4 INTS: E1AS Position */\r
-#define CCU4_CC4_INTS_E1AS_Msk (0x01UL << CCU4_CC4_INTS_E1AS_Pos) /*!< CCU4_CC4 INTS: E1AS Mask */\r
-#define CCU4_CC4_INTS_E2AS_Pos 10 /*!< CCU4_CC4 INTS: E2AS Position */\r
-#define CCU4_CC4_INTS_E2AS_Msk (0x01UL << CCU4_CC4_INTS_E2AS_Pos) /*!< CCU4_CC4 INTS: E2AS Mask */\r
-#define CCU4_CC4_INTS_TRPF_Pos 11 /*!< CCU4_CC4 INTS: TRPF Position */\r
-#define CCU4_CC4_INTS_TRPF_Msk (0x01UL << CCU4_CC4_INTS_TRPF_Pos) /*!< CCU4_CC4 INTS: TRPF Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_INTE ------------------------------- */\r
-#define CCU4_CC4_INTE_PME_Pos 0 /*!< CCU4_CC4 INTE: PME Position */\r
-#define CCU4_CC4_INTE_PME_Msk (0x01UL << CCU4_CC4_INTE_PME_Pos) /*!< CCU4_CC4 INTE: PME Mask */\r
-#define CCU4_CC4_INTE_OME_Pos 1 /*!< CCU4_CC4 INTE: OME Position */\r
-#define CCU4_CC4_INTE_OME_Msk (0x01UL << CCU4_CC4_INTE_OME_Pos) /*!< CCU4_CC4 INTE: OME Mask */\r
-#define CCU4_CC4_INTE_CMUE_Pos 2 /*!< CCU4_CC4 INTE: CMUE Position */\r
-#define CCU4_CC4_INTE_CMUE_Msk (0x01UL << CCU4_CC4_INTE_CMUE_Pos) /*!< CCU4_CC4 INTE: CMUE Mask */\r
-#define CCU4_CC4_INTE_CMDE_Pos 3 /*!< CCU4_CC4 INTE: CMDE Position */\r
-#define CCU4_CC4_INTE_CMDE_Msk (0x01UL << CCU4_CC4_INTE_CMDE_Pos) /*!< CCU4_CC4 INTE: CMDE Mask */\r
-#define CCU4_CC4_INTE_E0AE_Pos 8 /*!< CCU4_CC4 INTE: E0AE Position */\r
-#define CCU4_CC4_INTE_E0AE_Msk (0x01UL << CCU4_CC4_INTE_E0AE_Pos) /*!< CCU4_CC4 INTE: E0AE Mask */\r
-#define CCU4_CC4_INTE_E1AE_Pos 9 /*!< CCU4_CC4 INTE: E1AE Position */\r
-#define CCU4_CC4_INTE_E1AE_Msk (0x01UL << CCU4_CC4_INTE_E1AE_Pos) /*!< CCU4_CC4 INTE: E1AE Mask */\r
-#define CCU4_CC4_INTE_E2AE_Pos 10 /*!< CCU4_CC4 INTE: E2AE Position */\r
-#define CCU4_CC4_INTE_E2AE_Msk (0x01UL << CCU4_CC4_INTE_E2AE_Pos) /*!< CCU4_CC4 INTE: E2AE Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_SRS -------------------------------- */\r
-#define CCU4_CC4_SRS_POSR_Pos 0 /*!< CCU4_CC4 SRS: POSR Position */\r
-#define CCU4_CC4_SRS_POSR_Msk (0x03UL << CCU4_CC4_SRS_POSR_Pos) /*!< CCU4_CC4 SRS: POSR Mask */\r
-#define CCU4_CC4_SRS_CMSR_Pos 2 /*!< CCU4_CC4 SRS: CMSR Position */\r
-#define CCU4_CC4_SRS_CMSR_Msk (0x03UL << CCU4_CC4_SRS_CMSR_Pos) /*!< CCU4_CC4 SRS: CMSR Mask */\r
-#define CCU4_CC4_SRS_E0SR_Pos 8 /*!< CCU4_CC4 SRS: E0SR Position */\r
-#define CCU4_CC4_SRS_E0SR_Msk (0x03UL << CCU4_CC4_SRS_E0SR_Pos) /*!< CCU4_CC4 SRS: E0SR Mask */\r
-#define CCU4_CC4_SRS_E1SR_Pos 10 /*!< CCU4_CC4 SRS: E1SR Position */\r
-#define CCU4_CC4_SRS_E1SR_Msk (0x03UL << CCU4_CC4_SRS_E1SR_Pos) /*!< CCU4_CC4 SRS: E1SR Mask */\r
-#define CCU4_CC4_SRS_E2SR_Pos 12 /*!< CCU4_CC4 SRS: E2SR Position */\r
-#define CCU4_CC4_SRS_E2SR_Msk (0x03UL << CCU4_CC4_SRS_E2SR_Pos) /*!< CCU4_CC4 SRS: E2SR Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_SWS -------------------------------- */\r
-#define CCU4_CC4_SWS_SPM_Pos 0 /*!< CCU4_CC4 SWS: SPM Position */\r
-#define CCU4_CC4_SWS_SPM_Msk (0x01UL << CCU4_CC4_SWS_SPM_Pos) /*!< CCU4_CC4 SWS: SPM Mask */\r
-#define CCU4_CC4_SWS_SOM_Pos 1 /*!< CCU4_CC4 SWS: SOM Position */\r
-#define CCU4_CC4_SWS_SOM_Msk (0x01UL << CCU4_CC4_SWS_SOM_Pos) /*!< CCU4_CC4 SWS: SOM Mask */\r
-#define CCU4_CC4_SWS_SCMU_Pos 2 /*!< CCU4_CC4 SWS: SCMU Position */\r
-#define CCU4_CC4_SWS_SCMU_Msk (0x01UL << CCU4_CC4_SWS_SCMU_Pos) /*!< CCU4_CC4 SWS: SCMU Mask */\r
-#define CCU4_CC4_SWS_SCMD_Pos 3 /*!< CCU4_CC4 SWS: SCMD Position */\r
-#define CCU4_CC4_SWS_SCMD_Msk (0x01UL << CCU4_CC4_SWS_SCMD_Pos) /*!< CCU4_CC4 SWS: SCMD Mask */\r
-#define CCU4_CC4_SWS_SE0A_Pos 8 /*!< CCU4_CC4 SWS: SE0A Position */\r
-#define CCU4_CC4_SWS_SE0A_Msk (0x01UL << CCU4_CC4_SWS_SE0A_Pos) /*!< CCU4_CC4 SWS: SE0A Mask */\r
-#define CCU4_CC4_SWS_SE1A_Pos 9 /*!< CCU4_CC4 SWS: SE1A Position */\r
-#define CCU4_CC4_SWS_SE1A_Msk (0x01UL << CCU4_CC4_SWS_SE1A_Pos) /*!< CCU4_CC4 SWS: SE1A Mask */\r
-#define CCU4_CC4_SWS_SE2A_Pos 10 /*!< CCU4_CC4 SWS: SE2A Position */\r
-#define CCU4_CC4_SWS_SE2A_Msk (0x01UL << CCU4_CC4_SWS_SE2A_Pos) /*!< CCU4_CC4 SWS: SE2A Mask */\r
-#define CCU4_CC4_SWS_STRPF_Pos 11 /*!< CCU4_CC4 SWS: STRPF Position */\r
-#define CCU4_CC4_SWS_STRPF_Msk (0x01UL << CCU4_CC4_SWS_STRPF_Pos) /*!< CCU4_CC4 SWS: STRPF Mask */\r
-\r
-/* -------------------------------- CCU4_CC4_SWR -------------------------------- */\r
-#define CCU4_CC4_SWR_RPM_Pos 0 /*!< CCU4_CC4 SWR: RPM Position */\r
-#define CCU4_CC4_SWR_RPM_Msk (0x01UL << CCU4_CC4_SWR_RPM_Pos) /*!< CCU4_CC4 SWR: RPM Mask */\r
-#define CCU4_CC4_SWR_ROM_Pos 1 /*!< CCU4_CC4 SWR: ROM Position */\r
-#define CCU4_CC4_SWR_ROM_Msk (0x01UL << CCU4_CC4_SWR_ROM_Pos) /*!< CCU4_CC4 SWR: ROM Mask */\r
-#define CCU4_CC4_SWR_RCMU_Pos 2 /*!< CCU4_CC4 SWR: RCMU Position */\r
-#define CCU4_CC4_SWR_RCMU_Msk (0x01UL << CCU4_CC4_SWR_RCMU_Pos) /*!< CCU4_CC4 SWR: RCMU Mask */\r
-#define CCU4_CC4_SWR_RCMD_Pos 3 /*!< CCU4_CC4 SWR: RCMD Position */\r
-#define CCU4_CC4_SWR_RCMD_Msk (0x01UL << CCU4_CC4_SWR_RCMD_Pos) /*!< CCU4_CC4 SWR: RCMD Mask */\r
-#define CCU4_CC4_SWR_RE0A_Pos 8 /*!< CCU4_CC4 SWR: RE0A Position */\r
-#define CCU4_CC4_SWR_RE0A_Msk (0x01UL << CCU4_CC4_SWR_RE0A_Pos) /*!< CCU4_CC4 SWR: RE0A Mask */\r
-#define CCU4_CC4_SWR_RE1A_Pos 9 /*!< CCU4_CC4 SWR: RE1A Position */\r
-#define CCU4_CC4_SWR_RE1A_Msk (0x01UL << CCU4_CC4_SWR_RE1A_Pos) /*!< CCU4_CC4 SWR: RE1A Mask */\r
-#define CCU4_CC4_SWR_RE2A_Pos 10 /*!< CCU4_CC4 SWR: RE2A Position */\r
-#define CCU4_CC4_SWR_RE2A_Msk (0x01UL << CCU4_CC4_SWR_RE2A_Pos) /*!< CCU4_CC4 SWR: RE2A Mask */\r
-#define CCU4_CC4_SWR_RTRPF_Pos 11 /*!< CCU4_CC4 SWR: RTRPF Position */\r
-#define CCU4_CC4_SWR_RTRPF_Msk (0x01UL << CCU4_CC4_SWR_RTRPF_Pos) /*!< CCU4_CC4 SWR: RTRPF Mask */\r
-\r
-/* ------------------------------- CCU4_CC4_ECRD0 ------------------------------- */\r
-#define CCU4_CC4_ECRD0_CAPV_Pos 0 /*!< CCU4_CC4 ECRD0: CAPV Position */\r
-#define CCU4_CC4_ECRD0_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD0_CAPV_Pos) /*!< CCU4_CC4 ECRD0: CAPV Mask */\r
-#define CCU4_CC4_ECRD0_FPCV_Pos 16 /*!< CCU4_CC4 ECRD0: FPCV Position */\r
-#define CCU4_CC4_ECRD0_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD0_FPCV_Pos) /*!< CCU4_CC4 ECRD0: FPCV Mask */\r
-#define CCU4_CC4_ECRD0_SPTR_Pos 20 /*!< CCU4_CC4 ECRD0: SPTR Position */\r
-#define CCU4_CC4_ECRD0_SPTR_Msk (0x03UL << CCU4_CC4_ECRD0_SPTR_Pos) /*!< CCU4_CC4 ECRD0: SPTR Mask */\r
-#define CCU4_CC4_ECRD0_VPTR_Pos 22 /*!< CCU4_CC4 ECRD0: VPTR Position */\r
-#define CCU4_CC4_ECRD0_VPTR_Msk (0x03UL << CCU4_CC4_ECRD0_VPTR_Pos) /*!< CCU4_CC4 ECRD0: VPTR Mask */\r
-#define CCU4_CC4_ECRD0_FFL_Pos 24 /*!< CCU4_CC4 ECRD0: FFL Position */\r
-#define CCU4_CC4_ECRD0_FFL_Msk (0x01UL << CCU4_CC4_ECRD0_FFL_Pos) /*!< CCU4_CC4 ECRD0: FFL Mask */\r
-#define CCU4_CC4_ECRD0_LCV_Pos 25 /*!< CCU4_CC4 ECRD0: LCV Position */\r
-#define CCU4_CC4_ECRD0_LCV_Msk (0x01UL << CCU4_CC4_ECRD0_LCV_Pos) /*!< CCU4_CC4 ECRD0: LCV Mask */\r
-\r
-/* ------------------------------- CCU4_CC4_ECRD1 ------------------------------- */\r
-#define CCU4_CC4_ECRD1_CAPV_Pos 0 /*!< CCU4_CC4 ECRD1: CAPV Position */\r
-#define CCU4_CC4_ECRD1_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD1_CAPV_Pos) /*!< CCU4_CC4 ECRD1: CAPV Mask */\r
-#define CCU4_CC4_ECRD1_FPCV_Pos 16 /*!< CCU4_CC4 ECRD1: FPCV Position */\r
-#define CCU4_CC4_ECRD1_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD1_FPCV_Pos) /*!< CCU4_CC4 ECRD1: FPCV Mask */\r
-#define CCU4_CC4_ECRD1_SPTR_Pos 20 /*!< CCU4_CC4 ECRD1: SPTR Position */\r
-#define CCU4_CC4_ECRD1_SPTR_Msk (0x03UL << CCU4_CC4_ECRD1_SPTR_Pos) /*!< CCU4_CC4 ECRD1: SPTR Mask */\r
-#define CCU4_CC4_ECRD1_VPTR_Pos 22 /*!< CCU4_CC4 ECRD1: VPTR Position */\r
-#define CCU4_CC4_ECRD1_VPTR_Msk (0x03UL << CCU4_CC4_ECRD1_VPTR_Pos) /*!< CCU4_CC4 ECRD1: VPTR Mask */\r
-#define CCU4_CC4_ECRD1_FFL_Pos 24 /*!< CCU4_CC4 ECRD1: FFL Position */\r
-#define CCU4_CC4_ECRD1_FFL_Msk (0x01UL << CCU4_CC4_ECRD1_FFL_Pos) /*!< CCU4_CC4 ECRD1: FFL Mask */\r
-#define CCU4_CC4_ECRD1_LCV_Pos 25 /*!< CCU4_CC4 ECRD1: LCV Position */\r
-#define CCU4_CC4_ECRD1_LCV_Msk (0x01UL << CCU4_CC4_ECRD1_LCV_Pos) /*!< CCU4_CC4 ECRD1: LCV Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'VADC' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- VADC_CLC ---------------------------------- */\r
-#define VADC_CLC_DISR_Pos 0 /*!< VADC CLC: DISR Position */\r
-#define VADC_CLC_DISR_Msk (0x01UL << VADC_CLC_DISR_Pos) /*!< VADC CLC: DISR Mask */\r
-#define VADC_CLC_DISS_Pos 1 /*!< VADC CLC: DISS Position */\r
-#define VADC_CLC_DISS_Msk (0x01UL << VADC_CLC_DISS_Pos) /*!< VADC CLC: DISS Mask */\r
-#define VADC_CLC_EDIS_Pos 3 /*!< VADC CLC: EDIS Position */\r
-#define VADC_CLC_EDIS_Msk (0x01UL << VADC_CLC_EDIS_Pos) /*!< VADC CLC: EDIS Mask */\r
-\r
-/* ----------------------------------- VADC_ID ---------------------------------- */\r
-#define VADC_ID_MOD_REV_Pos 0 /*!< VADC ID: MOD_REV Position */\r
-#define VADC_ID_MOD_REV_Msk (0x000000ffUL << VADC_ID_MOD_REV_Pos) /*!< VADC ID: MOD_REV Mask */\r
-#define VADC_ID_MOD_TYPE_Pos 8 /*!< VADC ID: MOD_TYPE Position */\r
-#define VADC_ID_MOD_TYPE_Msk (0x000000ffUL << VADC_ID_MOD_TYPE_Pos) /*!< VADC ID: MOD_TYPE Mask */\r
-#define VADC_ID_MOD_NUMBER_Pos 16 /*!< VADC ID: MOD_NUMBER Position */\r
-#define VADC_ID_MOD_NUMBER_Msk (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos) /*!< VADC ID: MOD_NUMBER Mask */\r
-\r
-/* ---------------------------------- VADC_OCS ---------------------------------- */\r
-#define VADC_OCS_TGS_Pos 0 /*!< VADC OCS: TGS Position */\r
-#define VADC_OCS_TGS_Msk (0x03UL << VADC_OCS_TGS_Pos) /*!< VADC OCS: TGS Mask */\r
-#define VADC_OCS_TGB_Pos 2 /*!< VADC OCS: TGB Position */\r
-#define VADC_OCS_TGB_Msk (0x01UL << VADC_OCS_TGB_Pos) /*!< VADC OCS: TGB Mask */\r
-#define VADC_OCS_TG_P_Pos 3 /*!< VADC OCS: TG_P Position */\r
-#define VADC_OCS_TG_P_Msk (0x01UL << VADC_OCS_TG_P_Pos) /*!< VADC OCS: TG_P Mask */\r
-#define VADC_OCS_SUS_Pos 24 /*!< VADC OCS: SUS Position */\r
-#define VADC_OCS_SUS_Msk (0x0fUL << VADC_OCS_SUS_Pos) /*!< VADC OCS: SUS Mask */\r
-#define VADC_OCS_SUS_P_Pos 28 /*!< VADC OCS: SUS_P Position */\r
-#define VADC_OCS_SUS_P_Msk (0x01UL << VADC_OCS_SUS_P_Pos) /*!< VADC OCS: SUS_P Mask */\r
-#define VADC_OCS_SUSSTA_Pos 29 /*!< VADC OCS: SUSSTA Position */\r
-#define VADC_OCS_SUSSTA_Msk (0x01UL << VADC_OCS_SUSSTA_Pos) /*!< VADC OCS: SUSSTA Mask */\r
-\r
-/* -------------------------------- VADC_GLOBCFG -------------------------------- */\r
-#define VADC_GLOBCFG_DIVA_Pos 0 /*!< VADC GLOBCFG: DIVA Position */\r
-#define VADC_GLOBCFG_DIVA_Msk (0x1fUL << VADC_GLOBCFG_DIVA_Pos) /*!< VADC GLOBCFG: DIVA Mask */\r
-#define VADC_GLOBCFG_DCMSB_Pos 7 /*!< VADC GLOBCFG: DCMSB Position */\r
-#define VADC_GLOBCFG_DCMSB_Msk (0x01UL << VADC_GLOBCFG_DCMSB_Pos) /*!< VADC GLOBCFG: DCMSB Mask */\r
-#define VADC_GLOBCFG_DIVD_Pos 8 /*!< VADC GLOBCFG: DIVD Position */\r
-#define VADC_GLOBCFG_DIVD_Msk (0x03UL << VADC_GLOBCFG_DIVD_Pos) /*!< VADC GLOBCFG: DIVD Mask */\r
-#define VADC_GLOBCFG_DIVWC_Pos 15 /*!< VADC GLOBCFG: DIVWC Position */\r
-#define VADC_GLOBCFG_DIVWC_Msk (0x01UL << VADC_GLOBCFG_DIVWC_Pos) /*!< VADC GLOBCFG: DIVWC Mask */\r
-#define VADC_GLOBCFG_DPCAL0_Pos 16 /*!< VADC GLOBCFG: DPCAL0 Position */\r
-#define VADC_GLOBCFG_DPCAL0_Msk (0x01UL << VADC_GLOBCFG_DPCAL0_Pos) /*!< VADC GLOBCFG: DPCAL0 Mask */\r
-#define VADC_GLOBCFG_DPCAL1_Pos 17 /*!< VADC GLOBCFG: DPCAL1 Position */\r
-#define VADC_GLOBCFG_DPCAL1_Msk (0x01UL << VADC_GLOBCFG_DPCAL1_Pos) /*!< VADC GLOBCFG: DPCAL1 Mask */\r
-#define VADC_GLOBCFG_SUCAL_Pos 31 /*!< VADC GLOBCFG: SUCAL Position */\r
-#define VADC_GLOBCFG_SUCAL_Msk (0x01UL << VADC_GLOBCFG_SUCAL_Pos) /*!< VADC GLOBCFG: SUCAL Mask */\r
-\r
-/* -------------------------------- VADC_ACCPROT0 ------------------------------- */\r
-#define VADC_ACCPROT0_APC0_Pos 0 /*!< VADC ACCPROT0: APC0 Position */\r
-#define VADC_ACCPROT0_APC0_Msk (0x01UL << VADC_ACCPROT0_APC0_Pos) /*!< VADC ACCPROT0: APC0 Mask */\r
-#define VADC_ACCPROT0_APC1_Pos 1 /*!< VADC ACCPROT0: APC1 Position */\r
-#define VADC_ACCPROT0_APC1_Msk (0x01UL << VADC_ACCPROT0_APC1_Pos) /*!< VADC ACCPROT0: APC1 Mask */\r
-#define VADC_ACCPROT0_APEM_Pos 15 /*!< VADC ACCPROT0: APEM Position */\r
-#define VADC_ACCPROT0_APEM_Msk (0x01UL << VADC_ACCPROT0_APEM_Pos) /*!< VADC ACCPROT0: APEM Mask */\r
-#define VADC_ACCPROT0_API0_Pos 16 /*!< VADC ACCPROT0: API0 Position */\r
-#define VADC_ACCPROT0_API0_Msk (0x01UL << VADC_ACCPROT0_API0_Pos) /*!< VADC ACCPROT0: API0 Mask */\r
-#define VADC_ACCPROT0_API1_Pos 17 /*!< VADC ACCPROT0: API1 Position */\r
-#define VADC_ACCPROT0_API1_Msk (0x01UL << VADC_ACCPROT0_API1_Pos) /*!< VADC ACCPROT0: API1 Mask */\r
-#define VADC_ACCPROT0_APGC_Pos 31 /*!< VADC ACCPROT0: APGC Position */\r
-#define VADC_ACCPROT0_APGC_Msk (0x01UL << VADC_ACCPROT0_APGC_Pos) /*!< VADC ACCPROT0: APGC Mask */\r
-\r
-/* -------------------------------- VADC_ACCPROT1 ------------------------------- */\r
-#define VADC_ACCPROT1_APS0_Pos 0 /*!< VADC ACCPROT1: APS0 Position */\r
-#define VADC_ACCPROT1_APS0_Msk (0x01UL << VADC_ACCPROT1_APS0_Pos) /*!< VADC ACCPROT1: APS0 Mask */\r
-#define VADC_ACCPROT1_APS1_Pos 1 /*!< VADC ACCPROT1: APS1 Position */\r
-#define VADC_ACCPROT1_APS1_Msk (0x01UL << VADC_ACCPROT1_APS1_Pos) /*!< VADC ACCPROT1: APS1 Mask */\r
-#define VADC_ACCPROT1_APTF_Pos 15 /*!< VADC ACCPROT1: APTF Position */\r
-#define VADC_ACCPROT1_APTF_Msk (0x01UL << VADC_ACCPROT1_APTF_Pos) /*!< VADC ACCPROT1: APTF Mask */\r
-#define VADC_ACCPROT1_APR0_Pos 16 /*!< VADC ACCPROT1: APR0 Position */\r
-#define VADC_ACCPROT1_APR0_Msk (0x01UL << VADC_ACCPROT1_APR0_Pos) /*!< VADC ACCPROT1: APR0 Mask */\r
-#define VADC_ACCPROT1_APR1_Pos 17 /*!< VADC ACCPROT1: APR1 Position */\r
-#define VADC_ACCPROT1_APR1_Msk (0x01UL << VADC_ACCPROT1_APR1_Pos) /*!< VADC ACCPROT1: APR1 Mask */\r
-\r
-/* ------------------------------- VADC_GLOBICLASS ------------------------------ */\r
-#define VADC_GLOBICLASS_STCS_Pos 0 /*!< VADC GLOBICLASS: STCS Position */\r
-#define VADC_GLOBICLASS_STCS_Msk (0x1fUL << VADC_GLOBICLASS_STCS_Pos) /*!< VADC GLOBICLASS: STCS Mask */\r
-#define VADC_GLOBICLASS_CMS_Pos 8 /*!< VADC GLOBICLASS: CMS Position */\r
-#define VADC_GLOBICLASS_CMS_Msk (0x07UL << VADC_GLOBICLASS_CMS_Pos) /*!< VADC GLOBICLASS: CMS Mask */\r
-#define VADC_GLOBICLASS_STCE_Pos 16 /*!< VADC GLOBICLASS: STCE Position */\r
-#define VADC_GLOBICLASS_STCE_Msk (0x1fUL << VADC_GLOBICLASS_STCE_Pos) /*!< VADC GLOBICLASS: STCE Mask */\r
-#define VADC_GLOBICLASS_CME_Pos 24 /*!< VADC GLOBICLASS: CME Position */\r
-#define VADC_GLOBICLASS_CME_Msk (0x07UL << VADC_GLOBICLASS_CME_Pos) /*!< VADC GLOBICLASS: CME Mask */\r
-\r
-/* ------------------------------- VADC_GLOBBOUND ------------------------------- */\r
-#define VADC_GLOBBOUND_BOUNDARY0_Pos 0 /*!< VADC GLOBBOUND: BOUNDARY0 Position */\r
-#define VADC_GLOBBOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos) /*!< VADC GLOBBOUND: BOUNDARY0 Mask */\r
-#define VADC_GLOBBOUND_BOUNDARY1_Pos 16 /*!< VADC GLOBBOUND: BOUNDARY1 Position */\r
-#define VADC_GLOBBOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos) /*!< VADC GLOBBOUND: BOUNDARY1 Mask */\r
-\r
-/* ------------------------------- VADC_GLOBEFLAG ------------------------------- */\r
-#define VADC_GLOBEFLAG_SEVGLB_Pos 0 /*!< VADC GLOBEFLAG: SEVGLB Position */\r
-#define VADC_GLOBEFLAG_SEVGLB_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos) /*!< VADC GLOBEFLAG: SEVGLB Mask */\r
-#define VADC_GLOBEFLAG_REVGLB_Pos 8 /*!< VADC GLOBEFLAG: REVGLB Position */\r
-#define VADC_GLOBEFLAG_REVGLB_Msk (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos) /*!< VADC GLOBEFLAG: REVGLB Mask */\r
-#define VADC_GLOBEFLAG_SEVGLBCLR_Pos 16 /*!< VADC GLOBEFLAG: SEVGLBCLR Position */\r
-#define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos) /*!< VADC GLOBEFLAG: SEVGLBCLR Mask */\r
-#define VADC_GLOBEFLAG_REVGLBCLR_Pos 24 /*!< VADC GLOBEFLAG: REVGLBCLR Position */\r
-#define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos) /*!< VADC GLOBEFLAG: REVGLBCLR Mask */\r
-\r
-/* -------------------------------- VADC_GLOBEVNP ------------------------------- */\r
-#define VADC_GLOBEVNP_SEV0NP_Pos 0 /*!< VADC GLOBEVNP: SEV0NP Position */\r
-#define VADC_GLOBEVNP_SEV0NP_Msk (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos) /*!< VADC GLOBEVNP: SEV0NP Mask */\r
-#define VADC_GLOBEVNP_REV0NP_Pos 16 /*!< VADC GLOBEVNP: REV0NP Position */\r
-#define VADC_GLOBEVNP_REV0NP_Msk (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos) /*!< VADC GLOBEVNP: REV0NP Mask */\r
-\r
-/* --------------------------------- VADC_BRSSEL -------------------------------- */\r
-#define VADC_BRSSEL_CHSELG0_Pos 0 /*!< VADC BRSSEL: CHSELG0 Position */\r
-#define VADC_BRSSEL_CHSELG0_Msk (0x01UL << VADC_BRSSEL_CHSELG0_Pos) /*!< VADC BRSSEL: CHSELG0 Mask */\r
-#define VADC_BRSSEL_CHSELG1_Pos 1 /*!< VADC BRSSEL: CHSELG1 Position */\r
-#define VADC_BRSSEL_CHSELG1_Msk (0x01UL << VADC_BRSSEL_CHSELG1_Pos) /*!< VADC BRSSEL: CHSELG1 Mask */\r
-#define VADC_BRSSEL_CHSELG2_Pos 2 /*!< VADC BRSSEL: CHSELG2 Position */\r
-#define VADC_BRSSEL_CHSELG2_Msk (0x01UL << VADC_BRSSEL_CHSELG2_Pos) /*!< VADC BRSSEL: CHSELG2 Mask */\r
-#define VADC_BRSSEL_CHSELG3_Pos 3 /*!< VADC BRSSEL: CHSELG3 Position */\r
-#define VADC_BRSSEL_CHSELG3_Msk (0x01UL << VADC_BRSSEL_CHSELG3_Pos) /*!< VADC BRSSEL: CHSELG3 Mask */\r
-#define VADC_BRSSEL_CHSELG4_Pos 4 /*!< VADC BRSSEL: CHSELG4 Position */\r
-#define VADC_BRSSEL_CHSELG4_Msk (0x01UL << VADC_BRSSEL_CHSELG4_Pos) /*!< VADC BRSSEL: CHSELG4 Mask */\r
-#define VADC_BRSSEL_CHSELG5_Pos 5 /*!< VADC BRSSEL: CHSELG5 Position */\r
-#define VADC_BRSSEL_CHSELG5_Msk (0x01UL << VADC_BRSSEL_CHSELG5_Pos) /*!< VADC BRSSEL: CHSELG5 Mask */\r
-#define VADC_BRSSEL_CHSELG6_Pos 6 /*!< VADC BRSSEL: CHSELG6 Position */\r
-#define VADC_BRSSEL_CHSELG6_Msk (0x01UL << VADC_BRSSEL_CHSELG6_Pos) /*!< VADC BRSSEL: CHSELG6 Mask */\r
-#define VADC_BRSSEL_CHSELG7_Pos 7 /*!< VADC BRSSEL: CHSELG7 Position */\r
-#define VADC_BRSSEL_CHSELG7_Msk (0x01UL << VADC_BRSSEL_CHSELG7_Pos) /*!< VADC BRSSEL: CHSELG7 Mask */\r
-\r
-/* --------------------------------- VADC_BRSPND -------------------------------- */\r
-#define VADC_BRSPND_CHPNDG0_Pos 0 /*!< VADC BRSPND: CHPNDG0 Position */\r
-#define VADC_BRSPND_CHPNDG0_Msk (0x01UL << VADC_BRSPND_CHPNDG0_Pos) /*!< VADC BRSPND: CHPNDG0 Mask */\r
-#define VADC_BRSPND_CHPNDG1_Pos 1 /*!< VADC BRSPND: CHPNDG1 Position */\r
-#define VADC_BRSPND_CHPNDG1_Msk (0x01UL << VADC_BRSPND_CHPNDG1_Pos) /*!< VADC BRSPND: CHPNDG1 Mask */\r
-#define VADC_BRSPND_CHPNDG2_Pos 2 /*!< VADC BRSPND: CHPNDG2 Position */\r
-#define VADC_BRSPND_CHPNDG2_Msk (0x01UL << VADC_BRSPND_CHPNDG2_Pos) /*!< VADC BRSPND: CHPNDG2 Mask */\r
-#define VADC_BRSPND_CHPNDG3_Pos 3 /*!< VADC BRSPND: CHPNDG3 Position */\r
-#define VADC_BRSPND_CHPNDG3_Msk (0x01UL << VADC_BRSPND_CHPNDG3_Pos) /*!< VADC BRSPND: CHPNDG3 Mask */\r
-#define VADC_BRSPND_CHPNDG4_Pos 4 /*!< VADC BRSPND: CHPNDG4 Position */\r
-#define VADC_BRSPND_CHPNDG4_Msk (0x01UL << VADC_BRSPND_CHPNDG4_Pos) /*!< VADC BRSPND: CHPNDG4 Mask */\r
-#define VADC_BRSPND_CHPNDG5_Pos 5 /*!< VADC BRSPND: CHPNDG5 Position */\r
-#define VADC_BRSPND_CHPNDG5_Msk (0x01UL << VADC_BRSPND_CHPNDG5_Pos) /*!< VADC BRSPND: CHPNDG5 Mask */\r
-#define VADC_BRSPND_CHPNDG6_Pos 6 /*!< VADC BRSPND: CHPNDG6 Position */\r
-#define VADC_BRSPND_CHPNDG6_Msk (0x01UL << VADC_BRSPND_CHPNDG6_Pos) /*!< VADC BRSPND: CHPNDG6 Mask */\r
-#define VADC_BRSPND_CHPNDG7_Pos 7 /*!< VADC BRSPND: CHPNDG7 Position */\r
-#define VADC_BRSPND_CHPNDG7_Msk (0x01UL << VADC_BRSPND_CHPNDG7_Pos) /*!< VADC BRSPND: CHPNDG7 Mask */\r
-\r
-/* -------------------------------- VADC_BRSCTRL -------------------------------- */\r
-#define VADC_BRSCTRL_SRCRESREG_Pos 0 /*!< VADC BRSCTRL: SRCRESREG Position */\r
-#define VADC_BRSCTRL_SRCRESREG_Msk (0x0fUL << VADC_BRSCTRL_SRCRESREG_Pos) /*!< VADC BRSCTRL: SRCRESREG Mask */\r
-#define VADC_BRSCTRL_XTSEL_Pos 8 /*!< VADC BRSCTRL: XTSEL Position */\r
-#define VADC_BRSCTRL_XTSEL_Msk (0x0fUL << VADC_BRSCTRL_XTSEL_Pos) /*!< VADC BRSCTRL: XTSEL Mask */\r
-#define VADC_BRSCTRL_XTLVL_Pos 12 /*!< VADC BRSCTRL: XTLVL Position */\r
-#define VADC_BRSCTRL_XTLVL_Msk (0x01UL << VADC_BRSCTRL_XTLVL_Pos) /*!< VADC BRSCTRL: XTLVL Mask */\r
-#define VADC_BRSCTRL_XTMODE_Pos 13 /*!< VADC BRSCTRL: XTMODE Position */\r
-#define VADC_BRSCTRL_XTMODE_Msk (0x03UL << VADC_BRSCTRL_XTMODE_Pos) /*!< VADC BRSCTRL: XTMODE Mask */\r
-#define VADC_BRSCTRL_XTWC_Pos 15 /*!< VADC BRSCTRL: XTWC Position */\r
-#define VADC_BRSCTRL_XTWC_Msk (0x01UL << VADC_BRSCTRL_XTWC_Pos) /*!< VADC BRSCTRL: XTWC Mask */\r
-#define VADC_BRSCTRL_GTSEL_Pos 16 /*!< VADC BRSCTRL: GTSEL Position */\r
-#define VADC_BRSCTRL_GTSEL_Msk (0x0fUL << VADC_BRSCTRL_GTSEL_Pos) /*!< VADC BRSCTRL: GTSEL Mask */\r
-#define VADC_BRSCTRL_GTLVL_Pos 20 /*!< VADC BRSCTRL: GTLVL Position */\r
-#define VADC_BRSCTRL_GTLVL_Msk (0x01UL << VADC_BRSCTRL_GTLVL_Pos) /*!< VADC BRSCTRL: GTLVL Mask */\r
-#define VADC_BRSCTRL_GTWC_Pos 23 /*!< VADC BRSCTRL: GTWC Position */\r
-#define VADC_BRSCTRL_GTWC_Msk (0x01UL << VADC_BRSCTRL_GTWC_Pos) /*!< VADC BRSCTRL: GTWC Mask */\r
-\r
-/* --------------------------------- VADC_BRSMR --------------------------------- */\r
-#define VADC_BRSMR_ENGT_Pos 0 /*!< VADC BRSMR: ENGT Position */\r
-#define VADC_BRSMR_ENGT_Msk (0x03UL << VADC_BRSMR_ENGT_Pos) /*!< VADC BRSMR: ENGT Mask */\r
-#define VADC_BRSMR_ENTR_Pos 2 /*!< VADC BRSMR: ENTR Position */\r
-#define VADC_BRSMR_ENTR_Msk (0x01UL << VADC_BRSMR_ENTR_Pos) /*!< VADC BRSMR: ENTR Mask */\r
-#define VADC_BRSMR_ENSI_Pos 3 /*!< VADC BRSMR: ENSI Position */\r
-#define VADC_BRSMR_ENSI_Msk (0x01UL << VADC_BRSMR_ENSI_Pos) /*!< VADC BRSMR: ENSI Mask */\r
-#define VADC_BRSMR_SCAN_Pos 4 /*!< VADC BRSMR: SCAN Position */\r
-#define VADC_BRSMR_SCAN_Msk (0x01UL << VADC_BRSMR_SCAN_Pos) /*!< VADC BRSMR: SCAN Mask */\r
-#define VADC_BRSMR_LDM_Pos 5 /*!< VADC BRSMR: LDM Position */\r
-#define VADC_BRSMR_LDM_Msk (0x01UL << VADC_BRSMR_LDM_Pos) /*!< VADC BRSMR: LDM Mask */\r
-#define VADC_BRSMR_REQGT_Pos 7 /*!< VADC BRSMR: REQGT Position */\r
-#define VADC_BRSMR_REQGT_Msk (0x01UL << VADC_BRSMR_REQGT_Pos) /*!< VADC BRSMR: REQGT Mask */\r
-#define VADC_BRSMR_CLRPND_Pos 8 /*!< VADC BRSMR: CLRPND Position */\r
-#define VADC_BRSMR_CLRPND_Msk (0x01UL << VADC_BRSMR_CLRPND_Pos) /*!< VADC BRSMR: CLRPND Mask */\r
-#define VADC_BRSMR_LDEV_Pos 9 /*!< VADC BRSMR: LDEV Position */\r
-#define VADC_BRSMR_LDEV_Msk (0x01UL << VADC_BRSMR_LDEV_Pos) /*!< VADC BRSMR: LDEV Mask */\r
-#define VADC_BRSMR_RPTDIS_Pos 16 /*!< VADC BRSMR: RPTDIS Position */\r
-#define VADC_BRSMR_RPTDIS_Msk (0x01UL << VADC_BRSMR_RPTDIS_Pos) /*!< VADC BRSMR: RPTDIS Mask */\r
-\r
-/* -------------------------------- VADC_GLOBRCR -------------------------------- */\r
-#define VADC_GLOBRCR_DRCTR_Pos 16 /*!< VADC GLOBRCR: DRCTR Position */\r
-#define VADC_GLOBRCR_DRCTR_Msk (0x0fUL << VADC_GLOBRCR_DRCTR_Pos) /*!< VADC GLOBRCR: DRCTR Mask */\r
-#define VADC_GLOBRCR_WFR_Pos 24 /*!< VADC GLOBRCR: WFR Position */\r
-#define VADC_GLOBRCR_WFR_Msk (0x01UL << VADC_GLOBRCR_WFR_Pos) /*!< VADC GLOBRCR: WFR Mask */\r
-#define VADC_GLOBRCR_SRGEN_Pos 31 /*!< VADC GLOBRCR: SRGEN Position */\r
-#define VADC_GLOBRCR_SRGEN_Msk (0x01UL << VADC_GLOBRCR_SRGEN_Pos) /*!< VADC GLOBRCR: SRGEN Mask */\r
-\r
-/* -------------------------------- VADC_GLOBRES -------------------------------- */\r
-#define VADC_GLOBRES_RESULT_Pos 0 /*!< VADC GLOBRES: RESULT Position */\r
-#define VADC_GLOBRES_RESULT_Msk (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos) /*!< VADC GLOBRES: RESULT Mask */\r
-#define VADC_GLOBRES_GNR_Pos 16 /*!< VADC GLOBRES: GNR Position */\r
-#define VADC_GLOBRES_GNR_Msk (0x0fUL << VADC_GLOBRES_GNR_Pos) /*!< VADC GLOBRES: GNR Mask */\r
-#define VADC_GLOBRES_CHNR_Pos 20 /*!< VADC GLOBRES: CHNR Position */\r
-#define VADC_GLOBRES_CHNR_Msk (0x1fUL << VADC_GLOBRES_CHNR_Pos) /*!< VADC GLOBRES: CHNR Mask */\r
-#define VADC_GLOBRES_EMUX_Pos 25 /*!< VADC GLOBRES: EMUX Position */\r
-#define VADC_GLOBRES_EMUX_Msk (0x07UL << VADC_GLOBRES_EMUX_Pos) /*!< VADC GLOBRES: EMUX Mask */\r
-#define VADC_GLOBRES_CRS_Pos 28 /*!< VADC GLOBRES: CRS Position */\r
-#define VADC_GLOBRES_CRS_Msk (0x03UL << VADC_GLOBRES_CRS_Pos) /*!< VADC GLOBRES: CRS Mask */\r
-#define VADC_GLOBRES_FCR_Pos 30 /*!< VADC GLOBRES: FCR Position */\r
-#define VADC_GLOBRES_FCR_Msk (0x01UL << VADC_GLOBRES_FCR_Pos) /*!< VADC GLOBRES: FCR Mask */\r
-#define VADC_GLOBRES_VF_Pos 31 /*!< VADC GLOBRES: VF Position */\r
-#define VADC_GLOBRES_VF_Msk (0x01UL << VADC_GLOBRES_VF_Pos) /*!< VADC GLOBRES: VF Mask */\r
-\r
-/* -------------------------------- VADC_GLOBRESD ------------------------------- */\r
-#define VADC_GLOBRESD_RESULT_Pos 0 /*!< VADC GLOBRESD: RESULT Position */\r
-#define VADC_GLOBRESD_RESULT_Msk (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos) /*!< VADC GLOBRESD: RESULT Mask */\r
-#define VADC_GLOBRESD_GNR_Pos 16 /*!< VADC GLOBRESD: GNR Position */\r
-#define VADC_GLOBRESD_GNR_Msk (0x0fUL << VADC_GLOBRESD_GNR_Pos) /*!< VADC GLOBRESD: GNR Mask */\r
-#define VADC_GLOBRESD_CHNR_Pos 20 /*!< VADC GLOBRESD: CHNR Position */\r
-#define VADC_GLOBRESD_CHNR_Msk (0x1fUL << VADC_GLOBRESD_CHNR_Pos) /*!< VADC GLOBRESD: CHNR Mask */\r
-#define VADC_GLOBRESD_EMUX_Pos 25 /*!< VADC GLOBRESD: EMUX Position */\r
-#define VADC_GLOBRESD_EMUX_Msk (0x07UL << VADC_GLOBRESD_EMUX_Pos) /*!< VADC GLOBRESD: EMUX Mask */\r
-#define VADC_GLOBRESD_CRS_Pos 28 /*!< VADC GLOBRESD: CRS Position */\r
-#define VADC_GLOBRESD_CRS_Msk (0x03UL << VADC_GLOBRESD_CRS_Pos) /*!< VADC GLOBRESD: CRS Mask */\r
-#define VADC_GLOBRESD_FCR_Pos 30 /*!< VADC GLOBRESD: FCR Position */\r
-#define VADC_GLOBRESD_FCR_Msk (0x01UL << VADC_GLOBRESD_FCR_Pos) /*!< VADC GLOBRESD: FCR Mask */\r
-#define VADC_GLOBRESD_VF_Pos 31 /*!< VADC GLOBRESD: VF Position */\r
-#define VADC_GLOBRESD_VF_Msk (0x01UL << VADC_GLOBRESD_VF_Pos) /*!< VADC GLOBRESD: VF Mask */\r
-\r
-/* -------------------------------- VADC_EMUXSEL -------------------------------- */\r
-#define VADC_EMUXSEL_EMUXGRP0_Pos 0 /*!< VADC EMUXSEL: EMUXGRP0 Position */\r
-#define VADC_EMUXSEL_EMUXGRP0_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos) /*!< VADC EMUXSEL: EMUXGRP0 Mask */\r
-#define VADC_EMUXSEL_EMUXGRP1_Pos 4 /*!< VADC EMUXSEL: EMUXGRP1 Position */\r
-#define VADC_EMUXSEL_EMUXGRP1_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos) /*!< VADC EMUXSEL: EMUXGRP1 Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'VADC_G' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- VADC_G_ARBCFG ------------------------------- */\r
-#define VADC_G_ARBCFG_ANONC_Pos 0 /*!< VADC_G ARBCFG: ANONC Position */\r
-#define VADC_G_ARBCFG_ANONC_Msk (0x03UL << VADC_G_ARBCFG_ANONC_Pos) /*!< VADC_G ARBCFG: ANONC Mask */\r
-#define VADC_G_ARBCFG_ARBRND_Pos 4 /*!< VADC_G ARBCFG: ARBRND Position */\r
-#define VADC_G_ARBCFG_ARBRND_Msk (0x03UL << VADC_G_ARBCFG_ARBRND_Pos) /*!< VADC_G ARBCFG: ARBRND Mask */\r
-#define VADC_G_ARBCFG_ARBM_Pos 7 /*!< VADC_G ARBCFG: ARBM Position */\r
-#define VADC_G_ARBCFG_ARBM_Msk (0x01UL << VADC_G_ARBCFG_ARBM_Pos) /*!< VADC_G ARBCFG: ARBM Mask */\r
-#define VADC_G_ARBCFG_ANONS_Pos 16 /*!< VADC_G ARBCFG: ANONS Position */\r
-#define VADC_G_ARBCFG_ANONS_Msk (0x03UL << VADC_G_ARBCFG_ANONS_Pos) /*!< VADC_G ARBCFG: ANONS Mask */\r
-#define VADC_G_ARBCFG_CSRC_Pos 18 /*!< VADC_G ARBCFG: CSRC Position */\r
-#define VADC_G_ARBCFG_CSRC_Msk (0x03UL << VADC_G_ARBCFG_CSRC_Pos) /*!< VADC_G ARBCFG: CSRC Mask */\r
-#define VADC_G_ARBCFG_CHNR_Pos 20 /*!< VADC_G ARBCFG: CHNR Position */\r
-#define VADC_G_ARBCFG_CHNR_Msk (0x1fUL << VADC_G_ARBCFG_CHNR_Pos) /*!< VADC_G ARBCFG: CHNR Mask */\r
-#define VADC_G_ARBCFG_SYNRUN_Pos 25 /*!< VADC_G ARBCFG: SYNRUN Position */\r
-#define VADC_G_ARBCFG_SYNRUN_Msk (0x01UL << VADC_G_ARBCFG_SYNRUN_Pos) /*!< VADC_G ARBCFG: SYNRUN Mask */\r
-#define VADC_G_ARBCFG_CAL_Pos 28 /*!< VADC_G ARBCFG: CAL Position */\r
-#define VADC_G_ARBCFG_CAL_Msk (0x01UL << VADC_G_ARBCFG_CAL_Pos) /*!< VADC_G ARBCFG: CAL Mask */\r
-#define VADC_G_ARBCFG_CALS_Pos 29 /*!< VADC_G ARBCFG: CALS Position */\r
-#define VADC_G_ARBCFG_CALS_Msk (0x01UL << VADC_G_ARBCFG_CALS_Pos) /*!< VADC_G ARBCFG: CALS Mask */\r
-#define VADC_G_ARBCFG_BUSY_Pos 30 /*!< VADC_G ARBCFG: BUSY Position */\r
-#define VADC_G_ARBCFG_BUSY_Msk (0x01UL << VADC_G_ARBCFG_BUSY_Pos) /*!< VADC_G ARBCFG: BUSY Mask */\r
-#define VADC_G_ARBCFG_SAMPLE_Pos 31 /*!< VADC_G ARBCFG: SAMPLE Position */\r
-#define VADC_G_ARBCFG_SAMPLE_Msk (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos) /*!< VADC_G ARBCFG: SAMPLE Mask */\r
-\r
-/* -------------------------------- VADC_G_ARBPR -------------------------------- */\r
-#define VADC_G_ARBPR_PRIO0_Pos 0 /*!< VADC_G ARBPR: PRIO0 Position */\r
-#define VADC_G_ARBPR_PRIO0_Msk (0x03UL << VADC_G_ARBPR_PRIO0_Pos) /*!< VADC_G ARBPR: PRIO0 Mask */\r
-#define VADC_G_ARBPR_CSM0_Pos 3 /*!< VADC_G ARBPR: CSM0 Position */\r
-#define VADC_G_ARBPR_CSM0_Msk (0x01UL << VADC_G_ARBPR_CSM0_Pos) /*!< VADC_G ARBPR: CSM0 Mask */\r
-#define VADC_G_ARBPR_PRIO1_Pos 4 /*!< VADC_G ARBPR: PRIO1 Position */\r
-#define VADC_G_ARBPR_PRIO1_Msk (0x03UL << VADC_G_ARBPR_PRIO1_Pos) /*!< VADC_G ARBPR: PRIO1 Mask */\r
-#define VADC_G_ARBPR_CSM1_Pos 7 /*!< VADC_G ARBPR: CSM1 Position */\r
-#define VADC_G_ARBPR_CSM1_Msk (0x01UL << VADC_G_ARBPR_CSM1_Pos) /*!< VADC_G ARBPR: CSM1 Mask */\r
-#define VADC_G_ARBPR_PRIO2_Pos 8 /*!< VADC_G ARBPR: PRIO2 Position */\r
-#define VADC_G_ARBPR_PRIO2_Msk (0x03UL << VADC_G_ARBPR_PRIO2_Pos) /*!< VADC_G ARBPR: PRIO2 Mask */\r
-#define VADC_G_ARBPR_CSM2_Pos 11 /*!< VADC_G ARBPR: CSM2 Position */\r
-#define VADC_G_ARBPR_CSM2_Msk (0x01UL << VADC_G_ARBPR_CSM2_Pos) /*!< VADC_G ARBPR: CSM2 Mask */\r
-#define VADC_G_ARBPR_ASEN0_Pos 24 /*!< VADC_G ARBPR: ASEN0 Position */\r
-#define VADC_G_ARBPR_ASEN0_Msk (0x01UL << VADC_G_ARBPR_ASEN0_Pos) /*!< VADC_G ARBPR: ASEN0 Mask */\r
-#define VADC_G_ARBPR_ASEN1_Pos 25 /*!< VADC_G ARBPR: ASEN1 Position */\r
-#define VADC_G_ARBPR_ASEN1_Msk (0x01UL << VADC_G_ARBPR_ASEN1_Pos) /*!< VADC_G ARBPR: ASEN1 Mask */\r
-#define VADC_G_ARBPR_ASEN2_Pos 26 /*!< VADC_G ARBPR: ASEN2 Position */\r
-#define VADC_G_ARBPR_ASEN2_Msk (0x01UL << VADC_G_ARBPR_ASEN2_Pos) /*!< VADC_G ARBPR: ASEN2 Mask */\r
-\r
-/* -------------------------------- VADC_G_CHASS -------------------------------- */\r
-#define VADC_G_CHASS_ASSCH0_Pos 0 /*!< VADC_G CHASS: ASSCH0 Position */\r
-#define VADC_G_CHASS_ASSCH0_Msk (0x01UL << VADC_G_CHASS_ASSCH0_Pos) /*!< VADC_G CHASS: ASSCH0 Mask */\r
-#define VADC_G_CHASS_ASSCH1_Pos 1 /*!< VADC_G CHASS: ASSCH1 Position */\r
-#define VADC_G_CHASS_ASSCH1_Msk (0x01UL << VADC_G_CHASS_ASSCH1_Pos) /*!< VADC_G CHASS: ASSCH1 Mask */\r
-#define VADC_G_CHASS_ASSCH2_Pos 2 /*!< VADC_G CHASS: ASSCH2 Position */\r
-#define VADC_G_CHASS_ASSCH2_Msk (0x01UL << VADC_G_CHASS_ASSCH2_Pos) /*!< VADC_G CHASS: ASSCH2 Mask */\r
-#define VADC_G_CHASS_ASSCH3_Pos 3 /*!< VADC_G CHASS: ASSCH3 Position */\r
-#define VADC_G_CHASS_ASSCH3_Msk (0x01UL << VADC_G_CHASS_ASSCH3_Pos) /*!< VADC_G CHASS: ASSCH3 Mask */\r
-#define VADC_G_CHASS_ASSCH4_Pos 4 /*!< VADC_G CHASS: ASSCH4 Position */\r
-#define VADC_G_CHASS_ASSCH4_Msk (0x01UL << VADC_G_CHASS_ASSCH4_Pos) /*!< VADC_G CHASS: ASSCH4 Mask */\r
-#define VADC_G_CHASS_ASSCH5_Pos 5 /*!< VADC_G CHASS: ASSCH5 Position */\r
-#define VADC_G_CHASS_ASSCH5_Msk (0x01UL << VADC_G_CHASS_ASSCH5_Pos) /*!< VADC_G CHASS: ASSCH5 Mask */\r
-#define VADC_G_CHASS_ASSCH6_Pos 6 /*!< VADC_G CHASS: ASSCH6 Position */\r
-#define VADC_G_CHASS_ASSCH6_Msk (0x01UL << VADC_G_CHASS_ASSCH6_Pos) /*!< VADC_G CHASS: ASSCH6 Mask */\r
-#define VADC_G_CHASS_ASSCH7_Pos 7 /*!< VADC_G CHASS: ASSCH7 Position */\r
-#define VADC_G_CHASS_ASSCH7_Msk (0x01UL << VADC_G_CHASS_ASSCH7_Pos) /*!< VADC_G CHASS: ASSCH7 Mask */\r
-\r
-/* -------------------------------- VADC_G_RRASS -------------------------------- */\r
-#define VADC_G_RRASS_ASSRR0_Pos 0 /*!< VADC_G RRASS: ASSRR0 Position */\r
-#define VADC_G_RRASS_ASSRR0_Msk (0x01UL << VADC_G_RRASS_ASSRR0_Pos) /*!< VADC_G RRASS: ASSRR0 Mask */\r
-#define VADC_G_RRASS_ASSRR1_Pos 1 /*!< VADC_G RRASS: ASSRR1 Position */\r
-#define VADC_G_RRASS_ASSRR1_Msk (0x01UL << VADC_G_RRASS_ASSRR1_Pos) /*!< VADC_G RRASS: ASSRR1 Mask */\r
-#define VADC_G_RRASS_ASSRR2_Pos 2 /*!< VADC_G RRASS: ASSRR2 Position */\r
-#define VADC_G_RRASS_ASSRR2_Msk (0x01UL << VADC_G_RRASS_ASSRR2_Pos) /*!< VADC_G RRASS: ASSRR2 Mask */\r
-#define VADC_G_RRASS_ASSRR3_Pos 3 /*!< VADC_G RRASS: ASSRR3 Position */\r
-#define VADC_G_RRASS_ASSRR3_Msk (0x01UL << VADC_G_RRASS_ASSRR3_Pos) /*!< VADC_G RRASS: ASSRR3 Mask */\r
-#define VADC_G_RRASS_ASSRR4_Pos 4 /*!< VADC_G RRASS: ASSRR4 Position */\r
-#define VADC_G_RRASS_ASSRR4_Msk (0x01UL << VADC_G_RRASS_ASSRR4_Pos) /*!< VADC_G RRASS: ASSRR4 Mask */\r
-#define VADC_G_RRASS_ASSRR5_Pos 5 /*!< VADC_G RRASS: ASSRR5 Position */\r
-#define VADC_G_RRASS_ASSRR5_Msk (0x01UL << VADC_G_RRASS_ASSRR5_Pos) /*!< VADC_G RRASS: ASSRR5 Mask */\r
-#define VADC_G_RRASS_ASSRR6_Pos 6 /*!< VADC_G RRASS: ASSRR6 Position */\r
-#define VADC_G_RRASS_ASSRR6_Msk (0x01UL << VADC_G_RRASS_ASSRR6_Pos) /*!< VADC_G RRASS: ASSRR6 Mask */\r
-#define VADC_G_RRASS_ASSRR7_Pos 7 /*!< VADC_G RRASS: ASSRR7 Position */\r
-#define VADC_G_RRASS_ASSRR7_Msk (0x01UL << VADC_G_RRASS_ASSRR7_Pos) /*!< VADC_G RRASS: ASSRR7 Mask */\r
-#define VADC_G_RRASS_ASSRR8_Pos 8 /*!< VADC_G RRASS: ASSRR8 Position */\r
-#define VADC_G_RRASS_ASSRR8_Msk (0x01UL << VADC_G_RRASS_ASSRR8_Pos) /*!< VADC_G RRASS: ASSRR8 Mask */\r
-#define VADC_G_RRASS_ASSRR9_Pos 9 /*!< VADC_G RRASS: ASSRR9 Position */\r
-#define VADC_G_RRASS_ASSRR9_Msk (0x01UL << VADC_G_RRASS_ASSRR9_Pos) /*!< VADC_G RRASS: ASSRR9 Mask */\r
-#define VADC_G_RRASS_ASSRR10_Pos 10 /*!< VADC_G RRASS: ASSRR10 Position */\r
-#define VADC_G_RRASS_ASSRR10_Msk (0x01UL << VADC_G_RRASS_ASSRR10_Pos) /*!< VADC_G RRASS: ASSRR10 Mask */\r
-#define VADC_G_RRASS_ASSRR11_Pos 11 /*!< VADC_G RRASS: ASSRR11 Position */\r
-#define VADC_G_RRASS_ASSRR11_Msk (0x01UL << VADC_G_RRASS_ASSRR11_Pos) /*!< VADC_G RRASS: ASSRR11 Mask */\r
-#define VADC_G_RRASS_ASSRR12_Pos 12 /*!< VADC_G RRASS: ASSRR12 Position */\r
-#define VADC_G_RRASS_ASSRR12_Msk (0x01UL << VADC_G_RRASS_ASSRR12_Pos) /*!< VADC_G RRASS: ASSRR12 Mask */\r
-#define VADC_G_RRASS_ASSRR13_Pos 13 /*!< VADC_G RRASS: ASSRR13 Position */\r
-#define VADC_G_RRASS_ASSRR13_Msk (0x01UL << VADC_G_RRASS_ASSRR13_Pos) /*!< VADC_G RRASS: ASSRR13 Mask */\r
-#define VADC_G_RRASS_ASSRR14_Pos 14 /*!< VADC_G RRASS: ASSRR14 Position */\r
-#define VADC_G_RRASS_ASSRR14_Msk (0x01UL << VADC_G_RRASS_ASSRR14_Pos) /*!< VADC_G RRASS: ASSRR14 Mask */\r
-#define VADC_G_RRASS_ASSRR15_Pos 15 /*!< VADC_G RRASS: ASSRR15 Position */\r
-#define VADC_G_RRASS_ASSRR15_Msk (0x01UL << VADC_G_RRASS_ASSRR15_Pos) /*!< VADC_G RRASS: ASSRR15 Mask */\r
-\r
-/* -------------------------------- VADC_G_ICLASS ------------------------------- */\r
-#define VADC_G_ICLASS_STCS_Pos 0 /*!< VADC_G ICLASS: STCS Position */\r
-#define VADC_G_ICLASS_STCS_Msk (0x1fUL << VADC_G_ICLASS_STCS_Pos) /*!< VADC_G ICLASS: STCS Mask */\r
-#define VADC_G_ICLASS_CMS_Pos 8 /*!< VADC_G ICLASS: CMS Position */\r
-#define VADC_G_ICLASS_CMS_Msk (0x07UL << VADC_G_ICLASS_CMS_Pos) /*!< VADC_G ICLASS: CMS Mask */\r
-#define VADC_G_ICLASS_STCE_Pos 16 /*!< VADC_G ICLASS: STCE Position */\r
-#define VADC_G_ICLASS_STCE_Msk (0x1fUL << VADC_G_ICLASS_STCE_Pos) /*!< VADC_G ICLASS: STCE Mask */\r
-#define VADC_G_ICLASS_CME_Pos 24 /*!< VADC_G ICLASS: CME Position */\r
-#define VADC_G_ICLASS_CME_Msk (0x07UL << VADC_G_ICLASS_CME_Pos) /*!< VADC_G ICLASS: CME Mask */\r
-\r
-/* -------------------------------- VADC_G_ALIAS -------------------------------- */\r
-#define VADC_G_ALIAS_ALIAS0_Pos 0 /*!< VADC_G ALIAS: ALIAS0 Position */\r
-#define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos) /*!< VADC_G ALIAS: ALIAS0 Mask */\r
-#define VADC_G_ALIAS_ALIAS1_Pos 8 /*!< VADC_G ALIAS: ALIAS1 Position */\r
-#define VADC_G_ALIAS_ALIAS1_Msk (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos) /*!< VADC_G ALIAS: ALIAS1 Mask */\r
-\r
-/* -------------------------------- VADC_G_BOUND -------------------------------- */\r
-#define VADC_G_BOUND_BOUNDARY0_Pos 0 /*!< VADC_G BOUND: BOUNDARY0 Position */\r
-#define VADC_G_BOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos) /*!< VADC_G BOUND: BOUNDARY0 Mask */\r
-#define VADC_G_BOUND_BOUNDARY1_Pos 16 /*!< VADC_G BOUND: BOUNDARY1 Position */\r
-#define VADC_G_BOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos) /*!< VADC_G BOUND: BOUNDARY1 Mask */\r
-\r
-/* -------------------------------- VADC_G_SYNCTR ------------------------------- */\r
-#define VADC_G_SYNCTR_STSEL_Pos 0 /*!< VADC_G SYNCTR: STSEL Position */\r
-#define VADC_G_SYNCTR_STSEL_Msk (0x03UL << VADC_G_SYNCTR_STSEL_Pos) /*!< VADC_G SYNCTR: STSEL Mask */\r
-#define VADC_G_SYNCTR_EVALR1_Pos 4 /*!< VADC_G SYNCTR: EVALR1 Position */\r
-#define VADC_G_SYNCTR_EVALR1_Msk (0x01UL << VADC_G_SYNCTR_EVALR1_Pos) /*!< VADC_G SYNCTR: EVALR1 Mask */\r
-\r
-/* --------------------------------- VADC_G_BFL --------------------------------- */\r
-#define VADC_G_BFL_BFL0_Pos 0 /*!< VADC_G BFL: BFL0 Position */\r
-#define VADC_G_BFL_BFL0_Msk (0x01UL << VADC_G_BFL_BFL0_Pos) /*!< VADC_G BFL: BFL0 Mask */\r
-#define VADC_G_BFL_BFL1_Pos 1 /*!< VADC_G BFL: BFL1 Position */\r
-#define VADC_G_BFL_BFL1_Msk (0x01UL << VADC_G_BFL_BFL1_Pos) /*!< VADC_G BFL: BFL1 Mask */\r
-#define VADC_G_BFL_BFL2_Pos 2 /*!< VADC_G BFL: BFL2 Position */\r
-#define VADC_G_BFL_BFL2_Msk (0x01UL << VADC_G_BFL_BFL2_Pos) /*!< VADC_G BFL: BFL2 Mask */\r
-#define VADC_G_BFL_BFL3_Pos 3 /*!< VADC_G BFL: BFL3 Position */\r
-#define VADC_G_BFL_BFL3_Msk (0x01UL << VADC_G_BFL_BFL3_Pos) /*!< VADC_G BFL: BFL3 Mask */\r
-#define VADC_G_BFL_BFA0_Pos 8 /*!< VADC_G BFL: BFA0 Position */\r
-#define VADC_G_BFL_BFA0_Msk (0x01UL << VADC_G_BFL_BFA0_Pos) /*!< VADC_G BFL: BFA0 Mask */\r
-#define VADC_G_BFL_BFA1_Pos 9 /*!< VADC_G BFL: BFA1 Position */\r
-#define VADC_G_BFL_BFA1_Msk (0x01UL << VADC_G_BFL_BFA1_Pos) /*!< VADC_G BFL: BFA1 Mask */\r
-#define VADC_G_BFL_BFA2_Pos 10 /*!< VADC_G BFL: BFA2 Position */\r
-#define VADC_G_BFL_BFA2_Msk (0x01UL << VADC_G_BFL_BFA2_Pos) /*!< VADC_G BFL: BFA2 Mask */\r
-#define VADC_G_BFL_BFA3_Pos 11 /*!< VADC_G BFL: BFA3 Position */\r
-#define VADC_G_BFL_BFA3_Msk (0x01UL << VADC_G_BFL_BFA3_Pos) /*!< VADC_G BFL: BFA3 Mask */\r
-#define VADC_G_BFL_BFI0_Pos 16 /*!< VADC_G BFL: BFI0 Position */\r
-#define VADC_G_BFL_BFI0_Msk (0x01UL << VADC_G_BFL_BFI0_Pos) /*!< VADC_G BFL: BFI0 Mask */\r
-#define VADC_G_BFL_BFI1_Pos 17 /*!< VADC_G BFL: BFI1 Position */\r
-#define VADC_G_BFL_BFI1_Msk (0x01UL << VADC_G_BFL_BFI1_Pos) /*!< VADC_G BFL: BFI1 Mask */\r
-#define VADC_G_BFL_BFI2_Pos 18 /*!< VADC_G BFL: BFI2 Position */\r
-#define VADC_G_BFL_BFI2_Msk (0x01UL << VADC_G_BFL_BFI2_Pos) /*!< VADC_G BFL: BFI2 Mask */\r
-#define VADC_G_BFL_BFI3_Pos 19 /*!< VADC_G BFL: BFI3 Position */\r
-#define VADC_G_BFL_BFI3_Msk (0x01UL << VADC_G_BFL_BFI3_Pos) /*!< VADC_G BFL: BFI3 Mask */\r
-\r
-/* --------------------------------- VADC_G_BFLS -------------------------------- */\r
-#define VADC_G_BFLS_BFC0_Pos 0 /*!< VADC_G BFLS: BFC0 Position */\r
-#define VADC_G_BFLS_BFC0_Msk (0x01UL << VADC_G_BFLS_BFC0_Pos) /*!< VADC_G BFLS: BFC0 Mask */\r
-#define VADC_G_BFLS_BFC1_Pos 1 /*!< VADC_G BFLS: BFC1 Position */\r
-#define VADC_G_BFLS_BFC1_Msk (0x01UL << VADC_G_BFLS_BFC1_Pos) /*!< VADC_G BFLS: BFC1 Mask */\r
-#define VADC_G_BFLS_BFC2_Pos 2 /*!< VADC_G BFLS: BFC2 Position */\r
-#define VADC_G_BFLS_BFC2_Msk (0x01UL << VADC_G_BFLS_BFC2_Pos) /*!< VADC_G BFLS: BFC2 Mask */\r
-#define VADC_G_BFLS_BFC3_Pos 3 /*!< VADC_G BFLS: BFC3 Position */\r
-#define VADC_G_BFLS_BFC3_Msk (0x01UL << VADC_G_BFLS_BFC3_Pos) /*!< VADC_G BFLS: BFC3 Mask */\r
-#define VADC_G_BFLS_BFS0_Pos 16 /*!< VADC_G BFLS: BFS0 Position */\r
-#define VADC_G_BFLS_BFS0_Msk (0x01UL << VADC_G_BFLS_BFS0_Pos) /*!< VADC_G BFLS: BFS0 Mask */\r
-#define VADC_G_BFLS_BFS1_Pos 17 /*!< VADC_G BFLS: BFS1 Position */\r
-#define VADC_G_BFLS_BFS1_Msk (0x01UL << VADC_G_BFLS_BFS1_Pos) /*!< VADC_G BFLS: BFS1 Mask */\r
-#define VADC_G_BFLS_BFS2_Pos 18 /*!< VADC_G BFLS: BFS2 Position */\r
-#define VADC_G_BFLS_BFS2_Msk (0x01UL << VADC_G_BFLS_BFS2_Pos) /*!< VADC_G BFLS: BFS2 Mask */\r
-#define VADC_G_BFLS_BFS3_Pos 19 /*!< VADC_G BFLS: BFS3 Position */\r
-#define VADC_G_BFLS_BFS3_Msk (0x01UL << VADC_G_BFLS_BFS3_Pos) /*!< VADC_G BFLS: BFS3 Mask */\r
-\r
-/* --------------------------------- VADC_G_BFLC -------------------------------- */\r
-#define VADC_G_BFLC_BFM0_Pos 0 /*!< VADC_G BFLC: BFM0 Position */\r
-#define VADC_G_BFLC_BFM0_Msk (0x0fUL << VADC_G_BFLC_BFM0_Pos) /*!< VADC_G BFLC: BFM0 Mask */\r
-#define VADC_G_BFLC_BFM1_Pos 4 /*!< VADC_G BFLC: BFM1 Position */\r
-#define VADC_G_BFLC_BFM1_Msk (0x0fUL << VADC_G_BFLC_BFM1_Pos) /*!< VADC_G BFLC: BFM1 Mask */\r
-#define VADC_G_BFLC_BFM2_Pos 8 /*!< VADC_G BFLC: BFM2 Position */\r
-#define VADC_G_BFLC_BFM2_Msk (0x0fUL << VADC_G_BFLC_BFM2_Pos) /*!< VADC_G BFLC: BFM2 Mask */\r
-#define VADC_G_BFLC_BFM3_Pos 12 /*!< VADC_G BFLC: BFM3 Position */\r
-#define VADC_G_BFLC_BFM3_Msk (0x0fUL << VADC_G_BFLC_BFM3_Pos) /*!< VADC_G BFLC: BFM3 Mask */\r
-\r
-/* -------------------------------- VADC_G_BFLNP -------------------------------- */\r
-#define VADC_G_BFLNP_BFL0NP_Pos 0 /*!< VADC_G BFLNP: BFL0NP Position */\r
-#define VADC_G_BFLNP_BFL0NP_Msk (0x0fUL << VADC_G_BFLNP_BFL0NP_Pos) /*!< VADC_G BFLNP: BFL0NP Mask */\r
-#define VADC_G_BFLNP_BFL1NP_Pos 4 /*!< VADC_G BFLNP: BFL1NP Position */\r
-#define VADC_G_BFLNP_BFL1NP_Msk (0x0fUL << VADC_G_BFLNP_BFL1NP_Pos) /*!< VADC_G BFLNP: BFL1NP Mask */\r
-#define VADC_G_BFLNP_BFL2NP_Pos 8 /*!< VADC_G BFLNP: BFL2NP Position */\r
-#define VADC_G_BFLNP_BFL2NP_Msk (0x0fUL << VADC_G_BFLNP_BFL2NP_Pos) /*!< VADC_G BFLNP: BFL2NP Mask */\r
-#define VADC_G_BFLNP_BFL3NP_Pos 12 /*!< VADC_G BFLNP: BFL3NP Position */\r
-#define VADC_G_BFLNP_BFL3NP_Msk (0x0fUL << VADC_G_BFLNP_BFL3NP_Pos) /*!< VADC_G BFLNP: BFL3NP Mask */\r
-\r
-/* -------------------------------- VADC_G_QCTRL0 ------------------------------- */\r
-#define VADC_G_QCTRL0_SRCRESREG_Pos 0 /*!< VADC_G QCTRL0: SRCRESREG Position */\r
-#define VADC_G_QCTRL0_SRCRESREG_Msk (0x0fUL << VADC_G_QCTRL0_SRCRESREG_Pos) /*!< VADC_G QCTRL0: SRCRESREG Mask */\r
-#define VADC_G_QCTRL0_XTSEL_Pos 8 /*!< VADC_G QCTRL0: XTSEL Position */\r
-#define VADC_G_QCTRL0_XTSEL_Msk (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos) /*!< VADC_G QCTRL0: XTSEL Mask */\r
-#define VADC_G_QCTRL0_XTLVL_Pos 12 /*!< VADC_G QCTRL0: XTLVL Position */\r
-#define VADC_G_QCTRL0_XTLVL_Msk (0x01UL << VADC_G_QCTRL0_XTLVL_Pos) /*!< VADC_G QCTRL0: XTLVL Mask */\r
-#define VADC_G_QCTRL0_XTMODE_Pos 13 /*!< VADC_G QCTRL0: XTMODE Position */\r
-#define VADC_G_QCTRL0_XTMODE_Msk (0x03UL << VADC_G_QCTRL0_XTMODE_Pos) /*!< VADC_G QCTRL0: XTMODE Mask */\r
-#define VADC_G_QCTRL0_XTWC_Pos 15 /*!< VADC_G QCTRL0: XTWC Position */\r
-#define VADC_G_QCTRL0_XTWC_Msk (0x01UL << VADC_G_QCTRL0_XTWC_Pos) /*!< VADC_G QCTRL0: XTWC Mask */\r
-#define VADC_G_QCTRL0_GTSEL_Pos 16 /*!< VADC_G QCTRL0: GTSEL Position */\r
-#define VADC_G_QCTRL0_GTSEL_Msk (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos) /*!< VADC_G QCTRL0: GTSEL Mask */\r
-#define VADC_G_QCTRL0_GTLVL_Pos 20 /*!< VADC_G QCTRL0: GTLVL Position */\r
-#define VADC_G_QCTRL0_GTLVL_Msk (0x01UL << VADC_G_QCTRL0_GTLVL_Pos) /*!< VADC_G QCTRL0: GTLVL Mask */\r
-#define VADC_G_QCTRL0_GTWC_Pos 23 /*!< VADC_G QCTRL0: GTWC Position */\r
-#define VADC_G_QCTRL0_GTWC_Msk (0x01UL << VADC_G_QCTRL0_GTWC_Pos) /*!< VADC_G QCTRL0: GTWC Mask */\r
-#define VADC_G_QCTRL0_TMEN_Pos 28 /*!< VADC_G QCTRL0: TMEN Position */\r
-#define VADC_G_QCTRL0_TMEN_Msk (0x01UL << VADC_G_QCTRL0_TMEN_Pos) /*!< VADC_G QCTRL0: TMEN Mask */\r
-#define VADC_G_QCTRL0_TMWC_Pos 31 /*!< VADC_G QCTRL0: TMWC Position */\r
-#define VADC_G_QCTRL0_TMWC_Msk (0x01UL << VADC_G_QCTRL0_TMWC_Pos) /*!< VADC_G QCTRL0: TMWC Mask */\r
-\r
-/* --------------------------------- VADC_G_QMR0 -------------------------------- */\r
-#define VADC_G_QMR0_ENGT_Pos 0 /*!< VADC_G QMR0: ENGT Position */\r
-#define VADC_G_QMR0_ENGT_Msk (0x03UL << VADC_G_QMR0_ENGT_Pos) /*!< VADC_G QMR0: ENGT Mask */\r
-#define VADC_G_QMR0_ENTR_Pos 2 /*!< VADC_G QMR0: ENTR Position */\r
-#define VADC_G_QMR0_ENTR_Msk (0x01UL << VADC_G_QMR0_ENTR_Pos) /*!< VADC_G QMR0: ENTR Mask */\r
-#define VADC_G_QMR0_CLRV_Pos 8 /*!< VADC_G QMR0: CLRV Position */\r
-#define VADC_G_QMR0_CLRV_Msk (0x01UL << VADC_G_QMR0_CLRV_Pos) /*!< VADC_G QMR0: CLRV Mask */\r
-#define VADC_G_QMR0_TREV_Pos 9 /*!< VADC_G QMR0: TREV Position */\r
-#define VADC_G_QMR0_TREV_Msk (0x01UL << VADC_G_QMR0_TREV_Pos) /*!< VADC_G QMR0: TREV Mask */\r
-#define VADC_G_QMR0_FLUSH_Pos 10 /*!< VADC_G QMR0: FLUSH Position */\r
-#define VADC_G_QMR0_FLUSH_Msk (0x01UL << VADC_G_QMR0_FLUSH_Pos) /*!< VADC_G QMR0: FLUSH Mask */\r
-#define VADC_G_QMR0_CEV_Pos 11 /*!< VADC_G QMR0: CEV Position */\r
-#define VADC_G_QMR0_CEV_Msk (0x01UL << VADC_G_QMR0_CEV_Pos) /*!< VADC_G QMR0: CEV Mask */\r
-#define VADC_G_QMR0_RPTDIS_Pos 16 /*!< VADC_G QMR0: RPTDIS Position */\r
-#define VADC_G_QMR0_RPTDIS_Msk (0x01UL << VADC_G_QMR0_RPTDIS_Pos) /*!< VADC_G QMR0: RPTDIS Mask */\r
-\r
-/* --------------------------------- VADC_G_QSR0 -------------------------------- */\r
-#define VADC_G_QSR0_FILL_Pos 0 /*!< VADC_G QSR0: FILL Position */\r
-#define VADC_G_QSR0_FILL_Msk (0x0fUL << VADC_G_QSR0_FILL_Pos) /*!< VADC_G QSR0: FILL Mask */\r
-#define VADC_G_QSR0_EMPTY_Pos 5 /*!< VADC_G QSR0: EMPTY Position */\r
-#define VADC_G_QSR0_EMPTY_Msk (0x01UL << VADC_G_QSR0_EMPTY_Pos) /*!< VADC_G QSR0: EMPTY Mask */\r
-#define VADC_G_QSR0_REQGT_Pos 7 /*!< VADC_G QSR0: REQGT Position */\r
-#define VADC_G_QSR0_REQGT_Msk (0x01UL << VADC_G_QSR0_REQGT_Pos) /*!< VADC_G QSR0: REQGT Mask */\r
-#define VADC_G_QSR0_EV_Pos 8 /*!< VADC_G QSR0: EV Position */\r
-#define VADC_G_QSR0_EV_Msk (0x01UL << VADC_G_QSR0_EV_Pos) /*!< VADC_G QSR0: EV Mask */\r
-\r
-/* --------------------------------- VADC_G_Q0R0 -------------------------------- */\r
-#define VADC_G_Q0R0_REQCHNR_Pos 0 /*!< VADC_G Q0R0: REQCHNR Position */\r
-#define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos) /*!< VADC_G Q0R0: REQCHNR Mask */\r
-#define VADC_G_Q0R0_RF_Pos 5 /*!< VADC_G Q0R0: RF Position */\r
-#define VADC_G_Q0R0_RF_Msk (0x01UL << VADC_G_Q0R0_RF_Pos) /*!< VADC_G Q0R0: RF Mask */\r
-#define VADC_G_Q0R0_ENSI_Pos 6 /*!< VADC_G Q0R0: ENSI Position */\r
-#define VADC_G_Q0R0_ENSI_Msk (0x01UL << VADC_G_Q0R0_ENSI_Pos) /*!< VADC_G Q0R0: ENSI Mask */\r
-#define VADC_G_Q0R0_EXTR_Pos 7 /*!< VADC_G Q0R0: EXTR Position */\r
-#define VADC_G_Q0R0_EXTR_Msk (0x01UL << VADC_G_Q0R0_EXTR_Pos) /*!< VADC_G Q0R0: EXTR Mask */\r
-#define VADC_G_Q0R0_V_Pos 8 /*!< VADC_G Q0R0: V Position */\r
-#define VADC_G_Q0R0_V_Msk (0x01UL << VADC_G_Q0R0_V_Pos) /*!< VADC_G Q0R0: V Mask */\r
-\r
-/* -------------------------------- VADC_G_QINR0 -------------------------------- */\r
-#define VADC_G_QINR0_REQCHNR_Pos 0 /*!< VADC_G QINR0: REQCHNR Position */\r
-#define VADC_G_QINR0_REQCHNR_Msk (0x1fUL << VADC_G_QINR0_REQCHNR_Pos) /*!< VADC_G QINR0: REQCHNR Mask */\r
-#define VADC_G_QINR0_RF_Pos 5 /*!< VADC_G QINR0: RF Position */\r
-#define VADC_G_QINR0_RF_Msk (0x01UL << VADC_G_QINR0_RF_Pos) /*!< VADC_G QINR0: RF Mask */\r
-#define VADC_G_QINR0_ENSI_Pos 6 /*!< VADC_G QINR0: ENSI Position */\r
-#define VADC_G_QINR0_ENSI_Msk (0x01UL << VADC_G_QINR0_ENSI_Pos) /*!< VADC_G QINR0: ENSI Mask */\r
-#define VADC_G_QINR0_EXTR_Pos 7 /*!< VADC_G QINR0: EXTR Position */\r
-#define VADC_G_QINR0_EXTR_Msk (0x01UL << VADC_G_QINR0_EXTR_Pos) /*!< VADC_G QINR0: EXTR Mask */\r
-\r
-/* -------------------------------- VADC_G_QBUR0 -------------------------------- */\r
-#define VADC_G_QBUR0_REQCHNR_Pos 0 /*!< VADC_G QBUR0: REQCHNR Position */\r
-#define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos) /*!< VADC_G QBUR0: REQCHNR Mask */\r
-#define VADC_G_QBUR0_RF_Pos 5 /*!< VADC_G QBUR0: RF Position */\r
-#define VADC_G_QBUR0_RF_Msk (0x01UL << VADC_G_QBUR0_RF_Pos) /*!< VADC_G QBUR0: RF Mask */\r
-#define VADC_G_QBUR0_ENSI_Pos 6 /*!< VADC_G QBUR0: ENSI Position */\r
-#define VADC_G_QBUR0_ENSI_Msk (0x01UL << VADC_G_QBUR0_ENSI_Pos) /*!< VADC_G QBUR0: ENSI Mask */\r
-#define VADC_G_QBUR0_EXTR_Pos 7 /*!< VADC_G QBUR0: EXTR Position */\r
-#define VADC_G_QBUR0_EXTR_Msk (0x01UL << VADC_G_QBUR0_EXTR_Pos) /*!< VADC_G QBUR0: EXTR Mask */\r
-#define VADC_G_QBUR0_V_Pos 8 /*!< VADC_G QBUR0: V Position */\r
-#define VADC_G_QBUR0_V_Msk (0x01UL << VADC_G_QBUR0_V_Pos) /*!< VADC_G QBUR0: V Mask */\r
-\r
-/* -------------------------------- VADC_G_ASCTRL ------------------------------- */\r
-#define VADC_G_ASCTRL_SRCRESREG_Pos 0 /*!< VADC_G ASCTRL: SRCRESREG Position */\r
-#define VADC_G_ASCTRL_SRCRESREG_Msk (0x0fUL << VADC_G_ASCTRL_SRCRESREG_Pos) /*!< VADC_G ASCTRL: SRCRESREG Mask */\r
-#define VADC_G_ASCTRL_XTSEL_Pos 8 /*!< VADC_G ASCTRL: XTSEL Position */\r
-#define VADC_G_ASCTRL_XTSEL_Msk (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos) /*!< VADC_G ASCTRL: XTSEL Mask */\r
-#define VADC_G_ASCTRL_XTLVL_Pos 12 /*!< VADC_G ASCTRL: XTLVL Position */\r
-#define VADC_G_ASCTRL_XTLVL_Msk (0x01UL << VADC_G_ASCTRL_XTLVL_Pos) /*!< VADC_G ASCTRL: XTLVL Mask */\r
-#define VADC_G_ASCTRL_XTMODE_Pos 13 /*!< VADC_G ASCTRL: XTMODE Position */\r
-#define VADC_G_ASCTRL_XTMODE_Msk (0x03UL << VADC_G_ASCTRL_XTMODE_Pos) /*!< VADC_G ASCTRL: XTMODE Mask */\r
-#define VADC_G_ASCTRL_XTWC_Pos 15 /*!< VADC_G ASCTRL: XTWC Position */\r
-#define VADC_G_ASCTRL_XTWC_Msk (0x01UL << VADC_G_ASCTRL_XTWC_Pos) /*!< VADC_G ASCTRL: XTWC Mask */\r
-#define VADC_G_ASCTRL_GTSEL_Pos 16 /*!< VADC_G ASCTRL: GTSEL Position */\r
-#define VADC_G_ASCTRL_GTSEL_Msk (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos) /*!< VADC_G ASCTRL: GTSEL Mask */\r
-#define VADC_G_ASCTRL_GTLVL_Pos 20 /*!< VADC_G ASCTRL: GTLVL Position */\r
-#define VADC_G_ASCTRL_GTLVL_Msk (0x01UL << VADC_G_ASCTRL_GTLVL_Pos) /*!< VADC_G ASCTRL: GTLVL Mask */\r
-#define VADC_G_ASCTRL_GTWC_Pos 23 /*!< VADC_G ASCTRL: GTWC Position */\r
-#define VADC_G_ASCTRL_GTWC_Msk (0x01UL << VADC_G_ASCTRL_GTWC_Pos) /*!< VADC_G ASCTRL: GTWC Mask */\r
-#define VADC_G_ASCTRL_TMEN_Pos 28 /*!< VADC_G ASCTRL: TMEN Position */\r
-#define VADC_G_ASCTRL_TMEN_Msk (0x01UL << VADC_G_ASCTRL_TMEN_Pos) /*!< VADC_G ASCTRL: TMEN Mask */\r
-#define VADC_G_ASCTRL_TMWC_Pos 31 /*!< VADC_G ASCTRL: TMWC Position */\r
-#define VADC_G_ASCTRL_TMWC_Msk (0x01UL << VADC_G_ASCTRL_TMWC_Pos) /*!< VADC_G ASCTRL: TMWC Mask */\r
-\r
-/* --------------------------------- VADC_G_ASMR -------------------------------- */\r
-#define VADC_G_ASMR_ENGT_Pos 0 /*!< VADC_G ASMR: ENGT Position */\r
-#define VADC_G_ASMR_ENGT_Msk (0x03UL << VADC_G_ASMR_ENGT_Pos) /*!< VADC_G ASMR: ENGT Mask */\r
-#define VADC_G_ASMR_ENTR_Pos 2 /*!< VADC_G ASMR: ENTR Position */\r
-#define VADC_G_ASMR_ENTR_Msk (0x01UL << VADC_G_ASMR_ENTR_Pos) /*!< VADC_G ASMR: ENTR Mask */\r
-#define VADC_G_ASMR_ENSI_Pos 3 /*!< VADC_G ASMR: ENSI Position */\r
-#define VADC_G_ASMR_ENSI_Msk (0x01UL << VADC_G_ASMR_ENSI_Pos) /*!< VADC_G ASMR: ENSI Mask */\r
-#define VADC_G_ASMR_SCAN_Pos 4 /*!< VADC_G ASMR: SCAN Position */\r
-#define VADC_G_ASMR_SCAN_Msk (0x01UL << VADC_G_ASMR_SCAN_Pos) /*!< VADC_G ASMR: SCAN Mask */\r
-#define VADC_G_ASMR_LDM_Pos 5 /*!< VADC_G ASMR: LDM Position */\r
-#define VADC_G_ASMR_LDM_Msk (0x01UL << VADC_G_ASMR_LDM_Pos) /*!< VADC_G ASMR: LDM Mask */\r
-#define VADC_G_ASMR_REQGT_Pos 7 /*!< VADC_G ASMR: REQGT Position */\r
-#define VADC_G_ASMR_REQGT_Msk (0x01UL << VADC_G_ASMR_REQGT_Pos) /*!< VADC_G ASMR: REQGT Mask */\r
-#define VADC_G_ASMR_CLRPND_Pos 8 /*!< VADC_G ASMR: CLRPND Position */\r
-#define VADC_G_ASMR_CLRPND_Msk (0x01UL << VADC_G_ASMR_CLRPND_Pos) /*!< VADC_G ASMR: CLRPND Mask */\r
-#define VADC_G_ASMR_LDEV_Pos 9 /*!< VADC_G ASMR: LDEV Position */\r
-#define VADC_G_ASMR_LDEV_Msk (0x01UL << VADC_G_ASMR_LDEV_Pos) /*!< VADC_G ASMR: LDEV Mask */\r
-#define VADC_G_ASMR_RPTDIS_Pos 16 /*!< VADC_G ASMR: RPTDIS Position */\r
-#define VADC_G_ASMR_RPTDIS_Msk (0x01UL << VADC_G_ASMR_RPTDIS_Pos) /*!< VADC_G ASMR: RPTDIS Mask */\r
-\r
-/* -------------------------------- VADC_G_ASSEL -------------------------------- */\r
-#define VADC_G_ASSEL_CHSEL0_Pos 0 /*!< VADC_G ASSEL: CHSEL0 Position */\r
-#define VADC_G_ASSEL_CHSEL0_Msk (0x01UL << VADC_G_ASSEL_CHSEL0_Pos) /*!< VADC_G ASSEL: CHSEL0 Mask */\r
-#define VADC_G_ASSEL_CHSEL1_Pos 1 /*!< VADC_G ASSEL: CHSEL1 Position */\r
-#define VADC_G_ASSEL_CHSEL1_Msk (0x01UL << VADC_G_ASSEL_CHSEL1_Pos) /*!< VADC_G ASSEL: CHSEL1 Mask */\r
-#define VADC_G_ASSEL_CHSEL2_Pos 2 /*!< VADC_G ASSEL: CHSEL2 Position */\r
-#define VADC_G_ASSEL_CHSEL2_Msk (0x01UL << VADC_G_ASSEL_CHSEL2_Pos) /*!< VADC_G ASSEL: CHSEL2 Mask */\r
-#define VADC_G_ASSEL_CHSEL3_Pos 3 /*!< VADC_G ASSEL: CHSEL3 Position */\r
-#define VADC_G_ASSEL_CHSEL3_Msk (0x01UL << VADC_G_ASSEL_CHSEL3_Pos) /*!< VADC_G ASSEL: CHSEL3 Mask */\r
-#define VADC_G_ASSEL_CHSEL4_Pos 4 /*!< VADC_G ASSEL: CHSEL4 Position */\r
-#define VADC_G_ASSEL_CHSEL4_Msk (0x01UL << VADC_G_ASSEL_CHSEL4_Pos) /*!< VADC_G ASSEL: CHSEL4 Mask */\r
-#define VADC_G_ASSEL_CHSEL5_Pos 5 /*!< VADC_G ASSEL: CHSEL5 Position */\r
-#define VADC_G_ASSEL_CHSEL5_Msk (0x01UL << VADC_G_ASSEL_CHSEL5_Pos) /*!< VADC_G ASSEL: CHSEL5 Mask */\r
-#define VADC_G_ASSEL_CHSEL6_Pos 6 /*!< VADC_G ASSEL: CHSEL6 Position */\r
-#define VADC_G_ASSEL_CHSEL6_Msk (0x01UL << VADC_G_ASSEL_CHSEL6_Pos) /*!< VADC_G ASSEL: CHSEL6 Mask */\r
-#define VADC_G_ASSEL_CHSEL7_Pos 7 /*!< VADC_G ASSEL: CHSEL7 Position */\r
-#define VADC_G_ASSEL_CHSEL7_Msk (0x01UL << VADC_G_ASSEL_CHSEL7_Pos) /*!< VADC_G ASSEL: CHSEL7 Mask */\r
-\r
-/* -------------------------------- VADC_G_ASPND -------------------------------- */\r
-#define VADC_G_ASPND_CHPND0_Pos 0 /*!< VADC_G ASPND: CHPND0 Position */\r
-#define VADC_G_ASPND_CHPND0_Msk (0x01UL << VADC_G_ASPND_CHPND0_Pos) /*!< VADC_G ASPND: CHPND0 Mask */\r
-#define VADC_G_ASPND_CHPND1_Pos 1 /*!< VADC_G ASPND: CHPND1 Position */\r
-#define VADC_G_ASPND_CHPND1_Msk (0x01UL << VADC_G_ASPND_CHPND1_Pos) /*!< VADC_G ASPND: CHPND1 Mask */\r
-#define VADC_G_ASPND_CHPND2_Pos 2 /*!< VADC_G ASPND: CHPND2 Position */\r
-#define VADC_G_ASPND_CHPND2_Msk (0x01UL << VADC_G_ASPND_CHPND2_Pos) /*!< VADC_G ASPND: CHPND2 Mask */\r
-#define VADC_G_ASPND_CHPND3_Pos 3 /*!< VADC_G ASPND: CHPND3 Position */\r
-#define VADC_G_ASPND_CHPND3_Msk (0x01UL << VADC_G_ASPND_CHPND3_Pos) /*!< VADC_G ASPND: CHPND3 Mask */\r
-#define VADC_G_ASPND_CHPND4_Pos 4 /*!< VADC_G ASPND: CHPND4 Position */\r
-#define VADC_G_ASPND_CHPND4_Msk (0x01UL << VADC_G_ASPND_CHPND4_Pos) /*!< VADC_G ASPND: CHPND4 Mask */\r
-#define VADC_G_ASPND_CHPND5_Pos 5 /*!< VADC_G ASPND: CHPND5 Position */\r
-#define VADC_G_ASPND_CHPND5_Msk (0x01UL << VADC_G_ASPND_CHPND5_Pos) /*!< VADC_G ASPND: CHPND5 Mask */\r
-#define VADC_G_ASPND_CHPND6_Pos 6 /*!< VADC_G ASPND: CHPND6 Position */\r
-#define VADC_G_ASPND_CHPND6_Msk (0x01UL << VADC_G_ASPND_CHPND6_Pos) /*!< VADC_G ASPND: CHPND6 Mask */\r
-#define VADC_G_ASPND_CHPND7_Pos 7 /*!< VADC_G ASPND: CHPND7 Position */\r
-#define VADC_G_ASPND_CHPND7_Msk (0x01UL << VADC_G_ASPND_CHPND7_Pos) /*!< VADC_G ASPND: CHPND7 Mask */\r
-\r
-/* -------------------------------- VADC_G_CEFLAG ------------------------------- */\r
-#define VADC_G_CEFLAG_CEV0_Pos 0 /*!< VADC_G CEFLAG: CEV0 Position */\r
-#define VADC_G_CEFLAG_CEV0_Msk (0x01UL << VADC_G_CEFLAG_CEV0_Pos) /*!< VADC_G CEFLAG: CEV0 Mask */\r
-#define VADC_G_CEFLAG_CEV1_Pos 1 /*!< VADC_G CEFLAG: CEV1 Position */\r
-#define VADC_G_CEFLAG_CEV1_Msk (0x01UL << VADC_G_CEFLAG_CEV1_Pos) /*!< VADC_G CEFLAG: CEV1 Mask */\r
-#define VADC_G_CEFLAG_CEV2_Pos 2 /*!< VADC_G CEFLAG: CEV2 Position */\r
-#define VADC_G_CEFLAG_CEV2_Msk (0x01UL << VADC_G_CEFLAG_CEV2_Pos) /*!< VADC_G CEFLAG: CEV2 Mask */\r
-#define VADC_G_CEFLAG_CEV3_Pos 3 /*!< VADC_G CEFLAG: CEV3 Position */\r
-#define VADC_G_CEFLAG_CEV3_Msk (0x01UL << VADC_G_CEFLAG_CEV3_Pos) /*!< VADC_G CEFLAG: CEV3 Mask */\r
-#define VADC_G_CEFLAG_CEV4_Pos 4 /*!< VADC_G CEFLAG: CEV4 Position */\r
-#define VADC_G_CEFLAG_CEV4_Msk (0x01UL << VADC_G_CEFLAG_CEV4_Pos) /*!< VADC_G CEFLAG: CEV4 Mask */\r
-#define VADC_G_CEFLAG_CEV5_Pos 5 /*!< VADC_G CEFLAG: CEV5 Position */\r
-#define VADC_G_CEFLAG_CEV5_Msk (0x01UL << VADC_G_CEFLAG_CEV5_Pos) /*!< VADC_G CEFLAG: CEV5 Mask */\r
-#define VADC_G_CEFLAG_CEV6_Pos 6 /*!< VADC_G CEFLAG: CEV6 Position */\r
-#define VADC_G_CEFLAG_CEV6_Msk (0x01UL << VADC_G_CEFLAG_CEV6_Pos) /*!< VADC_G CEFLAG: CEV6 Mask */\r
-#define VADC_G_CEFLAG_CEV7_Pos 7 /*!< VADC_G CEFLAG: CEV7 Position */\r
-#define VADC_G_CEFLAG_CEV7_Msk (0x01UL << VADC_G_CEFLAG_CEV7_Pos) /*!< VADC_G CEFLAG: CEV7 Mask */\r
-\r
-/* -------------------------------- VADC_G_REFLAG ------------------------------- */\r
-#define VADC_G_REFLAG_REV0_Pos 0 /*!< VADC_G REFLAG: REV0 Position */\r
-#define VADC_G_REFLAG_REV0_Msk (0x01UL << VADC_G_REFLAG_REV0_Pos) /*!< VADC_G REFLAG: REV0 Mask */\r
-#define VADC_G_REFLAG_REV1_Pos 1 /*!< VADC_G REFLAG: REV1 Position */\r
-#define VADC_G_REFLAG_REV1_Msk (0x01UL << VADC_G_REFLAG_REV1_Pos) /*!< VADC_G REFLAG: REV1 Mask */\r
-#define VADC_G_REFLAG_REV2_Pos 2 /*!< VADC_G REFLAG: REV2 Position */\r
-#define VADC_G_REFLAG_REV2_Msk (0x01UL << VADC_G_REFLAG_REV2_Pos) /*!< VADC_G REFLAG: REV2 Mask */\r
-#define VADC_G_REFLAG_REV3_Pos 3 /*!< VADC_G REFLAG: REV3 Position */\r
-#define VADC_G_REFLAG_REV3_Msk (0x01UL << VADC_G_REFLAG_REV3_Pos) /*!< VADC_G REFLAG: REV3 Mask */\r
-#define VADC_G_REFLAG_REV4_Pos 4 /*!< VADC_G REFLAG: REV4 Position */\r
-#define VADC_G_REFLAG_REV4_Msk (0x01UL << VADC_G_REFLAG_REV4_Pos) /*!< VADC_G REFLAG: REV4 Mask */\r
-#define VADC_G_REFLAG_REV5_Pos 5 /*!< VADC_G REFLAG: REV5 Position */\r
-#define VADC_G_REFLAG_REV5_Msk (0x01UL << VADC_G_REFLAG_REV5_Pos) /*!< VADC_G REFLAG: REV5 Mask */\r
-#define VADC_G_REFLAG_REV6_Pos 6 /*!< VADC_G REFLAG: REV6 Position */\r
-#define VADC_G_REFLAG_REV6_Msk (0x01UL << VADC_G_REFLAG_REV6_Pos) /*!< VADC_G REFLAG: REV6 Mask */\r
-#define VADC_G_REFLAG_REV7_Pos 7 /*!< VADC_G REFLAG: REV7 Position */\r
-#define VADC_G_REFLAG_REV7_Msk (0x01UL << VADC_G_REFLAG_REV7_Pos) /*!< VADC_G REFLAG: REV7 Mask */\r
-#define VADC_G_REFLAG_REV8_Pos 8 /*!< VADC_G REFLAG: REV8 Position */\r
-#define VADC_G_REFLAG_REV8_Msk (0x01UL << VADC_G_REFLAG_REV8_Pos) /*!< VADC_G REFLAG: REV8 Mask */\r
-#define VADC_G_REFLAG_REV9_Pos 9 /*!< VADC_G REFLAG: REV9 Position */\r
-#define VADC_G_REFLAG_REV9_Msk (0x01UL << VADC_G_REFLAG_REV9_Pos) /*!< VADC_G REFLAG: REV9 Mask */\r
-#define VADC_G_REFLAG_REV10_Pos 10 /*!< VADC_G REFLAG: REV10 Position */\r
-#define VADC_G_REFLAG_REV10_Msk (0x01UL << VADC_G_REFLAG_REV10_Pos) /*!< VADC_G REFLAG: REV10 Mask */\r
-#define VADC_G_REFLAG_REV11_Pos 11 /*!< VADC_G REFLAG: REV11 Position */\r
-#define VADC_G_REFLAG_REV11_Msk (0x01UL << VADC_G_REFLAG_REV11_Pos) /*!< VADC_G REFLAG: REV11 Mask */\r
-#define VADC_G_REFLAG_REV12_Pos 12 /*!< VADC_G REFLAG: REV12 Position */\r
-#define VADC_G_REFLAG_REV12_Msk (0x01UL << VADC_G_REFLAG_REV12_Pos) /*!< VADC_G REFLAG: REV12 Mask */\r
-#define VADC_G_REFLAG_REV13_Pos 13 /*!< VADC_G REFLAG: REV13 Position */\r
-#define VADC_G_REFLAG_REV13_Msk (0x01UL << VADC_G_REFLAG_REV13_Pos) /*!< VADC_G REFLAG: REV13 Mask */\r
-#define VADC_G_REFLAG_REV14_Pos 14 /*!< VADC_G REFLAG: REV14 Position */\r
-#define VADC_G_REFLAG_REV14_Msk (0x01UL << VADC_G_REFLAG_REV14_Pos) /*!< VADC_G REFLAG: REV14 Mask */\r
-#define VADC_G_REFLAG_REV15_Pos 15 /*!< VADC_G REFLAG: REV15 Position */\r
-#define VADC_G_REFLAG_REV15_Msk (0x01UL << VADC_G_REFLAG_REV15_Pos) /*!< VADC_G REFLAG: REV15 Mask */\r
-\r
-/* -------------------------------- VADC_G_SEFLAG ------------------------------- */\r
-#define VADC_G_SEFLAG_SEV0_Pos 0 /*!< VADC_G SEFLAG: SEV0 Position */\r
-#define VADC_G_SEFLAG_SEV0_Msk (0x01UL << VADC_G_SEFLAG_SEV0_Pos) /*!< VADC_G SEFLAG: SEV0 Mask */\r
-#define VADC_G_SEFLAG_SEV1_Pos 1 /*!< VADC_G SEFLAG: SEV1 Position */\r
-#define VADC_G_SEFLAG_SEV1_Msk (0x01UL << VADC_G_SEFLAG_SEV1_Pos) /*!< VADC_G SEFLAG: SEV1 Mask */\r
-\r
-/* -------------------------------- VADC_G_CEFCLR ------------------------------- */\r
-#define VADC_G_CEFCLR_CEV0_Pos 0 /*!< VADC_G CEFCLR: CEV0 Position */\r
-#define VADC_G_CEFCLR_CEV0_Msk (0x01UL << VADC_G_CEFCLR_CEV0_Pos) /*!< VADC_G CEFCLR: CEV0 Mask */\r
-#define VADC_G_CEFCLR_CEV1_Pos 1 /*!< VADC_G CEFCLR: CEV1 Position */\r
-#define VADC_G_CEFCLR_CEV1_Msk (0x01UL << VADC_G_CEFCLR_CEV1_Pos) /*!< VADC_G CEFCLR: CEV1 Mask */\r
-#define VADC_G_CEFCLR_CEV2_Pos 2 /*!< VADC_G CEFCLR: CEV2 Position */\r
-#define VADC_G_CEFCLR_CEV2_Msk (0x01UL << VADC_G_CEFCLR_CEV2_Pos) /*!< VADC_G CEFCLR: CEV2 Mask */\r
-#define VADC_G_CEFCLR_CEV3_Pos 3 /*!< VADC_G CEFCLR: CEV3 Position */\r
-#define VADC_G_CEFCLR_CEV3_Msk (0x01UL << VADC_G_CEFCLR_CEV3_Pos) /*!< VADC_G CEFCLR: CEV3 Mask */\r
-#define VADC_G_CEFCLR_CEV4_Pos 4 /*!< VADC_G CEFCLR: CEV4 Position */\r
-#define VADC_G_CEFCLR_CEV4_Msk (0x01UL << VADC_G_CEFCLR_CEV4_Pos) /*!< VADC_G CEFCLR: CEV4 Mask */\r
-#define VADC_G_CEFCLR_CEV5_Pos 5 /*!< VADC_G CEFCLR: CEV5 Position */\r
-#define VADC_G_CEFCLR_CEV5_Msk (0x01UL << VADC_G_CEFCLR_CEV5_Pos) /*!< VADC_G CEFCLR: CEV5 Mask */\r
-#define VADC_G_CEFCLR_CEV6_Pos 6 /*!< VADC_G CEFCLR: CEV6 Position */\r
-#define VADC_G_CEFCLR_CEV6_Msk (0x01UL << VADC_G_CEFCLR_CEV6_Pos) /*!< VADC_G CEFCLR: CEV6 Mask */\r
-#define VADC_G_CEFCLR_CEV7_Pos 7 /*!< VADC_G CEFCLR: CEV7 Position */\r
-#define VADC_G_CEFCLR_CEV7_Msk (0x01UL << VADC_G_CEFCLR_CEV7_Pos) /*!< VADC_G CEFCLR: CEV7 Mask */\r
-\r
-/* -------------------------------- VADC_G_REFCLR ------------------------------- */\r
-#define VADC_G_REFCLR_REV0_Pos 0 /*!< VADC_G REFCLR: REV0 Position */\r
-#define VADC_G_REFCLR_REV0_Msk (0x01UL << VADC_G_REFCLR_REV0_Pos) /*!< VADC_G REFCLR: REV0 Mask */\r
-#define VADC_G_REFCLR_REV1_Pos 1 /*!< VADC_G REFCLR: REV1 Position */\r
-#define VADC_G_REFCLR_REV1_Msk (0x01UL << VADC_G_REFCLR_REV1_Pos) /*!< VADC_G REFCLR: REV1 Mask */\r
-#define VADC_G_REFCLR_REV2_Pos 2 /*!< VADC_G REFCLR: REV2 Position */\r
-#define VADC_G_REFCLR_REV2_Msk (0x01UL << VADC_G_REFCLR_REV2_Pos) /*!< VADC_G REFCLR: REV2 Mask */\r
-#define VADC_G_REFCLR_REV3_Pos 3 /*!< VADC_G REFCLR: REV3 Position */\r
-#define VADC_G_REFCLR_REV3_Msk (0x01UL << VADC_G_REFCLR_REV3_Pos) /*!< VADC_G REFCLR: REV3 Mask */\r
-#define VADC_G_REFCLR_REV4_Pos 4 /*!< VADC_G REFCLR: REV4 Position */\r
-#define VADC_G_REFCLR_REV4_Msk (0x01UL << VADC_G_REFCLR_REV4_Pos) /*!< VADC_G REFCLR: REV4 Mask */\r
-#define VADC_G_REFCLR_REV5_Pos 5 /*!< VADC_G REFCLR: REV5 Position */\r
-#define VADC_G_REFCLR_REV5_Msk (0x01UL << VADC_G_REFCLR_REV5_Pos) /*!< VADC_G REFCLR: REV5 Mask */\r
-#define VADC_G_REFCLR_REV6_Pos 6 /*!< VADC_G REFCLR: REV6 Position */\r
-#define VADC_G_REFCLR_REV6_Msk (0x01UL << VADC_G_REFCLR_REV6_Pos) /*!< VADC_G REFCLR: REV6 Mask */\r
-#define VADC_G_REFCLR_REV7_Pos 7 /*!< VADC_G REFCLR: REV7 Position */\r
-#define VADC_G_REFCLR_REV7_Msk (0x01UL << VADC_G_REFCLR_REV7_Pos) /*!< VADC_G REFCLR: REV7 Mask */\r
-#define VADC_G_REFCLR_REV8_Pos 8 /*!< VADC_G REFCLR: REV8 Position */\r
-#define VADC_G_REFCLR_REV8_Msk (0x01UL << VADC_G_REFCLR_REV8_Pos) /*!< VADC_G REFCLR: REV8 Mask */\r
-#define VADC_G_REFCLR_REV9_Pos 9 /*!< VADC_G REFCLR: REV9 Position */\r
-#define VADC_G_REFCLR_REV9_Msk (0x01UL << VADC_G_REFCLR_REV9_Pos) /*!< VADC_G REFCLR: REV9 Mask */\r
-#define VADC_G_REFCLR_REV10_Pos 10 /*!< VADC_G REFCLR: REV10 Position */\r
-#define VADC_G_REFCLR_REV10_Msk (0x01UL << VADC_G_REFCLR_REV10_Pos) /*!< VADC_G REFCLR: REV10 Mask */\r
-#define VADC_G_REFCLR_REV11_Pos 11 /*!< VADC_G REFCLR: REV11 Position */\r
-#define VADC_G_REFCLR_REV11_Msk (0x01UL << VADC_G_REFCLR_REV11_Pos) /*!< VADC_G REFCLR: REV11 Mask */\r
-#define VADC_G_REFCLR_REV12_Pos 12 /*!< VADC_G REFCLR: REV12 Position */\r
-#define VADC_G_REFCLR_REV12_Msk (0x01UL << VADC_G_REFCLR_REV12_Pos) /*!< VADC_G REFCLR: REV12 Mask */\r
-#define VADC_G_REFCLR_REV13_Pos 13 /*!< VADC_G REFCLR: REV13 Position */\r
-#define VADC_G_REFCLR_REV13_Msk (0x01UL << VADC_G_REFCLR_REV13_Pos) /*!< VADC_G REFCLR: REV13 Mask */\r
-#define VADC_G_REFCLR_REV14_Pos 14 /*!< VADC_G REFCLR: REV14 Position */\r
-#define VADC_G_REFCLR_REV14_Msk (0x01UL << VADC_G_REFCLR_REV14_Pos) /*!< VADC_G REFCLR: REV14 Mask */\r
-#define VADC_G_REFCLR_REV15_Pos 15 /*!< VADC_G REFCLR: REV15 Position */\r
-#define VADC_G_REFCLR_REV15_Msk (0x01UL << VADC_G_REFCLR_REV15_Pos) /*!< VADC_G REFCLR: REV15 Mask */\r
-\r
-/* -------------------------------- VADC_G_SEFCLR ------------------------------- */\r
-#define VADC_G_SEFCLR_SEV0_Pos 0 /*!< VADC_G SEFCLR: SEV0 Position */\r
-#define VADC_G_SEFCLR_SEV0_Msk (0x01UL << VADC_G_SEFCLR_SEV0_Pos) /*!< VADC_G SEFCLR: SEV0 Mask */\r
-#define VADC_G_SEFCLR_SEV1_Pos 1 /*!< VADC_G SEFCLR: SEV1 Position */\r
-#define VADC_G_SEFCLR_SEV1_Msk (0x01UL << VADC_G_SEFCLR_SEV1_Pos) /*!< VADC_G SEFCLR: SEV1 Mask */\r
-\r
-/* -------------------------------- VADC_G_CEVNP0 ------------------------------- */\r
-#define VADC_G_CEVNP0_CEV0NP_Pos 0 /*!< VADC_G CEVNP0: CEV0NP Position */\r
-#define VADC_G_CEVNP0_CEV0NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos) /*!< VADC_G CEVNP0: CEV0NP Mask */\r
-#define VADC_G_CEVNP0_CEV1NP_Pos 4 /*!< VADC_G CEVNP0: CEV1NP Position */\r
-#define VADC_G_CEVNP0_CEV1NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos) /*!< VADC_G CEVNP0: CEV1NP Mask */\r
-#define VADC_G_CEVNP0_CEV2NP_Pos 8 /*!< VADC_G CEVNP0: CEV2NP Position */\r
-#define VADC_G_CEVNP0_CEV2NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos) /*!< VADC_G CEVNP0: CEV2NP Mask */\r
-#define VADC_G_CEVNP0_CEV3NP_Pos 12 /*!< VADC_G CEVNP0: CEV3NP Position */\r
-#define VADC_G_CEVNP0_CEV3NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos) /*!< VADC_G CEVNP0: CEV3NP Mask */\r
-#define VADC_G_CEVNP0_CEV4NP_Pos 16 /*!< VADC_G CEVNP0: CEV4NP Position */\r
-#define VADC_G_CEVNP0_CEV4NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos) /*!< VADC_G CEVNP0: CEV4NP Mask */\r
-#define VADC_G_CEVNP0_CEV5NP_Pos 20 /*!< VADC_G CEVNP0: CEV5NP Position */\r
-#define VADC_G_CEVNP0_CEV5NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos) /*!< VADC_G CEVNP0: CEV5NP Mask */\r
-#define VADC_G_CEVNP0_CEV6NP_Pos 24 /*!< VADC_G CEVNP0: CEV6NP Position */\r
-#define VADC_G_CEVNP0_CEV6NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos) /*!< VADC_G CEVNP0: CEV6NP Mask */\r
-#define VADC_G_CEVNP0_CEV7NP_Pos 28 /*!< VADC_G CEVNP0: CEV7NP Position */\r
-#define VADC_G_CEVNP0_CEV7NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos) /*!< VADC_G CEVNP0: CEV7NP Mask */\r
-\r
-/* -------------------------------- VADC_G_REVNP0 ------------------------------- */\r
-#define VADC_G_REVNP0_REV0NP_Pos 0 /*!< VADC_G REVNP0: REV0NP Position */\r
-#define VADC_G_REVNP0_REV0NP_Msk (0x0fUL << VADC_G_REVNP0_REV0NP_Pos) /*!< VADC_G REVNP0: REV0NP Mask */\r
-#define VADC_G_REVNP0_REV1NP_Pos 4 /*!< VADC_G REVNP0: REV1NP Position */\r
-#define VADC_G_REVNP0_REV1NP_Msk (0x0fUL << VADC_G_REVNP0_REV1NP_Pos) /*!< VADC_G REVNP0: REV1NP Mask */\r
-#define VADC_G_REVNP0_REV2NP_Pos 8 /*!< VADC_G REVNP0: REV2NP Position */\r
-#define VADC_G_REVNP0_REV2NP_Msk (0x0fUL << VADC_G_REVNP0_REV2NP_Pos) /*!< VADC_G REVNP0: REV2NP Mask */\r
-#define VADC_G_REVNP0_REV3NP_Pos 12 /*!< VADC_G REVNP0: REV3NP Position */\r
-#define VADC_G_REVNP0_REV3NP_Msk (0x0fUL << VADC_G_REVNP0_REV3NP_Pos) /*!< VADC_G REVNP0: REV3NP Mask */\r
-#define VADC_G_REVNP0_REV4NP_Pos 16 /*!< VADC_G REVNP0: REV4NP Position */\r
-#define VADC_G_REVNP0_REV4NP_Msk (0x0fUL << VADC_G_REVNP0_REV4NP_Pos) /*!< VADC_G REVNP0: REV4NP Mask */\r
-#define VADC_G_REVNP0_REV5NP_Pos 20 /*!< VADC_G REVNP0: REV5NP Position */\r
-#define VADC_G_REVNP0_REV5NP_Msk (0x0fUL << VADC_G_REVNP0_REV5NP_Pos) /*!< VADC_G REVNP0: REV5NP Mask */\r
-#define VADC_G_REVNP0_REV6NP_Pos 24 /*!< VADC_G REVNP0: REV6NP Position */\r
-#define VADC_G_REVNP0_REV6NP_Msk (0x0fUL << VADC_G_REVNP0_REV6NP_Pos) /*!< VADC_G REVNP0: REV6NP Mask */\r
-#define VADC_G_REVNP0_REV7NP_Pos 28 /*!< VADC_G REVNP0: REV7NP Position */\r
-#define VADC_G_REVNP0_REV7NP_Msk (0x0fUL << VADC_G_REVNP0_REV7NP_Pos) /*!< VADC_G REVNP0: REV7NP Mask */\r
-\r
-/* -------------------------------- VADC_G_REVNP1 ------------------------------- */\r
-#define VADC_G_REVNP1_REV8NP_Pos 0 /*!< VADC_G REVNP1: REV8NP Position */\r
-#define VADC_G_REVNP1_REV8NP_Msk (0x0fUL << VADC_G_REVNP1_REV8NP_Pos) /*!< VADC_G REVNP1: REV8NP Mask */\r
-#define VADC_G_REVNP1_REV9NP_Pos 4 /*!< VADC_G REVNP1: REV9NP Position */\r
-#define VADC_G_REVNP1_REV9NP_Msk (0x0fUL << VADC_G_REVNP1_REV9NP_Pos) /*!< VADC_G REVNP1: REV9NP Mask */\r
-#define VADC_G_REVNP1_REV10NP_Pos 8 /*!< VADC_G REVNP1: REV10NP Position */\r
-#define VADC_G_REVNP1_REV10NP_Msk (0x0fUL << VADC_G_REVNP1_REV10NP_Pos) /*!< VADC_G REVNP1: REV10NP Mask */\r
-#define VADC_G_REVNP1_REV11NP_Pos 12 /*!< VADC_G REVNP1: REV11NP Position */\r
-#define VADC_G_REVNP1_REV11NP_Msk (0x0fUL << VADC_G_REVNP1_REV11NP_Pos) /*!< VADC_G REVNP1: REV11NP Mask */\r
-#define VADC_G_REVNP1_REV12NP_Pos 16 /*!< VADC_G REVNP1: REV12NP Position */\r
-#define VADC_G_REVNP1_REV12NP_Msk (0x0fUL << VADC_G_REVNP1_REV12NP_Pos) /*!< VADC_G REVNP1: REV12NP Mask */\r
-#define VADC_G_REVNP1_REV13NP_Pos 20 /*!< VADC_G REVNP1: REV13NP Position */\r
-#define VADC_G_REVNP1_REV13NP_Msk (0x0fUL << VADC_G_REVNP1_REV13NP_Pos) /*!< VADC_G REVNP1: REV13NP Mask */\r
-#define VADC_G_REVNP1_REV14NP_Pos 24 /*!< VADC_G REVNP1: REV14NP Position */\r
-#define VADC_G_REVNP1_REV14NP_Msk (0x0fUL << VADC_G_REVNP1_REV14NP_Pos) /*!< VADC_G REVNP1: REV14NP Mask */\r
-#define VADC_G_REVNP1_REV15NP_Pos 28 /*!< VADC_G REVNP1: REV15NP Position */\r
-#define VADC_G_REVNP1_REV15NP_Msk (0x0fUL << VADC_G_REVNP1_REV15NP_Pos) /*!< VADC_G REVNP1: REV15NP Mask */\r
-\r
-/* -------------------------------- VADC_G_SEVNP -------------------------------- */\r
-#define VADC_G_SEVNP_SEV0NP_Pos 0 /*!< VADC_G SEVNP: SEV0NP Position */\r
-#define VADC_G_SEVNP_SEV0NP_Msk (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos) /*!< VADC_G SEVNP: SEV0NP Mask */\r
-#define VADC_G_SEVNP_SEV1NP_Pos 4 /*!< VADC_G SEVNP: SEV1NP Position */\r
-#define VADC_G_SEVNP_SEV1NP_Msk (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos) /*!< VADC_G SEVNP: SEV1NP Mask */\r
-\r
-/* -------------------------------- VADC_G_SRACT -------------------------------- */\r
-#define VADC_G_SRACT_AGSR0_Pos 0 /*!< VADC_G SRACT: AGSR0 Position */\r
-#define VADC_G_SRACT_AGSR0_Msk (0x01UL << VADC_G_SRACT_AGSR0_Pos) /*!< VADC_G SRACT: AGSR0 Mask */\r
-#define VADC_G_SRACT_AGSR1_Pos 1 /*!< VADC_G SRACT: AGSR1 Position */\r
-#define VADC_G_SRACT_AGSR1_Msk (0x01UL << VADC_G_SRACT_AGSR1_Pos) /*!< VADC_G SRACT: AGSR1 Mask */\r
-#define VADC_G_SRACT_ASSR0_Pos 8 /*!< VADC_G SRACT: ASSR0 Position */\r
-#define VADC_G_SRACT_ASSR0_Msk (0x01UL << VADC_G_SRACT_ASSR0_Pos) /*!< VADC_G SRACT: ASSR0 Mask */\r
-#define VADC_G_SRACT_ASSR1_Pos 9 /*!< VADC_G SRACT: ASSR1 Position */\r
-#define VADC_G_SRACT_ASSR1_Msk (0x01UL << VADC_G_SRACT_ASSR1_Pos) /*!< VADC_G SRACT: ASSR1 Mask */\r
-#define VADC_G_SRACT_ASSR2_Pos 10 /*!< VADC_G SRACT: ASSR2 Position */\r
-#define VADC_G_SRACT_ASSR2_Msk (0x01UL << VADC_G_SRACT_ASSR2_Pos) /*!< VADC_G SRACT: ASSR2 Mask */\r
-#define VADC_G_SRACT_ASSR3_Pos 11 /*!< VADC_G SRACT: ASSR3 Position */\r
-#define VADC_G_SRACT_ASSR3_Msk (0x01UL << VADC_G_SRACT_ASSR3_Pos) /*!< VADC_G SRACT: ASSR3 Mask */\r
-\r
-/* ------------------------------- VADC_G_EMUXCTR ------------------------------- */\r
-#define VADC_G_EMUXCTR_EMUXSET_Pos 0 /*!< VADC_G EMUXCTR: EMUXSET Position */\r
-#define VADC_G_EMUXCTR_EMUXSET_Msk (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos) /*!< VADC_G EMUXCTR: EMUXSET Mask */\r
-#define VADC_G_EMUXCTR_EMUXACT_Pos 8 /*!< VADC_G EMUXCTR: EMUXACT Position */\r
-#define VADC_G_EMUXCTR_EMUXACT_Msk (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos) /*!< VADC_G EMUXCTR: EMUXACT Mask */\r
-#define VADC_G_EMUXCTR_EMUXCH_Pos 16 /*!< VADC_G EMUXCTR: EMUXCH Position */\r
-#define VADC_G_EMUXCTR_EMUXCH_Msk (0x000003ffUL << VADC_G_EMUXCTR_EMUXCH_Pos) /*!< VADC_G EMUXCTR: EMUXCH Mask */\r
-#define VADC_G_EMUXCTR_EMUXMODE_Pos 26 /*!< VADC_G EMUXCTR: EMUXMODE Position */\r
-#define VADC_G_EMUXCTR_EMUXMODE_Msk (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos) /*!< VADC_G EMUXCTR: EMUXMODE Mask */\r
-#define VADC_G_EMUXCTR_EMXCOD_Pos 28 /*!< VADC_G EMUXCTR: EMXCOD Position */\r
-#define VADC_G_EMUXCTR_EMXCOD_Msk (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos) /*!< VADC_G EMUXCTR: EMXCOD Mask */\r
-#define VADC_G_EMUXCTR_EMXST_Pos 29 /*!< VADC_G EMUXCTR: EMXST Position */\r
-#define VADC_G_EMUXCTR_EMXST_Msk (0x01UL << VADC_G_EMUXCTR_EMXST_Pos) /*!< VADC_G EMUXCTR: EMXST Mask */\r
-#define VADC_G_EMUXCTR_EMXCSS_Pos 30 /*!< VADC_G EMUXCTR: EMXCSS Position */\r
-#define VADC_G_EMUXCTR_EMXCSS_Msk (0x01UL << VADC_G_EMUXCTR_EMXCSS_Pos) /*!< VADC_G EMUXCTR: EMXCSS Mask */\r
-#define VADC_G_EMUXCTR_EMXWC_Pos 31 /*!< VADC_G EMUXCTR: EMXWC Position */\r
-#define VADC_G_EMUXCTR_EMXWC_Msk (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos) /*!< VADC_G EMUXCTR: EMXWC Mask */\r
-\r
-/* --------------------------------- VADC_G_VFR --------------------------------- */\r
-#define VADC_G_VFR_VF0_Pos 0 /*!< VADC_G VFR: VF0 Position */\r
-#define VADC_G_VFR_VF0_Msk (0x01UL << VADC_G_VFR_VF0_Pos) /*!< VADC_G VFR: VF0 Mask */\r
-#define VADC_G_VFR_VF1_Pos 1 /*!< VADC_G VFR: VF1 Position */\r
-#define VADC_G_VFR_VF1_Msk (0x01UL << VADC_G_VFR_VF1_Pos) /*!< VADC_G VFR: VF1 Mask */\r
-#define VADC_G_VFR_VF2_Pos 2 /*!< VADC_G VFR: VF2 Position */\r
-#define VADC_G_VFR_VF2_Msk (0x01UL << VADC_G_VFR_VF2_Pos) /*!< VADC_G VFR: VF2 Mask */\r
-#define VADC_G_VFR_VF3_Pos 3 /*!< VADC_G VFR: VF3 Position */\r
-#define VADC_G_VFR_VF3_Msk (0x01UL << VADC_G_VFR_VF3_Pos) /*!< VADC_G VFR: VF3 Mask */\r
-#define VADC_G_VFR_VF4_Pos 4 /*!< VADC_G VFR: VF4 Position */\r
-#define VADC_G_VFR_VF4_Msk (0x01UL << VADC_G_VFR_VF4_Pos) /*!< VADC_G VFR: VF4 Mask */\r
-#define VADC_G_VFR_VF5_Pos 5 /*!< VADC_G VFR: VF5 Position */\r
-#define VADC_G_VFR_VF5_Msk (0x01UL << VADC_G_VFR_VF5_Pos) /*!< VADC_G VFR: VF5 Mask */\r
-#define VADC_G_VFR_VF6_Pos 6 /*!< VADC_G VFR: VF6 Position */\r
-#define VADC_G_VFR_VF6_Msk (0x01UL << VADC_G_VFR_VF6_Pos) /*!< VADC_G VFR: VF6 Mask */\r
-#define VADC_G_VFR_VF7_Pos 7 /*!< VADC_G VFR: VF7 Position */\r
-#define VADC_G_VFR_VF7_Msk (0x01UL << VADC_G_VFR_VF7_Pos) /*!< VADC_G VFR: VF7 Mask */\r
-#define VADC_G_VFR_VF8_Pos 8 /*!< VADC_G VFR: VF8 Position */\r
-#define VADC_G_VFR_VF8_Msk (0x01UL << VADC_G_VFR_VF8_Pos) /*!< VADC_G VFR: VF8 Mask */\r
-#define VADC_G_VFR_VF9_Pos 9 /*!< VADC_G VFR: VF9 Position */\r
-#define VADC_G_VFR_VF9_Msk (0x01UL << VADC_G_VFR_VF9_Pos) /*!< VADC_G VFR: VF9 Mask */\r
-#define VADC_G_VFR_VF10_Pos 10 /*!< VADC_G VFR: VF10 Position */\r
-#define VADC_G_VFR_VF10_Msk (0x01UL << VADC_G_VFR_VF10_Pos) /*!< VADC_G VFR: VF10 Mask */\r
-#define VADC_G_VFR_VF11_Pos 11 /*!< VADC_G VFR: VF11 Position */\r
-#define VADC_G_VFR_VF11_Msk (0x01UL << VADC_G_VFR_VF11_Pos) /*!< VADC_G VFR: VF11 Mask */\r
-#define VADC_G_VFR_VF12_Pos 12 /*!< VADC_G VFR: VF12 Position */\r
-#define VADC_G_VFR_VF12_Msk (0x01UL << VADC_G_VFR_VF12_Pos) /*!< VADC_G VFR: VF12 Mask */\r
-#define VADC_G_VFR_VF13_Pos 13 /*!< VADC_G VFR: VF13 Position */\r
-#define VADC_G_VFR_VF13_Msk (0x01UL << VADC_G_VFR_VF13_Pos) /*!< VADC_G VFR: VF13 Mask */\r
-#define VADC_G_VFR_VF14_Pos 14 /*!< VADC_G VFR: VF14 Position */\r
-#define VADC_G_VFR_VF14_Msk (0x01UL << VADC_G_VFR_VF14_Pos) /*!< VADC_G VFR: VF14 Mask */\r
-#define VADC_G_VFR_VF15_Pos 15 /*!< VADC_G VFR: VF15 Position */\r
-#define VADC_G_VFR_VF15_Msk (0x01UL << VADC_G_VFR_VF15_Pos) /*!< VADC_G VFR: VF15 Mask */\r
-\r
-/* -------------------------------- VADC_G_CHCTR -------------------------------- */\r
-#define VADC_G_CHCTR_ICLSEL_Pos 0 /*!< VADC_G CHCTR: ICLSEL Position */\r
-#define VADC_G_CHCTR_ICLSEL_Msk (0x03UL << VADC_G_CHCTR_ICLSEL_Pos) /*!< VADC_G CHCTR: ICLSEL Mask */\r
-#define VADC_G_CHCTR_BNDSELL_Pos 4 /*!< VADC_G CHCTR: BNDSELL Position */\r
-#define VADC_G_CHCTR_BNDSELL_Msk (0x03UL << VADC_G_CHCTR_BNDSELL_Pos) /*!< VADC_G CHCTR: BNDSELL Mask */\r
-#define VADC_G_CHCTR_BNDSELU_Pos 6 /*!< VADC_G CHCTR: BNDSELU Position */\r
-#define VADC_G_CHCTR_BNDSELU_Msk (0x03UL << VADC_G_CHCTR_BNDSELU_Pos) /*!< VADC_G CHCTR: BNDSELU Mask */\r
-#define VADC_G_CHCTR_CHEVMODE_Pos 8 /*!< VADC_G CHCTR: CHEVMODE Position */\r
-#define VADC_G_CHCTR_CHEVMODE_Msk (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos) /*!< VADC_G CHCTR: CHEVMODE Mask */\r
-#define VADC_G_CHCTR_SYNC_Pos 10 /*!< VADC_G CHCTR: SYNC Position */\r
-#define VADC_G_CHCTR_SYNC_Msk (0x01UL << VADC_G_CHCTR_SYNC_Pos) /*!< VADC_G CHCTR: SYNC Mask */\r
-#define VADC_G_CHCTR_REFSEL_Pos 11 /*!< VADC_G CHCTR: REFSEL Position */\r
-#define VADC_G_CHCTR_REFSEL_Msk (0x01UL << VADC_G_CHCTR_REFSEL_Pos) /*!< VADC_G CHCTR: REFSEL Mask */\r
-#define VADC_G_CHCTR_BNDSELX_Pos 12 /*!< VADC_G CHCTR: BNDSELX Position */\r
-#define VADC_G_CHCTR_BNDSELX_Msk (0x0fUL << VADC_G_CHCTR_BNDSELX_Pos) /*!< VADC_G CHCTR: BNDSELX Mask */\r
-#define VADC_G_CHCTR_RESREG_Pos 16 /*!< VADC_G CHCTR: RESREG Position */\r
-#define VADC_G_CHCTR_RESREG_Msk (0x0fUL << VADC_G_CHCTR_RESREG_Pos) /*!< VADC_G CHCTR: RESREG Mask */\r
-#define VADC_G_CHCTR_RESTBS_Pos 20 /*!< VADC_G CHCTR: RESTBS Position */\r
-#define VADC_G_CHCTR_RESTBS_Msk (0x01UL << VADC_G_CHCTR_RESTBS_Pos) /*!< VADC_G CHCTR: RESTBS Mask */\r
-#define VADC_G_CHCTR_RESPOS_Pos 21 /*!< VADC_G CHCTR: RESPOS Position */\r
-#define VADC_G_CHCTR_RESPOS_Msk (0x01UL << VADC_G_CHCTR_RESPOS_Pos) /*!< VADC_G CHCTR: RESPOS Mask */\r
-#define VADC_G_CHCTR_BWDCH_Pos 28 /*!< VADC_G CHCTR: BWDCH Position */\r
-#define VADC_G_CHCTR_BWDCH_Msk (0x03UL << VADC_G_CHCTR_BWDCH_Pos) /*!< VADC_G CHCTR: BWDCH Mask */\r
-#define VADC_G_CHCTR_BWDEN_Pos 30 /*!< VADC_G CHCTR: BWDEN Position */\r
-#define VADC_G_CHCTR_BWDEN_Msk (0x01UL << VADC_G_CHCTR_BWDEN_Pos) /*!< VADC_G CHCTR: BWDEN Mask */\r
-\r
-/* --------------------------------- VADC_G_RCR --------------------------------- */\r
-#define VADC_G_RCR_DRCTR_Pos 16 /*!< VADC_G RCR: DRCTR Position */\r
-#define VADC_G_RCR_DRCTR_Msk (0x0fUL << VADC_G_RCR_DRCTR_Pos) /*!< VADC_G RCR: DRCTR Mask */\r
-#define VADC_G_RCR_DMM_Pos 20 /*!< VADC_G RCR: DMM Position */\r
-#define VADC_G_RCR_DMM_Msk (0x03UL << VADC_G_RCR_DMM_Pos) /*!< VADC_G RCR: DMM Mask */\r
-#define VADC_G_RCR_WFR_Pos 24 /*!< VADC_G RCR: WFR Position */\r
-#define VADC_G_RCR_WFR_Msk (0x01UL << VADC_G_RCR_WFR_Pos) /*!< VADC_G RCR: WFR Mask */\r
-#define VADC_G_RCR_FEN_Pos 25 /*!< VADC_G RCR: FEN Position */\r
-#define VADC_G_RCR_FEN_Msk (0x03UL << VADC_G_RCR_FEN_Pos) /*!< VADC_G RCR: FEN Mask */\r
-#define VADC_G_RCR_SRGEN_Pos 31 /*!< VADC_G RCR: SRGEN Position */\r
-#define VADC_G_RCR_SRGEN_Msk (0x01UL << VADC_G_RCR_SRGEN_Pos) /*!< VADC_G RCR: SRGEN Mask */\r
-\r
-/* --------------------------------- VADC_G_RES --------------------------------- */\r
-#define VADC_G_RES_RESULT_Pos 0 /*!< VADC_G RES: RESULT Position */\r
-#define VADC_G_RES_RESULT_Msk (0x0000ffffUL << VADC_G_RES_RESULT_Pos) /*!< VADC_G RES: RESULT Mask */\r
-#define VADC_G_RES_DRC_Pos 16 /*!< VADC_G RES: DRC Position */\r
-#define VADC_G_RES_DRC_Msk (0x0fUL << VADC_G_RES_DRC_Pos) /*!< VADC_G RES: DRC Mask */\r
-#define VADC_G_RES_CHNR_Pos 20 /*!< VADC_G RES: CHNR Position */\r
-#define VADC_G_RES_CHNR_Msk (0x1fUL << VADC_G_RES_CHNR_Pos) /*!< VADC_G RES: CHNR Mask */\r
-#define VADC_G_RES_EMUX_Pos 25 /*!< VADC_G RES: EMUX Position */\r
-#define VADC_G_RES_EMUX_Msk (0x07UL << VADC_G_RES_EMUX_Pos) /*!< VADC_G RES: EMUX Mask */\r
-#define VADC_G_RES_CRS_Pos 28 /*!< VADC_G RES: CRS Position */\r
-#define VADC_G_RES_CRS_Msk (0x03UL << VADC_G_RES_CRS_Pos) /*!< VADC_G RES: CRS Mask */\r
-#define VADC_G_RES_FCR_Pos 30 /*!< VADC_G RES: FCR Position */\r
-#define VADC_G_RES_FCR_Msk (0x01UL << VADC_G_RES_FCR_Pos) /*!< VADC_G RES: FCR Mask */\r
-#define VADC_G_RES_VF_Pos 31 /*!< VADC_G RES: VF Position */\r
-#define VADC_G_RES_VF_Msk (0x01UL << VADC_G_RES_VF_Pos) /*!< VADC_G RES: VF Mask */\r
-\r
-/* --------------------------------- VADC_G_RESD -------------------------------- */\r
-#define VADC_G_RESD_RESULT_Pos 0 /*!< VADC_G RESD: RESULT Position */\r
-#define VADC_G_RESD_RESULT_Msk (0x0000ffffUL << VADC_G_RESD_RESULT_Pos) /*!< VADC_G RESD: RESULT Mask */\r
-#define VADC_G_RESD_DRC_Pos 16 /*!< VADC_G RESD: DRC Position */\r
-#define VADC_G_RESD_DRC_Msk (0x0fUL << VADC_G_RESD_DRC_Pos) /*!< VADC_G RESD: DRC Mask */\r
-#define VADC_G_RESD_CHNR_Pos 20 /*!< VADC_G RESD: CHNR Position */\r
-#define VADC_G_RESD_CHNR_Msk (0x1fUL << VADC_G_RESD_CHNR_Pos) /*!< VADC_G RESD: CHNR Mask */\r
-#define VADC_G_RESD_EMUX_Pos 25 /*!< VADC_G RESD: EMUX Position */\r
-#define VADC_G_RESD_EMUX_Msk (0x07UL << VADC_G_RESD_EMUX_Pos) /*!< VADC_G RESD: EMUX Mask */\r
-#define VADC_G_RESD_CRS_Pos 28 /*!< VADC_G RESD: CRS Position */\r
-#define VADC_G_RESD_CRS_Msk (0x03UL << VADC_G_RESD_CRS_Pos) /*!< VADC_G RESD: CRS Mask */\r
-#define VADC_G_RESD_FCR_Pos 30 /*!< VADC_G RESD: FCR Position */\r
-#define VADC_G_RESD_FCR_Msk (0x01UL << VADC_G_RESD_FCR_Pos) /*!< VADC_G RESD: FCR Mask */\r
-#define VADC_G_RESD_VF_Pos 31 /*!< VADC_G RESD: VF Position */\r
-#define VADC_G_RESD_VF_Msk (0x01UL << VADC_G_RESD_VF_Pos) /*!< VADC_G RESD: VF Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'SHS' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ----------------------------------- SHS_ID ----------------------------------- */\r
-#define SHS_ID_MOD_REV_Pos 0 /*!< SHS ID: MOD_REV Position */\r
-#define SHS_ID_MOD_REV_Msk (0x000000ffUL << SHS_ID_MOD_REV_Pos) /*!< SHS ID: MOD_REV Mask */\r
-#define SHS_ID_MOD_TYPE_Pos 8 /*!< SHS ID: MOD_TYPE Position */\r
-#define SHS_ID_MOD_TYPE_Msk (0x000000ffUL << SHS_ID_MOD_TYPE_Pos) /*!< SHS ID: MOD_TYPE Mask */\r
-#define SHS_ID_MOD_NUMBER_Pos 16 /*!< SHS ID: MOD_NUMBER Position */\r
-#define SHS_ID_MOD_NUMBER_Msk (0x0000ffffUL << SHS_ID_MOD_NUMBER_Pos) /*!< SHS ID: MOD_NUMBER Mask */\r
-\r
-/* --------------------------------- SHS_SHSCFG --------------------------------- */\r
-#define SHS_SHSCFG_DIVS_Pos 0 /*!< SHS SHSCFG: DIVS Position */\r
-#define SHS_SHSCFG_DIVS_Msk (0x0fUL << SHS_SHSCFG_DIVS_Pos) /*!< SHS SHSCFG: DIVS Mask */\r
-#define SHS_SHSCFG_AREF_Pos 10 /*!< SHS SHSCFG: AREF Position */\r
-#define SHS_SHSCFG_AREF_Msk (0x03UL << SHS_SHSCFG_AREF_Pos) /*!< SHS SHSCFG: AREF Mask */\r
-#define SHS_SHSCFG_ANOFF_Pos 12 /*!< SHS SHSCFG: ANOFF Position */\r
-#define SHS_SHSCFG_ANOFF_Msk (0x01UL << SHS_SHSCFG_ANOFF_Pos) /*!< SHS SHSCFG: ANOFF Mask */\r
-#define SHS_SHSCFG_ANRDY_Pos 14 /*!< SHS SHSCFG: ANRDY Position */\r
-#define SHS_SHSCFG_ANRDY_Msk (0x01UL << SHS_SHSCFG_ANRDY_Pos) /*!< SHS SHSCFG: ANRDY Mask */\r
-#define SHS_SHSCFG_SCWC_Pos 15 /*!< SHS SHSCFG: SCWC Position */\r
-#define SHS_SHSCFG_SCWC_Msk (0x01UL << SHS_SHSCFG_SCWC_Pos) /*!< SHS SHSCFG: SCWC Mask */\r
-#define SHS_SHSCFG_SP0_Pos 16 /*!< SHS SHSCFG: SP0 Position */\r
-#define SHS_SHSCFG_SP0_Msk (0x01UL << SHS_SHSCFG_SP0_Pos) /*!< SHS SHSCFG: SP0 Mask */\r
-#define SHS_SHSCFG_SP1_Pos 17 /*!< SHS SHSCFG: SP1 Position */\r
-#define SHS_SHSCFG_SP1_Msk (0x01UL << SHS_SHSCFG_SP1_Pos) /*!< SHS SHSCFG: SP1 Mask */\r
-#define SHS_SHSCFG_TC_Pos 24 /*!< SHS SHSCFG: TC Position */\r
-#define SHS_SHSCFG_TC_Msk (0x0fUL << SHS_SHSCFG_TC_Pos) /*!< SHS SHSCFG: TC Mask */\r
-#define SHS_SHSCFG_STATE_Pos 28 /*!< SHS SHSCFG: STATE Position */\r
-#define SHS_SHSCFG_STATE_Msk (0x0fUL << SHS_SHSCFG_STATE_Pos) /*!< SHS SHSCFG: STATE Mask */\r
-\r
-/* --------------------------------- SHS_STEPCFG -------------------------------- */\r
-#define SHS_STEPCFG_KSEL0_Pos 0 /*!< SHS STEPCFG: KSEL0 Position */\r
-#define SHS_STEPCFG_KSEL0_Msk (0x07UL << SHS_STEPCFG_KSEL0_Pos) /*!< SHS STEPCFG: KSEL0 Mask */\r
-#define SHS_STEPCFG_SEN0_Pos 3 /*!< SHS STEPCFG: SEN0 Position */\r
-#define SHS_STEPCFG_SEN0_Msk (0x01UL << SHS_STEPCFG_SEN0_Pos) /*!< SHS STEPCFG: SEN0 Mask */\r
-#define SHS_STEPCFG_KSEL1_Pos 4 /*!< SHS STEPCFG: KSEL1 Position */\r
-#define SHS_STEPCFG_KSEL1_Msk (0x07UL << SHS_STEPCFG_KSEL1_Pos) /*!< SHS STEPCFG: KSEL1 Mask */\r
-#define SHS_STEPCFG_SEN1_Pos 7 /*!< SHS STEPCFG: SEN1 Position */\r
-#define SHS_STEPCFG_SEN1_Msk (0x01UL << SHS_STEPCFG_SEN1_Pos) /*!< SHS STEPCFG: SEN1 Mask */\r
-#define SHS_STEPCFG_KSEL2_Pos 8 /*!< SHS STEPCFG: KSEL2 Position */\r
-#define SHS_STEPCFG_KSEL2_Msk (0x07UL << SHS_STEPCFG_KSEL2_Pos) /*!< SHS STEPCFG: KSEL2 Mask */\r
-#define SHS_STEPCFG_SEN2_Pos 11 /*!< SHS STEPCFG: SEN2 Position */\r
-#define SHS_STEPCFG_SEN2_Msk (0x01UL << SHS_STEPCFG_SEN2_Pos) /*!< SHS STEPCFG: SEN2 Mask */\r
-#define SHS_STEPCFG_KSEL3_Pos 12 /*!< SHS STEPCFG: KSEL3 Position */\r
-#define SHS_STEPCFG_KSEL3_Msk (0x07UL << SHS_STEPCFG_KSEL3_Pos) /*!< SHS STEPCFG: KSEL3 Mask */\r
-#define SHS_STEPCFG_SEN3_Pos 15 /*!< SHS STEPCFG: SEN3 Position */\r
-#define SHS_STEPCFG_SEN3_Msk (0x01UL << SHS_STEPCFG_SEN3_Pos) /*!< SHS STEPCFG: SEN3 Mask */\r
-#define SHS_STEPCFG_KSEL4_Pos 16 /*!< SHS STEPCFG: KSEL4 Position */\r
-#define SHS_STEPCFG_KSEL4_Msk (0x07UL << SHS_STEPCFG_KSEL4_Pos) /*!< SHS STEPCFG: KSEL4 Mask */\r
-#define SHS_STEPCFG_SEN4_Pos 19 /*!< SHS STEPCFG: SEN4 Position */\r
-#define SHS_STEPCFG_SEN4_Msk (0x01UL << SHS_STEPCFG_SEN4_Pos) /*!< SHS STEPCFG: SEN4 Mask */\r
-#define SHS_STEPCFG_KSEL5_Pos 20 /*!< SHS STEPCFG: KSEL5 Position */\r
-#define SHS_STEPCFG_KSEL5_Msk (0x07UL << SHS_STEPCFG_KSEL5_Pos) /*!< SHS STEPCFG: KSEL5 Mask */\r
-#define SHS_STEPCFG_SEN5_Pos 23 /*!< SHS STEPCFG: SEN5 Position */\r
-#define SHS_STEPCFG_SEN5_Msk (0x01UL << SHS_STEPCFG_SEN5_Pos) /*!< SHS STEPCFG: SEN5 Mask */\r
-#define SHS_STEPCFG_KSEL6_Pos 24 /*!< SHS STEPCFG: KSEL6 Position */\r
-#define SHS_STEPCFG_KSEL6_Msk (0x07UL << SHS_STEPCFG_KSEL6_Pos) /*!< SHS STEPCFG: KSEL6 Mask */\r
-#define SHS_STEPCFG_SEN6_Pos 27 /*!< SHS STEPCFG: SEN6 Position */\r
-#define SHS_STEPCFG_SEN6_Msk (0x01UL << SHS_STEPCFG_SEN6_Pos) /*!< SHS STEPCFG: SEN6 Mask */\r
-#define SHS_STEPCFG_KSEL7_Pos 28 /*!< SHS STEPCFG: KSEL7 Position */\r
-#define SHS_STEPCFG_KSEL7_Msk (0x07UL << SHS_STEPCFG_KSEL7_Pos) /*!< SHS STEPCFG: KSEL7 Mask */\r
-#define SHS_STEPCFG_SEN7_Pos 31 /*!< SHS STEPCFG: SEN7 Position */\r
-#define SHS_STEPCFG_SEN7_Msk (0x01UL << SHS_STEPCFG_SEN7_Pos) /*!< SHS STEPCFG: SEN7 Mask */\r
-\r
-/* ---------------------------------- SHS_LOOP ---------------------------------- */\r
-#define SHS_LOOP_LPCH0_Pos 0 /*!< SHS LOOP: LPCH0 Position */\r
-#define SHS_LOOP_LPCH0_Msk (0x1fUL << SHS_LOOP_LPCH0_Pos) /*!< SHS LOOP: LPCH0 Mask */\r
-#define SHS_LOOP_LPSH0_Pos 8 /*!< SHS LOOP: LPSH0 Position */\r
-#define SHS_LOOP_LPSH0_Msk (0x01UL << SHS_LOOP_LPSH0_Pos) /*!< SHS LOOP: LPSH0 Mask */\r
-#define SHS_LOOP_LPEN0_Pos 15 /*!< SHS LOOP: LPEN0 Position */\r
-#define SHS_LOOP_LPEN0_Msk (0x01UL << SHS_LOOP_LPEN0_Pos) /*!< SHS LOOP: LPEN0 Mask */\r
-#define SHS_LOOP_LPCH1_Pos 16 /*!< SHS LOOP: LPCH1 Position */\r
-#define SHS_LOOP_LPCH1_Msk (0x1fUL << SHS_LOOP_LPCH1_Pos) /*!< SHS LOOP: LPCH1 Mask */\r
-#define SHS_LOOP_LPSH1_Pos 24 /*!< SHS LOOP: LPSH1 Position */\r
-#define SHS_LOOP_LPSH1_Msk (0x01UL << SHS_LOOP_LPSH1_Pos) /*!< SHS LOOP: LPSH1 Mask */\r
-#define SHS_LOOP_LPEN1_Pos 31 /*!< SHS LOOP: LPEN1 Position */\r
-#define SHS_LOOP_LPEN1_Msk (0x01UL << SHS_LOOP_LPEN1_Pos) /*!< SHS LOOP: LPEN1 Mask */\r
-\r
-/* --------------------------------- SHS_TIMCFG0 -------------------------------- */\r
-#define SHS_TIMCFG0_AT_Pos 0 /*!< SHS TIMCFG0: AT Position */\r
-#define SHS_TIMCFG0_AT_Msk (0x01UL << SHS_TIMCFG0_AT_Pos) /*!< SHS TIMCFG0: AT Mask */\r
-#define SHS_TIMCFG0_FCRT_Pos 4 /*!< SHS TIMCFG0: FCRT Position */\r
-#define SHS_TIMCFG0_FCRT_Msk (0x0fUL << SHS_TIMCFG0_FCRT_Pos) /*!< SHS TIMCFG0: FCRT Mask */\r
-#define SHS_TIMCFG0_SST_Pos 8 /*!< SHS TIMCFG0: SST Position */\r
-#define SHS_TIMCFG0_SST_Msk (0x3fUL << SHS_TIMCFG0_SST_Pos) /*!< SHS TIMCFG0: SST Mask */\r
-#define SHS_TIMCFG0_TGEN_Pos 16 /*!< SHS TIMCFG0: TGEN Position */\r
-#define SHS_TIMCFG0_TGEN_Msk (0x00003fffUL << SHS_TIMCFG0_TGEN_Pos) /*!< SHS TIMCFG0: TGEN Mask */\r
-\r
-/* --------------------------------- SHS_TIMCFG1 -------------------------------- */\r
-#define SHS_TIMCFG1_AT_Pos 0 /*!< SHS TIMCFG1: AT Position */\r
-#define SHS_TIMCFG1_AT_Msk (0x01UL << SHS_TIMCFG1_AT_Pos) /*!< SHS TIMCFG1: AT Mask */\r
-#define SHS_TIMCFG1_FCRT_Pos 4 /*!< SHS TIMCFG1: FCRT Position */\r
-#define SHS_TIMCFG1_FCRT_Msk (0x0fUL << SHS_TIMCFG1_FCRT_Pos) /*!< SHS TIMCFG1: FCRT Mask */\r
-#define SHS_TIMCFG1_SST_Pos 8 /*!< SHS TIMCFG1: SST Position */\r
-#define SHS_TIMCFG1_SST_Msk (0x3fUL << SHS_TIMCFG1_SST_Pos) /*!< SHS TIMCFG1: SST Mask */\r
-#define SHS_TIMCFG1_TGEN_Pos 16 /*!< SHS TIMCFG1: TGEN Position */\r
-#define SHS_TIMCFG1_TGEN_Msk (0x00003fffUL << SHS_TIMCFG1_TGEN_Pos) /*!< SHS TIMCFG1: TGEN Mask */\r
-\r
-/* --------------------------------- SHS_CALCTR --------------------------------- */\r
-#define SHS_CALCTR_CALORD_Pos 0 /*!< SHS CALCTR: CALORD Position */\r
-#define SHS_CALCTR_CALORD_Msk (0x01UL << SHS_CALCTR_CALORD_Pos) /*!< SHS CALCTR: CALORD Mask */\r
-#define SHS_CALCTR_CALGNSTC_Pos 8 /*!< SHS CALCTR: CALGNSTC Position */\r
-#define SHS_CALCTR_CALGNSTC_Msk (0x3fUL << SHS_CALCTR_CALGNSTC_Pos) /*!< SHS CALCTR: CALGNSTC Mask */\r
-#define SHS_CALCTR_SUCALVAL_Pos 16 /*!< SHS CALCTR: SUCALVAL Position */\r
-#define SHS_CALCTR_SUCALVAL_Msk (0x7fUL << SHS_CALCTR_SUCALVAL_Pos) /*!< SHS CALCTR: SUCALVAL Mask */\r
-#define SHS_CALCTR_CALMAX_Pos 24 /*!< SHS CALCTR: CALMAX Position */\r
-#define SHS_CALCTR_CALMAX_Msk (0x3fUL << SHS_CALCTR_CALMAX_Pos) /*!< SHS CALCTR: CALMAX Mask */\r
-#define SHS_CALCTR_SUCAL_Pos 31 /*!< SHS CALCTR: SUCAL Position */\r
-#define SHS_CALCTR_SUCAL_Msk (0x01UL << SHS_CALCTR_SUCAL_Pos) /*!< SHS CALCTR: SUCAL Mask */\r
-\r
-/* --------------------------------- SHS_CALGC0 --------------------------------- */\r
-#define SHS_CALGC0_CALGNVALS_Pos 0 /*!< SHS CALGC0: CALGNVALS Position */\r
-#define SHS_CALGC0_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALS_Pos) /*!< SHS CALGC0: CALGNVALS Mask */\r
-#define SHS_CALGC0_GNSWC_Pos 15 /*!< SHS CALGC0: GNSWC Position */\r
-#define SHS_CALGC0_GNSWC_Msk (0x01UL << SHS_CALGC0_GNSWC_Pos) /*!< SHS CALGC0: GNSWC Mask */\r
-#define SHS_CALGC0_CALGNVALA_Pos 16 /*!< SHS CALGC0: CALGNVALA Position */\r
-#define SHS_CALGC0_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALA_Pos) /*!< SHS CALGC0: CALGNVALA Mask */\r
-#define SHS_CALGC0_GNAWC_Pos 31 /*!< SHS CALGC0: GNAWC Position */\r
-#define SHS_CALGC0_GNAWC_Msk (0x01UL << SHS_CALGC0_GNAWC_Pos) /*!< SHS CALGC0: GNAWC Mask */\r
-\r
-/* --------------------------------- SHS_CALGC1 --------------------------------- */\r
-#define SHS_CALGC1_CALGNVALS_Pos 0 /*!< SHS CALGC1: CALGNVALS Position */\r
-#define SHS_CALGC1_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALS_Pos) /*!< SHS CALGC1: CALGNVALS Mask */\r
-#define SHS_CALGC1_GNSWC_Pos 15 /*!< SHS CALGC1: GNSWC Position */\r
-#define SHS_CALGC1_GNSWC_Msk (0x01UL << SHS_CALGC1_GNSWC_Pos) /*!< SHS CALGC1: GNSWC Mask */\r
-#define SHS_CALGC1_CALGNVALA_Pos 16 /*!< SHS CALGC1: CALGNVALA Position */\r
-#define SHS_CALGC1_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALA_Pos) /*!< SHS CALGC1: CALGNVALA Mask */\r
-#define SHS_CALGC1_GNAWC_Pos 31 /*!< SHS CALGC1: GNAWC Position */\r
-#define SHS_CALGC1_GNAWC_Msk (0x01UL << SHS_CALGC1_GNAWC_Pos) /*!< SHS CALGC1: GNAWC Mask */\r
-\r
-/* --------------------------------- SHS_GNCTR00 -------------------------------- */\r
-#define SHS_GNCTR00_GAIN0_Pos 0 /*!< SHS GNCTR00: GAIN0 Position */\r
-#define SHS_GNCTR00_GAIN0_Msk (0x0fUL << SHS_GNCTR00_GAIN0_Pos) /*!< SHS GNCTR00: GAIN0 Mask */\r
-#define SHS_GNCTR00_GAIN1_Pos 4 /*!< SHS GNCTR00: GAIN1 Position */\r
-#define SHS_GNCTR00_GAIN1_Msk (0x0fUL << SHS_GNCTR00_GAIN1_Pos) /*!< SHS GNCTR00: GAIN1 Mask */\r
-#define SHS_GNCTR00_GAIN2_Pos 8 /*!< SHS GNCTR00: GAIN2 Position */\r
-#define SHS_GNCTR00_GAIN2_Msk (0x0fUL << SHS_GNCTR00_GAIN2_Pos) /*!< SHS GNCTR00: GAIN2 Mask */\r
-#define SHS_GNCTR00_GAIN3_Pos 12 /*!< SHS GNCTR00: GAIN3 Position */\r
-#define SHS_GNCTR00_GAIN3_Msk (0x0fUL << SHS_GNCTR00_GAIN3_Pos) /*!< SHS GNCTR00: GAIN3 Mask */\r
-#define SHS_GNCTR00_GAIN4_Pos 16 /*!< SHS GNCTR00: GAIN4 Position */\r
-#define SHS_GNCTR00_GAIN4_Msk (0x0fUL << SHS_GNCTR00_GAIN4_Pos) /*!< SHS GNCTR00: GAIN4 Mask */\r
-#define SHS_GNCTR00_GAIN5_Pos 20 /*!< SHS GNCTR00: GAIN5 Position */\r
-#define SHS_GNCTR00_GAIN5_Msk (0x0fUL << SHS_GNCTR00_GAIN5_Pos) /*!< SHS GNCTR00: GAIN5 Mask */\r
-#define SHS_GNCTR00_GAIN6_Pos 24 /*!< SHS GNCTR00: GAIN6 Position */\r
-#define SHS_GNCTR00_GAIN6_Msk (0x0fUL << SHS_GNCTR00_GAIN6_Pos) /*!< SHS GNCTR00: GAIN6 Mask */\r
-#define SHS_GNCTR00_GAIN7_Pos 28 /*!< SHS GNCTR00: GAIN7 Position */\r
-#define SHS_GNCTR00_GAIN7_Msk (0x0fUL << SHS_GNCTR00_GAIN7_Pos) /*!< SHS GNCTR00: GAIN7 Mask */\r
-\r
-/* --------------------------------- SHS_GNCTR10 -------------------------------- */\r
-#define SHS_GNCTR10_GAIN0_Pos 0 /*!< SHS GNCTR10: GAIN0 Position */\r
-#define SHS_GNCTR10_GAIN0_Msk (0x0fUL << SHS_GNCTR10_GAIN0_Pos) /*!< SHS GNCTR10: GAIN0 Mask */\r
-#define SHS_GNCTR10_GAIN1_Pos 4 /*!< SHS GNCTR10: GAIN1 Position */\r
-#define SHS_GNCTR10_GAIN1_Msk (0x0fUL << SHS_GNCTR10_GAIN1_Pos) /*!< SHS GNCTR10: GAIN1 Mask */\r
-#define SHS_GNCTR10_GAIN2_Pos 8 /*!< SHS GNCTR10: GAIN2 Position */\r
-#define SHS_GNCTR10_GAIN2_Msk (0x0fUL << SHS_GNCTR10_GAIN2_Pos) /*!< SHS GNCTR10: GAIN2 Mask */\r
-#define SHS_GNCTR10_GAIN3_Pos 12 /*!< SHS GNCTR10: GAIN3 Position */\r
-#define SHS_GNCTR10_GAIN3_Msk (0x0fUL << SHS_GNCTR10_GAIN3_Pos) /*!< SHS GNCTR10: GAIN3 Mask */\r
-#define SHS_GNCTR10_GAIN4_Pos 16 /*!< SHS GNCTR10: GAIN4 Position */\r
-#define SHS_GNCTR10_GAIN4_Msk (0x0fUL << SHS_GNCTR10_GAIN4_Pos) /*!< SHS GNCTR10: GAIN4 Mask */\r
-#define SHS_GNCTR10_GAIN5_Pos 20 /*!< SHS GNCTR10: GAIN5 Position */\r
-#define SHS_GNCTR10_GAIN5_Msk (0x0fUL << SHS_GNCTR10_GAIN5_Pos) /*!< SHS GNCTR10: GAIN5 Mask */\r
-#define SHS_GNCTR10_GAIN6_Pos 24 /*!< SHS GNCTR10: GAIN6 Position */\r
-#define SHS_GNCTR10_GAIN6_Msk (0x0fUL << SHS_GNCTR10_GAIN6_Pos) /*!< SHS GNCTR10: GAIN6 Mask */\r
-#define SHS_GNCTR10_GAIN7_Pos 28 /*!< SHS GNCTR10: GAIN7 Position */\r
-#define SHS_GNCTR10_GAIN7_Msk (0x0fUL << SHS_GNCTR10_GAIN7_Pos) /*!< SHS GNCTR10: GAIN7 Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'BCCU' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- BCCU_GLOBCON -------------------------------- */\r
-#define BCCU_GLOBCON_TM_Pos 0 /*!< BCCU GLOBCON: TM Position */\r
-#define BCCU_GLOBCON_TM_Msk (0x01UL << BCCU_GLOBCON_TM_Pos) /*!< BCCU GLOBCON: TM Mask */\r
-#define BCCU_GLOBCON_TRDEL_Pos 2 /*!< BCCU GLOBCON: TRDEL Position */\r
-#define BCCU_GLOBCON_TRDEL_Msk (0x03UL << BCCU_GLOBCON_TRDEL_Pos) /*!< BCCU GLOBCON: TRDEL Mask */\r
-#define BCCU_GLOBCON_SUSCFG_Pos 4 /*!< BCCU GLOBCON: SUSCFG Position */\r
-#define BCCU_GLOBCON_SUSCFG_Msk (0x03UL << BCCU_GLOBCON_SUSCFG_Pos) /*!< BCCU GLOBCON: SUSCFG Mask */\r
-#define BCCU_GLOBCON_TRAPIS_Pos 6 /*!< BCCU GLOBCON: TRAPIS Position */\r
-#define BCCU_GLOBCON_TRAPIS_Msk (0x0fUL << BCCU_GLOBCON_TRAPIS_Pos) /*!< BCCU GLOBCON: TRAPIS Mask */\r
-#define BCCU_GLOBCON_TRAPED_Pos 10 /*!< BCCU GLOBCON: TRAPED Position */\r
-#define BCCU_GLOBCON_TRAPED_Msk (0x01UL << BCCU_GLOBCON_TRAPED_Pos) /*!< BCCU GLOBCON: TRAPED Mask */\r
-#define BCCU_GLOBCON_LTRS_Pos 12 /*!< BCCU GLOBCON: LTRS Position */\r
-#define BCCU_GLOBCON_LTRS_Msk (0x0fUL << BCCU_GLOBCON_LTRS_Pos) /*!< BCCU GLOBCON: LTRS Mask */\r
-#define BCCU_GLOBCON_WDMBN_Pos 16 /*!< BCCU GLOBCON: WDMBN Position */\r
-#define BCCU_GLOBCON_WDMBN_Msk (0x00000fffUL << BCCU_GLOBCON_WDMBN_Pos) /*!< BCCU GLOBCON: WDMBN Mask */\r
-\r
-/* -------------------------------- BCCU_GLOBCLK -------------------------------- */\r
-#define BCCU_GLOBCLK_FCLK_PS_Pos 0 /*!< BCCU GLOBCLK: FCLK_PS Position */\r
-#define BCCU_GLOBCLK_FCLK_PS_Msk (0x00000fffUL << BCCU_GLOBCLK_FCLK_PS_Pos) /*!< BCCU GLOBCLK: FCLK_PS Mask */\r
-#define BCCU_GLOBCLK_BCS_Pos 15 /*!< BCCU GLOBCLK: BCS Position */\r
-#define BCCU_GLOBCLK_BCS_Msk (0x01UL << BCCU_GLOBCLK_BCS_Pos) /*!< BCCU GLOBCLK: BCS Mask */\r
-#define BCCU_GLOBCLK_DCLK_PS_Pos 16 /*!< BCCU GLOBCLK: DCLK_PS Position */\r
-#define BCCU_GLOBCLK_DCLK_PS_Msk (0x00000fffUL << BCCU_GLOBCLK_DCLK_PS_Pos) /*!< BCCU GLOBCLK: DCLK_PS Mask */\r
-\r
-/* ----------------------------------- BCCU_ID ---------------------------------- */\r
-#define BCCU_ID_MOD_REV_Pos 0 /*!< BCCU ID: MOD_REV Position */\r
-#define BCCU_ID_MOD_REV_Msk (0x000000ffUL << BCCU_ID_MOD_REV_Pos) /*!< BCCU ID: MOD_REV Mask */\r
-#define BCCU_ID_MOD_TYPE0_Pos 8 /*!< BCCU ID: MOD_TYPE0 Position */\r
-#define BCCU_ID_MOD_TYPE0_Msk (0x000000ffUL << BCCU_ID_MOD_TYPE0_Pos) /*!< BCCU ID: MOD_TYPE0 Mask */\r
-#define BCCU_ID_MOD_NUMBER_Pos 16 /*!< BCCU ID: MOD_NUMBER Position */\r
-#define BCCU_ID_MOD_NUMBER_Msk (0x0000ffffUL << BCCU_ID_MOD_NUMBER_Pos) /*!< BCCU ID: MOD_NUMBER Mask */\r
-\r
-/* ---------------------------------- BCCU_CHEN --------------------------------- */\r
-#define BCCU_CHEN_ECH0_Pos 0 /*!< BCCU CHEN: ECH0 Position */\r
-#define BCCU_CHEN_ECH0_Msk (0x01UL << BCCU_CHEN_ECH0_Pos) /*!< BCCU CHEN: ECH0 Mask */\r
-#define BCCU_CHEN_ECH1_Pos 1 /*!< BCCU CHEN: ECH1 Position */\r
-#define BCCU_CHEN_ECH1_Msk (0x01UL << BCCU_CHEN_ECH1_Pos) /*!< BCCU CHEN: ECH1 Mask */\r
-#define BCCU_CHEN_ECH2_Pos 2 /*!< BCCU CHEN: ECH2 Position */\r
-#define BCCU_CHEN_ECH2_Msk (0x01UL << BCCU_CHEN_ECH2_Pos) /*!< BCCU CHEN: ECH2 Mask */\r
-#define BCCU_CHEN_ECH3_Pos 3 /*!< BCCU CHEN: ECH3 Position */\r
-#define BCCU_CHEN_ECH3_Msk (0x01UL << BCCU_CHEN_ECH3_Pos) /*!< BCCU CHEN: ECH3 Mask */\r
-#define BCCU_CHEN_ECH4_Pos 4 /*!< BCCU CHEN: ECH4 Position */\r
-#define BCCU_CHEN_ECH4_Msk (0x01UL << BCCU_CHEN_ECH4_Pos) /*!< BCCU CHEN: ECH4 Mask */\r
-#define BCCU_CHEN_ECH5_Pos 5 /*!< BCCU CHEN: ECH5 Position */\r
-#define BCCU_CHEN_ECH5_Msk (0x01UL << BCCU_CHEN_ECH5_Pos) /*!< BCCU CHEN: ECH5 Mask */\r
-#define BCCU_CHEN_ECH6_Pos 6 /*!< BCCU CHEN: ECH6 Position */\r
-#define BCCU_CHEN_ECH6_Msk (0x01UL << BCCU_CHEN_ECH6_Pos) /*!< BCCU CHEN: ECH6 Mask */\r
-#define BCCU_CHEN_ECH7_Pos 7 /*!< BCCU CHEN: ECH7 Position */\r
-#define BCCU_CHEN_ECH7_Msk (0x01UL << BCCU_CHEN_ECH7_Pos) /*!< BCCU CHEN: ECH7 Mask */\r
-#define BCCU_CHEN_ECH8_Pos 8 /*!< BCCU CHEN: ECH8 Position */\r
-#define BCCU_CHEN_ECH8_Msk (0x01UL << BCCU_CHEN_ECH8_Pos) /*!< BCCU CHEN: ECH8 Mask */\r
-\r
-/* --------------------------------- BCCU_CHOCON -------------------------------- */\r
-#define BCCU_CHOCON_CH0OP_Pos 0 /*!< BCCU CHOCON: CH0OP Position */\r
-#define BCCU_CHOCON_CH0OP_Msk (0x01UL << BCCU_CHOCON_CH0OP_Pos) /*!< BCCU CHOCON: CH0OP Mask */\r
-#define BCCU_CHOCON_CH1OP_Pos 1 /*!< BCCU CHOCON: CH1OP Position */\r
-#define BCCU_CHOCON_CH1OP_Msk (0x01UL << BCCU_CHOCON_CH1OP_Pos) /*!< BCCU CHOCON: CH1OP Mask */\r
-#define BCCU_CHOCON_CH2OP_Pos 2 /*!< BCCU CHOCON: CH2OP Position */\r
-#define BCCU_CHOCON_CH2OP_Msk (0x01UL << BCCU_CHOCON_CH2OP_Pos) /*!< BCCU CHOCON: CH2OP Mask */\r
-#define BCCU_CHOCON_CH3OP_Pos 3 /*!< BCCU CHOCON: CH3OP Position */\r
-#define BCCU_CHOCON_CH3OP_Msk (0x01UL << BCCU_CHOCON_CH3OP_Pos) /*!< BCCU CHOCON: CH3OP Mask */\r
-#define BCCU_CHOCON_CH4OP_Pos 4 /*!< BCCU CHOCON: CH4OP Position */\r
-#define BCCU_CHOCON_CH4OP_Msk (0x01UL << BCCU_CHOCON_CH4OP_Pos) /*!< BCCU CHOCON: CH4OP Mask */\r
-#define BCCU_CHOCON_CH5OP_Pos 5 /*!< BCCU CHOCON: CH5OP Position */\r
-#define BCCU_CHOCON_CH5OP_Msk (0x01UL << BCCU_CHOCON_CH5OP_Pos) /*!< BCCU CHOCON: CH5OP Mask */\r
-#define BCCU_CHOCON_CH6OP_Pos 6 /*!< BCCU CHOCON: CH6OP Position */\r
-#define BCCU_CHOCON_CH6OP_Msk (0x01UL << BCCU_CHOCON_CH6OP_Pos) /*!< BCCU CHOCON: CH6OP Mask */\r
-#define BCCU_CHOCON_CH7OP_Pos 7 /*!< BCCU CHOCON: CH7OP Position */\r
-#define BCCU_CHOCON_CH7OP_Msk (0x01UL << BCCU_CHOCON_CH7OP_Pos) /*!< BCCU CHOCON: CH7OP Mask */\r
-#define BCCU_CHOCON_CH8OP_Pos 8 /*!< BCCU CHOCON: CH8OP Position */\r
-#define BCCU_CHOCON_CH8OP_Msk (0x01UL << BCCU_CHOCON_CH8OP_Pos) /*!< BCCU CHOCON: CH8OP Mask */\r
-#define BCCU_CHOCON_CH0TPE_Pos 16 /*!< BCCU CHOCON: CH0TPE Position */\r
-#define BCCU_CHOCON_CH0TPE_Msk (0x01UL << BCCU_CHOCON_CH0TPE_Pos) /*!< BCCU CHOCON: CH0TPE Mask */\r
-#define BCCU_CHOCON_CH1TPE_Pos 17 /*!< BCCU CHOCON: CH1TPE Position */\r
-#define BCCU_CHOCON_CH1TPE_Msk (0x01UL << BCCU_CHOCON_CH1TPE_Pos) /*!< BCCU CHOCON: CH1TPE Mask */\r
-#define BCCU_CHOCON_CH2TPE_Pos 18 /*!< BCCU CHOCON: CH2TPE Position */\r
-#define BCCU_CHOCON_CH2TPE_Msk (0x01UL << BCCU_CHOCON_CH2TPE_Pos) /*!< BCCU CHOCON: CH2TPE Mask */\r
-#define BCCU_CHOCON_CH3TPE_Pos 19 /*!< BCCU CHOCON: CH3TPE Position */\r
-#define BCCU_CHOCON_CH3TPE_Msk (0x01UL << BCCU_CHOCON_CH3TPE_Pos) /*!< BCCU CHOCON: CH3TPE Mask */\r
-#define BCCU_CHOCON_CH4TPE_Pos 20 /*!< BCCU CHOCON: CH4TPE Position */\r
-#define BCCU_CHOCON_CH4TPE_Msk (0x01UL << BCCU_CHOCON_CH4TPE_Pos) /*!< BCCU CHOCON: CH4TPE Mask */\r
-#define BCCU_CHOCON_CH5TPE_Pos 21 /*!< BCCU CHOCON: CH5TPE Position */\r
-#define BCCU_CHOCON_CH5TPE_Msk (0x01UL << BCCU_CHOCON_CH5TPE_Pos) /*!< BCCU CHOCON: CH5TPE Mask */\r
-#define BCCU_CHOCON_CH6TPE_Pos 22 /*!< BCCU CHOCON: CH6TPE Position */\r
-#define BCCU_CHOCON_CH6TPE_Msk (0x01UL << BCCU_CHOCON_CH6TPE_Pos) /*!< BCCU CHOCON: CH6TPE Mask */\r
-#define BCCU_CHOCON_CH7TPE_Pos 23 /*!< BCCU CHOCON: CH7TPE Position */\r
-#define BCCU_CHOCON_CH7TPE_Msk (0x01UL << BCCU_CHOCON_CH7TPE_Pos) /*!< BCCU CHOCON: CH7TPE Mask */\r
-#define BCCU_CHOCON_CH8TPE_Pos 24 /*!< BCCU CHOCON: CH8TPE Position */\r
-#define BCCU_CHOCON_CH8TPE_Msk (0x01UL << BCCU_CHOCON_CH8TPE_Pos) /*!< BCCU CHOCON: CH8TPE Mask */\r
-\r
-/* --------------------------------- BCCU_CHTRIG -------------------------------- */\r
-#define BCCU_CHTRIG_ET0_Pos 0 /*!< BCCU CHTRIG: ET0 Position */\r
-#define BCCU_CHTRIG_ET0_Msk (0x01UL << BCCU_CHTRIG_ET0_Pos) /*!< BCCU CHTRIG: ET0 Mask */\r
-#define BCCU_CHTRIG_ET1_Pos 1 /*!< BCCU CHTRIG: ET1 Position */\r
-#define BCCU_CHTRIG_ET1_Msk (0x01UL << BCCU_CHTRIG_ET1_Pos) /*!< BCCU CHTRIG: ET1 Mask */\r
-#define BCCU_CHTRIG_ET2_Pos 2 /*!< BCCU CHTRIG: ET2 Position */\r
-#define BCCU_CHTRIG_ET2_Msk (0x01UL << BCCU_CHTRIG_ET2_Pos) /*!< BCCU CHTRIG: ET2 Mask */\r
-#define BCCU_CHTRIG_ET3_Pos 3 /*!< BCCU CHTRIG: ET3 Position */\r
-#define BCCU_CHTRIG_ET3_Msk (0x01UL << BCCU_CHTRIG_ET3_Pos) /*!< BCCU CHTRIG: ET3 Mask */\r
-#define BCCU_CHTRIG_ET4_Pos 4 /*!< BCCU CHTRIG: ET4 Position */\r
-#define BCCU_CHTRIG_ET4_Msk (0x01UL << BCCU_CHTRIG_ET4_Pos) /*!< BCCU CHTRIG: ET4 Mask */\r
-#define BCCU_CHTRIG_ET5_Pos 5 /*!< BCCU CHTRIG: ET5 Position */\r
-#define BCCU_CHTRIG_ET5_Msk (0x01UL << BCCU_CHTRIG_ET5_Pos) /*!< BCCU CHTRIG: ET5 Mask */\r
-#define BCCU_CHTRIG_ET6_Pos 6 /*!< BCCU CHTRIG: ET6 Position */\r
-#define BCCU_CHTRIG_ET6_Msk (0x01UL << BCCU_CHTRIG_ET6_Pos) /*!< BCCU CHTRIG: ET6 Mask */\r
-#define BCCU_CHTRIG_ET7_Pos 7 /*!< BCCU CHTRIG: ET7 Position */\r
-#define BCCU_CHTRIG_ET7_Msk (0x01UL << BCCU_CHTRIG_ET7_Pos) /*!< BCCU CHTRIG: ET7 Mask */\r
-#define BCCU_CHTRIG_ET8_Pos 8 /*!< BCCU CHTRIG: ET8 Position */\r
-#define BCCU_CHTRIG_ET8_Msk (0x01UL << BCCU_CHTRIG_ET8_Pos) /*!< BCCU CHTRIG: ET8 Mask */\r
-#define BCCU_CHTRIG_TOS0_Pos 16 /*!< BCCU CHTRIG: TOS0 Position */\r
-#define BCCU_CHTRIG_TOS0_Msk (0x01UL << BCCU_CHTRIG_TOS0_Pos) /*!< BCCU CHTRIG: TOS0 Mask */\r
-#define BCCU_CHTRIG_TOS1_Pos 17 /*!< BCCU CHTRIG: TOS1 Position */\r
-#define BCCU_CHTRIG_TOS1_Msk (0x01UL << BCCU_CHTRIG_TOS1_Pos) /*!< BCCU CHTRIG: TOS1 Mask */\r
-#define BCCU_CHTRIG_TOS2_Pos 18 /*!< BCCU CHTRIG: TOS2 Position */\r
-#define BCCU_CHTRIG_TOS2_Msk (0x01UL << BCCU_CHTRIG_TOS2_Pos) /*!< BCCU CHTRIG: TOS2 Mask */\r
-#define BCCU_CHTRIG_TOS3_Pos 19 /*!< BCCU CHTRIG: TOS3 Position */\r
-#define BCCU_CHTRIG_TOS3_Msk (0x01UL << BCCU_CHTRIG_TOS3_Pos) /*!< BCCU CHTRIG: TOS3 Mask */\r
-#define BCCU_CHTRIG_TOS4_Pos 20 /*!< BCCU CHTRIG: TOS4 Position */\r
-#define BCCU_CHTRIG_TOS4_Msk (0x01UL << BCCU_CHTRIG_TOS4_Pos) /*!< BCCU CHTRIG: TOS4 Mask */\r
-#define BCCU_CHTRIG_TOS5_Pos 21 /*!< BCCU CHTRIG: TOS5 Position */\r
-#define BCCU_CHTRIG_TOS5_Msk (0x01UL << BCCU_CHTRIG_TOS5_Pos) /*!< BCCU CHTRIG: TOS5 Mask */\r
-#define BCCU_CHTRIG_TOS6_Pos 22 /*!< BCCU CHTRIG: TOS6 Position */\r
-#define BCCU_CHTRIG_TOS6_Msk (0x01UL << BCCU_CHTRIG_TOS6_Pos) /*!< BCCU CHTRIG: TOS6 Mask */\r
-#define BCCU_CHTRIG_TOS7_Pos 23 /*!< BCCU CHTRIG: TOS7 Position */\r
-#define BCCU_CHTRIG_TOS7_Msk (0x01UL << BCCU_CHTRIG_TOS7_Pos) /*!< BCCU CHTRIG: TOS7 Mask */\r
-#define BCCU_CHTRIG_TOS8_Pos 24 /*!< BCCU CHTRIG: TOS8 Position */\r
-#define BCCU_CHTRIG_TOS8_Msk (0x01UL << BCCU_CHTRIG_TOS8_Pos) /*!< BCCU CHTRIG: TOS8 Mask */\r
-\r
-/* -------------------------------- BCCU_CHSTRCON ------------------------------- */\r
-#define BCCU_CHSTRCON_CH0S_Pos 0 /*!< BCCU CHSTRCON: CH0S Position */\r
-#define BCCU_CHSTRCON_CH0S_Msk (0x01UL << BCCU_CHSTRCON_CH0S_Pos) /*!< BCCU CHSTRCON: CH0S Mask */\r
-#define BCCU_CHSTRCON_CH1S_Pos 1 /*!< BCCU CHSTRCON: CH1S Position */\r
-#define BCCU_CHSTRCON_CH1S_Msk (0x01UL << BCCU_CHSTRCON_CH1S_Pos) /*!< BCCU CHSTRCON: CH1S Mask */\r
-#define BCCU_CHSTRCON_CH2S_Pos 2 /*!< BCCU CHSTRCON: CH2S Position */\r
-#define BCCU_CHSTRCON_CH2S_Msk (0x01UL << BCCU_CHSTRCON_CH2S_Pos) /*!< BCCU CHSTRCON: CH2S Mask */\r
-#define BCCU_CHSTRCON_CH3S_Pos 3 /*!< BCCU CHSTRCON: CH3S Position */\r
-#define BCCU_CHSTRCON_CH3S_Msk (0x01UL << BCCU_CHSTRCON_CH3S_Pos) /*!< BCCU CHSTRCON: CH3S Mask */\r
-#define BCCU_CHSTRCON_CH4S_Pos 4 /*!< BCCU CHSTRCON: CH4S Position */\r
-#define BCCU_CHSTRCON_CH4S_Msk (0x01UL << BCCU_CHSTRCON_CH4S_Pos) /*!< BCCU CHSTRCON: CH4S Mask */\r
-#define BCCU_CHSTRCON_CH5S_Pos 5 /*!< BCCU CHSTRCON: CH5S Position */\r
-#define BCCU_CHSTRCON_CH5S_Msk (0x01UL << BCCU_CHSTRCON_CH5S_Pos) /*!< BCCU CHSTRCON: CH5S Mask */\r
-#define BCCU_CHSTRCON_CH6S_Pos 6 /*!< BCCU CHSTRCON: CH6S Position */\r
-#define BCCU_CHSTRCON_CH6S_Msk (0x01UL << BCCU_CHSTRCON_CH6S_Pos) /*!< BCCU CHSTRCON: CH6S Mask */\r
-#define BCCU_CHSTRCON_CH7S_Pos 7 /*!< BCCU CHSTRCON: CH7S Position */\r
-#define BCCU_CHSTRCON_CH7S_Msk (0x01UL << BCCU_CHSTRCON_CH7S_Pos) /*!< BCCU CHSTRCON: CH7S Mask */\r
-#define BCCU_CHSTRCON_CH8S_Pos 8 /*!< BCCU CHSTRCON: CH8S Position */\r
-#define BCCU_CHSTRCON_CH8S_Msk (0x01UL << BCCU_CHSTRCON_CH8S_Pos) /*!< BCCU CHSTRCON: CH8S Mask */\r
-#define BCCU_CHSTRCON_CH0A_Pos 16 /*!< BCCU CHSTRCON: CH0A Position */\r
-#define BCCU_CHSTRCON_CH0A_Msk (0x01UL << BCCU_CHSTRCON_CH0A_Pos) /*!< BCCU CHSTRCON: CH0A Mask */\r
-#define BCCU_CHSTRCON_CH1A_Pos 17 /*!< BCCU CHSTRCON: CH1A Position */\r
-#define BCCU_CHSTRCON_CH1A_Msk (0x01UL << BCCU_CHSTRCON_CH1A_Pos) /*!< BCCU CHSTRCON: CH1A Mask */\r
-#define BCCU_CHSTRCON_CH2A_Pos 18 /*!< BCCU CHSTRCON: CH2A Position */\r
-#define BCCU_CHSTRCON_CH2A_Msk (0x01UL << BCCU_CHSTRCON_CH2A_Pos) /*!< BCCU CHSTRCON: CH2A Mask */\r
-#define BCCU_CHSTRCON_CH3A_Pos 19 /*!< BCCU CHSTRCON: CH3A Position */\r
-#define BCCU_CHSTRCON_CH3A_Msk (0x01UL << BCCU_CHSTRCON_CH3A_Pos) /*!< BCCU CHSTRCON: CH3A Mask */\r
-#define BCCU_CHSTRCON_CH4A_Pos 20 /*!< BCCU CHSTRCON: CH4A Position */\r
-#define BCCU_CHSTRCON_CH4A_Msk (0x01UL << BCCU_CHSTRCON_CH4A_Pos) /*!< BCCU CHSTRCON: CH4A Mask */\r
-#define BCCU_CHSTRCON_CH5A_Pos 21 /*!< BCCU CHSTRCON: CH5A Position */\r
-#define BCCU_CHSTRCON_CH5A_Msk (0x01UL << BCCU_CHSTRCON_CH5A_Pos) /*!< BCCU CHSTRCON: CH5A Mask */\r
-#define BCCU_CHSTRCON_CH6A_Pos 22 /*!< BCCU CHSTRCON: CH6A Position */\r
-#define BCCU_CHSTRCON_CH6A_Msk (0x01UL << BCCU_CHSTRCON_CH6A_Pos) /*!< BCCU CHSTRCON: CH6A Mask */\r
-#define BCCU_CHSTRCON_CH7A_Pos 23 /*!< BCCU CHSTRCON: CH7A Position */\r
-#define BCCU_CHSTRCON_CH7A_Msk (0x01UL << BCCU_CHSTRCON_CH7A_Pos) /*!< BCCU CHSTRCON: CH7A Mask */\r
-#define BCCU_CHSTRCON_CH8A_Pos 24 /*!< BCCU CHSTRCON: CH8A Position */\r
-#define BCCU_CHSTRCON_CH8A_Msk (0x01UL << BCCU_CHSTRCON_CH8A_Pos) /*!< BCCU CHSTRCON: CH8A Mask */\r
-\r
-/* --------------------------------- BCCU_LTCHOL -------------------------------- */\r
-#define BCCU_LTCHOL_LTOL0_Pos 0 /*!< BCCU LTCHOL: LTOL0 Position */\r
-#define BCCU_LTCHOL_LTOL0_Msk (0x01UL << BCCU_LTCHOL_LTOL0_Pos) /*!< BCCU LTCHOL: LTOL0 Mask */\r
-#define BCCU_LTCHOL_LTOL1_Pos 1 /*!< BCCU LTCHOL: LTOL1 Position */\r
-#define BCCU_LTCHOL_LTOL1_Msk (0x01UL << BCCU_LTCHOL_LTOL1_Pos) /*!< BCCU LTCHOL: LTOL1 Mask */\r
-#define BCCU_LTCHOL_LTOL2_Pos 2 /*!< BCCU LTCHOL: LTOL2 Position */\r
-#define BCCU_LTCHOL_LTOL2_Msk (0x01UL << BCCU_LTCHOL_LTOL2_Pos) /*!< BCCU LTCHOL: LTOL2 Mask */\r
-#define BCCU_LTCHOL_LTOL3_Pos 3 /*!< BCCU LTCHOL: LTOL3 Position */\r
-#define BCCU_LTCHOL_LTOL3_Msk (0x01UL << BCCU_LTCHOL_LTOL3_Pos) /*!< BCCU LTCHOL: LTOL3 Mask */\r
-#define BCCU_LTCHOL_LTOL4_Pos 4 /*!< BCCU LTCHOL: LTOL4 Position */\r
-#define BCCU_LTCHOL_LTOL4_Msk (0x01UL << BCCU_LTCHOL_LTOL4_Pos) /*!< BCCU LTCHOL: LTOL4 Mask */\r
-#define BCCU_LTCHOL_LTOL5_Pos 5 /*!< BCCU LTCHOL: LTOL5 Position */\r
-#define BCCU_LTCHOL_LTOL5_Msk (0x01UL << BCCU_LTCHOL_LTOL5_Pos) /*!< BCCU LTCHOL: LTOL5 Mask */\r
-#define BCCU_LTCHOL_LTOL6_Pos 6 /*!< BCCU LTCHOL: LTOL6 Position */\r
-#define BCCU_LTCHOL_LTOL6_Msk (0x01UL << BCCU_LTCHOL_LTOL6_Pos) /*!< BCCU LTCHOL: LTOL6 Mask */\r
-#define BCCU_LTCHOL_LTOL7_Pos 7 /*!< BCCU LTCHOL: LTOL7 Position */\r
-#define BCCU_LTCHOL_LTOL7_Msk (0x01UL << BCCU_LTCHOL_LTOL7_Pos) /*!< BCCU LTCHOL: LTOL7 Mask */\r
-#define BCCU_LTCHOL_LTOL8_Pos 8 /*!< BCCU LTCHOL: LTOL8 Position */\r
-#define BCCU_LTCHOL_LTOL8_Msk (0x01UL << BCCU_LTCHOL_LTOL8_Pos) /*!< BCCU LTCHOL: LTOL8 Mask */\r
-\r
-/* ---------------------------------- BCCU_DEEN --------------------------------- */\r
-#define BCCU_DEEN_EDE0_Pos 0 /*!< BCCU DEEN: EDE0 Position */\r
-#define BCCU_DEEN_EDE0_Msk (0x01UL << BCCU_DEEN_EDE0_Pos) /*!< BCCU DEEN: EDE0 Mask */\r
-#define BCCU_DEEN_EDE1_Pos 1 /*!< BCCU DEEN: EDE1 Position */\r
-#define BCCU_DEEN_EDE1_Msk (0x01UL << BCCU_DEEN_EDE1_Pos) /*!< BCCU DEEN: EDE1 Mask */\r
-#define BCCU_DEEN_EDE2_Pos 2 /*!< BCCU DEEN: EDE2 Position */\r
-#define BCCU_DEEN_EDE2_Msk (0x01UL << BCCU_DEEN_EDE2_Pos) /*!< BCCU DEEN: EDE2 Mask */\r
-\r
-/* -------------------------------- BCCU_DESTRCON ------------------------------- */\r
-#define BCCU_DESTRCON_DE0S_Pos 0 /*!< BCCU DESTRCON: DE0S Position */\r
-#define BCCU_DESTRCON_DE0S_Msk (0x01UL << BCCU_DESTRCON_DE0S_Pos) /*!< BCCU DESTRCON: DE0S Mask */\r
-#define BCCU_DESTRCON_DE1S_Pos 1 /*!< BCCU DESTRCON: DE1S Position */\r
-#define BCCU_DESTRCON_DE1S_Msk (0x01UL << BCCU_DESTRCON_DE1S_Pos) /*!< BCCU DESTRCON: DE1S Mask */\r
-#define BCCU_DESTRCON_DE2S_Pos 2 /*!< BCCU DESTRCON: DE2S Position */\r
-#define BCCU_DESTRCON_DE2S_Msk (0x01UL << BCCU_DESTRCON_DE2S_Pos) /*!< BCCU DESTRCON: DE2S Mask */\r
-#define BCCU_DESTRCON_DE0A_Pos 16 /*!< BCCU DESTRCON: DE0A Position */\r
-#define BCCU_DESTRCON_DE0A_Msk (0x01UL << BCCU_DESTRCON_DE0A_Pos) /*!< BCCU DESTRCON: DE0A Mask */\r
-#define BCCU_DESTRCON_DE1A_Pos 17 /*!< BCCU DESTRCON: DE1A Position */\r
-#define BCCU_DESTRCON_DE1A_Msk (0x01UL << BCCU_DESTRCON_DE1A_Pos) /*!< BCCU DESTRCON: DE1A Mask */\r
-#define BCCU_DESTRCON_DE2A_Pos 18 /*!< BCCU DESTRCON: DE2A Position */\r
-#define BCCU_DESTRCON_DE2A_Msk (0x01UL << BCCU_DESTRCON_DE2A_Pos) /*!< BCCU DESTRCON: DE2A Mask */\r
-\r
-/* -------------------------------- BCCU_GLOBDIM -------------------------------- */\r
-#define BCCU_GLOBDIM_GLOBDIM_Pos 0 /*!< BCCU GLOBDIM: GLOBDIM Position */\r
-#define BCCU_GLOBDIM_GLOBDIM_Msk (0x00000fffUL << BCCU_GLOBDIM_GLOBDIM_Pos) /*!< BCCU GLOBDIM: GLOBDIM Mask */\r
-\r
-/* --------------------------------- BCCU_EVIER --------------------------------- */\r
-#define BCCU_EVIER_T0IEN_Pos 0 /*!< BCCU EVIER: T0IEN Position */\r
-#define BCCU_EVIER_T0IEN_Msk (0x01UL << BCCU_EVIER_T0IEN_Pos) /*!< BCCU EVIER: T0IEN Mask */\r
-#define BCCU_EVIER_T1IEN_Pos 1 /*!< BCCU EVIER: T1IEN Position */\r
-#define BCCU_EVIER_T1IEN_Msk (0x01UL << BCCU_EVIER_T1IEN_Pos) /*!< BCCU EVIER: T1IEN Mask */\r
-#define BCCU_EVIER_FIEN_Pos 2 /*!< BCCU EVIER: FIEN Position */\r
-#define BCCU_EVIER_FIEN_Msk (0x01UL << BCCU_EVIER_FIEN_Pos) /*!< BCCU EVIER: FIEN Mask */\r
-#define BCCU_EVIER_EIEN_Pos 3 /*!< BCCU EVIER: EIEN Position */\r
-#define BCCU_EVIER_EIEN_Msk (0x01UL << BCCU_EVIER_EIEN_Pos) /*!< BCCU EVIER: EIEN Mask */\r
-#define BCCU_EVIER_TPIEN_Pos 4 /*!< BCCU EVIER: TPIEN Position */\r
-#define BCCU_EVIER_TPIEN_Msk (0x01UL << BCCU_EVIER_TPIEN_Pos) /*!< BCCU EVIER: TPIEN Mask */\r
-\r
-/* ---------------------------------- BCCU_EVFR --------------------------------- */\r
-#define BCCU_EVFR_T0F_Pos 0 /*!< BCCU EVFR: T0F Position */\r
-#define BCCU_EVFR_T0F_Msk (0x01UL << BCCU_EVFR_T0F_Pos) /*!< BCCU EVFR: T0F Mask */\r
-#define BCCU_EVFR_T1F_Pos 1 /*!< BCCU EVFR: T1F Position */\r
-#define BCCU_EVFR_T1F_Msk (0x01UL << BCCU_EVFR_T1F_Pos) /*!< BCCU EVFR: T1F Mask */\r
-#define BCCU_EVFR_FF_Pos 2 /*!< BCCU EVFR: FF Position */\r
-#define BCCU_EVFR_FF_Msk (0x01UL << BCCU_EVFR_FF_Pos) /*!< BCCU EVFR: FF Mask */\r
-#define BCCU_EVFR_EF_Pos 3 /*!< BCCU EVFR: EF Position */\r
-#define BCCU_EVFR_EF_Msk (0x01UL << BCCU_EVFR_EF_Pos) /*!< BCCU EVFR: EF Mask */\r
-#define BCCU_EVFR_TPF_Pos 4 /*!< BCCU EVFR: TPF Position */\r
-#define BCCU_EVFR_TPF_Msk (0x01UL << BCCU_EVFR_TPF_Pos) /*!< BCCU EVFR: TPF Mask */\r
-#define BCCU_EVFR_TPSF_Pos 6 /*!< BCCU EVFR: TPSF Position */\r
-#define BCCU_EVFR_TPSF_Msk (0x01UL << BCCU_EVFR_TPSF_Pos) /*!< BCCU EVFR: TPSF Mask */\r
-#define BCCU_EVFR_TPINL_Pos 7 /*!< BCCU EVFR: TPINL Position */\r
-#define BCCU_EVFR_TPINL_Msk (0x01UL << BCCU_EVFR_TPINL_Pos) /*!< BCCU EVFR: TPINL Mask */\r
-\r
-/* --------------------------------- BCCU_EVFSR --------------------------------- */\r
-#define BCCU_EVFSR_T0FS_Pos 0 /*!< BCCU EVFSR: T0FS Position */\r
-#define BCCU_EVFSR_T0FS_Msk (0x01UL << BCCU_EVFSR_T0FS_Pos) /*!< BCCU EVFSR: T0FS Mask */\r
-#define BCCU_EVFSR_T1FS_Pos 1 /*!< BCCU EVFSR: T1FS Position */\r
-#define BCCU_EVFSR_T1FS_Msk (0x01UL << BCCU_EVFSR_T1FS_Pos) /*!< BCCU EVFSR: T1FS Mask */\r
-#define BCCU_EVFSR_FFS_Pos 2 /*!< BCCU EVFSR: FFS Position */\r
-#define BCCU_EVFSR_FFS_Msk (0x01UL << BCCU_EVFSR_FFS_Pos) /*!< BCCU EVFSR: FFS Mask */\r
-#define BCCU_EVFSR_EFS_Pos 3 /*!< BCCU EVFSR: EFS Position */\r
-#define BCCU_EVFSR_EFS_Msk (0x01UL << BCCU_EVFSR_EFS_Pos) /*!< BCCU EVFSR: EFS Mask */\r
-#define BCCU_EVFSR_TPFS_Pos 4 /*!< BCCU EVFSR: TPFS Position */\r
-#define BCCU_EVFSR_TPFS_Msk (0x01UL << BCCU_EVFSR_TPFS_Pos) /*!< BCCU EVFSR: TPFS Mask */\r
-#define BCCU_EVFSR_TPS_Pos 6 /*!< BCCU EVFSR: TPS Position */\r
-#define BCCU_EVFSR_TPS_Msk (0x01UL << BCCU_EVFSR_TPS_Pos) /*!< BCCU EVFSR: TPS Mask */\r
-\r
-/* --------------------------------- BCCU_EVFCR --------------------------------- */\r
-#define BCCU_EVFCR_T0FC_Pos 0 /*!< BCCU EVFCR: T0FC Position */\r
-#define BCCU_EVFCR_T0FC_Msk (0x01UL << BCCU_EVFCR_T0FC_Pos) /*!< BCCU EVFCR: T0FC Mask */\r
-#define BCCU_EVFCR_T1FC_Pos 1 /*!< BCCU EVFCR: T1FC Position */\r
-#define BCCU_EVFCR_T1FC_Msk (0x01UL << BCCU_EVFCR_T1FC_Pos) /*!< BCCU EVFCR: T1FC Mask */\r
-#define BCCU_EVFCR_FFC_Pos 2 /*!< BCCU EVFCR: FFC Position */\r
-#define BCCU_EVFCR_FFC_Msk (0x01UL << BCCU_EVFCR_FFC_Pos) /*!< BCCU EVFCR: FFC Mask */\r
-#define BCCU_EVFCR_EFC_Pos 3 /*!< BCCU EVFCR: EFC Position */\r
-#define BCCU_EVFCR_EFC_Msk (0x01UL << BCCU_EVFCR_EFC_Pos) /*!< BCCU EVFCR: EFC Mask */\r
-#define BCCU_EVFCR_TPFC_Pos 4 /*!< BCCU EVFCR: TPFC Position */\r
-#define BCCU_EVFCR_TPFC_Msk (0x01UL << BCCU_EVFCR_TPFC_Pos) /*!< BCCU EVFCR: TPFC Mask */\r
-#define BCCU_EVFCR_TPC_Pos 6 /*!< BCCU EVFCR: TPC Position */\r
-#define BCCU_EVFCR_TPC_Msk (0x01UL << BCCU_EVFCR_TPC_Pos) /*!< BCCU EVFCR: TPC Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'BCCU_CH' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* -------------------------------- BCCU_CH_INTS -------------------------------- */\r
-#define BCCU_CH_INTS_TCHINT_Pos 0 /*!< BCCU_CH INTS: TCHINT Position */\r
-#define BCCU_CH_INTS_TCHINT_Msk (0x00000fffUL << BCCU_CH_INTS_TCHINT_Pos) /*!< BCCU_CH INTS: TCHINT Mask */\r
-\r
-/* --------------------------------- BCCU_CH_INT -------------------------------- */\r
-#define BCCU_CH_INT_CHINT_Pos 0 /*!< BCCU_CH INT: CHINT Position */\r
-#define BCCU_CH_INT_CHINT_Msk (0x00000fffUL << BCCU_CH_INT_CHINT_Pos) /*!< BCCU_CH INT: CHINT Mask */\r
-\r
-/* ------------------------------ BCCU_CH_CHCONFIG ------------------------------ */\r
-#define BCCU_CH_CHCONFIG_PKTH_Pos 0 /*!< BCCU_CH CHCONFIG: PKTH Position */\r
-#define BCCU_CH_CHCONFIG_PKTH_Msk (0x07UL << BCCU_CH_CHCONFIG_PKTH_Pos) /*!< BCCU_CH CHCONFIG: PKTH Mask */\r
-#define BCCU_CH_CHCONFIG_PEN_Pos 3 /*!< BCCU_CH CHCONFIG: PEN Position */\r
-#define BCCU_CH_CHCONFIG_PEN_Msk (0x01UL << BCCU_CH_CHCONFIG_PEN_Pos) /*!< BCCU_CH CHCONFIG: PEN Mask */\r
-#define BCCU_CH_CHCONFIG_DSEL_Pos 4 /*!< BCCU_CH CHCONFIG: DSEL Position */\r
-#define BCCU_CH_CHCONFIG_DSEL_Msk (0x07UL << BCCU_CH_CHCONFIG_DSEL_Pos) /*!< BCCU_CH CHCONFIG: DSEL Mask */\r
-#define BCCU_CH_CHCONFIG_DBP_Pos 7 /*!< BCCU_CH CHCONFIG: DBP Position */\r
-#define BCCU_CH_CHCONFIG_DBP_Msk (0x01UL << BCCU_CH_CHCONFIG_DBP_Pos) /*!< BCCU_CH CHCONFIG: DBP Mask */\r
-#define BCCU_CH_CHCONFIG_GEN_Pos 8 /*!< BCCU_CH CHCONFIG: GEN Position */\r
-#define BCCU_CH_CHCONFIG_GEN_Msk (0x01UL << BCCU_CH_CHCONFIG_GEN_Pos) /*!< BCCU_CH CHCONFIG: GEN Mask */\r
-#define BCCU_CH_CHCONFIG_WEN_Pos 9 /*!< BCCU_CH CHCONFIG: WEN Position */\r
-#define BCCU_CH_CHCONFIG_WEN_Msk (0x01UL << BCCU_CH_CHCONFIG_WEN_Pos) /*!< BCCU_CH CHCONFIG: WEN Mask */\r
-#define BCCU_CH_CHCONFIG_TRED_Pos 10 /*!< BCCU_CH CHCONFIG: TRED Position */\r
-#define BCCU_CH_CHCONFIG_TRED_Msk (0x01UL << BCCU_CH_CHCONFIG_TRED_Pos) /*!< BCCU_CH CHCONFIG: TRED Mask */\r
-#define BCCU_CH_CHCONFIG_ENFT_Pos 11 /*!< BCCU_CH CHCONFIG: ENFT Position */\r
-#define BCCU_CH_CHCONFIG_ENFT_Msk (0x01UL << BCCU_CH_CHCONFIG_ENFT_Pos) /*!< BCCU_CH CHCONFIG: ENFT Mask */\r
-#define BCCU_CH_CHCONFIG_LINPRES_Pos 16 /*!< BCCU_CH CHCONFIG: LINPRES Position */\r
-#define BCCU_CH_CHCONFIG_LINPRES_Msk (0x000003ffUL << BCCU_CH_CHCONFIG_LINPRES_Pos) /*!< BCCU_CH CHCONFIG: LINPRES Mask */\r
-\r
-/* -------------------------------- BCCU_CH_PKCMP ------------------------------- */\r
-#define BCCU_CH_PKCMP_OFFCMP_Pos 0 /*!< BCCU_CH PKCMP: OFFCMP Position */\r
-#define BCCU_CH_PKCMP_OFFCMP_Msk (0x000000ffUL << BCCU_CH_PKCMP_OFFCMP_Pos) /*!< BCCU_CH PKCMP: OFFCMP Mask */\r
-#define BCCU_CH_PKCMP_ONCMP_Pos 16 /*!< BCCU_CH PKCMP: ONCMP Position */\r
-#define BCCU_CH_PKCMP_ONCMP_Msk (0x000000ffUL << BCCU_CH_PKCMP_ONCMP_Pos) /*!< BCCU_CH PKCMP: ONCMP Mask */\r
-\r
-/* ------------------------------- BCCU_CH_PKCNTR ------------------------------- */\r
-#define BCCU_CH_PKCNTR_OFFCNTVAL_Pos 0 /*!< BCCU_CH PKCNTR: OFFCNTVAL Position */\r
-#define BCCU_CH_PKCNTR_OFFCNTVAL_Msk (0x000000ffUL << BCCU_CH_PKCNTR_OFFCNTVAL_Pos) /*!< BCCU_CH PKCNTR: OFFCNTVAL Mask */\r
-#define BCCU_CH_PKCNTR_ONCNTVAL_Pos 16 /*!< BCCU_CH PKCNTR: ONCNTVAL Position */\r
-#define BCCU_CH_PKCNTR_ONCNTVAL_Msk (0x000000ffUL << BCCU_CH_PKCNTR_ONCNTVAL_Pos) /*!< BCCU_CH PKCNTR: ONCNTVAL Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Group 'BCCU_DE' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* --------------------------------- BCCU_DE_DLS -------------------------------- */\r
-#define BCCU_DE_DLS_TDLEV_Pos 0 /*!< BCCU_DE DLS: TDLEV Position */\r
-#define BCCU_DE_DLS_TDLEV_Msk (0x00000fffUL << BCCU_DE_DLS_TDLEV_Pos) /*!< BCCU_DE DLS: TDLEV Mask */\r
-\r
-/* --------------------------------- BCCU_DE_DL --------------------------------- */\r
-#define BCCU_DE_DL_DLEV_Pos 0 /*!< BCCU_DE DL: DLEV Position */\r
-#define BCCU_DE_DL_DLEV_Msk (0x00000fffUL << BCCU_DE_DL_DLEV_Pos) /*!< BCCU_DE DL: DLEV Mask */\r
-\r
-/* --------------------------------- BCCU_DE_DTT -------------------------------- */\r
-#define BCCU_DE_DTT_DIMDIV_Pos 0 /*!< BCCU_DE DTT: DIMDIV Position */\r
-#define BCCU_DE_DTT_DIMDIV_Msk (0x000003ffUL << BCCU_DE_DTT_DIMDIV_Pos) /*!< BCCU_DE DTT: DIMDIV Mask */\r
-#define BCCU_DE_DTT_DTEN_Pos 16 /*!< BCCU_DE DTT: DTEN Position */\r
-#define BCCU_DE_DTT_DTEN_Msk (0x01UL << BCCU_DE_DTT_DTEN_Pos) /*!< BCCU_DE DTT: DTEN Mask */\r
-#define BCCU_DE_DTT_CSEL_Pos 17 /*!< BCCU_DE DTT: CSEL Position */\r
-#define BCCU_DE_DTT_CSEL_Msk (0x01UL << BCCU_DE_DTT_CSEL_Pos) /*!< BCCU_DE DTT: CSEL Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PORT0' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- PORT0_OUT --------------------------------- */\r
-#define PORT0_OUT_P0_Pos 0 /*!< PORT0 OUT: P0 Position */\r
-#define PORT0_OUT_P0_Msk (0x01UL << PORT0_OUT_P0_Pos) /*!< PORT0 OUT: P0 Mask */\r
-#define PORT0_OUT_P1_Pos 1 /*!< PORT0 OUT: P1 Position */\r
-#define PORT0_OUT_P1_Msk (0x01UL << PORT0_OUT_P1_Pos) /*!< PORT0 OUT: P1 Mask */\r
-#define PORT0_OUT_P2_Pos 2 /*!< PORT0 OUT: P2 Position */\r
-#define PORT0_OUT_P2_Msk (0x01UL << PORT0_OUT_P2_Pos) /*!< PORT0 OUT: P2 Mask */\r
-#define PORT0_OUT_P3_Pos 3 /*!< PORT0 OUT: P3 Position */\r
-#define PORT0_OUT_P3_Msk (0x01UL << PORT0_OUT_P3_Pos) /*!< PORT0 OUT: P3 Mask */\r
-#define PORT0_OUT_P4_Pos 4 /*!< PORT0 OUT: P4 Position */\r
-#define PORT0_OUT_P4_Msk (0x01UL << PORT0_OUT_P4_Pos) /*!< PORT0 OUT: P4 Mask */\r
-#define PORT0_OUT_P5_Pos 5 /*!< PORT0 OUT: P5 Position */\r
-#define PORT0_OUT_P5_Msk (0x01UL << PORT0_OUT_P5_Pos) /*!< PORT0 OUT: P5 Mask */\r
-#define PORT0_OUT_P6_Pos 6 /*!< PORT0 OUT: P6 Position */\r
-#define PORT0_OUT_P6_Msk (0x01UL << PORT0_OUT_P6_Pos) /*!< PORT0 OUT: P6 Mask */\r
-#define PORT0_OUT_P7_Pos 7 /*!< PORT0 OUT: P7 Position */\r
-#define PORT0_OUT_P7_Msk (0x01UL << PORT0_OUT_P7_Pos) /*!< PORT0 OUT: P7 Mask */\r
-#define PORT0_OUT_P8_Pos 8 /*!< PORT0 OUT: P8 Position */\r
-#define PORT0_OUT_P8_Msk (0x01UL << PORT0_OUT_P8_Pos) /*!< PORT0 OUT: P8 Mask */\r
-#define PORT0_OUT_P9_Pos 9 /*!< PORT0 OUT: P9 Position */\r
-#define PORT0_OUT_P9_Msk (0x01UL << PORT0_OUT_P9_Pos) /*!< PORT0 OUT: P9 Mask */\r
-#define PORT0_OUT_P10_Pos 10 /*!< PORT0 OUT: P10 Position */\r
-#define PORT0_OUT_P10_Msk (0x01UL << PORT0_OUT_P10_Pos) /*!< PORT0 OUT: P10 Mask */\r
-#define PORT0_OUT_P11_Pos 11 /*!< PORT0 OUT: P11 Position */\r
-#define PORT0_OUT_P11_Msk (0x01UL << PORT0_OUT_P11_Pos) /*!< PORT0 OUT: P11 Mask */\r
-#define PORT0_OUT_P12_Pos 12 /*!< PORT0 OUT: P12 Position */\r
-#define PORT0_OUT_P12_Msk (0x01UL << PORT0_OUT_P12_Pos) /*!< PORT0 OUT: P12 Mask */\r
-#define PORT0_OUT_P13_Pos 13 /*!< PORT0 OUT: P13 Position */\r
-#define PORT0_OUT_P13_Msk (0x01UL << PORT0_OUT_P13_Pos) /*!< PORT0 OUT: P13 Mask */\r
-#define PORT0_OUT_P14_Pos 14 /*!< PORT0 OUT: P14 Position */\r
-#define PORT0_OUT_P14_Msk (0x01UL << PORT0_OUT_P14_Pos) /*!< PORT0 OUT: P14 Mask */\r
-#define PORT0_OUT_P15_Pos 15 /*!< PORT0 OUT: P15 Position */\r
-#define PORT0_OUT_P15_Msk (0x01UL << PORT0_OUT_P15_Pos) /*!< PORT0 OUT: P15 Mask */\r
-\r
-/* ---------------------------------- PORT0_OMR --------------------------------- */\r
-#define PORT0_OMR_PS0_Pos 0 /*!< PORT0 OMR: PS0 Position */\r
-#define PORT0_OMR_PS0_Msk (0x01UL << PORT0_OMR_PS0_Pos) /*!< PORT0 OMR: PS0 Mask */\r
-#define PORT0_OMR_PS1_Pos 1 /*!< PORT0 OMR: PS1 Position */\r
-#define PORT0_OMR_PS1_Msk (0x01UL << PORT0_OMR_PS1_Pos) /*!< PORT0 OMR: PS1 Mask */\r
-#define PORT0_OMR_PS2_Pos 2 /*!< PORT0 OMR: PS2 Position */\r
-#define PORT0_OMR_PS2_Msk (0x01UL << PORT0_OMR_PS2_Pos) /*!< PORT0 OMR: PS2 Mask */\r
-#define PORT0_OMR_PS3_Pos 3 /*!< PORT0 OMR: PS3 Position */\r
-#define PORT0_OMR_PS3_Msk (0x01UL << PORT0_OMR_PS3_Pos) /*!< PORT0 OMR: PS3 Mask */\r
-#define PORT0_OMR_PS4_Pos 4 /*!< PORT0 OMR: PS4 Position */\r
-#define PORT0_OMR_PS4_Msk (0x01UL << PORT0_OMR_PS4_Pos) /*!< PORT0 OMR: PS4 Mask */\r
-#define PORT0_OMR_PS5_Pos 5 /*!< PORT0 OMR: PS5 Position */\r
-#define PORT0_OMR_PS5_Msk (0x01UL << PORT0_OMR_PS5_Pos) /*!< PORT0 OMR: PS5 Mask */\r
-#define PORT0_OMR_PS6_Pos 6 /*!< PORT0 OMR: PS6 Position */\r
-#define PORT0_OMR_PS6_Msk (0x01UL << PORT0_OMR_PS6_Pos) /*!< PORT0 OMR: PS6 Mask */\r
-#define PORT0_OMR_PS7_Pos 7 /*!< PORT0 OMR: PS7 Position */\r
-#define PORT0_OMR_PS7_Msk (0x01UL << PORT0_OMR_PS7_Pos) /*!< PORT0 OMR: PS7 Mask */\r
-#define PORT0_OMR_PS8_Pos 8 /*!< PORT0 OMR: PS8 Position */\r
-#define PORT0_OMR_PS8_Msk (0x01UL << PORT0_OMR_PS8_Pos) /*!< PORT0 OMR: PS8 Mask */\r
-#define PORT0_OMR_PS9_Pos 9 /*!< PORT0 OMR: PS9 Position */\r
-#define PORT0_OMR_PS9_Msk (0x01UL << PORT0_OMR_PS9_Pos) /*!< PORT0 OMR: PS9 Mask */\r
-#define PORT0_OMR_PS10_Pos 10 /*!< PORT0 OMR: PS10 Position */\r
-#define PORT0_OMR_PS10_Msk (0x01UL << PORT0_OMR_PS10_Pos) /*!< PORT0 OMR: PS10 Mask */\r
-#define PORT0_OMR_PS11_Pos 11 /*!< PORT0 OMR: PS11 Position */\r
-#define PORT0_OMR_PS11_Msk (0x01UL << PORT0_OMR_PS11_Pos) /*!< PORT0 OMR: PS11 Mask */\r
-#define PORT0_OMR_PS12_Pos 12 /*!< PORT0 OMR: PS12 Position */\r
-#define PORT0_OMR_PS12_Msk (0x01UL << PORT0_OMR_PS12_Pos) /*!< PORT0 OMR: PS12 Mask */\r
-#define PORT0_OMR_PS13_Pos 13 /*!< PORT0 OMR: PS13 Position */\r
-#define PORT0_OMR_PS13_Msk (0x01UL << PORT0_OMR_PS13_Pos) /*!< PORT0 OMR: PS13 Mask */\r
-#define PORT0_OMR_PS14_Pos 14 /*!< PORT0 OMR: PS14 Position */\r
-#define PORT0_OMR_PS14_Msk (0x01UL << PORT0_OMR_PS14_Pos) /*!< PORT0 OMR: PS14 Mask */\r
-#define PORT0_OMR_PS15_Pos 15 /*!< PORT0 OMR: PS15 Position */\r
-#define PORT0_OMR_PS15_Msk (0x01UL << PORT0_OMR_PS15_Pos) /*!< PORT0 OMR: PS15 Mask */\r
-#define PORT0_OMR_PR0_Pos 16 /*!< PORT0 OMR: PR0 Position */\r
-#define PORT0_OMR_PR0_Msk (0x01UL << PORT0_OMR_PR0_Pos) /*!< PORT0 OMR: PR0 Mask */\r
-#define PORT0_OMR_PR1_Pos 17 /*!< PORT0 OMR: PR1 Position */\r
-#define PORT0_OMR_PR1_Msk (0x01UL << PORT0_OMR_PR1_Pos) /*!< PORT0 OMR: PR1 Mask */\r
-#define PORT0_OMR_PR2_Pos 18 /*!< PORT0 OMR: PR2 Position */\r
-#define PORT0_OMR_PR2_Msk (0x01UL << PORT0_OMR_PR2_Pos) /*!< PORT0 OMR: PR2 Mask */\r
-#define PORT0_OMR_PR3_Pos 19 /*!< PORT0 OMR: PR3 Position */\r
-#define PORT0_OMR_PR3_Msk (0x01UL << PORT0_OMR_PR3_Pos) /*!< PORT0 OMR: PR3 Mask */\r
-#define PORT0_OMR_PR4_Pos 20 /*!< PORT0 OMR: PR4 Position */\r
-#define PORT0_OMR_PR4_Msk (0x01UL << PORT0_OMR_PR4_Pos) /*!< PORT0 OMR: PR4 Mask */\r
-#define PORT0_OMR_PR5_Pos 21 /*!< PORT0 OMR: PR5 Position */\r
-#define PORT0_OMR_PR5_Msk (0x01UL << PORT0_OMR_PR5_Pos) /*!< PORT0 OMR: PR5 Mask */\r
-#define PORT0_OMR_PR6_Pos 22 /*!< PORT0 OMR: PR6 Position */\r
-#define PORT0_OMR_PR6_Msk (0x01UL << PORT0_OMR_PR6_Pos) /*!< PORT0 OMR: PR6 Mask */\r
-#define PORT0_OMR_PR7_Pos 23 /*!< PORT0 OMR: PR7 Position */\r
-#define PORT0_OMR_PR7_Msk (0x01UL << PORT0_OMR_PR7_Pos) /*!< PORT0 OMR: PR7 Mask */\r
-#define PORT0_OMR_PR8_Pos 24 /*!< PORT0 OMR: PR8 Position */\r
-#define PORT0_OMR_PR8_Msk (0x01UL << PORT0_OMR_PR8_Pos) /*!< PORT0 OMR: PR8 Mask */\r
-#define PORT0_OMR_PR9_Pos 25 /*!< PORT0 OMR: PR9 Position */\r
-#define PORT0_OMR_PR9_Msk (0x01UL << PORT0_OMR_PR9_Pos) /*!< PORT0 OMR: PR9 Mask */\r
-#define PORT0_OMR_PR10_Pos 26 /*!< PORT0 OMR: PR10 Position */\r
-#define PORT0_OMR_PR10_Msk (0x01UL << PORT0_OMR_PR10_Pos) /*!< PORT0 OMR: PR10 Mask */\r
-#define PORT0_OMR_PR11_Pos 27 /*!< PORT0 OMR: PR11 Position */\r
-#define PORT0_OMR_PR11_Msk (0x01UL << PORT0_OMR_PR11_Pos) /*!< PORT0 OMR: PR11 Mask */\r
-#define PORT0_OMR_PR12_Pos 28 /*!< PORT0 OMR: PR12 Position */\r
-#define PORT0_OMR_PR12_Msk (0x01UL << PORT0_OMR_PR12_Pos) /*!< PORT0 OMR: PR12 Mask */\r
-#define PORT0_OMR_PR13_Pos 29 /*!< PORT0 OMR: PR13 Position */\r
-#define PORT0_OMR_PR13_Msk (0x01UL << PORT0_OMR_PR13_Pos) /*!< PORT0 OMR: PR13 Mask */\r
-#define PORT0_OMR_PR14_Pos 30 /*!< PORT0 OMR: PR14 Position */\r
-#define PORT0_OMR_PR14_Msk (0x01UL << PORT0_OMR_PR14_Pos) /*!< PORT0 OMR: PR14 Mask */\r
-#define PORT0_OMR_PR15_Pos 31 /*!< PORT0 OMR: PR15 Position */\r
-#define PORT0_OMR_PR15_Msk (0x01UL << PORT0_OMR_PR15_Pos) /*!< PORT0 OMR: PR15 Mask */\r
-\r
-/* --------------------------------- PORT0_IOCR0 -------------------------------- */\r
-#define PORT0_IOCR0_PC0_Pos 3 /*!< PORT0 IOCR0: PC0 Position */\r
-#define PORT0_IOCR0_PC0_Msk (0x1fUL << PORT0_IOCR0_PC0_Pos) /*!< PORT0 IOCR0: PC0 Mask */\r
-#define PORT0_IOCR0_PC1_Pos 11 /*!< PORT0 IOCR0: PC1 Position */\r
-#define PORT0_IOCR0_PC1_Msk (0x1fUL << PORT0_IOCR0_PC1_Pos) /*!< PORT0 IOCR0: PC1 Mask */\r
-#define PORT0_IOCR0_PC2_Pos 19 /*!< PORT0 IOCR0: PC2 Position */\r
-#define PORT0_IOCR0_PC2_Msk (0x1fUL << PORT0_IOCR0_PC2_Pos) /*!< PORT0 IOCR0: PC2 Mask */\r
-#define PORT0_IOCR0_PC3_Pos 27 /*!< PORT0 IOCR0: PC3 Position */\r
-#define PORT0_IOCR0_PC3_Msk (0x1fUL << PORT0_IOCR0_PC3_Pos) /*!< PORT0 IOCR0: PC3 Mask */\r
-\r
-/* --------------------------------- PORT0_IOCR4 -------------------------------- */\r
-#define PORT0_IOCR4_PC4_Pos 3 /*!< PORT0 IOCR4: PC4 Position */\r
-#define PORT0_IOCR4_PC4_Msk (0x1fUL << PORT0_IOCR4_PC4_Pos) /*!< PORT0 IOCR4: PC4 Mask */\r
-#define PORT0_IOCR4_PC5_Pos 11 /*!< PORT0 IOCR4: PC5 Position */\r
-#define PORT0_IOCR4_PC5_Msk (0x1fUL << PORT0_IOCR4_PC5_Pos) /*!< PORT0 IOCR4: PC5 Mask */\r
-#define PORT0_IOCR4_PC6_Pos 19 /*!< PORT0 IOCR4: PC6 Position */\r
-#define PORT0_IOCR4_PC6_Msk (0x1fUL << PORT0_IOCR4_PC6_Pos) /*!< PORT0 IOCR4: PC6 Mask */\r
-#define PORT0_IOCR4_PC7_Pos 27 /*!< PORT0 IOCR4: PC7 Position */\r
-#define PORT0_IOCR4_PC7_Msk (0x1fUL << PORT0_IOCR4_PC7_Pos) /*!< PORT0 IOCR4: PC7 Mask */\r
-\r
-/* --------------------------------- PORT0_IOCR8 -------------------------------- */\r
-#define PORT0_IOCR8_PC8_Pos 3 /*!< PORT0 IOCR8: PC8 Position */\r
-#define PORT0_IOCR8_PC8_Msk (0x1fUL << PORT0_IOCR8_PC8_Pos) /*!< PORT0 IOCR8: PC8 Mask */\r
-#define PORT0_IOCR8_PC9_Pos 11 /*!< PORT0 IOCR8: PC9 Position */\r
-#define PORT0_IOCR8_PC9_Msk (0x1fUL << PORT0_IOCR8_PC9_Pos) /*!< PORT0 IOCR8: PC9 Mask */\r
-#define PORT0_IOCR8_PC10_Pos 19 /*!< PORT0 IOCR8: PC10 Position */\r
-#define PORT0_IOCR8_PC10_Msk (0x1fUL << PORT0_IOCR8_PC10_Pos) /*!< PORT0 IOCR8: PC10 Mask */\r
-#define PORT0_IOCR8_PC11_Pos 27 /*!< PORT0 IOCR8: PC11 Position */\r
-#define PORT0_IOCR8_PC11_Msk (0x1fUL << PORT0_IOCR8_PC11_Pos) /*!< PORT0 IOCR8: PC11 Mask */\r
-\r
-/* -------------------------------- PORT0_IOCR12 -------------------------------- */\r
-#define PORT0_IOCR12_PC12_Pos 3 /*!< PORT0 IOCR12: PC12 Position */\r
-#define PORT0_IOCR12_PC12_Msk (0x1fUL << PORT0_IOCR12_PC12_Pos) /*!< PORT0 IOCR12: PC12 Mask */\r
-#define PORT0_IOCR12_PC13_Pos 11 /*!< PORT0 IOCR12: PC13 Position */\r
-#define PORT0_IOCR12_PC13_Msk (0x1fUL << PORT0_IOCR12_PC13_Pos) /*!< PORT0 IOCR12: PC13 Mask */\r
-#define PORT0_IOCR12_PC14_Pos 19 /*!< PORT0 IOCR12: PC14 Position */\r
-#define PORT0_IOCR12_PC14_Msk (0x1fUL << PORT0_IOCR12_PC14_Pos) /*!< PORT0 IOCR12: PC14 Mask */\r
-#define PORT0_IOCR12_PC15_Pos 27 /*!< PORT0 IOCR12: PC15 Position */\r
-#define PORT0_IOCR12_PC15_Msk (0x1fUL << PORT0_IOCR12_PC15_Pos) /*!< PORT0 IOCR12: PC15 Mask */\r
-\r
-/* ---------------------------------- PORT0_IN ---------------------------------- */\r
-#define PORT0_IN_P0_Pos 0 /*!< PORT0 IN: P0 Position */\r
-#define PORT0_IN_P0_Msk (0x01UL << PORT0_IN_P0_Pos) /*!< PORT0 IN: P0 Mask */\r
-#define PORT0_IN_P1_Pos 1 /*!< PORT0 IN: P1 Position */\r
-#define PORT0_IN_P1_Msk (0x01UL << PORT0_IN_P1_Pos) /*!< PORT0 IN: P1 Mask */\r
-#define PORT0_IN_P2_Pos 2 /*!< PORT0 IN: P2 Position */\r
-#define PORT0_IN_P2_Msk (0x01UL << PORT0_IN_P2_Pos) /*!< PORT0 IN: P2 Mask */\r
-#define PORT0_IN_P3_Pos 3 /*!< PORT0 IN: P3 Position */\r
-#define PORT0_IN_P3_Msk (0x01UL << PORT0_IN_P3_Pos) /*!< PORT0 IN: P3 Mask */\r
-#define PORT0_IN_P4_Pos 4 /*!< PORT0 IN: P4 Position */\r
-#define PORT0_IN_P4_Msk (0x01UL << PORT0_IN_P4_Pos) /*!< PORT0 IN: P4 Mask */\r
-#define PORT0_IN_P5_Pos 5 /*!< PORT0 IN: P5 Position */\r
-#define PORT0_IN_P5_Msk (0x01UL << PORT0_IN_P5_Pos) /*!< PORT0 IN: P5 Mask */\r
-#define PORT0_IN_P6_Pos 6 /*!< PORT0 IN: P6 Position */\r
-#define PORT0_IN_P6_Msk (0x01UL << PORT0_IN_P6_Pos) /*!< PORT0 IN: P6 Mask */\r
-#define PORT0_IN_P7_Pos 7 /*!< PORT0 IN: P7 Position */\r
-#define PORT0_IN_P7_Msk (0x01UL << PORT0_IN_P7_Pos) /*!< PORT0 IN: P7 Mask */\r
-#define PORT0_IN_P8_Pos 8 /*!< PORT0 IN: P8 Position */\r
-#define PORT0_IN_P8_Msk (0x01UL << PORT0_IN_P8_Pos) /*!< PORT0 IN: P8 Mask */\r
-#define PORT0_IN_P9_Pos 9 /*!< PORT0 IN: P9 Position */\r
-#define PORT0_IN_P9_Msk (0x01UL << PORT0_IN_P9_Pos) /*!< PORT0 IN: P9 Mask */\r
-#define PORT0_IN_P10_Pos 10 /*!< PORT0 IN: P10 Position */\r
-#define PORT0_IN_P10_Msk (0x01UL << PORT0_IN_P10_Pos) /*!< PORT0 IN: P10 Mask */\r
-#define PORT0_IN_P11_Pos 11 /*!< PORT0 IN: P11 Position */\r
-#define PORT0_IN_P11_Msk (0x01UL << PORT0_IN_P11_Pos) /*!< PORT0 IN: P11 Mask */\r
-#define PORT0_IN_P12_Pos 12 /*!< PORT0 IN: P12 Position */\r
-#define PORT0_IN_P12_Msk (0x01UL << PORT0_IN_P12_Pos) /*!< PORT0 IN: P12 Mask */\r
-#define PORT0_IN_P13_Pos 13 /*!< PORT0 IN: P13 Position */\r
-#define PORT0_IN_P13_Msk (0x01UL << PORT0_IN_P13_Pos) /*!< PORT0 IN: P13 Mask */\r
-#define PORT0_IN_P14_Pos 14 /*!< PORT0 IN: P14 Position */\r
-#define PORT0_IN_P14_Msk (0x01UL << PORT0_IN_P14_Pos) /*!< PORT0 IN: P14 Mask */\r
-#define PORT0_IN_P15_Pos 15 /*!< PORT0 IN: P15 Position */\r
-#define PORT0_IN_P15_Msk (0x01UL << PORT0_IN_P15_Pos) /*!< PORT0 IN: P15 Mask */\r
-\r
-/* --------------------------------- PORT0_PHCR0 -------------------------------- */\r
-#define PORT0_PHCR0_PH0_Pos 2 /*!< PORT0 PHCR0: PH0 Position */\r
-#define PORT0_PHCR0_PH0_Msk (0x01UL << PORT0_PHCR0_PH0_Pos) /*!< PORT0 PHCR0: PH0 Mask */\r
-#define PORT0_PHCR0_PH1_Pos 6 /*!< PORT0 PHCR0: PH1 Position */\r
-#define PORT0_PHCR0_PH1_Msk (0x01UL << PORT0_PHCR0_PH1_Pos) /*!< PORT0 PHCR0: PH1 Mask */\r
-#define PORT0_PHCR0_PH2_Pos 10 /*!< PORT0 PHCR0: PH2 Position */\r
-#define PORT0_PHCR0_PH2_Msk (0x01UL << PORT0_PHCR0_PH2_Pos) /*!< PORT0 PHCR0: PH2 Mask */\r
-#define PORT0_PHCR0_PH3_Pos 14 /*!< PORT0 PHCR0: PH3 Position */\r
-#define PORT0_PHCR0_PH3_Msk (0x01UL << PORT0_PHCR0_PH3_Pos) /*!< PORT0 PHCR0: PH3 Mask */\r
-#define PORT0_PHCR0_PH4_Pos 18 /*!< PORT0 PHCR0: PH4 Position */\r
-#define PORT0_PHCR0_PH4_Msk (0x01UL << PORT0_PHCR0_PH4_Pos) /*!< PORT0 PHCR0: PH4 Mask */\r
-#define PORT0_PHCR0_PH5_Pos 22 /*!< PORT0 PHCR0: PH5 Position */\r
-#define PORT0_PHCR0_PH5_Msk (0x01UL << PORT0_PHCR0_PH5_Pos) /*!< PORT0 PHCR0: PH5 Mask */\r
-#define PORT0_PHCR0_PH6_Pos 26 /*!< PORT0 PHCR0: PH6 Position */\r
-#define PORT0_PHCR0_PH6_Msk (0x01UL << PORT0_PHCR0_PH6_Pos) /*!< PORT0 PHCR0: PH6 Mask */\r
-#define PORT0_PHCR0_PH7_Pos 30 /*!< PORT0 PHCR0: PH7 Position */\r
-#define PORT0_PHCR0_PH7_Msk (0x01UL << PORT0_PHCR0_PH7_Pos) /*!< PORT0 PHCR0: PH7 Mask */\r
-\r
-/* --------------------------------- PORT0_PHCR1 -------------------------------- */\r
-#define PORT0_PHCR1_PH8_Pos 2 /*!< PORT0 PHCR1: PH8 Position */\r
-#define PORT0_PHCR1_PH8_Msk (0x01UL << PORT0_PHCR1_PH8_Pos) /*!< PORT0 PHCR1: PH8 Mask */\r
-#define PORT0_PHCR1_PH9_Pos 6 /*!< PORT0 PHCR1: PH9 Position */\r
-#define PORT0_PHCR1_PH9_Msk (0x01UL << PORT0_PHCR1_PH9_Pos) /*!< PORT0 PHCR1: PH9 Mask */\r
-#define PORT0_PHCR1_PH10_Pos 10 /*!< PORT0 PHCR1: PH10 Position */\r
-#define PORT0_PHCR1_PH10_Msk (0x01UL << PORT0_PHCR1_PH10_Pos) /*!< PORT0 PHCR1: PH10 Mask */\r
-#define PORT0_PHCR1_PH11_Pos 14 /*!< PORT0 PHCR1: PH11 Position */\r
-#define PORT0_PHCR1_PH11_Msk (0x01UL << PORT0_PHCR1_PH11_Pos) /*!< PORT0 PHCR1: PH11 Mask */\r
-#define PORT0_PHCR1_PH12_Pos 18 /*!< PORT0 PHCR1: PH12 Position */\r
-#define PORT0_PHCR1_PH12_Msk (0x01UL << PORT0_PHCR1_PH12_Pos) /*!< PORT0 PHCR1: PH12 Mask */\r
-#define PORT0_PHCR1_PH13_Pos 22 /*!< PORT0 PHCR1: PH13 Position */\r
-#define PORT0_PHCR1_PH13_Msk (0x01UL << PORT0_PHCR1_PH13_Pos) /*!< PORT0 PHCR1: PH13 Mask */\r
-#define PORT0_PHCR1_PH14_Pos 26 /*!< PORT0 PHCR1: PH14 Position */\r
-#define PORT0_PHCR1_PH14_Msk (0x01UL << PORT0_PHCR1_PH14_Pos) /*!< PORT0 PHCR1: PH14 Mask */\r
-#define PORT0_PHCR1_PH15_Pos 30 /*!< PORT0 PHCR1: PH15 Position */\r
-#define PORT0_PHCR1_PH15_Msk (0x01UL << PORT0_PHCR1_PH15_Pos) /*!< PORT0 PHCR1: PH15 Mask */\r
-\r
-/* --------------------------------- PORT0_PDISC -------------------------------- */\r
-#define PORT0_PDISC_PDIS0_Pos 0 /*!< PORT0 PDISC: PDIS0 Position */\r
-#define PORT0_PDISC_PDIS0_Msk (0x01UL << PORT0_PDISC_PDIS0_Pos) /*!< PORT0 PDISC: PDIS0 Mask */\r
-#define PORT0_PDISC_PDIS1_Pos 1 /*!< PORT0 PDISC: PDIS1 Position */\r
-#define PORT0_PDISC_PDIS1_Msk (0x01UL << PORT0_PDISC_PDIS1_Pos) /*!< PORT0 PDISC: PDIS1 Mask */\r
-#define PORT0_PDISC_PDIS2_Pos 2 /*!< PORT0 PDISC: PDIS2 Position */\r
-#define PORT0_PDISC_PDIS2_Msk (0x01UL << PORT0_PDISC_PDIS2_Pos) /*!< PORT0 PDISC: PDIS2 Mask */\r
-#define PORT0_PDISC_PDIS3_Pos 3 /*!< PORT0 PDISC: PDIS3 Position */\r
-#define PORT0_PDISC_PDIS3_Msk (0x01UL << PORT0_PDISC_PDIS3_Pos) /*!< PORT0 PDISC: PDIS3 Mask */\r
-#define PORT0_PDISC_PDIS4_Pos 4 /*!< PORT0 PDISC: PDIS4 Position */\r
-#define PORT0_PDISC_PDIS4_Msk (0x01UL << PORT0_PDISC_PDIS4_Pos) /*!< PORT0 PDISC: PDIS4 Mask */\r
-#define PORT0_PDISC_PDIS5_Pos 5 /*!< PORT0 PDISC: PDIS5 Position */\r
-#define PORT0_PDISC_PDIS5_Msk (0x01UL << PORT0_PDISC_PDIS5_Pos) /*!< PORT0 PDISC: PDIS5 Mask */\r
-#define PORT0_PDISC_PDIS6_Pos 6 /*!< PORT0 PDISC: PDIS6 Position */\r
-#define PORT0_PDISC_PDIS6_Msk (0x01UL << PORT0_PDISC_PDIS6_Pos) /*!< PORT0 PDISC: PDIS6 Mask */\r
-#define PORT0_PDISC_PDIS7_Pos 7 /*!< PORT0 PDISC: PDIS7 Position */\r
-#define PORT0_PDISC_PDIS7_Msk (0x01UL << PORT0_PDISC_PDIS7_Pos) /*!< PORT0 PDISC: PDIS7 Mask */\r
-#define PORT0_PDISC_PDIS8_Pos 8 /*!< PORT0 PDISC: PDIS8 Position */\r
-#define PORT0_PDISC_PDIS8_Msk (0x01UL << PORT0_PDISC_PDIS8_Pos) /*!< PORT0 PDISC: PDIS8 Mask */\r
-#define PORT0_PDISC_PDIS9_Pos 9 /*!< PORT0 PDISC: PDIS9 Position */\r
-#define PORT0_PDISC_PDIS9_Msk (0x01UL << PORT0_PDISC_PDIS9_Pos) /*!< PORT0 PDISC: PDIS9 Mask */\r
-#define PORT0_PDISC_PDIS10_Pos 10 /*!< PORT0 PDISC: PDIS10 Position */\r
-#define PORT0_PDISC_PDIS10_Msk (0x01UL << PORT0_PDISC_PDIS10_Pos) /*!< PORT0 PDISC: PDIS10 Mask */\r
-#define PORT0_PDISC_PDIS11_Pos 11 /*!< PORT0 PDISC: PDIS11 Position */\r
-#define PORT0_PDISC_PDIS11_Msk (0x01UL << PORT0_PDISC_PDIS11_Pos) /*!< PORT0 PDISC: PDIS11 Mask */\r
-#define PORT0_PDISC_PDIS12_Pos 12 /*!< PORT0 PDISC: PDIS12 Position */\r
-#define PORT0_PDISC_PDIS12_Msk (0x01UL << PORT0_PDISC_PDIS12_Pos) /*!< PORT0 PDISC: PDIS12 Mask */\r
-#define PORT0_PDISC_PDIS13_Pos 13 /*!< PORT0 PDISC: PDIS13 Position */\r
-#define PORT0_PDISC_PDIS13_Msk (0x01UL << PORT0_PDISC_PDIS13_Pos) /*!< PORT0 PDISC: PDIS13 Mask */\r
-#define PORT0_PDISC_PDIS14_Pos 14 /*!< PORT0 PDISC: PDIS14 Position */\r
-#define PORT0_PDISC_PDIS14_Msk (0x01UL << PORT0_PDISC_PDIS14_Pos) /*!< PORT0 PDISC: PDIS14 Mask */\r
-#define PORT0_PDISC_PDIS15_Pos 15 /*!< PORT0 PDISC: PDIS15 Position */\r
-#define PORT0_PDISC_PDIS15_Msk (0x01UL << PORT0_PDISC_PDIS15_Pos) /*!< PORT0 PDISC: PDIS15 Mask */\r
-\r
-/* ---------------------------------- PORT0_PPS --------------------------------- */\r
-#define PORT0_PPS_PPS0_Pos 0 /*!< PORT0 PPS: PPS0 Position */\r
-#define PORT0_PPS_PPS0_Msk (0x01UL << PORT0_PPS_PPS0_Pos) /*!< PORT0 PPS: PPS0 Mask */\r
-#define PORT0_PPS_PPS1_Pos 1 /*!< PORT0 PPS: PPS1 Position */\r
-#define PORT0_PPS_PPS1_Msk (0x01UL << PORT0_PPS_PPS1_Pos) /*!< PORT0 PPS: PPS1 Mask */\r
-#define PORT0_PPS_PPS2_Pos 2 /*!< PORT0 PPS: PPS2 Position */\r
-#define PORT0_PPS_PPS2_Msk (0x01UL << PORT0_PPS_PPS2_Pos) /*!< PORT0 PPS: PPS2 Mask */\r
-#define PORT0_PPS_PPS3_Pos 3 /*!< PORT0 PPS: PPS3 Position */\r
-#define PORT0_PPS_PPS3_Msk (0x01UL << PORT0_PPS_PPS3_Pos) /*!< PORT0 PPS: PPS3 Mask */\r
-#define PORT0_PPS_PPS4_Pos 4 /*!< PORT0 PPS: PPS4 Position */\r
-#define PORT0_PPS_PPS4_Msk (0x01UL << PORT0_PPS_PPS4_Pos) /*!< PORT0 PPS: PPS4 Mask */\r
-#define PORT0_PPS_PPS5_Pos 5 /*!< PORT0 PPS: PPS5 Position */\r
-#define PORT0_PPS_PPS5_Msk (0x01UL << PORT0_PPS_PPS5_Pos) /*!< PORT0 PPS: PPS5 Mask */\r
-#define PORT0_PPS_PPS6_Pos 6 /*!< PORT0 PPS: PPS6 Position */\r
-#define PORT0_PPS_PPS6_Msk (0x01UL << PORT0_PPS_PPS6_Pos) /*!< PORT0 PPS: PPS6 Mask */\r
-#define PORT0_PPS_PPS7_Pos 7 /*!< PORT0 PPS: PPS7 Position */\r
-#define PORT0_PPS_PPS7_Msk (0x01UL << PORT0_PPS_PPS7_Pos) /*!< PORT0 PPS: PPS7 Mask */\r
-#define PORT0_PPS_PPS8_Pos 8 /*!< PORT0 PPS: PPS8 Position */\r
-#define PORT0_PPS_PPS8_Msk (0x01UL << PORT0_PPS_PPS8_Pos) /*!< PORT0 PPS: PPS8 Mask */\r
-#define PORT0_PPS_PPS9_Pos 9 /*!< PORT0 PPS: PPS9 Position */\r
-#define PORT0_PPS_PPS9_Msk (0x01UL << PORT0_PPS_PPS9_Pos) /*!< PORT0 PPS: PPS9 Mask */\r
-#define PORT0_PPS_PPS10_Pos 10 /*!< PORT0 PPS: PPS10 Position */\r
-#define PORT0_PPS_PPS10_Msk (0x01UL << PORT0_PPS_PPS10_Pos) /*!< PORT0 PPS: PPS10 Mask */\r
-#define PORT0_PPS_PPS11_Pos 11 /*!< PORT0 PPS: PPS11 Position */\r
-#define PORT0_PPS_PPS11_Msk (0x01UL << PORT0_PPS_PPS11_Pos) /*!< PORT0 PPS: PPS11 Mask */\r
-#define PORT0_PPS_PPS12_Pos 12 /*!< PORT0 PPS: PPS12 Position */\r
-#define PORT0_PPS_PPS12_Msk (0x01UL << PORT0_PPS_PPS12_Pos) /*!< PORT0 PPS: PPS12 Mask */\r
-#define PORT0_PPS_PPS13_Pos 13 /*!< PORT0 PPS: PPS13 Position */\r
-#define PORT0_PPS_PPS13_Msk (0x01UL << PORT0_PPS_PPS13_Pos) /*!< PORT0 PPS: PPS13 Mask */\r
-#define PORT0_PPS_PPS14_Pos 14 /*!< PORT0 PPS: PPS14 Position */\r
-#define PORT0_PPS_PPS14_Msk (0x01UL << PORT0_PPS_PPS14_Pos) /*!< PORT0 PPS: PPS14 Mask */\r
-#define PORT0_PPS_PPS15_Pos 15 /*!< PORT0 PPS: PPS15 Position */\r
-#define PORT0_PPS_PPS15_Msk (0x01UL << PORT0_PPS_PPS15_Pos) /*!< PORT0 PPS: PPS15 Mask */\r
-\r
-/* --------------------------------- PORT0_HWSEL -------------------------------- */\r
-#define PORT0_HWSEL_HW0_Pos 0 /*!< PORT0 HWSEL: HW0 Position */\r
-#define PORT0_HWSEL_HW0_Msk (0x03UL << PORT0_HWSEL_HW0_Pos) /*!< PORT0 HWSEL: HW0 Mask */\r
-#define PORT0_HWSEL_HW1_Pos 2 /*!< PORT0 HWSEL: HW1 Position */\r
-#define PORT0_HWSEL_HW1_Msk (0x03UL << PORT0_HWSEL_HW1_Pos) /*!< PORT0 HWSEL: HW1 Mask */\r
-#define PORT0_HWSEL_HW2_Pos 4 /*!< PORT0 HWSEL: HW2 Position */\r
-#define PORT0_HWSEL_HW2_Msk (0x03UL << PORT0_HWSEL_HW2_Pos) /*!< PORT0 HWSEL: HW2 Mask */\r
-#define PORT0_HWSEL_HW3_Pos 6 /*!< PORT0 HWSEL: HW3 Position */\r
-#define PORT0_HWSEL_HW3_Msk (0x03UL << PORT0_HWSEL_HW3_Pos) /*!< PORT0 HWSEL: HW3 Mask */\r
-#define PORT0_HWSEL_HW4_Pos 8 /*!< PORT0 HWSEL: HW4 Position */\r
-#define PORT0_HWSEL_HW4_Msk (0x03UL << PORT0_HWSEL_HW4_Pos) /*!< PORT0 HWSEL: HW4 Mask */\r
-#define PORT0_HWSEL_HW5_Pos 10 /*!< PORT0 HWSEL: HW5 Position */\r
-#define PORT0_HWSEL_HW5_Msk (0x03UL << PORT0_HWSEL_HW5_Pos) /*!< PORT0 HWSEL: HW5 Mask */\r
-#define PORT0_HWSEL_HW6_Pos 12 /*!< PORT0 HWSEL: HW6 Position */\r
-#define PORT0_HWSEL_HW6_Msk (0x03UL << PORT0_HWSEL_HW6_Pos) /*!< PORT0 HWSEL: HW6 Mask */\r
-#define PORT0_HWSEL_HW7_Pos 14 /*!< PORT0 HWSEL: HW7 Position */\r
-#define PORT0_HWSEL_HW7_Msk (0x03UL << PORT0_HWSEL_HW7_Pos) /*!< PORT0 HWSEL: HW7 Mask */\r
-#define PORT0_HWSEL_HW8_Pos 16 /*!< PORT0 HWSEL: HW8 Position */\r
-#define PORT0_HWSEL_HW8_Msk (0x03UL << PORT0_HWSEL_HW8_Pos) /*!< PORT0 HWSEL: HW8 Mask */\r
-#define PORT0_HWSEL_HW9_Pos 18 /*!< PORT0 HWSEL: HW9 Position */\r
-#define PORT0_HWSEL_HW9_Msk (0x03UL << PORT0_HWSEL_HW9_Pos) /*!< PORT0 HWSEL: HW9 Mask */\r
-#define PORT0_HWSEL_HW10_Pos 20 /*!< PORT0 HWSEL: HW10 Position */\r
-#define PORT0_HWSEL_HW10_Msk (0x03UL << PORT0_HWSEL_HW10_Pos) /*!< PORT0 HWSEL: HW10 Mask */\r
-#define PORT0_HWSEL_HW11_Pos 22 /*!< PORT0 HWSEL: HW11 Position */\r
-#define PORT0_HWSEL_HW11_Msk (0x03UL << PORT0_HWSEL_HW11_Pos) /*!< PORT0 HWSEL: HW11 Mask */\r
-#define PORT0_HWSEL_HW12_Pos 24 /*!< PORT0 HWSEL: HW12 Position */\r
-#define PORT0_HWSEL_HW12_Msk (0x03UL << PORT0_HWSEL_HW12_Pos) /*!< PORT0 HWSEL: HW12 Mask */\r
-#define PORT0_HWSEL_HW13_Pos 26 /*!< PORT0 HWSEL: HW13 Position */\r
-#define PORT0_HWSEL_HW13_Msk (0x03UL << PORT0_HWSEL_HW13_Pos) /*!< PORT0 HWSEL: HW13 Mask */\r
-#define PORT0_HWSEL_HW14_Pos 28 /*!< PORT0 HWSEL: HW14 Position */\r
-#define PORT0_HWSEL_HW14_Msk (0x03UL << PORT0_HWSEL_HW14_Pos) /*!< PORT0 HWSEL: HW14 Mask */\r
-#define PORT0_HWSEL_HW15_Pos 30 /*!< PORT0 HWSEL: HW15 Position */\r
-#define PORT0_HWSEL_HW15_Msk (0x03UL << PORT0_HWSEL_HW15_Pos) /*!< PORT0 HWSEL: HW15 Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PORT1' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- PORT1_OUT --------------------------------- */\r
-#define PORT1_OUT_P0_Pos 0 /*!< PORT1 OUT: P0 Position */\r
-#define PORT1_OUT_P0_Msk (0x01UL << PORT1_OUT_P0_Pos) /*!< PORT1 OUT: P0 Mask */\r
-#define PORT1_OUT_P1_Pos 1 /*!< PORT1 OUT: P1 Position */\r
-#define PORT1_OUT_P1_Msk (0x01UL << PORT1_OUT_P1_Pos) /*!< PORT1 OUT: P1 Mask */\r
-#define PORT1_OUT_P2_Pos 2 /*!< PORT1 OUT: P2 Position */\r
-#define PORT1_OUT_P2_Msk (0x01UL << PORT1_OUT_P2_Pos) /*!< PORT1 OUT: P2 Mask */\r
-#define PORT1_OUT_P3_Pos 3 /*!< PORT1 OUT: P3 Position */\r
-#define PORT1_OUT_P3_Msk (0x01UL << PORT1_OUT_P3_Pos) /*!< PORT1 OUT: P3 Mask */\r
-#define PORT1_OUT_P4_Pos 4 /*!< PORT1 OUT: P4 Position */\r
-#define PORT1_OUT_P4_Msk (0x01UL << PORT1_OUT_P4_Pos) /*!< PORT1 OUT: P4 Mask */\r
-#define PORT1_OUT_P5_Pos 5 /*!< PORT1 OUT: P5 Position */\r
-#define PORT1_OUT_P5_Msk (0x01UL << PORT1_OUT_P5_Pos) /*!< PORT1 OUT: P5 Mask */\r
-\r
-/* ---------------------------------- PORT1_OMR --------------------------------- */\r
-#define PORT1_OMR_PS0_Pos 0 /*!< PORT1 OMR: PS0 Position */\r
-#define PORT1_OMR_PS0_Msk (0x01UL << PORT1_OMR_PS0_Pos) /*!< PORT1 OMR: PS0 Mask */\r
-#define PORT1_OMR_PS1_Pos 1 /*!< PORT1 OMR: PS1 Position */\r
-#define PORT1_OMR_PS1_Msk (0x01UL << PORT1_OMR_PS1_Pos) /*!< PORT1 OMR: PS1 Mask */\r
-#define PORT1_OMR_PS2_Pos 2 /*!< PORT1 OMR: PS2 Position */\r
-#define PORT1_OMR_PS2_Msk (0x01UL << PORT1_OMR_PS2_Pos) /*!< PORT1 OMR: PS2 Mask */\r
-#define PORT1_OMR_PS3_Pos 3 /*!< PORT1 OMR: PS3 Position */\r
-#define PORT1_OMR_PS3_Msk (0x01UL << PORT1_OMR_PS3_Pos) /*!< PORT1 OMR: PS3 Mask */\r
-#define PORT1_OMR_PS4_Pos 4 /*!< PORT1 OMR: PS4 Position */\r
-#define PORT1_OMR_PS4_Msk (0x01UL << PORT1_OMR_PS4_Pos) /*!< PORT1 OMR: PS4 Mask */\r
-#define PORT1_OMR_PS5_Pos 5 /*!< PORT1 OMR: PS5 Position */\r
-#define PORT1_OMR_PS5_Msk (0x01UL << PORT1_OMR_PS5_Pos) /*!< PORT1 OMR: PS5 Mask */\r
-#define PORT1_OMR_PR0_Pos 16 /*!< PORT1 OMR: PR0 Position */\r
-#define PORT1_OMR_PR0_Msk (0x01UL << PORT1_OMR_PR0_Pos) /*!< PORT1 OMR: PR0 Mask */\r
-#define PORT1_OMR_PR1_Pos 17 /*!< PORT1 OMR: PR1 Position */\r
-#define PORT1_OMR_PR1_Msk (0x01UL << PORT1_OMR_PR1_Pos) /*!< PORT1 OMR: PR1 Mask */\r
-#define PORT1_OMR_PR2_Pos 18 /*!< PORT1 OMR: PR2 Position */\r
-#define PORT1_OMR_PR2_Msk (0x01UL << PORT1_OMR_PR2_Pos) /*!< PORT1 OMR: PR2 Mask */\r
-#define PORT1_OMR_PR3_Pos 19 /*!< PORT1 OMR: PR3 Position */\r
-#define PORT1_OMR_PR3_Msk (0x01UL << PORT1_OMR_PR3_Pos) /*!< PORT1 OMR: PR3 Mask */\r
-#define PORT1_OMR_PR4_Pos 20 /*!< PORT1 OMR: PR4 Position */\r
-#define PORT1_OMR_PR4_Msk (0x01UL << PORT1_OMR_PR4_Pos) /*!< PORT1 OMR: PR4 Mask */\r
-#define PORT1_OMR_PR5_Pos 21 /*!< PORT1 OMR: PR5 Position */\r
-#define PORT1_OMR_PR5_Msk (0x01UL << PORT1_OMR_PR5_Pos) /*!< PORT1 OMR: PR5 Mask */\r
-\r
-/* --------------------------------- PORT1_IOCR0 -------------------------------- */\r
-#define PORT1_IOCR0_PC0_Pos 3 /*!< PORT1 IOCR0: PC0 Position */\r
-#define PORT1_IOCR0_PC0_Msk (0x1fUL << PORT1_IOCR0_PC0_Pos) /*!< PORT1 IOCR0: PC0 Mask */\r
-#define PORT1_IOCR0_PC1_Pos 11 /*!< PORT1 IOCR0: PC1 Position */\r
-#define PORT1_IOCR0_PC1_Msk (0x1fUL << PORT1_IOCR0_PC1_Pos) /*!< PORT1 IOCR0: PC1 Mask */\r
-#define PORT1_IOCR0_PC2_Pos 19 /*!< PORT1 IOCR0: PC2 Position */\r
-#define PORT1_IOCR0_PC2_Msk (0x1fUL << PORT1_IOCR0_PC2_Pos) /*!< PORT1 IOCR0: PC2 Mask */\r
-#define PORT1_IOCR0_PC3_Pos 27 /*!< PORT1 IOCR0: PC3 Position */\r
-#define PORT1_IOCR0_PC3_Msk (0x1fUL << PORT1_IOCR0_PC3_Pos) /*!< PORT1 IOCR0: PC3 Mask */\r
-\r
-/* --------------------------------- PORT1_IOCR4 -------------------------------- */\r
-#define PORT1_IOCR4_PC4_Pos 3 /*!< PORT1 IOCR4: PC4 Position */\r
-#define PORT1_IOCR4_PC4_Msk (0x1fUL << PORT1_IOCR4_PC4_Pos) /*!< PORT1 IOCR4: PC4 Mask */\r
-#define PORT1_IOCR4_PC5_Pos 11 /*!< PORT1 IOCR4: PC5 Position */\r
-#define PORT1_IOCR4_PC5_Msk (0x1fUL << PORT1_IOCR4_PC5_Pos) /*!< PORT1 IOCR4: PC5 Mask */\r
-\r
-/* ---------------------------------- PORT1_IN ---------------------------------- */\r
-#define PORT1_IN_P0_Pos 0 /*!< PORT1 IN: P0 Position */\r
-#define PORT1_IN_P0_Msk (0x01UL << PORT1_IN_P0_Pos) /*!< PORT1 IN: P0 Mask */\r
-#define PORT1_IN_P1_Pos 1 /*!< PORT1 IN: P1 Position */\r
-#define PORT1_IN_P1_Msk (0x01UL << PORT1_IN_P1_Pos) /*!< PORT1 IN: P1 Mask */\r
-#define PORT1_IN_P2_Pos 2 /*!< PORT1 IN: P2 Position */\r
-#define PORT1_IN_P2_Msk (0x01UL << PORT1_IN_P2_Pos) /*!< PORT1 IN: P2 Mask */\r
-#define PORT1_IN_P3_Pos 3 /*!< PORT1 IN: P3 Position */\r
-#define PORT1_IN_P3_Msk (0x01UL << PORT1_IN_P3_Pos) /*!< PORT1 IN: P3 Mask */\r
-#define PORT1_IN_P4_Pos 4 /*!< PORT1 IN: P4 Position */\r
-#define PORT1_IN_P4_Msk (0x01UL << PORT1_IN_P4_Pos) /*!< PORT1 IN: P4 Mask */\r
-#define PORT1_IN_P5_Pos 5 /*!< PORT1 IN: P5 Position */\r
-#define PORT1_IN_P5_Msk (0x01UL << PORT1_IN_P5_Pos) /*!< PORT1 IN: P5 Mask */\r
-\r
-/* --------------------------------- PORT1_PHCR0 -------------------------------- */\r
-#define PORT1_PHCR0_PH0_Pos 2 /*!< PORT1 PHCR0: PH0 Position */\r
-#define PORT1_PHCR0_PH0_Msk (0x01UL << PORT1_PHCR0_PH0_Pos) /*!< PORT1 PHCR0: PH0 Mask */\r
-#define PORT1_PHCR0_PH1_Pos 6 /*!< PORT1 PHCR0: PH1 Position */\r
-#define PORT1_PHCR0_PH1_Msk (0x01UL << PORT1_PHCR0_PH1_Pos) /*!< PORT1 PHCR0: PH1 Mask */\r
-#define PORT1_PHCR0_PH2_Pos 10 /*!< PORT1 PHCR0: PH2 Position */\r
-#define PORT1_PHCR0_PH2_Msk (0x01UL << PORT1_PHCR0_PH2_Pos) /*!< PORT1 PHCR0: PH2 Mask */\r
-#define PORT1_PHCR0_PH3_Pos 14 /*!< PORT1 PHCR0: PH3 Position */\r
-#define PORT1_PHCR0_PH3_Msk (0x01UL << PORT1_PHCR0_PH3_Pos) /*!< PORT1 PHCR0: PH3 Mask */\r
-#define PORT1_PHCR0_PH4_Pos 18 /*!< PORT1 PHCR0: PH4 Position */\r
-#define PORT1_PHCR0_PH4_Msk (0x01UL << PORT1_PHCR0_PH4_Pos) /*!< PORT1 PHCR0: PH4 Mask */\r
-#define PORT1_PHCR0_PH5_Pos 22 /*!< PORT1 PHCR0: PH5 Position */\r
-#define PORT1_PHCR0_PH5_Msk (0x01UL << PORT1_PHCR0_PH5_Pos) /*!< PORT1 PHCR0: PH5 Mask */\r
-\r
-/* --------------------------------- PORT1_PDISC -------------------------------- */\r
-#define PORT1_PDISC_PDIS0_Pos 0 /*!< PORT1 PDISC: PDIS0 Position */\r
-#define PORT1_PDISC_PDIS0_Msk (0x01UL << PORT1_PDISC_PDIS0_Pos) /*!< PORT1 PDISC: PDIS0 Mask */\r
-#define PORT1_PDISC_PDIS1_Pos 1 /*!< PORT1 PDISC: PDIS1 Position */\r
-#define PORT1_PDISC_PDIS1_Msk (0x01UL << PORT1_PDISC_PDIS1_Pos) /*!< PORT1 PDISC: PDIS1 Mask */\r
-#define PORT1_PDISC_PDIS2_Pos 2 /*!< PORT1 PDISC: PDIS2 Position */\r
-#define PORT1_PDISC_PDIS2_Msk (0x01UL << PORT1_PDISC_PDIS2_Pos) /*!< PORT1 PDISC: PDIS2 Mask */\r
-#define PORT1_PDISC_PDIS3_Pos 3 /*!< PORT1 PDISC: PDIS3 Position */\r
-#define PORT1_PDISC_PDIS3_Msk (0x01UL << PORT1_PDISC_PDIS3_Pos) /*!< PORT1 PDISC: PDIS3 Mask */\r
-#define PORT1_PDISC_PDIS4_Pos 4 /*!< PORT1 PDISC: PDIS4 Position */\r
-#define PORT1_PDISC_PDIS4_Msk (0x01UL << PORT1_PDISC_PDIS4_Pos) /*!< PORT1 PDISC: PDIS4 Mask */\r
-#define PORT1_PDISC_PDIS5_Pos 5 /*!< PORT1 PDISC: PDIS5 Position */\r
-#define PORT1_PDISC_PDIS5_Msk (0x01UL << PORT1_PDISC_PDIS5_Pos) /*!< PORT1 PDISC: PDIS5 Mask */\r
-\r
-/* ---------------------------------- PORT1_PPS --------------------------------- */\r
-#define PORT1_PPS_PPS0_Pos 0 /*!< PORT1 PPS: PPS0 Position */\r
-#define PORT1_PPS_PPS0_Msk (0x01UL << PORT1_PPS_PPS0_Pos) /*!< PORT1 PPS: PPS0 Mask */\r
-#define PORT1_PPS_PPS1_Pos 1 /*!< PORT1 PPS: PPS1 Position */\r
-#define PORT1_PPS_PPS1_Msk (0x01UL << PORT1_PPS_PPS1_Pos) /*!< PORT1 PPS: PPS1 Mask */\r
-#define PORT1_PPS_PPS2_Pos 2 /*!< PORT1 PPS: PPS2 Position */\r
-#define PORT1_PPS_PPS2_Msk (0x01UL << PORT1_PPS_PPS2_Pos) /*!< PORT1 PPS: PPS2 Mask */\r
-#define PORT1_PPS_PPS3_Pos 3 /*!< PORT1 PPS: PPS3 Position */\r
-#define PORT1_PPS_PPS3_Msk (0x01UL << PORT1_PPS_PPS3_Pos) /*!< PORT1 PPS: PPS3 Mask */\r
-#define PORT1_PPS_PPS4_Pos 4 /*!< PORT1 PPS: PPS4 Position */\r
-#define PORT1_PPS_PPS4_Msk (0x01UL << PORT1_PPS_PPS4_Pos) /*!< PORT1 PPS: PPS4 Mask */\r
-#define PORT1_PPS_PPS5_Pos 5 /*!< PORT1 PPS: PPS5 Position */\r
-#define PORT1_PPS_PPS5_Msk (0x01UL << PORT1_PPS_PPS5_Pos) /*!< PORT1 PPS: PPS5 Mask */\r
-\r
-/* --------------------------------- PORT1_HWSEL -------------------------------- */\r
-#define PORT1_HWSEL_HW0_Pos 0 /*!< PORT1 HWSEL: HW0 Position */\r
-#define PORT1_HWSEL_HW0_Msk (0x03UL << PORT1_HWSEL_HW0_Pos) /*!< PORT1 HWSEL: HW0 Mask */\r
-#define PORT1_HWSEL_HW1_Pos 2 /*!< PORT1 HWSEL: HW1 Position */\r
-#define PORT1_HWSEL_HW1_Msk (0x03UL << PORT1_HWSEL_HW1_Pos) /*!< PORT1 HWSEL: HW1 Mask */\r
-#define PORT1_HWSEL_HW2_Pos 4 /*!< PORT1 HWSEL: HW2 Position */\r
-#define PORT1_HWSEL_HW2_Msk (0x03UL << PORT1_HWSEL_HW2_Pos) /*!< PORT1 HWSEL: HW2 Mask */\r
-#define PORT1_HWSEL_HW3_Pos 6 /*!< PORT1 HWSEL: HW3 Position */\r
-#define PORT1_HWSEL_HW3_Msk (0x03UL << PORT1_HWSEL_HW3_Pos) /*!< PORT1 HWSEL: HW3 Mask */\r
-#define PORT1_HWSEL_HW4_Pos 8 /*!< PORT1 HWSEL: HW4 Position */\r
-#define PORT1_HWSEL_HW4_Msk (0x03UL << PORT1_HWSEL_HW4_Pos) /*!< PORT1 HWSEL: HW4 Mask */\r
-#define PORT1_HWSEL_HW5_Pos 10 /*!< PORT1 HWSEL: HW5 Position */\r
-#define PORT1_HWSEL_HW5_Msk (0x03UL << PORT1_HWSEL_HW5_Pos) /*!< PORT1 HWSEL: HW5 Mask */\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ struct 'PORT2' Position & Mask ================ */\r
-/* ================================================================================ */\r
-\r
-\r
-/* ---------------------------------- PORT2_OUT --------------------------------- */\r
-#define PORT2_OUT_P0_Pos 0 /*!< PORT2 OUT: P0 Position */\r
-#define PORT2_OUT_P0_Msk (0x01UL << PORT2_OUT_P0_Pos) /*!< PORT2 OUT: P0 Mask */\r
-#define PORT2_OUT_P1_Pos 1 /*!< PORT2 OUT: P1 Position */\r
-#define PORT2_OUT_P1_Msk (0x01UL << PORT2_OUT_P1_Pos) /*!< PORT2 OUT: P1 Mask */\r
-#define PORT2_OUT_P2_Pos 2 /*!< PORT2 OUT: P2 Position */\r
-#define PORT2_OUT_P2_Msk (0x01UL << PORT2_OUT_P2_Pos) /*!< PORT2 OUT: P2 Mask */\r
-#define PORT2_OUT_P3_Pos 3 /*!< PORT2 OUT: P3 Position */\r
-#define PORT2_OUT_P3_Msk (0x01UL << PORT2_OUT_P3_Pos) /*!< PORT2 OUT: P3 Mask */\r
-#define PORT2_OUT_P4_Pos 4 /*!< PORT2 OUT: P4 Position */\r
-#define PORT2_OUT_P4_Msk (0x01UL << PORT2_OUT_P4_Pos) /*!< PORT2 OUT: P4 Mask */\r
-#define PORT2_OUT_P5_Pos 5 /*!< PORT2 OUT: P5 Position */\r
-#define PORT2_OUT_P5_Msk (0x01UL << PORT2_OUT_P5_Pos) /*!< PORT2 OUT: P5 Mask */\r
-#define PORT2_OUT_P6_Pos 6 /*!< PORT2 OUT: P6 Position */\r
-#define PORT2_OUT_P6_Msk (0x01UL << PORT2_OUT_P6_Pos) /*!< PORT2 OUT: P6 Mask */\r
-#define PORT2_OUT_P7_Pos 7 /*!< PORT2 OUT: P7 Position */\r
-#define PORT2_OUT_P7_Msk (0x01UL << PORT2_OUT_P7_Pos) /*!< PORT2 OUT: P7 Mask */\r
-#define PORT2_OUT_P8_Pos 8 /*!< PORT2 OUT: P8 Position */\r
-#define PORT2_OUT_P8_Msk (0x01UL << PORT2_OUT_P8_Pos) /*!< PORT2 OUT: P8 Mask */\r
-#define PORT2_OUT_P9_Pos 9 /*!< PORT2 OUT: P9 Position */\r
-#define PORT2_OUT_P9_Msk (0x01UL << PORT2_OUT_P9_Pos) /*!< PORT2 OUT: P9 Mask */\r
-#define PORT2_OUT_P10_Pos 10 /*!< PORT2 OUT: P10 Position */\r
-#define PORT2_OUT_P10_Msk (0x01UL << PORT2_OUT_P10_Pos) /*!< PORT2 OUT: P10 Mask */\r
-#define PORT2_OUT_P11_Pos 11 /*!< PORT2 OUT: P11 Position */\r
-#define PORT2_OUT_P11_Msk (0x01UL << PORT2_OUT_P11_Pos) /*!< PORT2 OUT: P11 Mask */\r
-\r
-/* ---------------------------------- PORT2_OMR --------------------------------- */\r
-#define PORT2_OMR_PS0_Pos 0 /*!< PORT2 OMR: PS0 Position */\r
-#define PORT2_OMR_PS0_Msk (0x01UL << PORT2_OMR_PS0_Pos) /*!< PORT2 OMR: PS0 Mask */\r
-#define PORT2_OMR_PS1_Pos 1 /*!< PORT2 OMR: PS1 Position */\r
-#define PORT2_OMR_PS1_Msk (0x01UL << PORT2_OMR_PS1_Pos) /*!< PORT2 OMR: PS1 Mask */\r
-#define PORT2_OMR_PS2_Pos 2 /*!< PORT2 OMR: PS2 Position */\r
-#define PORT2_OMR_PS2_Msk (0x01UL << PORT2_OMR_PS2_Pos) /*!< PORT2 OMR: PS2 Mask */\r
-#define PORT2_OMR_PS3_Pos 3 /*!< PORT2 OMR: PS3 Position */\r
-#define PORT2_OMR_PS3_Msk (0x01UL << PORT2_OMR_PS3_Pos) /*!< PORT2 OMR: PS3 Mask */\r
-#define PORT2_OMR_PS4_Pos 4 /*!< PORT2 OMR: PS4 Position */\r
-#define PORT2_OMR_PS4_Msk (0x01UL << PORT2_OMR_PS4_Pos) /*!< PORT2 OMR: PS4 Mask */\r
-#define PORT2_OMR_PS5_Pos 5 /*!< PORT2 OMR: PS5 Position */\r
-#define PORT2_OMR_PS5_Msk (0x01UL << PORT2_OMR_PS5_Pos) /*!< PORT2 OMR: PS5 Mask */\r
-#define PORT2_OMR_PS6_Pos 6 /*!< PORT2 OMR: PS6 Position */\r
-#define PORT2_OMR_PS6_Msk (0x01UL << PORT2_OMR_PS6_Pos) /*!< PORT2 OMR: PS6 Mask */\r
-#define PORT2_OMR_PS7_Pos 7 /*!< PORT2 OMR: PS7 Position */\r
-#define PORT2_OMR_PS7_Msk (0x01UL << PORT2_OMR_PS7_Pos) /*!< PORT2 OMR: PS7 Mask */\r
-#define PORT2_OMR_PS8_Pos 8 /*!< PORT2 OMR: PS8 Position */\r
-#define PORT2_OMR_PS8_Msk (0x01UL << PORT2_OMR_PS8_Pos) /*!< PORT2 OMR: PS8 Mask */\r
-#define PORT2_OMR_PS9_Pos 9 /*!< PORT2 OMR: PS9 Position */\r
-#define PORT2_OMR_PS9_Msk (0x01UL << PORT2_OMR_PS9_Pos) /*!< PORT2 OMR: PS9 Mask */\r
-#define PORT2_OMR_PS10_Pos 10 /*!< PORT2 OMR: PS10 Position */\r
-#define PORT2_OMR_PS10_Msk (0x01UL << PORT2_OMR_PS10_Pos) /*!< PORT2 OMR: PS10 Mask */\r
-#define PORT2_OMR_PS11_Pos 11 /*!< PORT2 OMR: PS11 Position */\r
-#define PORT2_OMR_PS11_Msk (0x01UL << PORT2_OMR_PS11_Pos) /*!< PORT2 OMR: PS11 Mask */\r
-#define PORT2_OMR_PR0_Pos 16 /*!< PORT2 OMR: PR0 Position */\r
-#define PORT2_OMR_PR0_Msk (0x01UL << PORT2_OMR_PR0_Pos) /*!< PORT2 OMR: PR0 Mask */\r
-#define PORT2_OMR_PR1_Pos 17 /*!< PORT2 OMR: PR1 Position */\r
-#define PORT2_OMR_PR1_Msk (0x01UL << PORT2_OMR_PR1_Pos) /*!< PORT2 OMR: PR1 Mask */\r
-#define PORT2_OMR_PR2_Pos 18 /*!< PORT2 OMR: PR2 Position */\r
-#define PORT2_OMR_PR2_Msk (0x01UL << PORT2_OMR_PR2_Pos) /*!< PORT2 OMR: PR2 Mask */\r
-#define PORT2_OMR_PR3_Pos 19 /*!< PORT2 OMR: PR3 Position */\r
-#define PORT2_OMR_PR3_Msk (0x01UL << PORT2_OMR_PR3_Pos) /*!< PORT2 OMR: PR3 Mask */\r
-#define PORT2_OMR_PR4_Pos 20 /*!< PORT2 OMR: PR4 Position */\r
-#define PORT2_OMR_PR4_Msk (0x01UL << PORT2_OMR_PR4_Pos) /*!< PORT2 OMR: PR4 Mask */\r
-#define PORT2_OMR_PR5_Pos 21 /*!< PORT2 OMR: PR5 Position */\r
-#define PORT2_OMR_PR5_Msk (0x01UL << PORT2_OMR_PR5_Pos) /*!< PORT2 OMR: PR5 Mask */\r
-#define PORT2_OMR_PR6_Pos 22 /*!< PORT2 OMR: PR6 Position */\r
-#define PORT2_OMR_PR6_Msk (0x01UL << PORT2_OMR_PR6_Pos) /*!< PORT2 OMR: PR6 Mask */\r
-#define PORT2_OMR_PR7_Pos 23 /*!< PORT2 OMR: PR7 Position */\r
-#define PORT2_OMR_PR7_Msk (0x01UL << PORT2_OMR_PR7_Pos) /*!< PORT2 OMR: PR7 Mask */\r
-#define PORT2_OMR_PR8_Pos 24 /*!< PORT2 OMR: PR8 Position */\r
-#define PORT2_OMR_PR8_Msk (0x01UL << PORT2_OMR_PR8_Pos) /*!< PORT2 OMR: PR8 Mask */\r
-#define PORT2_OMR_PR9_Pos 25 /*!< PORT2 OMR: PR9 Position */\r
-#define PORT2_OMR_PR9_Msk (0x01UL << PORT2_OMR_PR9_Pos) /*!< PORT2 OMR: PR9 Mask */\r
-#define PORT2_OMR_PR10_Pos 26 /*!< PORT2 OMR: PR10 Position */\r
-#define PORT2_OMR_PR10_Msk (0x01UL << PORT2_OMR_PR10_Pos) /*!< PORT2 OMR: PR10 Mask */\r
-#define PORT2_OMR_PR11_Pos 27 /*!< PORT2 OMR: PR11 Position */\r
-#define PORT2_OMR_PR11_Msk (0x01UL << PORT2_OMR_PR11_Pos) /*!< PORT2 OMR: PR11 Mask */\r
-\r
-/* --------------------------------- PORT2_IOCR0 -------------------------------- */\r
-#define PORT2_IOCR0_PC0_Pos 3 /*!< PORT2 IOCR0: PC0 Position */\r
-#define PORT2_IOCR0_PC0_Msk (0x1fUL << PORT2_IOCR0_PC0_Pos) /*!< PORT2 IOCR0: PC0 Mask */\r
-#define PORT2_IOCR0_PC1_Pos 11 /*!< PORT2 IOCR0: PC1 Position */\r
-#define PORT2_IOCR0_PC1_Msk (0x1fUL << PORT2_IOCR0_PC1_Pos) /*!< PORT2 IOCR0: PC1 Mask */\r
-#define PORT2_IOCR0_PC2_Pos 19 /*!< PORT2 IOCR0: PC2 Position */\r
-#define PORT2_IOCR0_PC2_Msk (0x1fUL << PORT2_IOCR0_PC2_Pos) /*!< PORT2 IOCR0: PC2 Mask */\r
-#define PORT2_IOCR0_PC3_Pos 27 /*!< PORT2 IOCR0: PC3 Position */\r
-#define PORT2_IOCR0_PC3_Msk (0x1fUL << PORT2_IOCR0_PC3_Pos) /*!< PORT2 IOCR0: PC3 Mask */\r
-\r
-/* --------------------------------- PORT2_IOCR4 -------------------------------- */\r
-#define PORT2_IOCR4_PC4_Pos 3 /*!< PORT2 IOCR4: PC4 Position */\r
-#define PORT2_IOCR4_PC4_Msk (0x1fUL << PORT2_IOCR4_PC4_Pos) /*!< PORT2 IOCR4: PC4 Mask */\r
-#define PORT2_IOCR4_PC5_Pos 11 /*!< PORT2 IOCR4: PC5 Position */\r
-#define PORT2_IOCR4_PC5_Msk (0x1fUL << PORT2_IOCR4_PC5_Pos) /*!< PORT2 IOCR4: PC5 Mask */\r
-#define PORT2_IOCR4_PC6_Pos 19 /*!< PORT2 IOCR4: PC6 Position */\r
-#define PORT2_IOCR4_PC6_Msk (0x1fUL << PORT2_IOCR4_PC6_Pos) /*!< PORT2 IOCR4: PC6 Mask */\r
-#define PORT2_IOCR4_PC7_Pos 27 /*!< PORT2 IOCR4: PC7 Position */\r
-#define PORT2_IOCR4_PC7_Msk (0x1fUL << PORT2_IOCR4_PC7_Pos) /*!< PORT2 IOCR4: PC7 Mask */\r
-\r
-/* --------------------------------- PORT2_IOCR8 -------------------------------- */\r
-#define PORT2_IOCR8_PC8_Pos 3 /*!< PORT2 IOCR8: PC8 Position */\r
-#define PORT2_IOCR8_PC8_Msk (0x1fUL << PORT2_IOCR8_PC8_Pos) /*!< PORT2 IOCR8: PC8 Mask */\r
-#define PORT2_IOCR8_PC9_Pos 11 /*!< PORT2 IOCR8: PC9 Position */\r
-#define PORT2_IOCR8_PC9_Msk (0x1fUL << PORT2_IOCR8_PC9_Pos) /*!< PORT2 IOCR8: PC9 Mask */\r
-#define PORT2_IOCR8_PC10_Pos 19 /*!< PORT2 IOCR8: PC10 Position */\r
-#define PORT2_IOCR8_PC10_Msk (0x1fUL << PORT2_IOCR8_PC10_Pos) /*!< PORT2 IOCR8: PC10 Mask */\r
-#define PORT2_IOCR8_PC11_Pos 27 /*!< PORT2 IOCR8: PC11 Position */\r
-#define PORT2_IOCR8_PC11_Msk (0x1fUL << PORT2_IOCR8_PC11_Pos) /*!< PORT2 IOCR8: PC11 Mask */\r
-\r
-/* ---------------------------------- PORT2_IN ---------------------------------- */\r
-#define PORT2_IN_P0_Pos 0 /*!< PORT2 IN: P0 Position */\r
-#define PORT2_IN_P0_Msk (0x01UL << PORT2_IN_P0_Pos) /*!< PORT2 IN: P0 Mask */\r
-#define PORT2_IN_P1_Pos 1 /*!< PORT2 IN: P1 Position */\r
-#define PORT2_IN_P1_Msk (0x01UL << PORT2_IN_P1_Pos) /*!< PORT2 IN: P1 Mask */\r
-#define PORT2_IN_P2_Pos 2 /*!< PORT2 IN: P2 Position */\r
-#define PORT2_IN_P2_Msk (0x01UL << PORT2_IN_P2_Pos) /*!< PORT2 IN: P2 Mask */\r
-#define PORT2_IN_P3_Pos 3 /*!< PORT2 IN: P3 Position */\r
-#define PORT2_IN_P3_Msk (0x01UL << PORT2_IN_P3_Pos) /*!< PORT2 IN: P3 Mask */\r
-#define PORT2_IN_P4_Pos 4 /*!< PORT2 IN: P4 Position */\r
-#define PORT2_IN_P4_Msk (0x01UL << PORT2_IN_P4_Pos) /*!< PORT2 IN: P4 Mask */\r
-#define PORT2_IN_P5_Pos 5 /*!< PORT2 IN: P5 Position */\r
-#define PORT2_IN_P5_Msk (0x01UL << PORT2_IN_P5_Pos) /*!< PORT2 IN: P5 Mask */\r
-#define PORT2_IN_P6_Pos 6 /*!< PORT2 IN: P6 Position */\r
-#define PORT2_IN_P6_Msk (0x01UL << PORT2_IN_P6_Pos) /*!< PORT2 IN: P6 Mask */\r
-#define PORT2_IN_P7_Pos 7 /*!< PORT2 IN: P7 Position */\r
-#define PORT2_IN_P7_Msk (0x01UL << PORT2_IN_P7_Pos) /*!< PORT2 IN: P7 Mask */\r
-#define PORT2_IN_P8_Pos 8 /*!< PORT2 IN: P8 Position */\r
-#define PORT2_IN_P8_Msk (0x01UL << PORT2_IN_P8_Pos) /*!< PORT2 IN: P8 Mask */\r
-#define PORT2_IN_P9_Pos 9 /*!< PORT2 IN: P9 Position */\r
-#define PORT2_IN_P9_Msk (0x01UL << PORT2_IN_P9_Pos) /*!< PORT2 IN: P9 Mask */\r
-#define PORT2_IN_P10_Pos 10 /*!< PORT2 IN: P10 Position */\r
-#define PORT2_IN_P10_Msk (0x01UL << PORT2_IN_P10_Pos) /*!< PORT2 IN: P10 Mask */\r
-#define PORT2_IN_P11_Pos 11 /*!< PORT2 IN: P11 Position */\r
-#define PORT2_IN_P11_Msk (0x01UL << PORT2_IN_P11_Pos) /*!< PORT2 IN: P11 Mask */\r
-\r
-/* --------------------------------- PORT2_PHCR0 -------------------------------- */\r
-#define PORT2_PHCR0_PH0_Pos 2 /*!< PORT2 PHCR0: PH0 Position */\r
-#define PORT2_PHCR0_PH0_Msk (0x01UL << PORT2_PHCR0_PH0_Pos) /*!< PORT2 PHCR0: PH0 Mask */\r
-#define PORT2_PHCR0_PH1_Pos 6 /*!< PORT2 PHCR0: PH1 Position */\r
-#define PORT2_PHCR0_PH1_Msk (0x01UL << PORT2_PHCR0_PH1_Pos) /*!< PORT2 PHCR0: PH1 Mask */\r
-#define PORT2_PHCR0_PH2_Pos 10 /*!< PORT2 PHCR0: PH2 Position */\r
-#define PORT2_PHCR0_PH2_Msk (0x01UL << PORT2_PHCR0_PH2_Pos) /*!< PORT2 PHCR0: PH2 Mask */\r
-#define PORT2_PHCR0_PH3_Pos 14 /*!< PORT2 PHCR0: PH3 Position */\r
-#define PORT2_PHCR0_PH3_Msk (0x01UL << PORT2_PHCR0_PH3_Pos) /*!< PORT2 PHCR0: PH3 Mask */\r
-#define PORT2_PHCR0_PH4_Pos 18 /*!< PORT2 PHCR0: PH4 Position */\r
-#define PORT2_PHCR0_PH4_Msk (0x01UL << PORT2_PHCR0_PH4_Pos) /*!< PORT2 PHCR0: PH4 Mask */\r
-#define PORT2_PHCR0_PH5_Pos 22 /*!< PORT2 PHCR0: PH5 Position */\r
-#define PORT2_PHCR0_PH5_Msk (0x01UL << PORT2_PHCR0_PH5_Pos) /*!< PORT2 PHCR0: PH5 Mask */\r
-#define PORT2_PHCR0_PH6_Pos 26 /*!< PORT2 PHCR0: PH6 Position */\r
-#define PORT2_PHCR0_PH6_Msk (0x01UL << PORT2_PHCR0_PH6_Pos) /*!< PORT2 PHCR0: PH6 Mask */\r
-#define PORT2_PHCR0_PH7_Pos 30 /*!< PORT2 PHCR0: PH7 Position */\r
-#define PORT2_PHCR0_PH7_Msk (0x01UL << PORT2_PHCR0_PH7_Pos) /*!< PORT2 PHCR0: PH7 Mask */\r
-\r
-/* --------------------------------- PORT2_PHCR1 -------------------------------- */\r
-#define PORT2_PHCR1_PH8_Pos 2 /*!< PORT2 PHCR1: PH8 Position */\r
-#define PORT2_PHCR1_PH8_Msk (0x01UL << PORT2_PHCR1_PH8_Pos) /*!< PORT2 PHCR1: PH8 Mask */\r
-#define PORT2_PHCR1_PH9_Pos 6 /*!< PORT2 PHCR1: PH9 Position */\r
-#define PORT2_PHCR1_PH9_Msk (0x01UL << PORT2_PHCR1_PH9_Pos) /*!< PORT2 PHCR1: PH9 Mask */\r
-#define PORT2_PHCR1_PH10_Pos 10 /*!< PORT2 PHCR1: PH10 Position */\r
-#define PORT2_PHCR1_PH10_Msk (0x01UL << PORT2_PHCR1_PH10_Pos) /*!< PORT2 PHCR1: PH10 Mask */\r
-#define PORT2_PHCR1_PH11_Pos 14 /*!< PORT2 PHCR1: PH11 Position */\r
-#define PORT2_PHCR1_PH11_Msk (0x01UL << PORT2_PHCR1_PH11_Pos) /*!< PORT2 PHCR1: PH11 Mask */\r
-\r
-/* --------------------------------- PORT2_PDISC -------------------------------- */\r
-#define PORT2_PDISC_PDIS0_Pos 0 /*!< PORT2 PDISC: PDIS0 Position */\r
-#define PORT2_PDISC_PDIS0_Msk (0x01UL << PORT2_PDISC_PDIS0_Pos) /*!< PORT2 PDISC: PDIS0 Mask */\r
-#define PORT2_PDISC_PDIS1_Pos 1 /*!< PORT2 PDISC: PDIS1 Position */\r
-#define PORT2_PDISC_PDIS1_Msk (0x01UL << PORT2_PDISC_PDIS1_Pos) /*!< PORT2 PDISC: PDIS1 Mask */\r
-#define PORT2_PDISC_PDIS2_Pos 2 /*!< PORT2 PDISC: PDIS2 Position */\r
-#define PORT2_PDISC_PDIS2_Msk (0x01UL << PORT2_PDISC_PDIS2_Pos) /*!< PORT2 PDISC: PDIS2 Mask */\r
-#define PORT2_PDISC_PDIS3_Pos 3 /*!< PORT2 PDISC: PDIS3 Position */\r
-#define PORT2_PDISC_PDIS3_Msk (0x01UL << PORT2_PDISC_PDIS3_Pos) /*!< PORT2 PDISC: PDIS3 Mask */\r
-#define PORT2_PDISC_PDIS4_Pos 4 /*!< PORT2 PDISC: PDIS4 Position */\r
-#define PORT2_PDISC_PDIS4_Msk (0x01UL << PORT2_PDISC_PDIS4_Pos) /*!< PORT2 PDISC: PDIS4 Mask */\r
-#define PORT2_PDISC_PDIS5_Pos 5 /*!< PORT2 PDISC: PDIS5 Position */\r
-#define PORT2_PDISC_PDIS5_Msk (0x01UL << PORT2_PDISC_PDIS5_Pos) /*!< PORT2 PDISC: PDIS5 Mask */\r
-#define PORT2_PDISC_PDIS6_Pos 6 /*!< PORT2 PDISC: PDIS6 Position */\r
-#define PORT2_PDISC_PDIS6_Msk (0x01UL << PORT2_PDISC_PDIS6_Pos) /*!< PORT2 PDISC: PDIS6 Mask */\r
-#define PORT2_PDISC_PDIS7_Pos 7 /*!< PORT2 PDISC: PDIS7 Position */\r
-#define PORT2_PDISC_PDIS7_Msk (0x01UL << PORT2_PDISC_PDIS7_Pos) /*!< PORT2 PDISC: PDIS7 Mask */\r
-#define PORT2_PDISC_PDIS8_Pos 8 /*!< PORT2 PDISC: PDIS8 Position */\r
-#define PORT2_PDISC_PDIS8_Msk (0x01UL << PORT2_PDISC_PDIS8_Pos) /*!< PORT2 PDISC: PDIS8 Mask */\r
-#define PORT2_PDISC_PDIS9_Pos 9 /*!< PORT2 PDISC: PDIS9 Position */\r
-#define PORT2_PDISC_PDIS9_Msk (0x01UL << PORT2_PDISC_PDIS9_Pos) /*!< PORT2 PDISC: PDIS9 Mask */\r
-#define PORT2_PDISC_PDIS10_Pos 10 /*!< PORT2 PDISC: PDIS10 Position */\r
-#define PORT2_PDISC_PDIS10_Msk (0x01UL << PORT2_PDISC_PDIS10_Pos) /*!< PORT2 PDISC: PDIS10 Mask */\r
-#define PORT2_PDISC_PDIS11_Pos 11 /*!< PORT2 PDISC: PDIS11 Position */\r
-#define PORT2_PDISC_PDIS11_Msk (0x01UL << PORT2_PDISC_PDIS11_Pos) /*!< PORT2 PDISC: PDIS11 Mask */\r
-\r
-/* ---------------------------------- PORT2_PPS --------------------------------- */\r
-#define PORT2_PPS_PPS0_Pos 0 /*!< PORT2 PPS: PPS0 Position */\r
-#define PORT2_PPS_PPS0_Msk (0x01UL << PORT2_PPS_PPS0_Pos) /*!< PORT2 PPS: PPS0 Mask */\r
-#define PORT2_PPS_PPS1_Pos 1 /*!< PORT2 PPS: PPS1 Position */\r
-#define PORT2_PPS_PPS1_Msk (0x01UL << PORT2_PPS_PPS1_Pos) /*!< PORT2 PPS: PPS1 Mask */\r
-#define PORT2_PPS_PPS2_Pos 2 /*!< PORT2 PPS: PPS2 Position */\r
-#define PORT2_PPS_PPS2_Msk (0x01UL << PORT2_PPS_PPS2_Pos) /*!< PORT2 PPS: PPS2 Mask */\r
-#define PORT2_PPS_PPS3_Pos 3 /*!< PORT2 PPS: PPS3 Position */\r
-#define PORT2_PPS_PPS3_Msk (0x01UL << PORT2_PPS_PPS3_Pos) /*!< PORT2 PPS: PPS3 Mask */\r
-#define PORT2_PPS_PPS4_Pos 4 /*!< PORT2 PPS: PPS4 Position */\r
-#define PORT2_PPS_PPS4_Msk (0x01UL << PORT2_PPS_PPS4_Pos) /*!< PORT2 PPS: PPS4 Mask */\r
-#define PORT2_PPS_PPS5_Pos 5 /*!< PORT2 PPS: PPS5 Position */\r
-#define PORT2_PPS_PPS5_Msk (0x01UL << PORT2_PPS_PPS5_Pos) /*!< PORT2 PPS: PPS5 Mask */\r
-#define PORT2_PPS_PPS6_Pos 6 /*!< PORT2 PPS: PPS6 Position */\r
-#define PORT2_PPS_PPS6_Msk (0x01UL << PORT2_PPS_PPS6_Pos) /*!< PORT2 PPS: PPS6 Mask */\r
-#define PORT2_PPS_PPS7_Pos 7 /*!< PORT2 PPS: PPS7 Position */\r
-#define PORT2_PPS_PPS7_Msk (0x01UL << PORT2_PPS_PPS7_Pos) /*!< PORT2 PPS: PPS7 Mask */\r
-#define PORT2_PPS_PPS8_Pos 8 /*!< PORT2 PPS: PPS8 Position */\r
-#define PORT2_PPS_PPS8_Msk (0x01UL << PORT2_PPS_PPS8_Pos) /*!< PORT2 PPS: PPS8 Mask */\r
-#define PORT2_PPS_PPS9_Pos 9 /*!< PORT2 PPS: PPS9 Position */\r
-#define PORT2_PPS_PPS9_Msk (0x01UL << PORT2_PPS_PPS9_Pos) /*!< PORT2 PPS: PPS9 Mask */\r
-#define PORT2_PPS_PPS10_Pos 10 /*!< PORT2 PPS: PPS10 Position */\r
-#define PORT2_PPS_PPS10_Msk (0x01UL << PORT2_PPS_PPS10_Pos) /*!< PORT2 PPS: PPS10 Mask */\r
-#define PORT2_PPS_PPS11_Pos 11 /*!< PORT2 PPS: PPS11 Position */\r
-#define PORT2_PPS_PPS11_Msk (0x01UL << PORT2_PPS_PPS11_Pos) /*!< PORT2 PPS: PPS11 Mask */\r
-\r
-/* --------------------------------- PORT2_HWSEL -------------------------------- */\r
-#define PORT2_HWSEL_HW0_Pos 0 /*!< PORT2 HWSEL: HW0 Position */\r
-#define PORT2_HWSEL_HW0_Msk (0x03UL << PORT2_HWSEL_HW0_Pos) /*!< PORT2 HWSEL: HW0 Mask */\r
-#define PORT2_HWSEL_HW1_Pos 2 /*!< PORT2 HWSEL: HW1 Position */\r
-#define PORT2_HWSEL_HW1_Msk (0x03UL << PORT2_HWSEL_HW1_Pos) /*!< PORT2 HWSEL: HW1 Mask */\r
-#define PORT2_HWSEL_HW2_Pos 4 /*!< PORT2 HWSEL: HW2 Position */\r
-#define PORT2_HWSEL_HW2_Msk (0x03UL << PORT2_HWSEL_HW2_Pos) /*!< PORT2 HWSEL: HW2 Mask */\r
-#define PORT2_HWSEL_HW3_Pos 6 /*!< PORT2 HWSEL: HW3 Position */\r
-#define PORT2_HWSEL_HW3_Msk (0x03UL << PORT2_HWSEL_HW3_Pos) /*!< PORT2 HWSEL: HW3 Mask */\r
-#define PORT2_HWSEL_HW4_Pos 8 /*!< PORT2 HWSEL: HW4 Position */\r
-#define PORT2_HWSEL_HW4_Msk (0x03UL << PORT2_HWSEL_HW4_Pos) /*!< PORT2 HWSEL: HW4 Mask */\r
-#define PORT2_HWSEL_HW5_Pos 10 /*!< PORT2 HWSEL: HW5 Position */\r
-#define PORT2_HWSEL_HW5_Msk (0x03UL << PORT2_HWSEL_HW5_Pos) /*!< PORT2 HWSEL: HW5 Mask */\r
-#define PORT2_HWSEL_HW6_Pos 12 /*!< PORT2 HWSEL: HW6 Position */\r
-#define PORT2_HWSEL_HW6_Msk (0x03UL << PORT2_HWSEL_HW6_Pos) /*!< PORT2 HWSEL: HW6 Mask */\r
-#define PORT2_HWSEL_HW7_Pos 14 /*!< PORT2 HWSEL: HW7 Position */\r
-#define PORT2_HWSEL_HW7_Msk (0x03UL << PORT2_HWSEL_HW7_Pos) /*!< PORT2 HWSEL: HW7 Mask */\r
-#define PORT2_HWSEL_HW8_Pos 16 /*!< PORT2 HWSEL: HW8 Position */\r
-#define PORT2_HWSEL_HW8_Msk (0x03UL << PORT2_HWSEL_HW8_Pos) /*!< PORT2 HWSEL: HW8 Mask */\r
-#define PORT2_HWSEL_HW9_Pos 18 /*!< PORT2 HWSEL: HW9 Position */\r
-#define PORT2_HWSEL_HW9_Msk (0x03UL << PORT2_HWSEL_HW9_Pos) /*!< PORT2 HWSEL: HW9 Mask */\r
-#define PORT2_HWSEL_HW10_Pos 20 /*!< PORT2 HWSEL: HW10 Position */\r
-#define PORT2_HWSEL_HW10_Msk (0x03UL << PORT2_HWSEL_HW10_Pos) /*!< PORT2 HWSEL: HW10 Mask */\r
-#define PORT2_HWSEL_HW11_Pos 22 /*!< PORT2 HWSEL: HW11 Position */\r
-#define PORT2_HWSEL_HW11_Msk (0x03UL << PORT2_HWSEL_HW11_Pos) /*!< PORT2 HWSEL: HW11 Mask */\r
-\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Peripheral memory map ================ */\r
-/* ================================================================================ */\r
-\r
-#define PPB_BASE 0xE000E000UL\r
-#define ERU0_BASE 0x40010600UL\r
-#define PAU_BASE 0x40000000UL\r
-#define NVM_BASE 0x40050000UL\r
-#define WDT_BASE 0x40020000UL\r
-#define RTC_BASE 0x40010A00UL\r
-#define PRNG_BASE 0x48020000UL\r
-#define LEDTS0_BASE 0x50020000UL\r
-#define LEDTS1_BASE 0x50020400UL\r
-#define USIC0_BASE 0x48000008UL\r
-#define USIC0_CH0_BASE 0x48000000UL\r
-#define USIC0_CH1_BASE 0x48000200UL\r
-#define SCU_GENERAL_BASE 0x40010000UL\r
-#define SCU_INTERRUPT_BASE 0x40010038UL\r
-#define SCU_POWER_BASE 0x40010200UL\r
-#define SCU_CLK_BASE 0x40010300UL\r
-#define SCU_RESET_BASE 0x40010400UL\r
-#define COMPARATOR_BASE 0x40010500UL\r
-#define SCU_ANALOG_BASE 0x40011000UL\r
-#define CCU40_BASE 0x48040000UL\r
-#define CCU40_CC40_BASE 0x48040100UL\r
-#define CCU40_CC41_BASE 0x48040200UL\r
-#define CCU40_CC42_BASE 0x48040300UL\r
-#define CCU40_CC43_BASE 0x48040400UL\r
-#define VADC_BASE 0x48030000UL\r
-#define VADC_G0_BASE 0x48030400UL\r
-#define VADC_G1_BASE 0x48030800UL\r
-#define SHS0_BASE 0x48034000UL\r
-#define BCCU0_BASE 0x50030000UL\r
-#define BCCU0_CH0_BASE 0x5003003CUL\r
-#define BCCU0_CH1_BASE 0x50030050UL\r
-#define BCCU0_CH2_BASE 0x50030064UL\r
-#define BCCU0_CH3_BASE 0x50030078UL\r
-#define BCCU0_CH4_BASE 0x5003008CUL\r
-#define BCCU0_CH5_BASE 0x500300A0UL\r
-#define BCCU0_CH6_BASE 0x500300B4UL\r
-#define BCCU0_CH7_BASE 0x500300C8UL\r
-#define BCCU0_CH8_BASE 0x500300DCUL\r
-#define BCCU0_DE0_BASE 0x5003017CUL\r
-#define BCCU0_DE1_BASE 0x50030188UL\r
-#define BCCU0_DE2_BASE 0x50030194UL\r
-#define PORT0_BASE 0x40040000UL\r
-#define PORT1_BASE 0x40040100UL\r
-#define PORT2_BASE 0x40040200UL\r
-\r
-\r
-/* ================================================================================ */\r
-/* ================ Peripheral declaration ================ */\r
-/* ================================================================================ */\r
-\r
-#define PPB ((PPB_Type *) PPB_BASE)\r
-#define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE)\r
-#define PAU ((PAU_Type *) PAU_BASE)\r
-#define NVM ((NVM_Type *) NVM_BASE)\r
-#define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE)\r
-#define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE)\r
-#define PRNG ((PRNG_Type *) PRNG_BASE)\r
-#define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE)\r
-#define LEDTS1 ((LEDTS0_GLOBAL_TypeDef *) LEDTS1_BASE)\r
-#define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE)\r
-#define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE)\r
-#define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE)\r
-#define SCU_GENERAL ((SCU_GENERAL_Type *) SCU_GENERAL_BASE)\r
-#define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE)\r
-#define SCU_POWER ((SCU_POWER_Type *) SCU_POWER_BASE)\r
-#define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE)\r
-#define SCU_RESET ((SCU_RESET_Type *) SCU_RESET_BASE)\r
-#define COMPARATOR ((COMPARATOR_Type *) COMPARATOR_BASE)\r
-#define SCU_ANALOG ((SCU_ANALOG_Type *) SCU_ANALOG_BASE)\r
-#define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE)\r
-#define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE)\r
-#define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE)\r
-#define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE)\r
-#define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE)\r
-#define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE)\r
-#define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE)\r
-#define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE)\r
-#define SHS0 ((SHS_Type *) SHS0_BASE)\r
-#define BCCU0 ((BCCU_Type *) BCCU0_BASE)\r
-#define BCCU0_CH0 ((BCCU_CH_Type *) BCCU0_CH0_BASE)\r
-#define BCCU0_CH1 ((BCCU_CH_Type *) BCCU0_CH1_BASE)\r
-#define BCCU0_CH2 ((BCCU_CH_Type *) BCCU0_CH2_BASE)\r
-#define BCCU0_CH3 ((BCCU_CH_Type *) BCCU0_CH3_BASE)\r
-#define BCCU0_CH4 ((BCCU_CH_Type *) BCCU0_CH4_BASE)\r
-#define BCCU0_CH5 ((BCCU_CH_Type *) BCCU0_CH5_BASE)\r
-#define BCCU0_CH6 ((BCCU_CH_Type *) BCCU0_CH6_BASE)\r
-#define BCCU0_CH7 ((BCCU_CH_Type *) BCCU0_CH7_BASE)\r
-#define BCCU0_CH8 ((BCCU_CH_Type *) BCCU0_CH8_BASE)\r
-#define BCCU0_DE0 ((BCCU_DE_Type *) BCCU0_DE0_BASE)\r
-#define BCCU0_DE1 ((BCCU_DE_Type *) BCCU0_DE1_BASE)\r
-#define BCCU0_DE2 ((BCCU_DE_Type *) BCCU0_DE2_BASE)\r
-#define PORT0 ((PORT0_Type *) PORT0_BASE)\r
-#define PORT1 ((PORT1_Type *) PORT1_BASE)\r
-#define PORT2 ((PORT2_Type *) PORT2_BASE)\r
-\r
-\r
-/** @} */ /* End of group Device_Peripheral_Registers */\r
-/** @} */ /* End of group XMC1200 */\r
-/** @} */ /* End of group Infineon */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-\r
-#endif /* XMC1200_H */\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky style\r
- * project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
- * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
- * in main.c. This file implements the simply blinky style version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware, are defined in main.c.\r
- ******************************************************************************\r
- *\r
- * main_blinky() creates one queue, and two tasks. It then starts the\r
- * scheduler.\r
- *\r
- * The Queue Send Task:\r
- * The queue send task is implemented by the prvQueueSendTask() function in\r
- * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
- * block for 200 milliseconds, before sending the value 100 to the queue that\r
- * was created within main_blinky(). Once the value is sent, the task loops\r
- * back around to block for another 200 milliseconds.\r
- *\r
- * The Queue Receive Task:\r
- * The queue receive task is implemented by the prvQueueReceiveTask() function\r
- * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
- * blocks on attempts to read data from the queue that was created within\r
- * main_blinky(). When data is received, the task checks the value of the\r
- * data, and if the value equals the expected 100, toggles LED 1. The 'block\r
- * time' parameter passed to the queue receive function specifies that the\r
- * task should be held in the Blocked state indefinitely to wait for data to\r
- * be available on the queue. The queue receive task will only leave the\r
- * Blocked state when the queue send task writes to the queue. As the queue\r
- * send task writes to the queue every 200 milliseconds, the queue receive\r
- * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
- * the LED every 200 milliseconds.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "queue.h"\r
-\r
-/* Demo includes. */\r
-#include "ParTest.h"\r
-\r
-/* Priorities at which the tasks are created. */\r
-#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
-#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
-\r
-/* The rate at which data is sent to the queue. The 200ms value is converted\r
-to ticks using the portTICK_RATE_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
-\r
-/* The number of items the queue can hold. This is 1 as the receive task\r
-will remove items as they are added, meaning the send task should always find\r
-the queue empty. */\r
-#define mainQUEUE_LENGTH ( 1 )\r
-\r
-/* Values passed to the two tasks just to check the task parameter\r
-functionality. */\r
-#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
-#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
-\r
-/* The number of the LED that is toggled. */\r
-#define mainLED_TO_TOGGLE ( 0 )\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * The tasks as described in the comments at the top of this file.\r
- */\r
-static void prvQueueReceiveTask( void *pvParameters );\r
-static void prvQueueSendTask( void *pvParameters );\r
-\r
-/*\r
- * Called by main() to create the simply blinky style application if\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
- */\r
-void main_blinky( void );\r
-\r
-/*\r
- * The hardware only has a single LED. Simply toggle it.\r
- */\r
-extern void vMainToggleLED( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The queue used by both tasks. */\r
-static xQueueHandle xQueue = NULL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_blinky( void )\r
-{\r
- /* Create the queue. */\r
- xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
-\r
- if( xQueue != NULL )\r
- {\r
- /* Start the two tasks as described in the comments at the top of this\r
- file. */\r
- xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
- ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
- configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
- ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
- mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
- NULL ); /* The task handle is not required, so NULL is passed. */\r
-\r
- xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
-\r
- /* Start the tasks and timer running. */\r
- vTaskStartScheduler();\r
- }\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then\r
- there was insufficient FreeRTOS heap memory available for the idle and/or\r
- timer tasks to be created. See the memory management section on the\r
- FreeRTOS web site for more details. */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueSendTask( void *pvParameters )\r
-{\r
-portTickType xNextWakeTime;\r
-const unsigned long ulValueToSend = 100UL;\r
-\r
- /* Check the task parameter is as expected. */\r
- configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
-\r
- /* Initialise xNextWakeTime - this only needs to be done once. */\r
- xNextWakeTime = xTaskGetTickCount();\r
-\r
- for( ;; )\r
- {\r
- /* Place this task in the blocked state until it is time to run again.\r
- The block time is specified in ticks, the constant used converts ticks\r
- to ms. While in the Blocked state this task will not consume any CPU\r
- time. */\r
- vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
-\r
- /* Send to the queue - causing the queue receive task to unblock and\r
- toggle the LED. 0 is used as the block time so the sending operation\r
- will not block - it shouldn't need to block as the queue should always\r
- be empty at this point in the code. */\r
- xQueueSend( xQueue, &ulValueToSend, 0U );\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvQueueReceiveTask( void *pvParameters )\r
-{\r
-unsigned long ulReceivedValue;\r
-\r
- /* Check the task parameter is as expected. */\r
- configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
-\r
- for( ;; )\r
- {\r
- /* Wait until something arrives in the queue - this task will block\r
- indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
- FreeRTOSConfig.h. */\r
- xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
-\r
- /* To get here something must have been received from the queue, but\r
- is it the expected value? If it is, toggle the LED. */\r
- if( ulReceivedValue == 100UL )\r
- {\r
- vParTestToggleLED( mainLED_TO_TOGGLE );\r
- ulReceivedValue = 0U;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * NOTE 1: This project provides two demo applications. A simple blinky style\r
- * project, and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
- * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
- * in main.c. This file implements the comprehensive test and demo version.\r
- *\r
- * NOTE 2: This file only contains the source code that is specific to the\r
- * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
- * required to configure the hardware, are defined in main.c.\r
- ******************************************************************************\r
- *\r
- * main_full() creates a set of standard demo tasks, some application specific\r
- * tasks, and four timers. It then starts the scheduler. The web documentation\r
- * provides more details of the standard demo application tasks, which provide\r
- * no particular functionality, but do provide a good example of how to use the\r
- * FreeRTOS API.\r
- *\r
- * In addition to the standard demo tasks, the following tasks and timer are\r
- * defined and/or created within this file:\r
- *\r
- * "Reg test" tasks - These fill the registers with known values, then check\r
- * that each register maintains its expected value for the lifetime of the\r
- * task. Each task uses a different set of values. The reg test tasks execute\r
- * with a very low priority, so get preempted very frequently. A register\r
- * containing an unexpected value is indicative of an error in the context\r
- * switching mechanism.\r
- *\r
- * "Flash timers" - A software timer callback function is defined that does\r
- * nothing but toggle an LED. Three software timers are created that each\r
- * use the same callback function, but each toggles a different LED at a\r
- * different frequency. One software timer uses LED1, another LED2 and the\r
- * third LED3.\r
- *\r
- * "Check" software timer - The check timer period is initially set to three\r
- * seconds. Its callback function checks that all the standard demo tasks, and\r
- * the register check tasks, are not only still executing, but are executing\r
- * without reporting any errors. If the check timer callback discovers that a\r
- * task has either stalled, or reported an error, then it changes the period of\r
- * the check timer from the initial three seconds, to just 200ms. The callback\r
- * function also toggles LED 4 each time it is called. This provides a visual\r
- * indication of the system status: If the LED toggles every three seconds,\r
- * then no issues have been discovered. If the LED toggles every 200ms, then\r
- * an issue has been discovered with at least one task.\r
- */\r
-\r
-/* Kernel includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-#include "queue.h"\r
-#include "timers.h"\r
-\r
-/* Common demo includes. */\r
-#include "blocktim.h"\r
-#include "countsem.h"\r
-#include "recmutex.h"\r
-#include "ParTest.h"\r
-#include "dynamic.h"\r
-\r
-/* The period after which the check timer will expire provided no errors have\r
-been reported by any of the standard demo tasks. ms are converted to the\r
-equivalent in ticks using the portTICK_RATE_MS constant. */\r
-#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
-\r
-/* The period at which the check timer will expire if an error has been\r
-reported in one of the standard demo tasks. ms are converted to the equivalent\r
-in ticks using the portTICK_RATE_MS constant. */\r
-#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
-\r
-/* A block time of zero simply means "don't block". */\r
-#define mainDONT_BLOCK ( 0UL )\r
-\r
-/* The base toggle rate used by the flash timers. Each toggle rate is a\r
-multiple of this. */\r
-#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_RATE_MS )\r
-\r
-/* The LED toggle by the check timer. */\r
-#define mainCHECK_LED ( 4 )\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Register check tasks, as described at the top of this file. The nature of\r
- * these files necessitates that they are written in an assembly.\r
- */\r
-extern void vRegTest1Task( void *pvParameters );\r
-extern void vRegTest2Task( void *pvParameters );\r
-\r
-/*\r
- * The hardware only has a single LED. Simply toggle it.\r
- */\r
-extern void vMainToggleLED( void );\r
-\r
-/*\r
- * The check timer callback function, as described at the top of this file.\r
- */\r
-static void prvCheckTimerCallback( xTimerHandle xTimer );\r
-\r
-/*\r
- * The flash timer callback function, as described at the top of this file.\r
- * This callback function is assigned to three separate software timers.\r
- */\r
-static void prvFlashTimerCallback( xTimerHandle xTimer );\r
-\r
-/*\r
- * Called by main() to create the comprehensive test/demo application if\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1.\r
- */\r
-void main_full( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/* The following two variables are used to communicate the status of the\r
-register check tasks to the check software timer. If the variables keep\r
-incrementing, then the register check tasks has not discovered any errors. If\r
-a variable stops incrementing, then an error has been found. */\r
-volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-void main_full( void )\r
-{\r
-xTimerHandle xTimer = NULL;\r
-unsigned long ulTimer;\r
-const unsigned long ulTimersToCreate = 3L;\r
-/* The register test tasks are asm functions that don't use a stack. The\r
-stack allocated just has to be large enough to hold the task context, and\r
-for the additional required for the stack overflow checking to work (if\r
-configured). */\r
-const size_t xRegTestStackSize = 25U;\r
-\r
- /* Create the standard demo tasks */\r
- vCreateBlockTimeTasks();\r
- vStartCountingSemaphoreTasks();\r
- vStartRecursiveMutexTasks();\r
- vStartDynamicPriorityTasks();\r
-\r
- /* Create the register test tasks as described at the top of this file.\r
- These are naked functions that don't use any stack. A stack still has\r
- to be allocated to hold the task context. */\r
- xTaskCreate( vRegTest1Task, /* Function that implements the task. */\r
- ( signed char * ) "Reg1", /* Text name of the task. */\r
- xRegTestStackSize, /* Stack allocated to the task. */\r
- NULL, /* The task parameter is not used. */\r
- tskIDLE_PRIORITY, /* The priority to assign to the task. */\r
- NULL ); /* Don't receive a handle back, it is not needed. */\r
-\r
- xTaskCreate( vRegTest2Task, /* Function that implements the task. */\r
- ( signed char * ) "Reg2", /* Text name of the task. */\r
- xRegTestStackSize, /* Stack allocated to the task. */\r
- NULL, /* The task parameter is not used. */\r
- tskIDLE_PRIORITY, /* The priority to assign to the task. */\r
- NULL ); /* Don't receive a handle back, it is not needed. */\r
-\r
- /* Create the three flash timers. */\r
- for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ )\r
- {\r
- xTimer = xTimerCreate( ( const signed char * ) "FlashTimer", /* A text name, purely to help debugging. */\r
- ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */\r
- pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
- ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */\r
- prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
- );\r
-\r
- if( xTimer != NULL )\r
- {\r
- xTimerStart( xTimer, mainDONT_BLOCK );\r
- }\r
- }\r
-\r
- /* Create the software timer that performs the 'check' functionality,\r
- as described at the top of this file. */\r
- xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
- ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
- pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
- ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
- prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
- );\r
-\r
- /* If the software timer was created successfully, start it. It won't\r
- actually start running until the scheduler starts. A block time of\r
- zero is used in this call, although any value could be used as the block\r
- time will be ignored because the scheduler has not started yet. */\r
- if( xTimer != NULL )\r
- {\r
- xTimerStart( xTimer, mainDONT_BLOCK );\r
- }\r
-\r
- /* Start the kernel. From here on, only tasks and interrupts will run. */\r
- vTaskStartScheduler();\r
-\r
- /* If all is well, the scheduler will now be running, and the following\r
- line will never be reached. If the following line does execute, then there\r
- was insufficient FreeRTOS heap memory available for the idle and/or timer\r
- tasks to be created. See the memory management section on the FreeRTOS web\r
- site, or the FreeRTOS tutorial books for more details. */\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-/* See the description at the top of this file. */\r
-static void prvCheckTimerCallback( xTimerHandle xTimer )\r
-{\r
-static long lChangedTimerPeriodAlready = pdFALSE;\r
-static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
-unsigned long ulErrorFound = pdFALSE;\r
-\r
- /* Check all the demo and test tasks to ensure that they are all still\r
- running, and that none have detected an error. */\r
- if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= ( 0x01UL << 0UL );\r
- }\r
-\r
- if( xAreBlockTimeTestTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= ( 0x01UL << 1UL );\r
- }\r
-\r
- if( xAreCountingSemaphoreTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= ( 0x01UL << 2UL );\r
- }\r
-\r
- if( xAreRecursiveMutexTasksStillRunning() != pdPASS )\r
- {\r
- ulErrorFound |= ( 0x01UL << 3UL );\r
- }\r
-\r
- /* Check that the register test 1 task is still running. */\r
- if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
- {\r
- ulErrorFound |= ( 0x01UL << 4UL );\r
- }\r
- ulLastRegTest1Value = ulRegTest1LoopCounter;\r
-\r
- /* Check that the register test 2 task is still running. */\r
- if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
- {\r
- ulErrorFound |= ( 0x01UL << 5UL );\r
- }\r
- ulLastRegTest2Value = ulRegTest2LoopCounter;\r
-\r
- /* Toggle the check LED to give an indication of the system status. If\r
- the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
- everything is ok. A faster toggle indicates an error. */\r
- vParTestToggleLED( mainCHECK_LED );\r
-\r
- /* Have any errors been latched in ulErrorFound? If so, shorten the\r
- period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
- This will result in an increase in the rate at which mainCHECK_LED\r
- toggles. */\r
- if( ulErrorFound != pdFALSE )\r
- {\r
- if( lChangedTimerPeriodAlready == pdFALSE )\r
- {\r
- lChangedTimerPeriodAlready = pdTRUE;\r
-\r
- /* This call to xTimerChangePeriod() uses a zero block time.\r
- Functions called from inside of a timer callback function must\r
- *never* attempt to block. */\r
- xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvFlashTimerCallback( xTimerHandle xTimer )\r
-{\r
-unsigned long ulLED;\r
-\r
- /* This callback function is assigned to three separate software timers.\r
- Each timer toggles a different LED. Obtain the number of the LED that\r
- this timer is toggling. */\r
- ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer );\r
-\r
- /* Toggle the LED. */\r
- vParTestToggleLED( ulLED );\r
-}\r
-\r
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
-/******************************************************************************\r
- * This project provides two demo applications. A simple blinky style project,\r
- * and a more comprehensive test and demo application. The\r
- * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
- * select between the two. The simply blinky demo is implemented and described\r
- * in main_blinky.c. The more comprehensive test and demo application is\r
- * implemented and described in main_full.c.\r
- *\r
- * This file implements the code that is not demo specific, including the\r
- * hardware setup and FreeRTOS hook functions. It also contains a dummy\r
- * interrupt service routine called Dummy_IRQHandler() that is provided as an\r
- * example of how to use interrupt safe FreeRTOS API functions (those that end\r
- * in "FromISR").\r
- *\r
- *****************************************************************************/\r
-\r
-\r
-/* Standard includes. */\r
-#include "string.h"\r
-\r
-/* FreeRTOS includes. */\r
-#include "FreeRTOS.h"\r
-#include "task.h"\r
-\r
-/* Demo application include. */\r
-#include "ParTest.h"\r
-\r
-/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
-or 0 to run the more comprehensive test and demo application. */\r
-#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
-\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-/*\r
- * Perform any application specific hardware configuration. The clocks,\r
- * memory, etc. are configured before main() is called.\r
- */\r
-static void prvSetupHardware( void );\r
-\r
-/*\r
- * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
- * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
- */\r
-extern void main_blinky( void );\r
-extern void main_full( void );\r
-\r
-/*\r
- * CMSIS clock configuration function.\r
- */\r
-extern void SystemCoreClockUpdate( void );\r
-\r
-/*-----------------------------------------------------------*/\r
-\r
-int main( void )\r
-{\r
- /* Prepare the hardware to run this demo. */\r
- prvSetupHardware();\r
-\r
- /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
- of this file. */\r
- #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
- {\r
- main_blinky();\r
- }\r
- #else\r
- {\r
- main_full();\r
- }\r
- #endif\r
-\r
- return 0;\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-static void prvSetupHardware( void )\r
-{\r
- SystemCoreClockUpdate();\r
- vParTestInitialise();\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationMallocFailedHook( void )\r
-{\r
- /* vApplicationMallocFailedHook() will only be called if\r
- configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
- function that will get called if a call to pvPortMalloc() fails.\r
- pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
- timer or semaphore is created. It is also called by various parts of the\r
- demo application. If heap_1.c or heap_2.c are used, then the size of the\r
- heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
- FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
- to query the size of free heap space that remains (although it does not\r
- provide information on how the remaining heap might be fragmented). */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationIdleHook( void )\r
-{\r
- /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
- to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
- task. It is essential that code added to this hook function never attempts\r
- to block in any way (for example, call xQueueReceive() with a block time\r
- specified, or call vTaskDelay()). If the application makes use of the\r
- vTaskDelete() API function (as this demo application does) then it is also\r
- important that vApplicationIdleHook() is permitted to return to its calling\r
- function, because it is the responsibility of the idle task to clean up\r
- memory allocated by the kernel to any task that has since been deleted. */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
-{\r
- ( void ) pcTaskName;\r
- ( void ) pxTask;\r
-\r
- /* Run time stack overflow checking is performed if\r
- configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
- function is called if a stack overflow is detected. */\r
- taskDISABLE_INTERRUPTS();\r
- for( ;; );\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-void vApplicationTickHook( void )\r
-{\r
- /* This function will be called by each tick interrupt if\r
- configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
- added here, but the tick hook is called from an interrupt context, so\r
- code must not attempt to block, and only the interrupt safe FreeRTOS API\r
- functions can be used (those that end in FromISR()). */\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
-#ifdef JUST_AN_EXAMPLE_ISR\r
-\r
-void Dummy_IRQHandler(void)\r
-{\r
-long lHigherPriorityTaskWoken = pdFALSE;\r
-\r
- /* Clear the interrupt if necessary. */\r
- Dummy_ClearITPendingBit();\r
-\r
- /* This interrupt does nothing more than demonstrate how to synchronise a\r
- task with an interrupt. A semaphore is used for this purpose. Note\r
- lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions\r
- that end in "FromISR" can be called from an ISR. */\r
- xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
-\r
- /* If there was a task that was blocked on the semaphore, and giving the\r
- semaphore caused the task to unblock, and the unblocked task has a priority\r
- higher than the current Running state task (the task that this interrupt\r
- interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
- internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the\r
- portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
- ensure this interrupt returns directly to the unblocked, higher priority,\r
- task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
- portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
-}\r
-\r
-#endif /* JUST_AN_EXAMPLE_ISR */\r
-\r
-\r
-\r
-\r
+++ /dev/null
-@REM This batch file has been generated by the IAR Embedded Workbench\r
-@REM C-SPY Debugger, as an aid to preparing a command line for running\r
-@REM the cspybat command line utility using the appropriate settings.\r
-@REM\r
-@REM Note that this file is generated every time a new debug session\r
-@REM is initialized, so you may want to move or rename the file before\r
-@REM making changes.\r
-@REM\r
-@REM You can launch cspybat by typing the name of this batch file followed\r
-@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
-@REM\r
-@REM Read about available command line parameters in the C-SPY Debugging\r
-@REM Guide. Hints about additional command line parameters that may be\r
-@REM useful in specific cases:\r
-@REM --download_only Downloads a code image without starting a debug\r
-@REM session afterwards.\r
-@REM --silent Omits the sign-on message.\r
-@REM --timeout Limits the maximum allowed execution time.\r
-@REM \r
-\r
-\r
-"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\Infineon\FlashXMC1200.board" --backend -B "--endian=little" "--cpu=Cortex-M0" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc1200.ddf" "--drv_verify_download" "--semihosting" "--device=xmc1200" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000" \r
-\r
-\r
+++ /dev/null
-[DebugChecksum]\r
-Checksum=-2111807952\r
-[Stack]\r
-FillEnabled=0\r
-OverflowWarningsEnabled=1\r
-WarningThreshold=90\r
-SpWarningsEnabled=1\r
-WarnLogOnly=1\r
-UseTrigger=1\r
-TriggerName=main\r
-LimitSize=0\r
-ByteLimit=50\r
-[Exceptions]\r
-StopOnUncaught=_ 0\r
-StopOnThrow=_ 0\r
-[CallStack]\r
-ShowArgs=0\r
-[Disassembly]\r
-MixedMode=1\r
-[JLinkDriver]\r
-CStepIntDis=_ 0\r
-[SWOTraceHWSettings]\r
-OverrideDefaultClocks=0\r
-CpuClock=72000000\r
-ClockAutoDetect=0\r
-ClockWanted=1000000\r
-JtagSpeed=1000000\r
-Prescaler=72\r
-TimeStampPrescIndex=0\r
-TimeStampPrescData=0\r
-PcSampCYCTAP=1\r
-PcSampPOSTCNT=15\r
-PcSampIndex=0\r
-DataLogMode=0\r
-ITMportsEnable=0\r
-ITMportsTermIO=0\r
-ITMportsLogFile=0\r
-ITMlogFile=$PROJ_DIR$\ITM.log\r
-[PowerLog]\r
-LogEnabled=0\r
-GraphEnabled=0\r
-ShowTimeLog=1\r
-ShowTimeSum=0\r
-Title0=I0\r
-Symbol0=0 4 1\r
-LiveEnabled=0\r
-LiveFile=PowerLogLive.log\r
-[DataLog]\r
-LogEnabled=0\r
-SumEnabled=0\r
-GraphEnabled=0\r
-ShowTimeLog=1\r
-ShowTimeSum=1\r
-[EventLog]\r
-LogEnabled=0\r
-SumEnabled=0\r
-GraphEnabled=0\r
-ShowTimeLog=1\r
-ShowTimeSum=1\r
-Title0=Ch0\r
-Symbol0=0 4 1\r
-Title1=Ch1\r
-Symbol1=0 4 1\r
-Title2=Ch2\r
-Symbol2=0 4 1\r
-Title3=Ch3\r
-Symbol3=0 4 1\r
-SumSortOrder=0\r
-[InterruptLog]\r
-LogEnabled=0\r
-SumEnabled=0\r
-GraphEnabled=0\r
-ShowTimeLog=1\r
-ShowTimeSum=1\r
-SumSortOrder=0\r
-[Log file]\r
-LoggingEnabled=_ 0\r
-LogFile=_ ""\r
-Category=_ 0\r
-[TermIOLog]\r
-LoggingEnabled=_ 0\r
-LogFile=_ ""\r
-[Trace2]\r
-Enabled=0\r
-ShowSource=0\r
-[SWOTraceWindow]\r
-PcSampling=0\r
-InterruptLogs=0\r
-ForcedTimeStamps=0\r
-EventCPI=0\r
-EventEXC=0\r
-EventFOLD=0\r
-EventLSU=0\r
-EventSLEEP=0\r
-[PowerProbe]\r
-Frequency=10000\r
-Probe0=I0\r
-ProbeSetup0=2 1 1 2 0 0\r
-[CallStackLog]\r
-Enabled=0\r
-[DriverProfiling]\r
-Enabled=0\r
-Mode=3\r
-Graph=0\r
-Symbiont=0\r
-Exclusions=\r
-[Disassemble mode]\r
-mode=0\r
-[Breakpoints2]\r
-Count=0\r
-[Aliases]\r
-Count=0\r
-SuppressDialog=0\r
+++ /dev/null
-<?xml version="1.0" encoding="iso-8859-1"?>\r
-\r
-<Workspace>\r
- <ConfigDictionary>\r
- \r
- <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
- <Desktop>\r
- <Static>\r
- <Workspace>\r
- <ColumnWidths>\r
- \r
- \r
- \r
- \r
- <Column0>236</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
- </Workspace>\r
- <Build>\r
- \r
- \r
- \r
- \r
- <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
- <TerminalIO/>\r
- </Static>\r
- <Windows>\r
- \r
- \r
- <Wnd0>\r
- <Tabs>\r
- <Tab>\r
- <Identity>TabID-23707-15152</Identity>\r
- <TabName>Workspace</TabName>\r
- <Factory>Workspace</Factory>\r
- <Session>\r
- \r
- <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/System</ExpandedNode></NodeDict></Session>\r
- </Tab>\r
- </Tabs>\r
- \r
- <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
- <Tabs>\r
- <Tab>\r
- <Identity>TabID-19002-15240</Identity>\r
- <TabName>Build</TabName>\r
- <Factory>Build</Factory>\r
- <Session/>\r
- </Tab>\r
- </Tabs>\r
- \r
- <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
- <Editor>\r
- \r
- \r
- \r
- \r
- <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>99</YPos2><SelStart2>5509</SelStart2><SelEnd2>5509</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main-full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>111</YPos2><SelStart2>7445</SelStart2><SelEnd2>7445</SelEnd2></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
- <Positions>\r
- \r
- \r
- \r
- \r
- \r
- <Top><Row0><Sizes><Toolbar-01348f40><key>iaridepm.enu1</key></Toolbar-01348f40></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>310</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>185714</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
- </Desktop>\r
-</Workspace>\r
-\r
-\r
+++ /dev/null
-[BREAKPOINTS]\r
-ShowInfoWin = 1\r
-EnableFlashBP = 2\r
-BPDuringExecution = 0\r
-[CFI]\r
-CFISize = 0x00\r
-CFIAddr = 0x00\r
-[CPU]\r
-OverrideMemMap = 0\r
-AllowSimulation = 1\r
-ScriptFile=""\r
-[FLASH]\r
-CacheExcludeSize = 0x00\r
-CacheExcludeAddr = 0x00\r
-MinNumBytesFlashDL = 0\r
-SkipProgOnCRCMatch = 1\r
-VerifyDownload = 1\r
-AllowCaching = 1\r
-EnableFlashDL = 2\r
-Override = 0\r
-Device="UNSPECIFIED"\r
-[GENERAL]\r
-WorkRAMSize = 0x00\r
-WorkRAMAddr = 0x00\r
-RAMUsageLimit = 0x00\r
-[SWO]\r
-SWOLogFile=""\r
-[MEM]\r
-RdOverrideOrMask = 0x00\r
-RdOverrideAndMask = 0xFFFFFFFF\r
-RdOverrideAddr = 0xFFFFFFFF\r
-WrOverrideOrMask = 0x00\r
-WrOverrideAndMask = 0xFFFFFFFF\r
-WrOverrideAddr = 0xFFFFFFFF\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1200.c\r
- * @brief Device specific initialization for the XMC1200-Series according\r
- * to CMSIS\r
- * @version V1.4\r
- * @date 01 Feb 2013\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with\r
- * Infineon\92s microcontrollers.\r
- *\r
- * This file can be freely distributed within development tools that are\r
- * supporting such microcontrollers.\r
- *\r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * *************************** Change history ********************************\r
- * V1.2, 13 Dec 2012, PKB : Created change history table\r
- * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation\r
- * V1.4, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK\r
- */\r
-\r
-#include "system_XMC1200.h"\r
-#include <XMC1200.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions\r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-#define DCO_DCLK_MULTIPLIER 16384000UL\r
-#define DCO_DCLK_DIVIDER 9UL\r
-#define MCLK_MHZ 32000000UL\r
-#define KHZ_MULTIPLIER 1000UL\r
-#define FRACBITS 8UL\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */\r
-uint32_t SystemCoreClock;\r
-\r
-/*----------------------------------------------------------------------------\r
- Fixed point math definitions\r
- *----------------------------------------------------------------------------*/\r
-typedef int32_t Q_24_8;\r
-typedef int32_t Q_15_0;\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{\r
-\r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */\r
- if(AllowClkInitByStartup()){\r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note -\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, FDIV, CLKCR, Clock;\r
-\r
- CLKCR = SCU_CLK -> CLKCR;\r
- IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;\r
- FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;\r
-\r
- if(IDIV)\r
- {\r
- /* Divider is enabled and used */\r
- if(0 == FDIV)\r
- {\r
- /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */\r
- Clock = MCLK_MHZ / IDIV;\r
- }\r
- else\r
- {\r
- /* Both integer and fractional divider must be considered */\r
- /* 1. IDIV + FDIV/256 */\r
- Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;\r
-\r
- /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */\r
- Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;\r
- Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER;\r
- Clock = Clock >> DCO_DCLK_DIVIDER;\r
- }\r
- }\r
- else\r
- {\r
- /* Divider bypassed. Simply divide DCO_DCLK by 2 */\r
- Clock = MCLK_MHZ;\r
- }\r
-\r
- /* Finally with the math class over, update SystemCoreClock */\r
- SystemCoreClock = Clock;\r
-}\r
-\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1200.h\r
- * @brief Device specific initialization for the XMC1200-Series according \r
- * to CMSIS\r
- * @version V1.1\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/* \r
- * **************************** Change history *******************************\r
- * V1.1, 13 Dec 2012, PKB : Created this table, added extern and stdint\r
- */\r
-\r
-#include <stdint.h>\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-extern uint32_t SystemCoreClock;\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * Initialize the PLL and update the \r
- * SystemCoreClock variable.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void);\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void);\r
-\r
--- /dev/null
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--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
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+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
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+ </link>\r
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+ <type>1</type>\r
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+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/recmutex.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/Minimal/recmutex.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/ARM_CM0</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_BASE/Source/portable/GCC/ARM_CM0</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/heap_4.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/portable/MemMang/heap_4.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_BASE/Source/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/list.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/list.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/queue.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/queue.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/tasks.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/tasks.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/timers.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/timers.c</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <variableList>\r
+ <variable>\r
+ <name>FREERTOS_BASE</name>\r
+ <value>$%7BPARENT-2-PROJECT_LOC%7D</value>\r
+ </variable>\r
+ </variableList>\r
+</projectDescription>\r
--- /dev/null
+BOARD=XMC1200_Boot_Kit\r
+CODE_LOCATION=FLASH\r
+ENDIAN=Little-endian\r
+MCU=XMC1200-T038F0200\r
+MCU_VENDOR=Infineon\r
+MODEL=Pro\r
+PROBE=SEGGER J-LINK\r
+PROJECT_FORMAT_VERSION=2\r
+TARGET=ARM\u00AE\r
+VERSION=4.1.0\r
+eclipse.preferences.version=1\r
--- /dev/null
+eclipse.preferences.version=1\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/delimiter=;\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/operation=remove\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/delimiter=;\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/operation=remove\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/append=true\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/delimiter=;\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/operation=remove\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/append=true\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+void vRegTest1Task( void ) __attribute__((naked));\r
+void vRegTest2Task( void ) __attribute__((naked));\r
+\r
+void vRegTest1Task( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest1LoopCounter \n"\r
+ " \n"\r
+ " /* Fill the core registers with known values. */ \n"\r
+ " movs r1, #101 \n"\r
+ " movs r2, #102 \n"\r
+ " movs r3, #103 \n"\r
+ " movs r4, #104 \n"\r
+ " movs r5, #105 \n"\r
+ " movs r6, #106 \n"\r
+ " movs r7, #107 \n"\r
+ " movs r0, #108 \n"\r
+ " mov r8, r0 \n"\r
+ " movs r0, #109 \n"\r
+ " mov r9, r0 \n"\r
+ " movs r0, #110 \n"\r
+ " mov r10, r0 \n"\r
+ " movs r0, #111 \n"\r
+ " mov r11, r0 \n"\r
+ " movs r0, #112 \n"\r
+ " mov r12, r0 \n"\r
+ " movs r0, #100 \n"\r
+ " \n"\r
+ "reg1_loop: \n"\r
+ " \n"\r
+ " cmp r0, #100 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r1, #101 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r2, #102 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r3, #103 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r4, #104 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r5, #105 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r6, #106 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r7, #107 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #108 \n"\r
+ " cmp r8, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #109 \n"\r
+ " cmp r9, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #110 \n"\r
+ " cmp r10, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #111 \n"\r
+ " cmp r11, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #112 \n"\r
+ " cmp r12, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " \n"\r
+ " /* Everything passed, increment the loop counter. */ \n"\r
+ " push { r1 } \n"\r
+ " ldr r0, =ulRegTest1LoopCounter \n"\r
+ " ldr r1, [r0] \n"\r
+ " add r1, r1, #1 \n"\r
+ " str r1, [r0] \n"\r
+ " pop { r1 } \n"\r
+ " \n"\r
+ " /* Start again. */ \n"\r
+ " movs r0, #100 \n"\r
+ " b reg1_loop \n"\r
+ " \n"\r
+ "reg1_error_loop: \n"\r
+ " /* If this line is hit then there was an error in a core register value. \n"\r
+ " The loop ensures the loop counter stops incrementing. */ \n"\r
+ " b reg1_error_loop \n"\r
+ " nop \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest2Task( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest2LoopCounter \n"\r
+ " \n"\r
+ " /* Fill the core registers with known values. */ \n"\r
+ " movs r1, #1 \n"\r
+ " movs r2, #2 \n"\r
+ " movs r3, #3 \n"\r
+ " movs r4, #4 \n"\r
+ " movs r5, #5 \n"\r
+ " movs r6, #6 \n"\r
+ " movs r7, #7 \n"\r
+ " movs r0, #8 \n"\r
+ " movs r8, r0 \n"\r
+ " movs r0, #9 \n"\r
+ " mov r9, r0 \n"\r
+ " movs r0, #10 \n"\r
+ " mov r10, r0 \n"\r
+ " movs r0, #11 \n"\r
+ " mov r11, r0 \n"\r
+ " movs r0, #12 \n"\r
+ " mov r12, r0 \n"\r
+ " movs r0, #10 \n"\r
+ " \n"\r
+ "reg2_loop: \n"\r
+ " \n"\r
+ " cmp r0, #10 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r1, #1 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r2, #2 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r3, #3 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r4, #4 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r5, #5 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r6, #6 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r7, #7 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #8 \n"\r
+ " cmp r8, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #9 \n"\r
+ " cmp r9, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #10 \n"\r
+ " cmp r10, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #11 \n"\r
+ " cmp r11, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #12 \n"\r
+ " cmp r12, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " \n"\r
+ " /* Everything passed, increment the loop counter. */ \n"\r
+ " push { r1 } \n"\r
+ " ldr r0, =ulRegTest2LoopCounter \n"\r
+ " ldr r1, [r0] \n"\r
+ " add r1, r1, #1 \n"\r
+ " str r1, [r0] \n"\r
+ " pop { r1 } \n"\r
+ " \n"\r
+ " /* Start again. */ \n"\r
+ " movs r0, #10 \n"\r
+ " b reg2_loop \n"\r
+ " \n"\r
+ "reg2_error_loop: \n"\r
+ " /* If this line is hit then there was an error in a core register value. \n"\r
+ " The loop ensures the loop counter stops incrementing. */ \n"\r
+ " b reg2_error_loop \n"\r
+ " nop \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**
+*****************************************************************************
+**
+** File : startup_XMC1200.s
+**
+** Abstract : This assembler file contains interrupt vector and
+** startup code for ARM.
+**
+** Functions : Reset_Handler
+** Default_Handler
+** XMCVeneer code
+**
+** Target : Infineon $(DEVICE) Device
+**
+** Environment : Atollic TrueSTUDIO(R)
+**
+** Distribution: The file is distributed \93as is,\94 without any warranty
+** of any kind.
+**
+** (c)Copyright Atollic AB.
+** You may use this file as-is or modify it according to the needs of your
+** project. This file may only be built (assembled or compiled and linked)
+** using the Atollic TrueSTUDIO(R) product. The use of this file together
+** with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+#ifdef DAVE_CE
+#include <Device_Data.h>
+#else
+#define CLKVAL1_SSW 0x80000000
+#define CLKVAL2_SSW 0x80000000
+#endif
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global Reset_Handler
+.global InterruptVector
+.global Default_Handler
+
+/* Linker script definitions */
+/* start address for the initialization values of the .data section */
+.word _sidata
+/* start address for the .data section */
+.word _sdata
+/* end address for the .data section */
+.word _edata
+/* start address for the .bss section */
+.word _sbss
+/* end address for the .bss section */
+.word _ebss
+
+.word VeneerLoadAddr
+.word VeneerStart
+.word VeneerSize
+
+
+/**
+**===========================================================================
+** Program - Reset_Handler
+** Abstract: This code gets called after reset.
+**===========================================================================
+*/
+ .section .text.Reset_Handler,"ax", %progbits
+ .type Reset_Handler, %function
+Reset_Handler:
+ /* Set stack pointer */
+ ldr r0, =_estack
+ mov sp, r0
+
+ /* Branch to SystemInit function */
+ bl SystemInit
+
+ /* Copy data initialization values */
+ ldr r1,=_sidata
+ ldr r2,=_sdata
+ ldr r3,=_edata
+ b cmpdata
+CopyLoop:
+ ldr r0, [r1]
+ str r0, [r2]
+ adds r1, r1, #4
+ adds r2, r2, #4
+cmpdata:
+ cmp r2, r3
+ blt CopyLoop
+
+ /* Clear BSS section */
+ movs r0, #0
+ ldr r2,=_sbss
+ ldr r3,=_ebss
+ b cmpbss
+ClearLoop:
+ str r0, [r2]
+ adds r2, r2, #4
+cmpbss:
+ cmp r2, r3
+ blt ClearLoop
+
+ /* VENEER COPY */
+ /* R0 = Start address, R1 = Destination address, R2 = Size */
+ ldr r0, =VeneerLoadAddr
+ ldr r1, =VeneerStart
+ ldr r2, =VeneerSize
+
+STARTVENEERCOPY:
+ /* R2 contains byte count. Change it to word count. It is ensured in the
+ linker script that the length is always word aligned.
+ */
+ lsrs r2,r2,#2 /* Divide by 4 to obtain word count */
+ beq SKIPVENEERCOPY
+
+ /* The proverbial loop from the schooldays */
+VENEERCOPYLOOP:
+ ldr r3,[R0]
+ str r3,[R1]
+ subs r2,#1
+ beq SKIPVENEERCOPY
+ adds r0,#4
+ adds r1,#4
+ b VENEERCOPYLOOP
+
+SKIPVENEERCOPY:
+ /* Update System Clock */
+ ldr r0,=SystemCoreClockUpdate
+ blx r0
+
+ /* Call static constructors */
+ bl __libc_init_array
+
+ /* Branch to main */
+ bl main
+
+ /* If main returns, branch to Default_Handler. */
+ b Default_Handler
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+**===========================================================================
+** Program - Default_Handler
+** Abstract: This code gets called when the processor receives an
+** unexpected interrupt.
+**===========================================================================
+*/
+ .section .text.Default_Handler,"ax", %progbits
+Default_Handler:
+ b Default_Handler
+
+ .size Default_Handler, .-Default_Handler
+
+/**
+**===========================================================================
+** Interrupt vector table
+**===========================================================================
+*/
+ .section .isr_vector,"a", %progbits
+ .globl InterruptVector
+ .type InterruptVector, %object
+
+InterruptVector:
+ .word _estack /* 0 - Stack pointer */
+ .word Reset_Handler /* 1 - Reset */
+ .word NMI_Handler /* 2 - NMI */
+ .word HardFault_Handler /* 3 - Hard fault */
+ .word CLKVAL1_SSW /* Clock configuration value */
+ .word CLKVAL2_SSW /* Clock gating configuration */
+
+ .size InterruptVector, . - InterruptVector
+
+/**
+**===========================================================================
+** Weak interrupt handlers redirected to Default_Handler. These can be
+** overridden in user code.
+**===========================================================================
+*/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler, Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler, Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler, Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler, Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler, Default_Handler
+
+/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+/* IRQ Handlers */
+ .weak SCU_0_IRQHandler
+ .type SCU_0_IRQHandler, %function
+SCU_0_IRQHandler:
+ B .
+ .size SCU_0_IRQHandler, . - SCU_0_IRQHandler
+/* ======================================================================== */
+ .weak SCU_1_IRQHandler
+ .type SCU_1_IRQHandler, %function
+SCU_1_IRQHandler:
+ B .
+ .size SCU_1_IRQHandler, . - SCU_1_IRQHandler
+/* ======================================================================== */
+ .weak SCU_2_IRQHandler
+ .type SCU_2_IRQHandler, %function
+SCU_2_IRQHandler:
+ B .
+ .size SCU_2_IRQHandler, . - SCU_2_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_0_IRQHandler
+ .type ERU0_0_IRQHandler, %function
+ERU0_0_IRQHandler:
+ B .
+ .size ERU0_0_IRQHandler, . - ERU0_0_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_1_IRQHandler
+ .type ERU0_1_IRQHandler, %function
+ERU0_1_IRQHandler:
+ B .
+ .size ERU0_1_IRQHandler, . - ERU0_1_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_2_IRQHandler
+ .type ERU0_2_IRQHandler, %function
+ERU0_2_IRQHandler:
+ B .
+ .size ERU0_2_IRQHandler, . - ERU0_2_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_3_IRQHandler
+ .type ERU0_3_IRQHandler, %function
+ERU0_3_IRQHandler:
+ B .
+ .size ERU0_3_IRQHandler, . - ERU0_3_IRQHandler
+/* ======================================================================== */
+ .weak MATH0_0_IRQHandler
+ .type MATH0_0_IRQHandler, %function
+MATH0_0_IRQHandler:
+ B .
+ .size MATH0_0_IRQHandler, . - MATH0_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_C0_0_IRQHandler
+ .type VADC0_C0_0_IRQHandler , %function
+VADC0_C0_0_IRQHandler:
+ B .
+ .size VADC0_C0_0_IRQHandler , . - VADC0_C0_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_C0_1_IRQHandler
+ .type VADC0_C0_1_IRQHandler , %function
+VADC0_C0_1_IRQHandler:
+ B .
+ .size VADC0_C0_1_IRQHandler , . - VADC0_C0_1_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G0_0_IRQHandler
+ .type VADC0_G0_0_IRQHandler, %function
+VADC0_G0_0_IRQHandler:
+ B .
+ .size VADC0_G0_0_IRQHandler, . - VADC0_G0_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G0_1_IRQHandler
+ .type VADC0_G0_1_IRQHandler, %function
+VADC0_G0_1_IRQHandler:
+ B .
+ .size VADC0_G0_1_IRQHandler, . - VADC0_G0_1_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G1_0_IRQHandler
+ .type VADC0_G1_0_IRQHandler, %function
+VADC0_G1_0_IRQHandler:
+ B .
+ .size VADC0_G1_0_IRQHandler, . - VADC0_G1_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G1_1_IRQHandler
+ .type VADC0_G1_1_IRQHandler, %function
+VADC0_G1_1_IRQHandler:
+ B .
+ .size VADC0_G1_1_IRQHandler, . - VADC0_G1_1_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_0_IRQHandler
+ .type CCU40_0_IRQHandler, %function
+CCU40_0_IRQHandler:
+ B .
+ .size CCU40_0_IRQHandler, . - CCU40_0_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_1_IRQHandler
+ .type CCU40_1_IRQHandler, %function
+
+CCU40_1_IRQHandler:
+ B .
+ .size CCU40_1_IRQHandler, . - CCU40_1_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_2_IRQHandler
+ .type CCU40_2_IRQHandler, %function
+CCU40_2_IRQHandler:
+ B .
+ .size CCU40_2_IRQHandler, . - CCU40_2_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_3_IRQHandler
+ .type CCU40_3_IRQHandler, %function
+CCU40_3_IRQHandler:
+ B .
+ .size CCU40_3_IRQHandler, . - CCU40_3_IRQHandler
+/* ======================================================================== */
+ .weak CCU80_0_IRQHandler
+ .type CCU80_0_IRQHandler, %function
+CCU80_0_IRQHandler:
+ B .
+ .size CCU80_0_IRQHandler, . - CCU80_0_IRQHandler
+/* ======================================================================== */
+ .weak CCU80_1_IRQHandler
+ .type CCU80_1_IRQHandler, %function
+CCU80_1_IRQHandler:
+ B .
+ .size CCU80_1_IRQHandler, . - CCU80_1_IRQHandler
+/* ======================================================================== */
+ .weak POSIF0_0_IRQHandler
+ .type POSIF0_0_IRQHandler, %function
+
+POSIF0_0_IRQHandler:
+ B .
+ .size POSIF0_0_IRQHandler, . - POSIF0_0_IRQHandler
+/* ======================================================================== */
+ .weak POSIF0_1_IRQHandler
+ .type POSIF0_1_IRQHandler, %function
+POSIF0_1_IRQHandler:
+ B .
+ .size POSIF0_1_IRQHandler, . - POSIF0_1_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_0_IRQHandler
+ .type USIC0_0_IRQHandler, %function
+USIC0_0_IRQHandler:
+ B .
+ .size USIC0_0_IRQHandler, . - USIC0_0_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_1_IRQHandler
+ .type USIC0_1_IRQHandler, %function
+USIC0_1_IRQHandler:
+ B .
+ .size USIC0_1_IRQHandler, . - USIC0_1_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_2_IRQHandler
+ .type USIC0_2_IRQHandler, %function
+USIC0_2_IRQHandler:
+ B .
+ .size USIC0_2_IRQHandler, . - USIC0_2_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_3_IRQHandler
+ .type USIC0_3_IRQHandler, %function
+USIC0_3_IRQHandler:
+ B .
+ .size USIC0_3_IRQHandler, . - USIC0_3_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_4_IRQHandler
+ .type USIC0_4_IRQHandler, %function
+USIC0_4_IRQHandler:
+ B .
+ .size USIC0_4_IRQHandler, . - USIC0_4_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_5_IRQHandler
+ .type USIC0_5_IRQHandler, %function
+USIC0_5_IRQHandler:
+ B .
+ .size USIC0_5_IRQHandler, . - USIC0_5_IRQHandler
+/* ======================================================================== */
+ .weak LEDTS0_0_IRQHandler
+ .type LEDTS0_0_IRQHandler, %function
+LEDTS0_0_IRQHandler:
+ B .
+ .size LEDTS0_0_IRQHandler, . - LEDTS0_0_IRQHandler
+/* ======================================================================== */
+ .weak LEDTS1_0_IRQHandler
+ .type LEDTS1_0_IRQHandler, %function
+LEDTS1_0_IRQHandler:
+ B .
+ .size LEDTS1_0_IRQHandler, . - LEDTS1_0_IRQHandler
+/* ======================================================================== */
+ .weak BCCU0_0_IRQHandler
+ .type BCCU0_0_IRQHandler, %function
+BCCU0_0_IRQHandler:
+ B .
+ .size BCCU0_0_IRQHandler, . - BCCU0_0_IRQHandler
+/* ======================================================================== */
+/* ======================================================================== */
+
+/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
+ .section ".XmcVeneerCode","ax",%progbits
+.globl HardFault_Veneer
+HardFault_Veneer:
+ LDR R0, =HardFault_Handler
+ MOV PC,R0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+
+/* ======================================================================== */
+.globl SVC_Veneer
+SVC_Veneer:
+ LDR R0, =SVC_Handler
+ MOV PC,R0
+ .long 0
+ .long 0
+/* ======================================================================== */
+.globl PendSV_Veneer
+PendSV_Veneer:
+ LDR R0, =PendSV_Handler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SysTick_Veneer
+SysTick_Veneer:
+ LDR R0, =SysTick_Handler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_0_Veneer
+SCU_0_Veneer:
+ LDR R0, =SCU_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_1_Veneer
+SCU_1_Veneer:
+ LDR R0, =SCU_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_2_Veneer
+SCU_2_Veneer:
+ LDR R0, =SCU_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_3_Veneer
+SCU_3_Veneer:
+ LDR R0, =ERU0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_4_Veneer
+SCU_4_Veneer:
+ LDR R0, =ERU0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_5_Veneer
+SCU_5_Veneer:
+ LDR R0, =ERU0_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_6_Veneer
+SCU_6_Veneer:
+ LDR R0, =ERU0_3_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_7_Veneer
+SCU_7_Veneer:
+ LDR R0, =MATH0_0_IRQHandler
+ MOV PC,R0
+ .long 0
+/* ======================================================================== */
+.globl VADC0_C0_0_Veneer
+VADC0_C0_0_Veneer:
+ LDR R0, =VADC0_C0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_C0_1_Veneer
+VADC0_C0_1_Veneer:
+ LDR R0, =VADC0_C0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G0_0_Veneer
+VADC0_G0_0_Veneer:
+ LDR R0, =VADC0_G0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G0_1_Veneer
+VADC0_G0_1_Veneer:
+ LDR R0, =VADC0_G0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G1_0_Veneer
+VADC0_G1_0_Veneer:
+ LDR R0, =VADC0_G1_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G1_1_Veneer
+VADC0_G1_1_Veneer:
+ LDR R0, =VADC0_G1_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_0_Veneer
+CCU40_0_Veneer:
+ LDR R0, =CCU40_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_1_Veneer
+CCU40_1_Veneer:
+ LDR R0, =CCU40_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_2_Veneer
+CCU40_2_Veneer:
+ LDR R0, =CCU40_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_3_Veneer
+CCU40_3_Veneer:
+ LDR R0, =CCU40_3_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU80_0_Veneer
+CCU80_0_Veneer:
+ LDR R0, =CCU80_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU80_1_Veneer
+CCU80_1_Veneer:
+ LDR R0, =CCU80_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl POSIF0_0_Veneer
+POSIF0_0_Veneer:
+ LDR R0, =POSIF0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl POSIF0_1_Veneer
+POSIF0_1_Veneer:
+ LDR R0, =POSIF0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_0_Veneer
+USIC0_0_Veneer:
+ LDR R0, =USIC0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_1_Veneer
+USIC0_1_Veneer:
+ LDR R0, =USIC0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_2_Veneer
+USIC0_2_Veneer:
+ LDR R0, =USIC0_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_3_Veneer
+USIC0_3_Veneer:
+ LDR R0, =USIC0_3_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_4_Veneer
+USIC0_4_Veneer:
+ LDR R0, =USIC0_4_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_5_Veneer
+USIC0_5_Veneer:
+ LDR R0, =USIC0_5_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl LEDTS0_0_Veneer
+LEDTS0_0_Veneer:
+ LDR R0, =LEDTS0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl LEDTS1_0_Veneer
+LEDTS1_0_Veneer:
+ LDR R0, =LEDTS1_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+ .globl BCCU0_0_Veneer
+BCCU0_0_Veneer:
+ LDR R0, =BCCU0_0_IRQHandler
+ MOV PC,R0
+
+/* ======================================================================== */
+
+/* ===== Decision function queried by CMSIS startup for Clock tree setup === */
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
+ tree setup.
+
+ This decision routine defined here will always return TRUE.
+
+ When overridden by a definition defined in DAVE code engine, this routine
+ returns FALSE indicating that the code engine has performed the clock setup
+*/
+ .section ".XmcStartup"
+ .weak AllowClkInitByStartup
+ .type AllowClkInitByStartup, %function
+AllowClkInitByStartup:
+ MOVS R0,#1
+ BX LR
+ .size AllowClkInitByStartup, . - AllowClkInitByStartup
+
+/* ====== Definition of the default weak SystemInit_DAVE3 function =========
+If DAVE3 requires an extended SystemInit it will create its own version of
+SystemInit_DAVE3 which overrides this weak definition. Example includes
+setting up of external memory interfaces.
+*/
+ .weak SystemInit_DAVE3
+ .type SystemInit_DAVE3, %function
+SystemInit_DAVE3:
+ NOP
+ BX LR
+ .size SystemInit_DAVE3, . - SystemInit_DAVE3
+
+ .end
--- /dev/null
+/*
+*****************************************************************************
+**
+** File : xmc1000_flash.ld
+**
+** Abstract : Linker script for XMC1200-T038F0200 Device with
+** 200KByte FLASH, 16KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Target : Infineon XMC1000 Microcontrollers
+**
+** Environment : Atollic TrueSTUDIO(R)
+**
+** Distribution: The file is distributed \93as is,\94 without any warranty
+** of any kind.
+**
+** (c)Copyright Atollic AB.
+** You may use this file as-is or modify it according to the needs of your
+** project. This file may only be built (assembled or compiled and linked)
+** using the Atollic TrueSTUDIO(R) product. The use of this file together
+** with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000; /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0; /* required amount of heap */
+_Min_Stack_Size = 0x80; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x10001000, LENGTH = 200K
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
+ MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.XmcStartup);
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ . = ALIGN(4);
+ eROData = . ;
+
+ /* Initialize XMC Veneer interrupt code */
+ VeneerLoadAddr = ABSOLUTE(eROData);
+ .VENEER_Code ABSOLUTE(0x2000000C) :
+ {
+ VeneerStart = .;
+ KEEP(*(.XmcVeneerCode)) /* Keep the VeneerCode */
+ *(.XmcVeneerCode);
+ . = ALIGN(4);
+ VeneerEnd = .;
+
+ } >RAM AT> FLASH
+
+ VeneerSize = ABSOLUTE(VeneerEnd) - ABSOLUTE(VeneerStart);
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* MEMORY_bank1 section, code must be located here explicitly */
+ /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+ .memory_b1_text :
+ {
+ *(.mb1text) /* .mb1text sections (code) */
+ *(.mb1text*) /* .mb1text* sections (code) */
+ *(.mb1rodata) /* read-only data (constants) */
+ *(.mb1rodata*)
+ } >MEMORY_B1
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.20\r
+ * @date 05. March 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constrant "l"\r
+ * Otherwise, use general registers, specified by constrant "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32 - op2)); \r
+}\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+\r
+#ifndef FREERTOS_CONFIG_H\r
+#define FREERTOS_CONFIG_H\r
+\r
+/*-----------------------------------------------------------\r
+ * Application specific definitions.\r
+ *\r
+ * These definitions should be adjusted for your particular hardware and\r
+ * application requirements.\r
+ *\r
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE\r
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.\r
+ *\r
+ * See http://www.freertos.org/a00110.html.\r
+ *----------------------------------------------------------*/\r
+\r
+/* Prevent C code being included by the IAR assembler. */\r
+#ifndef __IASMARM__\r
+ #include <stdint.h>\r
+ extern uint32_t SystemCoreClock;\r
+#endif\r
+\r
+#define configUSE_PREEMPTION 1\r
+#define configUSE_IDLE_HOOK 0\r
+#define configUSE_TICK_HOOK 0\r
+#define configCPU_CLOCK_HZ ( SystemCoreClock )\r
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )\r
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )\r
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 )\r
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6000 ) )\r
+#define configMAX_TASK_NAME_LEN ( 5 )\r
+#define configUSE_TRACE_FACILITY 1\r
+#define configUSE_16_BIT_TICKS 0\r
+#define configIDLE_SHOULD_YIELD 1\r
+#define configUSE_MUTEXES 1\r
+#define configQUEUE_REGISTRY_SIZE 8\r
+#define configCHECK_FOR_STACK_OVERFLOW 2\r
+#define configUSE_RECURSIVE_MUTEXES 1\r
+#define configUSE_MALLOC_FAILED_HOOK 1\r
+#define configUSE_APPLICATION_TASK_TAG 0\r
+#define configUSE_COUNTING_SEMAPHORES 1\r
+#define configGENERATE_RUN_TIME_STATS 0\r
+\r
+/* Co-routine definitions. */\r
+#define configUSE_CO_ROUTINES 0\r
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )\r
+\r
+/* Software timer definitions. */\r
+#define configUSE_TIMERS 1\r
+#define configTIMER_TASK_PRIORITY ( 2 )\r
+#define configTIMER_QUEUE_LENGTH 5\r
+#define configTIMER_TASK_STACK_DEPTH ( 80 )\r
+\r
+/* Set the following definitions to 1 to include the API function, or zero\r
+to exclude the API function. */\r
+#define INCLUDE_vTaskPrioritySet 1\r
+#define INCLUDE_uxTaskPriorityGet 1\r
+#define INCLUDE_vTaskDelete 1\r
+#define INCLUDE_vTaskCleanUpResources 1\r
+#define INCLUDE_vTaskSuspend 1\r
+#define INCLUDE_vTaskDelayUntil 1\r
+#define INCLUDE_vTaskDelay 1\r
+\r
+/* Normal assert() semantics without relying on the provision of an assert.h\r
+header file. */\r
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }\r
+\r
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\r
+standard names - or at least those used in the unmodified vector table. */\r
+#define vPortSVCHandler SVC_Handler\r
+#define xPortPendSVHandler PendSV_Handler\r
+#define xPortSysTickHandler SysTick_Handler\r
+\r
+#endif /* FREERTOS_CONFIG_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+\r
+ EXTERN ulRegTest1LoopCounter\r
+ EXTERN ulRegTest2LoopCounter\r
+\r
+ PUBLIC vRegTest1Task\r
+ PUBLIC vRegTest2Task\r
+\r
+/*-----------------------------------------------------------*/\r
+vRegTest1Task\r
+\r
+ /* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #101\r
+ movs r2, #102\r
+ movs r3, #103\r
+ movs r4, #104\r
+ movs r5, #105\r
+ movs r6, #106\r
+ movs r7, #107\r
+ movs r0, #108\r
+ mov r8, r0\r
+ movs r0, #109\r
+ mov r9, r0\r
+ movs r0, #110\r
+ mov r10, r0\r
+ movs r0, #111\r
+ mov r11, r0\r
+ movs r0, #112\r
+ mov r12, r0\r
+ movs r0, #100\r
+\r
+reg1_loop\r
+ /* Repeatedly check that each register still contains the value written to\r
+ it when the task started. */\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ movs r0, #108\r
+ cmp r8, r0\r
+ bne reg1_error_loop\r
+ movs r0, #109\r
+ cmp r9, r0\r
+ bne reg1_error_loop\r
+ movs r0, #110\r
+ cmp r10, r0\r
+ bne reg1_error_loop\r
+ movs r0, #111\r
+ cmp r11, r0\r
+ bne reg1_error_loop\r
+ movs r0, #112\r
+ cmp r12, r0\r
+ bne reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ /* Start again. */\r
+ movs r0, #100\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+\r
+\r
+\r
+vRegTest2Task\r
+\r
+ /* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #1\r
+ movs r2, #2\r
+ movs r3, #3\r
+ movs r4, #4\r
+ movs r5, #5\r
+ movs r6, #6\r
+ movs r7, #7\r
+ movs r0, #8\r
+ mov r8, r0\r
+ movs r0, #9\r
+ mov r9, r0\r
+ movs r0, #10\r
+ mov r10, r0\r
+ movs r0, #11\r
+ mov r11, r0\r
+ movs r0, #12\r
+ mov r12, r0\r
+ movs r0, #10\r
+\r
+reg2_loop\r
+ /* Repeatedly check that each register still contains the value written to\r
+ it when the task started. */\r
+ cmp r0, #10\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ movs r0, #8\r
+ cmp r8, r0\r
+ bne reg2_error_loop\r
+ movs r0, #9\r
+ cmp r9, r0\r
+ bne reg2_error_loop\r
+ movs r0, #10\r
+ cmp r10, r0\r
+ bne reg2_error_loop\r
+ movs r0, #11\r
+ cmp r11, r0\r
+ bne reg2_error_loop\r
+ movs r0, #12\r
+ cmp r12, r0\r
+ bne reg2_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ /* Start again. */\r
+ movs r0, #10\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ ;/* If this line is hit then there was an error in a core register value.\r
+ ;The loop ensures the loop counter stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+\r
+ END\r
--- /dev/null
+;************************************************\r
+;*\r
+;* Part one of the system initialization code, contains low-level\r
+;* initialization, plain thumb variant.\r
+;*\r
+;* Copyright 2013 IAR Systems. All rights reserved.\r
+;*\r
+;* $Revision: 64600 $\r
+;*\r
+;******************* Version History **********************************************\r
+;\r
+; V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc\r
+;\r
+;**********************************************************************************\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+#ifdef DAVE_CE\r
+#include "XMC1200_SCU.inc"\r
+#include "Device_Data.h"\r
+#else\r
+#define CLKVAL1_SSW 0x00000100\r
+#define CLKVAL2_SSW 0x00000000\r
+#endif\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD 0 ; 0x8\r
+ DCD 0 ; 0xC\r
+ DCD CLKVAL1_SSW ; 0x10 CLK_VAL1 - (CLKCR default)\r
+ DCD CLKVAL2_SSW ; 0x14 CLK_VAL2 - (CGATCLR0 default)\r
+\r
+ SECTION .vect_table:CODE:ROOT(2)\r
+ THUMB\r
+ LDR R0,=HardFault_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=SVC_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=PendSV_Handler\r
+ BX R0\r
+ LDR R0,=SysTick_Handler\r
+ BX R0\r
+\r
+ ; External Interrupts\r
+ LDR R0,=SCU_0_IRQHandler ; Handler name for SR SCU_0\r
+ BX R0\r
+ LDR R0,=SCU_1_IRQHandler ; Handler name for SR SCU_1\r
+ BX R0\r
+ LDR R0,=SCU_2_IRQHandler ; Handler name for SR SCU_2\r
+ BX R0\r
+ LDR R0,=ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
+ BX R0\r
+ LDR R0,=ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
+ BX R0\r
+ LDR R0,=ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
+ BX R0\r
+ LDR R0,=ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
+ BX R0\r
+ LDR R0,=USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
+ BX R0\r
+ LDR R0,=USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
+ BX R0\r
+ LDR R0,=USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
+ BX R0\r
+ LDR R0,=USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
+ BX R0\r
+ LDR R0,=USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
+ BX R0\r
+ LDR R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
+ BX R0\r
+ LDR R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ BX R0\r
+ LDR R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
+ BX R0\r
+ LDR R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
+ BX R0\r
+ LDR R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
+ BX R0\r
+ LDR R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
+ BX R0\r
+ LDR R0,=CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
+ BX R0\r
+ LDR R0,=CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
+ BX R0\r
+ LDR R0,=CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
+ BX R0\r
+ LDR R0,=CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
+ BX R0\r
+ LDR R0,=LEDTS1_0_IRQHandler ; Handler name for SR LEDTS1_0\r
+ BX R0\r
+ LDR R0,=BCCU0_0_IRQHandler ; Handler name for SR BCCU0_0\r
+ BX R0\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ EXTERN SystemInit\r
+ SECTION .text:CODE:NOROOT(2)\r
+\r
+ THUMB\r
+\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =SystemInit_DAVE3\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK Undef_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+Undef_Handler\r
+ B Undef_Handler\r
+\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+\r
+ PUBWEAK SCU_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SCU_0_IRQHandler\r
+ B SCU_0_IRQHandler\r
+\r
+ PUBWEAK SCU_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SCU_1_IRQHandler\r
+ B SCU_1_IRQHandler\r
+\r
+\r
+ PUBWEAK SCU_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SCU_2_IRQHandler\r
+ B SCU_2_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_0_IRQHandler\r
+ B ERU0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_1_IRQHandler\r
+ B ERU0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_2_IRQHandler\r
+ B ERU0_2_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_3_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_3_IRQHandler\r
+ B ERU0_3_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_0_IRQHandler\r
+ B USIC0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_1_IRQHandler\r
+ B USIC0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_2_IRQHandler\r
+ B USIC0_2_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_3_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_3_IRQHandler\r
+ B USIC0_3_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_4_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_4_IRQHandler\r
+ B USIC0_4_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_5_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_5_IRQHandler\r
+ B USIC0_5_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_C0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_C0_0_IRQHandler\r
+ B VADC0_C0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_C0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_C0_1_IRQHandler\r
+ B VADC0_C0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G0_0_IRQHandler\r
+ B VADC0_G0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G0_1_IRQHandler\r
+ B VADC0_G0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G1_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G1_0_IRQHandler\r
+ B VADC0_G1_0_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G1_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G1_1_IRQHandler\r
+ B VADC0_G1_1_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_0_IRQHandler\r
+ B CCU40_0_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_1_IRQHandler\r
+ B CCU40_1_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_2_IRQHandler\r
+ B CCU40_2_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_3_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_3_IRQHandler\r
+ B CCU40_3_IRQHandler\r
+\r
+\r
+ PUBWEAK LEDTS0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+LEDTS0_0_IRQHandler\r
+ B LEDTS0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK LEDTS1_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+LEDTS1_0_IRQHandler\r
+ B LEDTS1_0_IRQHandler\r
+\r
+\r
+ PUBWEAK BCCU0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+BCCU0_0_IRQHandler\r
+ B BCCU0_0_IRQHandler\r
+\r
+; Definition of the default weak SystemInit_DAVE3 function\r
+;If DAVE3 requires an extended SystemInit it will create its own version of\r
+;SystemInit_DAVE3 which overrides this weak definition. Example includes\r
+;setting up of external memory interfaces.\r
+\r
+ PUBWEAK SystemInit_DAVE3\r
+ SECTION .text:CODE:REORDER:NOROOT(2)\r
+SystemInit_DAVE3\r
+ NOP\r
+ BX LR\r
+\r
+;Decision function queried by CMSIS startup for Clock tree setup ======== */\r
+;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.\r
+;This decision routine defined here will always return TRUE.\r
+;When overridden by a definition defined in DAVE code engine, this routine\r
+;returns FALSE indicating that the code engine has performed the clock setup\r
+\r
+ PUBWEAK AllowClkInitByStartup\r
+ SECTION .text:CODE:REORDER:NOROOT(2)\r
+AllowClkInitByStartup\r
+ MOVS R0,#1\r
+ BX LR\r
+\r
+ END\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+;/*\r
+; FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+;\r
+; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS provides completely free yet professionally developed, *\r
+; * robust, strictly quality controlled, supported, and cross *\r
+; * platform software that has become a de facto standard. *\r
+; * *\r
+; * Help yourself get started quickly and support the FreeRTOS *\r
+; * project by purchasing a FreeRTOS tutorial book, reference *\r
+; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+; * *\r
+; * Thank you! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+;\r
+; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+; >>! a combined work that includes FreeRTOS without being obliged to provide\r
+; >>! the source code for proprietary components outside of the FreeRTOS\r
+; >>! kernel.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+; link: http://www.freertos.org/a00114.html\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * Having a problem? Start by reading the FAQ "My application does *\r
+; * not run, what could be wrong?" *\r
+; * *\r
+; * http://www.FreeRTOS.org/FAQHelp.html *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+; license and Real Time Engineers Ltd. contact details.\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+; licenses offer ticketed support, indemnification and middleware.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;\r
+; 1 tab == 4 spaces!\r
+;*/\r
+\r
+ PRESERVE8\r
+ THUMB\r
+ \r
+\r
+ IMPORT ulRegTest1LoopCounter\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ EXTERN vPortYield ;////////////////////////////////////////////////////////////////////////////////////////\r
+\r
+ EXPORT vRegTest1Task\r
+ EXPORT vRegTest2Task\r
+ \r
+ AREA |.text|, CODE, READONLY\r
+\r
+;/*-----------------------------------------------------------*/\r
+vRegTest1Task PROC\r
+\r
+ ;/* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #101\r
+ movs r2, #102\r
+ movs r3, #103\r
+ movs r4, #104\r
+ movs r5, #105\r
+ movs r6, #106\r
+ movs r7, #107\r
+ movs r0, #108\r
+ mov r8, r0\r
+ movs r0, #109\r
+ mov r9, r0\r
+ movs r0, #110\r
+ mov r10, r0\r
+ movs r0, #111\r
+ mov r11, r0\r
+ movs r0, #112\r
+ mov r12, r0\r
+ movs r0, #100\r
+\r
+reg1_loop\r
+ ;/* Repeatedly check that each register still contains the value written to\r
+ ;it when the task started. */\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ movs r0, #108\r
+ cmp r8, r0\r
+ bne reg1_error_loop\r
+ movs r0, #109\r
+ cmp r9, r0\r
+ bne reg1_error_loop\r
+ movs r0, #110\r
+ cmp r10, r0\r
+ bne reg1_error_loop\r
+ movs r0, #111\r
+ cmp r11, r0\r
+ bne reg1_error_loop\r
+ movs r0, #112\r
+ cmp r12, r0\r
+ bne reg1_error_loop\r
+\r
+ ;/* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ ;/* Start again. */\r
+ movs r0, #100\r
+ \r
+ push {r0-r1}\r
+ bl vPortYield ;;///////////////////////////////////////////////////////////////////////////////////////////////////\r
+ pop {r0-r1}\r
+ \r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ ;/* If this line is hit then there was an error in a core register value.\r
+ ;The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+ ENDP\r
+\r
+\r
+\r
+vRegTest2Task PROC\r
+\r
+ ;/* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #1\r
+ movs r2, #2\r
+ movs r3, #3\r
+ movs r4, #4\r
+ movs r5, #5\r
+ movs r6, #6\r
+ movs r7, #7\r
+ movs r0, #8\r
+ mov r8, r0\r
+ movs r0, #9\r
+ mov r9, r0\r
+ movs r0, #10\r
+ mov r10, r0\r
+ movs r0, #11\r
+ mov r11, r0\r
+ movs r0, #12\r
+ mov r12, r0\r
+ movs r0, #10\r
+\r
+reg2_loop\r
+ ;/* Repeatedly check that each register still contains the value written to\r
+ ;it when the task started. */\r
+ cmp r0, #10\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ movs r0, #8\r
+ cmp r8, r0\r
+ bne reg2_error_loop\r
+ movs r0, #9\r
+ cmp r9, r0\r
+ bne reg2_error_loop\r
+ movs r0, #10\r
+ cmp r10, r0\r
+ bne reg2_error_loop\r
+ movs r0, #11\r
+ cmp r11, r0\r
+ bne reg2_error_loop\r
+ movs r0, #12\r
+ cmp r12, r0\r
+ bne reg2_error_loop\r
+\r
+ ;/* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ ;/* Start again. */\r
+ movs r0, #10\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ ;/* If this line is hit then there was an error in a core register value.\r
+ ;The loop ensures the loop counter stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+ ENDP\r
+\r
+ END\r
--- /dev/null
+;*****************************************************************************/\r
+; * @file startup_XMC1300.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC1300 Device Series\r
+; * @version V1.00\r
+; * @date 21. Jan. 2013\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+; <h> Clock system handling by SSW\r
+; <h> CLK_VAL1 Configuration\r
+; <o0.0..7> FDIV Fractional Divider Selection\r
+; <o0.8..15> IDIV Divider Selection\r
+; <0=> Divider is bypassed\r
+; <1=> MCLK = 32 MHz\r
+; <2=> MCLK = 16 MHz\r
+; <3=> MCLK = 10.67 MHz\r
+; <4=> MCLK = 8 MHz\r
+; <254=> MCLK = 126 kHz\r
+; <255=> MCLK = 125.5 kHz\r
+; <o0.16> PCLKSEL PCLK Clock Select\r
+; <0=> PCLK = MCLK\r
+; <1=> PCLK = 2 x MCLK\r
+; <o0.17..19> RTCCLKSEL RTC Clock Select\r
+; <0=> 32.768kHz standby clock\r
+; <1=> 32.768kHz external clock from ERU0.IOUT0\r
+; <2=> 32.768kHz external clock from ACMP0.OUT\r
+; <3=> 32.768kHz external clock from ACMP1.OUT\r
+; <4=> 32.768kHz external clock from ACMP2.OUT\r
+; <5=> Reserved\r
+; <6=> Reserved\r
+; <7=> Reserved\r
+; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
+; </h>\r
+CLK_VAL1_Val EQU 0x00000100 ; 0xF0000000\r
+\r
+; <h> CLK_VAL2 Configuration\r
+; <o0.0> disable VADC and SHS Gating\r
+; <o0.1> disable CCU80 Gating\r
+; <o0.2> disable CCU40 Gating\r
+; <o0.3> disable USIC0 Gating\r
+; <o0.4> disable BCCU0 Gating\r
+; <o0.5> disable LEDTS0 Gating\r
+; <o0.6> disable LEDTS1 Gating\r
+; <o0.7> disable POSIF0 Gating\r
+; <o0.8> disable MATH Gating\r
+; <o0.9> disable WDT Gating\r
+; <o0.10> disable RTC Gating\r
+; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
+; </h>\r
+CLK_VAL2_Val EQU 0x00000000 ; 0xF0000000\r
+; </h>\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table Mapped to Address 0 at Reset\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+\r
+\r
+__Vectors\r
+ DCD __initial_sp ;* Top of Stack\r
+ DCD Reset_Handler ;* Reset Handler\r
+ DCD 0 ;* Not used\r
+ DCD 0 ;* Not Used\r
+ DCD CLK_VAL1_Val ;* CLK_VAL1\r
+ DCD CLK_VAL2_Val ;* CLK_VAL2\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
+\r
+\r
+;* ================== START OF VECTOR ROUTINES ============================== */\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;* Reset Handler\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
+ LDR R0, =__initial_sp\r
+ MOV SP, R0\r
+\r
+ ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
+ ; The real veneers will be copied later from the scatter loader before reaching main.\r
+ ; This init code should handle an exception before the real veneers are copied.\r
+SRAM_BASE EQU 0x20000000\r
+VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
+\r
+ LDR R1, =SRAM_BASE\r
+ LDR R2, =VENEER_INIT_CODE \r
+ MOVS R0, #48 ; Veneer 0..47\r
+Init_Veneers\r
+ STR R2, [R1]\r
+ ADDS R1, #4\r
+ SUBS R0, R0, #1\r
+ BNE Init_Veneers\r
+\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+\r
+\r
+ ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ; weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+\r
+ ALIGN\r
+ ENDP\r
+\r
+;* ========================================================================== */\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
+;* Default exception Handlers - Users may override this default functionality\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler\\r
+ PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler\\r
+ PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler\\r
+ PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+;* IRQ Handlers\r
+\r
+Default_Handler PROC\r
+ EXPORT SCU_0_IRQHandler [WEAK]\r
+ EXPORT SCU_1_IRQHandler [WEAK]\r
+ EXPORT SCU_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_0_IRQHandler [WEAK]\r
+ EXPORT ERU0_1_IRQHandler [WEAK]\r
+ EXPORT ERU0_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_3_IRQHandler [WEAK]\r
+ EXPORT MATH0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_1_IRQHandler [WEAK]\r
+ EXPORT USIC0_2_IRQHandler [WEAK]\r
+ EXPORT USIC0_3_IRQHandler [WEAK]\r
+ EXPORT USIC0_4_IRQHandler [WEAK]\r
+ EXPORT USIC0_5_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_0_IRQHandler [WEAK]\r
+ EXPORT CCU40_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_2_IRQHandler [WEAK]\r
+ EXPORT CCU40_3_IRQHandler [WEAK]\r
+ EXPORT CCU80_0_IRQHandler [WEAK]\r
+ EXPORT CCU80_1_IRQHandler [WEAK]\r
+ EXPORT POSIF0_0_IRQHandler [WEAK]\r
+ EXPORT POSIF0_1_IRQHandler [WEAK]\r
+ EXPORT LEDTS0_0_IRQHandler [WEAK]\r
+ EXPORT LEDTS1_0_IRQHandler [WEAK]\r
+ EXPORT BCCU0_0_IRQHandler [WEAK]\r
+\r
+SCU_0_IRQHandler\r
+SCU_1_IRQHandler\r
+SCU_2_IRQHandler\r
+ERU0_0_IRQHandler\r
+ERU0_1_IRQHandler\r
+ERU0_2_IRQHandler\r
+ERU0_3_IRQHandler\r
+MATH0_0_IRQHandler\r
+USIC0_0_IRQHandler\r
+USIC0_1_IRQHandler\r
+USIC0_2_IRQHandler\r
+USIC0_3_IRQHandler\r
+USIC0_4_IRQHandler\r
+USIC0_5_IRQHandler\r
+VADC0_C0_0_IRQHandler\r
+VADC0_C0_1_IRQHandler\r
+VADC0_G0_0_IRQHandler\r
+VADC0_G0_1_IRQHandler\r
+VADC0_G1_0_IRQHandler\r
+VADC0_G1_1_IRQHandler\r
+CCU40_0_IRQHandler\r
+CCU40_1_IRQHandler\r
+CCU40_2_IRQHandler\r
+CCU40_3_IRQHandler\r
+CCU80_0_IRQHandler\r
+CCU80_1_IRQHandler\r
+POSIF0_0_IRQHandler\r
+POSIF0_1_IRQHandler\r
+LEDTS0_0_IRQHandler\r
+LEDTS1_0_IRQHandler\r
+BCCU0_0_IRQHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowClkInitByStartup Handler */\r
+AllowClkInitByStartup PROC\r
+ EXPORT AllowClkInitByStartup [WEAK]\r
+ MOVS R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
+; Veneers are located to fix SRAM Address 0x2000'0000\r
+ AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
+\r
+; Each Veneer has exactly a lengs of 4 Byte\r
+\r
+ MACRO\r
+ STAYHERE $IrqNumber\r
+ LDR R0, =$IrqNumber\r
+ B .\r
+ MEND\r
+\r
+ MACRO\r
+ JUMPTO $Handler\r
+ LDR R0, =$Handler\r
+ BX R0\r
+ MEND\r
+\r
+ STAYHERE 0x0 ;* Reserved\r
+ STAYHERE 0x1 ;* Reserved \r
+ STAYHERE 0x2 ;* Reserved \r
+ JUMPTO HardFault_Handler ;* HardFault Veneer \r
+ STAYHERE 0x4 ;* Reserved \r
+ STAYHERE 0x5 ;* Reserved \r
+ STAYHERE 0x6 ;* Reserved \r
+ STAYHERE 0x7 ;* Reserved \r
+ STAYHERE 0x8 ;* Reserved \r
+ STAYHERE 0x9 ;* Reserved \r
+ STAYHERE 0xA ;* Reserved\r
+ JUMPTO SVC_Handler ;* SVC Veneer \r
+ STAYHERE 0xC ;* Reserved\r
+ STAYHERE 0xD ;* Reserved\r
+ JUMPTO PendSV_Handler ;* PendSV Veneer \r
+ JUMPTO SysTick_Handler ;* SysTick Veneer \r
+ JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
+ JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
+ JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
+ JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
+ JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
+ JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
+ JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
+ JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
+ STAYHERE 0x18 ;* Reserved\r
+ JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
+ JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
+ JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
+ JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
+ JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
+ JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
+ JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
+ JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
+ JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
+ JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
+ JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
+ JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
+ JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
+ JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
+ JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
+ JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
+ JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
+ JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
+ JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
+ JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
+ JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
+\r
+ ALIGN\r
+\r
+;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
+\r
+ END\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1100.c\r
+ * @brief Device specific initialization for the XMC1100-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ */\r
+\r
+#include "system_XMC1100.h"\r
+#include <XMC1100.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1200.c\r
+ * @brief Device specific initialization for the XMC1200-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ */\r
+\r
+#include "System_XMC1200.h"\r
+#include <XMC1200.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1300.c\r
+ * @brief Device specific initialization for the XMC1300-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * ************************** Change history *********************************\r
+ * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_\r
+ */\r
+\r
+#include "system_XMC1300.h"\r
+#include <XMC1300.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/*-----------------------------------------------------------\r
+ * Simple GPIO (parallel port) IO routines.\r
+ *-----------------------------------------------------------*/\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Hardware includes. */\r
+#include <XMC1200.h>\r
+\r
+/* Standard demo include. */\r
+#include "partest.h"\r
+\r
+/* The port bits on which LEDs are connected. */\r
+static const unsigned long ulLEDBits[] = \r
+{ \r
+ 1UL << 0, /* P0.0 */\r
+ 1UL << 2, /* P0.2 */\r
+ 1UL << 5, /* P0.5 */\r
+ 1UL << 6, /* P0.6 */\r
+ 1UL << 7 /* P0.7 */\r
+};\r
+\r
+#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) )\r
+\r
+/* Shift the LED bit into the correct position within the POW register to\r
+perform the desired operation. */\r
+#define partstON_SHIFT ( 16UL )\r
+#define partstOFF_SHIFT ( 0UL )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestInitialise( void )\r
+{\r
+ /* Configure relevant port P0 to push pull output to drive LEDs. */\r
+ \r
+ /* P0.0 */\r
+ PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) );\r
+ PORT0->IOCR0 |= ( 0x80UL << 0 );\r
+ vParTestSetLED( 0, pdFALSE );\r
+\r
+ /* P0.2 */\r
+ PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) );\r
+ PORT0->IOCR0 |= ( 0x80UL << 16 );\r
+ vParTestSetLED( 1, pdFALSE );\r
+\r
+ /* P0.5 */\r
+ PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) );\r
+ PORT0->IOCR4 |= ( 0x80UL << 8 );\r
+ vParTestSetLED( 2, pdFALSE );\r
+\r
+ /* P0.6 */\r
+ PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) );\r
+ PORT0->IOCR4 |= ( 0x80UL << 16 );\r
+ vParTestSetLED( 3, pdFALSE );\r
+\r
+ /* P0.7 */\r
+ PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) );\r
+ PORT0->IOCR4 |= ( 0x80UL << 24 );\r
+ vParTestSetLED( 4, pdFALSE );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue )\r
+{\r
+ if( ulLED < partstNUM_LEDS )\r
+ {\r
+ if( xValue == pdTRUE )\r
+ {\r
+ /* Turn the LED on. */ \r
+ PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT );\r
+ }\r
+ else\r
+ {\r
+ /* Turn the LED off. */ \r
+ PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vParTestToggleLED( unsigned long ulLED )\r
+{\r
+ if( ulLED < partstNUM_LEDS )\r
+ {\r
+ /* Setting both the ON and OFF bits simultaneously results in the bit\r
+ being toggled. */\r
+ PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>C-SPY</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>25</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CInput</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCVariant</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>MemOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MemFile</name>\r
+ <state>$TOOLKIT_DIR$\CONFIG\debugger\Infineon\xmc1200.ddf</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToEnable</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>RunToName</name>\r
+ <state>main</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDDFArgumentProducer</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadSuppressDownload</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadVerifyAll</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProductVersion</name>\r
+ <state>6.50.2.4581</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDynDriverList</name>\r
+ <state>JLINK_ID</state>\r
+ </option>\r
+ <option>\r
+ <name>OCLastSavedByProductVersion</name>\r
+ <state>6.60.1.5099</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDownloadAttachToProgram</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>UseFlashLoader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CLowLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCBE8Slave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacFile2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CDevice</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>FlashLoadersV3</name>\r
+ <state>$TOOLKIT_DIR$\config\flashloader\Infineon\FlashXMC1200.board</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesSuppressCheck3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesPath3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OverrideDefFlashBoard</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesOffset3</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse1</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCImagesUse3</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDeviceConfigMacroFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDebuggerExtraOption</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCAllMTBOptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ARMSIM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCSimDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimEnablePSP</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspOverrideConfig</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCSimPspConfigFile</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ANGEL_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCAngelHeartbeat</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommunication</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommBaud</name>\r
+ <version>0</version>\r
+ <state>3</state>\r
+ </option>\r
+ <option>\r
+ <name>CAngelCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ANGELTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoAngelLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AngelLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CMSISDAP_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CMSISDAPMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>GDBSERVER_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IARROM_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRomLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRomCommBaud</name>\r
+ <version>0</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>IJET_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCIarProbeScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetResetList</name>\r
+ <version>1</version>\r
+ <state>10</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDuration</name>\r
+ <state>300</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetHWResetDelay</name>\r
+ <state>200</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerFromProbe</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetPowerRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTargetEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetJtagSpeedList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProtocolRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPin</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSwoPrescalerList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetRestoreBreakpointsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetUpdateBreakpointsEdit</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>RDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchCHKERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeCfgOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCProbeConfig</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>IjetProbeConfigRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetMultiCPUNumber</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IjetSelectedCPUBehaviour</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ICpuName</name>\r
+ <state></state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>JLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>15</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>JLinkSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkHWResetDelay</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>JLinkInitialSpeed</name>\r
+ <state>32</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDoJlinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCScanChainNonARMDevices</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkIRLength</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkCommRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkSpeedRadioV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCUSBDevice</name>\r
+ <version>1</version>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceRadio</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkResetList</name>\r
+ <version>6</version>\r
+ <state>7</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCORERESET</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchMMERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchNOCPERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchCHRERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchSTATERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchBUSERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchINTERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchHARDERR</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCatchDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkScriptFile</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkUsbSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCTcpIpAlt</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJLinkTcpIpSerialNo</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkTraceSourceDummy</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCJLinkDeviceName</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>LMIFTDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>LmiftdiSpeed</name>\r
+ <state>500</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiDoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiftdiLogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLmiFtdiInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>MACRAIGOR_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>3</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>jtag</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuSpeed</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TCPIP</name>\r
+ <state>aaa.bbb.ccc.ddd</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>DoEmuMultiTarget</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuMultiTarget</name>\r
+ <state>0@ARM7TDMI</state>\r
+ </option>\r
+ <option>\r
+ <name>EmuHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommBaud</name>\r
+ <version>0</version>\r
+ <state>4</state>\r
+ </option>\r
+ <option>\r
+ <name>CEmuCommPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>jtago</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>UnusedAddr</name>\r
+ <state>0x00800000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorHWResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagBreakpointRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagDoUpdateBreakpoints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJTagUpdateBreakpoints</name>\r
+ <state>_call_main</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMacraigorInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>PEMICRO_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCPEMicroAttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroInterfaceList</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroResetDelay</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroJtagSpeed</name>\r
+ <state>#UNINITIALIZED#</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroShowSettings</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroUSBDevice</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroSerialPort</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCJPEMicroTCPIPAutoScanNetwork</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroTCPIP</name>\r
+ <state>10.0.0.1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPEMicroCommCmdLineProducer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>RDI_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CRDIDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CRDILogFileEdit</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDIHWReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchReset</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchUndef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchSWI</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchData</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchPrefetch</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchIRQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRDICatchFIQ</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>STLINK_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceRadio</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkInterfaceCmdLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSTLinkResetList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCpuClockEdit</name>\r
+ <state>72.0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockAuto</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSwoClockEdit</name>\r
+ <state>2000</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>THIRDPARTY_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>0</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CThirdPartyDriverDll</name>\r
+ <state>###Uninitialized###</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CThirdPartyLogFileEditB</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>XDS100_ID</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>2</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OCDriverInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OCXDS100AttachSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackageOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>TIPackage</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCXds100InterfaceList</name>\r
+ <version>1</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>BoardFile</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>DoLogfile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>LogFile</name>\r
+ <state>$PROJ_DIR$\cspycomm.log</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <debuggerPlugins>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\middleware\HCCWare\HCCWare.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\AVIX\AVIX.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\MQX\MQXRtosPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB6_Plugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>\r
+ <loadFlag>1</loadFlag>\r
+ </plugin>\r
+ <plugin>\r
+ <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>\r
+ <loadFlag>0</loadFlag>\r
+ </plugin>\r
+ </debuggerPlugins>\r
+ </configuration>\r
+</project>\r
+\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<project>\r
+ <fileVersion>2</fileVersion>\r
+ <configuration>\r
+ <name>Debug</name>\r
+ <toolchain>\r
+ <name>ARM</name>\r
+ </toolchain>\r
+ <debug>1</debug>\r
+ <settings>\r
+ <name>General</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <version>22</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>ExePath</name>\r
+ <state>Debug\Exe</state>\r
+ </option>\r
+ <option>\r
+ <name>ObjPath</name>\r
+ <state>Debug\Obj</state>\r
+ </option>\r
+ <option>\r
+ <name>ListPath</name>\r
+ <state>Debug\List</state>\r
+ </option>\r
+ <option>\r
+ <name>Variant</name>\r
+ <version>20</version>\r
+ <state>34</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianMode</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input variant</name>\r
+ <version>3</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Input description</name>\r
+ <state>Automatic choice of formatter.</state>\r
+ </option>\r
+ <option>\r
+ <name>Output variant</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>Output description</name>\r
+ <state>Automatic choice of formatter.</state>\r
+ </option>\r
+ <option>\r
+ <name>GOutputBinary</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>FPU</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGCoreOrChip</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelect</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibSelectSlave</name>\r
+ <version>0</version>\r
+ <state>2</state>\r
+ </option>\r
+ <option>\r
+ <name>RTDescription</name>\r
+ <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>\r
+ </option>\r
+ <option>\r
+ <name>OGProductVersion</name>\r
+ <state>6.50.2.4581</state>\r
+ </option>\r
+ <option>\r
+ <name>OGLastSavedByProductVersion</name>\r
+ <state>6.60.1.5099</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralEnableMisra</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVerbose</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGChipSelectEditMenu</name>\r
+ <state>xmc1200 Infineon xmc1200</state>\r
+ </option>\r
+ <option>\r
+ <name>GenLowLevelInterface</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>GEndianModeBE</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OGBufferedTerminalOutput</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GenStdoutInterface</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraVer</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GeneralMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>RTConfigPath2</name>\r
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>\r
+ </option>\r
+ <option>\r
+ <name>GFPUCoreSlave</name>\r
+ <version>20</version>\r
+ <state>34</state>\r
+ </option>\r
+ <option>\r
+ <name>GBECoreSlave</name>\r
+ <version>20</version>\r
+ <state>34</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsis</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OGUseCmsisDspLib</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>GRuntimeLibThreads</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>ICCARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>29</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>CCDefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocComments</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPreprocLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMnemonics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListCMessages</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssFile</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCListAssSource</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCEnableRemarks</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagSuppress</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagRemark</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarning</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagError</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCAllowList</name>\r
+ <version>1</version>\r
+ <state>0000000</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDebugInfo</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IEndianMode</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptionsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IExtraOptions</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CCLangConformance</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCSignedPlainChar</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCRequirePrototypes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCDiagWarnAreErr</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCompilerRuntimeInfo</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>CCLibConfigHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>PreInclude</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCIncludePath2</name>\r
+ <state>$PROJ_DIR$\.</state>\r
+ <state>$PROJ_DIR$\CMSIS</state>\r
+ <state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\portable\IAR\ARM_CM0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCStdIncCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCCodeSection</name>\r
+ <state>.text</state>\r
+ </option>\r
+ <option>\r
+ <name>IInterwork2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IProcessorMode2</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevel</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptStrategy</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptLevelSlave</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules98</name>\r
+ <version>0</version>\r
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CompilerMisraRules04</name>\r
+ <version>0</version>\r
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRopi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndRwpi</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCPosIndNoDynInit</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccLang</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccAllowVLA</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppDialect</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccExceptions</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccRTTI</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccStaticDestr</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCppInlineSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>IccCmsis</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>IccFloatSemantics</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCOptimizationNoSizeConstraints</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>CCNoLiteralPool</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>AARM</name>\r
+ <archiveVersion>2</archiveVersion>\r
+ <data>\r
+ <version>9</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>AObjPrefix</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AEndian</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>ACaseSensitivity</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacroChars</name>\r
+ <version>0</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnWhat</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnOne</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange1</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AWarnRange2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>ADebug</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AltRegisterNames</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ADefines</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AList</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AListHeader</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AListing</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>Includes</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacDefs</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExps</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>MacExec</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OnlyAssed</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>MultiLine</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLengthCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>PageLength</name>\r
+ <state>80</state>\r
+ </option>\r
+ <option>\r
+ <name>TabSpacing</name>\r
+ <state>8</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRef</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDefines</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefInternal</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AXRefDual</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AFpuProcessor</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>AOutputFile</name>\r
+ <state>$FILE_BNAME$.o</state>\r
+ </option>\r
+ <option>\r
+ <name>AMultibyteSupport</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsCheck</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>ALimitErrorsEdit</name>\r
+ <state>100</state>\r
+ </option>\r
+ <option>\r
+ <name>AIgnoreStdInclude</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AUserIncludes</name>\r
+ <state>$PROJ_DIR$.\</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsCheckV2</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>AExtraOptionsV2</name>\r
+ <state></state>\r
+ </option>\r
+ <option>\r
+ <name>AsmNoLiteralPool</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>OBJCOPY</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data>\r
+ <version>1</version>\r
+ <wantNonLocal>1</wantNonLocal>\r
+ <debug>1</debug>\r
+ <option>\r
+ <name>OOCOutputFormat</name>\r
+ <version>2</version>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OCOutputOverride</name>\r
+ <state>0</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCOutputFile</name>\r
+ <state>RTOSDemo.srec</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCCommandLineProducer</name>\r
+ <state>1</state>\r
+ </option>\r
+ <option>\r
+ <name>OOCObjCopyEnable</name>\r
+ <state>0</state>\r
+ </option>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>CUSTOM</name>\r
+ <archiveVersion>3</archiveVersion>\r
+ <data>\r
+ <extensions></extensions>\r
+ <cmdline></cmdline>\r
+ </data>\r
+ </settings>\r
+ <settings>\r
+ <name>BICOMP</name>\r
+ <archiveVersion>0</archiveVersion>\r
+ <data/>\r
+ </settings>\r
+ <settings>\r
+ <name>BUILDACTION</name>\r
+ <archiveVersion>1</archiveVersion>\r
+ <data>\r
+ <prebuild></prebuild>\r
+ <postbuild></postbuild>\r
+ </data>\r
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--- /dev/null
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--- /dev/null
+<html>\r
+<body>\r
+<pre>\r
+<h1>µVision Build Log</h1>\r
+<h2>Project:</h2>\r
+C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil\RTOSDemo.uvproj\r
+Project File Date: 08/24/2013\r
+\r
+<h2>Output:</h2>\r
+Build target 'XMC1300'\r
+assembling startup_XMC1300.s...\r
+compiling timers.c...\r
+compiling list.c...\r
+compiling queue.c...\r
+compiling tasks.c...\r
+compiling port.c...\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(101): warning: #1207-D: attribute "naked" ignored\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(103): warning: #1207-D: attribute "naked" ignored\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(108): warning: #1207-D: attribute "naked" ignored\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(155): warning: #1267-D: Implicit physical register R3 should be defined as a variable\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error: #1086: Operand is wrong type\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(155): error: #114: label "pxCurrentTCBConst2" was referenced but not defined\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(168): warning: #1267-D: Implicit physical register R0 should be defined as a variable\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning: #1267-D: Implicit physical register R0 should be defined as a variable\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): warning: #1267-D: Implicit physical register R3 should be defined as a variable\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error: #1086: Operand is wrong type\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(278): error: #114: label "pxCurrentTCBConst" was referenced but not defined\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(306): error: #20: identifier "SystemCoreClock" is undefined\r
+compiling ParTest.c...\r
+compiling main.c...\r
+compiling main-blinky.c...\r
+".\RTOSDemo.axf" - 5 Errors, 7 Warning(s).\r
+Target not created\r
+Clean started: Project: 'RTOSDemo'\r
+ deleting intermediate output files for target 'XMC1300'\r
+Build target 'XMC1300'\r
+assembling startup_XMC1300.s...\r
+compiling timers.c...\r
+compiling list.c...\r
+compiling queue.c...\r
+compiling tasks.c...\r
+compiling port.c...\r
+..\..\Source\portable\RVDS\ARM_CM0\port.c(305): error: #20: identifier "SystemCoreClock" is undefined\r
+compiling ParTest.c...\r
+compiling main.c...\r
+compiling main-blinky.c...\r
+".\Output\RTOSDemo.axf" - 1 Errors, 0 Warning(s).\r
+Target not created\r
--- /dev/null
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+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>1</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>0</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x10001000</StartAddress>
+ <Size>0x32000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x10001000</StartAddress>
+ <Size>0x32000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x10001000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC1200.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_XMC1300.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\Keil_Specific\startup_XMC1300.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS source</GroupName>
+ <Files>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM0\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demo App Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>main-blinky.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main-blinky.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>main-full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main-full.c</FilePath>
+ </File>
+ <File>
+ <FileName>ParTest_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ParTest_XMC1200.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>RegTest_Keil.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\Keil_Specific\RegTest_Keil.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common Demo Tasks</GroupName>
+ <Files>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>XMC1200</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>XMC1200-200</Device>
+ <Vendor>Infineon</Vendor>
+ <Cpu>IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile>"STARTUP\Infineon\XMC1200\startup_XMC1200.s" ("Infineon XMC1200 Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000)</FlashDriverDll>
+ <DeviceId>6777</DeviceId>
+ <RegisterFile>XMC1200.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>SFD\Infineon\XMC1200\xmc1200.SFR</SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>Infineon\XMC1200\</RegisterFilePath>
+ <DBRegisterFilePath>Infineon\XMC1200\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\Output\</OutputDirectory>
+ <OutputName>RTOSDemo</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>1</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>7</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>Segger\JL2CM3.dll</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4100</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>Segger\JL2CM3.dll</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x10001000</StartAddress>
+ <Size>0x32000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x10001000</StartAddress>
+ <Size>0x32000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls>--c99</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>.;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;.\CMSIS</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x10001000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile>.\Output\RTOSDemo.sct</ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>System</GroupName>
+ <Files>
+ <File>
+ <FileName>system_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_XMC1200.c</FilePath>
+ </File>
+ <File>
+ <FileName>startup_XMC1300.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\Keil_Specific\startup_XMC1300.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>FreeRTOS source</GroupName>
+ <Files>
+ <File>
+ <FileName>timers.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\timers.c</FilePath>
+ </File>
+ <File>
+ <FileName>list.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\list.c</FilePath>
+ </File>
+ <File>
+ <FileName>queue.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\queue.c</FilePath>
+ </File>
+ <File>
+ <FileName>tasks.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\tasks.c</FilePath>
+ </File>
+ <File>
+ <FileName>port.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\RVDS\ARM_CM0\port.c</FilePath>
+ </File>
+ <File>
+ <FileName>heap_4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\Source\portable\MemMang\heap_4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Demo App Source</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main.c</FilePath>
+ </File>
+ <File>
+ <FileName>main-blinky.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main-blinky.c</FilePath>
+ </File>
+ <File>
+ <FileName>FreeRTOSConfig.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\FreeRTOSConfig.h</FilePath>
+ </File>
+ <File>
+ <FileName>main-full.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\main-full.c</FilePath>
+ </File>
+ <File>
+ <FileName>ParTest_XMC1200.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\ParTest_XMC1200.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>RegTest_Keil.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\Keil_Specific\RegTest_Keil.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Common Demo Tasks</GroupName>
+ <Files>
+ <File>
+ <FileName>dynamic.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\dynamic.c</FilePath>
+ </File>
+ <File>
+ <FileName>recmutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\recmutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>blocktim.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\blocktim.c</FilePath>
+ </File>
+ <File>
+ <FileName>countsem.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\Common\Minimal\countsem.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
--- /dev/null
+\r
+/****************************************************************************************************//**\r
+ * @file XMC1200.h\r
+ *\r
+ * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for\r
+ * XMC1200 from Infineon.\r
+ *\r
+ * @version V1.0.6 (Reference Manual v1.0)\r
+ * @date 26. March 2013\r
+ *\r
+ * @note Generated with SVDConv V2.78b \r
+ * from CMSIS SVD File 'XMC1200_Processed_SVD.xml' Version 1.0.6 (Reference Manual v1.0),\r
+ *******************************************************************************************************/\r
+\r
+\r
+\r
+/** @addtogroup Infineon\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup XMC1200\r
+ * @{\r
+ */\r
+\r
+#ifndef XMC1200_H\r
+#define XMC1200_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+\r
+/* ------------------------- Interrupt Number Definition ------------------------ */\r
+\r
+typedef enum {\r
+/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */\r
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */\r
+ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */\r
+ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */\r
+ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */\r
+ SysTick_IRQn = -1, /*!< 15 System Tick Timer */\r
+/* --------------------- XMC1200 Specific Interrupt Numbers --------------------- */\r
+ SCU_0_IRQn = 0, /*!< SCU SR0 Interrupt */\r
+ SCU_1_IRQn = 1, /*!< SCU SR1 Interrupt */\r
+ SCU_2_IRQn = 2, /*!< SCU SR2 Interrupt */\r
+ ERU0_0_IRQn = 3, /*!< ERU0 SR0 Interrupt */\r
+ ERU0_1_IRQn = 4, /*!< ERU0 SR1 Interrupt */\r
+ ERU0_2_IRQn = 5, /*!< ERU0 SR2 Interrupt */\r
+ ERU0_3_IRQn = 6, /*!< ERU0 SR3 Interrupt */\r
+ \r
+ USIC0_0_IRQn = 9, /*!< USIC SR0 Interrupt */\r
+ USIC0_1_IRQn = 10, /*!< USIC SR1 Interrupt */\r
+ USIC0_2_IRQn = 11, /*!< USIC SR2 Interrupt */\r
+ USIC0_3_IRQn = 12, /*!< USIC SR3 Interrupt */\r
+ USIC0_4_IRQn = 13, /*!< USIC SR4 Interrupt */\r
+ USIC0_5_IRQn = 14, /*!< USIC SR5 Interrupt */\r
+ \r
+ VADC0_C0_0_IRQn = 15, /*!< VADC SR0 Interrupt */\r
+ VADC0_C0_1_IRQn = 16, /*!< VADC SR1 Interrupt */\r
+ VADC0_G0_0_IRQn = 17, /*!< VADC SR2 Interrupt */\r
+ VADC0_G0_1_IRQn = 18, /*!< VADC SR3 Interrupt */\r
+ VADC0_G1_0_IRQn = 19, /*!< VADC SR4 Interrupt */\r
+ VADC0_G1_1_IRQn = 20, /*!< VADC SR5 Interrupt */\r
+ \r
+ CCU40_0_IRQn = 21, /*!< CCU40 SR0 Interrupt */\r
+ CCU40_1_IRQn = 22, /*!< CCU40 SR1 Interrupt */\r
+ CCU40_2_IRQn = 23, /*!< CCU40 SR2 Interrupt */\r
+ CCU40_3_IRQn = 24, /*!< CCU40 SR3 Interrupt */\r
+ \r
+ LEDTS0_0_IRQn = 29, /*!< LEDTS0 SR0 Interrupt */\r
+ LEDTS1_0_IRQn = 30, /*!< LEDTS1 SR0 Interrupt */\r
+ \r
+ BCCU0_0_IRQn = 31, /*!< BCCU0 SR0 Interrupt */\r
+} IRQn_Type;\r
+\r
+\r
+/** @addtogroup Configuration_of_CMSIS\r
+ * @{\r
+ */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Processor and Core Peripheral Section ================ */\r
+/* ================================================================================ */\r
+\r
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */\r
+#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */\r
+#define __MPU_PRESENT 0 /*!< MPU present or not */\r
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+/** @} */ /* End of group Configuration_of_CMSIS */\r
+\r
+#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */\r
+#include "system_XMC1200.h" /*!< XMC1200 System */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Device Specific Peripheral Section ================ */\r
+/* ================================================================================ */\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \\r
+ ((uint32_t)mask)) | \\r
+ (reg & ((uint32_t)~((uint32_t)mask)))\r
+\r
+/* Macro to modify desired bitfields of a register */\r
+#define WR_REG_SIZE(reg, mask, pos, val, size) { \\r
+uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \\r
+uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \\r
+uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \\r
+uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \\r
+reg = (uint##size##_t) (VAL2 | VAL4);\\r
+}\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)\r
+\r
+/** Macro to read bitfields from a register */\r
+#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \\r
+ (uint32_t)mask) >> pos) )\r
+\r
+/** Macro to set a bit in register */\r
+#define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))\r
+\r
+/** Macro to clear a bit in register */\r
+#define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler Definition ----------------------------------\r
+* ==========================================================================\r
+*/\r
+#define IRQ_Hdlr_0 SCU_0_IRQHandler\r
+#define IRQ_Hdlr_1 SCU_1_IRQHandler\r
+#define IRQ_Hdlr_2 SCU_2_IRQHandler\r
+#define IRQ_Hdlr_3 ERU0_0_IRQHandler\r
+#define IRQ_Hdlr_4 ERU0_1_IRQHandler\r
+#define IRQ_Hdlr_5 ERU0_2_IRQHandler\r
+#define IRQ_Hdlr_6 ERU0_3_IRQHandler\r
+\r
+#define IRQ_Hdlr_9 USIC0_0_IRQHandler\r
+#define IRQ_Hdlr_10 USIC0_1_IRQHandler\r
+#define IRQ_Hdlr_11 USIC0_2_IRQHandler\r
+#define IRQ_Hdlr_12 USIC0_3_IRQHandler\r
+#define IRQ_Hdlr_13 USIC0_4_IRQHandler\r
+#define IRQ_Hdlr_14 USIC0_5_IRQHandler\r
+#define IRQ_Hdlr_15 VADC0_C0_0_IRQHandler\r
+#define IRQ_Hdlr_16 VADC0_C0_1_IRQHandler\r
+#define IRQ_Hdlr_17 VADC0_G0_0_IRQHandler\r
+#define IRQ_Hdlr_18 VADC0_G0_1_IRQHandler\r
+#define IRQ_Hdlr_19 VADC0_G1_0_IRQHandler\r
+#define IRQ_Hdlr_20 VADC0_G1_1_IRQHandler\r
+#define IRQ_Hdlr_21 CCU40_0_IRQHandler\r
+#define IRQ_Hdlr_22 CCU40_1_IRQHandler\r
+#define IRQ_Hdlr_23 CCU40_2_IRQHandler\r
+#define IRQ_Hdlr_24 CCU40_3_IRQHandler\r
+#define IRQ_Hdlr_29 LEDTS0_0_IRQHandler\r
+#define IRQ_Hdlr_30 LEDTS1_0_IRQHandler\r
+#define IRQ_Hdlr_31 BCCU0_0_IRQHandler\r
+\r
+/*\r
+* ==========================================================================\r
+* ---------- Interrupt Handler retrieval macro -----------------------------\r
+* ==========================================================================\r
+*/\r
+#define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N\r
+\r
+\r
+/** @addtogroup Device_Peripheral_Registers\r
+ * @{\r
+ */\r
+\r
+\r
+/* ------------------- Start of section using anonymous unions ------------------ */\r
+#if defined(__CC_ARM)\r
+ #pragma push\r
+ #pragma anon_unions\r
+#elif defined(__ICCARM__)\r
+ #pragma language=extended\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+/* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+ #pragma warning 586\r
+#else\r
+ #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PPB ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Cortex-M0 Private Peripheral Block (PPB)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0xE000E000) PPB Structure */\r
+ __I uint32_t RESERVED0[4];\r
+ __IO uint32_t SYST_CSR; /*!< (@ 0xE000E010) SysTick Control and Status Register */\r
+ __IO uint32_t SYST_RVR; /*!< (@ 0xE000E014) SysTick Reload Value Register */\r
+ __IO uint32_t SYST_CVR; /*!< (@ 0xE000E018) SysTick Current Value Register */\r
+ __I uint32_t SYST_CALIB; /*!< (@ 0xE000E01C) SysTick Calibration Value Register */\r
+ __I uint32_t RESERVED1[56];\r
+ __IO uint32_t NVIC_ISER; /*!< (@ 0xE000E100) Interrupt Set-enable Register */\r
+ __I uint32_t RESERVED2[31];\r
+ __IO uint32_t NVIC_ICER; /*!< (@ 0xE000E180) IInterrupt Clear-enable Register */\r
+ __I uint32_t RESERVED3[31];\r
+ __IO uint32_t NVIC_ISPR; /*!< (@ 0xE000E200) Interrupt Set-pending Register */\r
+ __I uint32_t RESERVED4[31];\r
+ __IO uint32_t NVIC_ICPR; /*!< (@ 0xE000E280) Interrupt Clear-pending Register */\r
+ __I uint32_t RESERVED5[95];\r
+ __IO uint32_t NVIC_IPR0; /*!< (@ 0xE000E400) Interrupt Priority Register 0 */\r
+ __IO uint32_t NVIC_IPR1; /*!< (@ 0xE000E404) Interrupt Priority Register 1 */\r
+ __IO uint32_t NVIC_IPR2; /*!< (@ 0xE000E408) Interrupt Priority Register 2 */\r
+ __IO uint32_t NVIC_IPR3; /*!< (@ 0xE000E40C) Interrupt Priority Register 3 */\r
+ __IO uint32_t NVIC_IPR4; /*!< (@ 0xE000E410) Interrupt Priority Register 4 */\r
+ __IO uint32_t NVIC_IPR5; /*!< (@ 0xE000E414) Interrupt Priority Register 5 */\r
+ __IO uint32_t NVIC_IPR6; /*!< (@ 0xE000E418) Interrupt Priority Register 6 */\r
+ __IO uint32_t NVIC_IPR7; /*!< (@ 0xE000E41C) Interrupt Priority Register 7 */\r
+ __I uint32_t RESERVED6[568];\r
+ __I uint32_t CPUID; /*!< (@ 0xE000ED00) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< (@ 0xE000ED04) Interrupt Control and State Register */\r
+ __I uint32_t RESERVED7;\r
+ __IO uint32_t AIRCR; /*!< (@ 0xE000ED0C) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< (@ 0xE000ED10) System Control Register */\r
+ __I uint32_t CCR; /*!< (@ 0xE000ED14) Configuration and Control Register */\r
+ __I uint32_t RESERVED8;\r
+ __IO uint32_t SHPR2; /*!< (@ 0xE000ED1C) System Handler Priority Register 2 */\r
+ __IO uint32_t SHPR3; /*!< (@ 0xE000ED20) System Handler Priority Register 3 */\r
+ __IO uint32_t SHCSR; /*!< (@ 0xE000ED24) System Handler Control and State Register */\r
+} PPB_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ ERU [ERU0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Event Request Unit 0 (ERU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010600) ERU Structure */\r
+ __IO uint32_t EXISEL; /*!< (@ 0x40010600) Event Input Select */\r
+ __I uint32_t RESERVED0[3];\r
+ __IO uint32_t EXICON[4]; /*!< (@ 0x40010610) Event Input Control */\r
+ __IO uint32_t EXOCON[4]; /*!< (@ 0x40010620) Event Output Trigger Control */\r
+} ERU_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PAU ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief PAU Unit (PAU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40000000) PAU Structure */\r
+ __I uint32_t RESERVED0[16];\r
+ __I uint32_t AVAIL0; /*!< (@ 0x40000040) Peripheral Availability Register 0 */\r
+ __I uint32_t AVAIL1; /*!< (@ 0x40000044) Peripheral Availability Register 1 */\r
+ __I uint32_t AVAIL2; /*!< (@ 0x40000048) Peripheral Availability Register 2 */\r
+ __I uint32_t RESERVED1[13];\r
+ __IO uint32_t PRIVDIS0; /*!< (@ 0x40000080) Peripheral Privilege Access Register 0 */\r
+ __IO uint32_t PRIVDIS1; /*!< (@ 0x40000084) Peripheral Privilege Access Register 1 */\r
+ __IO uint32_t PRIVDIS2; /*!< (@ 0x40000088) Peripheral Privilege Access Register 2 */\r
+ __I uint32_t RESERVED2[221];\r
+ __I uint32_t ROMSIZE; /*!< (@ 0x40000400) ROM Size Register */\r
+ __I uint32_t FLSIZE; /*!< (@ 0x40000404) Flash Size Register */\r
+ __I uint32_t RESERVED3[2];\r
+ __I uint32_t RAM0SIZE; /*!< (@ 0x40000410) RAM0 Size Register */\r
+} PAU_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ NVM ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief NVM Unit (NVM)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40050000) NVM Structure */\r
+ __I uint16_t NVMSTATUS; /*!< (@ 0x40050000) NVM Status Register */\r
+ __I uint16_t RESERVED0;\r
+ __IO uint16_t NVMPROG; /*!< (@ 0x40050004) NVM Programming Control Register */\r
+ __I uint16_t RESERVED1;\r
+ __IO uint16_t NVMCONF; /*!< (@ 0x40050008) NVM Configuration Register */\r
+} NVM_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ WDT ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Watch Dog Timer (WDT)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40020000) WDT Structure */\r
+ __I uint32_t ID; /*!< (@ 0x40020000) WDT Module ID Register */\r
+ __IO uint32_t CTR; /*!< (@ 0x40020004) WDT Control Register */\r
+ __O uint32_t SRV; /*!< (@ 0x40020008) WDT Service Register */\r
+ __I uint32_t TIM; /*!< (@ 0x4002000C) WDT Timer Register */\r
+ __IO uint32_t WLB; /*!< (@ 0x40020010) WDT Window Lower Bound Register */\r
+ __IO uint32_t WUB; /*!< (@ 0x40020014) WDT Window Upper Bound Register */\r
+ __I uint32_t WDTSTS; /*!< (@ 0x40020018) WDT Status Register */\r
+ __O uint32_t WDTCLR; /*!< (@ 0x4002001C) WDT Clear Register */\r
+} WDT_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ RTC ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Real Time Clock (RTC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010A00) RTC Structure */\r
+ __I uint32_t ID; /*!< (@ 0x40010A00) RTC Module ID Register */\r
+ __IO uint32_t CTR; /*!< (@ 0x40010A04) RTC Control Register */\r
+ __I uint32_t RAWSTAT; /*!< (@ 0x40010A08) RTC Raw Service Request Register */\r
+ __I uint32_t STSSR; /*!< (@ 0x40010A0C) RTC Service Request Status Register */\r
+ __IO uint32_t MSKSR; /*!< (@ 0x40010A10) RTC Service Request Mask Register */\r
+ __O uint32_t CLRSR; /*!< (@ 0x40010A14) RTC Clear Service Request Register */\r
+ __IO uint32_t ATIM0; /*!< (@ 0x40010A18) RTC Alarm Time Register 0 */\r
+ __IO uint32_t ATIM1; /*!< (@ 0x40010A1C) RTC Alarm Time Register 1 */\r
+ __IO uint32_t TIM0; /*!< (@ 0x40010A20) RTC Time Register 0 */\r
+ __IO uint32_t TIM1; /*!< (@ 0x40010A24) RTC Time Register 1 */\r
+} RTC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PRNG ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief PRNG Unit (PRNG)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48020000) PRNG Structure */\r
+ __IO uint16_t WORD; /*!< (@ 0x48020000) Pseudo RNG Word Register */\r
+ __I uint16_t RESERVED0;\r
+ __I uint16_t CHK; /*!< (@ 0x48020004) Pseudo RNG Status Check Register */\r
+ __I uint16_t RESERVED1[3];\r
+ __IO uint16_t CTRL; /*!< (@ 0x4802000C) Pseudo RNG Control Register */\r
+} PRNG_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ LEDTS [LEDTS0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief LED and Touch Sense Unit 0 (LEDTS)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x50020000) LEDTS Structure */\r
+ __I uint32_t ID; /*!< (@ 0x50020000) Module Identification Register */\r
+ __IO uint32_t GLOBCTL; /*!< (@ 0x50020004) Global Control Register */\r
+ __IO uint32_t FNCTL; /*!< (@ 0x50020008) Function Control Register */\r
+ __O uint32_t EVFR; /*!< (@ 0x5002000C) Event Flag Register */\r
+ __IO uint32_t TSVAL; /*!< (@ 0x50020010) Touch-sense TS-Counter Value */\r
+ __IO uint32_t LINE0; /*!< (@ 0x50020014) Line Pattern Register 0 */\r
+ __IO uint32_t LINE1; /*!< (@ 0x50020018) Line Pattern Register 1 */\r
+ __IO uint32_t LDCMP0; /*!< (@ 0x5002001C) LED Compare Register 0 */\r
+ __IO uint32_t LDCMP1; /*!< (@ 0x50020020) LED Compare Register 1 */\r
+ __IO uint32_t TSCMP0; /*!< (@ 0x50020024) Touch-sense Compare Register 0 */\r
+ __IO uint32_t TSCMP1; /*!< (@ 0x50020028) Touch-sense Compare Register 1 */\r
+} LEDTS0_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ USIC [USIC0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Universal Serial Interface Controller 0 (USIC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48000008) USIC Structure */\r
+ __I uint32_t ID; /*!< (@ 0x48000008) Module Identification Register */\r
+} USIC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ USIC_CH [USIC0_CH0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Universal Serial Interface Controller 0 (USIC_CH)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48000000) USIC_CH Structure */\r
+ __I uint32_t RESERVED0;\r
+ __I uint32_t CCFG; /*!< (@ 0x48000004) Channel Configuration Register */\r
+ __I uint32_t RESERVED1;\r
+ __IO uint32_t KSCFG; /*!< (@ 0x4800000C) Kernel State Configuration Register */\r
+ __IO uint32_t FDR; /*!< (@ 0x48000010) Fractional Divider Register */\r
+ __IO uint32_t BRG; /*!< (@ 0x48000014) Baud Rate Generator Register */\r
+ __IO uint32_t INPR; /*!< (@ 0x48000018) Interrupt Node Pointer Register */\r
+ __IO uint32_t DX0CR; /*!< (@ 0x4800001C) Input Control Register 0 */\r
+ __IO uint32_t DX1CR; /*!< (@ 0x48000020) Input Control Register 1 */\r
+ __IO uint32_t DX2CR; /*!< (@ 0x48000024) Input Control Register 2 */\r
+ __IO uint32_t DX3CR; /*!< (@ 0x48000028) Input Control Register 3 */\r
+ __IO uint32_t DX4CR; /*!< (@ 0x4800002C) Input Control Register 4 */\r
+ __IO uint32_t DX5CR; /*!< (@ 0x48000030) Input Control Register 5 */\r
+ __IO uint32_t SCTR; /*!< (@ 0x48000034) Shift Control Register */\r
+ __IO uint32_t TCSR; /*!< (@ 0x48000038) Transmit Control/Status Register */\r
+ \r
+ union {\r
+ __IO uint32_t PCR_IICMode; /*!< (@ 0x4800003C) Protocol Control Register [IIC Mode] */\r
+ __IO uint32_t PCR_IISMode; /*!< (@ 0x4800003C) Protocol Control Register [IIS Mode] */\r
+ __IO uint32_t PCR_SSCMode; /*!< (@ 0x4800003C) Protocol Control Register [SSC Mode] */\r
+ __IO uint32_t PCR; /*!< (@ 0x4800003C) Protocol Control Register */\r
+ __IO uint32_t PCR_ASCMode; /*!< (@ 0x4800003C) Protocol Control Register [ASC Mode] */\r
+ };\r
+ __IO uint32_t CCR; /*!< (@ 0x48000040) Channel Control Register */\r
+ __IO uint32_t CMTR; /*!< (@ 0x48000044) Capture Mode Timer Register */\r
+ \r
+ union {\r
+ __IO uint32_t PSR_IICMode; /*!< (@ 0x48000048) Protocol Status Register [IIC Mode] */\r
+ __IO uint32_t PSR_IISMode; /*!< (@ 0x48000048) Protocol Status Register [IIS Mode] */\r
+ __IO uint32_t PSR_SSCMode; /*!< (@ 0x48000048) Protocol Status Register [SSC Mode] */\r
+ __IO uint32_t PSR; /*!< (@ 0x48000048) Protocol Status Register */\r
+ __IO uint32_t PSR_ASCMode; /*!< (@ 0x48000048) Protocol Status Register [ASC Mode] */\r
+ };\r
+ __O uint32_t PSCR; /*!< (@ 0x4800004C) Protocol Status Clear Register */\r
+ __I uint32_t RBUFSR; /*!< (@ 0x48000050) Receiver Buffer Status Register */\r
+ __I uint32_t RBUF; /*!< (@ 0x48000054) Receiver Buffer Register */\r
+ __I uint32_t RBUFD; /*!< (@ 0x48000058) Receiver Buffer Register for Debugger */\r
+ __I uint32_t RBUF0; /*!< (@ 0x4800005C) Receiver Buffer Register 0 */\r
+ __I uint32_t RBUF1; /*!< (@ 0x48000060) Receiver Buffer Register 1 */\r
+ __I uint32_t RBUF01SR; /*!< (@ 0x48000064) Receiver Buffer 01 Status Register */\r
+ __O uint32_t FMR; /*!< (@ 0x48000068) Flag Modification Register */\r
+ __I uint32_t RESERVED2[5];\r
+ __IO uint32_t TBUF[32]; /*!< (@ 0x48000080) Transmit Buffer */\r
+ __IO uint32_t BYP; /*!< (@ 0x48000100) Bypass Data Register */\r
+ __IO uint32_t BYPCR; /*!< (@ 0x48000104) Bypass Control Register */\r
+ __IO uint32_t TBCTR; /*!< (@ 0x48000108) Transmitter Buffer Control Register */\r
+ __IO uint32_t RBCTR; /*!< (@ 0x4800010C) Receiver Buffer Control Register */\r
+ __I uint32_t TRBPTR; /*!< (@ 0x48000110) Transmit/Receive Buffer Pointer Register */\r
+ __IO uint32_t TRBSR; /*!< (@ 0x48000114) Transmit/Receive Buffer Status Register */\r
+ __O uint32_t TRBSCR; /*!< (@ 0x48000118) Transmit/Receive Buffer Status Clear Register */\r
+ __I uint32_t OUTR; /*!< (@ 0x4800011C) Receiver Buffer Output Register */\r
+ __I uint32_t OUTDR; /*!< (@ 0x48000120) Receiver Buffer Output Register L for Debugger */\r
+ __I uint32_t RESERVED3[23];\r
+ __O uint32_t IN[32]; /*!< (@ 0x48000180) Transmit FIFO Buffer */\r
+} USIC_CH_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SCU_GENERAL ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (SCU_GENERAL)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010000) SCU_GENERAL Structure */\r
+ __I uint32_t DBGROMID; /*!< (@ 0x40010000) Debug System ROM ID Register */\r
+ __I uint32_t IDCHIP; /*!< (@ 0x40010004) Chip ID Register */\r
+ __I uint32_t ID; /*!< (@ 0x40010008) SCU Module ID Register */\r
+ __I uint32_t RESERVED0[2];\r
+ __IO uint32_t SSW0; /*!< (@ 0x40010014) SSW Register 0 */\r
+ __I uint32_t RESERVED1[3];\r
+ __IO uint32_t PASSWD; /*!< (@ 0x40010024) Password Register */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t CCUCON; /*!< (@ 0x40010030) CCU Control Register */\r
+ __I uint32_t RESERVED3[5];\r
+ __I uint32_t MIRRSTS; /*!< (@ 0x40010048) Mirror Update Status Register */\r
+ __I uint32_t RESERVED4[2];\r
+ __IO uint32_t PMTSR; /*!< (@ 0x40010054) Parity Memory Test Select Register */\r
+} SCU_GENERAL_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SCU_INTERRUPT ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (SCU_INTERRUPT)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010038) SCU_INTERRUPT Structure */\r
+ __I uint32_t SRRAW; /*!< (@ 0x40010038) SCU Raw Service Request Status */\r
+ __IO uint32_t SRMSK; /*!< (@ 0x4001003C) SCU Service Request Mask */\r
+ __O uint32_t SRCLR; /*!< (@ 0x40010040) SCU Service Request Clear */\r
+ __O uint32_t SRSET; /*!< (@ 0x40010044) SCU Service Request Set */\r
+} SCU_INTERRUPT_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SCU_POWER ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (SCU_POWER)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010200) SCU_POWER Structure */\r
+ __I uint32_t VDESR; /*!< (@ 0x40010200) Voltage Detector Status Register */\r
+} SCU_POWER_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SCU_CLK ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (SCU_CLK)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010300) SCU_CLK Structure */\r
+ __IO uint32_t CLKCR; /*!< (@ 0x40010300) Clock Control Register */\r
+ __IO uint32_t PWRSVCR; /*!< (@ 0x40010304) Power Save Control Register */\r
+ __I uint32_t CGATSTAT0; /*!< (@ 0x40010308) Peripheral 0 Clock Gating Status */\r
+ __O uint32_t CGATSET0; /*!< (@ 0x4001030C) Peripheral 0 Clock Gating Set */\r
+ __O uint32_t CGATCLR0; /*!< (@ 0x40010310) Peripheral 0 Clock Gating Clear */\r
+ __IO uint32_t OSCCSR; /*!< (@ 0x40010314) Oscillator Control and Status Register */\r
+} SCU_CLK_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SCU_RESET ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (SCU_RESET)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010400) SCU_RESET Structure */\r
+ __I uint32_t RSTSTAT; /*!< (@ 0x40010400) RCU Reset Status */\r
+ __O uint32_t RSTSET; /*!< (@ 0x40010404) RCU Reset Set Register */\r
+ __O uint32_t RSTCLR; /*!< (@ 0x40010408) RCU Reset Clear Register */\r
+ __IO uint32_t RSTCON; /*!< (@ 0x4001040C) RCU Reset Control Register */\r
+} SCU_RESET_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ COMPARATOR ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (COMPARATOR)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40010500) COMPARATOR Structure */\r
+ __IO uint32_t ORCCTRL; /*!< (@ 0x40010500) Out Of Range Comparator Control Register */\r
+ __I uint32_t RESERVED0[726];\r
+ __IO uint16_t ANACMP0; /*!< (@ 0x4001105C) Analog Comparator 0 Control Register */\r
+ __I uint16_t RESERVED1;\r
+ __IO uint16_t ANACMP1; /*!< (@ 0x40011060) Analog Comparator 1 Control Register */\r
+ __I uint16_t RESERVED2;\r
+ __IO uint16_t ANACMP2; /*!< (@ 0x40011064) Analog Comparator 2 Control Register */\r
+} COMPARATOR_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SCU_ANALOG ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief System Control Unit (SCU_ANALOG)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40011000) SCU_ANALOG Structure */\r
+ __I uint32_t RESERVED0[9];\r
+ __IO uint16_t ANATSECTRL; /*!< (@ 0x40011024) Temperature Sensor Control Register */\r
+ __I uint16_t RESERVED1[5];\r
+ __IO uint16_t ANATSEIH; /*!< (@ 0x40011030) Temperature Sensor High Temperature Interrupt\r
+ Register */\r
+ __I uint16_t RESERVED2;\r
+ __IO uint16_t ANATSEIL; /*!< (@ 0x40011034) Temperature Sensor Low Temperature Interrupt\r
+ Register */\r
+ __I uint16_t RESERVED3[5];\r
+ __I uint16_t ANATSEMON; /*!< (@ 0x40011040) Temperature Sensor Counter2 Monitor Register */\r
+ __I uint16_t RESERVED4[7];\r
+ __IO uint16_t ANAVDEL; /*!< (@ 0x40011050) Voltage Detector Control Register */\r
+ __I uint16_t RESERVED5[13];\r
+ __IO uint16_t ANAOFFSET; /*!< (@ 0x4001106C) DCO1 Offset Register */\r
+} SCU_ANALOG_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ CCU4 [CCU40] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Capture Compare Unit 4 - Unit 0 (CCU4)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48040000) CCU4 Structure */\r
+ __IO uint32_t GCTRL; /*!< (@ 0x48040000) Global Control Register */\r
+ __I uint32_t GSTAT; /*!< (@ 0x48040004) Global Status Register */\r
+ __O uint32_t GIDLS; /*!< (@ 0x48040008) Global Idle Set */\r
+ __O uint32_t GIDLC; /*!< (@ 0x4804000C) Global Idle Clear */\r
+ __O uint32_t GCSS; /*!< (@ 0x48040010) Global Channel Set */\r
+ __O uint32_t GCSC; /*!< (@ 0x48040014) Global Channel Clear */\r
+ __I uint32_t GCST; /*!< (@ 0x48040018) Global Channel Status */\r
+ __I uint32_t RESERVED0[25];\r
+ __I uint32_t MIDR; /*!< (@ 0x48040080) Module Identification */\r
+} CCU4_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ CCU4_CC4 [CCU40_CC40] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Capture Compare Unit 4 - Unit 0 (CCU4_CC4)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48040100) CCU4_CC4 Structure */\r
+ __IO uint32_t INS; /*!< (@ 0x48040100) Input Selector Configuration */\r
+ __IO uint32_t CMC; /*!< (@ 0x48040104) Connection Matrix Control */\r
+ __I uint32_t TCST; /*!< (@ 0x48040108) Slice Timer Status */\r
+ __O uint32_t TCSET; /*!< (@ 0x4804010C) Slice Timer Run Set */\r
+ __O uint32_t TCCLR; /*!< (@ 0x48040110) Slice Timer Clear */\r
+ __IO uint32_t TC; /*!< (@ 0x48040114) Slice Timer Control */\r
+ __IO uint32_t PSL; /*!< (@ 0x48040118) Passive Level Config */\r
+ __I uint32_t DIT; /*!< (@ 0x4804011C) Dither Config */\r
+ __IO uint32_t DITS; /*!< (@ 0x48040120) Dither Shadow Register */\r
+ __IO uint32_t PSC; /*!< (@ 0x48040124) Prescaler Control */\r
+ __IO uint32_t FPC; /*!< (@ 0x48040128) Floating Prescaler Control */\r
+ __IO uint32_t FPCS; /*!< (@ 0x4804012C) Floating Prescaler Shadow */\r
+ __I uint32_t PR; /*!< (@ 0x48040130) Timer Period Value */\r
+ __IO uint32_t PRS; /*!< (@ 0x48040134) Timer Shadow Period Value */\r
+ __I uint32_t CR; /*!< (@ 0x48040138) Timer Compare Value */\r
+ __IO uint32_t CRS; /*!< (@ 0x4804013C) Timer Shadow Compare Value */\r
+ __I uint32_t RESERVED0[12];\r
+ __IO uint32_t TIMER; /*!< (@ 0x48040170) Timer Value */\r
+ __I uint32_t CV[4]; /*!< (@ 0x48040174) Capture Register 0 */\r
+ __I uint32_t RESERVED1[7];\r
+ __I uint32_t INTS; /*!< (@ 0x480401A0) Interrupt Status */\r
+ __IO uint32_t INTE; /*!< (@ 0x480401A4) Interrupt Enable Control */\r
+ __IO uint32_t SRS; /*!< (@ 0x480401A8) Service Request Selector */\r
+ __O uint32_t SWS; /*!< (@ 0x480401AC) Interrupt Status Set */\r
+ __O uint32_t SWR; /*!< (@ 0x480401B0) Interrupt Status Clear */\r
+ __I uint32_t RESERVED2;\r
+ __I uint32_t ECRD0; /*!< (@ 0x480401B8) Extended Read Back 0 */\r
+ __I uint32_t ECRD1; /*!< (@ 0x480401BC) Extended Read Back 1 */\r
+} CCU4_CC4_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ VADC [VADC] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Analog to Digital Converter (VADC)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48030000) VADC Structure */\r
+ __IO uint32_t CLC; /*!< (@ 0x48030000) Clock Control Register */\r
+ __I uint32_t RESERVED0;\r
+ __I uint32_t ID; /*!< (@ 0x48030008) Module Identification Register */\r
+ __I uint32_t RESERVED1[7];\r
+ __IO uint32_t OCS; /*!< (@ 0x48030028) OCDS Control and Status Register */\r
+ __I uint32_t RESERVED2[21];\r
+ __IO uint32_t GLOBCFG; /*!< (@ 0x48030080) Global Configuration Register */\r
+ __I uint32_t RESERVED3;\r
+ __IO uint32_t ACCPROT0; /*!< (@ 0x48030088) Access Protection Register */\r
+ __IO uint32_t ACCPROT1; /*!< (@ 0x4803008C) Access Protection Register */\r
+ __I uint32_t RESERVED4[4];\r
+ __IO uint32_t GLOBICLASS[2]; /*!< (@ 0x480300A0) Input Class Register, Global */\r
+ __I uint32_t RESERVED5[4];\r
+ __IO uint32_t GLOBBOUND; /*!< (@ 0x480300B8) Global Boundary Select Register */\r
+ __I uint32_t RESERVED6[9];\r
+ __IO uint32_t GLOBEFLAG; /*!< (@ 0x480300E0) Global Event Flag Register */\r
+ __I uint32_t RESERVED7[23];\r
+ __IO uint32_t GLOBEVNP; /*!< (@ 0x48030140) Global Event Node Pointer Register */\r
+ __I uint32_t RESERVED8[15];\r
+ __IO uint32_t BRSSEL[2]; /*!< (@ 0x48030180) Background Request Source Channel Select Register */\r
+ __I uint32_t RESERVED9[14];\r
+ __IO uint32_t BRSPND[2]; /*!< (@ 0x480301C0) Background Request Source Pending Register */\r
+ __I uint32_t RESERVED10[14];\r
+ __IO uint32_t BRSCTRL; /*!< (@ 0x48030200) Background Request Source Control Register */\r
+ __IO uint32_t BRSMR; /*!< (@ 0x48030204) Background Request Source Mode Register */\r
+ __I uint32_t RESERVED11[30];\r
+ __IO uint32_t GLOBRCR; /*!< (@ 0x48030280) Global Result Control Register */\r
+ __I uint32_t RESERVED12[31];\r
+ __IO uint32_t GLOBRES; /*!< (@ 0x48030300) Global Result Register */\r
+ __I uint32_t RESERVED13[31];\r
+ __IO uint32_t GLOBRESD; /*!< (@ 0x48030380) Global Result Register, Debug */\r
+ __I uint32_t RESERVED14[27];\r
+ __IO uint32_t EMUXSEL; /*!< (@ 0x480303F0) External Multiplexer Select Register */\r
+} VADC_GLOBAL_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ VADC_G [VADC_G0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Analog to Digital Converter (VADC_G)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48030400) VADC_G Structure */\r
+ __I uint32_t RESERVED0[32];\r
+ __IO uint32_t ARBCFG; /*!< (@ 0x48030480) Arbitration Configuration Register */\r
+ __IO uint32_t ARBPR; /*!< (@ 0x48030484) Arbitration Priority Register */\r
+ __IO uint32_t CHASS; /*!< (@ 0x48030488) Channel Assignment Register */\r
+ __IO uint32_t RRASS; /*!< (@ 0x4803048C) Result Assignment Register */\r
+ __I uint32_t RESERVED1[4];\r
+ __IO uint32_t ICLASS[2]; /*!< (@ 0x480304A0) Input Class Register 0 */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t ALIAS; /*!< (@ 0x480304B0) Alias Register */\r
+ __I uint32_t RESERVED3;\r
+ __IO uint32_t BOUND; /*!< (@ 0x480304B8) Boundary Select Register */\r
+ __I uint32_t RESERVED4;\r
+ __IO uint32_t SYNCTR; /*!< (@ 0x480304C0) Synchronization Control Register */\r
+ __I uint32_t RESERVED5;\r
+ __IO uint32_t BFL; /*!< (@ 0x480304C8) Boundary Flag Register */\r
+ __O uint32_t BFLS; /*!< (@ 0x480304CC) Boundary Flag Software Register */\r
+ __IO uint32_t BFLC; /*!< (@ 0x480304D0) Boundary Flag Control Register */\r
+ __IO uint32_t BFLNP; /*!< (@ 0x480304D4) Boundary Flag Node Pointer Register */\r
+ __I uint32_t RESERVED6[10];\r
+ __IO uint32_t QCTRL0; /*!< (@ 0x48030500) Queue 0 Source Control Register */\r
+ __IO uint32_t QMR0; /*!< (@ 0x48030504) Queue 0 Mode Register */\r
+ __I uint32_t QSR0; /*!< (@ 0x48030508) Queue 0 Status Register */\r
+ __I uint32_t Q0R0; /*!< (@ 0x4803050C) Queue 0 Register 0 */\r
+ \r
+ union {\r
+ __I uint32_t QBUR0; /*!< (@ 0x48030510) Queue 0 Backup Register */\r
+ __O uint32_t QINR0; /*!< (@ 0x48030510) Queue 0 Input Register */\r
+ };\r
+ __I uint32_t RESERVED7[3];\r
+ __IO uint32_t ASCTRL; /*!< (@ 0x48030520) Autoscan Source Control Register */\r
+ __IO uint32_t ASMR; /*!< (@ 0x48030524) Autoscan Source Mode Register */\r
+ __IO uint32_t ASSEL; /*!< (@ 0x48030528) Autoscan Source Channel Select Register */\r
+ __IO uint32_t ASPND; /*!< (@ 0x4803052C) Autoscan Source Pending Register */\r
+ __I uint32_t RESERVED8[20];\r
+ __IO uint32_t CEFLAG; /*!< (@ 0x48030580) Channel Event Flag Register */\r
+ __IO uint32_t REFLAG; /*!< (@ 0x48030584) Result Event Flag Register */\r
+ __IO uint32_t SEFLAG; /*!< (@ 0x48030588) Source Event Flag Register */\r
+ __I uint32_t RESERVED9;\r
+ __O uint32_t CEFCLR; /*!< (@ 0x48030590) Channel Event Flag Clear Register */\r
+ __O uint32_t REFCLR; /*!< (@ 0x48030594) Result Event Flag Clear Register */\r
+ __O uint32_t SEFCLR; /*!< (@ 0x48030598) Source Event Flag Clear Register */\r
+ __I uint32_t RESERVED10;\r
+ __IO uint32_t CEVNP0; /*!< (@ 0x480305A0) Channel Event Node Pointer Register 0 */\r
+ __I uint32_t RESERVED11[3];\r
+ __IO uint32_t REVNP0; /*!< (@ 0x480305B0) Result Event Node Pointer Register 0 */\r
+ __IO uint32_t REVNP1; /*!< (@ 0x480305B4) Result Event Node Pointer Register 1 */\r
+ __I uint32_t RESERVED12[2];\r
+ __IO uint32_t SEVNP; /*!< (@ 0x480305C0) Source Event Node Pointer Register */\r
+ __I uint32_t RESERVED13;\r
+ __O uint32_t SRACT; /*!< (@ 0x480305C8) Service Request Software Activation Trigger */\r
+ __I uint32_t RESERVED14[9];\r
+ __IO uint32_t EMUXCTR; /*!< (@ 0x480305F0) E0ternal Multiplexer Control Register, Group\r
+ x */\r
+ __I uint32_t RESERVED15;\r
+ __IO uint32_t VFR; /*!< (@ 0x480305F8) Valid Flag Register, Group 0 */\r
+ __I uint32_t RESERVED16;\r
+ __IO uint32_t CHCTR[8]; /*!< (@ 0x48030600) Channel Ctrl. Reg. */\r
+ __I uint32_t RESERVED17[24];\r
+ __IO uint32_t RCR[16]; /*!< (@ 0x48030680) Result Control Reg. */\r
+ __I uint32_t RESERVED18[16];\r
+ __IO uint32_t RES[16]; /*!< (@ 0x48030700) Result Register */\r
+ __I uint32_t RESERVED19[16];\r
+ __I uint32_t RESD[16]; /*!< (@ 0x48030780) Result Register, Debug */\r
+} VADC_G_TypeDef;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ SHS [SHS0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Sample and Hold ADC Sequencer (SHS)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x48034000) SHS Structure */\r
+ __I uint32_t RESERVED0[2];\r
+ __I uint32_t ID; /*!< (@ 0x48034008) Module Identification Register */\r
+ __I uint32_t RESERVED1[13];\r
+ __IO uint32_t SHSCFG; /*!< (@ 0x48034040) SHS Configuration Register */\r
+ __IO uint32_t STEPCFG; /*!< (@ 0x48034044) Stepper Configuration Register */\r
+ __I uint32_t RESERVED2[2];\r
+ __IO uint32_t LOOP; /*!< (@ 0x48034050) Loop Control Register */\r
+ __I uint32_t RESERVED3[11];\r
+ __IO uint32_t TIMCFG0; /*!< (@ 0x48034080) Timing Configuration Register 0 */\r
+ __IO uint32_t TIMCFG1; /*!< (@ 0x48034084) Timing Configuration Register 1 */\r
+ __I uint32_t RESERVED4[13];\r
+ __IO uint32_t CALCTR; /*!< (@ 0x480340BC) Calibration Control Register */\r
+ __IO uint32_t CALGC0; /*!< (@ 0x480340C0) Gain Calibration Control Register 0 */\r
+ __IO uint32_t CALGC1; /*!< (@ 0x480340C4) Gain Calibration Control Register 1 */\r
+ __I uint32_t RESERVED5[46];\r
+ __IO uint32_t GNCTR00; /*!< (@ 0x48034180) Gain Control Register 00 */\r
+ __I uint32_t RESERVED6[3];\r
+ __IO uint32_t GNCTR10; /*!< (@ 0x48034190) Gain Control Register 10 */\r
+} SHS_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ BCCU [BCCU0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief BCCU Unit 0 (BCCU)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x50030000) BCCU Structure */\r
+ __IO uint32_t GLOBCON; /*!< (@ 0x50030000) Global Control */\r
+ __IO uint32_t GLOBCLK; /*!< (@ 0x50030004) Global Clock */\r
+ __I uint32_t ID; /*!< (@ 0x50030008) Module Identification */\r
+ __IO uint32_t CHEN; /*!< (@ 0x5003000C) Channel Enable */\r
+ __IO uint32_t CHOCON; /*!< (@ 0x50030010) Channel Output Control */\r
+ __IO uint32_t CHTRIG; /*!< (@ 0x50030014) Channel Trigger */\r
+ __IO uint32_t CHSTRCON; /*!< (@ 0x50030018) Channel Shadow Transfer */\r
+ __I uint32_t LTCHOL; /*!< (@ 0x5003001C) Last Trigger Channel Output Level */\r
+ __IO uint32_t DEEN; /*!< (@ 0x50030020) Dimming Engine Enable */\r
+ __IO uint32_t DESTRCON; /*!< (@ 0x50030024) Dimming Shadow Transfer */\r
+ __IO uint32_t GLOBDIM; /*!< (@ 0x50030028) Global Dimming Level */\r
+ __IO uint32_t EVIER; /*!< (@ 0x5003002C) Event Interrupt Enable */\r
+ __I uint32_t EVFR; /*!< (@ 0x50030030) Event Flag */\r
+ __O uint32_t EVFSR; /*!< (@ 0x50030034) Event Flag Set */\r
+ __O uint32_t EVFCR; /*!< (@ 0x50030038) Event Flag Clear */\r
+} BCCU_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ BCCU_CH [BCCU0_CH0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief BCCU Unit 0 (BCCU_CH)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x5003003C) BCCU_CH Structure */\r
+ __IO uint32_t INTS; /*!< (@ 0x5003003C) Channel Intensit0 Shadow */\r
+ __I uint32_t INT; /*!< (@ 0x50030040) Channel Intensit0 */\r
+ __IO uint32_t CHCONFIG; /*!< (@ 0x50030044) Channel Configuration */\r
+ __IO uint32_t PKCMP; /*!< (@ 0x50030048) Packer Compare */\r
+ __IO uint32_t PKCNTR; /*!< (@ 0x5003004C) Packer Counter */\r
+} BCCU_CH_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ BCCU_DE [BCCU0_DE0] ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief BCCU Unit 0 (BCCU_DE)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x5003017C) BCCU_DE Structure */\r
+ __IO uint32_t DLS; /*!< (@ 0x5003017C) Dimming Level Shadow */\r
+ __I uint32_t DL; /*!< (@ 0x50030180) Dimming Level */\r
+ __IO uint32_t DTT; /*!< (@ 0x50030184) Dimming Transition Time */\r
+} BCCU_DE_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PORT0 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Port 0 (PORT0)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40040000) PORT0 Structure */\r
+ __IO uint32_t OUT; /*!< (@ 0x40040000) Port 0 Output Register */\r
+ __O uint32_t OMR; /*!< (@ 0x40040004) Port 0 Output Modification Register */\r
+ __I uint32_t RESERVED0[2];\r
+ __IO uint32_t IOCR0; /*!< (@ 0x40040010) Port 0 Input/Output Control Register 0 */\r
+ __IO uint32_t IOCR4; /*!< (@ 0x40040014) Port 0 Input/Output Control Register 4 */\r
+ __IO uint32_t IOCR8; /*!< (@ 0x40040018) Port 0 Input/Output Control Register 8 */\r
+ __IO uint32_t IOCR12; /*!< (@ 0x4004001C) Port 0 Input/Output Control Register 12 */\r
+ __I uint32_t RESERVED1;\r
+ __I uint32_t IN; /*!< (@ 0x40040024) Port 0 Input Register */\r
+ __I uint32_t RESERVED2[6];\r
+ __IO uint32_t PHCR0; /*!< (@ 0x40040040) Port 0 Pad Hysteresis Control Register 0 */\r
+ __IO uint32_t PHCR1; /*!< (@ 0x40040044) Port 0 Pad Hysteresis Control Register 1 */\r
+ __I uint32_t RESERVED3[6];\r
+ __I uint32_t PDISC; /*!< (@ 0x40040060) Port 0 Pin Function Decision Control Register */\r
+ __I uint32_t RESERVED4[3];\r
+ __IO uint32_t PPS; /*!< (@ 0x40040070) Port 0 Pin Power Save Register */\r
+ __IO uint32_t HWSEL; /*!< (@ 0x40040074) Port 0 Pin Hardware Select Register */\r
+} PORT0_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PORT1 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Port 1 (PORT1)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40040100) PORT1 Structure */\r
+ __IO uint32_t OUT; /*!< (@ 0x40040100) Port 1 Output Register */\r
+ __O uint32_t OMR; /*!< (@ 0x40040104) Port 1 Output Modification Register */\r
+ __I uint32_t RESERVED0[2];\r
+ __IO uint32_t IOCR0; /*!< (@ 0x40040110) Port 1 Input/Output Control Register 0 */\r
+ __IO uint32_t IOCR4; /*!< (@ 0x40040114) Port 1 Input/Output Control Register 4 */\r
+ __I uint32_t RESERVED1[3];\r
+ __I uint32_t IN; /*!< (@ 0x40040124) Port 1 Input Register */\r
+ __I uint32_t RESERVED2[6];\r
+ __IO uint32_t PHCR0; /*!< (@ 0x40040140) Port 1 Pad Hysteresis Control Register 0 */\r
+ __I uint32_t RESERVED3[7];\r
+ __I uint32_t PDISC; /*!< (@ 0x40040160) Port 1 Pin Function Decision Control Register */\r
+ __I uint32_t RESERVED4[3];\r
+ __IO uint32_t PPS; /*!< (@ 0x40040170) Port 1 Pin Power Save Register */\r
+ __IO uint32_t HWSEL; /*!< (@ 0x40040174) Port 1 Pin Hardware Select Register */\r
+} PORT1_Type;\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ PORT2 ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/**\r
+ * @brief Port 2 (PORT2)\r
+ */\r
+\r
+typedef struct { /*!< (@ 0x40040200) PORT2 Structure */\r
+ __IO uint32_t OUT; /*!< (@ 0x40040200) Port 2 Output Register */\r
+ __O uint32_t OMR; /*!< (@ 0x40040204) Port 2 Output Modification Register */\r
+ __I uint32_t RESERVED0[2];\r
+ __IO uint32_t IOCR0; /*!< (@ 0x40040210) Port 2 Input/Output Control Register 0 */\r
+ __IO uint32_t IOCR4; /*!< (@ 0x40040214) Port 2 Input/Output Control Register 4 */\r
+ __IO uint32_t IOCR8; /*!< (@ 0x40040218) Port 2 Input/Output Control Register 8 */\r
+ __I uint32_t RESERVED1[2];\r
+ __I uint32_t IN; /*!< (@ 0x40040224) Port 2 Input Register */\r
+ __I uint32_t RESERVED2[6];\r
+ __IO uint32_t PHCR0; /*!< (@ 0x40040240) Port 2 Pad Hysteresis Control Register 0 */\r
+ __IO uint32_t PHCR1; /*!< (@ 0x40040244) Port 2 Pad Hysteresis Control Register 1 */\r
+ __I uint32_t RESERVED3[6];\r
+ __IO uint32_t PDISC; /*!< (@ 0x40040260) Port 2 Pin Function Decision Control Register */\r
+ __I uint32_t RESERVED4[3];\r
+ __IO uint32_t PPS; /*!< (@ 0x40040270) Port 2 Pin Power Save Register */\r
+ __IO uint32_t HWSEL; /*!< (@ 0x40040274) Port 2 Pin Hardware Select Register */\r
+} PORT2_Type;\r
+\r
+\r
+/* -------------------- End of section using anonymous unions ------------------- */\r
+#if defined(__CC_ARM)\r
+ #pragma pop\r
+#elif defined(__ICCARM__)\r
+ /* leave anonymous unions enabled */\r
+#elif defined(__GNUC__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TMS470__)\r
+ /* anonymous unions are enabled by default */\r
+#elif defined(__TASKING__)\r
+ #pragma warning restore\r
+#else\r
+ #warning Not supported compiler type\r
+#endif\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PPB' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- PPB_SYST_CSR -------------------------------- */\r
+#define PPB_SYST_CSR_ENABLE_Pos 0 /*!< PPB SYST_CSR: ENABLE Position */\r
+#define PPB_SYST_CSR_ENABLE_Msk (0x01UL << PPB_SYST_CSR_ENABLE_Pos) /*!< PPB SYST_CSR: ENABLE Mask */\r
+#define PPB_SYST_CSR_TICKINT_Pos 1 /*!< PPB SYST_CSR: TICKINT Position */\r
+#define PPB_SYST_CSR_TICKINT_Msk (0x01UL << PPB_SYST_CSR_TICKINT_Pos) /*!< PPB SYST_CSR: TICKINT Mask */\r
+#define PPB_SYST_CSR_CLKSOURCE_Pos 2 /*!< PPB SYST_CSR: CLKSOURCE Position */\r
+#define PPB_SYST_CSR_CLKSOURCE_Msk (0x01UL << PPB_SYST_CSR_CLKSOURCE_Pos) /*!< PPB SYST_CSR: CLKSOURCE Mask */\r
+#define PPB_SYST_CSR_COUNTFLAG_Pos 16 /*!< PPB SYST_CSR: COUNTFLAG Position */\r
+#define PPB_SYST_CSR_COUNTFLAG_Msk (0x01UL << PPB_SYST_CSR_COUNTFLAG_Pos) /*!< PPB SYST_CSR: COUNTFLAG Mask */\r
+\r
+/* -------------------------------- PPB_SYST_RVR -------------------------------- */\r
+#define PPB_SYST_RVR_RELOAD_Pos 0 /*!< PPB SYST_RVR: RELOAD Position */\r
+#define PPB_SYST_RVR_RELOAD_Msk (0x00ffffffUL << PPB_SYST_RVR_RELOAD_Pos) /*!< PPB SYST_RVR: RELOAD Mask */\r
+\r
+/* -------------------------------- PPB_SYST_CVR -------------------------------- */\r
+#define PPB_SYST_CVR_CURRENT_Pos 0 /*!< PPB SYST_CVR: CURRENT Position */\r
+#define PPB_SYST_CVR_CURRENT_Msk (0x00ffffffUL << PPB_SYST_CVR_CURRENT_Pos) /*!< PPB SYST_CVR: CURRENT Mask */\r
+\r
+/* ------------------------------- PPB_SYST_CALIB ------------------------------- */\r
+#define PPB_SYST_CALIB_TENMS_Pos 0 /*!< PPB SYST_CALIB: TENMS Position */\r
+#define PPB_SYST_CALIB_TENMS_Msk (0x00ffffffUL << PPB_SYST_CALIB_TENMS_Pos) /*!< PPB SYST_CALIB: TENMS Mask */\r
+#define PPB_SYST_CALIB_SKEW_Pos 30 /*!< PPB SYST_CALIB: SKEW Position */\r
+#define PPB_SYST_CALIB_SKEW_Msk (0x01UL << PPB_SYST_CALIB_SKEW_Pos) /*!< PPB SYST_CALIB: SKEW Mask */\r
+#define PPB_SYST_CALIB_NOREF_Pos 31 /*!< PPB SYST_CALIB: NOREF Position */\r
+#define PPB_SYST_CALIB_NOREF_Msk (0x01UL << PPB_SYST_CALIB_NOREF_Pos) /*!< PPB SYST_CALIB: NOREF Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_ISER ------------------------------- */\r
+#define PPB_NVIC_ISER_SETENA_Pos 0 /*!< PPB NVIC_ISER: SETENA Position */\r
+#define PPB_NVIC_ISER_SETENA_Msk (0xffffffffUL << PPB_NVIC_ISER_SETENA_Pos) /*!< PPB NVIC_ISER: SETENA Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_ICER ------------------------------- */\r
+#define PPB_NVIC_ICER_CLRENA_Pos 0 /*!< PPB NVIC_ICER: CLRENA Position */\r
+#define PPB_NVIC_ICER_CLRENA_Msk (0xffffffffUL << PPB_NVIC_ICER_CLRENA_Pos) /*!< PPB NVIC_ICER: CLRENA Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_ISPR ------------------------------- */\r
+#define PPB_NVIC_ISPR_SETPEND_Pos 0 /*!< PPB NVIC_ISPR: SETPEND Position */\r
+#define PPB_NVIC_ISPR_SETPEND_Msk (0xffffffffUL << PPB_NVIC_ISPR_SETPEND_Pos) /*!< PPB NVIC_ISPR: SETPEND Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_ICPR ------------------------------- */\r
+#define PPB_NVIC_ICPR_CLRPEND_Pos 0 /*!< PPB NVIC_ICPR: CLRPEND Position */\r
+#define PPB_NVIC_ICPR_CLRPEND_Msk (0xffffffffUL << PPB_NVIC_ICPR_CLRPEND_Pos) /*!< PPB NVIC_ICPR: CLRPEND Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */\r
+#define PPB_NVIC_IPR0_PRI_0_Pos 0 /*!< PPB NVIC_IPR0: PRI_0 Position */\r
+#define PPB_NVIC_IPR0_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_0_Pos) /*!< PPB NVIC_IPR0: PRI_0 Mask */\r
+#define PPB_NVIC_IPR0_PRI_1_Pos 8 /*!< PPB NVIC_IPR0: PRI_1 Position */\r
+#define PPB_NVIC_IPR0_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_1_Pos) /*!< PPB NVIC_IPR0: PRI_1 Mask */\r
+#define PPB_NVIC_IPR0_PRI_2_Pos 16 /*!< PPB NVIC_IPR0: PRI_2 Position */\r
+#define PPB_NVIC_IPR0_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_2_Pos) /*!< PPB NVIC_IPR0: PRI_2 Mask */\r
+#define PPB_NVIC_IPR0_PRI_3_Pos 24 /*!< PPB NVIC_IPR0: PRI_3 Position */\r
+#define PPB_NVIC_IPR0_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR0_PRI_3_Pos) /*!< PPB NVIC_IPR0: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */\r
+#define PPB_NVIC_IPR1_PRI_0_Pos 0 /*!< PPB NVIC_IPR1: PRI_0 Position */\r
+#define PPB_NVIC_IPR1_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_0_Pos) /*!< PPB NVIC_IPR1: PRI_0 Mask */\r
+#define PPB_NVIC_IPR1_PRI_1_Pos 8 /*!< PPB NVIC_IPR1: PRI_1 Position */\r
+#define PPB_NVIC_IPR1_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_1_Pos) /*!< PPB NVIC_IPR1: PRI_1 Mask */\r
+#define PPB_NVIC_IPR1_PRI_2_Pos 16 /*!< PPB NVIC_IPR1: PRI_2 Position */\r
+#define PPB_NVIC_IPR1_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_2_Pos) /*!< PPB NVIC_IPR1: PRI_2 Mask */\r
+#define PPB_NVIC_IPR1_PRI_3_Pos 24 /*!< PPB NVIC_IPR1: PRI_3 Position */\r
+#define PPB_NVIC_IPR1_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR1_PRI_3_Pos) /*!< PPB NVIC_IPR1: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */\r
+#define PPB_NVIC_IPR2_PRI_0_Pos 0 /*!< PPB NVIC_IPR2: PRI_0 Position */\r
+#define PPB_NVIC_IPR2_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_0_Pos) /*!< PPB NVIC_IPR2: PRI_0 Mask */\r
+#define PPB_NVIC_IPR2_PRI_1_Pos 8 /*!< PPB NVIC_IPR2: PRI_1 Position */\r
+#define PPB_NVIC_IPR2_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_1_Pos) /*!< PPB NVIC_IPR2: PRI_1 Mask */\r
+#define PPB_NVIC_IPR2_PRI_2_Pos 16 /*!< PPB NVIC_IPR2: PRI_2 Position */\r
+#define PPB_NVIC_IPR2_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_2_Pos) /*!< PPB NVIC_IPR2: PRI_2 Mask */\r
+#define PPB_NVIC_IPR2_PRI_3_Pos 24 /*!< PPB NVIC_IPR2: PRI_3 Position */\r
+#define PPB_NVIC_IPR2_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR2_PRI_3_Pos) /*!< PPB NVIC_IPR2: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */\r
+#define PPB_NVIC_IPR3_PRI_0_Pos 0 /*!< PPB NVIC_IPR3: PRI_0 Position */\r
+#define PPB_NVIC_IPR3_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_0_Pos) /*!< PPB NVIC_IPR3: PRI_0 Mask */\r
+#define PPB_NVIC_IPR3_PRI_1_Pos 8 /*!< PPB NVIC_IPR3: PRI_1 Position */\r
+#define PPB_NVIC_IPR3_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_1_Pos) /*!< PPB NVIC_IPR3: PRI_1 Mask */\r
+#define PPB_NVIC_IPR3_PRI_2_Pos 16 /*!< PPB NVIC_IPR3: PRI_2 Position */\r
+#define PPB_NVIC_IPR3_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_2_Pos) /*!< PPB NVIC_IPR3: PRI_2 Mask */\r
+#define PPB_NVIC_IPR3_PRI_3_Pos 24 /*!< PPB NVIC_IPR3: PRI_3 Position */\r
+#define PPB_NVIC_IPR3_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR3_PRI_3_Pos) /*!< PPB NVIC_IPR3: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */\r
+#define PPB_NVIC_IPR4_PRI_0_Pos 0 /*!< PPB NVIC_IPR4: PRI_0 Position */\r
+#define PPB_NVIC_IPR4_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_0_Pos) /*!< PPB NVIC_IPR4: PRI_0 Mask */\r
+#define PPB_NVIC_IPR4_PRI_1_Pos 8 /*!< PPB NVIC_IPR4: PRI_1 Position */\r
+#define PPB_NVIC_IPR4_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_1_Pos) /*!< PPB NVIC_IPR4: PRI_1 Mask */\r
+#define PPB_NVIC_IPR4_PRI_2_Pos 16 /*!< PPB NVIC_IPR4: PRI_2 Position */\r
+#define PPB_NVIC_IPR4_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_2_Pos) /*!< PPB NVIC_IPR4: PRI_2 Mask */\r
+#define PPB_NVIC_IPR4_PRI_3_Pos 24 /*!< PPB NVIC_IPR4: PRI_3 Position */\r
+#define PPB_NVIC_IPR4_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR4_PRI_3_Pos) /*!< PPB NVIC_IPR4: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */\r
+#define PPB_NVIC_IPR5_PRI_0_Pos 0 /*!< PPB NVIC_IPR5: PRI_0 Position */\r
+#define PPB_NVIC_IPR5_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_0_Pos) /*!< PPB NVIC_IPR5: PRI_0 Mask */\r
+#define PPB_NVIC_IPR5_PRI_1_Pos 8 /*!< PPB NVIC_IPR5: PRI_1 Position */\r
+#define PPB_NVIC_IPR5_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_1_Pos) /*!< PPB NVIC_IPR5: PRI_1 Mask */\r
+#define PPB_NVIC_IPR5_PRI_2_Pos 16 /*!< PPB NVIC_IPR5: PRI_2 Position */\r
+#define PPB_NVIC_IPR5_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_2_Pos) /*!< PPB NVIC_IPR5: PRI_2 Mask */\r
+#define PPB_NVIC_IPR5_PRI_3_Pos 24 /*!< PPB NVIC_IPR5: PRI_3 Position */\r
+#define PPB_NVIC_IPR5_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR5_PRI_3_Pos) /*!< PPB NVIC_IPR5: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */\r
+#define PPB_NVIC_IPR6_PRI_0_Pos 0 /*!< PPB NVIC_IPR6: PRI_0 Position */\r
+#define PPB_NVIC_IPR6_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_0_Pos) /*!< PPB NVIC_IPR6: PRI_0 Mask */\r
+#define PPB_NVIC_IPR6_PRI_1_Pos 8 /*!< PPB NVIC_IPR6: PRI_1 Position */\r
+#define PPB_NVIC_IPR6_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_1_Pos) /*!< PPB NVIC_IPR6: PRI_1 Mask */\r
+#define PPB_NVIC_IPR6_PRI_2_Pos 16 /*!< PPB NVIC_IPR6: PRI_2 Position */\r
+#define PPB_NVIC_IPR6_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_2_Pos) /*!< PPB NVIC_IPR6: PRI_2 Mask */\r
+#define PPB_NVIC_IPR6_PRI_3_Pos 24 /*!< PPB NVIC_IPR6: PRI_3 Position */\r
+#define PPB_NVIC_IPR6_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR6_PRI_3_Pos) /*!< PPB NVIC_IPR6: PRI_3 Mask */\r
+\r
+/* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */\r
+#define PPB_NVIC_IPR7_PRI_0_Pos 0 /*!< PPB NVIC_IPR7: PRI_0 Position */\r
+#define PPB_NVIC_IPR7_PRI_0_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_0_Pos) /*!< PPB NVIC_IPR7: PRI_0 Mask */\r
+#define PPB_NVIC_IPR7_PRI_1_Pos 8 /*!< PPB NVIC_IPR7: PRI_1 Position */\r
+#define PPB_NVIC_IPR7_PRI_1_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_1_Pos) /*!< PPB NVIC_IPR7: PRI_1 Mask */\r
+#define PPB_NVIC_IPR7_PRI_2_Pos 16 /*!< PPB NVIC_IPR7: PRI_2 Position */\r
+#define PPB_NVIC_IPR7_PRI_2_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_2_Pos) /*!< PPB NVIC_IPR7: PRI_2 Mask */\r
+#define PPB_NVIC_IPR7_PRI_3_Pos 24 /*!< PPB NVIC_IPR7: PRI_3 Position */\r
+#define PPB_NVIC_IPR7_PRI_3_Msk (0x000000ffUL << PPB_NVIC_IPR7_PRI_3_Pos) /*!< PPB NVIC_IPR7: PRI_3 Mask */\r
+\r
+/* ---------------------------------- PPB_CPUID --------------------------------- */\r
+#define PPB_CPUID_Revision_Pos 0 /*!< PPB CPUID: Revision Position */\r
+#define PPB_CPUID_Revision_Msk (0x0fUL << PPB_CPUID_Revision_Pos) /*!< PPB CPUID: Revision Mask */\r
+#define PPB_CPUID_PartNo_Pos 4 /*!< PPB CPUID: PartNo Position */\r
+#define PPB_CPUID_PartNo_Msk (0x00000fffUL << PPB_CPUID_PartNo_Pos) /*!< PPB CPUID: PartNo Mask */\r
+#define PPB_CPUID_Architecture_Pos 16 /*!< PPB CPUID: Architecture Position */\r
+#define PPB_CPUID_Architecture_Msk (0x0fUL << PPB_CPUID_Architecture_Pos) /*!< PPB CPUID: Architecture Mask */\r
+#define PPB_CPUID_Variant_Pos 20 /*!< PPB CPUID: Variant Position */\r
+#define PPB_CPUID_Variant_Msk (0x0fUL << PPB_CPUID_Variant_Pos) /*!< PPB CPUID: Variant Mask */\r
+#define PPB_CPUID_Implementer_Pos 24 /*!< PPB CPUID: Implementer Position */\r
+#define PPB_CPUID_Implementer_Msk (0x000000ffUL << PPB_CPUID_Implementer_Pos) /*!< PPB CPUID: Implementer Mask */\r
+\r
+/* ---------------------------------- PPB_ICSR ---------------------------------- */\r
+#define PPB_ICSR_VECTACTIVE_Pos 0 /*!< PPB ICSR: VECTACTIVE Position */\r
+#define PPB_ICSR_VECTACTIVE_Msk (0x3fUL << PPB_ICSR_VECTACTIVE_Pos) /*!< PPB ICSR: VECTACTIVE Mask */\r
+#define PPB_ICSR_VECTPENDING_Pos 12 /*!< PPB ICSR: VECTPENDING Position */\r
+#define PPB_ICSR_VECTPENDING_Msk (0x3fUL << PPB_ICSR_VECTPENDING_Pos) /*!< PPB ICSR: VECTPENDING Mask */\r
+#define PPB_ICSR_ISRPENDING_Pos 22 /*!< PPB ICSR: ISRPENDING Position */\r
+#define PPB_ICSR_ISRPENDING_Msk (0x01UL << PPB_ICSR_ISRPENDING_Pos) /*!< PPB ICSR: ISRPENDING Mask */\r
+#define PPB_ICSR_PENDSTCLR_Pos 25 /*!< PPB ICSR: PENDSTCLR Position */\r
+#define PPB_ICSR_PENDSTCLR_Msk (0x01UL << PPB_ICSR_PENDSTCLR_Pos) /*!< PPB ICSR: PENDSTCLR Mask */\r
+#define PPB_ICSR_PENDSTSET_Pos 26 /*!< PPB ICSR: PENDSTSET Position */\r
+#define PPB_ICSR_PENDSTSET_Msk (0x01UL << PPB_ICSR_PENDSTSET_Pos) /*!< PPB ICSR: PENDSTSET Mask */\r
+#define PPB_ICSR_PENDSVCLR_Pos 27 /*!< PPB ICSR: PENDSVCLR Position */\r
+#define PPB_ICSR_PENDSVCLR_Msk (0x01UL << PPB_ICSR_PENDSVCLR_Pos) /*!< PPB ICSR: PENDSVCLR Mask */\r
+#define PPB_ICSR_PENDSVSET_Pos 28 /*!< PPB ICSR: PENDSVSET Position */\r
+#define PPB_ICSR_PENDSVSET_Msk (0x01UL << PPB_ICSR_PENDSVSET_Pos) /*!< PPB ICSR: PENDSVSET Mask */\r
+\r
+/* ---------------------------------- PPB_AIRCR --------------------------------- */\r
+#define PPB_AIRCR_SYSRESETREQ_Pos 2 /*!< PPB AIRCR: SYSRESETREQ Position */\r
+#define PPB_AIRCR_SYSRESETREQ_Msk (0x01UL << PPB_AIRCR_SYSRESETREQ_Pos) /*!< PPB AIRCR: SYSRESETREQ Mask */\r
+#define PPB_AIRCR_ENDIANNESS_Pos 15 /*!< PPB AIRCR: ENDIANNESS Position */\r
+#define PPB_AIRCR_ENDIANNESS_Msk (0x01UL << PPB_AIRCR_ENDIANNESS_Pos) /*!< PPB AIRCR: ENDIANNESS Mask */\r
+#define PPB_AIRCR_VECTKEY_Pos 16 /*!< PPB AIRCR: VECTKEY Position */\r
+#define PPB_AIRCR_VECTKEY_Msk (0x0000ffffUL << PPB_AIRCR_VECTKEY_Pos) /*!< PPB AIRCR: VECTKEY Mask */\r
+\r
+/* ----------------------------------- PPB_SCR ---------------------------------- */\r
+#define PPB_SCR_SLEEPONEXIT_Pos 1 /*!< PPB SCR: SLEEPONEXIT Position */\r
+#define PPB_SCR_SLEEPONEXIT_Msk (0x01UL << PPB_SCR_SLEEPONEXIT_Pos) /*!< PPB SCR: SLEEPONEXIT Mask */\r
+#define PPB_SCR_SLEEPDEEP_Pos 2 /*!< PPB SCR: SLEEPDEEP Position */\r
+#define PPB_SCR_SLEEPDEEP_Msk (0x01UL << PPB_SCR_SLEEPDEEP_Pos) /*!< PPB SCR: SLEEPDEEP Mask */\r
+#define PPB_SCR_SEVONPEND_Pos 4 /*!< PPB SCR: SEVONPEND Position */\r
+#define PPB_SCR_SEVONPEND_Msk (0x01UL << PPB_SCR_SEVONPEND_Pos) /*!< PPB SCR: SEVONPEND Mask */\r
+\r
+/* ----------------------------------- PPB_CCR ---------------------------------- */\r
+#define PPB_CCR_UNALIGN_TRP_Pos 3 /*!< PPB CCR: UNALIGN_TRP Position */\r
+#define PPB_CCR_UNALIGN_TRP_Msk (0x01UL << PPB_CCR_UNALIGN_TRP_Pos) /*!< PPB CCR: UNALIGN_TRP Mask */\r
+#define PPB_CCR_STKALIGN_Pos 9 /*!< PPB CCR: STKALIGN Position */\r
+#define PPB_CCR_STKALIGN_Msk (0x01UL << PPB_CCR_STKALIGN_Pos) /*!< PPB CCR: STKALIGN Mask */\r
+\r
+/* ---------------------------------- PPB_SHPR2 --------------------------------- */\r
+#define PPB_SHPR2_PRI_11_Pos 24 /*!< PPB SHPR2: PRI_11 Position */\r
+#define PPB_SHPR2_PRI_11_Msk (0x000000ffUL << PPB_SHPR2_PRI_11_Pos) /*!< PPB SHPR2: PRI_11 Mask */\r
+\r
+/* ---------------------------------- PPB_SHPR3 --------------------------------- */\r
+#define PPB_SHPR3_PRI_14_Pos 16 /*!< PPB SHPR3: PRI_14 Position */\r
+#define PPB_SHPR3_PRI_14_Msk (0x000000ffUL << PPB_SHPR3_PRI_14_Pos) /*!< PPB SHPR3: PRI_14 Mask */\r
+#define PPB_SHPR3_PRI_15_Pos 24 /*!< PPB SHPR3: PRI_15 Position */\r
+#define PPB_SHPR3_PRI_15_Msk (0x000000ffUL << PPB_SHPR3_PRI_15_Pos) /*!< PPB SHPR3: PRI_15 Mask */\r
+\r
+/* ---------------------------------- PPB_SHCSR --------------------------------- */\r
+#define PPB_SHCSR_SVCALLPENDED_Pos 15 /*!< PPB SHCSR: SVCALLPENDED Position */\r
+#define PPB_SHCSR_SVCALLPENDED_Msk (0x01UL << PPB_SHCSR_SVCALLPENDED_Pos) /*!< PPB SHCSR: SVCALLPENDED Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'ERU' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- ERU_EXISEL --------------------------------- */\r
+#define ERU_EXISEL_EXS0A_Pos 0 /*!< ERU EXISEL: EXS0A Position */\r
+#define ERU_EXISEL_EXS0A_Msk (0x03UL << ERU_EXISEL_EXS0A_Pos) /*!< ERU EXISEL: EXS0A Mask */\r
+#define ERU_EXISEL_EXS0B_Pos 2 /*!< ERU EXISEL: EXS0B Position */\r
+#define ERU_EXISEL_EXS0B_Msk (0x03UL << ERU_EXISEL_EXS0B_Pos) /*!< ERU EXISEL: EXS0B Mask */\r
+#define ERU_EXISEL_EXS1A_Pos 4 /*!< ERU EXISEL: EXS1A Position */\r
+#define ERU_EXISEL_EXS1A_Msk (0x03UL << ERU_EXISEL_EXS1A_Pos) /*!< ERU EXISEL: EXS1A Mask */\r
+#define ERU_EXISEL_EXS1B_Pos 6 /*!< ERU EXISEL: EXS1B Position */\r
+#define ERU_EXISEL_EXS1B_Msk (0x03UL << ERU_EXISEL_EXS1B_Pos) /*!< ERU EXISEL: EXS1B Mask */\r
+#define ERU_EXISEL_EXS2A_Pos 8 /*!< ERU EXISEL: EXS2A Position */\r
+#define ERU_EXISEL_EXS2A_Msk (0x03UL << ERU_EXISEL_EXS2A_Pos) /*!< ERU EXISEL: EXS2A Mask */\r
+#define ERU_EXISEL_EXS2B_Pos 10 /*!< ERU EXISEL: EXS2B Position */\r
+#define ERU_EXISEL_EXS2B_Msk (0x03UL << ERU_EXISEL_EXS2B_Pos) /*!< ERU EXISEL: EXS2B Mask */\r
+#define ERU_EXISEL_EXS3A_Pos 12 /*!< ERU EXISEL: EXS3A Position */\r
+#define ERU_EXISEL_EXS3A_Msk (0x03UL << ERU_EXISEL_EXS3A_Pos) /*!< ERU EXISEL: EXS3A Mask */\r
+#define ERU_EXISEL_EXS3B_Pos 14 /*!< ERU EXISEL: EXS3B Position */\r
+#define ERU_EXISEL_EXS3B_Msk (0x03UL << ERU_EXISEL_EXS3B_Pos) /*!< ERU EXISEL: EXS3B Mask */\r
+\r
+/* --------------------------------- ERU_EXICON --------------------------------- */\r
+#define ERU_EXICON_PE_Pos 0 /*!< ERU EXICON: PE Position */\r
+#define ERU_EXICON_PE_Msk (0x01UL << ERU_EXICON_PE_Pos) /*!< ERU EXICON: PE Mask */\r
+#define ERU_EXICON_LD_Pos 1 /*!< ERU EXICON: LD Position */\r
+#define ERU_EXICON_LD_Msk (0x01UL << ERU_EXICON_LD_Pos) /*!< ERU EXICON: LD Mask */\r
+#define ERU_EXICON_RE_Pos 2 /*!< ERU EXICON: RE Position */\r
+#define ERU_EXICON_RE_Msk (0x01UL << ERU_EXICON_RE_Pos) /*!< ERU EXICON: RE Mask */\r
+#define ERU_EXICON_FE_Pos 3 /*!< ERU EXICON: FE Position */\r
+#define ERU_EXICON_FE_Msk (0x01UL << ERU_EXICON_FE_Pos) /*!< ERU EXICON: FE Mask */\r
+#define ERU_EXICON_OCS_Pos 4 /*!< ERU EXICON: OCS Position */\r
+#define ERU_EXICON_OCS_Msk (0x07UL << ERU_EXICON_OCS_Pos) /*!< ERU EXICON: OCS Mask */\r
+#define ERU_EXICON_FL_Pos 7 /*!< ERU EXICON: FL Position */\r
+#define ERU_EXICON_FL_Msk (0x01UL << ERU_EXICON_FL_Pos) /*!< ERU EXICON: FL Mask */\r
+#define ERU_EXICON_SS_Pos 8 /*!< ERU EXICON: SS Position */\r
+#define ERU_EXICON_SS_Msk (0x03UL << ERU_EXICON_SS_Pos) /*!< ERU EXICON: SS Mask */\r
+#define ERU_EXICON_NA_Pos 10 /*!< ERU EXICON: NA Position */\r
+#define ERU_EXICON_NA_Msk (0x01UL << ERU_EXICON_NA_Pos) /*!< ERU EXICON: NA Mask */\r
+#define ERU_EXICON_NB_Pos 11 /*!< ERU EXICON: NB Position */\r
+#define ERU_EXICON_NB_Msk (0x01UL << ERU_EXICON_NB_Pos) /*!< ERU EXICON: NB Mask */\r
+\r
+/* --------------------------------- ERU_EXOCON --------------------------------- */\r
+#define ERU_EXOCON_ISS_Pos 0 /*!< ERU EXOCON: ISS Position */\r
+#define ERU_EXOCON_ISS_Msk (0x03UL << ERU_EXOCON_ISS_Pos) /*!< ERU EXOCON: ISS Mask */\r
+#define ERU_EXOCON_GEEN_Pos 2 /*!< ERU EXOCON: GEEN Position */\r
+#define ERU_EXOCON_GEEN_Msk (0x01UL << ERU_EXOCON_GEEN_Pos) /*!< ERU EXOCON: GEEN Mask */\r
+#define ERU_EXOCON_PDR_Pos 3 /*!< ERU EXOCON: PDR Position */\r
+#define ERU_EXOCON_PDR_Msk (0x01UL << ERU_EXOCON_PDR_Pos) /*!< ERU EXOCON: PDR Mask */\r
+#define ERU_EXOCON_GP_Pos 4 /*!< ERU EXOCON: GP Position */\r
+#define ERU_EXOCON_GP_Msk (0x03UL << ERU_EXOCON_GP_Pos) /*!< ERU EXOCON: GP Mask */\r
+#define ERU_EXOCON_IPEN0_Pos 12 /*!< ERU EXOCON: IPEN0 Position */\r
+#define ERU_EXOCON_IPEN0_Msk (0x01UL << ERU_EXOCON_IPEN0_Pos) /*!< ERU EXOCON: IPEN0 Mask */\r
+#define ERU_EXOCON_IPEN1_Pos 13 /*!< ERU EXOCON: IPEN1 Position */\r
+#define ERU_EXOCON_IPEN1_Msk (0x01UL << ERU_EXOCON_IPEN1_Pos) /*!< ERU EXOCON: IPEN1 Mask */\r
+#define ERU_EXOCON_IPEN2_Pos 14 /*!< ERU EXOCON: IPEN2 Position */\r
+#define ERU_EXOCON_IPEN2_Msk (0x01UL << ERU_EXOCON_IPEN2_Pos) /*!< ERU EXOCON: IPEN2 Mask */\r
+#define ERU_EXOCON_IPEN3_Pos 15 /*!< ERU EXOCON: IPEN3 Position */\r
+#define ERU_EXOCON_IPEN3_Msk (0x01UL << ERU_EXOCON_IPEN3_Pos) /*!< ERU EXOCON: IPEN3 Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PAU' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- PAU_AVAIL0 --------------------------------- */\r
+#define PAU_AVAIL0_AVAIL22_Pos 22 /*!< PAU AVAIL0: AVAIL22 Position */\r
+#define PAU_AVAIL0_AVAIL22_Msk (0x01UL << PAU_AVAIL0_AVAIL22_Pos) /*!< PAU AVAIL0: AVAIL22 Mask */\r
+#define PAU_AVAIL0_AVAIL23_Pos 23 /*!< PAU AVAIL0: AVAIL23 Position */\r
+#define PAU_AVAIL0_AVAIL23_Msk (0x01UL << PAU_AVAIL0_AVAIL23_Pos) /*!< PAU AVAIL0: AVAIL23 Mask */\r
+#define PAU_AVAIL0_AVAIL24_Pos 24 /*!< PAU AVAIL0: AVAIL24 Position */\r
+#define PAU_AVAIL0_AVAIL24_Msk (0x01UL << PAU_AVAIL0_AVAIL24_Pos) /*!< PAU AVAIL0: AVAIL24 Mask */\r
+\r
+/* --------------------------------- PAU_AVAIL1 --------------------------------- */\r
+#define PAU_AVAIL1_AVAIL0_Pos 0 /*!< PAU AVAIL1: AVAIL0 Position */\r
+#define PAU_AVAIL1_AVAIL0_Msk (0x01UL << PAU_AVAIL1_AVAIL0_Pos) /*!< PAU AVAIL1: AVAIL0 Mask */\r
+#define PAU_AVAIL1_AVAIL1_Pos 1 /*!< PAU AVAIL1: AVAIL1 Position */\r
+#define PAU_AVAIL1_AVAIL1_Msk (0x01UL << PAU_AVAIL1_AVAIL1_Pos) /*!< PAU AVAIL1: AVAIL1 Mask */\r
+#define PAU_AVAIL1_AVAIL4_Pos 4 /*!< PAU AVAIL1: AVAIL4 Position */\r
+#define PAU_AVAIL1_AVAIL4_Msk (0x01UL << PAU_AVAIL1_AVAIL4_Pos) /*!< PAU AVAIL1: AVAIL4 Mask */\r
+#define PAU_AVAIL1_AVAIL5_Pos 5 /*!< PAU AVAIL1: AVAIL5 Position */\r
+#define PAU_AVAIL1_AVAIL5_Msk (0x01UL << PAU_AVAIL1_AVAIL5_Pos) /*!< PAU AVAIL1: AVAIL5 Mask */\r
+#define PAU_AVAIL1_AVAIL6_Pos 6 /*!< PAU AVAIL1: AVAIL6 Position */\r
+#define PAU_AVAIL1_AVAIL6_Msk (0x01UL << PAU_AVAIL1_AVAIL6_Pos) /*!< PAU AVAIL1: AVAIL6 Mask */\r
+#define PAU_AVAIL1_AVAIL7_Pos 7 /*!< PAU AVAIL1: AVAIL7 Position */\r
+#define PAU_AVAIL1_AVAIL7_Msk (0x01UL << PAU_AVAIL1_AVAIL7_Pos) /*!< PAU AVAIL1: AVAIL7 Mask */\r
+#define PAU_AVAIL1_AVAIL8_Pos 8 /*!< PAU AVAIL1: AVAIL8 Position */\r
+#define PAU_AVAIL1_AVAIL8_Msk (0x01UL << PAU_AVAIL1_AVAIL8_Pos) /*!< PAU AVAIL1: AVAIL8 Mask */\r
+#define PAU_AVAIL1_AVAIL9_Pos 9 /*!< PAU AVAIL1: AVAIL9 Position */\r
+#define PAU_AVAIL1_AVAIL9_Msk (0x01UL << PAU_AVAIL1_AVAIL9_Pos) /*!< PAU AVAIL1: AVAIL9 Mask */\r
+#define PAU_AVAIL1_AVAIL10_Pos 10 /*!< PAU AVAIL1: AVAIL10 Position */\r
+#define PAU_AVAIL1_AVAIL10_Msk (0x01UL << PAU_AVAIL1_AVAIL10_Pos) /*!< PAU AVAIL1: AVAIL10 Mask */\r
+#define PAU_AVAIL1_AVAIL11_Pos 11 /*!< PAU AVAIL1: AVAIL11 Position */\r
+#define PAU_AVAIL1_AVAIL11_Msk (0x01UL << PAU_AVAIL1_AVAIL11_Pos) /*!< PAU AVAIL1: AVAIL11 Mask */\r
+#define PAU_AVAIL1_AVAIL12_Pos 12 /*!< PAU AVAIL1: AVAIL12 Position */\r
+#define PAU_AVAIL1_AVAIL12_Msk (0x01UL << PAU_AVAIL1_AVAIL12_Pos) /*!< PAU AVAIL1: AVAIL12 Mask */\r
+\r
+/* --------------------------------- PAU_AVAIL2 --------------------------------- */\r
+#define PAU_AVAIL2_AVAIL13_Pos 13 /*!< PAU AVAIL2: AVAIL13 Position */\r
+#define PAU_AVAIL2_AVAIL13_Msk (0x01UL << PAU_AVAIL2_AVAIL13_Pos) /*!< PAU AVAIL2: AVAIL13 Mask */\r
+#define PAU_AVAIL2_AVAIL14_Pos 14 /*!< PAU AVAIL2: AVAIL14 Position */\r
+#define PAU_AVAIL2_AVAIL14_Msk (0x01UL << PAU_AVAIL2_AVAIL14_Pos) /*!< PAU AVAIL2: AVAIL14 Mask */\r
+#define PAU_AVAIL2_AVAIL15_Pos 15 /*!< PAU AVAIL2: AVAIL15 Position */\r
+#define PAU_AVAIL2_AVAIL15_Msk (0x01UL << PAU_AVAIL2_AVAIL15_Pos) /*!< PAU AVAIL2: AVAIL15 Mask */\r
+\r
+/* -------------------------------- PAU_PRIVDIS0 -------------------------------- */\r
+#define PAU_PRIVDIS0_PDIS2_Pos 2 /*!< PAU PRIVDIS0: PDIS2 Position */\r
+#define PAU_PRIVDIS0_PDIS2_Msk (0x01UL << PAU_PRIVDIS0_PDIS2_Pos) /*!< PAU PRIVDIS0: PDIS2 Mask */\r
+#define PAU_PRIVDIS0_PDIS5_Pos 5 /*!< PAU PRIVDIS0: PDIS5 Position */\r
+#define PAU_PRIVDIS0_PDIS5_Msk (0x01UL << PAU_PRIVDIS0_PDIS5_Pos) /*!< PAU PRIVDIS0: PDIS5 Mask */\r
+#define PAU_PRIVDIS0_PDIS6_Pos 6 /*!< PAU PRIVDIS0: PDIS6 Position */\r
+#define PAU_PRIVDIS0_PDIS6_Msk (0x01UL << PAU_PRIVDIS0_PDIS6_Pos) /*!< PAU PRIVDIS0: PDIS6 Mask */\r
+#define PAU_PRIVDIS0_PDIS7_Pos 7 /*!< PAU PRIVDIS0: PDIS7 Position */\r
+#define PAU_PRIVDIS0_PDIS7_Msk (0x01UL << PAU_PRIVDIS0_PDIS7_Pos) /*!< PAU PRIVDIS0: PDIS7 Mask */\r
+#define PAU_PRIVDIS0_PDIS19_Pos 19 /*!< PAU PRIVDIS0: PDIS19 Position */\r
+#define PAU_PRIVDIS0_PDIS19_Msk (0x01UL << PAU_PRIVDIS0_PDIS19_Pos) /*!< PAU PRIVDIS0: PDIS19 Mask */\r
+#define PAU_PRIVDIS0_PDIS22_Pos 22 /*!< PAU PRIVDIS0: PDIS22 Position */\r
+#define PAU_PRIVDIS0_PDIS22_Msk (0x01UL << PAU_PRIVDIS0_PDIS22_Pos) /*!< PAU PRIVDIS0: PDIS22 Mask */\r
+#define PAU_PRIVDIS0_PDIS23_Pos 23 /*!< PAU PRIVDIS0: PDIS23 Position */\r
+#define PAU_PRIVDIS0_PDIS23_Msk (0x01UL << PAU_PRIVDIS0_PDIS23_Pos) /*!< PAU PRIVDIS0: PDIS23 Mask */\r
+#define PAU_PRIVDIS0_PDIS24_Pos 24 /*!< PAU PRIVDIS0: PDIS24 Position */\r
+#define PAU_PRIVDIS0_PDIS24_Msk (0x01UL << PAU_PRIVDIS0_PDIS24_Pos) /*!< PAU PRIVDIS0: PDIS24 Mask */\r
+\r
+/* -------------------------------- PAU_PRIVDIS1 -------------------------------- */\r
+#define PAU_PRIVDIS1_PDIS0_Pos 0 /*!< PAU PRIVDIS1: PDIS0 Position */\r
+#define PAU_PRIVDIS1_PDIS0_Msk (0x01UL << PAU_PRIVDIS1_PDIS0_Pos) /*!< PAU PRIVDIS1: PDIS0 Mask */\r
+#define PAU_PRIVDIS1_PDIS1_Pos 1 /*!< PAU PRIVDIS1: PDIS1 Position */\r
+#define PAU_PRIVDIS1_PDIS1_Msk (0x01UL << PAU_PRIVDIS1_PDIS1_Pos) /*!< PAU PRIVDIS1: PDIS1 Mask */\r
+#define PAU_PRIVDIS1_PDIS5_Pos 5 /*!< PAU PRIVDIS1: PDIS5 Position */\r
+#define PAU_PRIVDIS1_PDIS5_Msk (0x01UL << PAU_PRIVDIS1_PDIS5_Pos) /*!< PAU PRIVDIS1: PDIS5 Mask */\r
+#define PAU_PRIVDIS1_PDIS6_Pos 6 /*!< PAU PRIVDIS1: PDIS6 Position */\r
+#define PAU_PRIVDIS1_PDIS6_Msk (0x01UL << PAU_PRIVDIS1_PDIS6_Pos) /*!< PAU PRIVDIS1: PDIS6 Mask */\r
+#define PAU_PRIVDIS1_PDIS7_Pos 7 /*!< PAU PRIVDIS1: PDIS7 Position */\r
+#define PAU_PRIVDIS1_PDIS7_Msk (0x01UL << PAU_PRIVDIS1_PDIS7_Pos) /*!< PAU PRIVDIS1: PDIS7 Mask */\r
+#define PAU_PRIVDIS1_PDIS8_Pos 8 /*!< PAU PRIVDIS1: PDIS8 Position */\r
+#define PAU_PRIVDIS1_PDIS8_Msk (0x01UL << PAU_PRIVDIS1_PDIS8_Pos) /*!< PAU PRIVDIS1: PDIS8 Mask */\r
+#define PAU_PRIVDIS1_PDIS9_Pos 9 /*!< PAU PRIVDIS1: PDIS9 Position */\r
+#define PAU_PRIVDIS1_PDIS9_Msk (0x01UL << PAU_PRIVDIS1_PDIS9_Pos) /*!< PAU PRIVDIS1: PDIS9 Mask */\r
+#define PAU_PRIVDIS1_PDIS10_Pos 10 /*!< PAU PRIVDIS1: PDIS10 Position */\r
+#define PAU_PRIVDIS1_PDIS10_Msk (0x01UL << PAU_PRIVDIS1_PDIS10_Pos) /*!< PAU PRIVDIS1: PDIS10 Mask */\r
+#define PAU_PRIVDIS1_PDIS11_Pos 11 /*!< PAU PRIVDIS1: PDIS11 Position */\r
+#define PAU_PRIVDIS1_PDIS11_Msk (0x01UL << PAU_PRIVDIS1_PDIS11_Pos) /*!< PAU PRIVDIS1: PDIS11 Mask */\r
+#define PAU_PRIVDIS1_PDIS12_Pos 12 /*!< PAU PRIVDIS1: PDIS12 Position */\r
+#define PAU_PRIVDIS1_PDIS12_Msk (0x01UL << PAU_PRIVDIS1_PDIS12_Pos) /*!< PAU PRIVDIS1: PDIS12 Mask */\r
+\r
+/* -------------------------------- PAU_PRIVDIS2 -------------------------------- */\r
+#define PAU_PRIVDIS2_PDIS13_Pos 13 /*!< PAU PRIVDIS2: PDIS13 Position */\r
+#define PAU_PRIVDIS2_PDIS13_Msk (0x01UL << PAU_PRIVDIS2_PDIS13_Pos) /*!< PAU PRIVDIS2: PDIS13 Mask */\r
+#define PAU_PRIVDIS2_PDIS14_Pos 14 /*!< PAU PRIVDIS2: PDIS14 Position */\r
+#define PAU_PRIVDIS2_PDIS14_Msk (0x01UL << PAU_PRIVDIS2_PDIS14_Pos) /*!< PAU PRIVDIS2: PDIS14 Mask */\r
+#define PAU_PRIVDIS2_PDIS15_Pos 15 /*!< PAU PRIVDIS2: PDIS15 Position */\r
+#define PAU_PRIVDIS2_PDIS15_Msk (0x01UL << PAU_PRIVDIS2_PDIS15_Pos) /*!< PAU PRIVDIS2: PDIS15 Mask */\r
+\r
+/* --------------------------------- PAU_ROMSIZE -------------------------------- */\r
+#define PAU_ROMSIZE_ADDR_Pos 8 /*!< PAU ROMSIZE: ADDR Position */\r
+#define PAU_ROMSIZE_ADDR_Msk (0x3fUL << PAU_ROMSIZE_ADDR_Pos) /*!< PAU ROMSIZE: ADDR Mask */\r
+\r
+/* --------------------------------- PAU_FLSIZE --------------------------------- */\r
+#define PAU_FLSIZE_ADDR_Pos 12 /*!< PAU FLSIZE: ADDR Position */\r
+#define PAU_FLSIZE_ADDR_Msk (0x3fUL << PAU_FLSIZE_ADDR_Pos) /*!< PAU FLSIZE: ADDR Mask */\r
+\r
+/* -------------------------------- PAU_RAM0SIZE -------------------------------- */\r
+#define PAU_RAM0SIZE_ADDR_Pos 8 /*!< PAU RAM0SIZE: ADDR Position */\r
+#define PAU_RAM0SIZE_ADDR_Msk (0x1fUL << PAU_RAM0SIZE_ADDR_Pos) /*!< PAU RAM0SIZE: ADDR Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'NVM' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- NVM_NVMSTATUS ------------------------------- */\r
+#define NVM_NVMSTATUS_BUSY_Pos 0 /*!< NVM NVMSTATUS: BUSY Position */\r
+#define NVM_NVMSTATUS_BUSY_Msk (0x01UL << NVM_NVMSTATUS_BUSY_Pos) /*!< NVM NVMSTATUS: BUSY Mask */\r
+#define NVM_NVMSTATUS_SLEEP_Pos 1 /*!< NVM NVMSTATUS: SLEEP Position */\r
+#define NVM_NVMSTATUS_SLEEP_Msk (0x01UL << NVM_NVMSTATUS_SLEEP_Pos) /*!< NVM NVMSTATUS: SLEEP Mask */\r
+#define NVM_NVMSTATUS_VERR_Pos 2 /*!< NVM NVMSTATUS: VERR Position */\r
+#define NVM_NVMSTATUS_VERR_Msk (0x03UL << NVM_NVMSTATUS_VERR_Pos) /*!< NVM NVMSTATUS: VERR Mask */\r
+#define NVM_NVMSTATUS_ECC1READ_Pos 4 /*!< NVM NVMSTATUS: ECC1READ Position */\r
+#define NVM_NVMSTATUS_ECC1READ_Msk (0x01UL << NVM_NVMSTATUS_ECC1READ_Pos) /*!< NVM NVMSTATUS: ECC1READ Mask */\r
+#define NVM_NVMSTATUS_ECC2READ_Pos 5 /*!< NVM NVMSTATUS: ECC2READ Position */\r
+#define NVM_NVMSTATUS_ECC2READ_Msk (0x01UL << NVM_NVMSTATUS_ECC2READ_Pos) /*!< NVM NVMSTATUS: ECC2READ Mask */\r
+#define NVM_NVMSTATUS_WRPERR_Pos 6 /*!< NVM NVMSTATUS: WRPERR Position */\r
+#define NVM_NVMSTATUS_WRPERR_Msk (0x01UL << NVM_NVMSTATUS_WRPERR_Pos) /*!< NVM NVMSTATUS: WRPERR Mask */\r
+\r
+/* --------------------------------- NVM_NVMPROG -------------------------------- */\r
+#define NVM_NVMPROG_ACTION_Pos 0 /*!< NVM NVMPROG: ACTION Position */\r
+#define NVM_NVMPROG_ACTION_Msk (0x000000ffUL << NVM_NVMPROG_ACTION_Pos) /*!< NVM NVMPROG: ACTION Mask */\r
+#define NVM_NVMPROG_RSTVERR_Pos 12 /*!< NVM NVMPROG: RSTVERR Position */\r
+#define NVM_NVMPROG_RSTVERR_Msk (0x01UL << NVM_NVMPROG_RSTVERR_Pos) /*!< NVM NVMPROG: RSTVERR Mask */\r
+#define NVM_NVMPROG_RSTECC_Pos 13 /*!< NVM NVMPROG: RSTECC Position */\r
+#define NVM_NVMPROG_RSTECC_Msk (0x01UL << NVM_NVMPROG_RSTECC_Pos) /*!< NVM NVMPROG: RSTECC Mask */\r
+\r
+/* --------------------------------- NVM_NVMCONF -------------------------------- */\r
+#define NVM_NVMCONF_HRLEV_Pos 1 /*!< NVM NVMCONF: HRLEV Position */\r
+#define NVM_NVMCONF_HRLEV_Msk (0x03UL << NVM_NVMCONF_HRLEV_Pos) /*!< NVM NVMCONF: HRLEV Mask */\r
+#define NVM_NVMCONF_SECPROT_Pos 4 /*!< NVM NVMCONF: SECPROT Position */\r
+#define NVM_NVMCONF_SECPROT_Msk (0x000000ffUL << NVM_NVMCONF_SECPROT_Pos) /*!< NVM NVMCONF: SECPROT Mask */\r
+#define NVM_NVMCONF_INT_ON_Pos 14 /*!< NVM NVMCONF: INT_ON Position */\r
+#define NVM_NVMCONF_INT_ON_Msk (0x01UL << NVM_NVMCONF_INT_ON_Pos) /*!< NVM NVMCONF: INT_ON Mask */\r
+#define NVM_NVMCONF_NVM_ON_Pos 15 /*!< NVM NVMCONF: NVM_ON Position */\r
+#define NVM_NVMCONF_NVM_ON_Msk (0x01UL << NVM_NVMCONF_NVM_ON_Pos) /*!< NVM NVMCONF: NVM_ON Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'WDT' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------- WDT_ID ----------------------------------- */\r
+#define WDT_ID_MOD_REV_Pos 0 /*!< WDT ID: MOD_REV Position */\r
+#define WDT_ID_MOD_REV_Msk (0x000000ffUL << WDT_ID_MOD_REV_Pos) /*!< WDT ID: MOD_REV Mask */\r
+#define WDT_ID_MOD_TYPE_Pos 8 /*!< WDT ID: MOD_TYPE Position */\r
+#define WDT_ID_MOD_TYPE_Msk (0x000000ffUL << WDT_ID_MOD_TYPE_Pos) /*!< WDT ID: MOD_TYPE Mask */\r
+#define WDT_ID_MOD_NUMBER_Pos 16 /*!< WDT ID: MOD_NUMBER Position */\r
+#define WDT_ID_MOD_NUMBER_Msk (0x0000ffffUL << WDT_ID_MOD_NUMBER_Pos) /*!< WDT ID: MOD_NUMBER Mask */\r
+\r
+/* ----------------------------------- WDT_CTR ---------------------------------- */\r
+#define WDT_CTR_ENB_Pos 0 /*!< WDT CTR: ENB Position */\r
+#define WDT_CTR_ENB_Msk (0x01UL << WDT_CTR_ENB_Pos) /*!< WDT CTR: ENB Mask */\r
+#define WDT_CTR_PRE_Pos 1 /*!< WDT CTR: PRE Position */\r
+#define WDT_CTR_PRE_Msk (0x01UL << WDT_CTR_PRE_Pos) /*!< WDT CTR: PRE Mask */\r
+#define WDT_CTR_DSP_Pos 4 /*!< WDT CTR: DSP Position */\r
+#define WDT_CTR_DSP_Msk (0x01UL << WDT_CTR_DSP_Pos) /*!< WDT CTR: DSP Mask */\r
+#define WDT_CTR_SPW_Pos 8 /*!< WDT CTR: SPW Position */\r
+#define WDT_CTR_SPW_Msk (0x000000ffUL << WDT_CTR_SPW_Pos) /*!< WDT CTR: SPW Mask */\r
+\r
+/* ----------------------------------- WDT_SRV ---------------------------------- */\r
+#define WDT_SRV_SRV_Pos 0 /*!< WDT SRV: SRV Position */\r
+#define WDT_SRV_SRV_Msk (0xffffffffUL << WDT_SRV_SRV_Pos) /*!< WDT SRV: SRV Mask */\r
+\r
+/* ----------------------------------- WDT_TIM ---------------------------------- */\r
+#define WDT_TIM_TIM_Pos 0 /*!< WDT TIM: TIM Position */\r
+#define WDT_TIM_TIM_Msk (0xffffffffUL << WDT_TIM_TIM_Pos) /*!< WDT TIM: TIM Mask */\r
+\r
+/* ----------------------------------- WDT_WLB ---------------------------------- */\r
+#define WDT_WLB_WLB_Pos 0 /*!< WDT WLB: WLB Position */\r
+#define WDT_WLB_WLB_Msk (0xffffffffUL << WDT_WLB_WLB_Pos) /*!< WDT WLB: WLB Mask */\r
+\r
+/* ----------------------------------- WDT_WUB ---------------------------------- */\r
+#define WDT_WUB_WUB_Pos 0 /*!< WDT WUB: WUB Position */\r
+#define WDT_WUB_WUB_Msk (0xffffffffUL << WDT_WUB_WUB_Pos) /*!< WDT WUB: WUB Mask */\r
+\r
+/* --------------------------------- WDT_WDTSTS --------------------------------- */\r
+#define WDT_WDTSTS_ALMS_Pos 0 /*!< WDT WDTSTS: ALMS Position */\r
+#define WDT_WDTSTS_ALMS_Msk (0x01UL << WDT_WDTSTS_ALMS_Pos) /*!< WDT WDTSTS: ALMS Mask */\r
+\r
+/* --------------------------------- WDT_WDTCLR --------------------------------- */\r
+#define WDT_WDTCLR_ALMC_Pos 0 /*!< WDT WDTCLR: ALMC Position */\r
+#define WDT_WDTCLR_ALMC_Msk (0x01UL << WDT_WDTCLR_ALMC_Pos) /*!< WDT WDTCLR: ALMC Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'RTC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------- RTC_ID ----------------------------------- */\r
+#define RTC_ID_MOD_REV_Pos 0 /*!< RTC ID: MOD_REV Position */\r
+#define RTC_ID_MOD_REV_Msk (0x000000ffUL << RTC_ID_MOD_REV_Pos) /*!< RTC ID: MOD_REV Mask */\r
+#define RTC_ID_MOD_TYPE_Pos 8 /*!< RTC ID: MOD_TYPE Position */\r
+#define RTC_ID_MOD_TYPE_Msk (0x000000ffUL << RTC_ID_MOD_TYPE_Pos) /*!< RTC ID: MOD_TYPE Mask */\r
+#define RTC_ID_MOD_NUMBER_Pos 16 /*!< RTC ID: MOD_NUMBER Position */\r
+#define RTC_ID_MOD_NUMBER_Msk (0x0000ffffUL << RTC_ID_MOD_NUMBER_Pos) /*!< RTC ID: MOD_NUMBER Mask */\r
+\r
+/* ----------------------------------- RTC_CTR ---------------------------------- */\r
+#define RTC_CTR_ENB_Pos 0 /*!< RTC CTR: ENB Position */\r
+#define RTC_CTR_ENB_Msk (0x01UL << RTC_CTR_ENB_Pos) /*!< RTC CTR: ENB Mask */\r
+#define RTC_CTR_SUS_Pos 1 /*!< RTC CTR: SUS Position */\r
+#define RTC_CTR_SUS_Msk (0x01UL << RTC_CTR_SUS_Pos) /*!< RTC CTR: SUS Mask */\r
+#define RTC_CTR_DIV_Pos 16 /*!< RTC CTR: DIV Position */\r
+#define RTC_CTR_DIV_Msk (0x0000ffffUL << RTC_CTR_DIV_Pos) /*!< RTC CTR: DIV Mask */\r
+\r
+/* --------------------------------- RTC_RAWSTAT -------------------------------- */\r
+#define RTC_RAWSTAT_RPSE_Pos 0 /*!< RTC RAWSTAT: RPSE Position */\r
+#define RTC_RAWSTAT_RPSE_Msk (0x01UL << RTC_RAWSTAT_RPSE_Pos) /*!< RTC RAWSTAT: RPSE Mask */\r
+#define RTC_RAWSTAT_RPMI_Pos 1 /*!< RTC RAWSTAT: RPMI Position */\r
+#define RTC_RAWSTAT_RPMI_Msk (0x01UL << RTC_RAWSTAT_RPMI_Pos) /*!< RTC RAWSTAT: RPMI Mask */\r
+#define RTC_RAWSTAT_RPHO_Pos 2 /*!< RTC RAWSTAT: RPHO Position */\r
+#define RTC_RAWSTAT_RPHO_Msk (0x01UL << RTC_RAWSTAT_RPHO_Pos) /*!< RTC RAWSTAT: RPHO Mask */\r
+#define RTC_RAWSTAT_RPDA_Pos 3 /*!< RTC RAWSTAT: RPDA Position */\r
+#define RTC_RAWSTAT_RPDA_Msk (0x01UL << RTC_RAWSTAT_RPDA_Pos) /*!< RTC RAWSTAT: RPDA Mask */\r
+#define RTC_RAWSTAT_RPMO_Pos 5 /*!< RTC RAWSTAT: RPMO Position */\r
+#define RTC_RAWSTAT_RPMO_Msk (0x01UL << RTC_RAWSTAT_RPMO_Pos) /*!< RTC RAWSTAT: RPMO Mask */\r
+#define RTC_RAWSTAT_RPYE_Pos 6 /*!< RTC RAWSTAT: RPYE Position */\r
+#define RTC_RAWSTAT_RPYE_Msk (0x01UL << RTC_RAWSTAT_RPYE_Pos) /*!< RTC RAWSTAT: RPYE Mask */\r
+#define RTC_RAWSTAT_RAI_Pos 8 /*!< RTC RAWSTAT: RAI Position */\r
+#define RTC_RAWSTAT_RAI_Msk (0x01UL << RTC_RAWSTAT_RAI_Pos) /*!< RTC RAWSTAT: RAI Mask */\r
+\r
+/* ---------------------------------- RTC_STSSR --------------------------------- */\r
+#define RTC_STSSR_SPSE_Pos 0 /*!< RTC STSSR: SPSE Position */\r
+#define RTC_STSSR_SPSE_Msk (0x01UL << RTC_STSSR_SPSE_Pos) /*!< RTC STSSR: SPSE Mask */\r
+#define RTC_STSSR_SPMI_Pos 1 /*!< RTC STSSR: SPMI Position */\r
+#define RTC_STSSR_SPMI_Msk (0x01UL << RTC_STSSR_SPMI_Pos) /*!< RTC STSSR: SPMI Mask */\r
+#define RTC_STSSR_SPHO_Pos 2 /*!< RTC STSSR: SPHO Position */\r
+#define RTC_STSSR_SPHO_Msk (0x01UL << RTC_STSSR_SPHO_Pos) /*!< RTC STSSR: SPHO Mask */\r
+#define RTC_STSSR_SPDA_Pos 3 /*!< RTC STSSR: SPDA Position */\r
+#define RTC_STSSR_SPDA_Msk (0x01UL << RTC_STSSR_SPDA_Pos) /*!< RTC STSSR: SPDA Mask */\r
+#define RTC_STSSR_SPMO_Pos 5 /*!< RTC STSSR: SPMO Position */\r
+#define RTC_STSSR_SPMO_Msk (0x01UL << RTC_STSSR_SPMO_Pos) /*!< RTC STSSR: SPMO Mask */\r
+#define RTC_STSSR_SPYE_Pos 6 /*!< RTC STSSR: SPYE Position */\r
+#define RTC_STSSR_SPYE_Msk (0x01UL << RTC_STSSR_SPYE_Pos) /*!< RTC STSSR: SPYE Mask */\r
+#define RTC_STSSR_SAI_Pos 8 /*!< RTC STSSR: SAI Position */\r
+#define RTC_STSSR_SAI_Msk (0x01UL << RTC_STSSR_SAI_Pos) /*!< RTC STSSR: SAI Mask */\r
+\r
+/* ---------------------------------- RTC_MSKSR --------------------------------- */\r
+#define RTC_MSKSR_MPSE_Pos 0 /*!< RTC MSKSR: MPSE Position */\r
+#define RTC_MSKSR_MPSE_Msk (0x01UL << RTC_MSKSR_MPSE_Pos) /*!< RTC MSKSR: MPSE Mask */\r
+#define RTC_MSKSR_MPMI_Pos 1 /*!< RTC MSKSR: MPMI Position */\r
+#define RTC_MSKSR_MPMI_Msk (0x01UL << RTC_MSKSR_MPMI_Pos) /*!< RTC MSKSR: MPMI Mask */\r
+#define RTC_MSKSR_MPHO_Pos 2 /*!< RTC MSKSR: MPHO Position */\r
+#define RTC_MSKSR_MPHO_Msk (0x01UL << RTC_MSKSR_MPHO_Pos) /*!< RTC MSKSR: MPHO Mask */\r
+#define RTC_MSKSR_MPDA_Pos 3 /*!< RTC MSKSR: MPDA Position */\r
+#define RTC_MSKSR_MPDA_Msk (0x01UL << RTC_MSKSR_MPDA_Pos) /*!< RTC MSKSR: MPDA Mask */\r
+#define RTC_MSKSR_MPMO_Pos 5 /*!< RTC MSKSR: MPMO Position */\r
+#define RTC_MSKSR_MPMO_Msk (0x01UL << RTC_MSKSR_MPMO_Pos) /*!< RTC MSKSR: MPMO Mask */\r
+#define RTC_MSKSR_MPYE_Pos 6 /*!< RTC MSKSR: MPYE Position */\r
+#define RTC_MSKSR_MPYE_Msk (0x01UL << RTC_MSKSR_MPYE_Pos) /*!< RTC MSKSR: MPYE Mask */\r
+#define RTC_MSKSR_MAI_Pos 8 /*!< RTC MSKSR: MAI Position */\r
+#define RTC_MSKSR_MAI_Msk (0x01UL << RTC_MSKSR_MAI_Pos) /*!< RTC MSKSR: MAI Mask */\r
+\r
+/* ---------------------------------- RTC_CLRSR --------------------------------- */\r
+#define RTC_CLRSR_RPSE_Pos 0 /*!< RTC CLRSR: RPSE Position */\r
+#define RTC_CLRSR_RPSE_Msk (0x01UL << RTC_CLRSR_RPSE_Pos) /*!< RTC CLRSR: RPSE Mask */\r
+#define RTC_CLRSR_RPMI_Pos 1 /*!< RTC CLRSR: RPMI Position */\r
+#define RTC_CLRSR_RPMI_Msk (0x01UL << RTC_CLRSR_RPMI_Pos) /*!< RTC CLRSR: RPMI Mask */\r
+#define RTC_CLRSR_RPHO_Pos 2 /*!< RTC CLRSR: RPHO Position */\r
+#define RTC_CLRSR_RPHO_Msk (0x01UL << RTC_CLRSR_RPHO_Pos) /*!< RTC CLRSR: RPHO Mask */\r
+#define RTC_CLRSR_RPDA_Pos 3 /*!< RTC CLRSR: RPDA Position */\r
+#define RTC_CLRSR_RPDA_Msk (0x01UL << RTC_CLRSR_RPDA_Pos) /*!< RTC CLRSR: RPDA Mask */\r
+#define RTC_CLRSR_RPMO_Pos 5 /*!< RTC CLRSR: RPMO Position */\r
+#define RTC_CLRSR_RPMO_Msk (0x01UL << RTC_CLRSR_RPMO_Pos) /*!< RTC CLRSR: RPMO Mask */\r
+#define RTC_CLRSR_RPYE_Pos 6 /*!< RTC CLRSR: RPYE Position */\r
+#define RTC_CLRSR_RPYE_Msk (0x01UL << RTC_CLRSR_RPYE_Pos) /*!< RTC CLRSR: RPYE Mask */\r
+#define RTC_CLRSR_RAI_Pos 8 /*!< RTC CLRSR: RAI Position */\r
+#define RTC_CLRSR_RAI_Msk (0x01UL << RTC_CLRSR_RAI_Pos) /*!< RTC CLRSR: RAI Mask */\r
+\r
+/* ---------------------------------- RTC_ATIM0 --------------------------------- */\r
+#define RTC_ATIM0_ASE_Pos 0 /*!< RTC ATIM0: ASE Position */\r
+#define RTC_ATIM0_ASE_Msk (0x3fUL << RTC_ATIM0_ASE_Pos) /*!< RTC ATIM0: ASE Mask */\r
+#define RTC_ATIM0_AMI_Pos 8 /*!< RTC ATIM0: AMI Position */\r
+#define RTC_ATIM0_AMI_Msk (0x3fUL << RTC_ATIM0_AMI_Pos) /*!< RTC ATIM0: AMI Mask */\r
+#define RTC_ATIM0_AHO_Pos 16 /*!< RTC ATIM0: AHO Position */\r
+#define RTC_ATIM0_AHO_Msk (0x1fUL << RTC_ATIM0_AHO_Pos) /*!< RTC ATIM0: AHO Mask */\r
+#define RTC_ATIM0_ADA_Pos 24 /*!< RTC ATIM0: ADA Position */\r
+#define RTC_ATIM0_ADA_Msk (0x1fUL << RTC_ATIM0_ADA_Pos) /*!< RTC ATIM0: ADA Mask */\r
+\r
+/* ---------------------------------- RTC_ATIM1 --------------------------------- */\r
+#define RTC_ATIM1_AMO_Pos 8 /*!< RTC ATIM1: AMO Position */\r
+#define RTC_ATIM1_AMO_Msk (0x0fUL << RTC_ATIM1_AMO_Pos) /*!< RTC ATIM1: AMO Mask */\r
+#define RTC_ATIM1_AYE_Pos 16 /*!< RTC ATIM1: AYE Position */\r
+#define RTC_ATIM1_AYE_Msk (0x0000ffffUL << RTC_ATIM1_AYE_Pos) /*!< RTC ATIM1: AYE Mask */\r
+\r
+/* ---------------------------------- RTC_TIM0 ---------------------------------- */\r
+#define RTC_TIM0_SE_Pos 0 /*!< RTC TIM0: SE Position */\r
+#define RTC_TIM0_SE_Msk (0x3fUL << RTC_TIM0_SE_Pos) /*!< RTC TIM0: SE Mask */\r
+#define RTC_TIM0_MI_Pos 8 /*!< RTC TIM0: MI Position */\r
+#define RTC_TIM0_MI_Msk (0x3fUL << RTC_TIM0_MI_Pos) /*!< RTC TIM0: MI Mask */\r
+#define RTC_TIM0_HO_Pos 16 /*!< RTC TIM0: HO Position */\r
+#define RTC_TIM0_HO_Msk (0x1fUL << RTC_TIM0_HO_Pos) /*!< RTC TIM0: HO Mask */\r
+#define RTC_TIM0_DA_Pos 24 /*!< RTC TIM0: DA Position */\r
+#define RTC_TIM0_DA_Msk (0x1fUL << RTC_TIM0_DA_Pos) /*!< RTC TIM0: DA Mask */\r
+\r
+/* ---------------------------------- RTC_TIM1 ---------------------------------- */\r
+#define RTC_TIM1_DAWE_Pos 0 /*!< RTC TIM1: DAWE Position */\r
+#define RTC_TIM1_DAWE_Msk (0x07UL << RTC_TIM1_DAWE_Pos) /*!< RTC TIM1: DAWE Mask */\r
+#define RTC_TIM1_MO_Pos 8 /*!< RTC TIM1: MO Position */\r
+#define RTC_TIM1_MO_Msk (0x0fUL << RTC_TIM1_MO_Pos) /*!< RTC TIM1: MO Mask */\r
+#define RTC_TIM1_YE_Pos 16 /*!< RTC TIM1: YE Position */\r
+#define RTC_TIM1_YE_Msk (0x0000ffffUL << RTC_TIM1_YE_Pos) /*!< RTC TIM1: YE Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PRNG' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- PRNG_WORD --------------------------------- */\r
+#define PRNG_WORD_RDATA_Pos 0 /*!< PRNG WORD: RDATA Position */\r
+#define PRNG_WORD_RDATA_Msk (0x0000ffffUL << PRNG_WORD_RDATA_Pos) /*!< PRNG WORD: RDATA Mask */\r
+\r
+/* ---------------------------------- PRNG_CHK ---------------------------------- */\r
+#define PRNG_CHK_RDV_Pos 0 /*!< PRNG CHK: RDV Position */\r
+#define PRNG_CHK_RDV_Msk (0x01UL << PRNG_CHK_RDV_Pos) /*!< PRNG CHK: RDV Mask */\r
+\r
+/* ---------------------------------- PRNG_CTRL --------------------------------- */\r
+#define PRNG_CTRL_RDBS_Pos 1 /*!< PRNG CTRL: RDBS Position */\r
+#define PRNG_CTRL_RDBS_Msk (0x03UL << PRNG_CTRL_RDBS_Pos) /*!< PRNG CTRL: RDBS Mask */\r
+#define PRNG_CTRL_KLD_Pos 3 /*!< PRNG CTRL: KLD Position */\r
+#define PRNG_CTRL_KLD_Msk (0x01UL << PRNG_CTRL_KLD_Pos) /*!< PRNG CTRL: KLD Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'LEDTS' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- LEDTS_ID ---------------------------------- */\r
+#define LEDTS_ID_MOD_REV_Pos 0 /*!< LEDTS ID: MOD_REV Position */\r
+#define LEDTS_ID_MOD_REV_Msk (0x000000ffUL << LEDTS_ID_MOD_REV_Pos) /*!< LEDTS ID: MOD_REV Mask */\r
+#define LEDTS_ID_MOD_TYPE_Pos 8 /*!< LEDTS ID: MOD_TYPE Position */\r
+#define LEDTS_ID_MOD_TYPE_Msk (0x000000ffUL << LEDTS_ID_MOD_TYPE_Pos) /*!< LEDTS ID: MOD_TYPE Mask */\r
+#define LEDTS_ID_MOD_NUMBER_Pos 16 /*!< LEDTS ID: MOD_NUMBER Position */\r
+#define LEDTS_ID_MOD_NUMBER_Msk (0x0000ffffUL << LEDTS_ID_MOD_NUMBER_Pos) /*!< LEDTS ID: MOD_NUMBER Mask */\r
+\r
+/* -------------------------------- LEDTS_GLOBCTL ------------------------------- */\r
+#define LEDTS_GLOBCTL_TS_EN_Pos 0 /*!< LEDTS GLOBCTL: TS_EN Position */\r
+#define LEDTS_GLOBCTL_TS_EN_Msk (0x01UL << LEDTS_GLOBCTL_TS_EN_Pos) /*!< LEDTS GLOBCTL: TS_EN Mask */\r
+#define LEDTS_GLOBCTL_LD_EN_Pos 1 /*!< LEDTS GLOBCTL: LD_EN Position */\r
+#define LEDTS_GLOBCTL_LD_EN_Msk (0x01UL << LEDTS_GLOBCTL_LD_EN_Pos) /*!< LEDTS GLOBCTL: LD_EN Mask */\r
+#define LEDTS_GLOBCTL_CMTR_Pos 2 /*!< LEDTS GLOBCTL: CMTR Position */\r
+#define LEDTS_GLOBCTL_CMTR_Msk (0x01UL << LEDTS_GLOBCTL_CMTR_Pos) /*!< LEDTS GLOBCTL: CMTR Mask */\r
+#define LEDTS_GLOBCTL_ENSYNC_Pos 3 /*!< LEDTS GLOBCTL: ENSYNC Position */\r
+#define LEDTS_GLOBCTL_ENSYNC_Msk (0x01UL << LEDTS_GLOBCTL_ENSYNC_Pos) /*!< LEDTS GLOBCTL: ENSYNC Mask */\r
+#define LEDTS_GLOBCTL_SUSCFG_Pos 8 /*!< LEDTS GLOBCTL: SUSCFG Position */\r
+#define LEDTS_GLOBCTL_SUSCFG_Msk (0x01UL << LEDTS_GLOBCTL_SUSCFG_Pos) /*!< LEDTS GLOBCTL: SUSCFG Mask */\r
+#define LEDTS_GLOBCTL_MASKVAL_Pos 9 /*!< LEDTS GLOBCTL: MASKVAL Position */\r
+#define LEDTS_GLOBCTL_MASKVAL_Msk (0x07UL << LEDTS_GLOBCTL_MASKVAL_Pos) /*!< LEDTS GLOBCTL: MASKVAL Mask */\r
+#define LEDTS_GLOBCTL_FENVAL_Pos 12 /*!< LEDTS GLOBCTL: FENVAL Position */\r
+#define LEDTS_GLOBCTL_FENVAL_Msk (0x01UL << LEDTS_GLOBCTL_FENVAL_Pos) /*!< LEDTS GLOBCTL: FENVAL Mask */\r
+#define LEDTS_GLOBCTL_ITS_EN_Pos 13 /*!< LEDTS GLOBCTL: ITS_EN Position */\r
+#define LEDTS_GLOBCTL_ITS_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITS_EN_Pos) /*!< LEDTS GLOBCTL: ITS_EN Mask */\r
+#define LEDTS_GLOBCTL_ITF_EN_Pos 14 /*!< LEDTS GLOBCTL: ITF_EN Position */\r
+#define LEDTS_GLOBCTL_ITF_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITF_EN_Pos) /*!< LEDTS GLOBCTL: ITF_EN Mask */\r
+#define LEDTS_GLOBCTL_ITP_EN_Pos 15 /*!< LEDTS GLOBCTL: ITP_EN Position */\r
+#define LEDTS_GLOBCTL_ITP_EN_Msk (0x01UL << LEDTS_GLOBCTL_ITP_EN_Pos) /*!< LEDTS GLOBCTL: ITP_EN Mask */\r
+#define LEDTS_GLOBCTL_CLK_PS_Pos 16 /*!< LEDTS GLOBCTL: CLK_PS Position */\r
+#define LEDTS_GLOBCTL_CLK_PS_Msk (0x0000ffffUL << LEDTS_GLOBCTL_CLK_PS_Pos) /*!< LEDTS GLOBCTL: CLK_PS Mask */\r
+\r
+/* --------------------------------- LEDTS_FNCTL -------------------------------- */\r
+#define LEDTS_FNCTL_PADT_Pos 0 /*!< LEDTS FNCTL: PADT Position */\r
+#define LEDTS_FNCTL_PADT_Msk (0x07UL << LEDTS_FNCTL_PADT_Pos) /*!< LEDTS FNCTL: PADT Mask */\r
+#define LEDTS_FNCTL_PADTSW_Pos 3 /*!< LEDTS FNCTL: PADTSW Position */\r
+#define LEDTS_FNCTL_PADTSW_Msk (0x01UL << LEDTS_FNCTL_PADTSW_Pos) /*!< LEDTS FNCTL: PADTSW Mask */\r
+#define LEDTS_FNCTL_EPULL_Pos 4 /*!< LEDTS FNCTL: EPULL Position */\r
+#define LEDTS_FNCTL_EPULL_Msk (0x01UL << LEDTS_FNCTL_EPULL_Pos) /*!< LEDTS FNCTL: EPULL Mask */\r
+#define LEDTS_FNCTL_FNCOL_Pos 5 /*!< LEDTS FNCTL: FNCOL Position */\r
+#define LEDTS_FNCTL_FNCOL_Msk (0x07UL << LEDTS_FNCTL_FNCOL_Pos) /*!< LEDTS FNCTL: FNCOL Mask */\r
+#define LEDTS_FNCTL_ACCCNT_Pos 16 /*!< LEDTS FNCTL: ACCCNT Position */\r
+#define LEDTS_FNCTL_ACCCNT_Msk (0x0fUL << LEDTS_FNCTL_ACCCNT_Pos) /*!< LEDTS FNCTL: ACCCNT Mask */\r
+#define LEDTS_FNCTL_TSCCMP_Pos 20 /*!< LEDTS FNCTL: TSCCMP Position */\r
+#define LEDTS_FNCTL_TSCCMP_Msk (0x01UL << LEDTS_FNCTL_TSCCMP_Pos) /*!< LEDTS FNCTL: TSCCMP Mask */\r
+#define LEDTS_FNCTL_TSOEXT_Pos 21 /*!< LEDTS FNCTL: TSOEXT Position */\r
+#define LEDTS_FNCTL_TSOEXT_Msk (0x03UL << LEDTS_FNCTL_TSOEXT_Pos) /*!< LEDTS FNCTL: TSOEXT Mask */\r
+#define LEDTS_FNCTL_TSCTRR_Pos 23 /*!< LEDTS FNCTL: TSCTRR Position */\r
+#define LEDTS_FNCTL_TSCTRR_Msk (0x01UL << LEDTS_FNCTL_TSCTRR_Pos) /*!< LEDTS FNCTL: TSCTRR Mask */\r
+#define LEDTS_FNCTL_TSCTRSAT_Pos 24 /*!< LEDTS FNCTL: TSCTRSAT Position */\r
+#define LEDTS_FNCTL_TSCTRSAT_Msk (0x01UL << LEDTS_FNCTL_TSCTRSAT_Pos) /*!< LEDTS FNCTL: TSCTRSAT Mask */\r
+#define LEDTS_FNCTL_NR_TSIN_Pos 25 /*!< LEDTS FNCTL: NR_TSIN Position */\r
+#define LEDTS_FNCTL_NR_TSIN_Msk (0x07UL << LEDTS_FNCTL_NR_TSIN_Pos) /*!< LEDTS FNCTL: NR_TSIN Mask */\r
+#define LEDTS_FNCTL_COLLEV_Pos 28 /*!< LEDTS FNCTL: COLLEV Position */\r
+#define LEDTS_FNCTL_COLLEV_Msk (0x01UL << LEDTS_FNCTL_COLLEV_Pos) /*!< LEDTS FNCTL: COLLEV Mask */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Pos 29 /*!< LEDTS FNCTL: NR_LEDCOL Position */\r
+#define LEDTS_FNCTL_NR_LEDCOL_Msk (0x07UL << LEDTS_FNCTL_NR_LEDCOL_Pos) /*!< LEDTS FNCTL: NR_LEDCOL Mask */\r
+\r
+/* --------------------------------- LEDTS_EVFR --------------------------------- */\r
+#define LEDTS_EVFR_TSF_Pos 0 /*!< LEDTS EVFR: TSF Position */\r
+#define LEDTS_EVFR_TSF_Msk (0x01UL << LEDTS_EVFR_TSF_Pos) /*!< LEDTS EVFR: TSF Mask */\r
+#define LEDTS_EVFR_TFF_Pos 1 /*!< LEDTS EVFR: TFF Position */\r
+#define LEDTS_EVFR_TFF_Msk (0x01UL << LEDTS_EVFR_TFF_Pos) /*!< LEDTS EVFR: TFF Mask */\r
+#define LEDTS_EVFR_TPF_Pos 2 /*!< LEDTS EVFR: TPF Position */\r
+#define LEDTS_EVFR_TPF_Msk (0x01UL << LEDTS_EVFR_TPF_Pos) /*!< LEDTS EVFR: TPF Mask */\r
+#define LEDTS_EVFR_TSCTROVF_Pos 3 /*!< LEDTS EVFR: TSCTROVF Position */\r
+#define LEDTS_EVFR_TSCTROVF_Msk (0x01UL << LEDTS_EVFR_TSCTROVF_Pos) /*!< LEDTS EVFR: TSCTROVF Mask */\r
+#define LEDTS_EVFR_CTSF_Pos 16 /*!< LEDTS EVFR: CTSF Position */\r
+#define LEDTS_EVFR_CTSF_Msk (0x01UL << LEDTS_EVFR_CTSF_Pos) /*!< LEDTS EVFR: CTSF Mask */\r
+#define LEDTS_EVFR_CTFF_Pos 17 /*!< LEDTS EVFR: CTFF Position */\r
+#define LEDTS_EVFR_CTFF_Msk (0x01UL << LEDTS_EVFR_CTFF_Pos) /*!< LEDTS EVFR: CTFF Mask */\r
+#define LEDTS_EVFR_CTPF_Pos 18 /*!< LEDTS EVFR: CTPF Position */\r
+#define LEDTS_EVFR_CTPF_Msk (0x01UL << LEDTS_EVFR_CTPF_Pos) /*!< LEDTS EVFR: CTPF Mask */\r
+\r
+/* --------------------------------- LEDTS_TSVAL -------------------------------- */\r
+#define LEDTS_TSVAL_TSCTRVALR_Pos 0 /*!< LEDTS TSVAL: TSCTRVALR Position */\r
+#define LEDTS_TSVAL_TSCTRVALR_Msk (0x0000ffffUL << LEDTS_TSVAL_TSCTRVALR_Pos) /*!< LEDTS TSVAL: TSCTRVALR Mask */\r
+#define LEDTS_TSVAL_TSCTRVAL_Pos 16 /*!< LEDTS TSVAL: TSCTRVAL Position */\r
+#define LEDTS_TSVAL_TSCTRVAL_Msk (0x0000ffffUL << LEDTS_TSVAL_TSCTRVAL_Pos) /*!< LEDTS TSVAL: TSCTRVAL Mask */\r
+\r
+/* --------------------------------- LEDTS_LINE0 -------------------------------- */\r
+#define LEDTS_LINE0_LINE_0_Pos 0 /*!< LEDTS LINE0: LINE_0 Position */\r
+#define LEDTS_LINE0_LINE_0_Msk (0x000000ffUL << LEDTS_LINE0_LINE_0_Pos) /*!< LEDTS LINE0: LINE_0 Mask */\r
+#define LEDTS_LINE0_LINE_1_Pos 8 /*!< LEDTS LINE0: LINE_1 Position */\r
+#define LEDTS_LINE0_LINE_1_Msk (0x000000ffUL << LEDTS_LINE0_LINE_1_Pos) /*!< LEDTS LINE0: LINE_1 Mask */\r
+#define LEDTS_LINE0_LINE_2_Pos 16 /*!< LEDTS LINE0: LINE_2 Position */\r
+#define LEDTS_LINE0_LINE_2_Msk (0x000000ffUL << LEDTS_LINE0_LINE_2_Pos) /*!< LEDTS LINE0: LINE_2 Mask */\r
+#define LEDTS_LINE0_LINE_3_Pos 24 /*!< LEDTS LINE0: LINE_3 Position */\r
+#define LEDTS_LINE0_LINE_3_Msk (0x000000ffUL << LEDTS_LINE0_LINE_3_Pos) /*!< LEDTS LINE0: LINE_3 Mask */\r
+\r
+/* --------------------------------- LEDTS_LINE1 -------------------------------- */\r
+#define LEDTS_LINE1_LINE_4_Pos 0 /*!< LEDTS LINE1: LINE_4 Position */\r
+#define LEDTS_LINE1_LINE_4_Msk (0x000000ffUL << LEDTS_LINE1_LINE_4_Pos) /*!< LEDTS LINE1: LINE_4 Mask */\r
+#define LEDTS_LINE1_LINE_5_Pos 8 /*!< LEDTS LINE1: LINE_5 Position */\r
+#define LEDTS_LINE1_LINE_5_Msk (0x000000ffUL << LEDTS_LINE1_LINE_5_Pos) /*!< LEDTS LINE1: LINE_5 Mask */\r
+#define LEDTS_LINE1_LINE_6_Pos 16 /*!< LEDTS LINE1: LINE_6 Position */\r
+#define LEDTS_LINE1_LINE_6_Msk (0x000000ffUL << LEDTS_LINE1_LINE_6_Pos) /*!< LEDTS LINE1: LINE_6 Mask */\r
+#define LEDTS_LINE1_LINE_A_Pos 24 /*!< LEDTS LINE1: LINE_A Position */\r
+#define LEDTS_LINE1_LINE_A_Msk (0x000000ffUL << LEDTS_LINE1_LINE_A_Pos) /*!< LEDTS LINE1: LINE_A Mask */\r
+\r
+/* -------------------------------- LEDTS_LDCMP0 -------------------------------- */\r
+#define LEDTS_LDCMP0_CMP_LD0_Pos 0 /*!< LEDTS LDCMP0: CMP_LD0 Position */\r
+#define LEDTS_LDCMP0_CMP_LD0_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD0_Pos) /*!< LEDTS LDCMP0: CMP_LD0 Mask */\r
+#define LEDTS_LDCMP0_CMP_LD1_Pos 8 /*!< LEDTS LDCMP0: CMP_LD1 Position */\r
+#define LEDTS_LDCMP0_CMP_LD1_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD1_Pos) /*!< LEDTS LDCMP0: CMP_LD1 Mask */\r
+#define LEDTS_LDCMP0_CMP_LD2_Pos 16 /*!< LEDTS LDCMP0: CMP_LD2 Position */\r
+#define LEDTS_LDCMP0_CMP_LD2_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD2_Pos) /*!< LEDTS LDCMP0: CMP_LD2 Mask */\r
+#define LEDTS_LDCMP0_CMP_LD3_Pos 24 /*!< LEDTS LDCMP0: CMP_LD3 Position */\r
+#define LEDTS_LDCMP0_CMP_LD3_Msk (0x000000ffUL << LEDTS_LDCMP0_CMP_LD3_Pos) /*!< LEDTS LDCMP0: CMP_LD3 Mask */\r
+\r
+/* -------------------------------- LEDTS_LDCMP1 -------------------------------- */\r
+#define LEDTS_LDCMP1_CMP_LD4_Pos 0 /*!< LEDTS LDCMP1: CMP_LD4 Position */\r
+#define LEDTS_LDCMP1_CMP_LD4_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD4_Pos) /*!< LEDTS LDCMP1: CMP_LD4 Mask */\r
+#define LEDTS_LDCMP1_CMP_LD5_Pos 8 /*!< LEDTS LDCMP1: CMP_LD5 Position */\r
+#define LEDTS_LDCMP1_CMP_LD5_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD5_Pos) /*!< LEDTS LDCMP1: CMP_LD5 Mask */\r
+#define LEDTS_LDCMP1_CMP_LD6_Pos 16 /*!< LEDTS LDCMP1: CMP_LD6 Position */\r
+#define LEDTS_LDCMP1_CMP_LD6_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LD6_Pos) /*!< LEDTS LDCMP1: CMP_LD6 Mask */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos 24 /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Position */\r
+#define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0x000000ffUL << LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos) /*!< LEDTS LDCMP1: CMP_LDA_TSCOM Mask */\r
+\r
+/* -------------------------------- LEDTS_TSCMP0 -------------------------------- */\r
+#define LEDTS_TSCMP0_CMP_TS0_Pos 0 /*!< LEDTS TSCMP0: CMP_TS0 Position */\r
+#define LEDTS_TSCMP0_CMP_TS0_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS0_Pos) /*!< LEDTS TSCMP0: CMP_TS0 Mask */\r
+#define LEDTS_TSCMP0_CMP_TS1_Pos 8 /*!< LEDTS TSCMP0: CMP_TS1 Position */\r
+#define LEDTS_TSCMP0_CMP_TS1_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS1_Pos) /*!< LEDTS TSCMP0: CMP_TS1 Mask */\r
+#define LEDTS_TSCMP0_CMP_TS2_Pos 16 /*!< LEDTS TSCMP0: CMP_TS2 Position */\r
+#define LEDTS_TSCMP0_CMP_TS2_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS2_Pos) /*!< LEDTS TSCMP0: CMP_TS2 Mask */\r
+#define LEDTS_TSCMP0_CMP_TS3_Pos 24 /*!< LEDTS TSCMP0: CMP_TS3 Position */\r
+#define LEDTS_TSCMP0_CMP_TS3_Msk (0x000000ffUL << LEDTS_TSCMP0_CMP_TS3_Pos) /*!< LEDTS TSCMP0: CMP_TS3 Mask */\r
+\r
+/* -------------------------------- LEDTS_TSCMP1 -------------------------------- */\r
+#define LEDTS_TSCMP1_CMP_TS4_Pos 0 /*!< LEDTS TSCMP1: CMP_TS4 Position */\r
+#define LEDTS_TSCMP1_CMP_TS4_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS4_Pos) /*!< LEDTS TSCMP1: CMP_TS4 Mask */\r
+#define LEDTS_TSCMP1_CMP_TS5_Pos 8 /*!< LEDTS TSCMP1: CMP_TS5 Position */\r
+#define LEDTS_TSCMP1_CMP_TS5_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS5_Pos) /*!< LEDTS TSCMP1: CMP_TS5 Mask */\r
+#define LEDTS_TSCMP1_CMP_TS6_Pos 16 /*!< LEDTS TSCMP1: CMP_TS6 Position */\r
+#define LEDTS_TSCMP1_CMP_TS6_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS6_Pos) /*!< LEDTS TSCMP1: CMP_TS6 Mask */\r
+#define LEDTS_TSCMP1_CMP_TS7_Pos 24 /*!< LEDTS TSCMP1: CMP_TS7 Position */\r
+#define LEDTS_TSCMP1_CMP_TS7_Msk (0x000000ffUL << LEDTS_TSCMP1_CMP_TS7_Pos) /*!< LEDTS TSCMP1: CMP_TS7 Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'USIC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------- USIC_ID ---------------------------------- */\r
+#define USIC_ID_MOD_REV_Pos 0 /*!< USIC ID: MOD_REV Position */\r
+#define USIC_ID_MOD_REV_Msk (0x000000ffUL << USIC_ID_MOD_REV_Pos) /*!< USIC ID: MOD_REV Mask */\r
+#define USIC_ID_MOD_TYPE_Pos 8 /*!< USIC ID: MOD_TYPE Position */\r
+#define USIC_ID_MOD_TYPE_Msk (0x000000ffUL << USIC_ID_MOD_TYPE_Pos) /*!< USIC ID: MOD_TYPE Mask */\r
+#define USIC_ID_MOD_NUMBER_Pos 16 /*!< USIC ID: MOD_NUMBER Position */\r
+#define USIC_ID_MOD_NUMBER_Msk (0x0000ffffUL << USIC_ID_MOD_NUMBER_Pos) /*!< USIC ID: MOD_NUMBER Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'USIC_CH' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- USIC_CH_CCFG -------------------------------- */\r
+#define USIC_CH_CCFG_SSC_Pos 0 /*!< USIC_CH CCFG: SSC Position */\r
+#define USIC_CH_CCFG_SSC_Msk (0x01UL << USIC_CH_CCFG_SSC_Pos) /*!< USIC_CH CCFG: SSC Mask */\r
+#define USIC_CH_CCFG_ASC_Pos 1 /*!< USIC_CH CCFG: ASC Position */\r
+#define USIC_CH_CCFG_ASC_Msk (0x01UL << USIC_CH_CCFG_ASC_Pos) /*!< USIC_CH CCFG: ASC Mask */\r
+#define USIC_CH_CCFG_IIC_Pos 2 /*!< USIC_CH CCFG: IIC Position */\r
+#define USIC_CH_CCFG_IIC_Msk (0x01UL << USIC_CH_CCFG_IIC_Pos) /*!< USIC_CH CCFG: IIC Mask */\r
+#define USIC_CH_CCFG_IIS_Pos 3 /*!< USIC_CH CCFG: IIS Position */\r
+#define USIC_CH_CCFG_IIS_Msk (0x01UL << USIC_CH_CCFG_IIS_Pos) /*!< USIC_CH CCFG: IIS Mask */\r
+#define USIC_CH_CCFG_RB_Pos 6 /*!< USIC_CH CCFG: RB Position */\r
+#define USIC_CH_CCFG_RB_Msk (0x01UL << USIC_CH_CCFG_RB_Pos) /*!< USIC_CH CCFG: RB Mask */\r
+#define USIC_CH_CCFG_TB_Pos 7 /*!< USIC_CH CCFG: TB Position */\r
+#define USIC_CH_CCFG_TB_Msk (0x01UL << USIC_CH_CCFG_TB_Pos) /*!< USIC_CH CCFG: TB Mask */\r
+\r
+/* -------------------------------- USIC_CH_KSCFG ------------------------------- */\r
+#define USIC_CH_KSCFG_MODEN_Pos 0 /*!< USIC_CH KSCFG: MODEN Position */\r
+#define USIC_CH_KSCFG_MODEN_Msk (0x01UL << USIC_CH_KSCFG_MODEN_Pos) /*!< USIC_CH KSCFG: MODEN Mask */\r
+#define USIC_CH_KSCFG_BPMODEN_Pos 1 /*!< USIC_CH KSCFG: BPMODEN Position */\r
+#define USIC_CH_KSCFG_BPMODEN_Msk (0x01UL << USIC_CH_KSCFG_BPMODEN_Pos) /*!< USIC_CH KSCFG: BPMODEN Mask */\r
+#define USIC_CH_KSCFG_NOMCFG_Pos 4 /*!< USIC_CH KSCFG: NOMCFG Position */\r
+#define USIC_CH_KSCFG_NOMCFG_Msk (0x03UL << USIC_CH_KSCFG_NOMCFG_Pos) /*!< USIC_CH KSCFG: NOMCFG Mask */\r
+#define USIC_CH_KSCFG_BPNOM_Pos 7 /*!< USIC_CH KSCFG: BPNOM Position */\r
+#define USIC_CH_KSCFG_BPNOM_Msk (0x01UL << USIC_CH_KSCFG_BPNOM_Pos) /*!< USIC_CH KSCFG: BPNOM Mask */\r
+#define USIC_CH_KSCFG_SUMCFG_Pos 8 /*!< USIC_CH KSCFG: SUMCFG Position */\r
+#define USIC_CH_KSCFG_SUMCFG_Msk (0x03UL << USIC_CH_KSCFG_SUMCFG_Pos) /*!< USIC_CH KSCFG: SUMCFG Mask */\r
+#define USIC_CH_KSCFG_BPSUM_Pos 11 /*!< USIC_CH KSCFG: BPSUM Position */\r
+#define USIC_CH_KSCFG_BPSUM_Msk (0x01UL << USIC_CH_KSCFG_BPSUM_Pos) /*!< USIC_CH KSCFG: BPSUM Mask */\r
+\r
+/* --------------------------------- USIC_CH_FDR -------------------------------- */\r
+#define USIC_CH_FDR_STEP_Pos 0 /*!< USIC_CH FDR: STEP Position */\r
+#define USIC_CH_FDR_STEP_Msk (0x000003ffUL << USIC_CH_FDR_STEP_Pos) /*!< USIC_CH FDR: STEP Mask */\r
+#define USIC_CH_FDR_DM_Pos 14 /*!< USIC_CH FDR: DM Position */\r
+#define USIC_CH_FDR_DM_Msk (0x03UL << USIC_CH_FDR_DM_Pos) /*!< USIC_CH FDR: DM Mask */\r
+#define USIC_CH_FDR_RESULT_Pos 16 /*!< USIC_CH FDR: RESULT Position */\r
+#define USIC_CH_FDR_RESULT_Msk (0x000003ffUL << USIC_CH_FDR_RESULT_Pos) /*!< USIC_CH FDR: RESULT Mask */\r
+\r
+/* --------------------------------- USIC_CH_BRG -------------------------------- */\r
+#define USIC_CH_BRG_CLKSEL_Pos 0 /*!< USIC_CH BRG: CLKSEL Position */\r
+#define USIC_CH_BRG_CLKSEL_Msk (0x03UL << USIC_CH_BRG_CLKSEL_Pos) /*!< USIC_CH BRG: CLKSEL Mask */\r
+#define USIC_CH_BRG_TMEN_Pos 3 /*!< USIC_CH BRG: TMEN Position */\r
+#define USIC_CH_BRG_TMEN_Msk (0x01UL << USIC_CH_BRG_TMEN_Pos) /*!< USIC_CH BRG: TMEN Mask */\r
+#define USIC_CH_BRG_PPPEN_Pos 4 /*!< USIC_CH BRG: PPPEN Position */\r
+#define USIC_CH_BRG_PPPEN_Msk (0x01UL << USIC_CH_BRG_PPPEN_Pos) /*!< USIC_CH BRG: PPPEN Mask */\r
+#define USIC_CH_BRG_CTQSEL_Pos 6 /*!< USIC_CH BRG: CTQSEL Position */\r
+#define USIC_CH_BRG_CTQSEL_Msk (0x03UL << USIC_CH_BRG_CTQSEL_Pos) /*!< USIC_CH BRG: CTQSEL Mask */\r
+#define USIC_CH_BRG_PCTQ_Pos 8 /*!< USIC_CH BRG: PCTQ Position */\r
+#define USIC_CH_BRG_PCTQ_Msk (0x03UL << USIC_CH_BRG_PCTQ_Pos) /*!< USIC_CH BRG: PCTQ Mask */\r
+#define USIC_CH_BRG_DCTQ_Pos 10 /*!< USIC_CH BRG: DCTQ Position */\r
+#define USIC_CH_BRG_DCTQ_Msk (0x1fUL << USIC_CH_BRG_DCTQ_Pos) /*!< USIC_CH BRG: DCTQ Mask */\r
+#define USIC_CH_BRG_PDIV_Pos 16 /*!< USIC_CH BRG: PDIV Position */\r
+#define USIC_CH_BRG_PDIV_Msk (0x000003ffUL << USIC_CH_BRG_PDIV_Pos) /*!< USIC_CH BRG: PDIV Mask */\r
+#define USIC_CH_BRG_SCLKOSEL_Pos 28 /*!< USIC_CH BRG: SCLKOSEL Position */\r
+#define USIC_CH_BRG_SCLKOSEL_Msk (0x01UL << USIC_CH_BRG_SCLKOSEL_Pos) /*!< USIC_CH BRG: SCLKOSEL Mask */\r
+#define USIC_CH_BRG_MCLKCFG_Pos 29 /*!< USIC_CH BRG: MCLKCFG Position */\r
+#define USIC_CH_BRG_MCLKCFG_Msk (0x01UL << USIC_CH_BRG_MCLKCFG_Pos) /*!< USIC_CH BRG: MCLKCFG Mask */\r
+#define USIC_CH_BRG_SCLKCFG_Pos 30 /*!< USIC_CH BRG: SCLKCFG Position */\r
+#define USIC_CH_BRG_SCLKCFG_Msk (0x03UL << USIC_CH_BRG_SCLKCFG_Pos) /*!< USIC_CH BRG: SCLKCFG Mask */\r
+\r
+/* -------------------------------- USIC_CH_INPR -------------------------------- */\r
+#define USIC_CH_INPR_TSINP_Pos 0 /*!< USIC_CH INPR: TSINP Position */\r
+#define USIC_CH_INPR_TSINP_Msk (0x07UL << USIC_CH_INPR_TSINP_Pos) /*!< USIC_CH INPR: TSINP Mask */\r
+#define USIC_CH_INPR_TBINP_Pos 4 /*!< USIC_CH INPR: TBINP Position */\r
+#define USIC_CH_INPR_TBINP_Msk (0x07UL << USIC_CH_INPR_TBINP_Pos) /*!< USIC_CH INPR: TBINP Mask */\r
+#define USIC_CH_INPR_RINP_Pos 8 /*!< USIC_CH INPR: RINP Position */\r
+#define USIC_CH_INPR_RINP_Msk (0x07UL << USIC_CH_INPR_RINP_Pos) /*!< USIC_CH INPR: RINP Mask */\r
+#define USIC_CH_INPR_AINP_Pos 12 /*!< USIC_CH INPR: AINP Position */\r
+#define USIC_CH_INPR_AINP_Msk (0x07UL << USIC_CH_INPR_AINP_Pos) /*!< USIC_CH INPR: AINP Mask */\r
+#define USIC_CH_INPR_PINP_Pos 16 /*!< USIC_CH INPR: PINP Position */\r
+#define USIC_CH_INPR_PINP_Msk (0x07UL << USIC_CH_INPR_PINP_Pos) /*!< USIC_CH INPR: PINP Mask */\r
+\r
+/* -------------------------------- USIC_CH_DX0CR ------------------------------- */\r
+#define USIC_CH_DX0CR_DSEL_Pos 0 /*!< USIC_CH DX0CR: DSEL Position */\r
+#define USIC_CH_DX0CR_DSEL_Msk (0x07UL << USIC_CH_DX0CR_DSEL_Pos) /*!< USIC_CH DX0CR: DSEL Mask */\r
+#define USIC_CH_DX0CR_INSW_Pos 4 /*!< USIC_CH DX0CR: INSW Position */\r
+#define USIC_CH_DX0CR_INSW_Msk (0x01UL << USIC_CH_DX0CR_INSW_Pos) /*!< USIC_CH DX0CR: INSW Mask */\r
+#define USIC_CH_DX0CR_DFEN_Pos 5 /*!< USIC_CH DX0CR: DFEN Position */\r
+#define USIC_CH_DX0CR_DFEN_Msk (0x01UL << USIC_CH_DX0CR_DFEN_Pos) /*!< USIC_CH DX0CR: DFEN Mask */\r
+#define USIC_CH_DX0CR_DSEN_Pos 6 /*!< USIC_CH DX0CR: DSEN Position */\r
+#define USIC_CH_DX0CR_DSEN_Msk (0x01UL << USIC_CH_DX0CR_DSEN_Pos) /*!< USIC_CH DX0CR: DSEN Mask */\r
+#define USIC_CH_DX0CR_DPOL_Pos 8 /*!< USIC_CH DX0CR: DPOL Position */\r
+#define USIC_CH_DX0CR_DPOL_Msk (0x01UL << USIC_CH_DX0CR_DPOL_Pos) /*!< USIC_CH DX0CR: DPOL Mask */\r
+#define USIC_CH_DX0CR_SFSEL_Pos 9 /*!< USIC_CH DX0CR: SFSEL Position */\r
+#define USIC_CH_DX0CR_SFSEL_Msk (0x01UL << USIC_CH_DX0CR_SFSEL_Pos) /*!< USIC_CH DX0CR: SFSEL Mask */\r
+#define USIC_CH_DX0CR_CM_Pos 10 /*!< USIC_CH DX0CR: CM Position */\r
+#define USIC_CH_DX0CR_CM_Msk (0x03UL << USIC_CH_DX0CR_CM_Pos) /*!< USIC_CH DX0CR: CM Mask */\r
+#define USIC_CH_DX0CR_DXS_Pos 15 /*!< USIC_CH DX0CR: DXS Position */\r
+#define USIC_CH_DX0CR_DXS_Msk (0x01UL << USIC_CH_DX0CR_DXS_Pos) /*!< USIC_CH DX0CR: DXS Mask */\r
+\r
+/* -------------------------------- USIC_CH_DX1CR ------------------------------- */\r
+#define USIC_CH_DX1CR_DSEL_Pos 0 /*!< USIC_CH DX1CR: DSEL Position */\r
+#define USIC_CH_DX1CR_DSEL_Msk (0x07UL << USIC_CH_DX1CR_DSEL_Pos) /*!< USIC_CH DX1CR: DSEL Mask */\r
+#define USIC_CH_DX1CR_DCEN_Pos 3 /*!< USIC_CH DX1CR: DCEN Position */\r
+#define USIC_CH_DX1CR_DCEN_Msk (0x01UL << USIC_CH_DX1CR_DCEN_Pos) /*!< USIC_CH DX1CR: DCEN Mask */\r
+#define USIC_CH_DX1CR_INSW_Pos 4 /*!< USIC_CH DX1CR: INSW Position */\r
+#define USIC_CH_DX1CR_INSW_Msk (0x01UL << USIC_CH_DX1CR_INSW_Pos) /*!< USIC_CH DX1CR: INSW Mask */\r
+#define USIC_CH_DX1CR_DFEN_Pos 5 /*!< USIC_CH DX1CR: DFEN Position */\r
+#define USIC_CH_DX1CR_DFEN_Msk (0x01UL << USIC_CH_DX1CR_DFEN_Pos) /*!< USIC_CH DX1CR: DFEN Mask */\r
+#define USIC_CH_DX1CR_DSEN_Pos 6 /*!< USIC_CH DX1CR: DSEN Position */\r
+#define USIC_CH_DX1CR_DSEN_Msk (0x01UL << USIC_CH_DX1CR_DSEN_Pos) /*!< USIC_CH DX1CR: DSEN Mask */\r
+#define USIC_CH_DX1CR_DPOL_Pos 8 /*!< USIC_CH DX1CR: DPOL Position */\r
+#define USIC_CH_DX1CR_DPOL_Msk (0x01UL << USIC_CH_DX1CR_DPOL_Pos) /*!< USIC_CH DX1CR: DPOL Mask */\r
+#define USIC_CH_DX1CR_SFSEL_Pos 9 /*!< USIC_CH DX1CR: SFSEL Position */\r
+#define USIC_CH_DX1CR_SFSEL_Msk (0x01UL << USIC_CH_DX1CR_SFSEL_Pos) /*!< USIC_CH DX1CR: SFSEL Mask */\r
+#define USIC_CH_DX1CR_CM_Pos 10 /*!< USIC_CH DX1CR: CM Position */\r
+#define USIC_CH_DX1CR_CM_Msk (0x03UL << USIC_CH_DX1CR_CM_Pos) /*!< USIC_CH DX1CR: CM Mask */\r
+#define USIC_CH_DX1CR_DXS_Pos 15 /*!< USIC_CH DX1CR: DXS Position */\r
+#define USIC_CH_DX1CR_DXS_Msk (0x01UL << USIC_CH_DX1CR_DXS_Pos) /*!< USIC_CH DX1CR: DXS Mask */\r
+\r
+/* -------------------------------- USIC_CH_DX2CR ------------------------------- */\r
+#define USIC_CH_DX2CR_DSEL_Pos 0 /*!< USIC_CH DX2CR: DSEL Position */\r
+#define USIC_CH_DX2CR_DSEL_Msk (0x07UL << USIC_CH_DX2CR_DSEL_Pos) /*!< USIC_CH DX2CR: DSEL Mask */\r
+#define USIC_CH_DX2CR_INSW_Pos 4 /*!< USIC_CH DX2CR: INSW Position */\r
+#define USIC_CH_DX2CR_INSW_Msk (0x01UL << USIC_CH_DX2CR_INSW_Pos) /*!< USIC_CH DX2CR: INSW Mask */\r
+#define USIC_CH_DX2CR_DFEN_Pos 5 /*!< USIC_CH DX2CR: DFEN Position */\r
+#define USIC_CH_DX2CR_DFEN_Msk (0x01UL << USIC_CH_DX2CR_DFEN_Pos) /*!< USIC_CH DX2CR: DFEN Mask */\r
+#define USIC_CH_DX2CR_DSEN_Pos 6 /*!< USIC_CH DX2CR: DSEN Position */\r
+#define USIC_CH_DX2CR_DSEN_Msk (0x01UL << USIC_CH_DX2CR_DSEN_Pos) /*!< USIC_CH DX2CR: DSEN Mask */\r
+#define USIC_CH_DX2CR_DPOL_Pos 8 /*!< USIC_CH DX2CR: DPOL Position */\r
+#define USIC_CH_DX2CR_DPOL_Msk (0x01UL << USIC_CH_DX2CR_DPOL_Pos) /*!< USIC_CH DX2CR: DPOL Mask */\r
+#define USIC_CH_DX2CR_SFSEL_Pos 9 /*!< USIC_CH DX2CR: SFSEL Position */\r
+#define USIC_CH_DX2CR_SFSEL_Msk (0x01UL << USIC_CH_DX2CR_SFSEL_Pos) /*!< USIC_CH DX2CR: SFSEL Mask */\r
+#define USIC_CH_DX2CR_CM_Pos 10 /*!< USIC_CH DX2CR: CM Position */\r
+#define USIC_CH_DX2CR_CM_Msk (0x03UL << USIC_CH_DX2CR_CM_Pos) /*!< USIC_CH DX2CR: CM Mask */\r
+#define USIC_CH_DX2CR_DXS_Pos 15 /*!< USIC_CH DX2CR: DXS Position */\r
+#define USIC_CH_DX2CR_DXS_Msk (0x01UL << USIC_CH_DX2CR_DXS_Pos) /*!< USIC_CH DX2CR: DXS Mask */\r
+\r
+/* -------------------------------- USIC_CH_DX3CR ------------------------------- */\r
+#define USIC_CH_DX3CR_DSEL_Pos 0 /*!< USIC_CH DX3CR: DSEL Position */\r
+#define USIC_CH_DX3CR_DSEL_Msk (0x07UL << USIC_CH_DX3CR_DSEL_Pos) /*!< USIC_CH DX3CR: DSEL Mask */\r
+#define USIC_CH_DX3CR_INSW_Pos 4 /*!< USIC_CH DX3CR: INSW Position */\r
+#define USIC_CH_DX3CR_INSW_Msk (0x01UL << USIC_CH_DX3CR_INSW_Pos) /*!< USIC_CH DX3CR: INSW Mask */\r
+#define USIC_CH_DX3CR_DFEN_Pos 5 /*!< USIC_CH DX3CR: DFEN Position */\r
+#define USIC_CH_DX3CR_DFEN_Msk (0x01UL << USIC_CH_DX3CR_DFEN_Pos) /*!< USIC_CH DX3CR: DFEN Mask */\r
+#define USIC_CH_DX3CR_DSEN_Pos 6 /*!< USIC_CH DX3CR: DSEN Position */\r
+#define USIC_CH_DX3CR_DSEN_Msk (0x01UL << USIC_CH_DX3CR_DSEN_Pos) /*!< USIC_CH DX3CR: DSEN Mask */\r
+#define USIC_CH_DX3CR_DPOL_Pos 8 /*!< USIC_CH DX3CR: DPOL Position */\r
+#define USIC_CH_DX3CR_DPOL_Msk (0x01UL << USIC_CH_DX3CR_DPOL_Pos) /*!< USIC_CH DX3CR: DPOL Mask */\r
+#define USIC_CH_DX3CR_SFSEL_Pos 9 /*!< USIC_CH DX3CR: SFSEL Position */\r
+#define USIC_CH_DX3CR_SFSEL_Msk (0x01UL << USIC_CH_DX3CR_SFSEL_Pos) /*!< USIC_CH DX3CR: SFSEL Mask */\r
+#define USIC_CH_DX3CR_CM_Pos 10 /*!< USIC_CH DX3CR: CM Position */\r
+#define USIC_CH_DX3CR_CM_Msk (0x03UL << USIC_CH_DX3CR_CM_Pos) /*!< USIC_CH DX3CR: CM Mask */\r
+#define USIC_CH_DX3CR_DXS_Pos 15 /*!< USIC_CH DX3CR: DXS Position */\r
+#define USIC_CH_DX3CR_DXS_Msk (0x01UL << USIC_CH_DX3CR_DXS_Pos) /*!< USIC_CH DX3CR: DXS Mask */\r
+\r
+/* -------------------------------- USIC_CH_DX4CR ------------------------------- */\r
+#define USIC_CH_DX4CR_DSEL_Pos 0 /*!< USIC_CH DX4CR: DSEL Position */\r
+#define USIC_CH_DX4CR_DSEL_Msk (0x07UL << USIC_CH_DX4CR_DSEL_Pos) /*!< USIC_CH DX4CR: DSEL Mask */\r
+#define USIC_CH_DX4CR_INSW_Pos 4 /*!< USIC_CH DX4CR: INSW Position */\r
+#define USIC_CH_DX4CR_INSW_Msk (0x01UL << USIC_CH_DX4CR_INSW_Pos) /*!< USIC_CH DX4CR: INSW Mask */\r
+#define USIC_CH_DX4CR_DFEN_Pos 5 /*!< USIC_CH DX4CR: DFEN Position */\r
+#define USIC_CH_DX4CR_DFEN_Msk (0x01UL << USIC_CH_DX4CR_DFEN_Pos) /*!< USIC_CH DX4CR: DFEN Mask */\r
+#define USIC_CH_DX4CR_DSEN_Pos 6 /*!< USIC_CH DX4CR: DSEN Position */\r
+#define USIC_CH_DX4CR_DSEN_Msk (0x01UL << USIC_CH_DX4CR_DSEN_Pos) /*!< USIC_CH DX4CR: DSEN Mask */\r
+#define USIC_CH_DX4CR_DPOL_Pos 8 /*!< USIC_CH DX4CR: DPOL Position */\r
+#define USIC_CH_DX4CR_DPOL_Msk (0x01UL << USIC_CH_DX4CR_DPOL_Pos) /*!< USIC_CH DX4CR: DPOL Mask */\r
+#define USIC_CH_DX4CR_SFSEL_Pos 9 /*!< USIC_CH DX4CR: SFSEL Position */\r
+#define USIC_CH_DX4CR_SFSEL_Msk (0x01UL << USIC_CH_DX4CR_SFSEL_Pos) /*!< USIC_CH DX4CR: SFSEL Mask */\r
+#define USIC_CH_DX4CR_CM_Pos 10 /*!< USIC_CH DX4CR: CM Position */\r
+#define USIC_CH_DX4CR_CM_Msk (0x03UL << USIC_CH_DX4CR_CM_Pos) /*!< USIC_CH DX4CR: CM Mask */\r
+#define USIC_CH_DX4CR_DXS_Pos 15 /*!< USIC_CH DX4CR: DXS Position */\r
+#define USIC_CH_DX4CR_DXS_Msk (0x01UL << USIC_CH_DX4CR_DXS_Pos) /*!< USIC_CH DX4CR: DXS Mask */\r
+\r
+/* -------------------------------- USIC_CH_DX5CR ------------------------------- */\r
+#define USIC_CH_DX5CR_DSEL_Pos 0 /*!< USIC_CH DX5CR: DSEL Position */\r
+#define USIC_CH_DX5CR_DSEL_Msk (0x07UL << USIC_CH_DX5CR_DSEL_Pos) /*!< USIC_CH DX5CR: DSEL Mask */\r
+#define USIC_CH_DX5CR_INSW_Pos 4 /*!< USIC_CH DX5CR: INSW Position */\r
+#define USIC_CH_DX5CR_INSW_Msk (0x01UL << USIC_CH_DX5CR_INSW_Pos) /*!< USIC_CH DX5CR: INSW Mask */\r
+#define USIC_CH_DX5CR_DFEN_Pos 5 /*!< USIC_CH DX5CR: DFEN Position */\r
+#define USIC_CH_DX5CR_DFEN_Msk (0x01UL << USIC_CH_DX5CR_DFEN_Pos) /*!< USIC_CH DX5CR: DFEN Mask */\r
+#define USIC_CH_DX5CR_DSEN_Pos 6 /*!< USIC_CH DX5CR: DSEN Position */\r
+#define USIC_CH_DX5CR_DSEN_Msk (0x01UL << USIC_CH_DX5CR_DSEN_Pos) /*!< USIC_CH DX5CR: DSEN Mask */\r
+#define USIC_CH_DX5CR_DPOL_Pos 8 /*!< USIC_CH DX5CR: DPOL Position */\r
+#define USIC_CH_DX5CR_DPOL_Msk (0x01UL << USIC_CH_DX5CR_DPOL_Pos) /*!< USIC_CH DX5CR: DPOL Mask */\r
+#define USIC_CH_DX5CR_SFSEL_Pos 9 /*!< USIC_CH DX5CR: SFSEL Position */\r
+#define USIC_CH_DX5CR_SFSEL_Msk (0x01UL << USIC_CH_DX5CR_SFSEL_Pos) /*!< USIC_CH DX5CR: SFSEL Mask */\r
+#define USIC_CH_DX5CR_CM_Pos 10 /*!< USIC_CH DX5CR: CM Position */\r
+#define USIC_CH_DX5CR_CM_Msk (0x03UL << USIC_CH_DX5CR_CM_Pos) /*!< USIC_CH DX5CR: CM Mask */\r
+#define USIC_CH_DX5CR_DXS_Pos 15 /*!< USIC_CH DX5CR: DXS Position */\r
+#define USIC_CH_DX5CR_DXS_Msk (0x01UL << USIC_CH_DX5CR_DXS_Pos) /*!< USIC_CH DX5CR: DXS Mask */\r
+\r
+/* -------------------------------- USIC_CH_SCTR -------------------------------- */\r
+#define USIC_CH_SCTR_SDIR_Pos 0 /*!< USIC_CH SCTR: SDIR Position */\r
+#define USIC_CH_SCTR_SDIR_Msk (0x01UL << USIC_CH_SCTR_SDIR_Pos) /*!< USIC_CH SCTR: SDIR Mask */\r
+#define USIC_CH_SCTR_PDL_Pos 1 /*!< USIC_CH SCTR: PDL Position */\r
+#define USIC_CH_SCTR_PDL_Msk (0x01UL << USIC_CH_SCTR_PDL_Pos) /*!< USIC_CH SCTR: PDL Mask */\r
+#define USIC_CH_SCTR_DSM_Pos 2 /*!< USIC_CH SCTR: DSM Position */\r
+#define USIC_CH_SCTR_DSM_Msk (0x03UL << USIC_CH_SCTR_DSM_Pos) /*!< USIC_CH SCTR: DSM Mask */\r
+#define USIC_CH_SCTR_HPCDIR_Pos 4 /*!< USIC_CH SCTR: HPCDIR Position */\r
+#define USIC_CH_SCTR_HPCDIR_Msk (0x01UL << USIC_CH_SCTR_HPCDIR_Pos) /*!< USIC_CH SCTR: HPCDIR Mask */\r
+#define USIC_CH_SCTR_DOCFG_Pos 6 /*!< USIC_CH SCTR: DOCFG Position */\r
+#define USIC_CH_SCTR_DOCFG_Msk (0x03UL << USIC_CH_SCTR_DOCFG_Pos) /*!< USIC_CH SCTR: DOCFG Mask */\r
+#define USIC_CH_SCTR_TRM_Pos 8 /*!< USIC_CH SCTR: TRM Position */\r
+#define USIC_CH_SCTR_TRM_Msk (0x03UL << USIC_CH_SCTR_TRM_Pos) /*!< USIC_CH SCTR: TRM Mask */\r
+#define USIC_CH_SCTR_FLE_Pos 16 /*!< USIC_CH SCTR: FLE Position */\r
+#define USIC_CH_SCTR_FLE_Msk (0x3fUL << USIC_CH_SCTR_FLE_Pos) /*!< USIC_CH SCTR: FLE Mask */\r
+#define USIC_CH_SCTR_WLE_Pos 24 /*!< USIC_CH SCTR: WLE Position */\r
+#define USIC_CH_SCTR_WLE_Msk (0x0fUL << USIC_CH_SCTR_WLE_Pos) /*!< USIC_CH SCTR: WLE Mask */\r
+\r
+/* -------------------------------- USIC_CH_TCSR -------------------------------- */\r
+#define USIC_CH_TCSR_WLEMD_Pos 0 /*!< USIC_CH TCSR: WLEMD Position */\r
+#define USIC_CH_TCSR_WLEMD_Msk (0x01UL << USIC_CH_TCSR_WLEMD_Pos) /*!< USIC_CH TCSR: WLEMD Mask */\r
+#define USIC_CH_TCSR_SELMD_Pos 1 /*!< USIC_CH TCSR: SELMD Position */\r
+#define USIC_CH_TCSR_SELMD_Msk (0x01UL << USIC_CH_TCSR_SELMD_Pos) /*!< USIC_CH TCSR: SELMD Mask */\r
+#define USIC_CH_TCSR_FLEMD_Pos 2 /*!< USIC_CH TCSR: FLEMD Position */\r
+#define USIC_CH_TCSR_FLEMD_Msk (0x01UL << USIC_CH_TCSR_FLEMD_Pos) /*!< USIC_CH TCSR: FLEMD Mask */\r
+#define USIC_CH_TCSR_WAMD_Pos 3 /*!< USIC_CH TCSR: WAMD Position */\r
+#define USIC_CH_TCSR_WAMD_Msk (0x01UL << USIC_CH_TCSR_WAMD_Pos) /*!< USIC_CH TCSR: WAMD Mask */\r
+#define USIC_CH_TCSR_HPCMD_Pos 4 /*!< USIC_CH TCSR: HPCMD Position */\r
+#define USIC_CH_TCSR_HPCMD_Msk (0x01UL << USIC_CH_TCSR_HPCMD_Pos) /*!< USIC_CH TCSR: HPCMD Mask */\r
+#define USIC_CH_TCSR_SOF_Pos 5 /*!< USIC_CH TCSR: SOF Position */\r
+#define USIC_CH_TCSR_SOF_Msk (0x01UL << USIC_CH_TCSR_SOF_Pos) /*!< USIC_CH TCSR: SOF Mask */\r
+#define USIC_CH_TCSR_EOF_Pos 6 /*!< USIC_CH TCSR: EOF Position */\r
+#define USIC_CH_TCSR_EOF_Msk (0x01UL << USIC_CH_TCSR_EOF_Pos) /*!< USIC_CH TCSR: EOF Mask */\r
+#define USIC_CH_TCSR_TDV_Pos 7 /*!< USIC_CH TCSR: TDV Position */\r
+#define USIC_CH_TCSR_TDV_Msk (0x01UL << USIC_CH_TCSR_TDV_Pos) /*!< USIC_CH TCSR: TDV Mask */\r
+#define USIC_CH_TCSR_TDSSM_Pos 8 /*!< USIC_CH TCSR: TDSSM Position */\r
+#define USIC_CH_TCSR_TDSSM_Msk (0x01UL << USIC_CH_TCSR_TDSSM_Pos) /*!< USIC_CH TCSR: TDSSM Mask */\r
+#define USIC_CH_TCSR_TDEN_Pos 10 /*!< USIC_CH TCSR: TDEN Position */\r
+#define USIC_CH_TCSR_TDEN_Msk (0x03UL << USIC_CH_TCSR_TDEN_Pos) /*!< USIC_CH TCSR: TDEN Mask */\r
+#define USIC_CH_TCSR_TDVTR_Pos 12 /*!< USIC_CH TCSR: TDVTR Position */\r
+#define USIC_CH_TCSR_TDVTR_Msk (0x01UL << USIC_CH_TCSR_TDVTR_Pos) /*!< USIC_CH TCSR: TDVTR Mask */\r
+#define USIC_CH_TCSR_WA_Pos 13 /*!< USIC_CH TCSR: WA Position */\r
+#define USIC_CH_TCSR_WA_Msk (0x01UL << USIC_CH_TCSR_WA_Pos) /*!< USIC_CH TCSR: WA Mask */\r
+#define USIC_CH_TCSR_TSOF_Pos 24 /*!< USIC_CH TCSR: TSOF Position */\r
+#define USIC_CH_TCSR_TSOF_Msk (0x01UL << USIC_CH_TCSR_TSOF_Pos) /*!< USIC_CH TCSR: TSOF Mask */\r
+#define USIC_CH_TCSR_TV_Pos 26 /*!< USIC_CH TCSR: TV Position */\r
+#define USIC_CH_TCSR_TV_Msk (0x01UL << USIC_CH_TCSR_TV_Pos) /*!< USIC_CH TCSR: TV Mask */\r
+#define USIC_CH_TCSR_TVC_Pos 27 /*!< USIC_CH TCSR: TVC Position */\r
+#define USIC_CH_TCSR_TVC_Msk (0x01UL << USIC_CH_TCSR_TVC_Pos) /*!< USIC_CH TCSR: TVC Mask */\r
+#define USIC_CH_TCSR_TE_Pos 28 /*!< USIC_CH TCSR: TE Position */\r
+#define USIC_CH_TCSR_TE_Msk (0x01UL << USIC_CH_TCSR_TE_Pos) /*!< USIC_CH TCSR: TE Mask */\r
+\r
+/* --------------------------------- USIC_CH_PCR -------------------------------- */\r
+#define USIC_CH_PCR_CTR0_Pos 0 /*!< USIC_CH PCR: CTR0 Position */\r
+#define USIC_CH_PCR_CTR0_Msk (0x01UL << USIC_CH_PCR_CTR0_Pos) /*!< USIC_CH PCR: CTR0 Mask */\r
+#define USIC_CH_PCR_CTR1_Pos 1 /*!< USIC_CH PCR: CTR1 Position */\r
+#define USIC_CH_PCR_CTR1_Msk (0x01UL << USIC_CH_PCR_CTR1_Pos) /*!< USIC_CH PCR: CTR1 Mask */\r
+#define USIC_CH_PCR_CTR2_Pos 2 /*!< USIC_CH PCR: CTR2 Position */\r
+#define USIC_CH_PCR_CTR2_Msk (0x01UL << USIC_CH_PCR_CTR2_Pos) /*!< USIC_CH PCR: CTR2 Mask */\r
+#define USIC_CH_PCR_CTR3_Pos 3 /*!< USIC_CH PCR: CTR3 Position */\r
+#define USIC_CH_PCR_CTR3_Msk (0x01UL << USIC_CH_PCR_CTR3_Pos) /*!< USIC_CH PCR: CTR3 Mask */\r
+#define USIC_CH_PCR_CTR4_Pos 4 /*!< USIC_CH PCR: CTR4 Position */\r
+#define USIC_CH_PCR_CTR4_Msk (0x01UL << USIC_CH_PCR_CTR4_Pos) /*!< USIC_CH PCR: CTR4 Mask */\r
+#define USIC_CH_PCR_CTR5_Pos 5 /*!< USIC_CH PCR: CTR5 Position */\r
+#define USIC_CH_PCR_CTR5_Msk (0x01UL << USIC_CH_PCR_CTR5_Pos) /*!< USIC_CH PCR: CTR5 Mask */\r
+#define USIC_CH_PCR_CTR6_Pos 6 /*!< USIC_CH PCR: CTR6 Position */\r
+#define USIC_CH_PCR_CTR6_Msk (0x01UL << USIC_CH_PCR_CTR6_Pos) /*!< USIC_CH PCR: CTR6 Mask */\r
+#define USIC_CH_PCR_CTR7_Pos 7 /*!< USIC_CH PCR: CTR7 Position */\r
+#define USIC_CH_PCR_CTR7_Msk (0x01UL << USIC_CH_PCR_CTR7_Pos) /*!< USIC_CH PCR: CTR7 Mask */\r
+#define USIC_CH_PCR_CTR8_Pos 8 /*!< USIC_CH PCR: CTR8 Position */\r
+#define USIC_CH_PCR_CTR8_Msk (0x01UL << USIC_CH_PCR_CTR8_Pos) /*!< USIC_CH PCR: CTR8 Mask */\r
+#define USIC_CH_PCR_CTR9_Pos 9 /*!< USIC_CH PCR: CTR9 Position */\r
+#define USIC_CH_PCR_CTR9_Msk (0x01UL << USIC_CH_PCR_CTR9_Pos) /*!< USIC_CH PCR: CTR9 Mask */\r
+#define USIC_CH_PCR_CTR10_Pos 10 /*!< USIC_CH PCR: CTR10 Position */\r
+#define USIC_CH_PCR_CTR10_Msk (0x01UL << USIC_CH_PCR_CTR10_Pos) /*!< USIC_CH PCR: CTR10 Mask */\r
+#define USIC_CH_PCR_CTR11_Pos 11 /*!< USIC_CH PCR: CTR11 Position */\r
+#define USIC_CH_PCR_CTR11_Msk (0x01UL << USIC_CH_PCR_CTR11_Pos) /*!< USIC_CH PCR: CTR11 Mask */\r
+#define USIC_CH_PCR_CTR12_Pos 12 /*!< USIC_CH PCR: CTR12 Position */\r
+#define USIC_CH_PCR_CTR12_Msk (0x01UL << USIC_CH_PCR_CTR12_Pos) /*!< USIC_CH PCR: CTR12 Mask */\r
+#define USIC_CH_PCR_CTR13_Pos 13 /*!< USIC_CH PCR: CTR13 Position */\r
+#define USIC_CH_PCR_CTR13_Msk (0x01UL << USIC_CH_PCR_CTR13_Pos) /*!< USIC_CH PCR: CTR13 Mask */\r
+#define USIC_CH_PCR_CTR14_Pos 14 /*!< USIC_CH PCR: CTR14 Position */\r
+#define USIC_CH_PCR_CTR14_Msk (0x01UL << USIC_CH_PCR_CTR14_Pos) /*!< USIC_CH PCR: CTR14 Mask */\r
+#define USIC_CH_PCR_CTR15_Pos 15 /*!< USIC_CH PCR: CTR15 Position */\r
+#define USIC_CH_PCR_CTR15_Msk (0x01UL << USIC_CH_PCR_CTR15_Pos) /*!< USIC_CH PCR: CTR15 Mask */\r
+#define USIC_CH_PCR_CTR16_Pos 16 /*!< USIC_CH PCR: CTR16 Position */\r
+#define USIC_CH_PCR_CTR16_Msk (0x01UL << USIC_CH_PCR_CTR16_Pos) /*!< USIC_CH PCR: CTR16 Mask */\r
+#define USIC_CH_PCR_CTR17_Pos 17 /*!< USIC_CH PCR: CTR17 Position */\r
+#define USIC_CH_PCR_CTR17_Msk (0x01UL << USIC_CH_PCR_CTR17_Pos) /*!< USIC_CH PCR: CTR17 Mask */\r
+#define USIC_CH_PCR_CTR18_Pos 18 /*!< USIC_CH PCR: CTR18 Position */\r
+#define USIC_CH_PCR_CTR18_Msk (0x01UL << USIC_CH_PCR_CTR18_Pos) /*!< USIC_CH PCR: CTR18 Mask */\r
+#define USIC_CH_PCR_CTR19_Pos 19 /*!< USIC_CH PCR: CTR19 Position */\r
+#define USIC_CH_PCR_CTR19_Msk (0x01UL << USIC_CH_PCR_CTR19_Pos) /*!< USIC_CH PCR: CTR19 Mask */\r
+#define USIC_CH_PCR_CTR20_Pos 20 /*!< USIC_CH PCR: CTR20 Position */\r
+#define USIC_CH_PCR_CTR20_Msk (0x01UL << USIC_CH_PCR_CTR20_Pos) /*!< USIC_CH PCR: CTR20 Mask */\r
+#define USIC_CH_PCR_CTR21_Pos 21 /*!< USIC_CH PCR: CTR21 Position */\r
+#define USIC_CH_PCR_CTR21_Msk (0x01UL << USIC_CH_PCR_CTR21_Pos) /*!< USIC_CH PCR: CTR21 Mask */\r
+#define USIC_CH_PCR_CTR22_Pos 22 /*!< USIC_CH PCR: CTR22 Position */\r
+#define USIC_CH_PCR_CTR22_Msk (0x01UL << USIC_CH_PCR_CTR22_Pos) /*!< USIC_CH PCR: CTR22 Mask */\r
+#define USIC_CH_PCR_CTR23_Pos 23 /*!< USIC_CH PCR: CTR23 Position */\r
+#define USIC_CH_PCR_CTR23_Msk (0x01UL << USIC_CH_PCR_CTR23_Pos) /*!< USIC_CH PCR: CTR23 Mask */\r
+#define USIC_CH_PCR_CTR24_Pos 24 /*!< USIC_CH PCR: CTR24 Position */\r
+#define USIC_CH_PCR_CTR24_Msk (0x01UL << USIC_CH_PCR_CTR24_Pos) /*!< USIC_CH PCR: CTR24 Mask */\r
+#define USIC_CH_PCR_CTR25_Pos 25 /*!< USIC_CH PCR: CTR25 Position */\r
+#define USIC_CH_PCR_CTR25_Msk (0x01UL << USIC_CH_PCR_CTR25_Pos) /*!< USIC_CH PCR: CTR25 Mask */\r
+#define USIC_CH_PCR_CTR26_Pos 26 /*!< USIC_CH PCR: CTR26 Position */\r
+#define USIC_CH_PCR_CTR26_Msk (0x01UL << USIC_CH_PCR_CTR26_Pos) /*!< USIC_CH PCR: CTR26 Mask */\r
+#define USIC_CH_PCR_CTR27_Pos 27 /*!< USIC_CH PCR: CTR27 Position */\r
+#define USIC_CH_PCR_CTR27_Msk (0x01UL << USIC_CH_PCR_CTR27_Pos) /*!< USIC_CH PCR: CTR27 Mask */\r
+#define USIC_CH_PCR_CTR28_Pos 28 /*!< USIC_CH PCR: CTR28 Position */\r
+#define USIC_CH_PCR_CTR28_Msk (0x01UL << USIC_CH_PCR_CTR28_Pos) /*!< USIC_CH PCR: CTR28 Mask */\r
+#define USIC_CH_PCR_CTR29_Pos 29 /*!< USIC_CH PCR: CTR29 Position */\r
+#define USIC_CH_PCR_CTR29_Msk (0x01UL << USIC_CH_PCR_CTR29_Pos) /*!< USIC_CH PCR: CTR29 Mask */\r
+#define USIC_CH_PCR_CTR30_Pos 30 /*!< USIC_CH PCR: CTR30 Position */\r
+#define USIC_CH_PCR_CTR30_Msk (0x01UL << USIC_CH_PCR_CTR30_Pos) /*!< USIC_CH PCR: CTR30 Mask */\r
+#define USIC_CH_PCR_CTR31_Pos 31 /*!< USIC_CH PCR: CTR31 Position */\r
+#define USIC_CH_PCR_CTR31_Msk (0x01UL << USIC_CH_PCR_CTR31_Pos) /*!< USIC_CH PCR: CTR31 Mask */\r
+\r
+/* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */\r
+#define USIC_CH_PCR_ASCMode_SMD_Pos 0 /*!< USIC_CH PCR_ASCMode: SMD Position */\r
+#define USIC_CH_PCR_ASCMode_SMD_Msk (0x01UL << USIC_CH_PCR_ASCMode_SMD_Pos) /*!< USIC_CH PCR_ASCMode: SMD Mask */\r
+#define USIC_CH_PCR_ASCMode_STPB_Pos 1 /*!< USIC_CH PCR_ASCMode: STPB Position */\r
+#define USIC_CH_PCR_ASCMode_STPB_Msk (0x01UL << USIC_CH_PCR_ASCMode_STPB_Pos) /*!< USIC_CH PCR_ASCMode: STPB Mask */\r
+#define USIC_CH_PCR_ASCMode_IDM_Pos 2 /*!< USIC_CH PCR_ASCMode: IDM Position */\r
+#define USIC_CH_PCR_ASCMode_IDM_Msk (0x01UL << USIC_CH_PCR_ASCMode_IDM_Pos) /*!< USIC_CH PCR_ASCMode: IDM Mask */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Pos 3 /*!< USIC_CH PCR_ASCMode: SBIEN Position */\r
+#define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_SBIEN_Pos) /*!< USIC_CH PCR_ASCMode: SBIEN Mask */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Pos 4 /*!< USIC_CH PCR_ASCMode: CDEN Position */\r
+#define USIC_CH_PCR_ASCMode_CDEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_CDEN_Pos) /*!< USIC_CH PCR_ASCMode: CDEN Mask */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Pos 5 /*!< USIC_CH PCR_ASCMode: RNIEN Position */\r
+#define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RNIEN_Pos) /*!< USIC_CH PCR_ASCMode: RNIEN Mask */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Pos 6 /*!< USIC_CH PCR_ASCMode: FEIEN Position */\r
+#define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FEIEN_Pos) /*!< USIC_CH PCR_ASCMode: FEIEN Mask */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Pos 7 /*!< USIC_CH PCR_ASCMode: FFIEN Position */\r
+#define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_FFIEN_Pos) /*!< USIC_CH PCR_ASCMode: FFIEN Mask */\r
+#define USIC_CH_PCR_ASCMode_SP_Pos 8 /*!< USIC_CH PCR_ASCMode: SP Position */\r
+#define USIC_CH_PCR_ASCMode_SP_Msk (0x1fUL << USIC_CH_PCR_ASCMode_SP_Pos) /*!< USIC_CH PCR_ASCMode: SP Mask */\r
+#define USIC_CH_PCR_ASCMode_PL_Pos 13 /*!< USIC_CH PCR_ASCMode: PL Position */\r
+#define USIC_CH_PCR_ASCMode_PL_Msk (0x07UL << USIC_CH_PCR_ASCMode_PL_Pos) /*!< USIC_CH PCR_ASCMode: PL Mask */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Pos 16 /*!< USIC_CH PCR_ASCMode: RSTEN Position */\r
+#define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_RSTEN_Pos) /*!< USIC_CH PCR_ASCMode: RSTEN Mask */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Pos 17 /*!< USIC_CH PCR_ASCMode: TSTEN Position */\r
+#define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x01UL << USIC_CH_PCR_ASCMode_TSTEN_Pos) /*!< USIC_CH PCR_ASCMode: TSTEN Mask */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Pos 31 /*!< USIC_CH PCR_ASCMode: MCLK Position */\r
+#define USIC_CH_PCR_ASCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_ASCMode_MCLK_Pos) /*!< USIC_CH PCR_ASCMode: MCLK Mask */\r
+\r
+/* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Pos 0 /*!< USIC_CH PCR_SSCMode: MSLSEN Position */\r
+#define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSEN Mask */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Pos 1 /*!< USIC_CH PCR_SSCMode: SELCTR Position */\r
+#define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELCTR_Pos) /*!< USIC_CH PCR_SSCMode: SELCTR Mask */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Pos 2 /*!< USIC_CH PCR_SSCMode: SELINV Position */\r
+#define USIC_CH_PCR_SSCMode_SELINV_Msk (0x01UL << USIC_CH_PCR_SSCMode_SELINV_Pos) /*!< USIC_CH PCR_SSCMode: SELINV Mask */\r
+#define USIC_CH_PCR_SSCMode_FEM_Pos 3 /*!< USIC_CH PCR_SSCMode: FEM Position */\r
+#define USIC_CH_PCR_SSCMode_FEM_Msk (0x01UL << USIC_CH_PCR_SSCMode_FEM_Pos) /*!< USIC_CH PCR_SSCMode: FEM Mask */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Pos 4 /*!< USIC_CH PCR_SSCMode: CTQSEL1 Position */\r
+#define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x03UL << USIC_CH_PCR_SSCMode_CTQSEL1_Pos) /*!< USIC_CH PCR_SSCMode: CTQSEL1 Mask */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Pos 6 /*!< USIC_CH PCR_SSCMode: PCTQ1 Position */\r
+#define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0x03UL << USIC_CH_PCR_SSCMode_PCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: PCTQ1 Mask */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Pos 8 /*!< USIC_CH PCR_SSCMode: DCTQ1 Position */\r
+#define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1fUL << USIC_CH_PCR_SSCMode_DCTQ1_Pos) /*!< USIC_CH PCR_SSCMode: DCTQ1 Mask */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Pos 13 /*!< USIC_CH PCR_SSCMode: PARIEN Position */\r
+#define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_PARIEN_Pos) /*!< USIC_CH PCR_SSCMode: PARIEN Mask */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Pos 14 /*!< USIC_CH PCR_SSCMode: MSLSIEN Position */\r
+#define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_MSLSIEN_Pos) /*!< USIC_CH PCR_SSCMode: MSLSIEN Mask */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_SSCMode: DX2TIEN Position */\r
+#define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_DX2TIEN_Pos) /*!< USIC_CH PCR_SSCMode: DX2TIEN Mask */\r
+#define USIC_CH_PCR_SSCMode_SELO_Pos 16 /*!< USIC_CH PCR_SSCMode: SELO Position */\r
+#define USIC_CH_PCR_SSCMode_SELO_Msk (0x000000ffUL << USIC_CH_PCR_SSCMode_SELO_Pos) /*!< USIC_CH PCR_SSCMode: SELO Mask */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Pos 24 /*!< USIC_CH PCR_SSCMode: TIWEN Position */\r
+#define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x01UL << USIC_CH_PCR_SSCMode_TIWEN_Pos) /*!< USIC_CH PCR_SSCMode: TIWEN Mask */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Pos 31 /*!< USIC_CH PCR_SSCMode: MCLK Position */\r
+#define USIC_CH_PCR_SSCMode_MCLK_Msk (0x01UL << USIC_CH_PCR_SSCMode_MCLK_Pos) /*!< USIC_CH PCR_SSCMode: MCLK Mask */\r
+\r
+/* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */\r
+#define USIC_CH_PCR_IICMode_SLAD_Pos 0 /*!< USIC_CH PCR_IICMode: SLAD Position */\r
+#define USIC_CH_PCR_IICMode_SLAD_Msk (0x0000ffffUL << USIC_CH_PCR_IICMode_SLAD_Pos) /*!< USIC_CH PCR_IICMode: SLAD Mask */\r
+#define USIC_CH_PCR_IICMode_ACK00_Pos 16 /*!< USIC_CH PCR_IICMode: ACK00 Position */\r
+#define USIC_CH_PCR_IICMode_ACK00_Msk (0x01UL << USIC_CH_PCR_IICMode_ACK00_Pos) /*!< USIC_CH PCR_IICMode: ACK00 Mask */\r
+#define USIC_CH_PCR_IICMode_STIM_Pos 17 /*!< USIC_CH PCR_IICMode: STIM Position */\r
+#define USIC_CH_PCR_IICMode_STIM_Msk (0x01UL << USIC_CH_PCR_IICMode_STIM_Pos) /*!< USIC_CH PCR_IICMode: STIM Mask */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Pos 18 /*!< USIC_CH PCR_IICMode: SCRIEN Position */\r
+#define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SCRIEN_Pos) /*!< USIC_CH PCR_IICMode: SCRIEN Mask */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Pos 19 /*!< USIC_CH PCR_IICMode: RSCRIEN Position */\r
+#define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_RSCRIEN_Pos) /*!< USIC_CH PCR_IICMode: RSCRIEN Mask */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Pos 20 /*!< USIC_CH PCR_IICMode: PCRIEN Position */\r
+#define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_PCRIEN_Pos) /*!< USIC_CH PCR_IICMode: PCRIEN Mask */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Pos 21 /*!< USIC_CH PCR_IICMode: NACKIEN Position */\r
+#define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_NACKIEN_Pos) /*!< USIC_CH PCR_IICMode: NACKIEN Mask */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Pos 22 /*!< USIC_CH PCR_IICMode: ARLIEN Position */\r
+#define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ARLIEN_Pos) /*!< USIC_CH PCR_IICMode: ARLIEN Mask */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Pos 23 /*!< USIC_CH PCR_IICMode: SRRIEN Position */\r
+#define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_SRRIEN_Pos) /*!< USIC_CH PCR_IICMode: SRRIEN Mask */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Pos 24 /*!< USIC_CH PCR_IICMode: ERRIEN Position */\r
+#define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ERRIEN_Pos) /*!< USIC_CH PCR_IICMode: ERRIEN Mask */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Pos 25 /*!< USIC_CH PCR_IICMode: SACKDIS Position */\r
+#define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x01UL << USIC_CH_PCR_IICMode_SACKDIS_Pos) /*!< USIC_CH PCR_IICMode: SACKDIS Mask */\r
+#define USIC_CH_PCR_IICMode_HDEL_Pos 26 /*!< USIC_CH PCR_IICMode: HDEL Position */\r
+#define USIC_CH_PCR_IICMode_HDEL_Msk (0x0fUL << USIC_CH_PCR_IICMode_HDEL_Pos) /*!< USIC_CH PCR_IICMode: HDEL Mask */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Pos 30 /*!< USIC_CH PCR_IICMode: ACKIEN Position */\r
+#define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x01UL << USIC_CH_PCR_IICMode_ACKIEN_Pos) /*!< USIC_CH PCR_IICMode: ACKIEN Mask */\r
+#define USIC_CH_PCR_IICMode_MCLK_Pos 31 /*!< USIC_CH PCR_IICMode: MCLK Position */\r
+#define USIC_CH_PCR_IICMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IICMode_MCLK_Pos) /*!< USIC_CH PCR_IICMode: MCLK Mask */\r
+\r
+/* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Pos 0 /*!< USIC_CH PCR_IISMode: WAGEN Position */\r
+#define USIC_CH_PCR_IISMode_WAGEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAGEN_Pos) /*!< USIC_CH PCR_IISMode: WAGEN Mask */\r
+#define USIC_CH_PCR_IISMode_DTEN_Pos 1 /*!< USIC_CH PCR_IISMode: DTEN Position */\r
+#define USIC_CH_PCR_IISMode_DTEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DTEN_Pos) /*!< USIC_CH PCR_IISMode: DTEN Mask */\r
+#define USIC_CH_PCR_IISMode_SELINV_Pos 2 /*!< USIC_CH PCR_IISMode: SELINV Position */\r
+#define USIC_CH_PCR_IISMode_SELINV_Msk (0x01UL << USIC_CH_PCR_IISMode_SELINV_Pos) /*!< USIC_CH PCR_IISMode: SELINV Mask */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Pos 4 /*!< USIC_CH PCR_IISMode: WAFEIEN Position */\r
+#define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAFEIEN_Pos) /*!< USIC_CH PCR_IISMode: WAFEIEN Mask */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Pos 5 /*!< USIC_CH PCR_IISMode: WAREIEN Position */\r
+#define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_WAREIEN_Pos) /*!< USIC_CH PCR_IISMode: WAREIEN Mask */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Pos 6 /*!< USIC_CH PCR_IISMode: ENDIEN Position */\r
+#define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_ENDIEN_Pos) /*!< USIC_CH PCR_IISMode: ENDIEN Mask */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Pos 15 /*!< USIC_CH PCR_IISMode: DX2TIEN Position */\r
+#define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x01UL << USIC_CH_PCR_IISMode_DX2TIEN_Pos) /*!< USIC_CH PCR_IISMode: DX2TIEN Mask */\r
+#define USIC_CH_PCR_IISMode_TDEL_Pos 16 /*!< USIC_CH PCR_IISMode: TDEL Position */\r
+#define USIC_CH_PCR_IISMode_TDEL_Msk (0x3fUL << USIC_CH_PCR_IISMode_TDEL_Pos) /*!< USIC_CH PCR_IISMode: TDEL Mask */\r
+#define USIC_CH_PCR_IISMode_MCLK_Pos 31 /*!< USIC_CH PCR_IISMode: MCLK Position */\r
+#define USIC_CH_PCR_IISMode_MCLK_Msk (0x01UL << USIC_CH_PCR_IISMode_MCLK_Pos) /*!< USIC_CH PCR_IISMode: MCLK Mask */\r
+\r
+/* --------------------------------- USIC_CH_CCR -------------------------------- */\r
+#define USIC_CH_CCR_MODE_Pos 0 /*!< USIC_CH CCR: MODE Position */\r
+#define USIC_CH_CCR_MODE_Msk (0x0fUL << USIC_CH_CCR_MODE_Pos) /*!< USIC_CH CCR: MODE Mask */\r
+#define USIC_CH_CCR_HPCEN_Pos 6 /*!< USIC_CH CCR: HPCEN Position */\r
+#define USIC_CH_CCR_HPCEN_Msk (0x03UL << USIC_CH_CCR_HPCEN_Pos) /*!< USIC_CH CCR: HPCEN Mask */\r
+#define USIC_CH_CCR_PM_Pos 8 /*!< USIC_CH CCR: PM Position */\r
+#define USIC_CH_CCR_PM_Msk (0x03UL << USIC_CH_CCR_PM_Pos) /*!< USIC_CH CCR: PM Mask */\r
+#define USIC_CH_CCR_RSIEN_Pos 10 /*!< USIC_CH CCR: RSIEN Position */\r
+#define USIC_CH_CCR_RSIEN_Msk (0x01UL << USIC_CH_CCR_RSIEN_Pos) /*!< USIC_CH CCR: RSIEN Mask */\r
+#define USIC_CH_CCR_DLIEN_Pos 11 /*!< USIC_CH CCR: DLIEN Position */\r
+#define USIC_CH_CCR_DLIEN_Msk (0x01UL << USIC_CH_CCR_DLIEN_Pos) /*!< USIC_CH CCR: DLIEN Mask */\r
+#define USIC_CH_CCR_TSIEN_Pos 12 /*!< USIC_CH CCR: TSIEN Position */\r
+#define USIC_CH_CCR_TSIEN_Msk (0x01UL << USIC_CH_CCR_TSIEN_Pos) /*!< USIC_CH CCR: TSIEN Mask */\r
+#define USIC_CH_CCR_TBIEN_Pos 13 /*!< USIC_CH CCR: TBIEN Position */\r
+#define USIC_CH_CCR_TBIEN_Msk (0x01UL << USIC_CH_CCR_TBIEN_Pos) /*!< USIC_CH CCR: TBIEN Mask */\r
+#define USIC_CH_CCR_RIEN_Pos 14 /*!< USIC_CH CCR: RIEN Position */\r
+#define USIC_CH_CCR_RIEN_Msk (0x01UL << USIC_CH_CCR_RIEN_Pos) /*!< USIC_CH CCR: RIEN Mask */\r
+#define USIC_CH_CCR_AIEN_Pos 15 /*!< USIC_CH CCR: AIEN Position */\r
+#define USIC_CH_CCR_AIEN_Msk (0x01UL << USIC_CH_CCR_AIEN_Pos) /*!< USIC_CH CCR: AIEN Mask */\r
+#define USIC_CH_CCR_BRGIEN_Pos 16 /*!< USIC_CH CCR: BRGIEN Position */\r
+#define USIC_CH_CCR_BRGIEN_Msk (0x01UL << USIC_CH_CCR_BRGIEN_Pos) /*!< USIC_CH CCR: BRGIEN Mask */\r
+\r
+/* -------------------------------- USIC_CH_CMTR -------------------------------- */\r
+#define USIC_CH_CMTR_CTV_Pos 0 /*!< USIC_CH CMTR: CTV Position */\r
+#define USIC_CH_CMTR_CTV_Msk (0x000003ffUL << USIC_CH_CMTR_CTV_Pos) /*!< USIC_CH CMTR: CTV Mask */\r
+\r
+/* --------------------------------- USIC_CH_PSR -------------------------------- */\r
+#define USIC_CH_PSR_ST0_Pos 0 /*!< USIC_CH PSR: ST0 Position */\r
+#define USIC_CH_PSR_ST0_Msk (0x01UL << USIC_CH_PSR_ST0_Pos) /*!< USIC_CH PSR: ST0 Mask */\r
+#define USIC_CH_PSR_ST1_Pos 1 /*!< USIC_CH PSR: ST1 Position */\r
+#define USIC_CH_PSR_ST1_Msk (0x01UL << USIC_CH_PSR_ST1_Pos) /*!< USIC_CH PSR: ST1 Mask */\r
+#define USIC_CH_PSR_ST2_Pos 2 /*!< USIC_CH PSR: ST2 Position */\r
+#define USIC_CH_PSR_ST2_Msk (0x01UL << USIC_CH_PSR_ST2_Pos) /*!< USIC_CH PSR: ST2 Mask */\r
+#define USIC_CH_PSR_ST3_Pos 3 /*!< USIC_CH PSR: ST3 Position */\r
+#define USIC_CH_PSR_ST3_Msk (0x01UL << USIC_CH_PSR_ST3_Pos) /*!< USIC_CH PSR: ST3 Mask */\r
+#define USIC_CH_PSR_ST4_Pos 4 /*!< USIC_CH PSR: ST4 Position */\r
+#define USIC_CH_PSR_ST4_Msk (0x01UL << USIC_CH_PSR_ST4_Pos) /*!< USIC_CH PSR: ST4 Mask */\r
+#define USIC_CH_PSR_ST5_Pos 5 /*!< USIC_CH PSR: ST5 Position */\r
+#define USIC_CH_PSR_ST5_Msk (0x01UL << USIC_CH_PSR_ST5_Pos) /*!< USIC_CH PSR: ST5 Mask */\r
+#define USIC_CH_PSR_ST6_Pos 6 /*!< USIC_CH PSR: ST6 Position */\r
+#define USIC_CH_PSR_ST6_Msk (0x01UL << USIC_CH_PSR_ST6_Pos) /*!< USIC_CH PSR: ST6 Mask */\r
+#define USIC_CH_PSR_ST7_Pos 7 /*!< USIC_CH PSR: ST7 Position */\r
+#define USIC_CH_PSR_ST7_Msk (0x01UL << USIC_CH_PSR_ST7_Pos) /*!< USIC_CH PSR: ST7 Mask */\r
+#define USIC_CH_PSR_ST8_Pos 8 /*!< USIC_CH PSR: ST8 Position */\r
+#define USIC_CH_PSR_ST8_Msk (0x01UL << USIC_CH_PSR_ST8_Pos) /*!< USIC_CH PSR: ST8 Mask */\r
+#define USIC_CH_PSR_ST9_Pos 9 /*!< USIC_CH PSR: ST9 Position */\r
+#define USIC_CH_PSR_ST9_Msk (0x01UL << USIC_CH_PSR_ST9_Pos) /*!< USIC_CH PSR: ST9 Mask */\r
+#define USIC_CH_PSR_RSIF_Pos 10 /*!< USIC_CH PSR: RSIF Position */\r
+#define USIC_CH_PSR_RSIF_Msk (0x01UL << USIC_CH_PSR_RSIF_Pos) /*!< USIC_CH PSR: RSIF Mask */\r
+#define USIC_CH_PSR_DLIF_Pos 11 /*!< USIC_CH PSR: DLIF Position */\r
+#define USIC_CH_PSR_DLIF_Msk (0x01UL << USIC_CH_PSR_DLIF_Pos) /*!< USIC_CH PSR: DLIF Mask */\r
+#define USIC_CH_PSR_TSIF_Pos 12 /*!< USIC_CH PSR: TSIF Position */\r
+#define USIC_CH_PSR_TSIF_Msk (0x01UL << USIC_CH_PSR_TSIF_Pos) /*!< USIC_CH PSR: TSIF Mask */\r
+#define USIC_CH_PSR_TBIF_Pos 13 /*!< USIC_CH PSR: TBIF Position */\r
+#define USIC_CH_PSR_TBIF_Msk (0x01UL << USIC_CH_PSR_TBIF_Pos) /*!< USIC_CH PSR: TBIF Mask */\r
+#define USIC_CH_PSR_RIF_Pos 14 /*!< USIC_CH PSR: RIF Position */\r
+#define USIC_CH_PSR_RIF_Msk (0x01UL << USIC_CH_PSR_RIF_Pos) /*!< USIC_CH PSR: RIF Mask */\r
+#define USIC_CH_PSR_AIF_Pos 15 /*!< USIC_CH PSR: AIF Position */\r
+#define USIC_CH_PSR_AIF_Msk (0x01UL << USIC_CH_PSR_AIF_Pos) /*!< USIC_CH PSR: AIF Mask */\r
+#define USIC_CH_PSR_BRGIF_Pos 16 /*!< USIC_CH PSR: BRGIF Position */\r
+#define USIC_CH_PSR_BRGIF_Msk (0x01UL << USIC_CH_PSR_BRGIF_Pos) /*!< USIC_CH PSR: BRGIF Mask */\r
+\r
+/* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Pos 0 /*!< USIC_CH PSR_ASCMode: TXIDLE Position */\r
+#define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_TXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: TXIDLE Mask */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Pos 1 /*!< USIC_CH PSR_ASCMode: RXIDLE Position */\r
+#define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x01UL << USIC_CH_PSR_ASCMode_RXIDLE_Pos) /*!< USIC_CH PSR_ASCMode: RXIDLE Mask */\r
+#define USIC_CH_PSR_ASCMode_SBD_Pos 2 /*!< USIC_CH PSR_ASCMode: SBD Position */\r
+#define USIC_CH_PSR_ASCMode_SBD_Msk (0x01UL << USIC_CH_PSR_ASCMode_SBD_Pos) /*!< USIC_CH PSR_ASCMode: SBD Mask */\r
+#define USIC_CH_PSR_ASCMode_COL_Pos 3 /*!< USIC_CH PSR_ASCMode: COL Position */\r
+#define USIC_CH_PSR_ASCMode_COL_Msk (0x01UL << USIC_CH_PSR_ASCMode_COL_Pos) /*!< USIC_CH PSR_ASCMode: COL Mask */\r
+#define USIC_CH_PSR_ASCMode_RNS_Pos 4 /*!< USIC_CH PSR_ASCMode: RNS Position */\r
+#define USIC_CH_PSR_ASCMode_RNS_Msk (0x01UL << USIC_CH_PSR_ASCMode_RNS_Pos) /*!< USIC_CH PSR_ASCMode: RNS Mask */\r
+#define USIC_CH_PSR_ASCMode_FER0_Pos 5 /*!< USIC_CH PSR_ASCMode: FER0 Position */\r
+#define USIC_CH_PSR_ASCMode_FER0_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER0_Pos) /*!< USIC_CH PSR_ASCMode: FER0 Mask */\r
+#define USIC_CH_PSR_ASCMode_FER1_Pos 6 /*!< USIC_CH PSR_ASCMode: FER1 Position */\r
+#define USIC_CH_PSR_ASCMode_FER1_Msk (0x01UL << USIC_CH_PSR_ASCMode_FER1_Pos) /*!< USIC_CH PSR_ASCMode: FER1 Mask */\r
+#define USIC_CH_PSR_ASCMode_RFF_Pos 7 /*!< USIC_CH PSR_ASCMode: RFF Position */\r
+#define USIC_CH_PSR_ASCMode_RFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RFF_Pos) /*!< USIC_CH PSR_ASCMode: RFF Mask */\r
+#define USIC_CH_PSR_ASCMode_TFF_Pos 8 /*!< USIC_CH PSR_ASCMode: TFF Position */\r
+#define USIC_CH_PSR_ASCMode_TFF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TFF_Pos) /*!< USIC_CH PSR_ASCMode: TFF Mask */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Pos 9 /*!< USIC_CH PSR_ASCMode: BUSY Position */\r
+#define USIC_CH_PSR_ASCMode_BUSY_Msk (0x01UL << USIC_CH_PSR_ASCMode_BUSY_Pos) /*!< USIC_CH PSR_ASCMode: BUSY Mask */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Pos 10 /*!< USIC_CH PSR_ASCMode: RSIF Position */\r
+#define USIC_CH_PSR_ASCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RSIF_Pos) /*!< USIC_CH PSR_ASCMode: RSIF Mask */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Pos 11 /*!< USIC_CH PSR_ASCMode: DLIF Position */\r
+#define USIC_CH_PSR_ASCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_DLIF_Pos) /*!< USIC_CH PSR_ASCMode: DLIF Mask */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Pos 12 /*!< USIC_CH PSR_ASCMode: TSIF Position */\r
+#define USIC_CH_PSR_ASCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TSIF_Pos) /*!< USIC_CH PSR_ASCMode: TSIF Mask */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Pos 13 /*!< USIC_CH PSR_ASCMode: TBIF Position */\r
+#define USIC_CH_PSR_ASCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_TBIF_Pos) /*!< USIC_CH PSR_ASCMode: TBIF Mask */\r
+#define USIC_CH_PSR_ASCMode_RIF_Pos 14 /*!< USIC_CH PSR_ASCMode: RIF Position */\r
+#define USIC_CH_PSR_ASCMode_RIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_RIF_Pos) /*!< USIC_CH PSR_ASCMode: RIF Mask */\r
+#define USIC_CH_PSR_ASCMode_AIF_Pos 15 /*!< USIC_CH PSR_ASCMode: AIF Position */\r
+#define USIC_CH_PSR_ASCMode_AIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_AIF_Pos) /*!< USIC_CH PSR_ASCMode: AIF Mask */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_ASCMode: BRGIF Position */\r
+#define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_ASCMode_BRGIF_Pos) /*!< USIC_CH PSR_ASCMode: BRGIF Mask */\r
+\r
+/* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Pos 0 /*!< USIC_CH PSR_SSCMode: MSLS Position */\r
+#define USIC_CH_PSR_SSCMode_MSLS_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLS_Pos) /*!< USIC_CH PSR_SSCMode: MSLS Mask */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Pos 1 /*!< USIC_CH PSR_SSCMode: DX2S Position */\r
+#define USIC_CH_PSR_SSCMode_DX2S_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2S_Pos) /*!< USIC_CH PSR_SSCMode: DX2S Mask */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Pos 2 /*!< USIC_CH PSR_SSCMode: MSLSEV Position */\r
+#define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_MSLSEV_Pos) /*!< USIC_CH PSR_SSCMode: MSLSEV Mask */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_SSCMode: DX2TEV Position */\r
+#define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_SSCMode_DX2TEV_Pos) /*!< USIC_CH PSR_SSCMode: DX2TEV Mask */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Pos 4 /*!< USIC_CH PSR_SSCMode: PARERR Position */\r
+#define USIC_CH_PSR_SSCMode_PARERR_Msk (0x01UL << USIC_CH_PSR_SSCMode_PARERR_Pos) /*!< USIC_CH PSR_SSCMode: PARERR Mask */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Pos 10 /*!< USIC_CH PSR_SSCMode: RSIF Position */\r
+#define USIC_CH_PSR_SSCMode_RSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RSIF_Pos) /*!< USIC_CH PSR_SSCMode: RSIF Mask */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Pos 11 /*!< USIC_CH PSR_SSCMode: DLIF Position */\r
+#define USIC_CH_PSR_SSCMode_DLIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_DLIF_Pos) /*!< USIC_CH PSR_SSCMode: DLIF Mask */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Pos 12 /*!< USIC_CH PSR_SSCMode: TSIF Position */\r
+#define USIC_CH_PSR_SSCMode_TSIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TSIF_Pos) /*!< USIC_CH PSR_SSCMode: TSIF Mask */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Pos 13 /*!< USIC_CH PSR_SSCMode: TBIF Position */\r
+#define USIC_CH_PSR_SSCMode_TBIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_TBIF_Pos) /*!< USIC_CH PSR_SSCMode: TBIF Mask */\r
+#define USIC_CH_PSR_SSCMode_RIF_Pos 14 /*!< USIC_CH PSR_SSCMode: RIF Position */\r
+#define USIC_CH_PSR_SSCMode_RIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_RIF_Pos) /*!< USIC_CH PSR_SSCMode: RIF Mask */\r
+#define USIC_CH_PSR_SSCMode_AIF_Pos 15 /*!< USIC_CH PSR_SSCMode: AIF Position */\r
+#define USIC_CH_PSR_SSCMode_AIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_AIF_Pos) /*!< USIC_CH PSR_SSCMode: AIF Mask */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Pos 16 /*!< USIC_CH PSR_SSCMode: BRGIF Position */\r
+#define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_SSCMode_BRGIF_Pos) /*!< USIC_CH PSR_SSCMode: BRGIF Mask */\r
+\r
+/* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Pos 0 /*!< USIC_CH PSR_IICMode: SLSEL Position */\r
+#define USIC_CH_PSR_IICMode_SLSEL_Msk (0x01UL << USIC_CH_PSR_IICMode_SLSEL_Pos) /*!< USIC_CH PSR_IICMode: SLSEL Mask */\r
+#define USIC_CH_PSR_IICMode_WTDF_Pos 1 /*!< USIC_CH PSR_IICMode: WTDF Position */\r
+#define USIC_CH_PSR_IICMode_WTDF_Msk (0x01UL << USIC_CH_PSR_IICMode_WTDF_Pos) /*!< USIC_CH PSR_IICMode: WTDF Mask */\r
+#define USIC_CH_PSR_IICMode_SCR_Pos 2 /*!< USIC_CH PSR_IICMode: SCR Position */\r
+#define USIC_CH_PSR_IICMode_SCR_Msk (0x01UL << USIC_CH_PSR_IICMode_SCR_Pos) /*!< USIC_CH PSR_IICMode: SCR Mask */\r
+#define USIC_CH_PSR_IICMode_RSCR_Pos 3 /*!< USIC_CH PSR_IICMode: RSCR Position */\r
+#define USIC_CH_PSR_IICMode_RSCR_Msk (0x01UL << USIC_CH_PSR_IICMode_RSCR_Pos) /*!< USIC_CH PSR_IICMode: RSCR Mask */\r
+#define USIC_CH_PSR_IICMode_PCR_Pos 4 /*!< USIC_CH PSR_IICMode: PCR Position */\r
+#define USIC_CH_PSR_IICMode_PCR_Msk (0x01UL << USIC_CH_PSR_IICMode_PCR_Pos) /*!< USIC_CH PSR_IICMode: PCR Mask */\r
+#define USIC_CH_PSR_IICMode_NACK_Pos 5 /*!< USIC_CH PSR_IICMode: NACK Position */\r
+#define USIC_CH_PSR_IICMode_NACK_Msk (0x01UL << USIC_CH_PSR_IICMode_NACK_Pos) /*!< USIC_CH PSR_IICMode: NACK Mask */\r
+#define USIC_CH_PSR_IICMode_ARL_Pos 6 /*!< USIC_CH PSR_IICMode: ARL Position */\r
+#define USIC_CH_PSR_IICMode_ARL_Msk (0x01UL << USIC_CH_PSR_IICMode_ARL_Pos) /*!< USIC_CH PSR_IICMode: ARL Mask */\r
+#define USIC_CH_PSR_IICMode_SRR_Pos 7 /*!< USIC_CH PSR_IICMode: SRR Position */\r
+#define USIC_CH_PSR_IICMode_SRR_Msk (0x01UL << USIC_CH_PSR_IICMode_SRR_Pos) /*!< USIC_CH PSR_IICMode: SRR Mask */\r
+#define USIC_CH_PSR_IICMode_ERR_Pos 8 /*!< USIC_CH PSR_IICMode: ERR Position */\r
+#define USIC_CH_PSR_IICMode_ERR_Msk (0x01UL << USIC_CH_PSR_IICMode_ERR_Pos) /*!< USIC_CH PSR_IICMode: ERR Mask */\r
+#define USIC_CH_PSR_IICMode_ACK_Pos 9 /*!< USIC_CH PSR_IICMode: ACK Position */\r
+#define USIC_CH_PSR_IICMode_ACK_Msk (0x01UL << USIC_CH_PSR_IICMode_ACK_Pos) /*!< USIC_CH PSR_IICMode: ACK Mask */\r
+#define USIC_CH_PSR_IICMode_RSIF_Pos 10 /*!< USIC_CH PSR_IICMode: RSIF Position */\r
+#define USIC_CH_PSR_IICMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RSIF_Pos) /*!< USIC_CH PSR_IICMode: RSIF Mask */\r
+#define USIC_CH_PSR_IICMode_DLIF_Pos 11 /*!< USIC_CH PSR_IICMode: DLIF Position */\r
+#define USIC_CH_PSR_IICMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IICMode_DLIF_Pos) /*!< USIC_CH PSR_IICMode: DLIF Mask */\r
+#define USIC_CH_PSR_IICMode_TSIF_Pos 12 /*!< USIC_CH PSR_IICMode: TSIF Position */\r
+#define USIC_CH_PSR_IICMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TSIF_Pos) /*!< USIC_CH PSR_IICMode: TSIF Mask */\r
+#define USIC_CH_PSR_IICMode_TBIF_Pos 13 /*!< USIC_CH PSR_IICMode: TBIF Position */\r
+#define USIC_CH_PSR_IICMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IICMode_TBIF_Pos) /*!< USIC_CH PSR_IICMode: TBIF Mask */\r
+#define USIC_CH_PSR_IICMode_RIF_Pos 14 /*!< USIC_CH PSR_IICMode: RIF Position */\r
+#define USIC_CH_PSR_IICMode_RIF_Msk (0x01UL << USIC_CH_PSR_IICMode_RIF_Pos) /*!< USIC_CH PSR_IICMode: RIF Mask */\r
+#define USIC_CH_PSR_IICMode_AIF_Pos 15 /*!< USIC_CH PSR_IICMode: AIF Position */\r
+#define USIC_CH_PSR_IICMode_AIF_Msk (0x01UL << USIC_CH_PSR_IICMode_AIF_Pos) /*!< USIC_CH PSR_IICMode: AIF Mask */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IICMode: BRGIF Position */\r
+#define USIC_CH_PSR_IICMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IICMode_BRGIF_Pos) /*!< USIC_CH PSR_IICMode: BRGIF Mask */\r
+\r
+/* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */\r
+#define USIC_CH_PSR_IISMode_WA_Pos 0 /*!< USIC_CH PSR_IISMode: WA Position */\r
+#define USIC_CH_PSR_IISMode_WA_Msk (0x01UL << USIC_CH_PSR_IISMode_WA_Pos) /*!< USIC_CH PSR_IISMode: WA Mask */\r
+#define USIC_CH_PSR_IISMode_DX2S_Pos 1 /*!< USIC_CH PSR_IISMode: DX2S Position */\r
+#define USIC_CH_PSR_IISMode_DX2S_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2S_Pos) /*!< USIC_CH PSR_IISMode: DX2S Mask */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Pos 3 /*!< USIC_CH PSR_IISMode: DX2TEV Position */\r
+#define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x01UL << USIC_CH_PSR_IISMode_DX2TEV_Pos) /*!< USIC_CH PSR_IISMode: DX2TEV Mask */\r
+#define USIC_CH_PSR_IISMode_WAFE_Pos 4 /*!< USIC_CH PSR_IISMode: WAFE Position */\r
+#define USIC_CH_PSR_IISMode_WAFE_Msk (0x01UL << USIC_CH_PSR_IISMode_WAFE_Pos) /*!< USIC_CH PSR_IISMode: WAFE Mask */\r
+#define USIC_CH_PSR_IISMode_WARE_Pos 5 /*!< USIC_CH PSR_IISMode: WARE Position */\r
+#define USIC_CH_PSR_IISMode_WARE_Msk (0x01UL << USIC_CH_PSR_IISMode_WARE_Pos) /*!< USIC_CH PSR_IISMode: WARE Mask */\r
+#define USIC_CH_PSR_IISMode_END_Pos 6 /*!< USIC_CH PSR_IISMode: END Position */\r
+#define USIC_CH_PSR_IISMode_END_Msk (0x01UL << USIC_CH_PSR_IISMode_END_Pos) /*!< USIC_CH PSR_IISMode: END Mask */\r
+#define USIC_CH_PSR_IISMode_RSIF_Pos 10 /*!< USIC_CH PSR_IISMode: RSIF Position */\r
+#define USIC_CH_PSR_IISMode_RSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RSIF_Pos) /*!< USIC_CH PSR_IISMode: RSIF Mask */\r
+#define USIC_CH_PSR_IISMode_DLIF_Pos 11 /*!< USIC_CH PSR_IISMode: DLIF Position */\r
+#define USIC_CH_PSR_IISMode_DLIF_Msk (0x01UL << USIC_CH_PSR_IISMode_DLIF_Pos) /*!< USIC_CH PSR_IISMode: DLIF Mask */\r
+#define USIC_CH_PSR_IISMode_TSIF_Pos 12 /*!< USIC_CH PSR_IISMode: TSIF Position */\r
+#define USIC_CH_PSR_IISMode_TSIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TSIF_Pos) /*!< USIC_CH PSR_IISMode: TSIF Mask */\r
+#define USIC_CH_PSR_IISMode_TBIF_Pos 13 /*!< USIC_CH PSR_IISMode: TBIF Position */\r
+#define USIC_CH_PSR_IISMode_TBIF_Msk (0x01UL << USIC_CH_PSR_IISMode_TBIF_Pos) /*!< USIC_CH PSR_IISMode: TBIF Mask */\r
+#define USIC_CH_PSR_IISMode_RIF_Pos 14 /*!< USIC_CH PSR_IISMode: RIF Position */\r
+#define USIC_CH_PSR_IISMode_RIF_Msk (0x01UL << USIC_CH_PSR_IISMode_RIF_Pos) /*!< USIC_CH PSR_IISMode: RIF Mask */\r
+#define USIC_CH_PSR_IISMode_AIF_Pos 15 /*!< USIC_CH PSR_IISMode: AIF Position */\r
+#define USIC_CH_PSR_IISMode_AIF_Msk (0x01UL << USIC_CH_PSR_IISMode_AIF_Pos) /*!< USIC_CH PSR_IISMode: AIF Mask */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Pos 16 /*!< USIC_CH PSR_IISMode: BRGIF Position */\r
+#define USIC_CH_PSR_IISMode_BRGIF_Msk (0x01UL << USIC_CH_PSR_IISMode_BRGIF_Pos) /*!< USIC_CH PSR_IISMode: BRGIF Mask */\r
+\r
+/* -------------------------------- USIC_CH_PSCR -------------------------------- */\r
+#define USIC_CH_PSCR_CST0_Pos 0 /*!< USIC_CH PSCR: CST0 Position */\r
+#define USIC_CH_PSCR_CST0_Msk (0x01UL << USIC_CH_PSCR_CST0_Pos) /*!< USIC_CH PSCR: CST0 Mask */\r
+#define USIC_CH_PSCR_CST1_Pos 1 /*!< USIC_CH PSCR: CST1 Position */\r
+#define USIC_CH_PSCR_CST1_Msk (0x01UL << USIC_CH_PSCR_CST1_Pos) /*!< USIC_CH PSCR: CST1 Mask */\r
+#define USIC_CH_PSCR_CST2_Pos 2 /*!< USIC_CH PSCR: CST2 Position */\r
+#define USIC_CH_PSCR_CST2_Msk (0x01UL << USIC_CH_PSCR_CST2_Pos) /*!< USIC_CH PSCR: CST2 Mask */\r
+#define USIC_CH_PSCR_CST3_Pos 3 /*!< USIC_CH PSCR: CST3 Position */\r
+#define USIC_CH_PSCR_CST3_Msk (0x01UL << USIC_CH_PSCR_CST3_Pos) /*!< USIC_CH PSCR: CST3 Mask */\r
+#define USIC_CH_PSCR_CST4_Pos 4 /*!< USIC_CH PSCR: CST4 Position */\r
+#define USIC_CH_PSCR_CST4_Msk (0x01UL << USIC_CH_PSCR_CST4_Pos) /*!< USIC_CH PSCR: CST4 Mask */\r
+#define USIC_CH_PSCR_CST5_Pos 5 /*!< USIC_CH PSCR: CST5 Position */\r
+#define USIC_CH_PSCR_CST5_Msk (0x01UL << USIC_CH_PSCR_CST5_Pos) /*!< USIC_CH PSCR: CST5 Mask */\r
+#define USIC_CH_PSCR_CST6_Pos 6 /*!< USIC_CH PSCR: CST6 Position */\r
+#define USIC_CH_PSCR_CST6_Msk (0x01UL << USIC_CH_PSCR_CST6_Pos) /*!< USIC_CH PSCR: CST6 Mask */\r
+#define USIC_CH_PSCR_CST7_Pos 7 /*!< USIC_CH PSCR: CST7 Position */\r
+#define USIC_CH_PSCR_CST7_Msk (0x01UL << USIC_CH_PSCR_CST7_Pos) /*!< USIC_CH PSCR: CST7 Mask */\r
+#define USIC_CH_PSCR_CST8_Pos 8 /*!< USIC_CH PSCR: CST8 Position */\r
+#define USIC_CH_PSCR_CST8_Msk (0x01UL << USIC_CH_PSCR_CST8_Pos) /*!< USIC_CH PSCR: CST8 Mask */\r
+#define USIC_CH_PSCR_CST9_Pos 9 /*!< USIC_CH PSCR: CST9 Position */\r
+#define USIC_CH_PSCR_CST9_Msk (0x01UL << USIC_CH_PSCR_CST9_Pos) /*!< USIC_CH PSCR: CST9 Mask */\r
+#define USIC_CH_PSCR_CRSIF_Pos 10 /*!< USIC_CH PSCR: CRSIF Position */\r
+#define USIC_CH_PSCR_CRSIF_Msk (0x01UL << USIC_CH_PSCR_CRSIF_Pos) /*!< USIC_CH PSCR: CRSIF Mask */\r
+#define USIC_CH_PSCR_CDLIF_Pos 11 /*!< USIC_CH PSCR: CDLIF Position */\r
+#define USIC_CH_PSCR_CDLIF_Msk (0x01UL << USIC_CH_PSCR_CDLIF_Pos) /*!< USIC_CH PSCR: CDLIF Mask */\r
+#define USIC_CH_PSCR_CTSIF_Pos 12 /*!< USIC_CH PSCR: CTSIF Position */\r
+#define USIC_CH_PSCR_CTSIF_Msk (0x01UL << USIC_CH_PSCR_CTSIF_Pos) /*!< USIC_CH PSCR: CTSIF Mask */\r
+#define USIC_CH_PSCR_CTBIF_Pos 13 /*!< USIC_CH PSCR: CTBIF Position */\r
+#define USIC_CH_PSCR_CTBIF_Msk (0x01UL << USIC_CH_PSCR_CTBIF_Pos) /*!< USIC_CH PSCR: CTBIF Mask */\r
+#define USIC_CH_PSCR_CRIF_Pos 14 /*!< USIC_CH PSCR: CRIF Position */\r
+#define USIC_CH_PSCR_CRIF_Msk (0x01UL << USIC_CH_PSCR_CRIF_Pos) /*!< USIC_CH PSCR: CRIF Mask */\r
+#define USIC_CH_PSCR_CAIF_Pos 15 /*!< USIC_CH PSCR: CAIF Position */\r
+#define USIC_CH_PSCR_CAIF_Msk (0x01UL << USIC_CH_PSCR_CAIF_Pos) /*!< USIC_CH PSCR: CAIF Mask */\r
+#define USIC_CH_PSCR_CBRGIF_Pos 16 /*!< USIC_CH PSCR: CBRGIF Position */\r
+#define USIC_CH_PSCR_CBRGIF_Msk (0x01UL << USIC_CH_PSCR_CBRGIF_Pos) /*!< USIC_CH PSCR: CBRGIF Mask */\r
+\r
+/* ------------------------------- USIC_CH_RBUFSR ------------------------------- */\r
+#define USIC_CH_RBUFSR_WLEN_Pos 0 /*!< USIC_CH RBUFSR: WLEN Position */\r
+#define USIC_CH_RBUFSR_WLEN_Msk (0x0fUL << USIC_CH_RBUFSR_WLEN_Pos) /*!< USIC_CH RBUFSR: WLEN Mask */\r
+#define USIC_CH_RBUFSR_SOF_Pos 6 /*!< USIC_CH RBUFSR: SOF Position */\r
+#define USIC_CH_RBUFSR_SOF_Msk (0x01UL << USIC_CH_RBUFSR_SOF_Pos) /*!< USIC_CH RBUFSR: SOF Mask */\r
+#define USIC_CH_RBUFSR_PAR_Pos 8 /*!< USIC_CH RBUFSR: PAR Position */\r
+#define USIC_CH_RBUFSR_PAR_Msk (0x01UL << USIC_CH_RBUFSR_PAR_Pos) /*!< USIC_CH RBUFSR: PAR Mask */\r
+#define USIC_CH_RBUFSR_PERR_Pos 9 /*!< USIC_CH RBUFSR: PERR Position */\r
+#define USIC_CH_RBUFSR_PERR_Msk (0x01UL << USIC_CH_RBUFSR_PERR_Pos) /*!< USIC_CH RBUFSR: PERR Mask */\r
+#define USIC_CH_RBUFSR_RDV0_Pos 13 /*!< USIC_CH RBUFSR: RDV0 Position */\r
+#define USIC_CH_RBUFSR_RDV0_Msk (0x01UL << USIC_CH_RBUFSR_RDV0_Pos) /*!< USIC_CH RBUFSR: RDV0 Mask */\r
+#define USIC_CH_RBUFSR_RDV1_Pos 14 /*!< USIC_CH RBUFSR: RDV1 Position */\r
+#define USIC_CH_RBUFSR_RDV1_Msk (0x01UL << USIC_CH_RBUFSR_RDV1_Pos) /*!< USIC_CH RBUFSR: RDV1 Mask */\r
+#define USIC_CH_RBUFSR_DS_Pos 15 /*!< USIC_CH RBUFSR: DS Position */\r
+#define USIC_CH_RBUFSR_DS_Msk (0x01UL << USIC_CH_RBUFSR_DS_Pos) /*!< USIC_CH RBUFSR: DS Mask */\r
+\r
+/* -------------------------------- USIC_CH_RBUF -------------------------------- */\r
+#define USIC_CH_RBUF_DSR_Pos 0 /*!< USIC_CH RBUF: DSR Position */\r
+#define USIC_CH_RBUF_DSR_Msk (0x0000ffffUL << USIC_CH_RBUF_DSR_Pos) /*!< USIC_CH RBUF: DSR Mask */\r
+\r
+/* -------------------------------- USIC_CH_RBUFD ------------------------------- */\r
+#define USIC_CH_RBUFD_DSR_Pos 0 /*!< USIC_CH RBUFD: DSR Position */\r
+#define USIC_CH_RBUFD_DSR_Msk (0x0000ffffUL << USIC_CH_RBUFD_DSR_Pos) /*!< USIC_CH RBUFD: DSR Mask */\r
+\r
+/* -------------------------------- USIC_CH_RBUF0 ------------------------------- */\r
+#define USIC_CH_RBUF0_DSR0_Pos 0 /*!< USIC_CH RBUF0: DSR0 Position */\r
+#define USIC_CH_RBUF0_DSR0_Msk (0x0000ffffUL << USIC_CH_RBUF0_DSR0_Pos) /*!< USIC_CH RBUF0: DSR0 Mask */\r
+\r
+/* -------------------------------- USIC_CH_RBUF1 ------------------------------- */\r
+#define USIC_CH_RBUF1_DSR1_Pos 0 /*!< USIC_CH RBUF1: DSR1 Position */\r
+#define USIC_CH_RBUF1_DSR1_Msk (0x0000ffffUL << USIC_CH_RBUF1_DSR1_Pos) /*!< USIC_CH RBUF1: DSR1 Mask */\r
+\r
+/* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */\r
+#define USIC_CH_RBUF01SR_WLEN0_Pos 0 /*!< USIC_CH RBUF01SR: WLEN0 Position */\r
+#define USIC_CH_RBUF01SR_WLEN0_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN0_Pos) /*!< USIC_CH RBUF01SR: WLEN0 Mask */\r
+#define USIC_CH_RBUF01SR_SOF0_Pos 6 /*!< USIC_CH RBUF01SR: SOF0 Position */\r
+#define USIC_CH_RBUF01SR_SOF0_Msk (0x01UL << USIC_CH_RBUF01SR_SOF0_Pos) /*!< USIC_CH RBUF01SR: SOF0 Mask */\r
+#define USIC_CH_RBUF01SR_PAR0_Pos 8 /*!< USIC_CH RBUF01SR: PAR0 Position */\r
+#define USIC_CH_RBUF01SR_PAR0_Msk (0x01UL << USIC_CH_RBUF01SR_PAR0_Pos) /*!< USIC_CH RBUF01SR: PAR0 Mask */\r
+#define USIC_CH_RBUF01SR_PERR0_Pos 9 /*!< USIC_CH RBUF01SR: PERR0 Position */\r
+#define USIC_CH_RBUF01SR_PERR0_Msk (0x01UL << USIC_CH_RBUF01SR_PERR0_Pos) /*!< USIC_CH RBUF01SR: PERR0 Mask */\r
+#define USIC_CH_RBUF01SR_RDV00_Pos 13 /*!< USIC_CH RBUF01SR: RDV00 Position */\r
+#define USIC_CH_RBUF01SR_RDV00_Msk (0x01UL << USIC_CH_RBUF01SR_RDV00_Pos) /*!< USIC_CH RBUF01SR: RDV00 Mask */\r
+#define USIC_CH_RBUF01SR_RDV01_Pos 14 /*!< USIC_CH RBUF01SR: RDV01 Position */\r
+#define USIC_CH_RBUF01SR_RDV01_Msk (0x01UL << USIC_CH_RBUF01SR_RDV01_Pos) /*!< USIC_CH RBUF01SR: RDV01 Mask */\r
+#define USIC_CH_RBUF01SR_DS0_Pos 15 /*!< USIC_CH RBUF01SR: DS0 Position */\r
+#define USIC_CH_RBUF01SR_DS0_Msk (0x01UL << USIC_CH_RBUF01SR_DS0_Pos) /*!< USIC_CH RBUF01SR: DS0 Mask */\r
+#define USIC_CH_RBUF01SR_WLEN1_Pos 16 /*!< USIC_CH RBUF01SR: WLEN1 Position */\r
+#define USIC_CH_RBUF01SR_WLEN1_Msk (0x0fUL << USIC_CH_RBUF01SR_WLEN1_Pos) /*!< USIC_CH RBUF01SR: WLEN1 Mask */\r
+#define USIC_CH_RBUF01SR_SOF1_Pos 22 /*!< USIC_CH RBUF01SR: SOF1 Position */\r
+#define USIC_CH_RBUF01SR_SOF1_Msk (0x01UL << USIC_CH_RBUF01SR_SOF1_Pos) /*!< USIC_CH RBUF01SR: SOF1 Mask */\r
+#define USIC_CH_RBUF01SR_PAR1_Pos 24 /*!< USIC_CH RBUF01SR: PAR1 Position */\r
+#define USIC_CH_RBUF01SR_PAR1_Msk (0x01UL << USIC_CH_RBUF01SR_PAR1_Pos) /*!< USIC_CH RBUF01SR: PAR1 Mask */\r
+#define USIC_CH_RBUF01SR_PERR1_Pos 25 /*!< USIC_CH RBUF01SR: PERR1 Position */\r
+#define USIC_CH_RBUF01SR_PERR1_Msk (0x01UL << USIC_CH_RBUF01SR_PERR1_Pos) /*!< USIC_CH RBUF01SR: PERR1 Mask */\r
+#define USIC_CH_RBUF01SR_RDV10_Pos 29 /*!< USIC_CH RBUF01SR: RDV10 Position */\r
+#define USIC_CH_RBUF01SR_RDV10_Msk (0x01UL << USIC_CH_RBUF01SR_RDV10_Pos) /*!< USIC_CH RBUF01SR: RDV10 Mask */\r
+#define USIC_CH_RBUF01SR_RDV11_Pos 30 /*!< USIC_CH RBUF01SR: RDV11 Position */\r
+#define USIC_CH_RBUF01SR_RDV11_Msk (0x01UL << USIC_CH_RBUF01SR_RDV11_Pos) /*!< USIC_CH RBUF01SR: RDV11 Mask */\r
+#define USIC_CH_RBUF01SR_DS1_Pos 31 /*!< USIC_CH RBUF01SR: DS1 Position */\r
+#define USIC_CH_RBUF01SR_DS1_Msk (0x01UL << USIC_CH_RBUF01SR_DS1_Pos) /*!< USIC_CH RBUF01SR: DS1 Mask */\r
+\r
+/* --------------------------------- USIC_CH_FMR -------------------------------- */\r
+#define USIC_CH_FMR_MTDV_Pos 0 /*!< USIC_CH FMR: MTDV Position */\r
+#define USIC_CH_FMR_MTDV_Msk (0x03UL << USIC_CH_FMR_MTDV_Pos) /*!< USIC_CH FMR: MTDV Mask */\r
+#define USIC_CH_FMR_ATVC_Pos 4 /*!< USIC_CH FMR: ATVC Position */\r
+#define USIC_CH_FMR_ATVC_Msk (0x01UL << USIC_CH_FMR_ATVC_Pos) /*!< USIC_CH FMR: ATVC Mask */\r
+#define USIC_CH_FMR_CRDV0_Pos 14 /*!< USIC_CH FMR: CRDV0 Position */\r
+#define USIC_CH_FMR_CRDV0_Msk (0x01UL << USIC_CH_FMR_CRDV0_Pos) /*!< USIC_CH FMR: CRDV0 Mask */\r
+#define USIC_CH_FMR_CRDV1_Pos 15 /*!< USIC_CH FMR: CRDV1 Position */\r
+#define USIC_CH_FMR_CRDV1_Msk (0x01UL << USIC_CH_FMR_CRDV1_Pos) /*!< USIC_CH FMR: CRDV1 Mask */\r
+#define USIC_CH_FMR_SIO0_Pos 16 /*!< USIC_CH FMR: SIO0 Position */\r
+#define USIC_CH_FMR_SIO0_Msk (0x01UL << USIC_CH_FMR_SIO0_Pos) /*!< USIC_CH FMR: SIO0 Mask */\r
+#define USIC_CH_FMR_SIO1_Pos 17 /*!< USIC_CH FMR: SIO1 Position */\r
+#define USIC_CH_FMR_SIO1_Msk (0x01UL << USIC_CH_FMR_SIO1_Pos) /*!< USIC_CH FMR: SIO1 Mask */\r
+#define USIC_CH_FMR_SIO2_Pos 18 /*!< USIC_CH FMR: SIO2 Position */\r
+#define USIC_CH_FMR_SIO2_Msk (0x01UL << USIC_CH_FMR_SIO2_Pos) /*!< USIC_CH FMR: SIO2 Mask */\r
+#define USIC_CH_FMR_SIO3_Pos 19 /*!< USIC_CH FMR: SIO3 Position */\r
+#define USIC_CH_FMR_SIO3_Msk (0x01UL << USIC_CH_FMR_SIO3_Pos) /*!< USIC_CH FMR: SIO3 Mask */\r
+#define USIC_CH_FMR_SIO4_Pos 20 /*!< USIC_CH FMR: SIO4 Position */\r
+#define USIC_CH_FMR_SIO4_Msk (0x01UL << USIC_CH_FMR_SIO4_Pos) /*!< USIC_CH FMR: SIO4 Mask */\r
+#define USIC_CH_FMR_SIO5_Pos 21 /*!< USIC_CH FMR: SIO5 Position */\r
+#define USIC_CH_FMR_SIO5_Msk (0x01UL << USIC_CH_FMR_SIO5_Pos) /*!< USIC_CH FMR: SIO5 Mask */\r
+\r
+/* -------------------------------- USIC_CH_TBUF -------------------------------- */\r
+#define USIC_CH_TBUF_TDATA_Pos 0 /*!< USIC_CH TBUF: TDATA Position */\r
+#define USIC_CH_TBUF_TDATA_Msk (0x0000ffffUL << USIC_CH_TBUF_TDATA_Pos) /*!< USIC_CH TBUF: TDATA Mask */\r
+\r
+/* --------------------------------- USIC_CH_BYP -------------------------------- */\r
+#define USIC_CH_BYP_BDATA_Pos 0 /*!< USIC_CH BYP: BDATA Position */\r
+#define USIC_CH_BYP_BDATA_Msk (0x0000ffffUL << USIC_CH_BYP_BDATA_Pos) /*!< USIC_CH BYP: BDATA Mask */\r
+\r
+/* -------------------------------- USIC_CH_BYPCR ------------------------------- */\r
+#define USIC_CH_BYPCR_BWLE_Pos 0 /*!< USIC_CH BYPCR: BWLE Position */\r
+#define USIC_CH_BYPCR_BWLE_Msk (0x0fUL << USIC_CH_BYPCR_BWLE_Pos) /*!< USIC_CH BYPCR: BWLE Mask */\r
+#define USIC_CH_BYPCR_BDSSM_Pos 8 /*!< USIC_CH BYPCR: BDSSM Position */\r
+#define USIC_CH_BYPCR_BDSSM_Msk (0x01UL << USIC_CH_BYPCR_BDSSM_Pos) /*!< USIC_CH BYPCR: BDSSM Mask */\r
+#define USIC_CH_BYPCR_BDEN_Pos 10 /*!< USIC_CH BYPCR: BDEN Position */\r
+#define USIC_CH_BYPCR_BDEN_Msk (0x03UL << USIC_CH_BYPCR_BDEN_Pos) /*!< USIC_CH BYPCR: BDEN Mask */\r
+#define USIC_CH_BYPCR_BDVTR_Pos 12 /*!< USIC_CH BYPCR: BDVTR Position */\r
+#define USIC_CH_BYPCR_BDVTR_Msk (0x01UL << USIC_CH_BYPCR_BDVTR_Pos) /*!< USIC_CH BYPCR: BDVTR Mask */\r
+#define USIC_CH_BYPCR_BPRIO_Pos 13 /*!< USIC_CH BYPCR: BPRIO Position */\r
+#define USIC_CH_BYPCR_BPRIO_Msk (0x01UL << USIC_CH_BYPCR_BPRIO_Pos) /*!< USIC_CH BYPCR: BPRIO Mask */\r
+#define USIC_CH_BYPCR_BDV_Pos 15 /*!< USIC_CH BYPCR: BDV Position */\r
+#define USIC_CH_BYPCR_BDV_Msk (0x01UL << USIC_CH_BYPCR_BDV_Pos) /*!< USIC_CH BYPCR: BDV Mask */\r
+#define USIC_CH_BYPCR_BSELO_Pos 16 /*!< USIC_CH BYPCR: BSELO Position */\r
+#define USIC_CH_BYPCR_BSELO_Msk (0x1fUL << USIC_CH_BYPCR_BSELO_Pos) /*!< USIC_CH BYPCR: BSELO Mask */\r
+#define USIC_CH_BYPCR_BHPC_Pos 21 /*!< USIC_CH BYPCR: BHPC Position */\r
+#define USIC_CH_BYPCR_BHPC_Msk (0x07UL << USIC_CH_BYPCR_BHPC_Pos) /*!< USIC_CH BYPCR: BHPC Mask */\r
+\r
+/* -------------------------------- USIC_CH_TBCTR ------------------------------- */\r
+#define USIC_CH_TBCTR_DPTR_Pos 0 /*!< USIC_CH TBCTR: DPTR Position */\r
+#define USIC_CH_TBCTR_DPTR_Msk (0x3fUL << USIC_CH_TBCTR_DPTR_Pos) /*!< USIC_CH TBCTR: DPTR Mask */\r
+#define USIC_CH_TBCTR_LIMIT_Pos 8 /*!< USIC_CH TBCTR: LIMIT Position */\r
+#define USIC_CH_TBCTR_LIMIT_Msk (0x3fUL << USIC_CH_TBCTR_LIMIT_Pos) /*!< USIC_CH TBCTR: LIMIT Mask */\r
+#define USIC_CH_TBCTR_STBTM_Pos 14 /*!< USIC_CH TBCTR: STBTM Position */\r
+#define USIC_CH_TBCTR_STBTM_Msk (0x01UL << USIC_CH_TBCTR_STBTM_Pos) /*!< USIC_CH TBCTR: STBTM Mask */\r
+#define USIC_CH_TBCTR_STBTEN_Pos 15 /*!< USIC_CH TBCTR: STBTEN Position */\r
+#define USIC_CH_TBCTR_STBTEN_Msk (0x01UL << USIC_CH_TBCTR_STBTEN_Pos) /*!< USIC_CH TBCTR: STBTEN Mask */\r
+#define USIC_CH_TBCTR_STBINP_Pos 16 /*!< USIC_CH TBCTR: STBINP Position */\r
+#define USIC_CH_TBCTR_STBINP_Msk (0x07UL << USIC_CH_TBCTR_STBINP_Pos) /*!< USIC_CH TBCTR: STBINP Mask */\r
+#define USIC_CH_TBCTR_ATBINP_Pos 19 /*!< USIC_CH TBCTR: ATBINP Position */\r
+#define USIC_CH_TBCTR_ATBINP_Msk (0x07UL << USIC_CH_TBCTR_ATBINP_Pos) /*!< USIC_CH TBCTR: ATBINP Mask */\r
+#define USIC_CH_TBCTR_SIZE_Pos 24 /*!< USIC_CH TBCTR: SIZE Position */\r
+#define USIC_CH_TBCTR_SIZE_Msk (0x07UL << USIC_CH_TBCTR_SIZE_Pos) /*!< USIC_CH TBCTR: SIZE Mask */\r
+#define USIC_CH_TBCTR_LOF_Pos 28 /*!< USIC_CH TBCTR: LOF Position */\r
+#define USIC_CH_TBCTR_LOF_Msk (0x01UL << USIC_CH_TBCTR_LOF_Pos) /*!< USIC_CH TBCTR: LOF Mask */\r
+#define USIC_CH_TBCTR_STBIEN_Pos 30 /*!< USIC_CH TBCTR: STBIEN Position */\r
+#define USIC_CH_TBCTR_STBIEN_Msk (0x01UL << USIC_CH_TBCTR_STBIEN_Pos) /*!< USIC_CH TBCTR: STBIEN Mask */\r
+#define USIC_CH_TBCTR_TBERIEN_Pos 31 /*!< USIC_CH TBCTR: TBERIEN Position */\r
+#define USIC_CH_TBCTR_TBERIEN_Msk (0x01UL << USIC_CH_TBCTR_TBERIEN_Pos) /*!< USIC_CH TBCTR: TBERIEN Mask */\r
+\r
+/* -------------------------------- USIC_CH_RBCTR ------------------------------- */\r
+#define USIC_CH_RBCTR_DPTR_Pos 0 /*!< USIC_CH RBCTR: DPTR Position */\r
+#define USIC_CH_RBCTR_DPTR_Msk (0x3fUL << USIC_CH_RBCTR_DPTR_Pos) /*!< USIC_CH RBCTR: DPTR Mask */\r
+#define USIC_CH_RBCTR_LIMIT_Pos 8 /*!< USIC_CH RBCTR: LIMIT Position */\r
+#define USIC_CH_RBCTR_LIMIT_Msk (0x3fUL << USIC_CH_RBCTR_LIMIT_Pos) /*!< USIC_CH RBCTR: LIMIT Mask */\r
+#define USIC_CH_RBCTR_SRBTM_Pos 14 /*!< USIC_CH RBCTR: SRBTM Position */\r
+#define USIC_CH_RBCTR_SRBTM_Msk (0x01UL << USIC_CH_RBCTR_SRBTM_Pos) /*!< USIC_CH RBCTR: SRBTM Mask */\r
+#define USIC_CH_RBCTR_SRBTEN_Pos 15 /*!< USIC_CH RBCTR: SRBTEN Position */\r
+#define USIC_CH_RBCTR_SRBTEN_Msk (0x01UL << USIC_CH_RBCTR_SRBTEN_Pos) /*!< USIC_CH RBCTR: SRBTEN Mask */\r
+#define USIC_CH_RBCTR_SRBINP_Pos 16 /*!< USIC_CH RBCTR: SRBINP Position */\r
+#define USIC_CH_RBCTR_SRBINP_Msk (0x07UL << USIC_CH_RBCTR_SRBINP_Pos) /*!< USIC_CH RBCTR: SRBINP Mask */\r
+#define USIC_CH_RBCTR_ARBINP_Pos 19 /*!< USIC_CH RBCTR: ARBINP Position */\r
+#define USIC_CH_RBCTR_ARBINP_Msk (0x07UL << USIC_CH_RBCTR_ARBINP_Pos) /*!< USIC_CH RBCTR: ARBINP Mask */\r
+#define USIC_CH_RBCTR_RCIM_Pos 22 /*!< USIC_CH RBCTR: RCIM Position */\r
+#define USIC_CH_RBCTR_RCIM_Msk (0x03UL << USIC_CH_RBCTR_RCIM_Pos) /*!< USIC_CH RBCTR: RCIM Mask */\r
+#define USIC_CH_RBCTR_SIZE_Pos 24 /*!< USIC_CH RBCTR: SIZE Position */\r
+#define USIC_CH_RBCTR_SIZE_Msk (0x07UL << USIC_CH_RBCTR_SIZE_Pos) /*!< USIC_CH RBCTR: SIZE Mask */\r
+#define USIC_CH_RBCTR_RNM_Pos 27 /*!< USIC_CH RBCTR: RNM Position */\r
+#define USIC_CH_RBCTR_RNM_Msk (0x01UL << USIC_CH_RBCTR_RNM_Pos) /*!< USIC_CH RBCTR: RNM Mask */\r
+#define USIC_CH_RBCTR_LOF_Pos 28 /*!< USIC_CH RBCTR: LOF Position */\r
+#define USIC_CH_RBCTR_LOF_Msk (0x01UL << USIC_CH_RBCTR_LOF_Pos) /*!< USIC_CH RBCTR: LOF Mask */\r
+#define USIC_CH_RBCTR_ARBIEN_Pos 29 /*!< USIC_CH RBCTR: ARBIEN Position */\r
+#define USIC_CH_RBCTR_ARBIEN_Msk (0x01UL << USIC_CH_RBCTR_ARBIEN_Pos) /*!< USIC_CH RBCTR: ARBIEN Mask */\r
+#define USIC_CH_RBCTR_SRBIEN_Pos 30 /*!< USIC_CH RBCTR: SRBIEN Position */\r
+#define USIC_CH_RBCTR_SRBIEN_Msk (0x01UL << USIC_CH_RBCTR_SRBIEN_Pos) /*!< USIC_CH RBCTR: SRBIEN Mask */\r
+#define USIC_CH_RBCTR_RBERIEN_Pos 31 /*!< USIC_CH RBCTR: RBERIEN Position */\r
+#define USIC_CH_RBCTR_RBERIEN_Msk (0x01UL << USIC_CH_RBCTR_RBERIEN_Pos) /*!< USIC_CH RBCTR: RBERIEN Mask */\r
+\r
+/* ------------------------------- USIC_CH_TRBPTR ------------------------------- */\r
+#define USIC_CH_TRBPTR_TDIPTR_Pos 0 /*!< USIC_CH TRBPTR: TDIPTR Position */\r
+#define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDIPTR_Pos) /*!< USIC_CH TRBPTR: TDIPTR Mask */\r
+#define USIC_CH_TRBPTR_TDOPTR_Pos 8 /*!< USIC_CH TRBPTR: TDOPTR Position */\r
+#define USIC_CH_TRBPTR_TDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_TDOPTR_Pos) /*!< USIC_CH TRBPTR: TDOPTR Mask */\r
+#define USIC_CH_TRBPTR_RDIPTR_Pos 16 /*!< USIC_CH TRBPTR: RDIPTR Position */\r
+#define USIC_CH_TRBPTR_RDIPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDIPTR_Pos) /*!< USIC_CH TRBPTR: RDIPTR Mask */\r
+#define USIC_CH_TRBPTR_RDOPTR_Pos 24 /*!< USIC_CH TRBPTR: RDOPTR Position */\r
+#define USIC_CH_TRBPTR_RDOPTR_Msk (0x3fUL << USIC_CH_TRBPTR_RDOPTR_Pos) /*!< USIC_CH TRBPTR: RDOPTR Mask */\r
+\r
+/* -------------------------------- USIC_CH_TRBSR ------------------------------- */\r
+#define USIC_CH_TRBSR_SRBI_Pos 0 /*!< USIC_CH TRBSR: SRBI Position */\r
+#define USIC_CH_TRBSR_SRBI_Msk (0x01UL << USIC_CH_TRBSR_SRBI_Pos) /*!< USIC_CH TRBSR: SRBI Mask */\r
+#define USIC_CH_TRBSR_RBERI_Pos 1 /*!< USIC_CH TRBSR: RBERI Position */\r
+#define USIC_CH_TRBSR_RBERI_Msk (0x01UL << USIC_CH_TRBSR_RBERI_Pos) /*!< USIC_CH TRBSR: RBERI Mask */\r
+#define USIC_CH_TRBSR_ARBI_Pos 2 /*!< USIC_CH TRBSR: ARBI Position */\r
+#define USIC_CH_TRBSR_ARBI_Msk (0x01UL << USIC_CH_TRBSR_ARBI_Pos) /*!< USIC_CH TRBSR: ARBI Mask */\r
+#define USIC_CH_TRBSR_REMPTY_Pos 3 /*!< USIC_CH TRBSR: REMPTY Position */\r
+#define USIC_CH_TRBSR_REMPTY_Msk (0x01UL << USIC_CH_TRBSR_REMPTY_Pos) /*!< USIC_CH TRBSR: REMPTY Mask */\r
+#define USIC_CH_TRBSR_RFULL_Pos 4 /*!< USIC_CH TRBSR: RFULL Position */\r
+#define USIC_CH_TRBSR_RFULL_Msk (0x01UL << USIC_CH_TRBSR_RFULL_Pos) /*!< USIC_CH TRBSR: RFULL Mask */\r
+#define USIC_CH_TRBSR_RBUS_Pos 5 /*!< USIC_CH TRBSR: RBUS Position */\r
+#define USIC_CH_TRBSR_RBUS_Msk (0x01UL << USIC_CH_TRBSR_RBUS_Pos) /*!< USIC_CH TRBSR: RBUS Mask */\r
+#define USIC_CH_TRBSR_SRBT_Pos 6 /*!< USIC_CH TRBSR: SRBT Position */\r
+#define USIC_CH_TRBSR_SRBT_Msk (0x01UL << USIC_CH_TRBSR_SRBT_Pos) /*!< USIC_CH TRBSR: SRBT Mask */\r
+#define USIC_CH_TRBSR_STBI_Pos 8 /*!< USIC_CH TRBSR: STBI Position */\r
+#define USIC_CH_TRBSR_STBI_Msk (0x01UL << USIC_CH_TRBSR_STBI_Pos) /*!< USIC_CH TRBSR: STBI Mask */\r
+#define USIC_CH_TRBSR_TBERI_Pos 9 /*!< USIC_CH TRBSR: TBERI Position */\r
+#define USIC_CH_TRBSR_TBERI_Msk (0x01UL << USIC_CH_TRBSR_TBERI_Pos) /*!< USIC_CH TRBSR: TBERI Mask */\r
+#define USIC_CH_TRBSR_TEMPTY_Pos 11 /*!< USIC_CH TRBSR: TEMPTY Position */\r
+#define USIC_CH_TRBSR_TEMPTY_Msk (0x01UL << USIC_CH_TRBSR_TEMPTY_Pos) /*!< USIC_CH TRBSR: TEMPTY Mask */\r
+#define USIC_CH_TRBSR_TFULL_Pos 12 /*!< USIC_CH TRBSR: TFULL Position */\r
+#define USIC_CH_TRBSR_TFULL_Msk (0x01UL << USIC_CH_TRBSR_TFULL_Pos) /*!< USIC_CH TRBSR: TFULL Mask */\r
+#define USIC_CH_TRBSR_TBUS_Pos 13 /*!< USIC_CH TRBSR: TBUS Position */\r
+#define USIC_CH_TRBSR_TBUS_Msk (0x01UL << USIC_CH_TRBSR_TBUS_Pos) /*!< USIC_CH TRBSR: TBUS Mask */\r
+#define USIC_CH_TRBSR_STBT_Pos 14 /*!< USIC_CH TRBSR: STBT Position */\r
+#define USIC_CH_TRBSR_STBT_Msk (0x01UL << USIC_CH_TRBSR_STBT_Pos) /*!< USIC_CH TRBSR: STBT Mask */\r
+#define USIC_CH_TRBSR_RBFLVL_Pos 16 /*!< USIC_CH TRBSR: RBFLVL Position */\r
+#define USIC_CH_TRBSR_RBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_RBFLVL_Pos) /*!< USIC_CH TRBSR: RBFLVL Mask */\r
+#define USIC_CH_TRBSR_TBFLVL_Pos 24 /*!< USIC_CH TRBSR: TBFLVL Position */\r
+#define USIC_CH_TRBSR_TBFLVL_Msk (0x7fUL << USIC_CH_TRBSR_TBFLVL_Pos) /*!< USIC_CH TRBSR: TBFLVL Mask */\r
+\r
+/* ------------------------------- USIC_CH_TRBSCR ------------------------------- */\r
+#define USIC_CH_TRBSCR_CSRBI_Pos 0 /*!< USIC_CH TRBSCR: CSRBI Position */\r
+#define USIC_CH_TRBSCR_CSRBI_Msk (0x01UL << USIC_CH_TRBSCR_CSRBI_Pos) /*!< USIC_CH TRBSCR: CSRBI Mask */\r
+#define USIC_CH_TRBSCR_CRBERI_Pos 1 /*!< USIC_CH TRBSCR: CRBERI Position */\r
+#define USIC_CH_TRBSCR_CRBERI_Msk (0x01UL << USIC_CH_TRBSCR_CRBERI_Pos) /*!< USIC_CH TRBSCR: CRBERI Mask */\r
+#define USIC_CH_TRBSCR_CARBI_Pos 2 /*!< USIC_CH TRBSCR: CARBI Position */\r
+#define USIC_CH_TRBSCR_CARBI_Msk (0x01UL << USIC_CH_TRBSCR_CARBI_Pos) /*!< USIC_CH TRBSCR: CARBI Mask */\r
+#define USIC_CH_TRBSCR_CSTBI_Pos 8 /*!< USIC_CH TRBSCR: CSTBI Position */\r
+#define USIC_CH_TRBSCR_CSTBI_Msk (0x01UL << USIC_CH_TRBSCR_CSTBI_Pos) /*!< USIC_CH TRBSCR: CSTBI Mask */\r
+#define USIC_CH_TRBSCR_CTBERI_Pos 9 /*!< USIC_CH TRBSCR: CTBERI Position */\r
+#define USIC_CH_TRBSCR_CTBERI_Msk (0x01UL << USIC_CH_TRBSCR_CTBERI_Pos) /*!< USIC_CH TRBSCR: CTBERI Mask */\r
+#define USIC_CH_TRBSCR_CBDV_Pos 10 /*!< USIC_CH TRBSCR: CBDV Position */\r
+#define USIC_CH_TRBSCR_CBDV_Msk (0x01UL << USIC_CH_TRBSCR_CBDV_Pos) /*!< USIC_CH TRBSCR: CBDV Mask */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Pos 14 /*!< USIC_CH TRBSCR: FLUSHRB Position */\r
+#define USIC_CH_TRBSCR_FLUSHRB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHRB_Pos) /*!< USIC_CH TRBSCR: FLUSHRB Mask */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Pos 15 /*!< USIC_CH TRBSCR: FLUSHTB Position */\r
+#define USIC_CH_TRBSCR_FLUSHTB_Msk (0x01UL << USIC_CH_TRBSCR_FLUSHTB_Pos) /*!< USIC_CH TRBSCR: FLUSHTB Mask */\r
+\r
+/* -------------------------------- USIC_CH_OUTR -------------------------------- */\r
+#define USIC_CH_OUTR_DSR_Pos 0 /*!< USIC_CH OUTR: DSR Position */\r
+#define USIC_CH_OUTR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTR_DSR_Pos) /*!< USIC_CH OUTR: DSR Mask */\r
+#define USIC_CH_OUTR_RCI_Pos 16 /*!< USIC_CH OUTR: RCI Position */\r
+#define USIC_CH_OUTR_RCI_Msk (0x1fUL << USIC_CH_OUTR_RCI_Pos) /*!< USIC_CH OUTR: RCI Mask */\r
+\r
+/* -------------------------------- USIC_CH_OUTDR ------------------------------- */\r
+#define USIC_CH_OUTDR_DSR_Pos 0 /*!< USIC_CH OUTDR: DSR Position */\r
+#define USIC_CH_OUTDR_DSR_Msk (0x0000ffffUL << USIC_CH_OUTDR_DSR_Pos) /*!< USIC_CH OUTDR: DSR Mask */\r
+#define USIC_CH_OUTDR_RCI_Pos 16 /*!< USIC_CH OUTDR: RCI Position */\r
+#define USIC_CH_OUTDR_RCI_Msk (0x1fUL << USIC_CH_OUTDR_RCI_Pos) /*!< USIC_CH OUTDR: RCI Mask */\r
+\r
+/* --------------------------------- USIC_CH_IN --------------------------------- */\r
+#define USIC_CH_IN_TDATA_Pos 0 /*!< USIC_CH IN: TDATA Position */\r
+#define USIC_CH_IN_TDATA_Msk (0x0000ffffUL << USIC_CH_IN_TDATA_Pos) /*!< USIC_CH IN: TDATA Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SCU_GENERAL' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------- SCU_GENERAL_DBGROMID ---------------------------- */\r
+#define SCU_GENERAL_DBGROMID_MANUFID_Pos 1 /*!< SCU_GENERAL DBGROMID: MANUFID Position */\r
+#define SCU_GENERAL_DBGROMID_MANUFID_Msk (0x000007ffUL << SCU_GENERAL_DBGROMID_MANUFID_Pos) /*!< SCU_GENERAL DBGROMID: MANUFID Mask */\r
+#define SCU_GENERAL_DBGROMID_PARTNO_Pos 12 /*!< SCU_GENERAL DBGROMID: PARTNO Position */\r
+#define SCU_GENERAL_DBGROMID_PARTNO_Msk (0x0000ffffUL << SCU_GENERAL_DBGROMID_PARTNO_Pos) /*!< SCU_GENERAL DBGROMID: PARTNO Mask */\r
+#define SCU_GENERAL_DBGROMID_VERSION_Pos 28 /*!< SCU_GENERAL DBGROMID: VERSION Position */\r
+#define SCU_GENERAL_DBGROMID_VERSION_Msk (0x0fUL << SCU_GENERAL_DBGROMID_VERSION_Pos) /*!< SCU_GENERAL DBGROMID: VERSION Mask */\r
+\r
+/* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Pos 0 /*!< SCU_GENERAL IDCHIP: IDCHIP Position */\r
+#define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL << SCU_GENERAL_IDCHIP_IDCHIP_Pos) /*!< SCU_GENERAL IDCHIP: IDCHIP Mask */\r
+\r
+/* ------------------------------- SCU_GENERAL_ID ------------------------------- */\r
+#define SCU_GENERAL_ID_MOD_REV_Pos 0 /*!< SCU_GENERAL ID: MOD_REV Position */\r
+#define SCU_GENERAL_ID_MOD_REV_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_REV_Pos) /*!< SCU_GENERAL ID: MOD_REV Mask */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Pos 8 /*!< SCU_GENERAL ID: MOD_TYPE Position */\r
+#define SCU_GENERAL_ID_MOD_TYPE_Msk (0x000000ffUL << SCU_GENERAL_ID_MOD_TYPE_Pos) /*!< SCU_GENERAL ID: MOD_TYPE Mask */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Pos 16 /*!< SCU_GENERAL ID: MOD_NUMBER Position */\r
+#define SCU_GENERAL_ID_MOD_NUMBER_Msk (0x0000ffffUL << SCU_GENERAL_ID_MOD_NUMBER_Pos) /*!< SCU_GENERAL ID: MOD_NUMBER Mask */\r
+\r
+/* ------------------------------ SCU_GENERAL_SSW0 ------------------------------ */\r
+#define SCU_GENERAL_SSW0_DAT_Pos 0 /*!< SCU_GENERAL SSW0: DAT Position */\r
+#define SCU_GENERAL_SSW0_DAT_Msk (0xffffffffUL << SCU_GENERAL_SSW0_DAT_Pos) /*!< SCU_GENERAL SSW0: DAT Mask */\r
+\r
+/* ----------------------------- SCU_GENERAL_PASSWD ----------------------------- */\r
+#define SCU_GENERAL_PASSWD_MODE_Pos 0 /*!< SCU_GENERAL PASSWD: MODE Position */\r
+#define SCU_GENERAL_PASSWD_MODE_Msk (0x03UL << SCU_GENERAL_PASSWD_MODE_Pos) /*!< SCU_GENERAL PASSWD: MODE Mask */\r
+#define SCU_GENERAL_PASSWD_PROTS_Pos 2 /*!< SCU_GENERAL PASSWD: PROTS Position */\r
+#define SCU_GENERAL_PASSWD_PROTS_Msk (0x01UL << SCU_GENERAL_PASSWD_PROTS_Pos) /*!< SCU_GENERAL PASSWD: PROTS Mask */\r
+#define SCU_GENERAL_PASSWD_PASS_Pos 3 /*!< SCU_GENERAL PASSWD: PASS Position */\r
+#define SCU_GENERAL_PASSWD_PASS_Msk (0x1fUL << SCU_GENERAL_PASSWD_PASS_Pos) /*!< SCU_GENERAL PASSWD: PASS Mask */\r
+\r
+/* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */\r
+#define SCU_GENERAL_CCUCON_GSC40_Pos 0 /*!< SCU_GENERAL CCUCON: GSC40 Position */\r
+#define SCU_GENERAL_CCUCON_GSC40_Msk (0x01UL << SCU_GENERAL_CCUCON_GSC40_Pos) /*!< SCU_GENERAL CCUCON: GSC40 Mask */\r
+\r
+/* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos 0 /*!< SCU_GENERAL MIRRSTS: RTC_CTR Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_CTR_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_CTR Mask */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos 1 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM0 Mask */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos 2 /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_ATIM1 Mask */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos 3 /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM0 Mask */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos 4 /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Position */\r
+#define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x01UL << SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos) /*!< SCU_GENERAL MIRRSTS: RTC_TIM1 Mask */\r
+\r
+/* ------------------------------ SCU_GENERAL_PMTSR ----------------------------- */\r
+#define SCU_GENERAL_PMTSR_MTENS_Pos 0 /*!< SCU_GENERAL PMTSR: MTENS Position */\r
+#define SCU_GENERAL_PMTSR_MTENS_Msk (0x01UL << SCU_GENERAL_PMTSR_MTENS_Pos) /*!< SCU_GENERAL PMTSR: MTENS Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRRAW: PRWARN Position */\r
+#define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PRWARN_Pos) /*!< SCU_INTERRUPT SRRAW: PRWARN Mask */\r
+#define SCU_INTERRUPT_SRRAW_PI_Pos 1 /*!< SCU_INTERRUPT SRRAW: PI Position */\r
+#define SCU_INTERRUPT_SRRAW_PI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PI_Pos) /*!< SCU_INTERRUPT SRRAW: PI Mask */\r
+#define SCU_INTERRUPT_SRRAW_AI_Pos 2 /*!< SCU_INTERRUPT SRRAW: AI Position */\r
+#define SCU_INTERRUPT_SRRAW_AI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_AI_Pos) /*!< SCU_INTERRUPT SRRAW: AI Mask */\r
+#define SCU_INTERRUPT_SRRAW_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRRAW: VDDPI Position */\r
+#define SCU_INTERRUPT_SRRAW_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDDPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDDPI Mask */\r
+#define SCU_INTERRUPT_SRRAW_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRRAW: ACMP0I Position */\r
+#define SCU_INTERRUPT_SRRAW_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP0I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP0I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRRAW: ACMP1I Position */\r
+#define SCU_INTERRUPT_SRRAW_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP1I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP1I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRRAW: ACMP2I Position */\r
+#define SCU_INTERRUPT_SRRAW_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ACMP2I_Pos) /*!< SCU_INTERRUPT SRRAW: ACMP2I Mask */\r
+#define SCU_INTERRUPT_SRRAW_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRRAW: VDROPI Position */\r
+#define SCU_INTERRUPT_SRRAW_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VDROPI_Pos) /*!< SCU_INTERRUPT SRRAW: VDROPI Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRRAW: ORC0I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC0I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC0I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRRAW: ORC1I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC1I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC1I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRRAW: ORC2I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC2I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC2I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRRAW: ORC3I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC3I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC3I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRRAW: ORC4I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC4I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC4I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRRAW: ORC5I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC5I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC5I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRRAW: ORC6I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC6I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC6I Mask */\r
+#define SCU_INTERRUPT_SRRAW_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRRAW: ORC7I Position */\r
+#define SCU_INTERRUPT_SRRAW_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_ORC7I_Pos) /*!< SCU_INTERRUPT SRRAW: ORC7I Mask */\r
+#define SCU_INTERRUPT_SRRAW_LOCI_Pos 16 /*!< SCU_INTERRUPT SRRAW: LOCI Position */\r
+#define SCU_INTERRUPT_SRRAW_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_LOCI_Pos) /*!< SCU_INTERRUPT SRRAW: LOCI Mask */\r
+#define SCU_INTERRUPT_SRRAW_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRRAW: PESRAMI Position */\r
+#define SCU_INTERRUPT_SRRAW_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PESRAMI_Pos) /*!< SCU_INTERRUPT SRRAW: PESRAMI Mask */\r
+#define SCU_INTERRUPT_SRRAW_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRRAW: PEU0I Position */\r
+#define SCU_INTERRUPT_SRRAW_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_PEU0I_Pos) /*!< SCU_INTERRUPT SRRAW: PEU0I Mask */\r
+#define SCU_INTERRUPT_SRRAW_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRRAW: FLECC2I Position */\r
+#define SCU_INTERRUPT_SRRAW_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLECC2I_Pos) /*!< SCU_INTERRUPT SRRAW: FLECC2I Mask */\r
+#define SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Position */\r
+#define SCU_INTERRUPT_SRRAW_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRRAW: FLCMPLTI Mask */\r
+#define SCU_INTERRUPT_SRRAW_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRRAW: VCLIPI Position */\r
+#define SCU_INTERRUPT_SRRAW_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_VCLIPI_Pos) /*!< SCU_INTERRUPT SRRAW: VCLIPI Mask */\r
+#define SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Position */\r
+#define SCU_INTERRUPT_SRRAW_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRRAW_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRRAW: SBYCLKFI Mask */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRRAW: RTC_CTR Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_CTR Mask */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM0 Mask */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_ATIM1 Mask */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM0 Mask */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRRAW: RTC_TIM1 Mask */\r
+#define SCU_INTERRUPT_SRRAW_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRRAW: TSE_DONE Position */\r
+#define SCU_INTERRUPT_SRRAW_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_DONE Mask */\r
+#define SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Position */\r
+#define SCU_INTERRUPT_SRRAW_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_HIGH Mask */\r
+#define SCU_INTERRUPT_SRRAW_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRRAW: TSE_LOW Position */\r
+#define SCU_INTERRUPT_SRRAW_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRRAW_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRRAW: TSE_LOW Mask */\r
+\r
+/* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRMSK: PRWARN Position */\r
+#define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PRWARN_Pos) /*!< SCU_INTERRUPT SRMSK: PRWARN Mask */\r
+#define SCU_INTERRUPT_SRMSK_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRMSK: VDDPI Position */\r
+#define SCU_INTERRUPT_SRMSK_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDDPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDDPI Mask */\r
+#define SCU_INTERRUPT_SRMSK_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRMSK: ACMP0I Position */\r
+#define SCU_INTERRUPT_SRMSK_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP0I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP0I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRMSK: ACMP1I Position */\r
+#define SCU_INTERRUPT_SRMSK_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP1I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP1I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRMSK: ACMP2I Position */\r
+#define SCU_INTERRUPT_SRMSK_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ACMP2I_Pos) /*!< SCU_INTERRUPT SRMSK: ACMP2I Mask */\r
+#define SCU_INTERRUPT_SRMSK_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRMSK: VDROPI Position */\r
+#define SCU_INTERRUPT_SRMSK_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VDROPI_Pos) /*!< SCU_INTERRUPT SRMSK: VDROPI Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRMSK: ORC0I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC0I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC0I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRMSK: ORC1I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC1I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC1I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRMSK: ORC2I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC2I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC2I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRMSK: ORC3I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC3I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC3I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRMSK: ORC4I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC4I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC4I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRMSK: ORC5I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC5I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC5I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRMSK: ORC6I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC6I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC6I Mask */\r
+#define SCU_INTERRUPT_SRMSK_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRMSK: ORC7I Position */\r
+#define SCU_INTERRUPT_SRMSK_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_ORC7I_Pos) /*!< SCU_INTERRUPT SRMSK: ORC7I Mask */\r
+#define SCU_INTERRUPT_SRMSK_LOCI_Pos 16 /*!< SCU_INTERRUPT SRMSK: LOCI Position */\r
+#define SCU_INTERRUPT_SRMSK_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_LOCI_Pos) /*!< SCU_INTERRUPT SRMSK: LOCI Mask */\r
+#define SCU_INTERRUPT_SRMSK_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRMSK: PESRAMI Position */\r
+#define SCU_INTERRUPT_SRMSK_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PESRAMI_Pos) /*!< SCU_INTERRUPT SRMSK: PESRAMI Mask */\r
+#define SCU_INTERRUPT_SRMSK_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRMSK: PEU0I Position */\r
+#define SCU_INTERRUPT_SRMSK_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_PEU0I_Pos) /*!< SCU_INTERRUPT SRMSK: PEU0I Mask */\r
+#define SCU_INTERRUPT_SRMSK_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRMSK: FLECC2I Position */\r
+#define SCU_INTERRUPT_SRMSK_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRMSK_FLECC2I_Pos) /*!< SCU_INTERRUPT SRMSK: FLECC2I Mask */\r
+#define SCU_INTERRUPT_SRMSK_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRMSK: VCLIPI Position */\r
+#define SCU_INTERRUPT_SRMSK_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_VCLIPI_Pos) /*!< SCU_INTERRUPT SRMSK: VCLIPI Mask */\r
+#define SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Position */\r
+#define SCU_INTERRUPT_SRMSK_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRMSK_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRMSK: SBYCLKFI Mask */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRMSK: RTC_CTR Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_CTR Mask */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM0 Mask */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_ATIM1 Mask */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM0 Mask */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRMSK: RTC_TIM1 Mask */\r
+#define SCU_INTERRUPT_SRMSK_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRMSK: TSE_DONE Position */\r
+#define SCU_INTERRUPT_SRMSK_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_DONE Mask */\r
+#define SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Position */\r
+#define SCU_INTERRUPT_SRMSK_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_HIGH Mask */\r
+#define SCU_INTERRUPT_SRMSK_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRMSK: TSE_LOW Position */\r
+#define SCU_INTERRUPT_SRMSK_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRMSK_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRMSK: TSE_LOW Mask */\r
+\r
+/* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRCLR: PRWARN Position */\r
+#define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PRWARN_Pos) /*!< SCU_INTERRUPT SRCLR: PRWARN Mask */\r
+#define SCU_INTERRUPT_SRCLR_PI_Pos 1 /*!< SCU_INTERRUPT SRCLR: PI Position */\r
+#define SCU_INTERRUPT_SRCLR_PI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PI_Pos) /*!< SCU_INTERRUPT SRCLR: PI Mask */\r
+#define SCU_INTERRUPT_SRCLR_AI_Pos 2 /*!< SCU_INTERRUPT SRCLR: AI Position */\r
+#define SCU_INTERRUPT_SRCLR_AI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_AI_Pos) /*!< SCU_INTERRUPT SRCLR: AI Mask */\r
+#define SCU_INTERRUPT_SRCLR_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRCLR: VDDPI Position */\r
+#define SCU_INTERRUPT_SRCLR_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDDPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDDPI Mask */\r
+#define SCU_INTERRUPT_SRCLR_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRCLR: ACMP0I Position */\r
+#define SCU_INTERRUPT_SRCLR_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP0I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP0I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRCLR: ACMP1I Position */\r
+#define SCU_INTERRUPT_SRCLR_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP1I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP1I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRCLR: ACMP2I Position */\r
+#define SCU_INTERRUPT_SRCLR_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ACMP2I_Pos) /*!< SCU_INTERRUPT SRCLR: ACMP2I Mask */\r
+#define SCU_INTERRUPT_SRCLR_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRCLR: VDROPI Position */\r
+#define SCU_INTERRUPT_SRCLR_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VDROPI_Pos) /*!< SCU_INTERRUPT SRCLR: VDROPI Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRCLR: ORC0I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC0I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC0I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRCLR: ORC1I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC1I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC1I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRCLR: ORC2I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC2I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC2I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRCLR: ORC3I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC3I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC3I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRCLR: ORC4I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC4I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC4I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRCLR: ORC5I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC5I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC5I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRCLR: ORC6I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC6I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC6I Mask */\r
+#define SCU_INTERRUPT_SRCLR_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRCLR: ORC7I Position */\r
+#define SCU_INTERRUPT_SRCLR_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_ORC7I_Pos) /*!< SCU_INTERRUPT SRCLR: ORC7I Mask */\r
+#define SCU_INTERRUPT_SRCLR_LOCI_Pos 16 /*!< SCU_INTERRUPT SRCLR: LOCI Position */\r
+#define SCU_INTERRUPT_SRCLR_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_LOCI_Pos) /*!< SCU_INTERRUPT SRCLR: LOCI Mask */\r
+#define SCU_INTERRUPT_SRCLR_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRCLR: PESRAMI Position */\r
+#define SCU_INTERRUPT_SRCLR_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PESRAMI_Pos) /*!< SCU_INTERRUPT SRCLR: PESRAMI Mask */\r
+#define SCU_INTERRUPT_SRCLR_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRCLR: PEU0I Position */\r
+#define SCU_INTERRUPT_SRCLR_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_PEU0I_Pos) /*!< SCU_INTERRUPT SRCLR: PEU0I Mask */\r
+#define SCU_INTERRUPT_SRCLR_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRCLR: FLECC2I Position */\r
+#define SCU_INTERRUPT_SRCLR_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLECC2I_Pos) /*!< SCU_INTERRUPT SRCLR: FLECC2I Mask */\r
+#define SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Position */\r
+#define SCU_INTERRUPT_SRCLR_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRCLR: FLCMPLTI Mask */\r
+#define SCU_INTERRUPT_SRCLR_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRCLR: VCLIPI Position */\r
+#define SCU_INTERRUPT_SRCLR_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_VCLIPI_Pos) /*!< SCU_INTERRUPT SRCLR: VCLIPI Mask */\r
+#define SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Position */\r
+#define SCU_INTERRUPT_SRCLR_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRCLR_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRCLR: SBYCLKFI Mask */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRCLR: RTC_CTR Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_CTR Mask */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM0 Mask */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_ATIM1 Mask */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM0 Mask */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRCLR: RTC_TIM1 Mask */\r
+#define SCU_INTERRUPT_SRCLR_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRCLR: TSE_DONE Position */\r
+#define SCU_INTERRUPT_SRCLR_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_DONE Mask */\r
+#define SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Position */\r
+#define SCU_INTERRUPT_SRCLR_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_HIGH Mask */\r
+#define SCU_INTERRUPT_SRCLR_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRCLR: TSE_LOW Position */\r
+#define SCU_INTERRUPT_SRCLR_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRCLR_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRCLR: TSE_LOW Mask */\r
+\r
+/* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Pos 0 /*!< SCU_INTERRUPT SRSET: PRWARN Position */\r
+#define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x01UL << SCU_INTERRUPT_SRSET_PRWARN_Pos) /*!< SCU_INTERRUPT SRSET: PRWARN Mask */\r
+#define SCU_INTERRUPT_SRSET_PI_Pos 1 /*!< SCU_INTERRUPT SRSET: PI Position */\r
+#define SCU_INTERRUPT_SRSET_PI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PI_Pos) /*!< SCU_INTERRUPT SRSET: PI Mask */\r
+#define SCU_INTERRUPT_SRSET_AI_Pos 2 /*!< SCU_INTERRUPT SRSET: AI Position */\r
+#define SCU_INTERRUPT_SRSET_AI_Msk (0x01UL << SCU_INTERRUPT_SRSET_AI_Pos) /*!< SCU_INTERRUPT SRSET: AI Mask */\r
+#define SCU_INTERRUPT_SRSET_VDDPI_Pos 3 /*!< SCU_INTERRUPT SRSET: VDDPI Position */\r
+#define SCU_INTERRUPT_SRSET_VDDPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDDPI_Pos) /*!< SCU_INTERRUPT SRSET: VDDPI Mask */\r
+#define SCU_INTERRUPT_SRSET_ACMP0I_Pos 4 /*!< SCU_INTERRUPT SRSET: ACMP0I Position */\r
+#define SCU_INTERRUPT_SRSET_ACMP0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP0I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP0I Mask */\r
+#define SCU_INTERRUPT_SRSET_ACMP1I_Pos 5 /*!< SCU_INTERRUPT SRSET: ACMP1I Position */\r
+#define SCU_INTERRUPT_SRSET_ACMP1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP1I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP1I Mask */\r
+#define SCU_INTERRUPT_SRSET_ACMP2I_Pos 6 /*!< SCU_INTERRUPT SRSET: ACMP2I Position */\r
+#define SCU_INTERRUPT_SRSET_ACMP2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ACMP2I_Pos) /*!< SCU_INTERRUPT SRSET: ACMP2I Mask */\r
+#define SCU_INTERRUPT_SRSET_VDROPI_Pos 7 /*!< SCU_INTERRUPT SRSET: VDROPI Position */\r
+#define SCU_INTERRUPT_SRSET_VDROPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VDROPI_Pos) /*!< SCU_INTERRUPT SRSET: VDROPI Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC0I_Pos 8 /*!< SCU_INTERRUPT SRSET: ORC0I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC0I_Pos) /*!< SCU_INTERRUPT SRSET: ORC0I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC1I_Pos 9 /*!< SCU_INTERRUPT SRSET: ORC1I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC1I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC1I_Pos) /*!< SCU_INTERRUPT SRSET: ORC1I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC2I_Pos 10 /*!< SCU_INTERRUPT SRSET: ORC2I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC2I_Pos) /*!< SCU_INTERRUPT SRSET: ORC2I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC3I_Pos 11 /*!< SCU_INTERRUPT SRSET: ORC3I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC3I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC3I_Pos) /*!< SCU_INTERRUPT SRSET: ORC3I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC4I_Pos 12 /*!< SCU_INTERRUPT SRSET: ORC4I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC4I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC4I_Pos) /*!< SCU_INTERRUPT SRSET: ORC4I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC5I_Pos 13 /*!< SCU_INTERRUPT SRSET: ORC5I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC5I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC5I_Pos) /*!< SCU_INTERRUPT SRSET: ORC5I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC6I_Pos 14 /*!< SCU_INTERRUPT SRSET: ORC6I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC6I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC6I_Pos) /*!< SCU_INTERRUPT SRSET: ORC6I Mask */\r
+#define SCU_INTERRUPT_SRSET_ORC7I_Pos 15 /*!< SCU_INTERRUPT SRSET: ORC7I Position */\r
+#define SCU_INTERRUPT_SRSET_ORC7I_Msk (0x01UL << SCU_INTERRUPT_SRSET_ORC7I_Pos) /*!< SCU_INTERRUPT SRSET: ORC7I Mask */\r
+#define SCU_INTERRUPT_SRSET_LOCI_Pos 16 /*!< SCU_INTERRUPT SRSET: LOCI Position */\r
+#define SCU_INTERRUPT_SRSET_LOCI_Msk (0x01UL << SCU_INTERRUPT_SRSET_LOCI_Pos) /*!< SCU_INTERRUPT SRSET: LOCI Mask */\r
+#define SCU_INTERRUPT_SRSET_PESRAMI_Pos 17 /*!< SCU_INTERRUPT SRSET: PESRAMI Position */\r
+#define SCU_INTERRUPT_SRSET_PESRAMI_Msk (0x01UL << SCU_INTERRUPT_SRSET_PESRAMI_Pos) /*!< SCU_INTERRUPT SRSET: PESRAMI Mask */\r
+#define SCU_INTERRUPT_SRSET_PEU0I_Pos 18 /*!< SCU_INTERRUPT SRSET: PEU0I Position */\r
+#define SCU_INTERRUPT_SRSET_PEU0I_Msk (0x01UL << SCU_INTERRUPT_SRSET_PEU0I_Pos) /*!< SCU_INTERRUPT SRSET: PEU0I Mask */\r
+#define SCU_INTERRUPT_SRSET_FLECC2I_Pos 19 /*!< SCU_INTERRUPT SRSET: FLECC2I Position */\r
+#define SCU_INTERRUPT_SRSET_FLECC2I_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLECC2I_Pos) /*!< SCU_INTERRUPT SRSET: FLECC2I Mask */\r
+#define SCU_INTERRUPT_SRSET_FLCMPLTI_Pos 20 /*!< SCU_INTERRUPT SRSET: FLCMPLTI Position */\r
+#define SCU_INTERRUPT_SRSET_FLCMPLTI_Msk (0x01UL << SCU_INTERRUPT_SRSET_FLCMPLTI_Pos) /*!< SCU_INTERRUPT SRSET: FLCMPLTI Mask */\r
+#define SCU_INTERRUPT_SRSET_VCLIPI_Pos 21 /*!< SCU_INTERRUPT SRSET: VCLIPI Position */\r
+#define SCU_INTERRUPT_SRSET_VCLIPI_Msk (0x01UL << SCU_INTERRUPT_SRSET_VCLIPI_Pos) /*!< SCU_INTERRUPT SRSET: VCLIPI Mask */\r
+#define SCU_INTERRUPT_SRSET_SBYCLKFI_Pos 22 /*!< SCU_INTERRUPT SRSET: SBYCLKFI Position */\r
+#define SCU_INTERRUPT_SRSET_SBYCLKFI_Msk (0x01UL << SCU_INTERRUPT_SRSET_SBYCLKFI_Pos) /*!< SCU_INTERRUPT SRSET: SBYCLKFI Mask */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Pos 24 /*!< SCU_INTERRUPT SRSET: RTC_CTR Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_CTR_Pos) /*!< SCU_INTERRUPT SRSET: RTC_CTR Mask */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos 25 /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM0 Mask */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos 26 /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_ATIM1 Mask */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos 27 /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM0_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM0 Mask */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos 28 /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Position */\r
+#define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x01UL << SCU_INTERRUPT_SRSET_RTC_TIM1_Pos) /*!< SCU_INTERRUPT SRSET: RTC_TIM1 Mask */\r
+#define SCU_INTERRUPT_SRSET_TSE_DONE_Pos 29 /*!< SCU_INTERRUPT SRSET: TSE_DONE Position */\r
+#define SCU_INTERRUPT_SRSET_TSE_DONE_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_DONE_Pos) /*!< SCU_INTERRUPT SRSET: TSE_DONE Mask */\r
+#define SCU_INTERRUPT_SRSET_TSE_HIGH_Pos 30 /*!< SCU_INTERRUPT SRSET: TSE_HIGH Position */\r
+#define SCU_INTERRUPT_SRSET_TSE_HIGH_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_HIGH_Pos) /*!< SCU_INTERRUPT SRSET: TSE_HIGH Mask */\r
+#define SCU_INTERRUPT_SRSET_TSE_LOW_Pos 31 /*!< SCU_INTERRUPT SRSET: TSE_LOW Position */\r
+#define SCU_INTERRUPT_SRSET_TSE_LOW_Msk (0x01UL << SCU_INTERRUPT_SRSET_TSE_LOW_Pos) /*!< SCU_INTERRUPT SRSET: TSE_LOW Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SCU_POWER' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------- SCU_POWER_VDESR ------------------------------ */\r
+#define SCU_POWER_VDESR_VCLIP_Pos 0 /*!< SCU_POWER VDESR: VCLIP Position */\r
+#define SCU_POWER_VDESR_VCLIP_Msk (0x01UL << SCU_POWER_VDESR_VCLIP_Pos) /*!< SCU_POWER VDESR: VCLIP Mask */\r
+#define SCU_POWER_VDESR_VDDPPW_Pos 1 /*!< SCU_POWER VDESR: VDDPPW Position */\r
+#define SCU_POWER_VDESR_VDDPPW_Msk (0x01UL << SCU_POWER_VDESR_VDDPPW_Pos) /*!< SCU_POWER VDESR: VDDPPW Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SCU_CLK' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- SCU_CLK_CLKCR ------------------------------- */\r
+#define SCU_CLK_CLKCR_FDIV_Pos 0 /*!< SCU_CLK CLKCR: FDIV Position */\r
+#define SCU_CLK_CLKCR_FDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_FDIV_Pos) /*!< SCU_CLK CLKCR: FDIV Mask */\r
+#define SCU_CLK_CLKCR_IDIV_Pos 8 /*!< SCU_CLK CLKCR: IDIV Position */\r
+#define SCU_CLK_CLKCR_IDIV_Msk (0x000000ffUL << SCU_CLK_CLKCR_IDIV_Pos) /*!< SCU_CLK CLKCR: IDIV Mask */\r
+#define SCU_CLK_CLKCR_PCLKSEL_Pos 16 /*!< SCU_CLK CLKCR: PCLKSEL Position */\r
+#define SCU_CLK_CLKCR_PCLKSEL_Msk (0x01UL << SCU_CLK_CLKCR_PCLKSEL_Pos) /*!< SCU_CLK CLKCR: PCLKSEL Mask */\r
+#define SCU_CLK_CLKCR_RTCCLKSEL_Pos 17 /*!< SCU_CLK CLKCR: RTCCLKSEL Position */\r
+#define SCU_CLK_CLKCR_RTCCLKSEL_Msk (0x07UL << SCU_CLK_CLKCR_RTCCLKSEL_Pos) /*!< SCU_CLK CLKCR: RTCCLKSEL Mask */\r
+#define SCU_CLK_CLKCR_CNTADJ_Pos 20 /*!< SCU_CLK CLKCR: CNTADJ Position */\r
+#define SCU_CLK_CLKCR_CNTADJ_Msk (0x000003ffUL << SCU_CLK_CLKCR_CNTADJ_Pos) /*!< SCU_CLK CLKCR: CNTADJ Mask */\r
+#define SCU_CLK_CLKCR_VDDC2LOW_Pos 30 /*!< SCU_CLK CLKCR: VDDC2LOW Position */\r
+#define SCU_CLK_CLKCR_VDDC2LOW_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2LOW_Pos) /*!< SCU_CLK CLKCR: VDDC2LOW Mask */\r
+#define SCU_CLK_CLKCR_VDDC2HIGH_Pos 31 /*!< SCU_CLK CLKCR: VDDC2HIGH Position */\r
+#define SCU_CLK_CLKCR_VDDC2HIGH_Msk (0x01UL << SCU_CLK_CLKCR_VDDC2HIGH_Pos) /*!< SCU_CLK CLKCR: VDDC2HIGH Mask */\r
+\r
+/* ------------------------------- SCU_CLK_PWRSVCR ------------------------------ */\r
+#define SCU_CLK_PWRSVCR_FPD_Pos 0 /*!< SCU_CLK PWRSVCR: FPD Position */\r
+#define SCU_CLK_PWRSVCR_FPD_Msk (0x01UL << SCU_CLK_PWRSVCR_FPD_Pos) /*!< SCU_CLK PWRSVCR: FPD Mask */\r
+\r
+/* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */\r
+#define SCU_CLK_CGATSTAT0_VADC_Pos 0 /*!< SCU_CLK CGATSTAT0: VADC Position */\r
+#define SCU_CLK_CGATSTAT0_VADC_Msk (0x01UL << SCU_CLK_CGATSTAT0_VADC_Pos) /*!< SCU_CLK CGATSTAT0: VADC Mask */\r
+#define SCU_CLK_CGATSTAT0_CCU40_Pos 2 /*!< SCU_CLK CGATSTAT0: CCU40 Position */\r
+#define SCU_CLK_CGATSTAT0_CCU40_Msk (0x01UL << SCU_CLK_CGATSTAT0_CCU40_Pos) /*!< SCU_CLK CGATSTAT0: CCU40 Mask */\r
+#define SCU_CLK_CGATSTAT0_USIC0_Pos 3 /*!< SCU_CLK CGATSTAT0: USIC0 Position */\r
+#define SCU_CLK_CGATSTAT0_USIC0_Msk (0x01UL << SCU_CLK_CGATSTAT0_USIC0_Pos) /*!< SCU_CLK CGATSTAT0: USIC0 Mask */\r
+#define SCU_CLK_CGATSTAT0_BCCU0_Pos 4 /*!< SCU_CLK CGATSTAT0: BCCU0 Position */\r
+#define SCU_CLK_CGATSTAT0_BCCU0_Msk (0x01UL << SCU_CLK_CGATSTAT0_BCCU0_Pos) /*!< SCU_CLK CGATSTAT0: BCCU0 Mask */\r
+#define SCU_CLK_CGATSTAT0_LEDTS0_Pos 5 /*!< SCU_CLK CGATSTAT0: LEDTS0 Position */\r
+#define SCU_CLK_CGATSTAT0_LEDTS0_Msk (0x01UL << SCU_CLK_CGATSTAT0_LEDTS0_Pos) /*!< SCU_CLK CGATSTAT0: LEDTS0 Mask */\r
+#define SCU_CLK_CGATSTAT0_LEDTS1_Pos 6 /*!< SCU_CLK CGATSTAT0: LEDTS1 Position */\r
+#define SCU_CLK_CGATSTAT0_LEDTS1_Msk (0x01UL << SCU_CLK_CGATSTAT0_LEDTS1_Pos) /*!< SCU_CLK CGATSTAT0: LEDTS1 Mask */\r
+#define SCU_CLK_CGATSTAT0_WDT_Pos 9 /*!< SCU_CLK CGATSTAT0: WDT Position */\r
+#define SCU_CLK_CGATSTAT0_WDT_Msk (0x01UL << SCU_CLK_CGATSTAT0_WDT_Pos) /*!< SCU_CLK CGATSTAT0: WDT Mask */\r
+#define SCU_CLK_CGATSTAT0_RTC_Pos 10 /*!< SCU_CLK CGATSTAT0: RTC Position */\r
+#define SCU_CLK_CGATSTAT0_RTC_Msk (0x01UL << SCU_CLK_CGATSTAT0_RTC_Pos) /*!< SCU_CLK CGATSTAT0: RTC Mask */\r
+\r
+/* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */\r
+#define SCU_CLK_CGATSET0_VADC_Pos 0 /*!< SCU_CLK CGATSET0: VADC Position */\r
+#define SCU_CLK_CGATSET0_VADC_Msk (0x01UL << SCU_CLK_CGATSET0_VADC_Pos) /*!< SCU_CLK CGATSET0: VADC Mask */\r
+#define SCU_CLK_CGATSET0_CCU40_Pos 2 /*!< SCU_CLK CGATSET0: CCU40 Position */\r
+#define SCU_CLK_CGATSET0_CCU40_Msk (0x01UL << SCU_CLK_CGATSET0_CCU40_Pos) /*!< SCU_CLK CGATSET0: CCU40 Mask */\r
+#define SCU_CLK_CGATSET0_USIC0_Pos 3 /*!< SCU_CLK CGATSET0: USIC0 Position */\r
+#define SCU_CLK_CGATSET0_USIC0_Msk (0x01UL << SCU_CLK_CGATSET0_USIC0_Pos) /*!< SCU_CLK CGATSET0: USIC0 Mask */\r
+#define SCU_CLK_CGATSET0_BCCU0_Pos 4 /*!< SCU_CLK CGATSET0: BCCU0 Position */\r
+#define SCU_CLK_CGATSET0_BCCU0_Msk (0x01UL << SCU_CLK_CGATSET0_BCCU0_Pos) /*!< SCU_CLK CGATSET0: BCCU0 Mask */\r
+#define SCU_CLK_CGATSET0_LEDTS0_Pos 5 /*!< SCU_CLK CGATSET0: LEDTS0 Position */\r
+#define SCU_CLK_CGATSET0_LEDTS0_Msk (0x01UL << SCU_CLK_CGATSET0_LEDTS0_Pos) /*!< SCU_CLK CGATSET0: LEDTS0 Mask */\r
+#define SCU_CLK_CGATSET0_LEDTS1_Pos 6 /*!< SCU_CLK CGATSET0: LEDTS1 Position */\r
+#define SCU_CLK_CGATSET0_LEDTS1_Msk (0x01UL << SCU_CLK_CGATSET0_LEDTS1_Pos) /*!< SCU_CLK CGATSET0: LEDTS1 Mask */\r
+#define SCU_CLK_CGATSET0_WDT_Pos 9 /*!< SCU_CLK CGATSET0: WDT Position */\r
+#define SCU_CLK_CGATSET0_WDT_Msk (0x01UL << SCU_CLK_CGATSET0_WDT_Pos) /*!< SCU_CLK CGATSET0: WDT Mask */\r
+#define SCU_CLK_CGATSET0_RTC_Pos 10 /*!< SCU_CLK CGATSET0: RTC Position */\r
+#define SCU_CLK_CGATSET0_RTC_Msk (0x01UL << SCU_CLK_CGATSET0_RTC_Pos) /*!< SCU_CLK CGATSET0: RTC Mask */\r
+\r
+/* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */\r
+#define SCU_CLK_CGATCLR0_VADC_Pos 0 /*!< SCU_CLK CGATCLR0: VADC Position */\r
+#define SCU_CLK_CGATCLR0_VADC_Msk (0x01UL << SCU_CLK_CGATCLR0_VADC_Pos) /*!< SCU_CLK CGATCLR0: VADC Mask */\r
+#define SCU_CLK_CGATCLR0_CCU40_Pos 2 /*!< SCU_CLK CGATCLR0: CCU40 Position */\r
+#define SCU_CLK_CGATCLR0_CCU40_Msk (0x01UL << SCU_CLK_CGATCLR0_CCU40_Pos) /*!< SCU_CLK CGATCLR0: CCU40 Mask */\r
+#define SCU_CLK_CGATCLR0_USIC0_Pos 3 /*!< SCU_CLK CGATCLR0: USIC0 Position */\r
+#define SCU_CLK_CGATCLR0_USIC0_Msk (0x01UL << SCU_CLK_CGATCLR0_USIC0_Pos) /*!< SCU_CLK CGATCLR0: USIC0 Mask */\r
+#define SCU_CLK_CGATCLR0_BCCU0_Pos 4 /*!< SCU_CLK CGATCLR0: BCCU0 Position */\r
+#define SCU_CLK_CGATCLR0_BCCU0_Msk (0x01UL << SCU_CLK_CGATCLR0_BCCU0_Pos) /*!< SCU_CLK CGATCLR0: BCCU0 Mask */\r
+#define SCU_CLK_CGATCLR0_LEDTS0_Pos 5 /*!< SCU_CLK CGATCLR0: LEDTS0 Position */\r
+#define SCU_CLK_CGATCLR0_LEDTS0_Msk (0x01UL << SCU_CLK_CGATCLR0_LEDTS0_Pos) /*!< SCU_CLK CGATCLR0: LEDTS0 Mask */\r
+#define SCU_CLK_CGATCLR0_LEDTS1_Pos 6 /*!< SCU_CLK CGATCLR0: LEDTS1 Position */\r
+#define SCU_CLK_CGATCLR0_LEDTS1_Msk (0x01UL << SCU_CLK_CGATCLR0_LEDTS1_Pos) /*!< SCU_CLK CGATCLR0: LEDTS1 Mask */\r
+#define SCU_CLK_CGATCLR0_WDT_Pos 9 /*!< SCU_CLK CGATCLR0: WDT Position */\r
+#define SCU_CLK_CGATCLR0_WDT_Msk (0x01UL << SCU_CLK_CGATCLR0_WDT_Pos) /*!< SCU_CLK CGATCLR0: WDT Mask */\r
+#define SCU_CLK_CGATCLR0_RTC_Pos 10 /*!< SCU_CLK CGATCLR0: RTC Position */\r
+#define SCU_CLK_CGATCLR0_RTC_Msk (0x01UL << SCU_CLK_CGATCLR0_RTC_Pos) /*!< SCU_CLK CGATCLR0: RTC Mask */\r
+\r
+/* ------------------------------- SCU_CLK_OSCCSR ------------------------------- */\r
+#define SCU_CLK_OSCCSR_OSC2L_Pos 0 /*!< SCU_CLK OSCCSR: OSC2L Position */\r
+#define SCU_CLK_OSCCSR_OSC2L_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2L_Pos) /*!< SCU_CLK OSCCSR: OSC2L Mask */\r
+#define SCU_CLK_OSCCSR_OSC2H_Pos 1 /*!< SCU_CLK OSCCSR: OSC2H Position */\r
+#define SCU_CLK_OSCCSR_OSC2H_Msk (0x01UL << SCU_CLK_OSCCSR_OSC2H_Pos) /*!< SCU_CLK OSCCSR: OSC2H Mask */\r
+#define SCU_CLK_OSCCSR_OWDRES_Pos 16 /*!< SCU_CLK OSCCSR: OWDRES Position */\r
+#define SCU_CLK_OSCCSR_OWDRES_Msk (0x01UL << SCU_CLK_OSCCSR_OWDRES_Pos) /*!< SCU_CLK OSCCSR: OWDRES Mask */\r
+#define SCU_CLK_OSCCSR_OWDEN_Pos 17 /*!< SCU_CLK OSCCSR: OWDEN Position */\r
+#define SCU_CLK_OSCCSR_OWDEN_Msk (0x01UL << SCU_CLK_OSCCSR_OWDEN_Pos) /*!< SCU_CLK OSCCSR: OWDEN Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SCU_RESET' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Pos 0 /*!< SCU_RESET RSTSTAT: RSTSTAT Position */\r
+#define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0x000003ffUL << SCU_RESET_RSTSTAT_RSTSTAT_Pos) /*!< SCU_RESET RSTSTAT: RSTSTAT Mask */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Pos 10 /*!< SCU_RESET RSTSTAT: LCKEN Position */\r
+#define SCU_RESET_RSTSTAT_LCKEN_Msk (0x01UL << SCU_RESET_RSTSTAT_LCKEN_Pos) /*!< SCU_RESET RSTSTAT: LCKEN Mask */\r
+\r
+/* ------------------------------ SCU_RESET_RSTSET ------------------------------ */\r
+#define SCU_RESET_RSTSET_LCKEN_Pos 10 /*!< SCU_RESET RSTSET: LCKEN Position */\r
+#define SCU_RESET_RSTSET_LCKEN_Msk (0x01UL << SCU_RESET_RSTSET_LCKEN_Pos) /*!< SCU_RESET RSTSET: LCKEN Mask */\r
+\r
+/* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */\r
+#define SCU_RESET_RSTCLR_RSCLR_Pos 0 /*!< SCU_RESET RSTCLR: RSCLR Position */\r
+#define SCU_RESET_RSTCLR_RSCLR_Msk (0x01UL << SCU_RESET_RSTCLR_RSCLR_Pos) /*!< SCU_RESET RSTCLR: RSCLR Mask */\r
+#define SCU_RESET_RSTCLR_LCKEN_Pos 10 /*!< SCU_RESET RSTCLR: LCKEN Position */\r
+#define SCU_RESET_RSTCLR_LCKEN_Msk (0x01UL << SCU_RESET_RSTCLR_LCKEN_Pos) /*!< SCU_RESET RSTCLR: LCKEN Mask */\r
+\r
+/* ------------------------------ SCU_RESET_RSTCON ------------------------------ */\r
+#define SCU_RESET_RSTCON_ECCRSTEN_Pos 0 /*!< SCU_RESET RSTCON: ECCRSTEN Position */\r
+#define SCU_RESET_RSTCON_ECCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_ECCRSTEN_Pos) /*!< SCU_RESET RSTCON: ECCRSTEN Mask */\r
+#define SCU_RESET_RSTCON_LOCRSTEN_Pos 1 /*!< SCU_RESET RSTCON: LOCRSTEN Position */\r
+#define SCU_RESET_RSTCON_LOCRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_LOCRSTEN_Pos) /*!< SCU_RESET RSTCON: LOCRSTEN Mask */\r
+#define SCU_RESET_RSTCON_SPERSTEN_Pos 2 /*!< SCU_RESET RSTCON: SPERSTEN Position */\r
+#define SCU_RESET_RSTCON_SPERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_SPERSTEN_Pos) /*!< SCU_RESET RSTCON: SPERSTEN Mask */\r
+#define SCU_RESET_RSTCON_U0PERSTEN_Pos 3 /*!< SCU_RESET RSTCON: U0PERSTEN Position */\r
+#define SCU_RESET_RSTCON_U0PERSTEN_Msk (0x01UL << SCU_RESET_RSTCON_U0PERSTEN_Pos) /*!< SCU_RESET RSTCON: U0PERSTEN Mask */\r
+#define SCU_RESET_RSTCON_MRSTEN_Pos 16 /*!< SCU_RESET RSTCON: MRSTEN Position */\r
+#define SCU_RESET_RSTCON_MRSTEN_Msk (0x01UL << SCU_RESET_RSTCON_MRSTEN_Pos) /*!< SCU_RESET RSTCON: MRSTEN Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'COMPARATOR' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------- COMPARATOR_ORCCTRL ----------------------------- */\r
+#define COMPARATOR_ORCCTRL_ENORC0_Pos 0 /*!< COMPARATOR ORCCTRL: ENORC0 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC0_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC0_Pos) /*!< COMPARATOR ORCCTRL: ENORC0 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC1_Pos 1 /*!< COMPARATOR ORCCTRL: ENORC1 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC1_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC1_Pos) /*!< COMPARATOR ORCCTRL: ENORC1 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC2_Pos 2 /*!< COMPARATOR ORCCTRL: ENORC2 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC2_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC2_Pos) /*!< COMPARATOR ORCCTRL: ENORC2 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC3_Pos 3 /*!< COMPARATOR ORCCTRL: ENORC3 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC3_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC3_Pos) /*!< COMPARATOR ORCCTRL: ENORC3 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC4_Pos 4 /*!< COMPARATOR ORCCTRL: ENORC4 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC4_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC4_Pos) /*!< COMPARATOR ORCCTRL: ENORC4 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC5_Pos 5 /*!< COMPARATOR ORCCTRL: ENORC5 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC5_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC5_Pos) /*!< COMPARATOR ORCCTRL: ENORC5 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC6_Pos 6 /*!< COMPARATOR ORCCTRL: ENORC6 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC6_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC6_Pos) /*!< COMPARATOR ORCCTRL: ENORC6 Mask */\r
+#define COMPARATOR_ORCCTRL_ENORC7_Pos 7 /*!< COMPARATOR ORCCTRL: ENORC7 Position */\r
+#define COMPARATOR_ORCCTRL_ENORC7_Msk (0x01UL << COMPARATOR_ORCCTRL_ENORC7_Pos) /*!< COMPARATOR ORCCTRL: ENORC7 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF0_Pos 16 /*!< COMPARATOR ORCCTRL: CNF0 Position */\r
+#define COMPARATOR_ORCCTRL_CNF0_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF0_Pos) /*!< COMPARATOR ORCCTRL: CNF0 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF1_Pos 17 /*!< COMPARATOR ORCCTRL: CNF1 Position */\r
+#define COMPARATOR_ORCCTRL_CNF1_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF1_Pos) /*!< COMPARATOR ORCCTRL: CNF1 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF2_Pos 18 /*!< COMPARATOR ORCCTRL: CNF2 Position */\r
+#define COMPARATOR_ORCCTRL_CNF2_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF2_Pos) /*!< COMPARATOR ORCCTRL: CNF2 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF3_Pos 19 /*!< COMPARATOR ORCCTRL: CNF3 Position */\r
+#define COMPARATOR_ORCCTRL_CNF3_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF3_Pos) /*!< COMPARATOR ORCCTRL: CNF3 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF4_Pos 20 /*!< COMPARATOR ORCCTRL: CNF4 Position */\r
+#define COMPARATOR_ORCCTRL_CNF4_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF4_Pos) /*!< COMPARATOR ORCCTRL: CNF4 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF5_Pos 21 /*!< COMPARATOR ORCCTRL: CNF5 Position */\r
+#define COMPARATOR_ORCCTRL_CNF5_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF5_Pos) /*!< COMPARATOR ORCCTRL: CNF5 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF6_Pos 22 /*!< COMPARATOR ORCCTRL: CNF6 Position */\r
+#define COMPARATOR_ORCCTRL_CNF6_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF6_Pos) /*!< COMPARATOR ORCCTRL: CNF6 Mask */\r
+#define COMPARATOR_ORCCTRL_CNF7_Pos 23 /*!< COMPARATOR ORCCTRL: CNF7 Position */\r
+#define COMPARATOR_ORCCTRL_CNF7_Msk (0x01UL << COMPARATOR_ORCCTRL_CNF7_Pos) /*!< COMPARATOR ORCCTRL: CNF7 Mask */\r
+\r
+/* ----------------------------- COMPARATOR_ANACMP0 ----------------------------- */\r
+#define COMPARATOR_ANACMP0_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP0: CMP_EN Position */\r
+#define COMPARATOR_ANACMP0_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_EN_Pos) /*!< COMPARATOR ANACMP0: CMP_EN Mask */\r
+#define COMPARATOR_ANACMP0_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP0: CMP_FLT_OFF Position */\r
+#define COMPARATOR_ANACMP0_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP0: CMP_FLT_OFF Mask */\r
+#define COMPARATOR_ANACMP0_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP0: CMP_INV_OUT Position */\r
+#define COMPARATOR_ANACMP0_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP0: CMP_INV_OUT Mask */\r
+#define COMPARATOR_ANACMP0_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP0: CMP_HYST_ADJ Position */\r
+#define COMPARATOR_ANACMP0_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP0_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP0: CMP_HYST_ADJ Mask */\r
+#define COMPARATOR_ANACMP0_ACMP0_SEL_Pos 6 /*!< COMPARATOR ANACMP0: ACMP0_SEL Position */\r
+#define COMPARATOR_ANACMP0_ACMP0_SEL_Msk (0x01UL << COMPARATOR_ANACMP0_ACMP0_SEL_Pos) /*!< COMPARATOR ANACMP0: ACMP0_SEL Mask */\r
+#define COMPARATOR_ANACMP0_CMP_LPWR_Pos 8 /*!< COMPARATOR ANACMP0: CMP_LPWR Position */\r
+#define COMPARATOR_ANACMP0_CMP_LPWR_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_LPWR_Pos) /*!< COMPARATOR ANACMP0: CMP_LPWR Mask */\r
+#define COMPARATOR_ANACMP0_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP0: CMP_OUT Position */\r
+#define COMPARATOR_ANACMP0_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP0_CMP_OUT_Pos) /*!< COMPARATOR ANACMP0: CMP_OUT Mask */\r
+\r
+/* ----------------------------- COMPARATOR_ANACMP1 ----------------------------- */\r
+#define COMPARATOR_ANACMP1_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP1: CMP_EN Position */\r
+#define COMPARATOR_ANACMP1_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_EN_Pos) /*!< COMPARATOR ANACMP1: CMP_EN Mask */\r
+#define COMPARATOR_ANACMP1_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP1: CMP_FLT_OFF Position */\r
+#define COMPARATOR_ANACMP1_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP1: CMP_FLT_OFF Mask */\r
+#define COMPARATOR_ANACMP1_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP1: CMP_INV_OUT Position */\r
+#define COMPARATOR_ANACMP1_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP1: CMP_INV_OUT Mask */\r
+#define COMPARATOR_ANACMP1_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP1: CMP_HYST_ADJ Position */\r
+#define COMPARATOR_ANACMP1_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP1_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP1: CMP_HYST_ADJ Mask */\r
+#define COMPARATOR_ANACMP1_REF_DIV_EN_Pos 6 /*!< COMPARATOR ANACMP1: REF_DIV_EN Position */\r
+#define COMPARATOR_ANACMP1_REF_DIV_EN_Msk (0x01UL << COMPARATOR_ANACMP1_REF_DIV_EN_Pos) /*!< COMPARATOR ANACMP1: REF_DIV_EN Mask */\r
+#define COMPARATOR_ANACMP1_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP1: CMP_OUT Position */\r
+#define COMPARATOR_ANACMP1_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP1_CMP_OUT_Pos) /*!< COMPARATOR ANACMP1: CMP_OUT Mask */\r
+\r
+/* ----------------------------- COMPARATOR_ANACMP2 ----------------------------- */\r
+#define COMPARATOR_ANACMP2_CMP_EN_Pos 0 /*!< COMPARATOR ANACMP2: CMP_EN Position */\r
+#define COMPARATOR_ANACMP2_CMP_EN_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_EN_Pos) /*!< COMPARATOR ANACMP2: CMP_EN Mask */\r
+#define COMPARATOR_ANACMP2_CMP_FLT_OFF_Pos 1 /*!< COMPARATOR ANACMP2: CMP_FLT_OFF Position */\r
+#define COMPARATOR_ANACMP2_CMP_FLT_OFF_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_FLT_OFF_Pos) /*!< COMPARATOR ANACMP2: CMP_FLT_OFF Mask */\r
+#define COMPARATOR_ANACMP2_CMP_INV_OUT_Pos 3 /*!< COMPARATOR ANACMP2: CMP_INV_OUT Position */\r
+#define COMPARATOR_ANACMP2_CMP_INV_OUT_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_INV_OUT_Pos) /*!< COMPARATOR ANACMP2: CMP_INV_OUT Mask */\r
+#define COMPARATOR_ANACMP2_CMP_HYST_ADJ_Pos 4 /*!< COMPARATOR ANACMP2: CMP_HYST_ADJ Position */\r
+#define COMPARATOR_ANACMP2_CMP_HYST_ADJ_Msk (0x03UL << COMPARATOR_ANACMP2_CMP_HYST_ADJ_Pos) /*!< COMPARATOR ANACMP2: CMP_HYST_ADJ Mask */\r
+#define COMPARATOR_ANACMP2_ACMP2_SEL_Pos 6 /*!< COMPARATOR ANACMP2: ACMP2_SEL Position */\r
+#define COMPARATOR_ANACMP2_ACMP2_SEL_Msk (0x01UL << COMPARATOR_ANACMP2_ACMP2_SEL_Pos) /*!< COMPARATOR ANACMP2: ACMP2_SEL Mask */\r
+#define COMPARATOR_ANACMP2_CMP_OUT_Pos 15 /*!< COMPARATOR ANACMP2: CMP_OUT Position */\r
+#define COMPARATOR_ANACMP2_CMP_OUT_Msk (0x01UL << COMPARATOR_ANACMP2_CMP_OUT_Pos) /*!< COMPARATOR ANACMP2: CMP_OUT Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'SCU_ANALOG' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------- SCU_ANALOG_ANATSECTRL --------------------------- */\r
+#define SCU_ANALOG_ANATSECTRL_TSE_EN_Pos 0 /*!< SCU_ANALOG ANATSECTRL: TSE_EN Position */\r
+#define SCU_ANALOG_ANATSECTRL_TSE_EN_Msk (0x01UL << SCU_ANALOG_ANATSECTRL_TSE_EN_Pos) /*!< SCU_ANALOG ANATSECTRL: TSE_EN Mask */\r
+\r
+/* ----------------------------- SCU_ANALOG_ANATSEIH ---------------------------- */\r
+#define SCU_ANALOG_ANATSEIH_TSE_IH_Pos 0 /*!< SCU_ANALOG ANATSEIH: TSE_IH Position */\r
+#define SCU_ANALOG_ANATSEIH_TSE_IH_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEIH_TSE_IH_Pos) /*!< SCU_ANALOG ANATSEIH: TSE_IH Mask */\r
+\r
+/* ----------------------------- SCU_ANALOG_ANATSEIL ---------------------------- */\r
+#define SCU_ANALOG_ANATSEIL_TSE_IL_Pos 0 /*!< SCU_ANALOG ANATSEIL: TSE_IL Position */\r
+#define SCU_ANALOG_ANATSEIL_TSE_IL_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEIL_TSE_IL_Pos) /*!< SCU_ANALOG ANATSEIL: TSE_IL Mask */\r
+\r
+/* ---------------------------- SCU_ANALOG_ANATSEMON ---------------------------- */\r
+#define SCU_ANALOG_ANATSEMON_TSE_MON_Pos 0 /*!< SCU_ANALOG ANATSEMON: TSE_MON Position */\r
+#define SCU_ANALOG_ANATSEMON_TSE_MON_Msk (0x0000ffffUL << SCU_ANALOG_ANATSEMON_TSE_MON_Pos) /*!< SCU_ANALOG ANATSEMON: TSE_MON Mask */\r
+\r
+/* ----------------------------- SCU_ANALOG_ANAVDEL ----------------------------- */\r
+#define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos 0 /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Position */\r
+#define SCU_ANALOG_ANAVDEL_VDEL_SELECT_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_SELECT_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_SELECT Mask */\r
+#define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos 2 /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Position */\r
+#define SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Msk (0x03UL << SCU_ANALOG_ANAVDEL_VDEL_TIM_ADJ_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_TIM_ADJ Mask */\r
+#define SCU_ANALOG_ANAVDEL_VDEL_EN_Pos 4 /*!< SCU_ANALOG ANAVDEL: VDEL_EN Position */\r
+#define SCU_ANALOG_ANAVDEL_VDEL_EN_Msk (0x01UL << SCU_ANALOG_ANAVDEL_VDEL_EN_Pos) /*!< SCU_ANALOG ANAVDEL: VDEL_EN Mask */\r
+\r
+/* ---------------------------- SCU_ANALOG_ANAOFFSET ---------------------------- */\r
+#define SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Pos 0 /*!< SCU_ANALOG ANAOFFSET: ADJL_OFFSET Position */\r
+#define SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Msk (0x0fUL << SCU_ANALOG_ANAOFFSET_ADJL_OFFSET_Pos) /*!< SCU_ANALOG ANAOFFSET: ADJL_OFFSET Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'CCU4' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- CCU4_GCTRL --------------------------------- */\r
+#define CCU4_GCTRL_PRBC_Pos 0 /*!< CCU4 GCTRL: PRBC Position */\r
+#define CCU4_GCTRL_PRBC_Msk (0x07UL << CCU4_GCTRL_PRBC_Pos) /*!< CCU4 GCTRL: PRBC Mask */\r
+#define CCU4_GCTRL_PCIS_Pos 4 /*!< CCU4 GCTRL: PCIS Position */\r
+#define CCU4_GCTRL_PCIS_Msk (0x03UL << CCU4_GCTRL_PCIS_Pos) /*!< CCU4 GCTRL: PCIS Mask */\r
+#define CCU4_GCTRL_SUSCFG_Pos 8 /*!< CCU4 GCTRL: SUSCFG Position */\r
+#define CCU4_GCTRL_SUSCFG_Msk (0x03UL << CCU4_GCTRL_SUSCFG_Pos) /*!< CCU4 GCTRL: SUSCFG Mask */\r
+#define CCU4_GCTRL_MSE0_Pos 10 /*!< CCU4 GCTRL: MSE0 Position */\r
+#define CCU4_GCTRL_MSE0_Msk (0x01UL << CCU4_GCTRL_MSE0_Pos) /*!< CCU4 GCTRL: MSE0 Mask */\r
+#define CCU4_GCTRL_MSE1_Pos 11 /*!< CCU4 GCTRL: MSE1 Position */\r
+#define CCU4_GCTRL_MSE1_Msk (0x01UL << CCU4_GCTRL_MSE1_Pos) /*!< CCU4 GCTRL: MSE1 Mask */\r
+#define CCU4_GCTRL_MSE2_Pos 12 /*!< CCU4 GCTRL: MSE2 Position */\r
+#define CCU4_GCTRL_MSE2_Msk (0x01UL << CCU4_GCTRL_MSE2_Pos) /*!< CCU4 GCTRL: MSE2 Mask */\r
+#define CCU4_GCTRL_MSE3_Pos 13 /*!< CCU4 GCTRL: MSE3 Position */\r
+#define CCU4_GCTRL_MSE3_Msk (0x01UL << CCU4_GCTRL_MSE3_Pos) /*!< CCU4 GCTRL: MSE3 Mask */\r
+#define CCU4_GCTRL_MSDE_Pos 14 /*!< CCU4 GCTRL: MSDE Position */\r
+#define CCU4_GCTRL_MSDE_Msk (0x03UL << CCU4_GCTRL_MSDE_Pos) /*!< CCU4 GCTRL: MSDE Mask */\r
+\r
+/* --------------------------------- CCU4_GSTAT --------------------------------- */\r
+#define CCU4_GSTAT_S0I_Pos 0 /*!< CCU4 GSTAT: S0I Position */\r
+#define CCU4_GSTAT_S0I_Msk (0x01UL << CCU4_GSTAT_S0I_Pos) /*!< CCU4 GSTAT: S0I Mask */\r
+#define CCU4_GSTAT_S1I_Pos 1 /*!< CCU4 GSTAT: S1I Position */\r
+#define CCU4_GSTAT_S1I_Msk (0x01UL << CCU4_GSTAT_S1I_Pos) /*!< CCU4 GSTAT: S1I Mask */\r
+#define CCU4_GSTAT_S2I_Pos 2 /*!< CCU4 GSTAT: S2I Position */\r
+#define CCU4_GSTAT_S2I_Msk (0x01UL << CCU4_GSTAT_S2I_Pos) /*!< CCU4 GSTAT: S2I Mask */\r
+#define CCU4_GSTAT_S3I_Pos 3 /*!< CCU4 GSTAT: S3I Position */\r
+#define CCU4_GSTAT_S3I_Msk (0x01UL << CCU4_GSTAT_S3I_Pos) /*!< CCU4 GSTAT: S3I Mask */\r
+#define CCU4_GSTAT_PRB_Pos 8 /*!< CCU4 GSTAT: PRB Position */\r
+#define CCU4_GSTAT_PRB_Msk (0x01UL << CCU4_GSTAT_PRB_Pos) /*!< CCU4 GSTAT: PRB Mask */\r
+\r
+/* --------------------------------- CCU4_GIDLS --------------------------------- */\r
+#define CCU4_GIDLS_SS0I_Pos 0 /*!< CCU4 GIDLS: SS0I Position */\r
+#define CCU4_GIDLS_SS0I_Msk (0x01UL << CCU4_GIDLS_SS0I_Pos) /*!< CCU4 GIDLS: SS0I Mask */\r
+#define CCU4_GIDLS_SS1I_Pos 1 /*!< CCU4 GIDLS: SS1I Position */\r
+#define CCU4_GIDLS_SS1I_Msk (0x01UL << CCU4_GIDLS_SS1I_Pos) /*!< CCU4 GIDLS: SS1I Mask */\r
+#define CCU4_GIDLS_SS2I_Pos 2 /*!< CCU4 GIDLS: SS2I Position */\r
+#define CCU4_GIDLS_SS2I_Msk (0x01UL << CCU4_GIDLS_SS2I_Pos) /*!< CCU4 GIDLS: SS2I Mask */\r
+#define CCU4_GIDLS_SS3I_Pos 3 /*!< CCU4 GIDLS: SS3I Position */\r
+#define CCU4_GIDLS_SS3I_Msk (0x01UL << CCU4_GIDLS_SS3I_Pos) /*!< CCU4 GIDLS: SS3I Mask */\r
+#define CCU4_GIDLS_CPRB_Pos 8 /*!< CCU4 GIDLS: CPRB Position */\r
+#define CCU4_GIDLS_CPRB_Msk (0x01UL << CCU4_GIDLS_CPRB_Pos) /*!< CCU4 GIDLS: CPRB Mask */\r
+#define CCU4_GIDLS_PSIC_Pos 9 /*!< CCU4 GIDLS: PSIC Position */\r
+#define CCU4_GIDLS_PSIC_Msk (0x01UL << CCU4_GIDLS_PSIC_Pos) /*!< CCU4 GIDLS: PSIC Mask */\r
+\r
+/* --------------------------------- CCU4_GIDLC --------------------------------- */\r
+#define CCU4_GIDLC_CS0I_Pos 0 /*!< CCU4 GIDLC: CS0I Position */\r
+#define CCU4_GIDLC_CS0I_Msk (0x01UL << CCU4_GIDLC_CS0I_Pos) /*!< CCU4 GIDLC: CS0I Mask */\r
+#define CCU4_GIDLC_CS1I_Pos 1 /*!< CCU4 GIDLC: CS1I Position */\r
+#define CCU4_GIDLC_CS1I_Msk (0x01UL << CCU4_GIDLC_CS1I_Pos) /*!< CCU4 GIDLC: CS1I Mask */\r
+#define CCU4_GIDLC_CS2I_Pos 2 /*!< CCU4 GIDLC: CS2I Position */\r
+#define CCU4_GIDLC_CS2I_Msk (0x01UL << CCU4_GIDLC_CS2I_Pos) /*!< CCU4 GIDLC: CS2I Mask */\r
+#define CCU4_GIDLC_CS3I_Pos 3 /*!< CCU4 GIDLC: CS3I Position */\r
+#define CCU4_GIDLC_CS3I_Msk (0x01UL << CCU4_GIDLC_CS3I_Pos) /*!< CCU4 GIDLC: CS3I Mask */\r
+#define CCU4_GIDLC_SPRB_Pos 8 /*!< CCU4 GIDLC: SPRB Position */\r
+#define CCU4_GIDLC_SPRB_Msk (0x01UL << CCU4_GIDLC_SPRB_Pos) /*!< CCU4 GIDLC: SPRB Mask */\r
+\r
+/* ---------------------------------- CCU4_GCSS --------------------------------- */\r
+#define CCU4_GCSS_S0SE_Pos 0 /*!< CCU4 GCSS: S0SE Position */\r
+#define CCU4_GCSS_S0SE_Msk (0x01UL << CCU4_GCSS_S0SE_Pos) /*!< CCU4 GCSS: S0SE Mask */\r
+#define CCU4_GCSS_S0DSE_Pos 1 /*!< CCU4 GCSS: S0DSE Position */\r
+#define CCU4_GCSS_S0DSE_Msk (0x01UL << CCU4_GCSS_S0DSE_Pos) /*!< CCU4 GCSS: S0DSE Mask */\r
+#define CCU4_GCSS_S0PSE_Pos 2 /*!< CCU4 GCSS: S0PSE Position */\r
+#define CCU4_GCSS_S0PSE_Msk (0x01UL << CCU4_GCSS_S0PSE_Pos) /*!< CCU4 GCSS: S0PSE Mask */\r
+#define CCU4_GCSS_S1SE_Pos 4 /*!< CCU4 GCSS: S1SE Position */\r
+#define CCU4_GCSS_S1SE_Msk (0x01UL << CCU4_GCSS_S1SE_Pos) /*!< CCU4 GCSS: S1SE Mask */\r
+#define CCU4_GCSS_S1DSE_Pos 5 /*!< CCU4 GCSS: S1DSE Position */\r
+#define CCU4_GCSS_S1DSE_Msk (0x01UL << CCU4_GCSS_S1DSE_Pos) /*!< CCU4 GCSS: S1DSE Mask */\r
+#define CCU4_GCSS_S1PSE_Pos 6 /*!< CCU4 GCSS: S1PSE Position */\r
+#define CCU4_GCSS_S1PSE_Msk (0x01UL << CCU4_GCSS_S1PSE_Pos) /*!< CCU4 GCSS: S1PSE Mask */\r
+#define CCU4_GCSS_S2SE_Pos 8 /*!< CCU4 GCSS: S2SE Position */\r
+#define CCU4_GCSS_S2SE_Msk (0x01UL << CCU4_GCSS_S2SE_Pos) /*!< CCU4 GCSS: S2SE Mask */\r
+#define CCU4_GCSS_S2DSE_Pos 9 /*!< CCU4 GCSS: S2DSE Position */\r
+#define CCU4_GCSS_S2DSE_Msk (0x01UL << CCU4_GCSS_S2DSE_Pos) /*!< CCU4 GCSS: S2DSE Mask */\r
+#define CCU4_GCSS_S2PSE_Pos 10 /*!< CCU4 GCSS: S2PSE Position */\r
+#define CCU4_GCSS_S2PSE_Msk (0x01UL << CCU4_GCSS_S2PSE_Pos) /*!< CCU4 GCSS: S2PSE Mask */\r
+#define CCU4_GCSS_S3SE_Pos 12 /*!< CCU4 GCSS: S3SE Position */\r
+#define CCU4_GCSS_S3SE_Msk (0x01UL << CCU4_GCSS_S3SE_Pos) /*!< CCU4 GCSS: S3SE Mask */\r
+#define CCU4_GCSS_S3DSE_Pos 13 /*!< CCU4 GCSS: S3DSE Position */\r
+#define CCU4_GCSS_S3DSE_Msk (0x01UL << CCU4_GCSS_S3DSE_Pos) /*!< CCU4 GCSS: S3DSE Mask */\r
+#define CCU4_GCSS_S3PSE_Pos 14 /*!< CCU4 GCSS: S3PSE Position */\r
+#define CCU4_GCSS_S3PSE_Msk (0x01UL << CCU4_GCSS_S3PSE_Pos) /*!< CCU4 GCSS: S3PSE Mask */\r
+#define CCU4_GCSS_S0STS_Pos 16 /*!< CCU4 GCSS: S0STS Position */\r
+#define CCU4_GCSS_S0STS_Msk (0x01UL << CCU4_GCSS_S0STS_Pos) /*!< CCU4 GCSS: S0STS Mask */\r
+#define CCU4_GCSS_S1STS_Pos 17 /*!< CCU4 GCSS: S1STS Position */\r
+#define CCU4_GCSS_S1STS_Msk (0x01UL << CCU4_GCSS_S1STS_Pos) /*!< CCU4 GCSS: S1STS Mask */\r
+#define CCU4_GCSS_S2STS_Pos 18 /*!< CCU4 GCSS: S2STS Position */\r
+#define CCU4_GCSS_S2STS_Msk (0x01UL << CCU4_GCSS_S2STS_Pos) /*!< CCU4 GCSS: S2STS Mask */\r
+#define CCU4_GCSS_S3STS_Pos 19 /*!< CCU4 GCSS: S3STS Position */\r
+#define CCU4_GCSS_S3STS_Msk (0x01UL << CCU4_GCSS_S3STS_Pos) /*!< CCU4 GCSS: S3STS Mask */\r
+\r
+/* ---------------------------------- CCU4_GCSC --------------------------------- */\r
+#define CCU4_GCSC_S0SC_Pos 0 /*!< CCU4 GCSC: S0SC Position */\r
+#define CCU4_GCSC_S0SC_Msk (0x01UL << CCU4_GCSC_S0SC_Pos) /*!< CCU4 GCSC: S0SC Mask */\r
+#define CCU4_GCSC_S0DSC_Pos 1 /*!< CCU4 GCSC: S0DSC Position */\r
+#define CCU4_GCSC_S0DSC_Msk (0x01UL << CCU4_GCSC_S0DSC_Pos) /*!< CCU4 GCSC: S0DSC Mask */\r
+#define CCU4_GCSC_S0PSC_Pos 2 /*!< CCU4 GCSC: S0PSC Position */\r
+#define CCU4_GCSC_S0PSC_Msk (0x01UL << CCU4_GCSC_S0PSC_Pos) /*!< CCU4 GCSC: S0PSC Mask */\r
+#define CCU4_GCSC_S1SC_Pos 4 /*!< CCU4 GCSC: S1SC Position */\r
+#define CCU4_GCSC_S1SC_Msk (0x01UL << CCU4_GCSC_S1SC_Pos) /*!< CCU4 GCSC: S1SC Mask */\r
+#define CCU4_GCSC_S1DSC_Pos 5 /*!< CCU4 GCSC: S1DSC Position */\r
+#define CCU4_GCSC_S1DSC_Msk (0x01UL << CCU4_GCSC_S1DSC_Pos) /*!< CCU4 GCSC: S1DSC Mask */\r
+#define CCU4_GCSC_S1PSC_Pos 6 /*!< CCU4 GCSC: S1PSC Position */\r
+#define CCU4_GCSC_S1PSC_Msk (0x01UL << CCU4_GCSC_S1PSC_Pos) /*!< CCU4 GCSC: S1PSC Mask */\r
+#define CCU4_GCSC_S2SC_Pos 8 /*!< CCU4 GCSC: S2SC Position */\r
+#define CCU4_GCSC_S2SC_Msk (0x01UL << CCU4_GCSC_S2SC_Pos) /*!< CCU4 GCSC: S2SC Mask */\r
+#define CCU4_GCSC_S2DSC_Pos 9 /*!< CCU4 GCSC: S2DSC Position */\r
+#define CCU4_GCSC_S2DSC_Msk (0x01UL << CCU4_GCSC_S2DSC_Pos) /*!< CCU4 GCSC: S2DSC Mask */\r
+#define CCU4_GCSC_S2PSC_Pos 10 /*!< CCU4 GCSC: S2PSC Position */\r
+#define CCU4_GCSC_S2PSC_Msk (0x01UL << CCU4_GCSC_S2PSC_Pos) /*!< CCU4 GCSC: S2PSC Mask */\r
+#define CCU4_GCSC_S3SC_Pos 12 /*!< CCU4 GCSC: S3SC Position */\r
+#define CCU4_GCSC_S3SC_Msk (0x01UL << CCU4_GCSC_S3SC_Pos) /*!< CCU4 GCSC: S3SC Mask */\r
+#define CCU4_GCSC_S3DSC_Pos 13 /*!< CCU4 GCSC: S3DSC Position */\r
+#define CCU4_GCSC_S3DSC_Msk (0x01UL << CCU4_GCSC_S3DSC_Pos) /*!< CCU4 GCSC: S3DSC Mask */\r
+#define CCU4_GCSC_S3PSC_Pos 14 /*!< CCU4 GCSC: S3PSC Position */\r
+#define CCU4_GCSC_S3PSC_Msk (0x01UL << CCU4_GCSC_S3PSC_Pos) /*!< CCU4 GCSC: S3PSC Mask */\r
+#define CCU4_GCSC_S0STC_Pos 16 /*!< CCU4 GCSC: S0STC Position */\r
+#define CCU4_GCSC_S0STC_Msk (0x01UL << CCU4_GCSC_S0STC_Pos) /*!< CCU4 GCSC: S0STC Mask */\r
+#define CCU4_GCSC_S1STC_Pos 17 /*!< CCU4 GCSC: S1STC Position */\r
+#define CCU4_GCSC_S1STC_Msk (0x01UL << CCU4_GCSC_S1STC_Pos) /*!< CCU4 GCSC: S1STC Mask */\r
+#define CCU4_GCSC_S2STC_Pos 18 /*!< CCU4 GCSC: S2STC Position */\r
+#define CCU4_GCSC_S2STC_Msk (0x01UL << CCU4_GCSC_S2STC_Pos) /*!< CCU4 GCSC: S2STC Mask */\r
+#define CCU4_GCSC_S3STC_Pos 19 /*!< CCU4 GCSC: S3STC Position */\r
+#define CCU4_GCSC_S3STC_Msk (0x01UL << CCU4_GCSC_S3STC_Pos) /*!< CCU4 GCSC: S3STC Mask */\r
+\r
+/* ---------------------------------- CCU4_GCST --------------------------------- */\r
+#define CCU4_GCST_S0SS_Pos 0 /*!< CCU4 GCST: S0SS Position */\r
+#define CCU4_GCST_S0SS_Msk (0x01UL << CCU4_GCST_S0SS_Pos) /*!< CCU4 GCST: S0SS Mask */\r
+#define CCU4_GCST_S0DSS_Pos 1 /*!< CCU4 GCST: S0DSS Position */\r
+#define CCU4_GCST_S0DSS_Msk (0x01UL << CCU4_GCST_S0DSS_Pos) /*!< CCU4 GCST: S0DSS Mask */\r
+#define CCU4_GCST_S0PSS_Pos 2 /*!< CCU4 GCST: S0PSS Position */\r
+#define CCU4_GCST_S0PSS_Msk (0x01UL << CCU4_GCST_S0PSS_Pos) /*!< CCU4 GCST: S0PSS Mask */\r
+#define CCU4_GCST_S1SS_Pos 4 /*!< CCU4 GCST: S1SS Position */\r
+#define CCU4_GCST_S1SS_Msk (0x01UL << CCU4_GCST_S1SS_Pos) /*!< CCU4 GCST: S1SS Mask */\r
+#define CCU4_GCST_S1DSS_Pos 5 /*!< CCU4 GCST: S1DSS Position */\r
+#define CCU4_GCST_S1DSS_Msk (0x01UL << CCU4_GCST_S1DSS_Pos) /*!< CCU4 GCST: S1DSS Mask */\r
+#define CCU4_GCST_S1PSS_Pos 6 /*!< CCU4 GCST: S1PSS Position */\r
+#define CCU4_GCST_S1PSS_Msk (0x01UL << CCU4_GCST_S1PSS_Pos) /*!< CCU4 GCST: S1PSS Mask */\r
+#define CCU4_GCST_S2SS_Pos 8 /*!< CCU4 GCST: S2SS Position */\r
+#define CCU4_GCST_S2SS_Msk (0x01UL << CCU4_GCST_S2SS_Pos) /*!< CCU4 GCST: S2SS Mask */\r
+#define CCU4_GCST_S2DSS_Pos 9 /*!< CCU4 GCST: S2DSS Position */\r
+#define CCU4_GCST_S2DSS_Msk (0x01UL << CCU4_GCST_S2DSS_Pos) /*!< CCU4 GCST: S2DSS Mask */\r
+#define CCU4_GCST_S2PSS_Pos 10 /*!< CCU4 GCST: S2PSS Position */\r
+#define CCU4_GCST_S2PSS_Msk (0x01UL << CCU4_GCST_S2PSS_Pos) /*!< CCU4 GCST: S2PSS Mask */\r
+#define CCU4_GCST_S3SS_Pos 12 /*!< CCU4 GCST: S3SS Position */\r
+#define CCU4_GCST_S3SS_Msk (0x01UL << CCU4_GCST_S3SS_Pos) /*!< CCU4 GCST: S3SS Mask */\r
+#define CCU4_GCST_S3DSS_Pos 13 /*!< CCU4 GCST: S3DSS Position */\r
+#define CCU4_GCST_S3DSS_Msk (0x01UL << CCU4_GCST_S3DSS_Pos) /*!< CCU4 GCST: S3DSS Mask */\r
+#define CCU4_GCST_S3PSS_Pos 14 /*!< CCU4 GCST: S3PSS Position */\r
+#define CCU4_GCST_S3PSS_Msk (0x01UL << CCU4_GCST_S3PSS_Pos) /*!< CCU4 GCST: S3PSS Mask */\r
+#define CCU4_GCST_CC40ST_Pos 16 /*!< CCU4 GCST: CC40ST Position */\r
+#define CCU4_GCST_CC40ST_Msk (0x01UL << CCU4_GCST_CC40ST_Pos) /*!< CCU4 GCST: CC40ST Mask */\r
+#define CCU4_GCST_CC41ST_Pos 17 /*!< CCU4 GCST: CC41ST Position */\r
+#define CCU4_GCST_CC41ST_Msk (0x01UL << CCU4_GCST_CC41ST_Pos) /*!< CCU4 GCST: CC41ST Mask */\r
+#define CCU4_GCST_CC42ST_Pos 18 /*!< CCU4 GCST: CC42ST Position */\r
+#define CCU4_GCST_CC42ST_Msk (0x01UL << CCU4_GCST_CC42ST_Pos) /*!< CCU4 GCST: CC42ST Mask */\r
+#define CCU4_GCST_CC43ST_Pos 19 /*!< CCU4 GCST: CC43ST Position */\r
+#define CCU4_GCST_CC43ST_Msk (0x01UL << CCU4_GCST_CC43ST_Pos) /*!< CCU4 GCST: CC43ST Mask */\r
+\r
+/* ---------------------------------- CCU4_MIDR --------------------------------- */\r
+#define CCU4_MIDR_MODR_Pos 0 /*!< CCU4 MIDR: MODR Position */\r
+#define CCU4_MIDR_MODR_Msk (0x000000ffUL << CCU4_MIDR_MODR_Pos) /*!< CCU4 MIDR: MODR Mask */\r
+#define CCU4_MIDR_MODT_Pos 8 /*!< CCU4 MIDR: MODT Position */\r
+#define CCU4_MIDR_MODT_Msk (0x000000ffUL << CCU4_MIDR_MODT_Pos) /*!< CCU4 MIDR: MODT Mask */\r
+#define CCU4_MIDR_MODN_Pos 16 /*!< CCU4 MIDR: MODN Position */\r
+#define CCU4_MIDR_MODN_Msk (0x0000ffffUL << CCU4_MIDR_MODN_Pos) /*!< CCU4 MIDR: MODN Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'CCU4_CC4' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- CCU4_CC4_INS -------------------------------- */\r
+#define CCU4_CC4_INS_EV0IS_Pos 0 /*!< CCU4_CC4 INS: EV0IS Position */\r
+#define CCU4_CC4_INS_EV0IS_Msk (0x0fUL << CCU4_CC4_INS_EV0IS_Pos) /*!< CCU4_CC4 INS: EV0IS Mask */\r
+#define CCU4_CC4_INS_EV1IS_Pos 4 /*!< CCU4_CC4 INS: EV1IS Position */\r
+#define CCU4_CC4_INS_EV1IS_Msk (0x0fUL << CCU4_CC4_INS_EV1IS_Pos) /*!< CCU4_CC4 INS: EV1IS Mask */\r
+#define CCU4_CC4_INS_EV2IS_Pos 8 /*!< CCU4_CC4 INS: EV2IS Position */\r
+#define CCU4_CC4_INS_EV2IS_Msk (0x0fUL << CCU4_CC4_INS_EV2IS_Pos) /*!< CCU4_CC4 INS: EV2IS Mask */\r
+#define CCU4_CC4_INS_EV0EM_Pos 16 /*!< CCU4_CC4 INS: EV0EM Position */\r
+#define CCU4_CC4_INS_EV0EM_Msk (0x03UL << CCU4_CC4_INS_EV0EM_Pos) /*!< CCU4_CC4 INS: EV0EM Mask */\r
+#define CCU4_CC4_INS_EV1EM_Pos 18 /*!< CCU4_CC4 INS: EV1EM Position */\r
+#define CCU4_CC4_INS_EV1EM_Msk (0x03UL << CCU4_CC4_INS_EV1EM_Pos) /*!< CCU4_CC4 INS: EV1EM Mask */\r
+#define CCU4_CC4_INS_EV2EM_Pos 20 /*!< CCU4_CC4 INS: EV2EM Position */\r
+#define CCU4_CC4_INS_EV2EM_Msk (0x03UL << CCU4_CC4_INS_EV2EM_Pos) /*!< CCU4_CC4 INS: EV2EM Mask */\r
+#define CCU4_CC4_INS_EV0LM_Pos 22 /*!< CCU4_CC4 INS: EV0LM Position */\r
+#define CCU4_CC4_INS_EV0LM_Msk (0x01UL << CCU4_CC4_INS_EV0LM_Pos) /*!< CCU4_CC4 INS: EV0LM Mask */\r
+#define CCU4_CC4_INS_EV1LM_Pos 23 /*!< CCU4_CC4 INS: EV1LM Position */\r
+#define CCU4_CC4_INS_EV1LM_Msk (0x01UL << CCU4_CC4_INS_EV1LM_Pos) /*!< CCU4_CC4 INS: EV1LM Mask */\r
+#define CCU4_CC4_INS_EV2LM_Pos 24 /*!< CCU4_CC4 INS: EV2LM Position */\r
+#define CCU4_CC4_INS_EV2LM_Msk (0x01UL << CCU4_CC4_INS_EV2LM_Pos) /*!< CCU4_CC4 INS: EV2LM Mask */\r
+#define CCU4_CC4_INS_LPF0M_Pos 25 /*!< CCU4_CC4 INS: LPF0M Position */\r
+#define CCU4_CC4_INS_LPF0M_Msk (0x03UL << CCU4_CC4_INS_LPF0M_Pos) /*!< CCU4_CC4 INS: LPF0M Mask */\r
+#define CCU4_CC4_INS_LPF1M_Pos 27 /*!< CCU4_CC4 INS: LPF1M Position */\r
+#define CCU4_CC4_INS_LPF1M_Msk (0x03UL << CCU4_CC4_INS_LPF1M_Pos) /*!< CCU4_CC4 INS: LPF1M Mask */\r
+#define CCU4_CC4_INS_LPF2M_Pos 29 /*!< CCU4_CC4 INS: LPF2M Position */\r
+#define CCU4_CC4_INS_LPF2M_Msk (0x03UL << CCU4_CC4_INS_LPF2M_Pos) /*!< CCU4_CC4 INS: LPF2M Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_CMC -------------------------------- */\r
+#define CCU4_CC4_CMC_STRTS_Pos 0 /*!< CCU4_CC4 CMC: STRTS Position */\r
+#define CCU4_CC4_CMC_STRTS_Msk (0x03UL << CCU4_CC4_CMC_STRTS_Pos) /*!< CCU4_CC4 CMC: STRTS Mask */\r
+#define CCU4_CC4_CMC_ENDS_Pos 2 /*!< CCU4_CC4 CMC: ENDS Position */\r
+#define CCU4_CC4_CMC_ENDS_Msk (0x03UL << CCU4_CC4_CMC_ENDS_Pos) /*!< CCU4_CC4 CMC: ENDS Mask */\r
+#define CCU4_CC4_CMC_CAP0S_Pos 4 /*!< CCU4_CC4 CMC: CAP0S Position */\r
+#define CCU4_CC4_CMC_CAP0S_Msk (0x03UL << CCU4_CC4_CMC_CAP0S_Pos) /*!< CCU4_CC4 CMC: CAP0S Mask */\r
+#define CCU4_CC4_CMC_CAP1S_Pos 6 /*!< CCU4_CC4 CMC: CAP1S Position */\r
+#define CCU4_CC4_CMC_CAP1S_Msk (0x03UL << CCU4_CC4_CMC_CAP1S_Pos) /*!< CCU4_CC4 CMC: CAP1S Mask */\r
+#define CCU4_CC4_CMC_GATES_Pos 8 /*!< CCU4_CC4 CMC: GATES Position */\r
+#define CCU4_CC4_CMC_GATES_Msk (0x03UL << CCU4_CC4_CMC_GATES_Pos) /*!< CCU4_CC4 CMC: GATES Mask */\r
+#define CCU4_CC4_CMC_UDS_Pos 10 /*!< CCU4_CC4 CMC: UDS Position */\r
+#define CCU4_CC4_CMC_UDS_Msk (0x03UL << CCU4_CC4_CMC_UDS_Pos) /*!< CCU4_CC4 CMC: UDS Mask */\r
+#define CCU4_CC4_CMC_LDS_Pos 12 /*!< CCU4_CC4 CMC: LDS Position */\r
+#define CCU4_CC4_CMC_LDS_Msk (0x03UL << CCU4_CC4_CMC_LDS_Pos) /*!< CCU4_CC4 CMC: LDS Mask */\r
+#define CCU4_CC4_CMC_CNTS_Pos 14 /*!< CCU4_CC4 CMC: CNTS Position */\r
+#define CCU4_CC4_CMC_CNTS_Msk (0x03UL << CCU4_CC4_CMC_CNTS_Pos) /*!< CCU4_CC4 CMC: CNTS Mask */\r
+#define CCU4_CC4_CMC_OFS_Pos 16 /*!< CCU4_CC4 CMC: OFS Position */\r
+#define CCU4_CC4_CMC_OFS_Msk (0x01UL << CCU4_CC4_CMC_OFS_Pos) /*!< CCU4_CC4 CMC: OFS Mask */\r
+#define CCU4_CC4_CMC_TS_Pos 17 /*!< CCU4_CC4 CMC: TS Position */\r
+#define CCU4_CC4_CMC_TS_Msk (0x01UL << CCU4_CC4_CMC_TS_Pos) /*!< CCU4_CC4 CMC: TS Mask */\r
+#define CCU4_CC4_CMC_MOS_Pos 18 /*!< CCU4_CC4 CMC: MOS Position */\r
+#define CCU4_CC4_CMC_MOS_Msk (0x03UL << CCU4_CC4_CMC_MOS_Pos) /*!< CCU4_CC4 CMC: MOS Mask */\r
+#define CCU4_CC4_CMC_TCE_Pos 20 /*!< CCU4_CC4 CMC: TCE Position */\r
+#define CCU4_CC4_CMC_TCE_Msk (0x01UL << CCU4_CC4_CMC_TCE_Pos) /*!< CCU4_CC4 CMC: TCE Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_TCST ------------------------------- */\r
+#define CCU4_CC4_TCST_TRB_Pos 0 /*!< CCU4_CC4 TCST: TRB Position */\r
+#define CCU4_CC4_TCST_TRB_Msk (0x01UL << CCU4_CC4_TCST_TRB_Pos) /*!< CCU4_CC4 TCST: TRB Mask */\r
+#define CCU4_CC4_TCST_CDIR_Pos 1 /*!< CCU4_CC4 TCST: CDIR Position */\r
+#define CCU4_CC4_TCST_CDIR_Msk (0x01UL << CCU4_CC4_TCST_CDIR_Pos) /*!< CCU4_CC4 TCST: CDIR Mask */\r
+\r
+/* ------------------------------- CCU4_CC4_TCSET ------------------------------- */\r
+#define CCU4_CC4_TCSET_TRBS_Pos 0 /*!< CCU4_CC4 TCSET: TRBS Position */\r
+#define CCU4_CC4_TCSET_TRBS_Msk (0x01UL << CCU4_CC4_TCSET_TRBS_Pos) /*!< CCU4_CC4 TCSET: TRBS Mask */\r
+\r
+/* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */\r
+#define CCU4_CC4_TCCLR_TRBC_Pos 0 /*!< CCU4_CC4 TCCLR: TRBC Position */\r
+#define CCU4_CC4_TCCLR_TRBC_Msk (0x01UL << CCU4_CC4_TCCLR_TRBC_Pos) /*!< CCU4_CC4 TCCLR: TRBC Mask */\r
+#define CCU4_CC4_TCCLR_TCC_Pos 1 /*!< CCU4_CC4 TCCLR: TCC Position */\r
+#define CCU4_CC4_TCCLR_TCC_Msk (0x01UL << CCU4_CC4_TCCLR_TCC_Pos) /*!< CCU4_CC4 TCCLR: TCC Mask */\r
+#define CCU4_CC4_TCCLR_DITC_Pos 2 /*!< CCU4_CC4 TCCLR: DITC Position */\r
+#define CCU4_CC4_TCCLR_DITC_Msk (0x01UL << CCU4_CC4_TCCLR_DITC_Pos) /*!< CCU4_CC4 TCCLR: DITC Mask */\r
+\r
+/* --------------------------------- CCU4_CC4_TC -------------------------------- */\r
+#define CCU4_CC4_TC_TCM_Pos 0 /*!< CCU4_CC4 TC: TCM Position */\r
+#define CCU4_CC4_TC_TCM_Msk (0x01UL << CCU4_CC4_TC_TCM_Pos) /*!< CCU4_CC4 TC: TCM Mask */\r
+#define CCU4_CC4_TC_TSSM_Pos 1 /*!< CCU4_CC4 TC: TSSM Position */\r
+#define CCU4_CC4_TC_TSSM_Msk (0x01UL << CCU4_CC4_TC_TSSM_Pos) /*!< CCU4_CC4 TC: TSSM Mask */\r
+#define CCU4_CC4_TC_CLST_Pos 2 /*!< CCU4_CC4 TC: CLST Position */\r
+#define CCU4_CC4_TC_CLST_Msk (0x01UL << CCU4_CC4_TC_CLST_Pos) /*!< CCU4_CC4 TC: CLST Mask */\r
+#define CCU4_CC4_TC_CMOD_Pos 3 /*!< CCU4_CC4 TC: CMOD Position */\r
+#define CCU4_CC4_TC_CMOD_Msk (0x01UL << CCU4_CC4_TC_CMOD_Pos) /*!< CCU4_CC4 TC: CMOD Mask */\r
+#define CCU4_CC4_TC_ECM_Pos 4 /*!< CCU4_CC4 TC: ECM Position */\r
+#define CCU4_CC4_TC_ECM_Msk (0x01UL << CCU4_CC4_TC_ECM_Pos) /*!< CCU4_CC4 TC: ECM Mask */\r
+#define CCU4_CC4_TC_CAPC_Pos 5 /*!< CCU4_CC4 TC: CAPC Position */\r
+#define CCU4_CC4_TC_CAPC_Msk (0x03UL << CCU4_CC4_TC_CAPC_Pos) /*!< CCU4_CC4 TC: CAPC Mask */\r
+#define CCU4_CC4_TC_ENDM_Pos 8 /*!< CCU4_CC4 TC: ENDM Position */\r
+#define CCU4_CC4_TC_ENDM_Msk (0x03UL << CCU4_CC4_TC_ENDM_Pos) /*!< CCU4_CC4 TC: ENDM Mask */\r
+#define CCU4_CC4_TC_STRM_Pos 10 /*!< CCU4_CC4 TC: STRM Position */\r
+#define CCU4_CC4_TC_STRM_Msk (0x01UL << CCU4_CC4_TC_STRM_Pos) /*!< CCU4_CC4 TC: STRM Mask */\r
+#define CCU4_CC4_TC_SCE_Pos 11 /*!< CCU4_CC4 TC: SCE Position */\r
+#define CCU4_CC4_TC_SCE_Msk (0x01UL << CCU4_CC4_TC_SCE_Pos) /*!< CCU4_CC4 TC: SCE Mask */\r
+#define CCU4_CC4_TC_CCS_Pos 12 /*!< CCU4_CC4 TC: CCS Position */\r
+#define CCU4_CC4_TC_CCS_Msk (0x01UL << CCU4_CC4_TC_CCS_Pos) /*!< CCU4_CC4 TC: CCS Mask */\r
+#define CCU4_CC4_TC_DITHE_Pos 13 /*!< CCU4_CC4 TC: DITHE Position */\r
+#define CCU4_CC4_TC_DITHE_Msk (0x03UL << CCU4_CC4_TC_DITHE_Pos) /*!< CCU4_CC4 TC: DITHE Mask */\r
+#define CCU4_CC4_TC_DIM_Pos 15 /*!< CCU4_CC4 TC: DIM Position */\r
+#define CCU4_CC4_TC_DIM_Msk (0x01UL << CCU4_CC4_TC_DIM_Pos) /*!< CCU4_CC4 TC: DIM Mask */\r
+#define CCU4_CC4_TC_FPE_Pos 16 /*!< CCU4_CC4 TC: FPE Position */\r
+#define CCU4_CC4_TC_FPE_Msk (0x01UL << CCU4_CC4_TC_FPE_Pos) /*!< CCU4_CC4 TC: FPE Mask */\r
+#define CCU4_CC4_TC_TRAPE_Pos 17 /*!< CCU4_CC4 TC: TRAPE Position */\r
+#define CCU4_CC4_TC_TRAPE_Msk (0x01UL << CCU4_CC4_TC_TRAPE_Pos) /*!< CCU4_CC4 TC: TRAPE Mask */\r
+#define CCU4_CC4_TC_TRPSE_Pos 21 /*!< CCU4_CC4 TC: TRPSE Position */\r
+#define CCU4_CC4_TC_TRPSE_Msk (0x01UL << CCU4_CC4_TC_TRPSE_Pos) /*!< CCU4_CC4 TC: TRPSE Mask */\r
+#define CCU4_CC4_TC_TRPSW_Pos 22 /*!< CCU4_CC4 TC: TRPSW Position */\r
+#define CCU4_CC4_TC_TRPSW_Msk (0x01UL << CCU4_CC4_TC_TRPSW_Pos) /*!< CCU4_CC4 TC: TRPSW Mask */\r
+#define CCU4_CC4_TC_EMS_Pos 23 /*!< CCU4_CC4 TC: EMS Position */\r
+#define CCU4_CC4_TC_EMS_Msk (0x01UL << CCU4_CC4_TC_EMS_Pos) /*!< CCU4_CC4 TC: EMS Mask */\r
+#define CCU4_CC4_TC_EMT_Pos 24 /*!< CCU4_CC4 TC: EMT Position */\r
+#define CCU4_CC4_TC_EMT_Msk (0x01UL << CCU4_CC4_TC_EMT_Pos) /*!< CCU4_CC4 TC: EMT Mask */\r
+#define CCU4_CC4_TC_MCME_Pos 25 /*!< CCU4_CC4 TC: MCME Position */\r
+#define CCU4_CC4_TC_MCME_Msk (0x01UL << CCU4_CC4_TC_MCME_Pos) /*!< CCU4_CC4 TC: MCME Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_PSL -------------------------------- */\r
+#define CCU4_CC4_PSL_PSL_Pos 0 /*!< CCU4_CC4 PSL: PSL Position */\r
+#define CCU4_CC4_PSL_PSL_Msk (0x01UL << CCU4_CC4_PSL_PSL_Pos) /*!< CCU4_CC4 PSL: PSL Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_DIT -------------------------------- */\r
+#define CCU4_CC4_DIT_DCV_Pos 0 /*!< CCU4_CC4 DIT: DCV Position */\r
+#define CCU4_CC4_DIT_DCV_Msk (0x0fUL << CCU4_CC4_DIT_DCV_Pos) /*!< CCU4_CC4 DIT: DCV Mask */\r
+#define CCU4_CC4_DIT_DCNT_Pos 8 /*!< CCU4_CC4 DIT: DCNT Position */\r
+#define CCU4_CC4_DIT_DCNT_Msk (0x0fUL << CCU4_CC4_DIT_DCNT_Pos) /*!< CCU4_CC4 DIT: DCNT Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_DITS ------------------------------- */\r
+#define CCU4_CC4_DITS_DCVS_Pos 0 /*!< CCU4_CC4 DITS: DCVS Position */\r
+#define CCU4_CC4_DITS_DCVS_Msk (0x0fUL << CCU4_CC4_DITS_DCVS_Pos) /*!< CCU4_CC4 DITS: DCVS Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_PSC -------------------------------- */\r
+#define CCU4_CC4_PSC_PSIV_Pos 0 /*!< CCU4_CC4 PSC: PSIV Position */\r
+#define CCU4_CC4_PSC_PSIV_Msk (0x0fUL << CCU4_CC4_PSC_PSIV_Pos) /*!< CCU4_CC4 PSC: PSIV Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_FPC -------------------------------- */\r
+#define CCU4_CC4_FPC_PCMP_Pos 0 /*!< CCU4_CC4 FPC: PCMP Position */\r
+#define CCU4_CC4_FPC_PCMP_Msk (0x0fUL << CCU4_CC4_FPC_PCMP_Pos) /*!< CCU4_CC4 FPC: PCMP Mask */\r
+#define CCU4_CC4_FPC_PVAL_Pos 8 /*!< CCU4_CC4 FPC: PVAL Position */\r
+#define CCU4_CC4_FPC_PVAL_Msk (0x0fUL << CCU4_CC4_FPC_PVAL_Pos) /*!< CCU4_CC4 FPC: PVAL Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_FPCS ------------------------------- */\r
+#define CCU4_CC4_FPCS_PCMP_Pos 0 /*!< CCU4_CC4 FPCS: PCMP Position */\r
+#define CCU4_CC4_FPCS_PCMP_Msk (0x0fUL << CCU4_CC4_FPCS_PCMP_Pos) /*!< CCU4_CC4 FPCS: PCMP Mask */\r
+\r
+/* --------------------------------- CCU4_CC4_PR -------------------------------- */\r
+#define CCU4_CC4_PR_PR_Pos 0 /*!< CCU4_CC4 PR: PR Position */\r
+#define CCU4_CC4_PR_PR_Msk (0x0000ffffUL << CCU4_CC4_PR_PR_Pos) /*!< CCU4_CC4 PR: PR Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_PRS -------------------------------- */\r
+#define CCU4_CC4_PRS_PRS_Pos 0 /*!< CCU4_CC4 PRS: PRS Position */\r
+#define CCU4_CC4_PRS_PRS_Msk (0x0000ffffUL << CCU4_CC4_PRS_PRS_Pos) /*!< CCU4_CC4 PRS: PRS Mask */\r
+\r
+/* --------------------------------- CCU4_CC4_CR -------------------------------- */\r
+#define CCU4_CC4_CR_CR_Pos 0 /*!< CCU4_CC4 CR: CR Position */\r
+#define CCU4_CC4_CR_CR_Msk (0x0000ffffUL << CCU4_CC4_CR_CR_Pos) /*!< CCU4_CC4 CR: CR Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_CRS -------------------------------- */\r
+#define CCU4_CC4_CRS_CRS_Pos 0 /*!< CCU4_CC4 CRS: CRS Position */\r
+#define CCU4_CC4_CRS_CRS_Msk (0x0000ffffUL << CCU4_CC4_CRS_CRS_Pos) /*!< CCU4_CC4 CRS: CRS Mask */\r
+\r
+/* ------------------------------- CCU4_CC4_TIMER ------------------------------- */\r
+#define CCU4_CC4_TIMER_TVAL_Pos 0 /*!< CCU4_CC4 TIMER: TVAL Position */\r
+#define CCU4_CC4_TIMER_TVAL_Msk (0x0000ffffUL << CCU4_CC4_TIMER_TVAL_Pos) /*!< CCU4_CC4 TIMER: TVAL Mask */\r
+\r
+/* --------------------------------- CCU4_CC4_CV -------------------------------- */\r
+#define CCU4_CC4_CV_CAPTV_Pos 0 /*!< CCU4_CC4 CV: CAPTV Position */\r
+#define CCU4_CC4_CV_CAPTV_Msk (0x0000ffffUL << CCU4_CC4_CV_CAPTV_Pos) /*!< CCU4_CC4 CV: CAPTV Mask */\r
+#define CCU4_CC4_CV_FPCV_Pos 16 /*!< CCU4_CC4 CV: FPCV Position */\r
+#define CCU4_CC4_CV_FPCV_Msk (0x0fUL << CCU4_CC4_CV_FPCV_Pos) /*!< CCU4_CC4 CV: FPCV Mask */\r
+#define CCU4_CC4_CV_FFL_Pos 20 /*!< CCU4_CC4 CV: FFL Position */\r
+#define CCU4_CC4_CV_FFL_Msk (0x01UL << CCU4_CC4_CV_FFL_Pos) /*!< CCU4_CC4 CV: FFL Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_INTS ------------------------------- */\r
+#define CCU4_CC4_INTS_PMUS_Pos 0 /*!< CCU4_CC4 INTS: PMUS Position */\r
+#define CCU4_CC4_INTS_PMUS_Msk (0x01UL << CCU4_CC4_INTS_PMUS_Pos) /*!< CCU4_CC4 INTS: PMUS Mask */\r
+#define CCU4_CC4_INTS_OMDS_Pos 1 /*!< CCU4_CC4 INTS: OMDS Position */\r
+#define CCU4_CC4_INTS_OMDS_Msk (0x01UL << CCU4_CC4_INTS_OMDS_Pos) /*!< CCU4_CC4 INTS: OMDS Mask */\r
+#define CCU4_CC4_INTS_CMUS_Pos 2 /*!< CCU4_CC4 INTS: CMUS Position */\r
+#define CCU4_CC4_INTS_CMUS_Msk (0x01UL << CCU4_CC4_INTS_CMUS_Pos) /*!< CCU4_CC4 INTS: CMUS Mask */\r
+#define CCU4_CC4_INTS_CMDS_Pos 3 /*!< CCU4_CC4 INTS: CMDS Position */\r
+#define CCU4_CC4_INTS_CMDS_Msk (0x01UL << CCU4_CC4_INTS_CMDS_Pos) /*!< CCU4_CC4 INTS: CMDS Mask */\r
+#define CCU4_CC4_INTS_E0AS_Pos 8 /*!< CCU4_CC4 INTS: E0AS Position */\r
+#define CCU4_CC4_INTS_E0AS_Msk (0x01UL << CCU4_CC4_INTS_E0AS_Pos) /*!< CCU4_CC4 INTS: E0AS Mask */\r
+#define CCU4_CC4_INTS_E1AS_Pos 9 /*!< CCU4_CC4 INTS: E1AS Position */\r
+#define CCU4_CC4_INTS_E1AS_Msk (0x01UL << CCU4_CC4_INTS_E1AS_Pos) /*!< CCU4_CC4 INTS: E1AS Mask */\r
+#define CCU4_CC4_INTS_E2AS_Pos 10 /*!< CCU4_CC4 INTS: E2AS Position */\r
+#define CCU4_CC4_INTS_E2AS_Msk (0x01UL << CCU4_CC4_INTS_E2AS_Pos) /*!< CCU4_CC4 INTS: E2AS Mask */\r
+#define CCU4_CC4_INTS_TRPF_Pos 11 /*!< CCU4_CC4 INTS: TRPF Position */\r
+#define CCU4_CC4_INTS_TRPF_Msk (0x01UL << CCU4_CC4_INTS_TRPF_Pos) /*!< CCU4_CC4 INTS: TRPF Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_INTE ------------------------------- */\r
+#define CCU4_CC4_INTE_PME_Pos 0 /*!< CCU4_CC4 INTE: PME Position */\r
+#define CCU4_CC4_INTE_PME_Msk (0x01UL << CCU4_CC4_INTE_PME_Pos) /*!< CCU4_CC4 INTE: PME Mask */\r
+#define CCU4_CC4_INTE_OME_Pos 1 /*!< CCU4_CC4 INTE: OME Position */\r
+#define CCU4_CC4_INTE_OME_Msk (0x01UL << CCU4_CC4_INTE_OME_Pos) /*!< CCU4_CC4 INTE: OME Mask */\r
+#define CCU4_CC4_INTE_CMUE_Pos 2 /*!< CCU4_CC4 INTE: CMUE Position */\r
+#define CCU4_CC4_INTE_CMUE_Msk (0x01UL << CCU4_CC4_INTE_CMUE_Pos) /*!< CCU4_CC4 INTE: CMUE Mask */\r
+#define CCU4_CC4_INTE_CMDE_Pos 3 /*!< CCU4_CC4 INTE: CMDE Position */\r
+#define CCU4_CC4_INTE_CMDE_Msk (0x01UL << CCU4_CC4_INTE_CMDE_Pos) /*!< CCU4_CC4 INTE: CMDE Mask */\r
+#define CCU4_CC4_INTE_E0AE_Pos 8 /*!< CCU4_CC4 INTE: E0AE Position */\r
+#define CCU4_CC4_INTE_E0AE_Msk (0x01UL << CCU4_CC4_INTE_E0AE_Pos) /*!< CCU4_CC4 INTE: E0AE Mask */\r
+#define CCU4_CC4_INTE_E1AE_Pos 9 /*!< CCU4_CC4 INTE: E1AE Position */\r
+#define CCU4_CC4_INTE_E1AE_Msk (0x01UL << CCU4_CC4_INTE_E1AE_Pos) /*!< CCU4_CC4 INTE: E1AE Mask */\r
+#define CCU4_CC4_INTE_E2AE_Pos 10 /*!< CCU4_CC4 INTE: E2AE Position */\r
+#define CCU4_CC4_INTE_E2AE_Msk (0x01UL << CCU4_CC4_INTE_E2AE_Pos) /*!< CCU4_CC4 INTE: E2AE Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_SRS -------------------------------- */\r
+#define CCU4_CC4_SRS_POSR_Pos 0 /*!< CCU4_CC4 SRS: POSR Position */\r
+#define CCU4_CC4_SRS_POSR_Msk (0x03UL << CCU4_CC4_SRS_POSR_Pos) /*!< CCU4_CC4 SRS: POSR Mask */\r
+#define CCU4_CC4_SRS_CMSR_Pos 2 /*!< CCU4_CC4 SRS: CMSR Position */\r
+#define CCU4_CC4_SRS_CMSR_Msk (0x03UL << CCU4_CC4_SRS_CMSR_Pos) /*!< CCU4_CC4 SRS: CMSR Mask */\r
+#define CCU4_CC4_SRS_E0SR_Pos 8 /*!< CCU4_CC4 SRS: E0SR Position */\r
+#define CCU4_CC4_SRS_E0SR_Msk (0x03UL << CCU4_CC4_SRS_E0SR_Pos) /*!< CCU4_CC4 SRS: E0SR Mask */\r
+#define CCU4_CC4_SRS_E1SR_Pos 10 /*!< CCU4_CC4 SRS: E1SR Position */\r
+#define CCU4_CC4_SRS_E1SR_Msk (0x03UL << CCU4_CC4_SRS_E1SR_Pos) /*!< CCU4_CC4 SRS: E1SR Mask */\r
+#define CCU4_CC4_SRS_E2SR_Pos 12 /*!< CCU4_CC4 SRS: E2SR Position */\r
+#define CCU4_CC4_SRS_E2SR_Msk (0x03UL << CCU4_CC4_SRS_E2SR_Pos) /*!< CCU4_CC4 SRS: E2SR Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_SWS -------------------------------- */\r
+#define CCU4_CC4_SWS_SPM_Pos 0 /*!< CCU4_CC4 SWS: SPM Position */\r
+#define CCU4_CC4_SWS_SPM_Msk (0x01UL << CCU4_CC4_SWS_SPM_Pos) /*!< CCU4_CC4 SWS: SPM Mask */\r
+#define CCU4_CC4_SWS_SOM_Pos 1 /*!< CCU4_CC4 SWS: SOM Position */\r
+#define CCU4_CC4_SWS_SOM_Msk (0x01UL << CCU4_CC4_SWS_SOM_Pos) /*!< CCU4_CC4 SWS: SOM Mask */\r
+#define CCU4_CC4_SWS_SCMU_Pos 2 /*!< CCU4_CC4 SWS: SCMU Position */\r
+#define CCU4_CC4_SWS_SCMU_Msk (0x01UL << CCU4_CC4_SWS_SCMU_Pos) /*!< CCU4_CC4 SWS: SCMU Mask */\r
+#define CCU4_CC4_SWS_SCMD_Pos 3 /*!< CCU4_CC4 SWS: SCMD Position */\r
+#define CCU4_CC4_SWS_SCMD_Msk (0x01UL << CCU4_CC4_SWS_SCMD_Pos) /*!< CCU4_CC4 SWS: SCMD Mask */\r
+#define CCU4_CC4_SWS_SE0A_Pos 8 /*!< CCU4_CC4 SWS: SE0A Position */\r
+#define CCU4_CC4_SWS_SE0A_Msk (0x01UL << CCU4_CC4_SWS_SE0A_Pos) /*!< CCU4_CC4 SWS: SE0A Mask */\r
+#define CCU4_CC4_SWS_SE1A_Pos 9 /*!< CCU4_CC4 SWS: SE1A Position */\r
+#define CCU4_CC4_SWS_SE1A_Msk (0x01UL << CCU4_CC4_SWS_SE1A_Pos) /*!< CCU4_CC4 SWS: SE1A Mask */\r
+#define CCU4_CC4_SWS_SE2A_Pos 10 /*!< CCU4_CC4 SWS: SE2A Position */\r
+#define CCU4_CC4_SWS_SE2A_Msk (0x01UL << CCU4_CC4_SWS_SE2A_Pos) /*!< CCU4_CC4 SWS: SE2A Mask */\r
+#define CCU4_CC4_SWS_STRPF_Pos 11 /*!< CCU4_CC4 SWS: STRPF Position */\r
+#define CCU4_CC4_SWS_STRPF_Msk (0x01UL << CCU4_CC4_SWS_STRPF_Pos) /*!< CCU4_CC4 SWS: STRPF Mask */\r
+\r
+/* -------------------------------- CCU4_CC4_SWR -------------------------------- */\r
+#define CCU4_CC4_SWR_RPM_Pos 0 /*!< CCU4_CC4 SWR: RPM Position */\r
+#define CCU4_CC4_SWR_RPM_Msk (0x01UL << CCU4_CC4_SWR_RPM_Pos) /*!< CCU4_CC4 SWR: RPM Mask */\r
+#define CCU4_CC4_SWR_ROM_Pos 1 /*!< CCU4_CC4 SWR: ROM Position */\r
+#define CCU4_CC4_SWR_ROM_Msk (0x01UL << CCU4_CC4_SWR_ROM_Pos) /*!< CCU4_CC4 SWR: ROM Mask */\r
+#define CCU4_CC4_SWR_RCMU_Pos 2 /*!< CCU4_CC4 SWR: RCMU Position */\r
+#define CCU4_CC4_SWR_RCMU_Msk (0x01UL << CCU4_CC4_SWR_RCMU_Pos) /*!< CCU4_CC4 SWR: RCMU Mask */\r
+#define CCU4_CC4_SWR_RCMD_Pos 3 /*!< CCU4_CC4 SWR: RCMD Position */\r
+#define CCU4_CC4_SWR_RCMD_Msk (0x01UL << CCU4_CC4_SWR_RCMD_Pos) /*!< CCU4_CC4 SWR: RCMD Mask */\r
+#define CCU4_CC4_SWR_RE0A_Pos 8 /*!< CCU4_CC4 SWR: RE0A Position */\r
+#define CCU4_CC4_SWR_RE0A_Msk (0x01UL << CCU4_CC4_SWR_RE0A_Pos) /*!< CCU4_CC4 SWR: RE0A Mask */\r
+#define CCU4_CC4_SWR_RE1A_Pos 9 /*!< CCU4_CC4 SWR: RE1A Position */\r
+#define CCU4_CC4_SWR_RE1A_Msk (0x01UL << CCU4_CC4_SWR_RE1A_Pos) /*!< CCU4_CC4 SWR: RE1A Mask */\r
+#define CCU4_CC4_SWR_RE2A_Pos 10 /*!< CCU4_CC4 SWR: RE2A Position */\r
+#define CCU4_CC4_SWR_RE2A_Msk (0x01UL << CCU4_CC4_SWR_RE2A_Pos) /*!< CCU4_CC4 SWR: RE2A Mask */\r
+#define CCU4_CC4_SWR_RTRPF_Pos 11 /*!< CCU4_CC4 SWR: RTRPF Position */\r
+#define CCU4_CC4_SWR_RTRPF_Msk (0x01UL << CCU4_CC4_SWR_RTRPF_Pos) /*!< CCU4_CC4 SWR: RTRPF Mask */\r
+\r
+/* ------------------------------- CCU4_CC4_ECRD0 ------------------------------- */\r
+#define CCU4_CC4_ECRD0_CAPV_Pos 0 /*!< CCU4_CC4 ECRD0: CAPV Position */\r
+#define CCU4_CC4_ECRD0_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD0_CAPV_Pos) /*!< CCU4_CC4 ECRD0: CAPV Mask */\r
+#define CCU4_CC4_ECRD0_FPCV_Pos 16 /*!< CCU4_CC4 ECRD0: FPCV Position */\r
+#define CCU4_CC4_ECRD0_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD0_FPCV_Pos) /*!< CCU4_CC4 ECRD0: FPCV Mask */\r
+#define CCU4_CC4_ECRD0_SPTR_Pos 20 /*!< CCU4_CC4 ECRD0: SPTR Position */\r
+#define CCU4_CC4_ECRD0_SPTR_Msk (0x03UL << CCU4_CC4_ECRD0_SPTR_Pos) /*!< CCU4_CC4 ECRD0: SPTR Mask */\r
+#define CCU4_CC4_ECRD0_VPTR_Pos 22 /*!< CCU4_CC4 ECRD0: VPTR Position */\r
+#define CCU4_CC4_ECRD0_VPTR_Msk (0x03UL << CCU4_CC4_ECRD0_VPTR_Pos) /*!< CCU4_CC4 ECRD0: VPTR Mask */\r
+#define CCU4_CC4_ECRD0_FFL_Pos 24 /*!< CCU4_CC4 ECRD0: FFL Position */\r
+#define CCU4_CC4_ECRD0_FFL_Msk (0x01UL << CCU4_CC4_ECRD0_FFL_Pos) /*!< CCU4_CC4 ECRD0: FFL Mask */\r
+#define CCU4_CC4_ECRD0_LCV_Pos 25 /*!< CCU4_CC4 ECRD0: LCV Position */\r
+#define CCU4_CC4_ECRD0_LCV_Msk (0x01UL << CCU4_CC4_ECRD0_LCV_Pos) /*!< CCU4_CC4 ECRD0: LCV Mask */\r
+\r
+/* ------------------------------- CCU4_CC4_ECRD1 ------------------------------- */\r
+#define CCU4_CC4_ECRD1_CAPV_Pos 0 /*!< CCU4_CC4 ECRD1: CAPV Position */\r
+#define CCU4_CC4_ECRD1_CAPV_Msk (0x0000ffffUL << CCU4_CC4_ECRD1_CAPV_Pos) /*!< CCU4_CC4 ECRD1: CAPV Mask */\r
+#define CCU4_CC4_ECRD1_FPCV_Pos 16 /*!< CCU4_CC4 ECRD1: FPCV Position */\r
+#define CCU4_CC4_ECRD1_FPCV_Msk (0x0fUL << CCU4_CC4_ECRD1_FPCV_Pos) /*!< CCU4_CC4 ECRD1: FPCV Mask */\r
+#define CCU4_CC4_ECRD1_SPTR_Pos 20 /*!< CCU4_CC4 ECRD1: SPTR Position */\r
+#define CCU4_CC4_ECRD1_SPTR_Msk (0x03UL << CCU4_CC4_ECRD1_SPTR_Pos) /*!< CCU4_CC4 ECRD1: SPTR Mask */\r
+#define CCU4_CC4_ECRD1_VPTR_Pos 22 /*!< CCU4_CC4 ECRD1: VPTR Position */\r
+#define CCU4_CC4_ECRD1_VPTR_Msk (0x03UL << CCU4_CC4_ECRD1_VPTR_Pos) /*!< CCU4_CC4 ECRD1: VPTR Mask */\r
+#define CCU4_CC4_ECRD1_FFL_Pos 24 /*!< CCU4_CC4 ECRD1: FFL Position */\r
+#define CCU4_CC4_ECRD1_FFL_Msk (0x01UL << CCU4_CC4_ECRD1_FFL_Pos) /*!< CCU4_CC4 ECRD1: FFL Mask */\r
+#define CCU4_CC4_ECRD1_LCV_Pos 25 /*!< CCU4_CC4 ECRD1: LCV Position */\r
+#define CCU4_CC4_ECRD1_LCV_Msk (0x01UL << CCU4_CC4_ECRD1_LCV_Pos) /*!< CCU4_CC4 ECRD1: LCV Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'VADC' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- VADC_CLC ---------------------------------- */\r
+#define VADC_CLC_DISR_Pos 0 /*!< VADC CLC: DISR Position */\r
+#define VADC_CLC_DISR_Msk (0x01UL << VADC_CLC_DISR_Pos) /*!< VADC CLC: DISR Mask */\r
+#define VADC_CLC_DISS_Pos 1 /*!< VADC CLC: DISS Position */\r
+#define VADC_CLC_DISS_Msk (0x01UL << VADC_CLC_DISS_Pos) /*!< VADC CLC: DISS Mask */\r
+#define VADC_CLC_EDIS_Pos 3 /*!< VADC CLC: EDIS Position */\r
+#define VADC_CLC_EDIS_Msk (0x01UL << VADC_CLC_EDIS_Pos) /*!< VADC CLC: EDIS Mask */\r
+\r
+/* ----------------------------------- VADC_ID ---------------------------------- */\r
+#define VADC_ID_MOD_REV_Pos 0 /*!< VADC ID: MOD_REV Position */\r
+#define VADC_ID_MOD_REV_Msk (0x000000ffUL << VADC_ID_MOD_REV_Pos) /*!< VADC ID: MOD_REV Mask */\r
+#define VADC_ID_MOD_TYPE_Pos 8 /*!< VADC ID: MOD_TYPE Position */\r
+#define VADC_ID_MOD_TYPE_Msk (0x000000ffUL << VADC_ID_MOD_TYPE_Pos) /*!< VADC ID: MOD_TYPE Mask */\r
+#define VADC_ID_MOD_NUMBER_Pos 16 /*!< VADC ID: MOD_NUMBER Position */\r
+#define VADC_ID_MOD_NUMBER_Msk (0x0000ffffUL << VADC_ID_MOD_NUMBER_Pos) /*!< VADC ID: MOD_NUMBER Mask */\r
+\r
+/* ---------------------------------- VADC_OCS ---------------------------------- */\r
+#define VADC_OCS_TGS_Pos 0 /*!< VADC OCS: TGS Position */\r
+#define VADC_OCS_TGS_Msk (0x03UL << VADC_OCS_TGS_Pos) /*!< VADC OCS: TGS Mask */\r
+#define VADC_OCS_TGB_Pos 2 /*!< VADC OCS: TGB Position */\r
+#define VADC_OCS_TGB_Msk (0x01UL << VADC_OCS_TGB_Pos) /*!< VADC OCS: TGB Mask */\r
+#define VADC_OCS_TG_P_Pos 3 /*!< VADC OCS: TG_P Position */\r
+#define VADC_OCS_TG_P_Msk (0x01UL << VADC_OCS_TG_P_Pos) /*!< VADC OCS: TG_P Mask */\r
+#define VADC_OCS_SUS_Pos 24 /*!< VADC OCS: SUS Position */\r
+#define VADC_OCS_SUS_Msk (0x0fUL << VADC_OCS_SUS_Pos) /*!< VADC OCS: SUS Mask */\r
+#define VADC_OCS_SUS_P_Pos 28 /*!< VADC OCS: SUS_P Position */\r
+#define VADC_OCS_SUS_P_Msk (0x01UL << VADC_OCS_SUS_P_Pos) /*!< VADC OCS: SUS_P Mask */\r
+#define VADC_OCS_SUSSTA_Pos 29 /*!< VADC OCS: SUSSTA Position */\r
+#define VADC_OCS_SUSSTA_Msk (0x01UL << VADC_OCS_SUSSTA_Pos) /*!< VADC OCS: SUSSTA Mask */\r
+\r
+/* -------------------------------- VADC_GLOBCFG -------------------------------- */\r
+#define VADC_GLOBCFG_DIVA_Pos 0 /*!< VADC GLOBCFG: DIVA Position */\r
+#define VADC_GLOBCFG_DIVA_Msk (0x1fUL << VADC_GLOBCFG_DIVA_Pos) /*!< VADC GLOBCFG: DIVA Mask */\r
+#define VADC_GLOBCFG_DCMSB_Pos 7 /*!< VADC GLOBCFG: DCMSB Position */\r
+#define VADC_GLOBCFG_DCMSB_Msk (0x01UL << VADC_GLOBCFG_DCMSB_Pos) /*!< VADC GLOBCFG: DCMSB Mask */\r
+#define VADC_GLOBCFG_DIVD_Pos 8 /*!< VADC GLOBCFG: DIVD Position */\r
+#define VADC_GLOBCFG_DIVD_Msk (0x03UL << VADC_GLOBCFG_DIVD_Pos) /*!< VADC GLOBCFG: DIVD Mask */\r
+#define VADC_GLOBCFG_DIVWC_Pos 15 /*!< VADC GLOBCFG: DIVWC Position */\r
+#define VADC_GLOBCFG_DIVWC_Msk (0x01UL << VADC_GLOBCFG_DIVWC_Pos) /*!< VADC GLOBCFG: DIVWC Mask */\r
+#define VADC_GLOBCFG_DPCAL0_Pos 16 /*!< VADC GLOBCFG: DPCAL0 Position */\r
+#define VADC_GLOBCFG_DPCAL0_Msk (0x01UL << VADC_GLOBCFG_DPCAL0_Pos) /*!< VADC GLOBCFG: DPCAL0 Mask */\r
+#define VADC_GLOBCFG_DPCAL1_Pos 17 /*!< VADC GLOBCFG: DPCAL1 Position */\r
+#define VADC_GLOBCFG_DPCAL1_Msk (0x01UL << VADC_GLOBCFG_DPCAL1_Pos) /*!< VADC GLOBCFG: DPCAL1 Mask */\r
+#define VADC_GLOBCFG_SUCAL_Pos 31 /*!< VADC GLOBCFG: SUCAL Position */\r
+#define VADC_GLOBCFG_SUCAL_Msk (0x01UL << VADC_GLOBCFG_SUCAL_Pos) /*!< VADC GLOBCFG: SUCAL Mask */\r
+\r
+/* -------------------------------- VADC_ACCPROT0 ------------------------------- */\r
+#define VADC_ACCPROT0_APC0_Pos 0 /*!< VADC ACCPROT0: APC0 Position */\r
+#define VADC_ACCPROT0_APC0_Msk (0x01UL << VADC_ACCPROT0_APC0_Pos) /*!< VADC ACCPROT0: APC0 Mask */\r
+#define VADC_ACCPROT0_APC1_Pos 1 /*!< VADC ACCPROT0: APC1 Position */\r
+#define VADC_ACCPROT0_APC1_Msk (0x01UL << VADC_ACCPROT0_APC1_Pos) /*!< VADC ACCPROT0: APC1 Mask */\r
+#define VADC_ACCPROT0_APEM_Pos 15 /*!< VADC ACCPROT0: APEM Position */\r
+#define VADC_ACCPROT0_APEM_Msk (0x01UL << VADC_ACCPROT0_APEM_Pos) /*!< VADC ACCPROT0: APEM Mask */\r
+#define VADC_ACCPROT0_API0_Pos 16 /*!< VADC ACCPROT0: API0 Position */\r
+#define VADC_ACCPROT0_API0_Msk (0x01UL << VADC_ACCPROT0_API0_Pos) /*!< VADC ACCPROT0: API0 Mask */\r
+#define VADC_ACCPROT0_API1_Pos 17 /*!< VADC ACCPROT0: API1 Position */\r
+#define VADC_ACCPROT0_API1_Msk (0x01UL << VADC_ACCPROT0_API1_Pos) /*!< VADC ACCPROT0: API1 Mask */\r
+#define VADC_ACCPROT0_APGC_Pos 31 /*!< VADC ACCPROT0: APGC Position */\r
+#define VADC_ACCPROT0_APGC_Msk (0x01UL << VADC_ACCPROT0_APGC_Pos) /*!< VADC ACCPROT0: APGC Mask */\r
+\r
+/* -------------------------------- VADC_ACCPROT1 ------------------------------- */\r
+#define VADC_ACCPROT1_APS0_Pos 0 /*!< VADC ACCPROT1: APS0 Position */\r
+#define VADC_ACCPROT1_APS0_Msk (0x01UL << VADC_ACCPROT1_APS0_Pos) /*!< VADC ACCPROT1: APS0 Mask */\r
+#define VADC_ACCPROT1_APS1_Pos 1 /*!< VADC ACCPROT1: APS1 Position */\r
+#define VADC_ACCPROT1_APS1_Msk (0x01UL << VADC_ACCPROT1_APS1_Pos) /*!< VADC ACCPROT1: APS1 Mask */\r
+#define VADC_ACCPROT1_APTF_Pos 15 /*!< VADC ACCPROT1: APTF Position */\r
+#define VADC_ACCPROT1_APTF_Msk (0x01UL << VADC_ACCPROT1_APTF_Pos) /*!< VADC ACCPROT1: APTF Mask */\r
+#define VADC_ACCPROT1_APR0_Pos 16 /*!< VADC ACCPROT1: APR0 Position */\r
+#define VADC_ACCPROT1_APR0_Msk (0x01UL << VADC_ACCPROT1_APR0_Pos) /*!< VADC ACCPROT1: APR0 Mask */\r
+#define VADC_ACCPROT1_APR1_Pos 17 /*!< VADC ACCPROT1: APR1 Position */\r
+#define VADC_ACCPROT1_APR1_Msk (0x01UL << VADC_ACCPROT1_APR1_Pos) /*!< VADC ACCPROT1: APR1 Mask */\r
+\r
+/* ------------------------------- VADC_GLOBICLASS ------------------------------ */\r
+#define VADC_GLOBICLASS_STCS_Pos 0 /*!< VADC GLOBICLASS: STCS Position */\r
+#define VADC_GLOBICLASS_STCS_Msk (0x1fUL << VADC_GLOBICLASS_STCS_Pos) /*!< VADC GLOBICLASS: STCS Mask */\r
+#define VADC_GLOBICLASS_CMS_Pos 8 /*!< VADC GLOBICLASS: CMS Position */\r
+#define VADC_GLOBICLASS_CMS_Msk (0x07UL << VADC_GLOBICLASS_CMS_Pos) /*!< VADC GLOBICLASS: CMS Mask */\r
+#define VADC_GLOBICLASS_STCE_Pos 16 /*!< VADC GLOBICLASS: STCE Position */\r
+#define VADC_GLOBICLASS_STCE_Msk (0x1fUL << VADC_GLOBICLASS_STCE_Pos) /*!< VADC GLOBICLASS: STCE Mask */\r
+#define VADC_GLOBICLASS_CME_Pos 24 /*!< VADC GLOBICLASS: CME Position */\r
+#define VADC_GLOBICLASS_CME_Msk (0x07UL << VADC_GLOBICLASS_CME_Pos) /*!< VADC GLOBICLASS: CME Mask */\r
+\r
+/* ------------------------------- VADC_GLOBBOUND ------------------------------- */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Pos 0 /*!< VADC GLOBBOUND: BOUNDARY0 Position */\r
+#define VADC_GLOBBOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY0_Pos) /*!< VADC GLOBBOUND: BOUNDARY0 Mask */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Pos 16 /*!< VADC GLOBBOUND: BOUNDARY1 Position */\r
+#define VADC_GLOBBOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_GLOBBOUND_BOUNDARY1_Pos) /*!< VADC GLOBBOUND: BOUNDARY1 Mask */\r
+\r
+/* ------------------------------- VADC_GLOBEFLAG ------------------------------- */\r
+#define VADC_GLOBEFLAG_SEVGLB_Pos 0 /*!< VADC GLOBEFLAG: SEVGLB Position */\r
+#define VADC_GLOBEFLAG_SEVGLB_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLB_Pos) /*!< VADC GLOBEFLAG: SEVGLB Mask */\r
+#define VADC_GLOBEFLAG_REVGLB_Pos 8 /*!< VADC GLOBEFLAG: REVGLB Position */\r
+#define VADC_GLOBEFLAG_REVGLB_Msk (0x01UL << VADC_GLOBEFLAG_REVGLB_Pos) /*!< VADC GLOBEFLAG: REVGLB Mask */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Pos 16 /*!< VADC GLOBEFLAG: SEVGLBCLR Position */\r
+#define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_SEVGLBCLR_Pos) /*!< VADC GLOBEFLAG: SEVGLBCLR Mask */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Pos 24 /*!< VADC GLOBEFLAG: REVGLBCLR Position */\r
+#define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x01UL << VADC_GLOBEFLAG_REVGLBCLR_Pos) /*!< VADC GLOBEFLAG: REVGLBCLR Mask */\r
+\r
+/* -------------------------------- VADC_GLOBEVNP ------------------------------- */\r
+#define VADC_GLOBEVNP_SEV0NP_Pos 0 /*!< VADC GLOBEVNP: SEV0NP Position */\r
+#define VADC_GLOBEVNP_SEV0NP_Msk (0x0fUL << VADC_GLOBEVNP_SEV0NP_Pos) /*!< VADC GLOBEVNP: SEV0NP Mask */\r
+#define VADC_GLOBEVNP_REV0NP_Pos 16 /*!< VADC GLOBEVNP: REV0NP Position */\r
+#define VADC_GLOBEVNP_REV0NP_Msk (0x0fUL << VADC_GLOBEVNP_REV0NP_Pos) /*!< VADC GLOBEVNP: REV0NP Mask */\r
+\r
+/* --------------------------------- VADC_BRSSEL -------------------------------- */\r
+#define VADC_BRSSEL_CHSELG0_Pos 0 /*!< VADC BRSSEL: CHSELG0 Position */\r
+#define VADC_BRSSEL_CHSELG0_Msk (0x01UL << VADC_BRSSEL_CHSELG0_Pos) /*!< VADC BRSSEL: CHSELG0 Mask */\r
+#define VADC_BRSSEL_CHSELG1_Pos 1 /*!< VADC BRSSEL: CHSELG1 Position */\r
+#define VADC_BRSSEL_CHSELG1_Msk (0x01UL << VADC_BRSSEL_CHSELG1_Pos) /*!< VADC BRSSEL: CHSELG1 Mask */\r
+#define VADC_BRSSEL_CHSELG2_Pos 2 /*!< VADC BRSSEL: CHSELG2 Position */\r
+#define VADC_BRSSEL_CHSELG2_Msk (0x01UL << VADC_BRSSEL_CHSELG2_Pos) /*!< VADC BRSSEL: CHSELG2 Mask */\r
+#define VADC_BRSSEL_CHSELG3_Pos 3 /*!< VADC BRSSEL: CHSELG3 Position */\r
+#define VADC_BRSSEL_CHSELG3_Msk (0x01UL << VADC_BRSSEL_CHSELG3_Pos) /*!< VADC BRSSEL: CHSELG3 Mask */\r
+#define VADC_BRSSEL_CHSELG4_Pos 4 /*!< VADC BRSSEL: CHSELG4 Position */\r
+#define VADC_BRSSEL_CHSELG4_Msk (0x01UL << VADC_BRSSEL_CHSELG4_Pos) /*!< VADC BRSSEL: CHSELG4 Mask */\r
+#define VADC_BRSSEL_CHSELG5_Pos 5 /*!< VADC BRSSEL: CHSELG5 Position */\r
+#define VADC_BRSSEL_CHSELG5_Msk (0x01UL << VADC_BRSSEL_CHSELG5_Pos) /*!< VADC BRSSEL: CHSELG5 Mask */\r
+#define VADC_BRSSEL_CHSELG6_Pos 6 /*!< VADC BRSSEL: CHSELG6 Position */\r
+#define VADC_BRSSEL_CHSELG6_Msk (0x01UL << VADC_BRSSEL_CHSELG6_Pos) /*!< VADC BRSSEL: CHSELG6 Mask */\r
+#define VADC_BRSSEL_CHSELG7_Pos 7 /*!< VADC BRSSEL: CHSELG7 Position */\r
+#define VADC_BRSSEL_CHSELG7_Msk (0x01UL << VADC_BRSSEL_CHSELG7_Pos) /*!< VADC BRSSEL: CHSELG7 Mask */\r
+\r
+/* --------------------------------- VADC_BRSPND -------------------------------- */\r
+#define VADC_BRSPND_CHPNDG0_Pos 0 /*!< VADC BRSPND: CHPNDG0 Position */\r
+#define VADC_BRSPND_CHPNDG0_Msk (0x01UL << VADC_BRSPND_CHPNDG0_Pos) /*!< VADC BRSPND: CHPNDG0 Mask */\r
+#define VADC_BRSPND_CHPNDG1_Pos 1 /*!< VADC BRSPND: CHPNDG1 Position */\r
+#define VADC_BRSPND_CHPNDG1_Msk (0x01UL << VADC_BRSPND_CHPNDG1_Pos) /*!< VADC BRSPND: CHPNDG1 Mask */\r
+#define VADC_BRSPND_CHPNDG2_Pos 2 /*!< VADC BRSPND: CHPNDG2 Position */\r
+#define VADC_BRSPND_CHPNDG2_Msk (0x01UL << VADC_BRSPND_CHPNDG2_Pos) /*!< VADC BRSPND: CHPNDG2 Mask */\r
+#define VADC_BRSPND_CHPNDG3_Pos 3 /*!< VADC BRSPND: CHPNDG3 Position */\r
+#define VADC_BRSPND_CHPNDG3_Msk (0x01UL << VADC_BRSPND_CHPNDG3_Pos) /*!< VADC BRSPND: CHPNDG3 Mask */\r
+#define VADC_BRSPND_CHPNDG4_Pos 4 /*!< VADC BRSPND: CHPNDG4 Position */\r
+#define VADC_BRSPND_CHPNDG4_Msk (0x01UL << VADC_BRSPND_CHPNDG4_Pos) /*!< VADC BRSPND: CHPNDG4 Mask */\r
+#define VADC_BRSPND_CHPNDG5_Pos 5 /*!< VADC BRSPND: CHPNDG5 Position */\r
+#define VADC_BRSPND_CHPNDG5_Msk (0x01UL << VADC_BRSPND_CHPNDG5_Pos) /*!< VADC BRSPND: CHPNDG5 Mask */\r
+#define VADC_BRSPND_CHPNDG6_Pos 6 /*!< VADC BRSPND: CHPNDG6 Position */\r
+#define VADC_BRSPND_CHPNDG6_Msk (0x01UL << VADC_BRSPND_CHPNDG6_Pos) /*!< VADC BRSPND: CHPNDG6 Mask */\r
+#define VADC_BRSPND_CHPNDG7_Pos 7 /*!< VADC BRSPND: CHPNDG7 Position */\r
+#define VADC_BRSPND_CHPNDG7_Msk (0x01UL << VADC_BRSPND_CHPNDG7_Pos) /*!< VADC BRSPND: CHPNDG7 Mask */\r
+\r
+/* -------------------------------- VADC_BRSCTRL -------------------------------- */\r
+#define VADC_BRSCTRL_SRCRESREG_Pos 0 /*!< VADC BRSCTRL: SRCRESREG Position */\r
+#define VADC_BRSCTRL_SRCRESREG_Msk (0x0fUL << VADC_BRSCTRL_SRCRESREG_Pos) /*!< VADC BRSCTRL: SRCRESREG Mask */\r
+#define VADC_BRSCTRL_XTSEL_Pos 8 /*!< VADC BRSCTRL: XTSEL Position */\r
+#define VADC_BRSCTRL_XTSEL_Msk (0x0fUL << VADC_BRSCTRL_XTSEL_Pos) /*!< VADC BRSCTRL: XTSEL Mask */\r
+#define VADC_BRSCTRL_XTLVL_Pos 12 /*!< VADC BRSCTRL: XTLVL Position */\r
+#define VADC_BRSCTRL_XTLVL_Msk (0x01UL << VADC_BRSCTRL_XTLVL_Pos) /*!< VADC BRSCTRL: XTLVL Mask */\r
+#define VADC_BRSCTRL_XTMODE_Pos 13 /*!< VADC BRSCTRL: XTMODE Position */\r
+#define VADC_BRSCTRL_XTMODE_Msk (0x03UL << VADC_BRSCTRL_XTMODE_Pos) /*!< VADC BRSCTRL: XTMODE Mask */\r
+#define VADC_BRSCTRL_XTWC_Pos 15 /*!< VADC BRSCTRL: XTWC Position */\r
+#define VADC_BRSCTRL_XTWC_Msk (0x01UL << VADC_BRSCTRL_XTWC_Pos) /*!< VADC BRSCTRL: XTWC Mask */\r
+#define VADC_BRSCTRL_GTSEL_Pos 16 /*!< VADC BRSCTRL: GTSEL Position */\r
+#define VADC_BRSCTRL_GTSEL_Msk (0x0fUL << VADC_BRSCTRL_GTSEL_Pos) /*!< VADC BRSCTRL: GTSEL Mask */\r
+#define VADC_BRSCTRL_GTLVL_Pos 20 /*!< VADC BRSCTRL: GTLVL Position */\r
+#define VADC_BRSCTRL_GTLVL_Msk (0x01UL << VADC_BRSCTRL_GTLVL_Pos) /*!< VADC BRSCTRL: GTLVL Mask */\r
+#define VADC_BRSCTRL_GTWC_Pos 23 /*!< VADC BRSCTRL: GTWC Position */\r
+#define VADC_BRSCTRL_GTWC_Msk (0x01UL << VADC_BRSCTRL_GTWC_Pos) /*!< VADC BRSCTRL: GTWC Mask */\r
+\r
+/* --------------------------------- VADC_BRSMR --------------------------------- */\r
+#define VADC_BRSMR_ENGT_Pos 0 /*!< VADC BRSMR: ENGT Position */\r
+#define VADC_BRSMR_ENGT_Msk (0x03UL << VADC_BRSMR_ENGT_Pos) /*!< VADC BRSMR: ENGT Mask */\r
+#define VADC_BRSMR_ENTR_Pos 2 /*!< VADC BRSMR: ENTR Position */\r
+#define VADC_BRSMR_ENTR_Msk (0x01UL << VADC_BRSMR_ENTR_Pos) /*!< VADC BRSMR: ENTR Mask */\r
+#define VADC_BRSMR_ENSI_Pos 3 /*!< VADC BRSMR: ENSI Position */\r
+#define VADC_BRSMR_ENSI_Msk (0x01UL << VADC_BRSMR_ENSI_Pos) /*!< VADC BRSMR: ENSI Mask */\r
+#define VADC_BRSMR_SCAN_Pos 4 /*!< VADC BRSMR: SCAN Position */\r
+#define VADC_BRSMR_SCAN_Msk (0x01UL << VADC_BRSMR_SCAN_Pos) /*!< VADC BRSMR: SCAN Mask */\r
+#define VADC_BRSMR_LDM_Pos 5 /*!< VADC BRSMR: LDM Position */\r
+#define VADC_BRSMR_LDM_Msk (0x01UL << VADC_BRSMR_LDM_Pos) /*!< VADC BRSMR: LDM Mask */\r
+#define VADC_BRSMR_REQGT_Pos 7 /*!< VADC BRSMR: REQGT Position */\r
+#define VADC_BRSMR_REQGT_Msk (0x01UL << VADC_BRSMR_REQGT_Pos) /*!< VADC BRSMR: REQGT Mask */\r
+#define VADC_BRSMR_CLRPND_Pos 8 /*!< VADC BRSMR: CLRPND Position */\r
+#define VADC_BRSMR_CLRPND_Msk (0x01UL << VADC_BRSMR_CLRPND_Pos) /*!< VADC BRSMR: CLRPND Mask */\r
+#define VADC_BRSMR_LDEV_Pos 9 /*!< VADC BRSMR: LDEV Position */\r
+#define VADC_BRSMR_LDEV_Msk (0x01UL << VADC_BRSMR_LDEV_Pos) /*!< VADC BRSMR: LDEV Mask */\r
+#define VADC_BRSMR_RPTDIS_Pos 16 /*!< VADC BRSMR: RPTDIS Position */\r
+#define VADC_BRSMR_RPTDIS_Msk (0x01UL << VADC_BRSMR_RPTDIS_Pos) /*!< VADC BRSMR: RPTDIS Mask */\r
+\r
+/* -------------------------------- VADC_GLOBRCR -------------------------------- */\r
+#define VADC_GLOBRCR_DRCTR_Pos 16 /*!< VADC GLOBRCR: DRCTR Position */\r
+#define VADC_GLOBRCR_DRCTR_Msk (0x0fUL << VADC_GLOBRCR_DRCTR_Pos) /*!< VADC GLOBRCR: DRCTR Mask */\r
+#define VADC_GLOBRCR_WFR_Pos 24 /*!< VADC GLOBRCR: WFR Position */\r
+#define VADC_GLOBRCR_WFR_Msk (0x01UL << VADC_GLOBRCR_WFR_Pos) /*!< VADC GLOBRCR: WFR Mask */\r
+#define VADC_GLOBRCR_SRGEN_Pos 31 /*!< VADC GLOBRCR: SRGEN Position */\r
+#define VADC_GLOBRCR_SRGEN_Msk (0x01UL << VADC_GLOBRCR_SRGEN_Pos) /*!< VADC GLOBRCR: SRGEN Mask */\r
+\r
+/* -------------------------------- VADC_GLOBRES -------------------------------- */\r
+#define VADC_GLOBRES_RESULT_Pos 0 /*!< VADC GLOBRES: RESULT Position */\r
+#define VADC_GLOBRES_RESULT_Msk (0x0000ffffUL << VADC_GLOBRES_RESULT_Pos) /*!< VADC GLOBRES: RESULT Mask */\r
+#define VADC_GLOBRES_GNR_Pos 16 /*!< VADC GLOBRES: GNR Position */\r
+#define VADC_GLOBRES_GNR_Msk (0x0fUL << VADC_GLOBRES_GNR_Pos) /*!< VADC GLOBRES: GNR Mask */\r
+#define VADC_GLOBRES_CHNR_Pos 20 /*!< VADC GLOBRES: CHNR Position */\r
+#define VADC_GLOBRES_CHNR_Msk (0x1fUL << VADC_GLOBRES_CHNR_Pos) /*!< VADC GLOBRES: CHNR Mask */\r
+#define VADC_GLOBRES_EMUX_Pos 25 /*!< VADC GLOBRES: EMUX Position */\r
+#define VADC_GLOBRES_EMUX_Msk (0x07UL << VADC_GLOBRES_EMUX_Pos) /*!< VADC GLOBRES: EMUX Mask */\r
+#define VADC_GLOBRES_CRS_Pos 28 /*!< VADC GLOBRES: CRS Position */\r
+#define VADC_GLOBRES_CRS_Msk (0x03UL << VADC_GLOBRES_CRS_Pos) /*!< VADC GLOBRES: CRS Mask */\r
+#define VADC_GLOBRES_FCR_Pos 30 /*!< VADC GLOBRES: FCR Position */\r
+#define VADC_GLOBRES_FCR_Msk (0x01UL << VADC_GLOBRES_FCR_Pos) /*!< VADC GLOBRES: FCR Mask */\r
+#define VADC_GLOBRES_VF_Pos 31 /*!< VADC GLOBRES: VF Position */\r
+#define VADC_GLOBRES_VF_Msk (0x01UL << VADC_GLOBRES_VF_Pos) /*!< VADC GLOBRES: VF Mask */\r
+\r
+/* -------------------------------- VADC_GLOBRESD ------------------------------- */\r
+#define VADC_GLOBRESD_RESULT_Pos 0 /*!< VADC GLOBRESD: RESULT Position */\r
+#define VADC_GLOBRESD_RESULT_Msk (0x0000ffffUL << VADC_GLOBRESD_RESULT_Pos) /*!< VADC GLOBRESD: RESULT Mask */\r
+#define VADC_GLOBRESD_GNR_Pos 16 /*!< VADC GLOBRESD: GNR Position */\r
+#define VADC_GLOBRESD_GNR_Msk (0x0fUL << VADC_GLOBRESD_GNR_Pos) /*!< VADC GLOBRESD: GNR Mask */\r
+#define VADC_GLOBRESD_CHNR_Pos 20 /*!< VADC GLOBRESD: CHNR Position */\r
+#define VADC_GLOBRESD_CHNR_Msk (0x1fUL << VADC_GLOBRESD_CHNR_Pos) /*!< VADC GLOBRESD: CHNR Mask */\r
+#define VADC_GLOBRESD_EMUX_Pos 25 /*!< VADC GLOBRESD: EMUX Position */\r
+#define VADC_GLOBRESD_EMUX_Msk (0x07UL << VADC_GLOBRESD_EMUX_Pos) /*!< VADC GLOBRESD: EMUX Mask */\r
+#define VADC_GLOBRESD_CRS_Pos 28 /*!< VADC GLOBRESD: CRS Position */\r
+#define VADC_GLOBRESD_CRS_Msk (0x03UL << VADC_GLOBRESD_CRS_Pos) /*!< VADC GLOBRESD: CRS Mask */\r
+#define VADC_GLOBRESD_FCR_Pos 30 /*!< VADC GLOBRESD: FCR Position */\r
+#define VADC_GLOBRESD_FCR_Msk (0x01UL << VADC_GLOBRESD_FCR_Pos) /*!< VADC GLOBRESD: FCR Mask */\r
+#define VADC_GLOBRESD_VF_Pos 31 /*!< VADC GLOBRESD: VF Position */\r
+#define VADC_GLOBRESD_VF_Msk (0x01UL << VADC_GLOBRESD_VF_Pos) /*!< VADC GLOBRESD: VF Mask */\r
+\r
+/* -------------------------------- VADC_EMUXSEL -------------------------------- */\r
+#define VADC_EMUXSEL_EMUXGRP0_Pos 0 /*!< VADC EMUXSEL: EMUXGRP0 Position */\r
+#define VADC_EMUXSEL_EMUXGRP0_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP0_Pos) /*!< VADC EMUXSEL: EMUXGRP0 Mask */\r
+#define VADC_EMUXSEL_EMUXGRP1_Pos 4 /*!< VADC EMUXSEL: EMUXGRP1 Position */\r
+#define VADC_EMUXSEL_EMUXGRP1_Msk (0x0fUL << VADC_EMUXSEL_EMUXGRP1_Pos) /*!< VADC EMUXSEL: EMUXGRP1 Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'VADC_G' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- VADC_G_ARBCFG ------------------------------- */\r
+#define VADC_G_ARBCFG_ANONC_Pos 0 /*!< VADC_G ARBCFG: ANONC Position */\r
+#define VADC_G_ARBCFG_ANONC_Msk (0x03UL << VADC_G_ARBCFG_ANONC_Pos) /*!< VADC_G ARBCFG: ANONC Mask */\r
+#define VADC_G_ARBCFG_ARBRND_Pos 4 /*!< VADC_G ARBCFG: ARBRND Position */\r
+#define VADC_G_ARBCFG_ARBRND_Msk (0x03UL << VADC_G_ARBCFG_ARBRND_Pos) /*!< VADC_G ARBCFG: ARBRND Mask */\r
+#define VADC_G_ARBCFG_ARBM_Pos 7 /*!< VADC_G ARBCFG: ARBM Position */\r
+#define VADC_G_ARBCFG_ARBM_Msk (0x01UL << VADC_G_ARBCFG_ARBM_Pos) /*!< VADC_G ARBCFG: ARBM Mask */\r
+#define VADC_G_ARBCFG_ANONS_Pos 16 /*!< VADC_G ARBCFG: ANONS Position */\r
+#define VADC_G_ARBCFG_ANONS_Msk (0x03UL << VADC_G_ARBCFG_ANONS_Pos) /*!< VADC_G ARBCFG: ANONS Mask */\r
+#define VADC_G_ARBCFG_CSRC_Pos 18 /*!< VADC_G ARBCFG: CSRC Position */\r
+#define VADC_G_ARBCFG_CSRC_Msk (0x03UL << VADC_G_ARBCFG_CSRC_Pos) /*!< VADC_G ARBCFG: CSRC Mask */\r
+#define VADC_G_ARBCFG_CHNR_Pos 20 /*!< VADC_G ARBCFG: CHNR Position */\r
+#define VADC_G_ARBCFG_CHNR_Msk (0x1fUL << VADC_G_ARBCFG_CHNR_Pos) /*!< VADC_G ARBCFG: CHNR Mask */\r
+#define VADC_G_ARBCFG_SYNRUN_Pos 25 /*!< VADC_G ARBCFG: SYNRUN Position */\r
+#define VADC_G_ARBCFG_SYNRUN_Msk (0x01UL << VADC_G_ARBCFG_SYNRUN_Pos) /*!< VADC_G ARBCFG: SYNRUN Mask */\r
+#define VADC_G_ARBCFG_CAL_Pos 28 /*!< VADC_G ARBCFG: CAL Position */\r
+#define VADC_G_ARBCFG_CAL_Msk (0x01UL << VADC_G_ARBCFG_CAL_Pos) /*!< VADC_G ARBCFG: CAL Mask */\r
+#define VADC_G_ARBCFG_CALS_Pos 29 /*!< VADC_G ARBCFG: CALS Position */\r
+#define VADC_G_ARBCFG_CALS_Msk (0x01UL << VADC_G_ARBCFG_CALS_Pos) /*!< VADC_G ARBCFG: CALS Mask */\r
+#define VADC_G_ARBCFG_BUSY_Pos 30 /*!< VADC_G ARBCFG: BUSY Position */\r
+#define VADC_G_ARBCFG_BUSY_Msk (0x01UL << VADC_G_ARBCFG_BUSY_Pos) /*!< VADC_G ARBCFG: BUSY Mask */\r
+#define VADC_G_ARBCFG_SAMPLE_Pos 31 /*!< VADC_G ARBCFG: SAMPLE Position */\r
+#define VADC_G_ARBCFG_SAMPLE_Msk (0x01UL << VADC_G_ARBCFG_SAMPLE_Pos) /*!< VADC_G ARBCFG: SAMPLE Mask */\r
+\r
+/* -------------------------------- VADC_G_ARBPR -------------------------------- */\r
+#define VADC_G_ARBPR_PRIO0_Pos 0 /*!< VADC_G ARBPR: PRIO0 Position */\r
+#define VADC_G_ARBPR_PRIO0_Msk (0x03UL << VADC_G_ARBPR_PRIO0_Pos) /*!< VADC_G ARBPR: PRIO0 Mask */\r
+#define VADC_G_ARBPR_CSM0_Pos 3 /*!< VADC_G ARBPR: CSM0 Position */\r
+#define VADC_G_ARBPR_CSM0_Msk (0x01UL << VADC_G_ARBPR_CSM0_Pos) /*!< VADC_G ARBPR: CSM0 Mask */\r
+#define VADC_G_ARBPR_PRIO1_Pos 4 /*!< VADC_G ARBPR: PRIO1 Position */\r
+#define VADC_G_ARBPR_PRIO1_Msk (0x03UL << VADC_G_ARBPR_PRIO1_Pos) /*!< VADC_G ARBPR: PRIO1 Mask */\r
+#define VADC_G_ARBPR_CSM1_Pos 7 /*!< VADC_G ARBPR: CSM1 Position */\r
+#define VADC_G_ARBPR_CSM1_Msk (0x01UL << VADC_G_ARBPR_CSM1_Pos) /*!< VADC_G ARBPR: CSM1 Mask */\r
+#define VADC_G_ARBPR_PRIO2_Pos 8 /*!< VADC_G ARBPR: PRIO2 Position */\r
+#define VADC_G_ARBPR_PRIO2_Msk (0x03UL << VADC_G_ARBPR_PRIO2_Pos) /*!< VADC_G ARBPR: PRIO2 Mask */\r
+#define VADC_G_ARBPR_CSM2_Pos 11 /*!< VADC_G ARBPR: CSM2 Position */\r
+#define VADC_G_ARBPR_CSM2_Msk (0x01UL << VADC_G_ARBPR_CSM2_Pos) /*!< VADC_G ARBPR: CSM2 Mask */\r
+#define VADC_G_ARBPR_ASEN0_Pos 24 /*!< VADC_G ARBPR: ASEN0 Position */\r
+#define VADC_G_ARBPR_ASEN0_Msk (0x01UL << VADC_G_ARBPR_ASEN0_Pos) /*!< VADC_G ARBPR: ASEN0 Mask */\r
+#define VADC_G_ARBPR_ASEN1_Pos 25 /*!< VADC_G ARBPR: ASEN1 Position */\r
+#define VADC_G_ARBPR_ASEN1_Msk (0x01UL << VADC_G_ARBPR_ASEN1_Pos) /*!< VADC_G ARBPR: ASEN1 Mask */\r
+#define VADC_G_ARBPR_ASEN2_Pos 26 /*!< VADC_G ARBPR: ASEN2 Position */\r
+#define VADC_G_ARBPR_ASEN2_Msk (0x01UL << VADC_G_ARBPR_ASEN2_Pos) /*!< VADC_G ARBPR: ASEN2 Mask */\r
+\r
+/* -------------------------------- VADC_G_CHASS -------------------------------- */\r
+#define VADC_G_CHASS_ASSCH0_Pos 0 /*!< VADC_G CHASS: ASSCH0 Position */\r
+#define VADC_G_CHASS_ASSCH0_Msk (0x01UL << VADC_G_CHASS_ASSCH0_Pos) /*!< VADC_G CHASS: ASSCH0 Mask */\r
+#define VADC_G_CHASS_ASSCH1_Pos 1 /*!< VADC_G CHASS: ASSCH1 Position */\r
+#define VADC_G_CHASS_ASSCH1_Msk (0x01UL << VADC_G_CHASS_ASSCH1_Pos) /*!< VADC_G CHASS: ASSCH1 Mask */\r
+#define VADC_G_CHASS_ASSCH2_Pos 2 /*!< VADC_G CHASS: ASSCH2 Position */\r
+#define VADC_G_CHASS_ASSCH2_Msk (0x01UL << VADC_G_CHASS_ASSCH2_Pos) /*!< VADC_G CHASS: ASSCH2 Mask */\r
+#define VADC_G_CHASS_ASSCH3_Pos 3 /*!< VADC_G CHASS: ASSCH3 Position */\r
+#define VADC_G_CHASS_ASSCH3_Msk (0x01UL << VADC_G_CHASS_ASSCH3_Pos) /*!< VADC_G CHASS: ASSCH3 Mask */\r
+#define VADC_G_CHASS_ASSCH4_Pos 4 /*!< VADC_G CHASS: ASSCH4 Position */\r
+#define VADC_G_CHASS_ASSCH4_Msk (0x01UL << VADC_G_CHASS_ASSCH4_Pos) /*!< VADC_G CHASS: ASSCH4 Mask */\r
+#define VADC_G_CHASS_ASSCH5_Pos 5 /*!< VADC_G CHASS: ASSCH5 Position */\r
+#define VADC_G_CHASS_ASSCH5_Msk (0x01UL << VADC_G_CHASS_ASSCH5_Pos) /*!< VADC_G CHASS: ASSCH5 Mask */\r
+#define VADC_G_CHASS_ASSCH6_Pos 6 /*!< VADC_G CHASS: ASSCH6 Position */\r
+#define VADC_G_CHASS_ASSCH6_Msk (0x01UL << VADC_G_CHASS_ASSCH6_Pos) /*!< VADC_G CHASS: ASSCH6 Mask */\r
+#define VADC_G_CHASS_ASSCH7_Pos 7 /*!< VADC_G CHASS: ASSCH7 Position */\r
+#define VADC_G_CHASS_ASSCH7_Msk (0x01UL << VADC_G_CHASS_ASSCH7_Pos) /*!< VADC_G CHASS: ASSCH7 Mask */\r
+\r
+/* -------------------------------- VADC_G_RRASS -------------------------------- */\r
+#define VADC_G_RRASS_ASSRR0_Pos 0 /*!< VADC_G RRASS: ASSRR0 Position */\r
+#define VADC_G_RRASS_ASSRR0_Msk (0x01UL << VADC_G_RRASS_ASSRR0_Pos) /*!< VADC_G RRASS: ASSRR0 Mask */\r
+#define VADC_G_RRASS_ASSRR1_Pos 1 /*!< VADC_G RRASS: ASSRR1 Position */\r
+#define VADC_G_RRASS_ASSRR1_Msk (0x01UL << VADC_G_RRASS_ASSRR1_Pos) /*!< VADC_G RRASS: ASSRR1 Mask */\r
+#define VADC_G_RRASS_ASSRR2_Pos 2 /*!< VADC_G RRASS: ASSRR2 Position */\r
+#define VADC_G_RRASS_ASSRR2_Msk (0x01UL << VADC_G_RRASS_ASSRR2_Pos) /*!< VADC_G RRASS: ASSRR2 Mask */\r
+#define VADC_G_RRASS_ASSRR3_Pos 3 /*!< VADC_G RRASS: ASSRR3 Position */\r
+#define VADC_G_RRASS_ASSRR3_Msk (0x01UL << VADC_G_RRASS_ASSRR3_Pos) /*!< VADC_G RRASS: ASSRR3 Mask */\r
+#define VADC_G_RRASS_ASSRR4_Pos 4 /*!< VADC_G RRASS: ASSRR4 Position */\r
+#define VADC_G_RRASS_ASSRR4_Msk (0x01UL << VADC_G_RRASS_ASSRR4_Pos) /*!< VADC_G RRASS: ASSRR4 Mask */\r
+#define VADC_G_RRASS_ASSRR5_Pos 5 /*!< VADC_G RRASS: ASSRR5 Position */\r
+#define VADC_G_RRASS_ASSRR5_Msk (0x01UL << VADC_G_RRASS_ASSRR5_Pos) /*!< VADC_G RRASS: ASSRR5 Mask */\r
+#define VADC_G_RRASS_ASSRR6_Pos 6 /*!< VADC_G RRASS: ASSRR6 Position */\r
+#define VADC_G_RRASS_ASSRR6_Msk (0x01UL << VADC_G_RRASS_ASSRR6_Pos) /*!< VADC_G RRASS: ASSRR6 Mask */\r
+#define VADC_G_RRASS_ASSRR7_Pos 7 /*!< VADC_G RRASS: ASSRR7 Position */\r
+#define VADC_G_RRASS_ASSRR7_Msk (0x01UL << VADC_G_RRASS_ASSRR7_Pos) /*!< VADC_G RRASS: ASSRR7 Mask */\r
+#define VADC_G_RRASS_ASSRR8_Pos 8 /*!< VADC_G RRASS: ASSRR8 Position */\r
+#define VADC_G_RRASS_ASSRR8_Msk (0x01UL << VADC_G_RRASS_ASSRR8_Pos) /*!< VADC_G RRASS: ASSRR8 Mask */\r
+#define VADC_G_RRASS_ASSRR9_Pos 9 /*!< VADC_G RRASS: ASSRR9 Position */\r
+#define VADC_G_RRASS_ASSRR9_Msk (0x01UL << VADC_G_RRASS_ASSRR9_Pos) /*!< VADC_G RRASS: ASSRR9 Mask */\r
+#define VADC_G_RRASS_ASSRR10_Pos 10 /*!< VADC_G RRASS: ASSRR10 Position */\r
+#define VADC_G_RRASS_ASSRR10_Msk (0x01UL << VADC_G_RRASS_ASSRR10_Pos) /*!< VADC_G RRASS: ASSRR10 Mask */\r
+#define VADC_G_RRASS_ASSRR11_Pos 11 /*!< VADC_G RRASS: ASSRR11 Position */\r
+#define VADC_G_RRASS_ASSRR11_Msk (0x01UL << VADC_G_RRASS_ASSRR11_Pos) /*!< VADC_G RRASS: ASSRR11 Mask */\r
+#define VADC_G_RRASS_ASSRR12_Pos 12 /*!< VADC_G RRASS: ASSRR12 Position */\r
+#define VADC_G_RRASS_ASSRR12_Msk (0x01UL << VADC_G_RRASS_ASSRR12_Pos) /*!< VADC_G RRASS: ASSRR12 Mask */\r
+#define VADC_G_RRASS_ASSRR13_Pos 13 /*!< VADC_G RRASS: ASSRR13 Position */\r
+#define VADC_G_RRASS_ASSRR13_Msk (0x01UL << VADC_G_RRASS_ASSRR13_Pos) /*!< VADC_G RRASS: ASSRR13 Mask */\r
+#define VADC_G_RRASS_ASSRR14_Pos 14 /*!< VADC_G RRASS: ASSRR14 Position */\r
+#define VADC_G_RRASS_ASSRR14_Msk (0x01UL << VADC_G_RRASS_ASSRR14_Pos) /*!< VADC_G RRASS: ASSRR14 Mask */\r
+#define VADC_G_RRASS_ASSRR15_Pos 15 /*!< VADC_G RRASS: ASSRR15 Position */\r
+#define VADC_G_RRASS_ASSRR15_Msk (0x01UL << VADC_G_RRASS_ASSRR15_Pos) /*!< VADC_G RRASS: ASSRR15 Mask */\r
+\r
+/* -------------------------------- VADC_G_ICLASS ------------------------------- */\r
+#define VADC_G_ICLASS_STCS_Pos 0 /*!< VADC_G ICLASS: STCS Position */\r
+#define VADC_G_ICLASS_STCS_Msk (0x1fUL << VADC_G_ICLASS_STCS_Pos) /*!< VADC_G ICLASS: STCS Mask */\r
+#define VADC_G_ICLASS_CMS_Pos 8 /*!< VADC_G ICLASS: CMS Position */\r
+#define VADC_G_ICLASS_CMS_Msk (0x07UL << VADC_G_ICLASS_CMS_Pos) /*!< VADC_G ICLASS: CMS Mask */\r
+#define VADC_G_ICLASS_STCE_Pos 16 /*!< VADC_G ICLASS: STCE Position */\r
+#define VADC_G_ICLASS_STCE_Msk (0x1fUL << VADC_G_ICLASS_STCE_Pos) /*!< VADC_G ICLASS: STCE Mask */\r
+#define VADC_G_ICLASS_CME_Pos 24 /*!< VADC_G ICLASS: CME Position */\r
+#define VADC_G_ICLASS_CME_Msk (0x07UL << VADC_G_ICLASS_CME_Pos) /*!< VADC_G ICLASS: CME Mask */\r
+\r
+/* -------------------------------- VADC_G_ALIAS -------------------------------- */\r
+#define VADC_G_ALIAS_ALIAS0_Pos 0 /*!< VADC_G ALIAS: ALIAS0 Position */\r
+#define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL << VADC_G_ALIAS_ALIAS0_Pos) /*!< VADC_G ALIAS: ALIAS0 Mask */\r
+#define VADC_G_ALIAS_ALIAS1_Pos 8 /*!< VADC_G ALIAS: ALIAS1 Position */\r
+#define VADC_G_ALIAS_ALIAS1_Msk (0x1fUL << VADC_G_ALIAS_ALIAS1_Pos) /*!< VADC_G ALIAS: ALIAS1 Mask */\r
+\r
+/* -------------------------------- VADC_G_BOUND -------------------------------- */\r
+#define VADC_G_BOUND_BOUNDARY0_Pos 0 /*!< VADC_G BOUND: BOUNDARY0 Position */\r
+#define VADC_G_BOUND_BOUNDARY0_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY0_Pos) /*!< VADC_G BOUND: BOUNDARY0 Mask */\r
+#define VADC_G_BOUND_BOUNDARY1_Pos 16 /*!< VADC_G BOUND: BOUNDARY1 Position */\r
+#define VADC_G_BOUND_BOUNDARY1_Msk (0x00000fffUL << VADC_G_BOUND_BOUNDARY1_Pos) /*!< VADC_G BOUND: BOUNDARY1 Mask */\r
+\r
+/* -------------------------------- VADC_G_SYNCTR ------------------------------- */\r
+#define VADC_G_SYNCTR_STSEL_Pos 0 /*!< VADC_G SYNCTR: STSEL Position */\r
+#define VADC_G_SYNCTR_STSEL_Msk (0x03UL << VADC_G_SYNCTR_STSEL_Pos) /*!< VADC_G SYNCTR: STSEL Mask */\r
+#define VADC_G_SYNCTR_EVALR1_Pos 4 /*!< VADC_G SYNCTR: EVALR1 Position */\r
+#define VADC_G_SYNCTR_EVALR1_Msk (0x01UL << VADC_G_SYNCTR_EVALR1_Pos) /*!< VADC_G SYNCTR: EVALR1 Mask */\r
+\r
+/* --------------------------------- VADC_G_BFL --------------------------------- */\r
+#define VADC_G_BFL_BFL0_Pos 0 /*!< VADC_G BFL: BFL0 Position */\r
+#define VADC_G_BFL_BFL0_Msk (0x01UL << VADC_G_BFL_BFL0_Pos) /*!< VADC_G BFL: BFL0 Mask */\r
+#define VADC_G_BFL_BFL1_Pos 1 /*!< VADC_G BFL: BFL1 Position */\r
+#define VADC_G_BFL_BFL1_Msk (0x01UL << VADC_G_BFL_BFL1_Pos) /*!< VADC_G BFL: BFL1 Mask */\r
+#define VADC_G_BFL_BFL2_Pos 2 /*!< VADC_G BFL: BFL2 Position */\r
+#define VADC_G_BFL_BFL2_Msk (0x01UL << VADC_G_BFL_BFL2_Pos) /*!< VADC_G BFL: BFL2 Mask */\r
+#define VADC_G_BFL_BFL3_Pos 3 /*!< VADC_G BFL: BFL3 Position */\r
+#define VADC_G_BFL_BFL3_Msk (0x01UL << VADC_G_BFL_BFL3_Pos) /*!< VADC_G BFL: BFL3 Mask */\r
+#define VADC_G_BFL_BFA0_Pos 8 /*!< VADC_G BFL: BFA0 Position */\r
+#define VADC_G_BFL_BFA0_Msk (0x01UL << VADC_G_BFL_BFA0_Pos) /*!< VADC_G BFL: BFA0 Mask */\r
+#define VADC_G_BFL_BFA1_Pos 9 /*!< VADC_G BFL: BFA1 Position */\r
+#define VADC_G_BFL_BFA1_Msk (0x01UL << VADC_G_BFL_BFA1_Pos) /*!< VADC_G BFL: BFA1 Mask */\r
+#define VADC_G_BFL_BFA2_Pos 10 /*!< VADC_G BFL: BFA2 Position */\r
+#define VADC_G_BFL_BFA2_Msk (0x01UL << VADC_G_BFL_BFA2_Pos) /*!< VADC_G BFL: BFA2 Mask */\r
+#define VADC_G_BFL_BFA3_Pos 11 /*!< VADC_G BFL: BFA3 Position */\r
+#define VADC_G_BFL_BFA3_Msk (0x01UL << VADC_G_BFL_BFA3_Pos) /*!< VADC_G BFL: BFA3 Mask */\r
+#define VADC_G_BFL_BFI0_Pos 16 /*!< VADC_G BFL: BFI0 Position */\r
+#define VADC_G_BFL_BFI0_Msk (0x01UL << VADC_G_BFL_BFI0_Pos) /*!< VADC_G BFL: BFI0 Mask */\r
+#define VADC_G_BFL_BFI1_Pos 17 /*!< VADC_G BFL: BFI1 Position */\r
+#define VADC_G_BFL_BFI1_Msk (0x01UL << VADC_G_BFL_BFI1_Pos) /*!< VADC_G BFL: BFI1 Mask */\r
+#define VADC_G_BFL_BFI2_Pos 18 /*!< VADC_G BFL: BFI2 Position */\r
+#define VADC_G_BFL_BFI2_Msk (0x01UL << VADC_G_BFL_BFI2_Pos) /*!< VADC_G BFL: BFI2 Mask */\r
+#define VADC_G_BFL_BFI3_Pos 19 /*!< VADC_G BFL: BFI3 Position */\r
+#define VADC_G_BFL_BFI3_Msk (0x01UL << VADC_G_BFL_BFI3_Pos) /*!< VADC_G BFL: BFI3 Mask */\r
+\r
+/* --------------------------------- VADC_G_BFLS -------------------------------- */\r
+#define VADC_G_BFLS_BFC0_Pos 0 /*!< VADC_G BFLS: BFC0 Position */\r
+#define VADC_G_BFLS_BFC0_Msk (0x01UL << VADC_G_BFLS_BFC0_Pos) /*!< VADC_G BFLS: BFC0 Mask */\r
+#define VADC_G_BFLS_BFC1_Pos 1 /*!< VADC_G BFLS: BFC1 Position */\r
+#define VADC_G_BFLS_BFC1_Msk (0x01UL << VADC_G_BFLS_BFC1_Pos) /*!< VADC_G BFLS: BFC1 Mask */\r
+#define VADC_G_BFLS_BFC2_Pos 2 /*!< VADC_G BFLS: BFC2 Position */\r
+#define VADC_G_BFLS_BFC2_Msk (0x01UL << VADC_G_BFLS_BFC2_Pos) /*!< VADC_G BFLS: BFC2 Mask */\r
+#define VADC_G_BFLS_BFC3_Pos 3 /*!< VADC_G BFLS: BFC3 Position */\r
+#define VADC_G_BFLS_BFC3_Msk (0x01UL << VADC_G_BFLS_BFC3_Pos) /*!< VADC_G BFLS: BFC3 Mask */\r
+#define VADC_G_BFLS_BFS0_Pos 16 /*!< VADC_G BFLS: BFS0 Position */\r
+#define VADC_G_BFLS_BFS0_Msk (0x01UL << VADC_G_BFLS_BFS0_Pos) /*!< VADC_G BFLS: BFS0 Mask */\r
+#define VADC_G_BFLS_BFS1_Pos 17 /*!< VADC_G BFLS: BFS1 Position */\r
+#define VADC_G_BFLS_BFS1_Msk (0x01UL << VADC_G_BFLS_BFS1_Pos) /*!< VADC_G BFLS: BFS1 Mask */\r
+#define VADC_G_BFLS_BFS2_Pos 18 /*!< VADC_G BFLS: BFS2 Position */\r
+#define VADC_G_BFLS_BFS2_Msk (0x01UL << VADC_G_BFLS_BFS2_Pos) /*!< VADC_G BFLS: BFS2 Mask */\r
+#define VADC_G_BFLS_BFS3_Pos 19 /*!< VADC_G BFLS: BFS3 Position */\r
+#define VADC_G_BFLS_BFS3_Msk (0x01UL << VADC_G_BFLS_BFS3_Pos) /*!< VADC_G BFLS: BFS3 Mask */\r
+\r
+/* --------------------------------- VADC_G_BFLC -------------------------------- */\r
+#define VADC_G_BFLC_BFM0_Pos 0 /*!< VADC_G BFLC: BFM0 Position */\r
+#define VADC_G_BFLC_BFM0_Msk (0x0fUL << VADC_G_BFLC_BFM0_Pos) /*!< VADC_G BFLC: BFM0 Mask */\r
+#define VADC_G_BFLC_BFM1_Pos 4 /*!< VADC_G BFLC: BFM1 Position */\r
+#define VADC_G_BFLC_BFM1_Msk (0x0fUL << VADC_G_BFLC_BFM1_Pos) /*!< VADC_G BFLC: BFM1 Mask */\r
+#define VADC_G_BFLC_BFM2_Pos 8 /*!< VADC_G BFLC: BFM2 Position */\r
+#define VADC_G_BFLC_BFM2_Msk (0x0fUL << VADC_G_BFLC_BFM2_Pos) /*!< VADC_G BFLC: BFM2 Mask */\r
+#define VADC_G_BFLC_BFM3_Pos 12 /*!< VADC_G BFLC: BFM3 Position */\r
+#define VADC_G_BFLC_BFM3_Msk (0x0fUL << VADC_G_BFLC_BFM3_Pos) /*!< VADC_G BFLC: BFM3 Mask */\r
+\r
+/* -------------------------------- VADC_G_BFLNP -------------------------------- */\r
+#define VADC_G_BFLNP_BFL0NP_Pos 0 /*!< VADC_G BFLNP: BFL0NP Position */\r
+#define VADC_G_BFLNP_BFL0NP_Msk (0x0fUL << VADC_G_BFLNP_BFL0NP_Pos) /*!< VADC_G BFLNP: BFL0NP Mask */\r
+#define VADC_G_BFLNP_BFL1NP_Pos 4 /*!< VADC_G BFLNP: BFL1NP Position */\r
+#define VADC_G_BFLNP_BFL1NP_Msk (0x0fUL << VADC_G_BFLNP_BFL1NP_Pos) /*!< VADC_G BFLNP: BFL1NP Mask */\r
+#define VADC_G_BFLNP_BFL2NP_Pos 8 /*!< VADC_G BFLNP: BFL2NP Position */\r
+#define VADC_G_BFLNP_BFL2NP_Msk (0x0fUL << VADC_G_BFLNP_BFL2NP_Pos) /*!< VADC_G BFLNP: BFL2NP Mask */\r
+#define VADC_G_BFLNP_BFL3NP_Pos 12 /*!< VADC_G BFLNP: BFL3NP Position */\r
+#define VADC_G_BFLNP_BFL3NP_Msk (0x0fUL << VADC_G_BFLNP_BFL3NP_Pos) /*!< VADC_G BFLNP: BFL3NP Mask */\r
+\r
+/* -------------------------------- VADC_G_QCTRL0 ------------------------------- */\r
+#define VADC_G_QCTRL0_SRCRESREG_Pos 0 /*!< VADC_G QCTRL0: SRCRESREG Position */\r
+#define VADC_G_QCTRL0_SRCRESREG_Msk (0x0fUL << VADC_G_QCTRL0_SRCRESREG_Pos) /*!< VADC_G QCTRL0: SRCRESREG Mask */\r
+#define VADC_G_QCTRL0_XTSEL_Pos 8 /*!< VADC_G QCTRL0: XTSEL Position */\r
+#define VADC_G_QCTRL0_XTSEL_Msk (0x0fUL << VADC_G_QCTRL0_XTSEL_Pos) /*!< VADC_G QCTRL0: XTSEL Mask */\r
+#define VADC_G_QCTRL0_XTLVL_Pos 12 /*!< VADC_G QCTRL0: XTLVL Position */\r
+#define VADC_G_QCTRL0_XTLVL_Msk (0x01UL << VADC_G_QCTRL0_XTLVL_Pos) /*!< VADC_G QCTRL0: XTLVL Mask */\r
+#define VADC_G_QCTRL0_XTMODE_Pos 13 /*!< VADC_G QCTRL0: XTMODE Position */\r
+#define VADC_G_QCTRL0_XTMODE_Msk (0x03UL << VADC_G_QCTRL0_XTMODE_Pos) /*!< VADC_G QCTRL0: XTMODE Mask */\r
+#define VADC_G_QCTRL0_XTWC_Pos 15 /*!< VADC_G QCTRL0: XTWC Position */\r
+#define VADC_G_QCTRL0_XTWC_Msk (0x01UL << VADC_G_QCTRL0_XTWC_Pos) /*!< VADC_G QCTRL0: XTWC Mask */\r
+#define VADC_G_QCTRL0_GTSEL_Pos 16 /*!< VADC_G QCTRL0: GTSEL Position */\r
+#define VADC_G_QCTRL0_GTSEL_Msk (0x0fUL << VADC_G_QCTRL0_GTSEL_Pos) /*!< VADC_G QCTRL0: GTSEL Mask */\r
+#define VADC_G_QCTRL0_GTLVL_Pos 20 /*!< VADC_G QCTRL0: GTLVL Position */\r
+#define VADC_G_QCTRL0_GTLVL_Msk (0x01UL << VADC_G_QCTRL0_GTLVL_Pos) /*!< VADC_G QCTRL0: GTLVL Mask */\r
+#define VADC_G_QCTRL0_GTWC_Pos 23 /*!< VADC_G QCTRL0: GTWC Position */\r
+#define VADC_G_QCTRL0_GTWC_Msk (0x01UL << VADC_G_QCTRL0_GTWC_Pos) /*!< VADC_G QCTRL0: GTWC Mask */\r
+#define VADC_G_QCTRL0_TMEN_Pos 28 /*!< VADC_G QCTRL0: TMEN Position */\r
+#define VADC_G_QCTRL0_TMEN_Msk (0x01UL << VADC_G_QCTRL0_TMEN_Pos) /*!< VADC_G QCTRL0: TMEN Mask */\r
+#define VADC_G_QCTRL0_TMWC_Pos 31 /*!< VADC_G QCTRL0: TMWC Position */\r
+#define VADC_G_QCTRL0_TMWC_Msk (0x01UL << VADC_G_QCTRL0_TMWC_Pos) /*!< VADC_G QCTRL0: TMWC Mask */\r
+\r
+/* --------------------------------- VADC_G_QMR0 -------------------------------- */\r
+#define VADC_G_QMR0_ENGT_Pos 0 /*!< VADC_G QMR0: ENGT Position */\r
+#define VADC_G_QMR0_ENGT_Msk (0x03UL << VADC_G_QMR0_ENGT_Pos) /*!< VADC_G QMR0: ENGT Mask */\r
+#define VADC_G_QMR0_ENTR_Pos 2 /*!< VADC_G QMR0: ENTR Position */\r
+#define VADC_G_QMR0_ENTR_Msk (0x01UL << VADC_G_QMR0_ENTR_Pos) /*!< VADC_G QMR0: ENTR Mask */\r
+#define VADC_G_QMR0_CLRV_Pos 8 /*!< VADC_G QMR0: CLRV Position */\r
+#define VADC_G_QMR0_CLRV_Msk (0x01UL << VADC_G_QMR0_CLRV_Pos) /*!< VADC_G QMR0: CLRV Mask */\r
+#define VADC_G_QMR0_TREV_Pos 9 /*!< VADC_G QMR0: TREV Position */\r
+#define VADC_G_QMR0_TREV_Msk (0x01UL << VADC_G_QMR0_TREV_Pos) /*!< VADC_G QMR0: TREV Mask */\r
+#define VADC_G_QMR0_FLUSH_Pos 10 /*!< VADC_G QMR0: FLUSH Position */\r
+#define VADC_G_QMR0_FLUSH_Msk (0x01UL << VADC_G_QMR0_FLUSH_Pos) /*!< VADC_G QMR0: FLUSH Mask */\r
+#define VADC_G_QMR0_CEV_Pos 11 /*!< VADC_G QMR0: CEV Position */\r
+#define VADC_G_QMR0_CEV_Msk (0x01UL << VADC_G_QMR0_CEV_Pos) /*!< VADC_G QMR0: CEV Mask */\r
+#define VADC_G_QMR0_RPTDIS_Pos 16 /*!< VADC_G QMR0: RPTDIS Position */\r
+#define VADC_G_QMR0_RPTDIS_Msk (0x01UL << VADC_G_QMR0_RPTDIS_Pos) /*!< VADC_G QMR0: RPTDIS Mask */\r
+\r
+/* --------------------------------- VADC_G_QSR0 -------------------------------- */\r
+#define VADC_G_QSR0_FILL_Pos 0 /*!< VADC_G QSR0: FILL Position */\r
+#define VADC_G_QSR0_FILL_Msk (0x0fUL << VADC_G_QSR0_FILL_Pos) /*!< VADC_G QSR0: FILL Mask */\r
+#define VADC_G_QSR0_EMPTY_Pos 5 /*!< VADC_G QSR0: EMPTY Position */\r
+#define VADC_G_QSR0_EMPTY_Msk (0x01UL << VADC_G_QSR0_EMPTY_Pos) /*!< VADC_G QSR0: EMPTY Mask */\r
+#define VADC_G_QSR0_REQGT_Pos 7 /*!< VADC_G QSR0: REQGT Position */\r
+#define VADC_G_QSR0_REQGT_Msk (0x01UL << VADC_G_QSR0_REQGT_Pos) /*!< VADC_G QSR0: REQGT Mask */\r
+#define VADC_G_QSR0_EV_Pos 8 /*!< VADC_G QSR0: EV Position */\r
+#define VADC_G_QSR0_EV_Msk (0x01UL << VADC_G_QSR0_EV_Pos) /*!< VADC_G QSR0: EV Mask */\r
+\r
+/* --------------------------------- VADC_G_Q0R0 -------------------------------- */\r
+#define VADC_G_Q0R0_REQCHNR_Pos 0 /*!< VADC_G Q0R0: REQCHNR Position */\r
+#define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL << VADC_G_Q0R0_REQCHNR_Pos) /*!< VADC_G Q0R0: REQCHNR Mask */\r
+#define VADC_G_Q0R0_RF_Pos 5 /*!< VADC_G Q0R0: RF Position */\r
+#define VADC_G_Q0R0_RF_Msk (0x01UL << VADC_G_Q0R0_RF_Pos) /*!< VADC_G Q0R0: RF Mask */\r
+#define VADC_G_Q0R0_ENSI_Pos 6 /*!< VADC_G Q0R0: ENSI Position */\r
+#define VADC_G_Q0R0_ENSI_Msk (0x01UL << VADC_G_Q0R0_ENSI_Pos) /*!< VADC_G Q0R0: ENSI Mask */\r
+#define VADC_G_Q0R0_EXTR_Pos 7 /*!< VADC_G Q0R0: EXTR Position */\r
+#define VADC_G_Q0R0_EXTR_Msk (0x01UL << VADC_G_Q0R0_EXTR_Pos) /*!< VADC_G Q0R0: EXTR Mask */\r
+#define VADC_G_Q0R0_V_Pos 8 /*!< VADC_G Q0R0: V Position */\r
+#define VADC_G_Q0R0_V_Msk (0x01UL << VADC_G_Q0R0_V_Pos) /*!< VADC_G Q0R0: V Mask */\r
+\r
+/* -------------------------------- VADC_G_QINR0 -------------------------------- */\r
+#define VADC_G_QINR0_REQCHNR_Pos 0 /*!< VADC_G QINR0: REQCHNR Position */\r
+#define VADC_G_QINR0_REQCHNR_Msk (0x1fUL << VADC_G_QINR0_REQCHNR_Pos) /*!< VADC_G QINR0: REQCHNR Mask */\r
+#define VADC_G_QINR0_RF_Pos 5 /*!< VADC_G QINR0: RF Position */\r
+#define VADC_G_QINR0_RF_Msk (0x01UL << VADC_G_QINR0_RF_Pos) /*!< VADC_G QINR0: RF Mask */\r
+#define VADC_G_QINR0_ENSI_Pos 6 /*!< VADC_G QINR0: ENSI Position */\r
+#define VADC_G_QINR0_ENSI_Msk (0x01UL << VADC_G_QINR0_ENSI_Pos) /*!< VADC_G QINR0: ENSI Mask */\r
+#define VADC_G_QINR0_EXTR_Pos 7 /*!< VADC_G QINR0: EXTR Position */\r
+#define VADC_G_QINR0_EXTR_Msk (0x01UL << VADC_G_QINR0_EXTR_Pos) /*!< VADC_G QINR0: EXTR Mask */\r
+\r
+/* -------------------------------- VADC_G_QBUR0 -------------------------------- */\r
+#define VADC_G_QBUR0_REQCHNR_Pos 0 /*!< VADC_G QBUR0: REQCHNR Position */\r
+#define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL << VADC_G_QBUR0_REQCHNR_Pos) /*!< VADC_G QBUR0: REQCHNR Mask */\r
+#define VADC_G_QBUR0_RF_Pos 5 /*!< VADC_G QBUR0: RF Position */\r
+#define VADC_G_QBUR0_RF_Msk (0x01UL << VADC_G_QBUR0_RF_Pos) /*!< VADC_G QBUR0: RF Mask */\r
+#define VADC_G_QBUR0_ENSI_Pos 6 /*!< VADC_G QBUR0: ENSI Position */\r
+#define VADC_G_QBUR0_ENSI_Msk (0x01UL << VADC_G_QBUR0_ENSI_Pos) /*!< VADC_G QBUR0: ENSI Mask */\r
+#define VADC_G_QBUR0_EXTR_Pos 7 /*!< VADC_G QBUR0: EXTR Position */\r
+#define VADC_G_QBUR0_EXTR_Msk (0x01UL << VADC_G_QBUR0_EXTR_Pos) /*!< VADC_G QBUR0: EXTR Mask */\r
+#define VADC_G_QBUR0_V_Pos 8 /*!< VADC_G QBUR0: V Position */\r
+#define VADC_G_QBUR0_V_Msk (0x01UL << VADC_G_QBUR0_V_Pos) /*!< VADC_G QBUR0: V Mask */\r
+\r
+/* -------------------------------- VADC_G_ASCTRL ------------------------------- */\r
+#define VADC_G_ASCTRL_SRCRESREG_Pos 0 /*!< VADC_G ASCTRL: SRCRESREG Position */\r
+#define VADC_G_ASCTRL_SRCRESREG_Msk (0x0fUL << VADC_G_ASCTRL_SRCRESREG_Pos) /*!< VADC_G ASCTRL: SRCRESREG Mask */\r
+#define VADC_G_ASCTRL_XTSEL_Pos 8 /*!< VADC_G ASCTRL: XTSEL Position */\r
+#define VADC_G_ASCTRL_XTSEL_Msk (0x0fUL << VADC_G_ASCTRL_XTSEL_Pos) /*!< VADC_G ASCTRL: XTSEL Mask */\r
+#define VADC_G_ASCTRL_XTLVL_Pos 12 /*!< VADC_G ASCTRL: XTLVL Position */\r
+#define VADC_G_ASCTRL_XTLVL_Msk (0x01UL << VADC_G_ASCTRL_XTLVL_Pos) /*!< VADC_G ASCTRL: XTLVL Mask */\r
+#define VADC_G_ASCTRL_XTMODE_Pos 13 /*!< VADC_G ASCTRL: XTMODE Position */\r
+#define VADC_G_ASCTRL_XTMODE_Msk (0x03UL << VADC_G_ASCTRL_XTMODE_Pos) /*!< VADC_G ASCTRL: XTMODE Mask */\r
+#define VADC_G_ASCTRL_XTWC_Pos 15 /*!< VADC_G ASCTRL: XTWC Position */\r
+#define VADC_G_ASCTRL_XTWC_Msk (0x01UL << VADC_G_ASCTRL_XTWC_Pos) /*!< VADC_G ASCTRL: XTWC Mask */\r
+#define VADC_G_ASCTRL_GTSEL_Pos 16 /*!< VADC_G ASCTRL: GTSEL Position */\r
+#define VADC_G_ASCTRL_GTSEL_Msk (0x0fUL << VADC_G_ASCTRL_GTSEL_Pos) /*!< VADC_G ASCTRL: GTSEL Mask */\r
+#define VADC_G_ASCTRL_GTLVL_Pos 20 /*!< VADC_G ASCTRL: GTLVL Position */\r
+#define VADC_G_ASCTRL_GTLVL_Msk (0x01UL << VADC_G_ASCTRL_GTLVL_Pos) /*!< VADC_G ASCTRL: GTLVL Mask */\r
+#define VADC_G_ASCTRL_GTWC_Pos 23 /*!< VADC_G ASCTRL: GTWC Position */\r
+#define VADC_G_ASCTRL_GTWC_Msk (0x01UL << VADC_G_ASCTRL_GTWC_Pos) /*!< VADC_G ASCTRL: GTWC Mask */\r
+#define VADC_G_ASCTRL_TMEN_Pos 28 /*!< VADC_G ASCTRL: TMEN Position */\r
+#define VADC_G_ASCTRL_TMEN_Msk (0x01UL << VADC_G_ASCTRL_TMEN_Pos) /*!< VADC_G ASCTRL: TMEN Mask */\r
+#define VADC_G_ASCTRL_TMWC_Pos 31 /*!< VADC_G ASCTRL: TMWC Position */\r
+#define VADC_G_ASCTRL_TMWC_Msk (0x01UL << VADC_G_ASCTRL_TMWC_Pos) /*!< VADC_G ASCTRL: TMWC Mask */\r
+\r
+/* --------------------------------- VADC_G_ASMR -------------------------------- */\r
+#define VADC_G_ASMR_ENGT_Pos 0 /*!< VADC_G ASMR: ENGT Position */\r
+#define VADC_G_ASMR_ENGT_Msk (0x03UL << VADC_G_ASMR_ENGT_Pos) /*!< VADC_G ASMR: ENGT Mask */\r
+#define VADC_G_ASMR_ENTR_Pos 2 /*!< VADC_G ASMR: ENTR Position */\r
+#define VADC_G_ASMR_ENTR_Msk (0x01UL << VADC_G_ASMR_ENTR_Pos) /*!< VADC_G ASMR: ENTR Mask */\r
+#define VADC_G_ASMR_ENSI_Pos 3 /*!< VADC_G ASMR: ENSI Position */\r
+#define VADC_G_ASMR_ENSI_Msk (0x01UL << VADC_G_ASMR_ENSI_Pos) /*!< VADC_G ASMR: ENSI Mask */\r
+#define VADC_G_ASMR_SCAN_Pos 4 /*!< VADC_G ASMR: SCAN Position */\r
+#define VADC_G_ASMR_SCAN_Msk (0x01UL << VADC_G_ASMR_SCAN_Pos) /*!< VADC_G ASMR: SCAN Mask */\r
+#define VADC_G_ASMR_LDM_Pos 5 /*!< VADC_G ASMR: LDM Position */\r
+#define VADC_G_ASMR_LDM_Msk (0x01UL << VADC_G_ASMR_LDM_Pos) /*!< VADC_G ASMR: LDM Mask */\r
+#define VADC_G_ASMR_REQGT_Pos 7 /*!< VADC_G ASMR: REQGT Position */\r
+#define VADC_G_ASMR_REQGT_Msk (0x01UL << VADC_G_ASMR_REQGT_Pos) /*!< VADC_G ASMR: REQGT Mask */\r
+#define VADC_G_ASMR_CLRPND_Pos 8 /*!< VADC_G ASMR: CLRPND Position */\r
+#define VADC_G_ASMR_CLRPND_Msk (0x01UL << VADC_G_ASMR_CLRPND_Pos) /*!< VADC_G ASMR: CLRPND Mask */\r
+#define VADC_G_ASMR_LDEV_Pos 9 /*!< VADC_G ASMR: LDEV Position */\r
+#define VADC_G_ASMR_LDEV_Msk (0x01UL << VADC_G_ASMR_LDEV_Pos) /*!< VADC_G ASMR: LDEV Mask */\r
+#define VADC_G_ASMR_RPTDIS_Pos 16 /*!< VADC_G ASMR: RPTDIS Position */\r
+#define VADC_G_ASMR_RPTDIS_Msk (0x01UL << VADC_G_ASMR_RPTDIS_Pos) /*!< VADC_G ASMR: RPTDIS Mask */\r
+\r
+/* -------------------------------- VADC_G_ASSEL -------------------------------- */\r
+#define VADC_G_ASSEL_CHSEL0_Pos 0 /*!< VADC_G ASSEL: CHSEL0 Position */\r
+#define VADC_G_ASSEL_CHSEL0_Msk (0x01UL << VADC_G_ASSEL_CHSEL0_Pos) /*!< VADC_G ASSEL: CHSEL0 Mask */\r
+#define VADC_G_ASSEL_CHSEL1_Pos 1 /*!< VADC_G ASSEL: CHSEL1 Position */\r
+#define VADC_G_ASSEL_CHSEL1_Msk (0x01UL << VADC_G_ASSEL_CHSEL1_Pos) /*!< VADC_G ASSEL: CHSEL1 Mask */\r
+#define VADC_G_ASSEL_CHSEL2_Pos 2 /*!< VADC_G ASSEL: CHSEL2 Position */\r
+#define VADC_G_ASSEL_CHSEL2_Msk (0x01UL << VADC_G_ASSEL_CHSEL2_Pos) /*!< VADC_G ASSEL: CHSEL2 Mask */\r
+#define VADC_G_ASSEL_CHSEL3_Pos 3 /*!< VADC_G ASSEL: CHSEL3 Position */\r
+#define VADC_G_ASSEL_CHSEL3_Msk (0x01UL << VADC_G_ASSEL_CHSEL3_Pos) /*!< VADC_G ASSEL: CHSEL3 Mask */\r
+#define VADC_G_ASSEL_CHSEL4_Pos 4 /*!< VADC_G ASSEL: CHSEL4 Position */\r
+#define VADC_G_ASSEL_CHSEL4_Msk (0x01UL << VADC_G_ASSEL_CHSEL4_Pos) /*!< VADC_G ASSEL: CHSEL4 Mask */\r
+#define VADC_G_ASSEL_CHSEL5_Pos 5 /*!< VADC_G ASSEL: CHSEL5 Position */\r
+#define VADC_G_ASSEL_CHSEL5_Msk (0x01UL << VADC_G_ASSEL_CHSEL5_Pos) /*!< VADC_G ASSEL: CHSEL5 Mask */\r
+#define VADC_G_ASSEL_CHSEL6_Pos 6 /*!< VADC_G ASSEL: CHSEL6 Position */\r
+#define VADC_G_ASSEL_CHSEL6_Msk (0x01UL << VADC_G_ASSEL_CHSEL6_Pos) /*!< VADC_G ASSEL: CHSEL6 Mask */\r
+#define VADC_G_ASSEL_CHSEL7_Pos 7 /*!< VADC_G ASSEL: CHSEL7 Position */\r
+#define VADC_G_ASSEL_CHSEL7_Msk (0x01UL << VADC_G_ASSEL_CHSEL7_Pos) /*!< VADC_G ASSEL: CHSEL7 Mask */\r
+\r
+/* -------------------------------- VADC_G_ASPND -------------------------------- */\r
+#define VADC_G_ASPND_CHPND0_Pos 0 /*!< VADC_G ASPND: CHPND0 Position */\r
+#define VADC_G_ASPND_CHPND0_Msk (0x01UL << VADC_G_ASPND_CHPND0_Pos) /*!< VADC_G ASPND: CHPND0 Mask */\r
+#define VADC_G_ASPND_CHPND1_Pos 1 /*!< VADC_G ASPND: CHPND1 Position */\r
+#define VADC_G_ASPND_CHPND1_Msk (0x01UL << VADC_G_ASPND_CHPND1_Pos) /*!< VADC_G ASPND: CHPND1 Mask */\r
+#define VADC_G_ASPND_CHPND2_Pos 2 /*!< VADC_G ASPND: CHPND2 Position */\r
+#define VADC_G_ASPND_CHPND2_Msk (0x01UL << VADC_G_ASPND_CHPND2_Pos) /*!< VADC_G ASPND: CHPND2 Mask */\r
+#define VADC_G_ASPND_CHPND3_Pos 3 /*!< VADC_G ASPND: CHPND3 Position */\r
+#define VADC_G_ASPND_CHPND3_Msk (0x01UL << VADC_G_ASPND_CHPND3_Pos) /*!< VADC_G ASPND: CHPND3 Mask */\r
+#define VADC_G_ASPND_CHPND4_Pos 4 /*!< VADC_G ASPND: CHPND4 Position */\r
+#define VADC_G_ASPND_CHPND4_Msk (0x01UL << VADC_G_ASPND_CHPND4_Pos) /*!< VADC_G ASPND: CHPND4 Mask */\r
+#define VADC_G_ASPND_CHPND5_Pos 5 /*!< VADC_G ASPND: CHPND5 Position */\r
+#define VADC_G_ASPND_CHPND5_Msk (0x01UL << VADC_G_ASPND_CHPND5_Pos) /*!< VADC_G ASPND: CHPND5 Mask */\r
+#define VADC_G_ASPND_CHPND6_Pos 6 /*!< VADC_G ASPND: CHPND6 Position */\r
+#define VADC_G_ASPND_CHPND6_Msk (0x01UL << VADC_G_ASPND_CHPND6_Pos) /*!< VADC_G ASPND: CHPND6 Mask */\r
+#define VADC_G_ASPND_CHPND7_Pos 7 /*!< VADC_G ASPND: CHPND7 Position */\r
+#define VADC_G_ASPND_CHPND7_Msk (0x01UL << VADC_G_ASPND_CHPND7_Pos) /*!< VADC_G ASPND: CHPND7 Mask */\r
+\r
+/* -------------------------------- VADC_G_CEFLAG ------------------------------- */\r
+#define VADC_G_CEFLAG_CEV0_Pos 0 /*!< VADC_G CEFLAG: CEV0 Position */\r
+#define VADC_G_CEFLAG_CEV0_Msk (0x01UL << VADC_G_CEFLAG_CEV0_Pos) /*!< VADC_G CEFLAG: CEV0 Mask */\r
+#define VADC_G_CEFLAG_CEV1_Pos 1 /*!< VADC_G CEFLAG: CEV1 Position */\r
+#define VADC_G_CEFLAG_CEV1_Msk (0x01UL << VADC_G_CEFLAG_CEV1_Pos) /*!< VADC_G CEFLAG: CEV1 Mask */\r
+#define VADC_G_CEFLAG_CEV2_Pos 2 /*!< VADC_G CEFLAG: CEV2 Position */\r
+#define VADC_G_CEFLAG_CEV2_Msk (0x01UL << VADC_G_CEFLAG_CEV2_Pos) /*!< VADC_G CEFLAG: CEV2 Mask */\r
+#define VADC_G_CEFLAG_CEV3_Pos 3 /*!< VADC_G CEFLAG: CEV3 Position */\r
+#define VADC_G_CEFLAG_CEV3_Msk (0x01UL << VADC_G_CEFLAG_CEV3_Pos) /*!< VADC_G CEFLAG: CEV3 Mask */\r
+#define VADC_G_CEFLAG_CEV4_Pos 4 /*!< VADC_G CEFLAG: CEV4 Position */\r
+#define VADC_G_CEFLAG_CEV4_Msk (0x01UL << VADC_G_CEFLAG_CEV4_Pos) /*!< VADC_G CEFLAG: CEV4 Mask */\r
+#define VADC_G_CEFLAG_CEV5_Pos 5 /*!< VADC_G CEFLAG: CEV5 Position */\r
+#define VADC_G_CEFLAG_CEV5_Msk (0x01UL << VADC_G_CEFLAG_CEV5_Pos) /*!< VADC_G CEFLAG: CEV5 Mask */\r
+#define VADC_G_CEFLAG_CEV6_Pos 6 /*!< VADC_G CEFLAG: CEV6 Position */\r
+#define VADC_G_CEFLAG_CEV6_Msk (0x01UL << VADC_G_CEFLAG_CEV6_Pos) /*!< VADC_G CEFLAG: CEV6 Mask */\r
+#define VADC_G_CEFLAG_CEV7_Pos 7 /*!< VADC_G CEFLAG: CEV7 Position */\r
+#define VADC_G_CEFLAG_CEV7_Msk (0x01UL << VADC_G_CEFLAG_CEV7_Pos) /*!< VADC_G CEFLAG: CEV7 Mask */\r
+\r
+/* -------------------------------- VADC_G_REFLAG ------------------------------- */\r
+#define VADC_G_REFLAG_REV0_Pos 0 /*!< VADC_G REFLAG: REV0 Position */\r
+#define VADC_G_REFLAG_REV0_Msk (0x01UL << VADC_G_REFLAG_REV0_Pos) /*!< VADC_G REFLAG: REV0 Mask */\r
+#define VADC_G_REFLAG_REV1_Pos 1 /*!< VADC_G REFLAG: REV1 Position */\r
+#define VADC_G_REFLAG_REV1_Msk (0x01UL << VADC_G_REFLAG_REV1_Pos) /*!< VADC_G REFLAG: REV1 Mask */\r
+#define VADC_G_REFLAG_REV2_Pos 2 /*!< VADC_G REFLAG: REV2 Position */\r
+#define VADC_G_REFLAG_REV2_Msk (0x01UL << VADC_G_REFLAG_REV2_Pos) /*!< VADC_G REFLAG: REV2 Mask */\r
+#define VADC_G_REFLAG_REV3_Pos 3 /*!< VADC_G REFLAG: REV3 Position */\r
+#define VADC_G_REFLAG_REV3_Msk (0x01UL << VADC_G_REFLAG_REV3_Pos) /*!< VADC_G REFLAG: REV3 Mask */\r
+#define VADC_G_REFLAG_REV4_Pos 4 /*!< VADC_G REFLAG: REV4 Position */\r
+#define VADC_G_REFLAG_REV4_Msk (0x01UL << VADC_G_REFLAG_REV4_Pos) /*!< VADC_G REFLAG: REV4 Mask */\r
+#define VADC_G_REFLAG_REV5_Pos 5 /*!< VADC_G REFLAG: REV5 Position */\r
+#define VADC_G_REFLAG_REV5_Msk (0x01UL << VADC_G_REFLAG_REV5_Pos) /*!< VADC_G REFLAG: REV5 Mask */\r
+#define VADC_G_REFLAG_REV6_Pos 6 /*!< VADC_G REFLAG: REV6 Position */\r
+#define VADC_G_REFLAG_REV6_Msk (0x01UL << VADC_G_REFLAG_REV6_Pos) /*!< VADC_G REFLAG: REV6 Mask */\r
+#define VADC_G_REFLAG_REV7_Pos 7 /*!< VADC_G REFLAG: REV7 Position */\r
+#define VADC_G_REFLAG_REV7_Msk (0x01UL << VADC_G_REFLAG_REV7_Pos) /*!< VADC_G REFLAG: REV7 Mask */\r
+#define VADC_G_REFLAG_REV8_Pos 8 /*!< VADC_G REFLAG: REV8 Position */\r
+#define VADC_G_REFLAG_REV8_Msk (0x01UL << VADC_G_REFLAG_REV8_Pos) /*!< VADC_G REFLAG: REV8 Mask */\r
+#define VADC_G_REFLAG_REV9_Pos 9 /*!< VADC_G REFLAG: REV9 Position */\r
+#define VADC_G_REFLAG_REV9_Msk (0x01UL << VADC_G_REFLAG_REV9_Pos) /*!< VADC_G REFLAG: REV9 Mask */\r
+#define VADC_G_REFLAG_REV10_Pos 10 /*!< VADC_G REFLAG: REV10 Position */\r
+#define VADC_G_REFLAG_REV10_Msk (0x01UL << VADC_G_REFLAG_REV10_Pos) /*!< VADC_G REFLAG: REV10 Mask */\r
+#define VADC_G_REFLAG_REV11_Pos 11 /*!< VADC_G REFLAG: REV11 Position */\r
+#define VADC_G_REFLAG_REV11_Msk (0x01UL << VADC_G_REFLAG_REV11_Pos) /*!< VADC_G REFLAG: REV11 Mask */\r
+#define VADC_G_REFLAG_REV12_Pos 12 /*!< VADC_G REFLAG: REV12 Position */\r
+#define VADC_G_REFLAG_REV12_Msk (0x01UL << VADC_G_REFLAG_REV12_Pos) /*!< VADC_G REFLAG: REV12 Mask */\r
+#define VADC_G_REFLAG_REV13_Pos 13 /*!< VADC_G REFLAG: REV13 Position */\r
+#define VADC_G_REFLAG_REV13_Msk (0x01UL << VADC_G_REFLAG_REV13_Pos) /*!< VADC_G REFLAG: REV13 Mask */\r
+#define VADC_G_REFLAG_REV14_Pos 14 /*!< VADC_G REFLAG: REV14 Position */\r
+#define VADC_G_REFLAG_REV14_Msk (0x01UL << VADC_G_REFLAG_REV14_Pos) /*!< VADC_G REFLAG: REV14 Mask */\r
+#define VADC_G_REFLAG_REV15_Pos 15 /*!< VADC_G REFLAG: REV15 Position */\r
+#define VADC_G_REFLAG_REV15_Msk (0x01UL << VADC_G_REFLAG_REV15_Pos) /*!< VADC_G REFLAG: REV15 Mask */\r
+\r
+/* -------------------------------- VADC_G_SEFLAG ------------------------------- */\r
+#define VADC_G_SEFLAG_SEV0_Pos 0 /*!< VADC_G SEFLAG: SEV0 Position */\r
+#define VADC_G_SEFLAG_SEV0_Msk (0x01UL << VADC_G_SEFLAG_SEV0_Pos) /*!< VADC_G SEFLAG: SEV0 Mask */\r
+#define VADC_G_SEFLAG_SEV1_Pos 1 /*!< VADC_G SEFLAG: SEV1 Position */\r
+#define VADC_G_SEFLAG_SEV1_Msk (0x01UL << VADC_G_SEFLAG_SEV1_Pos) /*!< VADC_G SEFLAG: SEV1 Mask */\r
+\r
+/* -------------------------------- VADC_G_CEFCLR ------------------------------- */\r
+#define VADC_G_CEFCLR_CEV0_Pos 0 /*!< VADC_G CEFCLR: CEV0 Position */\r
+#define VADC_G_CEFCLR_CEV0_Msk (0x01UL << VADC_G_CEFCLR_CEV0_Pos) /*!< VADC_G CEFCLR: CEV0 Mask */\r
+#define VADC_G_CEFCLR_CEV1_Pos 1 /*!< VADC_G CEFCLR: CEV1 Position */\r
+#define VADC_G_CEFCLR_CEV1_Msk (0x01UL << VADC_G_CEFCLR_CEV1_Pos) /*!< VADC_G CEFCLR: CEV1 Mask */\r
+#define VADC_G_CEFCLR_CEV2_Pos 2 /*!< VADC_G CEFCLR: CEV2 Position */\r
+#define VADC_G_CEFCLR_CEV2_Msk (0x01UL << VADC_G_CEFCLR_CEV2_Pos) /*!< VADC_G CEFCLR: CEV2 Mask */\r
+#define VADC_G_CEFCLR_CEV3_Pos 3 /*!< VADC_G CEFCLR: CEV3 Position */\r
+#define VADC_G_CEFCLR_CEV3_Msk (0x01UL << VADC_G_CEFCLR_CEV3_Pos) /*!< VADC_G CEFCLR: CEV3 Mask */\r
+#define VADC_G_CEFCLR_CEV4_Pos 4 /*!< VADC_G CEFCLR: CEV4 Position */\r
+#define VADC_G_CEFCLR_CEV4_Msk (0x01UL << VADC_G_CEFCLR_CEV4_Pos) /*!< VADC_G CEFCLR: CEV4 Mask */\r
+#define VADC_G_CEFCLR_CEV5_Pos 5 /*!< VADC_G CEFCLR: CEV5 Position */\r
+#define VADC_G_CEFCLR_CEV5_Msk (0x01UL << VADC_G_CEFCLR_CEV5_Pos) /*!< VADC_G CEFCLR: CEV5 Mask */\r
+#define VADC_G_CEFCLR_CEV6_Pos 6 /*!< VADC_G CEFCLR: CEV6 Position */\r
+#define VADC_G_CEFCLR_CEV6_Msk (0x01UL << VADC_G_CEFCLR_CEV6_Pos) /*!< VADC_G CEFCLR: CEV6 Mask */\r
+#define VADC_G_CEFCLR_CEV7_Pos 7 /*!< VADC_G CEFCLR: CEV7 Position */\r
+#define VADC_G_CEFCLR_CEV7_Msk (0x01UL << VADC_G_CEFCLR_CEV7_Pos) /*!< VADC_G CEFCLR: CEV7 Mask */\r
+\r
+/* -------------------------------- VADC_G_REFCLR ------------------------------- */\r
+#define VADC_G_REFCLR_REV0_Pos 0 /*!< VADC_G REFCLR: REV0 Position */\r
+#define VADC_G_REFCLR_REV0_Msk (0x01UL << VADC_G_REFCLR_REV0_Pos) /*!< VADC_G REFCLR: REV0 Mask */\r
+#define VADC_G_REFCLR_REV1_Pos 1 /*!< VADC_G REFCLR: REV1 Position */\r
+#define VADC_G_REFCLR_REV1_Msk (0x01UL << VADC_G_REFCLR_REV1_Pos) /*!< VADC_G REFCLR: REV1 Mask */\r
+#define VADC_G_REFCLR_REV2_Pos 2 /*!< VADC_G REFCLR: REV2 Position */\r
+#define VADC_G_REFCLR_REV2_Msk (0x01UL << VADC_G_REFCLR_REV2_Pos) /*!< VADC_G REFCLR: REV2 Mask */\r
+#define VADC_G_REFCLR_REV3_Pos 3 /*!< VADC_G REFCLR: REV3 Position */\r
+#define VADC_G_REFCLR_REV3_Msk (0x01UL << VADC_G_REFCLR_REV3_Pos) /*!< VADC_G REFCLR: REV3 Mask */\r
+#define VADC_G_REFCLR_REV4_Pos 4 /*!< VADC_G REFCLR: REV4 Position */\r
+#define VADC_G_REFCLR_REV4_Msk (0x01UL << VADC_G_REFCLR_REV4_Pos) /*!< VADC_G REFCLR: REV4 Mask */\r
+#define VADC_G_REFCLR_REV5_Pos 5 /*!< VADC_G REFCLR: REV5 Position */\r
+#define VADC_G_REFCLR_REV5_Msk (0x01UL << VADC_G_REFCLR_REV5_Pos) /*!< VADC_G REFCLR: REV5 Mask */\r
+#define VADC_G_REFCLR_REV6_Pos 6 /*!< VADC_G REFCLR: REV6 Position */\r
+#define VADC_G_REFCLR_REV6_Msk (0x01UL << VADC_G_REFCLR_REV6_Pos) /*!< VADC_G REFCLR: REV6 Mask */\r
+#define VADC_G_REFCLR_REV7_Pos 7 /*!< VADC_G REFCLR: REV7 Position */\r
+#define VADC_G_REFCLR_REV7_Msk (0x01UL << VADC_G_REFCLR_REV7_Pos) /*!< VADC_G REFCLR: REV7 Mask */\r
+#define VADC_G_REFCLR_REV8_Pos 8 /*!< VADC_G REFCLR: REV8 Position */\r
+#define VADC_G_REFCLR_REV8_Msk (0x01UL << VADC_G_REFCLR_REV8_Pos) /*!< VADC_G REFCLR: REV8 Mask */\r
+#define VADC_G_REFCLR_REV9_Pos 9 /*!< VADC_G REFCLR: REV9 Position */\r
+#define VADC_G_REFCLR_REV9_Msk (0x01UL << VADC_G_REFCLR_REV9_Pos) /*!< VADC_G REFCLR: REV9 Mask */\r
+#define VADC_G_REFCLR_REV10_Pos 10 /*!< VADC_G REFCLR: REV10 Position */\r
+#define VADC_G_REFCLR_REV10_Msk (0x01UL << VADC_G_REFCLR_REV10_Pos) /*!< VADC_G REFCLR: REV10 Mask */\r
+#define VADC_G_REFCLR_REV11_Pos 11 /*!< VADC_G REFCLR: REV11 Position */\r
+#define VADC_G_REFCLR_REV11_Msk (0x01UL << VADC_G_REFCLR_REV11_Pos) /*!< VADC_G REFCLR: REV11 Mask */\r
+#define VADC_G_REFCLR_REV12_Pos 12 /*!< VADC_G REFCLR: REV12 Position */\r
+#define VADC_G_REFCLR_REV12_Msk (0x01UL << VADC_G_REFCLR_REV12_Pos) /*!< VADC_G REFCLR: REV12 Mask */\r
+#define VADC_G_REFCLR_REV13_Pos 13 /*!< VADC_G REFCLR: REV13 Position */\r
+#define VADC_G_REFCLR_REV13_Msk (0x01UL << VADC_G_REFCLR_REV13_Pos) /*!< VADC_G REFCLR: REV13 Mask */\r
+#define VADC_G_REFCLR_REV14_Pos 14 /*!< VADC_G REFCLR: REV14 Position */\r
+#define VADC_G_REFCLR_REV14_Msk (0x01UL << VADC_G_REFCLR_REV14_Pos) /*!< VADC_G REFCLR: REV14 Mask */\r
+#define VADC_G_REFCLR_REV15_Pos 15 /*!< VADC_G REFCLR: REV15 Position */\r
+#define VADC_G_REFCLR_REV15_Msk (0x01UL << VADC_G_REFCLR_REV15_Pos) /*!< VADC_G REFCLR: REV15 Mask */\r
+\r
+/* -------------------------------- VADC_G_SEFCLR ------------------------------- */\r
+#define VADC_G_SEFCLR_SEV0_Pos 0 /*!< VADC_G SEFCLR: SEV0 Position */\r
+#define VADC_G_SEFCLR_SEV0_Msk (0x01UL << VADC_G_SEFCLR_SEV0_Pos) /*!< VADC_G SEFCLR: SEV0 Mask */\r
+#define VADC_G_SEFCLR_SEV1_Pos 1 /*!< VADC_G SEFCLR: SEV1 Position */\r
+#define VADC_G_SEFCLR_SEV1_Msk (0x01UL << VADC_G_SEFCLR_SEV1_Pos) /*!< VADC_G SEFCLR: SEV1 Mask */\r
+\r
+/* -------------------------------- VADC_G_CEVNP0 ------------------------------- */\r
+#define VADC_G_CEVNP0_CEV0NP_Pos 0 /*!< VADC_G CEVNP0: CEV0NP Position */\r
+#define VADC_G_CEVNP0_CEV0NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV0NP_Pos) /*!< VADC_G CEVNP0: CEV0NP Mask */\r
+#define VADC_G_CEVNP0_CEV1NP_Pos 4 /*!< VADC_G CEVNP0: CEV1NP Position */\r
+#define VADC_G_CEVNP0_CEV1NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV1NP_Pos) /*!< VADC_G CEVNP0: CEV1NP Mask */\r
+#define VADC_G_CEVNP0_CEV2NP_Pos 8 /*!< VADC_G CEVNP0: CEV2NP Position */\r
+#define VADC_G_CEVNP0_CEV2NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV2NP_Pos) /*!< VADC_G CEVNP0: CEV2NP Mask */\r
+#define VADC_G_CEVNP0_CEV3NP_Pos 12 /*!< VADC_G CEVNP0: CEV3NP Position */\r
+#define VADC_G_CEVNP0_CEV3NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV3NP_Pos) /*!< VADC_G CEVNP0: CEV3NP Mask */\r
+#define VADC_G_CEVNP0_CEV4NP_Pos 16 /*!< VADC_G CEVNP0: CEV4NP Position */\r
+#define VADC_G_CEVNP0_CEV4NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV4NP_Pos) /*!< VADC_G CEVNP0: CEV4NP Mask */\r
+#define VADC_G_CEVNP0_CEV5NP_Pos 20 /*!< VADC_G CEVNP0: CEV5NP Position */\r
+#define VADC_G_CEVNP0_CEV5NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV5NP_Pos) /*!< VADC_G CEVNP0: CEV5NP Mask */\r
+#define VADC_G_CEVNP0_CEV6NP_Pos 24 /*!< VADC_G CEVNP0: CEV6NP Position */\r
+#define VADC_G_CEVNP0_CEV6NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV6NP_Pos) /*!< VADC_G CEVNP0: CEV6NP Mask */\r
+#define VADC_G_CEVNP0_CEV7NP_Pos 28 /*!< VADC_G CEVNP0: CEV7NP Position */\r
+#define VADC_G_CEVNP0_CEV7NP_Msk (0x0fUL << VADC_G_CEVNP0_CEV7NP_Pos) /*!< VADC_G CEVNP0: CEV7NP Mask */\r
+\r
+/* -------------------------------- VADC_G_REVNP0 ------------------------------- */\r
+#define VADC_G_REVNP0_REV0NP_Pos 0 /*!< VADC_G REVNP0: REV0NP Position */\r
+#define VADC_G_REVNP0_REV0NP_Msk (0x0fUL << VADC_G_REVNP0_REV0NP_Pos) /*!< VADC_G REVNP0: REV0NP Mask */\r
+#define VADC_G_REVNP0_REV1NP_Pos 4 /*!< VADC_G REVNP0: REV1NP Position */\r
+#define VADC_G_REVNP0_REV1NP_Msk (0x0fUL << VADC_G_REVNP0_REV1NP_Pos) /*!< VADC_G REVNP0: REV1NP Mask */\r
+#define VADC_G_REVNP0_REV2NP_Pos 8 /*!< VADC_G REVNP0: REV2NP Position */\r
+#define VADC_G_REVNP0_REV2NP_Msk (0x0fUL << VADC_G_REVNP0_REV2NP_Pos) /*!< VADC_G REVNP0: REV2NP Mask */\r
+#define VADC_G_REVNP0_REV3NP_Pos 12 /*!< VADC_G REVNP0: REV3NP Position */\r
+#define VADC_G_REVNP0_REV3NP_Msk (0x0fUL << VADC_G_REVNP0_REV3NP_Pos) /*!< VADC_G REVNP0: REV3NP Mask */\r
+#define VADC_G_REVNP0_REV4NP_Pos 16 /*!< VADC_G REVNP0: REV4NP Position */\r
+#define VADC_G_REVNP0_REV4NP_Msk (0x0fUL << VADC_G_REVNP0_REV4NP_Pos) /*!< VADC_G REVNP0: REV4NP Mask */\r
+#define VADC_G_REVNP0_REV5NP_Pos 20 /*!< VADC_G REVNP0: REV5NP Position */\r
+#define VADC_G_REVNP0_REV5NP_Msk (0x0fUL << VADC_G_REVNP0_REV5NP_Pos) /*!< VADC_G REVNP0: REV5NP Mask */\r
+#define VADC_G_REVNP0_REV6NP_Pos 24 /*!< VADC_G REVNP0: REV6NP Position */\r
+#define VADC_G_REVNP0_REV6NP_Msk (0x0fUL << VADC_G_REVNP0_REV6NP_Pos) /*!< VADC_G REVNP0: REV6NP Mask */\r
+#define VADC_G_REVNP0_REV7NP_Pos 28 /*!< VADC_G REVNP0: REV7NP Position */\r
+#define VADC_G_REVNP0_REV7NP_Msk (0x0fUL << VADC_G_REVNP0_REV7NP_Pos) /*!< VADC_G REVNP0: REV7NP Mask */\r
+\r
+/* -------------------------------- VADC_G_REVNP1 ------------------------------- */\r
+#define VADC_G_REVNP1_REV8NP_Pos 0 /*!< VADC_G REVNP1: REV8NP Position */\r
+#define VADC_G_REVNP1_REV8NP_Msk (0x0fUL << VADC_G_REVNP1_REV8NP_Pos) /*!< VADC_G REVNP1: REV8NP Mask */\r
+#define VADC_G_REVNP1_REV9NP_Pos 4 /*!< VADC_G REVNP1: REV9NP Position */\r
+#define VADC_G_REVNP1_REV9NP_Msk (0x0fUL << VADC_G_REVNP1_REV9NP_Pos) /*!< VADC_G REVNP1: REV9NP Mask */\r
+#define VADC_G_REVNP1_REV10NP_Pos 8 /*!< VADC_G REVNP1: REV10NP Position */\r
+#define VADC_G_REVNP1_REV10NP_Msk (0x0fUL << VADC_G_REVNP1_REV10NP_Pos) /*!< VADC_G REVNP1: REV10NP Mask */\r
+#define VADC_G_REVNP1_REV11NP_Pos 12 /*!< VADC_G REVNP1: REV11NP Position */\r
+#define VADC_G_REVNP1_REV11NP_Msk (0x0fUL << VADC_G_REVNP1_REV11NP_Pos) /*!< VADC_G REVNP1: REV11NP Mask */\r
+#define VADC_G_REVNP1_REV12NP_Pos 16 /*!< VADC_G REVNP1: REV12NP Position */\r
+#define VADC_G_REVNP1_REV12NP_Msk (0x0fUL << VADC_G_REVNP1_REV12NP_Pos) /*!< VADC_G REVNP1: REV12NP Mask */\r
+#define VADC_G_REVNP1_REV13NP_Pos 20 /*!< VADC_G REVNP1: REV13NP Position */\r
+#define VADC_G_REVNP1_REV13NP_Msk (0x0fUL << VADC_G_REVNP1_REV13NP_Pos) /*!< VADC_G REVNP1: REV13NP Mask */\r
+#define VADC_G_REVNP1_REV14NP_Pos 24 /*!< VADC_G REVNP1: REV14NP Position */\r
+#define VADC_G_REVNP1_REV14NP_Msk (0x0fUL << VADC_G_REVNP1_REV14NP_Pos) /*!< VADC_G REVNP1: REV14NP Mask */\r
+#define VADC_G_REVNP1_REV15NP_Pos 28 /*!< VADC_G REVNP1: REV15NP Position */\r
+#define VADC_G_REVNP1_REV15NP_Msk (0x0fUL << VADC_G_REVNP1_REV15NP_Pos) /*!< VADC_G REVNP1: REV15NP Mask */\r
+\r
+/* -------------------------------- VADC_G_SEVNP -------------------------------- */\r
+#define VADC_G_SEVNP_SEV0NP_Pos 0 /*!< VADC_G SEVNP: SEV0NP Position */\r
+#define VADC_G_SEVNP_SEV0NP_Msk (0x0fUL << VADC_G_SEVNP_SEV0NP_Pos) /*!< VADC_G SEVNP: SEV0NP Mask */\r
+#define VADC_G_SEVNP_SEV1NP_Pos 4 /*!< VADC_G SEVNP: SEV1NP Position */\r
+#define VADC_G_SEVNP_SEV1NP_Msk (0x0fUL << VADC_G_SEVNP_SEV1NP_Pos) /*!< VADC_G SEVNP: SEV1NP Mask */\r
+\r
+/* -------------------------------- VADC_G_SRACT -------------------------------- */\r
+#define VADC_G_SRACT_AGSR0_Pos 0 /*!< VADC_G SRACT: AGSR0 Position */\r
+#define VADC_G_SRACT_AGSR0_Msk (0x01UL << VADC_G_SRACT_AGSR0_Pos) /*!< VADC_G SRACT: AGSR0 Mask */\r
+#define VADC_G_SRACT_AGSR1_Pos 1 /*!< VADC_G SRACT: AGSR1 Position */\r
+#define VADC_G_SRACT_AGSR1_Msk (0x01UL << VADC_G_SRACT_AGSR1_Pos) /*!< VADC_G SRACT: AGSR1 Mask */\r
+#define VADC_G_SRACT_ASSR0_Pos 8 /*!< VADC_G SRACT: ASSR0 Position */\r
+#define VADC_G_SRACT_ASSR0_Msk (0x01UL << VADC_G_SRACT_ASSR0_Pos) /*!< VADC_G SRACT: ASSR0 Mask */\r
+#define VADC_G_SRACT_ASSR1_Pos 9 /*!< VADC_G SRACT: ASSR1 Position */\r
+#define VADC_G_SRACT_ASSR1_Msk (0x01UL << VADC_G_SRACT_ASSR1_Pos) /*!< VADC_G SRACT: ASSR1 Mask */\r
+#define VADC_G_SRACT_ASSR2_Pos 10 /*!< VADC_G SRACT: ASSR2 Position */\r
+#define VADC_G_SRACT_ASSR2_Msk (0x01UL << VADC_G_SRACT_ASSR2_Pos) /*!< VADC_G SRACT: ASSR2 Mask */\r
+#define VADC_G_SRACT_ASSR3_Pos 11 /*!< VADC_G SRACT: ASSR3 Position */\r
+#define VADC_G_SRACT_ASSR3_Msk (0x01UL << VADC_G_SRACT_ASSR3_Pos) /*!< VADC_G SRACT: ASSR3 Mask */\r
+\r
+/* ------------------------------- VADC_G_EMUXCTR ------------------------------- */\r
+#define VADC_G_EMUXCTR_EMUXSET_Pos 0 /*!< VADC_G EMUXCTR: EMUXSET Position */\r
+#define VADC_G_EMUXCTR_EMUXSET_Msk (0x07UL << VADC_G_EMUXCTR_EMUXSET_Pos) /*!< VADC_G EMUXCTR: EMUXSET Mask */\r
+#define VADC_G_EMUXCTR_EMUXACT_Pos 8 /*!< VADC_G EMUXCTR: EMUXACT Position */\r
+#define VADC_G_EMUXCTR_EMUXACT_Msk (0x07UL << VADC_G_EMUXCTR_EMUXACT_Pos) /*!< VADC_G EMUXCTR: EMUXACT Mask */\r
+#define VADC_G_EMUXCTR_EMUXCH_Pos 16 /*!< VADC_G EMUXCTR: EMUXCH Position */\r
+#define VADC_G_EMUXCTR_EMUXCH_Msk (0x000003ffUL << VADC_G_EMUXCTR_EMUXCH_Pos) /*!< VADC_G EMUXCTR: EMUXCH Mask */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Pos 26 /*!< VADC_G EMUXCTR: EMUXMODE Position */\r
+#define VADC_G_EMUXCTR_EMUXMODE_Msk (0x03UL << VADC_G_EMUXCTR_EMUXMODE_Pos) /*!< VADC_G EMUXCTR: EMUXMODE Mask */\r
+#define VADC_G_EMUXCTR_EMXCOD_Pos 28 /*!< VADC_G EMUXCTR: EMXCOD Position */\r
+#define VADC_G_EMUXCTR_EMXCOD_Msk (0x01UL << VADC_G_EMUXCTR_EMXCOD_Pos) /*!< VADC_G EMUXCTR: EMXCOD Mask */\r
+#define VADC_G_EMUXCTR_EMXST_Pos 29 /*!< VADC_G EMUXCTR: EMXST Position */\r
+#define VADC_G_EMUXCTR_EMXST_Msk (0x01UL << VADC_G_EMUXCTR_EMXST_Pos) /*!< VADC_G EMUXCTR: EMXST Mask */\r
+#define VADC_G_EMUXCTR_EMXCSS_Pos 30 /*!< VADC_G EMUXCTR: EMXCSS Position */\r
+#define VADC_G_EMUXCTR_EMXCSS_Msk (0x01UL << VADC_G_EMUXCTR_EMXCSS_Pos) /*!< VADC_G EMUXCTR: EMXCSS Mask */\r
+#define VADC_G_EMUXCTR_EMXWC_Pos 31 /*!< VADC_G EMUXCTR: EMXWC Position */\r
+#define VADC_G_EMUXCTR_EMXWC_Msk (0x01UL << VADC_G_EMUXCTR_EMXWC_Pos) /*!< VADC_G EMUXCTR: EMXWC Mask */\r
+\r
+/* --------------------------------- VADC_G_VFR --------------------------------- */\r
+#define VADC_G_VFR_VF0_Pos 0 /*!< VADC_G VFR: VF0 Position */\r
+#define VADC_G_VFR_VF0_Msk (0x01UL << VADC_G_VFR_VF0_Pos) /*!< VADC_G VFR: VF0 Mask */\r
+#define VADC_G_VFR_VF1_Pos 1 /*!< VADC_G VFR: VF1 Position */\r
+#define VADC_G_VFR_VF1_Msk (0x01UL << VADC_G_VFR_VF1_Pos) /*!< VADC_G VFR: VF1 Mask */\r
+#define VADC_G_VFR_VF2_Pos 2 /*!< VADC_G VFR: VF2 Position */\r
+#define VADC_G_VFR_VF2_Msk (0x01UL << VADC_G_VFR_VF2_Pos) /*!< VADC_G VFR: VF2 Mask */\r
+#define VADC_G_VFR_VF3_Pos 3 /*!< VADC_G VFR: VF3 Position */\r
+#define VADC_G_VFR_VF3_Msk (0x01UL << VADC_G_VFR_VF3_Pos) /*!< VADC_G VFR: VF3 Mask */\r
+#define VADC_G_VFR_VF4_Pos 4 /*!< VADC_G VFR: VF4 Position */\r
+#define VADC_G_VFR_VF4_Msk (0x01UL << VADC_G_VFR_VF4_Pos) /*!< VADC_G VFR: VF4 Mask */\r
+#define VADC_G_VFR_VF5_Pos 5 /*!< VADC_G VFR: VF5 Position */\r
+#define VADC_G_VFR_VF5_Msk (0x01UL << VADC_G_VFR_VF5_Pos) /*!< VADC_G VFR: VF5 Mask */\r
+#define VADC_G_VFR_VF6_Pos 6 /*!< VADC_G VFR: VF6 Position */\r
+#define VADC_G_VFR_VF6_Msk (0x01UL << VADC_G_VFR_VF6_Pos) /*!< VADC_G VFR: VF6 Mask */\r
+#define VADC_G_VFR_VF7_Pos 7 /*!< VADC_G VFR: VF7 Position */\r
+#define VADC_G_VFR_VF7_Msk (0x01UL << VADC_G_VFR_VF7_Pos) /*!< VADC_G VFR: VF7 Mask */\r
+#define VADC_G_VFR_VF8_Pos 8 /*!< VADC_G VFR: VF8 Position */\r
+#define VADC_G_VFR_VF8_Msk (0x01UL << VADC_G_VFR_VF8_Pos) /*!< VADC_G VFR: VF8 Mask */\r
+#define VADC_G_VFR_VF9_Pos 9 /*!< VADC_G VFR: VF9 Position */\r
+#define VADC_G_VFR_VF9_Msk (0x01UL << VADC_G_VFR_VF9_Pos) /*!< VADC_G VFR: VF9 Mask */\r
+#define VADC_G_VFR_VF10_Pos 10 /*!< VADC_G VFR: VF10 Position */\r
+#define VADC_G_VFR_VF10_Msk (0x01UL << VADC_G_VFR_VF10_Pos) /*!< VADC_G VFR: VF10 Mask */\r
+#define VADC_G_VFR_VF11_Pos 11 /*!< VADC_G VFR: VF11 Position */\r
+#define VADC_G_VFR_VF11_Msk (0x01UL << VADC_G_VFR_VF11_Pos) /*!< VADC_G VFR: VF11 Mask */\r
+#define VADC_G_VFR_VF12_Pos 12 /*!< VADC_G VFR: VF12 Position */\r
+#define VADC_G_VFR_VF12_Msk (0x01UL << VADC_G_VFR_VF12_Pos) /*!< VADC_G VFR: VF12 Mask */\r
+#define VADC_G_VFR_VF13_Pos 13 /*!< VADC_G VFR: VF13 Position */\r
+#define VADC_G_VFR_VF13_Msk (0x01UL << VADC_G_VFR_VF13_Pos) /*!< VADC_G VFR: VF13 Mask */\r
+#define VADC_G_VFR_VF14_Pos 14 /*!< VADC_G VFR: VF14 Position */\r
+#define VADC_G_VFR_VF14_Msk (0x01UL << VADC_G_VFR_VF14_Pos) /*!< VADC_G VFR: VF14 Mask */\r
+#define VADC_G_VFR_VF15_Pos 15 /*!< VADC_G VFR: VF15 Position */\r
+#define VADC_G_VFR_VF15_Msk (0x01UL << VADC_G_VFR_VF15_Pos) /*!< VADC_G VFR: VF15 Mask */\r
+\r
+/* -------------------------------- VADC_G_CHCTR -------------------------------- */\r
+#define VADC_G_CHCTR_ICLSEL_Pos 0 /*!< VADC_G CHCTR: ICLSEL Position */\r
+#define VADC_G_CHCTR_ICLSEL_Msk (0x03UL << VADC_G_CHCTR_ICLSEL_Pos) /*!< VADC_G CHCTR: ICLSEL Mask */\r
+#define VADC_G_CHCTR_BNDSELL_Pos 4 /*!< VADC_G CHCTR: BNDSELL Position */\r
+#define VADC_G_CHCTR_BNDSELL_Msk (0x03UL << VADC_G_CHCTR_BNDSELL_Pos) /*!< VADC_G CHCTR: BNDSELL Mask */\r
+#define VADC_G_CHCTR_BNDSELU_Pos 6 /*!< VADC_G CHCTR: BNDSELU Position */\r
+#define VADC_G_CHCTR_BNDSELU_Msk (0x03UL << VADC_G_CHCTR_BNDSELU_Pos) /*!< VADC_G CHCTR: BNDSELU Mask */\r
+#define VADC_G_CHCTR_CHEVMODE_Pos 8 /*!< VADC_G CHCTR: CHEVMODE Position */\r
+#define VADC_G_CHCTR_CHEVMODE_Msk (0x03UL << VADC_G_CHCTR_CHEVMODE_Pos) /*!< VADC_G CHCTR: CHEVMODE Mask */\r
+#define VADC_G_CHCTR_SYNC_Pos 10 /*!< VADC_G CHCTR: SYNC Position */\r
+#define VADC_G_CHCTR_SYNC_Msk (0x01UL << VADC_G_CHCTR_SYNC_Pos) /*!< VADC_G CHCTR: SYNC Mask */\r
+#define VADC_G_CHCTR_REFSEL_Pos 11 /*!< VADC_G CHCTR: REFSEL Position */\r
+#define VADC_G_CHCTR_REFSEL_Msk (0x01UL << VADC_G_CHCTR_REFSEL_Pos) /*!< VADC_G CHCTR: REFSEL Mask */\r
+#define VADC_G_CHCTR_BNDSELX_Pos 12 /*!< VADC_G CHCTR: BNDSELX Position */\r
+#define VADC_G_CHCTR_BNDSELX_Msk (0x0fUL << VADC_G_CHCTR_BNDSELX_Pos) /*!< VADC_G CHCTR: BNDSELX Mask */\r
+#define VADC_G_CHCTR_RESREG_Pos 16 /*!< VADC_G CHCTR: RESREG Position */\r
+#define VADC_G_CHCTR_RESREG_Msk (0x0fUL << VADC_G_CHCTR_RESREG_Pos) /*!< VADC_G CHCTR: RESREG Mask */\r
+#define VADC_G_CHCTR_RESTBS_Pos 20 /*!< VADC_G CHCTR: RESTBS Position */\r
+#define VADC_G_CHCTR_RESTBS_Msk (0x01UL << VADC_G_CHCTR_RESTBS_Pos) /*!< VADC_G CHCTR: RESTBS Mask */\r
+#define VADC_G_CHCTR_RESPOS_Pos 21 /*!< VADC_G CHCTR: RESPOS Position */\r
+#define VADC_G_CHCTR_RESPOS_Msk (0x01UL << VADC_G_CHCTR_RESPOS_Pos) /*!< VADC_G CHCTR: RESPOS Mask */\r
+#define VADC_G_CHCTR_BWDCH_Pos 28 /*!< VADC_G CHCTR: BWDCH Position */\r
+#define VADC_G_CHCTR_BWDCH_Msk (0x03UL << VADC_G_CHCTR_BWDCH_Pos) /*!< VADC_G CHCTR: BWDCH Mask */\r
+#define VADC_G_CHCTR_BWDEN_Pos 30 /*!< VADC_G CHCTR: BWDEN Position */\r
+#define VADC_G_CHCTR_BWDEN_Msk (0x01UL << VADC_G_CHCTR_BWDEN_Pos) /*!< VADC_G CHCTR: BWDEN Mask */\r
+\r
+/* --------------------------------- VADC_G_RCR --------------------------------- */\r
+#define VADC_G_RCR_DRCTR_Pos 16 /*!< VADC_G RCR: DRCTR Position */\r
+#define VADC_G_RCR_DRCTR_Msk (0x0fUL << VADC_G_RCR_DRCTR_Pos) /*!< VADC_G RCR: DRCTR Mask */\r
+#define VADC_G_RCR_DMM_Pos 20 /*!< VADC_G RCR: DMM Position */\r
+#define VADC_G_RCR_DMM_Msk (0x03UL << VADC_G_RCR_DMM_Pos) /*!< VADC_G RCR: DMM Mask */\r
+#define VADC_G_RCR_WFR_Pos 24 /*!< VADC_G RCR: WFR Position */\r
+#define VADC_G_RCR_WFR_Msk (0x01UL << VADC_G_RCR_WFR_Pos) /*!< VADC_G RCR: WFR Mask */\r
+#define VADC_G_RCR_FEN_Pos 25 /*!< VADC_G RCR: FEN Position */\r
+#define VADC_G_RCR_FEN_Msk (0x03UL << VADC_G_RCR_FEN_Pos) /*!< VADC_G RCR: FEN Mask */\r
+#define VADC_G_RCR_SRGEN_Pos 31 /*!< VADC_G RCR: SRGEN Position */\r
+#define VADC_G_RCR_SRGEN_Msk (0x01UL << VADC_G_RCR_SRGEN_Pos) /*!< VADC_G RCR: SRGEN Mask */\r
+\r
+/* --------------------------------- VADC_G_RES --------------------------------- */\r
+#define VADC_G_RES_RESULT_Pos 0 /*!< VADC_G RES: RESULT Position */\r
+#define VADC_G_RES_RESULT_Msk (0x0000ffffUL << VADC_G_RES_RESULT_Pos) /*!< VADC_G RES: RESULT Mask */\r
+#define VADC_G_RES_DRC_Pos 16 /*!< VADC_G RES: DRC Position */\r
+#define VADC_G_RES_DRC_Msk (0x0fUL << VADC_G_RES_DRC_Pos) /*!< VADC_G RES: DRC Mask */\r
+#define VADC_G_RES_CHNR_Pos 20 /*!< VADC_G RES: CHNR Position */\r
+#define VADC_G_RES_CHNR_Msk (0x1fUL << VADC_G_RES_CHNR_Pos) /*!< VADC_G RES: CHNR Mask */\r
+#define VADC_G_RES_EMUX_Pos 25 /*!< VADC_G RES: EMUX Position */\r
+#define VADC_G_RES_EMUX_Msk (0x07UL << VADC_G_RES_EMUX_Pos) /*!< VADC_G RES: EMUX Mask */\r
+#define VADC_G_RES_CRS_Pos 28 /*!< VADC_G RES: CRS Position */\r
+#define VADC_G_RES_CRS_Msk (0x03UL << VADC_G_RES_CRS_Pos) /*!< VADC_G RES: CRS Mask */\r
+#define VADC_G_RES_FCR_Pos 30 /*!< VADC_G RES: FCR Position */\r
+#define VADC_G_RES_FCR_Msk (0x01UL << VADC_G_RES_FCR_Pos) /*!< VADC_G RES: FCR Mask */\r
+#define VADC_G_RES_VF_Pos 31 /*!< VADC_G RES: VF Position */\r
+#define VADC_G_RES_VF_Msk (0x01UL << VADC_G_RES_VF_Pos) /*!< VADC_G RES: VF Mask */\r
+\r
+/* --------------------------------- VADC_G_RESD -------------------------------- */\r
+#define VADC_G_RESD_RESULT_Pos 0 /*!< VADC_G RESD: RESULT Position */\r
+#define VADC_G_RESD_RESULT_Msk (0x0000ffffUL << VADC_G_RESD_RESULT_Pos) /*!< VADC_G RESD: RESULT Mask */\r
+#define VADC_G_RESD_DRC_Pos 16 /*!< VADC_G RESD: DRC Position */\r
+#define VADC_G_RESD_DRC_Msk (0x0fUL << VADC_G_RESD_DRC_Pos) /*!< VADC_G RESD: DRC Mask */\r
+#define VADC_G_RESD_CHNR_Pos 20 /*!< VADC_G RESD: CHNR Position */\r
+#define VADC_G_RESD_CHNR_Msk (0x1fUL << VADC_G_RESD_CHNR_Pos) /*!< VADC_G RESD: CHNR Mask */\r
+#define VADC_G_RESD_EMUX_Pos 25 /*!< VADC_G RESD: EMUX Position */\r
+#define VADC_G_RESD_EMUX_Msk (0x07UL << VADC_G_RESD_EMUX_Pos) /*!< VADC_G RESD: EMUX Mask */\r
+#define VADC_G_RESD_CRS_Pos 28 /*!< VADC_G RESD: CRS Position */\r
+#define VADC_G_RESD_CRS_Msk (0x03UL << VADC_G_RESD_CRS_Pos) /*!< VADC_G RESD: CRS Mask */\r
+#define VADC_G_RESD_FCR_Pos 30 /*!< VADC_G RESD: FCR Position */\r
+#define VADC_G_RESD_FCR_Msk (0x01UL << VADC_G_RESD_FCR_Pos) /*!< VADC_G RESD: FCR Mask */\r
+#define VADC_G_RESD_VF_Pos 31 /*!< VADC_G RESD: VF Position */\r
+#define VADC_G_RESD_VF_Msk (0x01UL << VADC_G_RESD_VF_Pos) /*!< VADC_G RESD: VF Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'SHS' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ----------------------------------- SHS_ID ----------------------------------- */\r
+#define SHS_ID_MOD_REV_Pos 0 /*!< SHS ID: MOD_REV Position */\r
+#define SHS_ID_MOD_REV_Msk (0x000000ffUL << SHS_ID_MOD_REV_Pos) /*!< SHS ID: MOD_REV Mask */\r
+#define SHS_ID_MOD_TYPE_Pos 8 /*!< SHS ID: MOD_TYPE Position */\r
+#define SHS_ID_MOD_TYPE_Msk (0x000000ffUL << SHS_ID_MOD_TYPE_Pos) /*!< SHS ID: MOD_TYPE Mask */\r
+#define SHS_ID_MOD_NUMBER_Pos 16 /*!< SHS ID: MOD_NUMBER Position */\r
+#define SHS_ID_MOD_NUMBER_Msk (0x0000ffffUL << SHS_ID_MOD_NUMBER_Pos) /*!< SHS ID: MOD_NUMBER Mask */\r
+\r
+/* --------------------------------- SHS_SHSCFG --------------------------------- */\r
+#define SHS_SHSCFG_DIVS_Pos 0 /*!< SHS SHSCFG: DIVS Position */\r
+#define SHS_SHSCFG_DIVS_Msk (0x0fUL << SHS_SHSCFG_DIVS_Pos) /*!< SHS SHSCFG: DIVS Mask */\r
+#define SHS_SHSCFG_AREF_Pos 10 /*!< SHS SHSCFG: AREF Position */\r
+#define SHS_SHSCFG_AREF_Msk (0x03UL << SHS_SHSCFG_AREF_Pos) /*!< SHS SHSCFG: AREF Mask */\r
+#define SHS_SHSCFG_ANOFF_Pos 12 /*!< SHS SHSCFG: ANOFF Position */\r
+#define SHS_SHSCFG_ANOFF_Msk (0x01UL << SHS_SHSCFG_ANOFF_Pos) /*!< SHS SHSCFG: ANOFF Mask */\r
+#define SHS_SHSCFG_ANRDY_Pos 14 /*!< SHS SHSCFG: ANRDY Position */\r
+#define SHS_SHSCFG_ANRDY_Msk (0x01UL << SHS_SHSCFG_ANRDY_Pos) /*!< SHS SHSCFG: ANRDY Mask */\r
+#define SHS_SHSCFG_SCWC_Pos 15 /*!< SHS SHSCFG: SCWC Position */\r
+#define SHS_SHSCFG_SCWC_Msk (0x01UL << SHS_SHSCFG_SCWC_Pos) /*!< SHS SHSCFG: SCWC Mask */\r
+#define SHS_SHSCFG_SP0_Pos 16 /*!< SHS SHSCFG: SP0 Position */\r
+#define SHS_SHSCFG_SP0_Msk (0x01UL << SHS_SHSCFG_SP0_Pos) /*!< SHS SHSCFG: SP0 Mask */\r
+#define SHS_SHSCFG_SP1_Pos 17 /*!< SHS SHSCFG: SP1 Position */\r
+#define SHS_SHSCFG_SP1_Msk (0x01UL << SHS_SHSCFG_SP1_Pos) /*!< SHS SHSCFG: SP1 Mask */\r
+#define SHS_SHSCFG_TC_Pos 24 /*!< SHS SHSCFG: TC Position */\r
+#define SHS_SHSCFG_TC_Msk (0x0fUL << SHS_SHSCFG_TC_Pos) /*!< SHS SHSCFG: TC Mask */\r
+#define SHS_SHSCFG_STATE_Pos 28 /*!< SHS SHSCFG: STATE Position */\r
+#define SHS_SHSCFG_STATE_Msk (0x0fUL << SHS_SHSCFG_STATE_Pos) /*!< SHS SHSCFG: STATE Mask */\r
+\r
+/* --------------------------------- SHS_STEPCFG -------------------------------- */\r
+#define SHS_STEPCFG_KSEL0_Pos 0 /*!< SHS STEPCFG: KSEL0 Position */\r
+#define SHS_STEPCFG_KSEL0_Msk (0x07UL << SHS_STEPCFG_KSEL0_Pos) /*!< SHS STEPCFG: KSEL0 Mask */\r
+#define SHS_STEPCFG_SEN0_Pos 3 /*!< SHS STEPCFG: SEN0 Position */\r
+#define SHS_STEPCFG_SEN0_Msk (0x01UL << SHS_STEPCFG_SEN0_Pos) /*!< SHS STEPCFG: SEN0 Mask */\r
+#define SHS_STEPCFG_KSEL1_Pos 4 /*!< SHS STEPCFG: KSEL1 Position */\r
+#define SHS_STEPCFG_KSEL1_Msk (0x07UL << SHS_STEPCFG_KSEL1_Pos) /*!< SHS STEPCFG: KSEL1 Mask */\r
+#define SHS_STEPCFG_SEN1_Pos 7 /*!< SHS STEPCFG: SEN1 Position */\r
+#define SHS_STEPCFG_SEN1_Msk (0x01UL << SHS_STEPCFG_SEN1_Pos) /*!< SHS STEPCFG: SEN1 Mask */\r
+#define SHS_STEPCFG_KSEL2_Pos 8 /*!< SHS STEPCFG: KSEL2 Position */\r
+#define SHS_STEPCFG_KSEL2_Msk (0x07UL << SHS_STEPCFG_KSEL2_Pos) /*!< SHS STEPCFG: KSEL2 Mask */\r
+#define SHS_STEPCFG_SEN2_Pos 11 /*!< SHS STEPCFG: SEN2 Position */\r
+#define SHS_STEPCFG_SEN2_Msk (0x01UL << SHS_STEPCFG_SEN2_Pos) /*!< SHS STEPCFG: SEN2 Mask */\r
+#define SHS_STEPCFG_KSEL3_Pos 12 /*!< SHS STEPCFG: KSEL3 Position */\r
+#define SHS_STEPCFG_KSEL3_Msk (0x07UL << SHS_STEPCFG_KSEL3_Pos) /*!< SHS STEPCFG: KSEL3 Mask */\r
+#define SHS_STEPCFG_SEN3_Pos 15 /*!< SHS STEPCFG: SEN3 Position */\r
+#define SHS_STEPCFG_SEN3_Msk (0x01UL << SHS_STEPCFG_SEN3_Pos) /*!< SHS STEPCFG: SEN3 Mask */\r
+#define SHS_STEPCFG_KSEL4_Pos 16 /*!< SHS STEPCFG: KSEL4 Position */\r
+#define SHS_STEPCFG_KSEL4_Msk (0x07UL << SHS_STEPCFG_KSEL4_Pos) /*!< SHS STEPCFG: KSEL4 Mask */\r
+#define SHS_STEPCFG_SEN4_Pos 19 /*!< SHS STEPCFG: SEN4 Position */\r
+#define SHS_STEPCFG_SEN4_Msk (0x01UL << SHS_STEPCFG_SEN4_Pos) /*!< SHS STEPCFG: SEN4 Mask */\r
+#define SHS_STEPCFG_KSEL5_Pos 20 /*!< SHS STEPCFG: KSEL5 Position */\r
+#define SHS_STEPCFG_KSEL5_Msk (0x07UL << SHS_STEPCFG_KSEL5_Pos) /*!< SHS STEPCFG: KSEL5 Mask */\r
+#define SHS_STEPCFG_SEN5_Pos 23 /*!< SHS STEPCFG: SEN5 Position */\r
+#define SHS_STEPCFG_SEN5_Msk (0x01UL << SHS_STEPCFG_SEN5_Pos) /*!< SHS STEPCFG: SEN5 Mask */\r
+#define SHS_STEPCFG_KSEL6_Pos 24 /*!< SHS STEPCFG: KSEL6 Position */\r
+#define SHS_STEPCFG_KSEL6_Msk (0x07UL << SHS_STEPCFG_KSEL6_Pos) /*!< SHS STEPCFG: KSEL6 Mask */\r
+#define SHS_STEPCFG_SEN6_Pos 27 /*!< SHS STEPCFG: SEN6 Position */\r
+#define SHS_STEPCFG_SEN6_Msk (0x01UL << SHS_STEPCFG_SEN6_Pos) /*!< SHS STEPCFG: SEN6 Mask */\r
+#define SHS_STEPCFG_KSEL7_Pos 28 /*!< SHS STEPCFG: KSEL7 Position */\r
+#define SHS_STEPCFG_KSEL7_Msk (0x07UL << SHS_STEPCFG_KSEL7_Pos) /*!< SHS STEPCFG: KSEL7 Mask */\r
+#define SHS_STEPCFG_SEN7_Pos 31 /*!< SHS STEPCFG: SEN7 Position */\r
+#define SHS_STEPCFG_SEN7_Msk (0x01UL << SHS_STEPCFG_SEN7_Pos) /*!< SHS STEPCFG: SEN7 Mask */\r
+\r
+/* ---------------------------------- SHS_LOOP ---------------------------------- */\r
+#define SHS_LOOP_LPCH0_Pos 0 /*!< SHS LOOP: LPCH0 Position */\r
+#define SHS_LOOP_LPCH0_Msk (0x1fUL << SHS_LOOP_LPCH0_Pos) /*!< SHS LOOP: LPCH0 Mask */\r
+#define SHS_LOOP_LPSH0_Pos 8 /*!< SHS LOOP: LPSH0 Position */\r
+#define SHS_LOOP_LPSH0_Msk (0x01UL << SHS_LOOP_LPSH0_Pos) /*!< SHS LOOP: LPSH0 Mask */\r
+#define SHS_LOOP_LPEN0_Pos 15 /*!< SHS LOOP: LPEN0 Position */\r
+#define SHS_LOOP_LPEN0_Msk (0x01UL << SHS_LOOP_LPEN0_Pos) /*!< SHS LOOP: LPEN0 Mask */\r
+#define SHS_LOOP_LPCH1_Pos 16 /*!< SHS LOOP: LPCH1 Position */\r
+#define SHS_LOOP_LPCH1_Msk (0x1fUL << SHS_LOOP_LPCH1_Pos) /*!< SHS LOOP: LPCH1 Mask */\r
+#define SHS_LOOP_LPSH1_Pos 24 /*!< SHS LOOP: LPSH1 Position */\r
+#define SHS_LOOP_LPSH1_Msk (0x01UL << SHS_LOOP_LPSH1_Pos) /*!< SHS LOOP: LPSH1 Mask */\r
+#define SHS_LOOP_LPEN1_Pos 31 /*!< SHS LOOP: LPEN1 Position */\r
+#define SHS_LOOP_LPEN1_Msk (0x01UL << SHS_LOOP_LPEN1_Pos) /*!< SHS LOOP: LPEN1 Mask */\r
+\r
+/* --------------------------------- SHS_TIMCFG0 -------------------------------- */\r
+#define SHS_TIMCFG0_AT_Pos 0 /*!< SHS TIMCFG0: AT Position */\r
+#define SHS_TIMCFG0_AT_Msk (0x01UL << SHS_TIMCFG0_AT_Pos) /*!< SHS TIMCFG0: AT Mask */\r
+#define SHS_TIMCFG0_FCRT_Pos 4 /*!< SHS TIMCFG0: FCRT Position */\r
+#define SHS_TIMCFG0_FCRT_Msk (0x0fUL << SHS_TIMCFG0_FCRT_Pos) /*!< SHS TIMCFG0: FCRT Mask */\r
+#define SHS_TIMCFG0_SST_Pos 8 /*!< SHS TIMCFG0: SST Position */\r
+#define SHS_TIMCFG0_SST_Msk (0x3fUL << SHS_TIMCFG0_SST_Pos) /*!< SHS TIMCFG0: SST Mask */\r
+#define SHS_TIMCFG0_TGEN_Pos 16 /*!< SHS TIMCFG0: TGEN Position */\r
+#define SHS_TIMCFG0_TGEN_Msk (0x00003fffUL << SHS_TIMCFG0_TGEN_Pos) /*!< SHS TIMCFG0: TGEN Mask */\r
+\r
+/* --------------------------------- SHS_TIMCFG1 -------------------------------- */\r
+#define SHS_TIMCFG1_AT_Pos 0 /*!< SHS TIMCFG1: AT Position */\r
+#define SHS_TIMCFG1_AT_Msk (0x01UL << SHS_TIMCFG1_AT_Pos) /*!< SHS TIMCFG1: AT Mask */\r
+#define SHS_TIMCFG1_FCRT_Pos 4 /*!< SHS TIMCFG1: FCRT Position */\r
+#define SHS_TIMCFG1_FCRT_Msk (0x0fUL << SHS_TIMCFG1_FCRT_Pos) /*!< SHS TIMCFG1: FCRT Mask */\r
+#define SHS_TIMCFG1_SST_Pos 8 /*!< SHS TIMCFG1: SST Position */\r
+#define SHS_TIMCFG1_SST_Msk (0x3fUL << SHS_TIMCFG1_SST_Pos) /*!< SHS TIMCFG1: SST Mask */\r
+#define SHS_TIMCFG1_TGEN_Pos 16 /*!< SHS TIMCFG1: TGEN Position */\r
+#define SHS_TIMCFG1_TGEN_Msk (0x00003fffUL << SHS_TIMCFG1_TGEN_Pos) /*!< SHS TIMCFG1: TGEN Mask */\r
+\r
+/* --------------------------------- SHS_CALCTR --------------------------------- */\r
+#define SHS_CALCTR_CALORD_Pos 0 /*!< SHS CALCTR: CALORD Position */\r
+#define SHS_CALCTR_CALORD_Msk (0x01UL << SHS_CALCTR_CALORD_Pos) /*!< SHS CALCTR: CALORD Mask */\r
+#define SHS_CALCTR_CALGNSTC_Pos 8 /*!< SHS CALCTR: CALGNSTC Position */\r
+#define SHS_CALCTR_CALGNSTC_Msk (0x3fUL << SHS_CALCTR_CALGNSTC_Pos) /*!< SHS CALCTR: CALGNSTC Mask */\r
+#define SHS_CALCTR_SUCALVAL_Pos 16 /*!< SHS CALCTR: SUCALVAL Position */\r
+#define SHS_CALCTR_SUCALVAL_Msk (0x7fUL << SHS_CALCTR_SUCALVAL_Pos) /*!< SHS CALCTR: SUCALVAL Mask */\r
+#define SHS_CALCTR_CALMAX_Pos 24 /*!< SHS CALCTR: CALMAX Position */\r
+#define SHS_CALCTR_CALMAX_Msk (0x3fUL << SHS_CALCTR_CALMAX_Pos) /*!< SHS CALCTR: CALMAX Mask */\r
+#define SHS_CALCTR_SUCAL_Pos 31 /*!< SHS CALCTR: SUCAL Position */\r
+#define SHS_CALCTR_SUCAL_Msk (0x01UL << SHS_CALCTR_SUCAL_Pos) /*!< SHS CALCTR: SUCAL Mask */\r
+\r
+/* --------------------------------- SHS_CALGC0 --------------------------------- */\r
+#define SHS_CALGC0_CALGNVALS_Pos 0 /*!< SHS CALGC0: CALGNVALS Position */\r
+#define SHS_CALGC0_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALS_Pos) /*!< SHS CALGC0: CALGNVALS Mask */\r
+#define SHS_CALGC0_GNSWC_Pos 15 /*!< SHS CALGC0: GNSWC Position */\r
+#define SHS_CALGC0_GNSWC_Msk (0x01UL << SHS_CALGC0_GNSWC_Pos) /*!< SHS CALGC0: GNSWC Mask */\r
+#define SHS_CALGC0_CALGNVALA_Pos 16 /*!< SHS CALGC0: CALGNVALA Position */\r
+#define SHS_CALGC0_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC0_CALGNVALA_Pos) /*!< SHS CALGC0: CALGNVALA Mask */\r
+#define SHS_CALGC0_GNAWC_Pos 31 /*!< SHS CALGC0: GNAWC Position */\r
+#define SHS_CALGC0_GNAWC_Msk (0x01UL << SHS_CALGC0_GNAWC_Pos) /*!< SHS CALGC0: GNAWC Mask */\r
+\r
+/* --------------------------------- SHS_CALGC1 --------------------------------- */\r
+#define SHS_CALGC1_CALGNVALS_Pos 0 /*!< SHS CALGC1: CALGNVALS Position */\r
+#define SHS_CALGC1_CALGNVALS_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALS_Pos) /*!< SHS CALGC1: CALGNVALS Mask */\r
+#define SHS_CALGC1_GNSWC_Pos 15 /*!< SHS CALGC1: GNSWC Position */\r
+#define SHS_CALGC1_GNSWC_Msk (0x01UL << SHS_CALGC1_GNSWC_Pos) /*!< SHS CALGC1: GNSWC Mask */\r
+#define SHS_CALGC1_CALGNVALA_Pos 16 /*!< SHS CALGC1: CALGNVALA Position */\r
+#define SHS_CALGC1_CALGNVALA_Msk (0x00003fffUL << SHS_CALGC1_CALGNVALA_Pos) /*!< SHS CALGC1: CALGNVALA Mask */\r
+#define SHS_CALGC1_GNAWC_Pos 31 /*!< SHS CALGC1: GNAWC Position */\r
+#define SHS_CALGC1_GNAWC_Msk (0x01UL << SHS_CALGC1_GNAWC_Pos) /*!< SHS CALGC1: GNAWC Mask */\r
+\r
+/* --------------------------------- SHS_GNCTR00 -------------------------------- */\r
+#define SHS_GNCTR00_GAIN0_Pos 0 /*!< SHS GNCTR00: GAIN0 Position */\r
+#define SHS_GNCTR00_GAIN0_Msk (0x0fUL << SHS_GNCTR00_GAIN0_Pos) /*!< SHS GNCTR00: GAIN0 Mask */\r
+#define SHS_GNCTR00_GAIN1_Pos 4 /*!< SHS GNCTR00: GAIN1 Position */\r
+#define SHS_GNCTR00_GAIN1_Msk (0x0fUL << SHS_GNCTR00_GAIN1_Pos) /*!< SHS GNCTR00: GAIN1 Mask */\r
+#define SHS_GNCTR00_GAIN2_Pos 8 /*!< SHS GNCTR00: GAIN2 Position */\r
+#define SHS_GNCTR00_GAIN2_Msk (0x0fUL << SHS_GNCTR00_GAIN2_Pos) /*!< SHS GNCTR00: GAIN2 Mask */\r
+#define SHS_GNCTR00_GAIN3_Pos 12 /*!< SHS GNCTR00: GAIN3 Position */\r
+#define SHS_GNCTR00_GAIN3_Msk (0x0fUL << SHS_GNCTR00_GAIN3_Pos) /*!< SHS GNCTR00: GAIN3 Mask */\r
+#define SHS_GNCTR00_GAIN4_Pos 16 /*!< SHS GNCTR00: GAIN4 Position */\r
+#define SHS_GNCTR00_GAIN4_Msk (0x0fUL << SHS_GNCTR00_GAIN4_Pos) /*!< SHS GNCTR00: GAIN4 Mask */\r
+#define SHS_GNCTR00_GAIN5_Pos 20 /*!< SHS GNCTR00: GAIN5 Position */\r
+#define SHS_GNCTR00_GAIN5_Msk (0x0fUL << SHS_GNCTR00_GAIN5_Pos) /*!< SHS GNCTR00: GAIN5 Mask */\r
+#define SHS_GNCTR00_GAIN6_Pos 24 /*!< SHS GNCTR00: GAIN6 Position */\r
+#define SHS_GNCTR00_GAIN6_Msk (0x0fUL << SHS_GNCTR00_GAIN6_Pos) /*!< SHS GNCTR00: GAIN6 Mask */\r
+#define SHS_GNCTR00_GAIN7_Pos 28 /*!< SHS GNCTR00: GAIN7 Position */\r
+#define SHS_GNCTR00_GAIN7_Msk (0x0fUL << SHS_GNCTR00_GAIN7_Pos) /*!< SHS GNCTR00: GAIN7 Mask */\r
+\r
+/* --------------------------------- SHS_GNCTR10 -------------------------------- */\r
+#define SHS_GNCTR10_GAIN0_Pos 0 /*!< SHS GNCTR10: GAIN0 Position */\r
+#define SHS_GNCTR10_GAIN0_Msk (0x0fUL << SHS_GNCTR10_GAIN0_Pos) /*!< SHS GNCTR10: GAIN0 Mask */\r
+#define SHS_GNCTR10_GAIN1_Pos 4 /*!< SHS GNCTR10: GAIN1 Position */\r
+#define SHS_GNCTR10_GAIN1_Msk (0x0fUL << SHS_GNCTR10_GAIN1_Pos) /*!< SHS GNCTR10: GAIN1 Mask */\r
+#define SHS_GNCTR10_GAIN2_Pos 8 /*!< SHS GNCTR10: GAIN2 Position */\r
+#define SHS_GNCTR10_GAIN2_Msk (0x0fUL << SHS_GNCTR10_GAIN2_Pos) /*!< SHS GNCTR10: GAIN2 Mask */\r
+#define SHS_GNCTR10_GAIN3_Pos 12 /*!< SHS GNCTR10: GAIN3 Position */\r
+#define SHS_GNCTR10_GAIN3_Msk (0x0fUL << SHS_GNCTR10_GAIN3_Pos) /*!< SHS GNCTR10: GAIN3 Mask */\r
+#define SHS_GNCTR10_GAIN4_Pos 16 /*!< SHS GNCTR10: GAIN4 Position */\r
+#define SHS_GNCTR10_GAIN4_Msk (0x0fUL << SHS_GNCTR10_GAIN4_Pos) /*!< SHS GNCTR10: GAIN4 Mask */\r
+#define SHS_GNCTR10_GAIN5_Pos 20 /*!< SHS GNCTR10: GAIN5 Position */\r
+#define SHS_GNCTR10_GAIN5_Msk (0x0fUL << SHS_GNCTR10_GAIN5_Pos) /*!< SHS GNCTR10: GAIN5 Mask */\r
+#define SHS_GNCTR10_GAIN6_Pos 24 /*!< SHS GNCTR10: GAIN6 Position */\r
+#define SHS_GNCTR10_GAIN6_Msk (0x0fUL << SHS_GNCTR10_GAIN6_Pos) /*!< SHS GNCTR10: GAIN6 Mask */\r
+#define SHS_GNCTR10_GAIN7_Pos 28 /*!< SHS GNCTR10: GAIN7 Position */\r
+#define SHS_GNCTR10_GAIN7_Msk (0x0fUL << SHS_GNCTR10_GAIN7_Pos) /*!< SHS GNCTR10: GAIN7 Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'BCCU' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- BCCU_GLOBCON -------------------------------- */\r
+#define BCCU_GLOBCON_TM_Pos 0 /*!< BCCU GLOBCON: TM Position */\r
+#define BCCU_GLOBCON_TM_Msk (0x01UL << BCCU_GLOBCON_TM_Pos) /*!< BCCU GLOBCON: TM Mask */\r
+#define BCCU_GLOBCON_TRDEL_Pos 2 /*!< BCCU GLOBCON: TRDEL Position */\r
+#define BCCU_GLOBCON_TRDEL_Msk (0x03UL << BCCU_GLOBCON_TRDEL_Pos) /*!< BCCU GLOBCON: TRDEL Mask */\r
+#define BCCU_GLOBCON_SUSCFG_Pos 4 /*!< BCCU GLOBCON: SUSCFG Position */\r
+#define BCCU_GLOBCON_SUSCFG_Msk (0x03UL << BCCU_GLOBCON_SUSCFG_Pos) /*!< BCCU GLOBCON: SUSCFG Mask */\r
+#define BCCU_GLOBCON_TRAPIS_Pos 6 /*!< BCCU GLOBCON: TRAPIS Position */\r
+#define BCCU_GLOBCON_TRAPIS_Msk (0x0fUL << BCCU_GLOBCON_TRAPIS_Pos) /*!< BCCU GLOBCON: TRAPIS Mask */\r
+#define BCCU_GLOBCON_TRAPED_Pos 10 /*!< BCCU GLOBCON: TRAPED Position */\r
+#define BCCU_GLOBCON_TRAPED_Msk (0x01UL << BCCU_GLOBCON_TRAPED_Pos) /*!< BCCU GLOBCON: TRAPED Mask */\r
+#define BCCU_GLOBCON_LTRS_Pos 12 /*!< BCCU GLOBCON: LTRS Position */\r
+#define BCCU_GLOBCON_LTRS_Msk (0x0fUL << BCCU_GLOBCON_LTRS_Pos) /*!< BCCU GLOBCON: LTRS Mask */\r
+#define BCCU_GLOBCON_WDMBN_Pos 16 /*!< BCCU GLOBCON: WDMBN Position */\r
+#define BCCU_GLOBCON_WDMBN_Msk (0x00000fffUL << BCCU_GLOBCON_WDMBN_Pos) /*!< BCCU GLOBCON: WDMBN Mask */\r
+\r
+/* -------------------------------- BCCU_GLOBCLK -------------------------------- */\r
+#define BCCU_GLOBCLK_FCLK_PS_Pos 0 /*!< BCCU GLOBCLK: FCLK_PS Position */\r
+#define BCCU_GLOBCLK_FCLK_PS_Msk (0x00000fffUL << BCCU_GLOBCLK_FCLK_PS_Pos) /*!< BCCU GLOBCLK: FCLK_PS Mask */\r
+#define BCCU_GLOBCLK_BCS_Pos 15 /*!< BCCU GLOBCLK: BCS Position */\r
+#define BCCU_GLOBCLK_BCS_Msk (0x01UL << BCCU_GLOBCLK_BCS_Pos) /*!< BCCU GLOBCLK: BCS Mask */\r
+#define BCCU_GLOBCLK_DCLK_PS_Pos 16 /*!< BCCU GLOBCLK: DCLK_PS Position */\r
+#define BCCU_GLOBCLK_DCLK_PS_Msk (0x00000fffUL << BCCU_GLOBCLK_DCLK_PS_Pos) /*!< BCCU GLOBCLK: DCLK_PS Mask */\r
+\r
+/* ----------------------------------- BCCU_ID ---------------------------------- */\r
+#define BCCU_ID_MOD_REV_Pos 0 /*!< BCCU ID: MOD_REV Position */\r
+#define BCCU_ID_MOD_REV_Msk (0x000000ffUL << BCCU_ID_MOD_REV_Pos) /*!< BCCU ID: MOD_REV Mask */\r
+#define BCCU_ID_MOD_TYPE0_Pos 8 /*!< BCCU ID: MOD_TYPE0 Position */\r
+#define BCCU_ID_MOD_TYPE0_Msk (0x000000ffUL << BCCU_ID_MOD_TYPE0_Pos) /*!< BCCU ID: MOD_TYPE0 Mask */\r
+#define BCCU_ID_MOD_NUMBER_Pos 16 /*!< BCCU ID: MOD_NUMBER Position */\r
+#define BCCU_ID_MOD_NUMBER_Msk (0x0000ffffUL << BCCU_ID_MOD_NUMBER_Pos) /*!< BCCU ID: MOD_NUMBER Mask */\r
+\r
+/* ---------------------------------- BCCU_CHEN --------------------------------- */\r
+#define BCCU_CHEN_ECH0_Pos 0 /*!< BCCU CHEN: ECH0 Position */\r
+#define BCCU_CHEN_ECH0_Msk (0x01UL << BCCU_CHEN_ECH0_Pos) /*!< BCCU CHEN: ECH0 Mask */\r
+#define BCCU_CHEN_ECH1_Pos 1 /*!< BCCU CHEN: ECH1 Position */\r
+#define BCCU_CHEN_ECH1_Msk (0x01UL << BCCU_CHEN_ECH1_Pos) /*!< BCCU CHEN: ECH1 Mask */\r
+#define BCCU_CHEN_ECH2_Pos 2 /*!< BCCU CHEN: ECH2 Position */\r
+#define BCCU_CHEN_ECH2_Msk (0x01UL << BCCU_CHEN_ECH2_Pos) /*!< BCCU CHEN: ECH2 Mask */\r
+#define BCCU_CHEN_ECH3_Pos 3 /*!< BCCU CHEN: ECH3 Position */\r
+#define BCCU_CHEN_ECH3_Msk (0x01UL << BCCU_CHEN_ECH3_Pos) /*!< BCCU CHEN: ECH3 Mask */\r
+#define BCCU_CHEN_ECH4_Pos 4 /*!< BCCU CHEN: ECH4 Position */\r
+#define BCCU_CHEN_ECH4_Msk (0x01UL << BCCU_CHEN_ECH4_Pos) /*!< BCCU CHEN: ECH4 Mask */\r
+#define BCCU_CHEN_ECH5_Pos 5 /*!< BCCU CHEN: ECH5 Position */\r
+#define BCCU_CHEN_ECH5_Msk (0x01UL << BCCU_CHEN_ECH5_Pos) /*!< BCCU CHEN: ECH5 Mask */\r
+#define BCCU_CHEN_ECH6_Pos 6 /*!< BCCU CHEN: ECH6 Position */\r
+#define BCCU_CHEN_ECH6_Msk (0x01UL << BCCU_CHEN_ECH6_Pos) /*!< BCCU CHEN: ECH6 Mask */\r
+#define BCCU_CHEN_ECH7_Pos 7 /*!< BCCU CHEN: ECH7 Position */\r
+#define BCCU_CHEN_ECH7_Msk (0x01UL << BCCU_CHEN_ECH7_Pos) /*!< BCCU CHEN: ECH7 Mask */\r
+#define BCCU_CHEN_ECH8_Pos 8 /*!< BCCU CHEN: ECH8 Position */\r
+#define BCCU_CHEN_ECH8_Msk (0x01UL << BCCU_CHEN_ECH8_Pos) /*!< BCCU CHEN: ECH8 Mask */\r
+\r
+/* --------------------------------- BCCU_CHOCON -------------------------------- */\r
+#define BCCU_CHOCON_CH0OP_Pos 0 /*!< BCCU CHOCON: CH0OP Position */\r
+#define BCCU_CHOCON_CH0OP_Msk (0x01UL << BCCU_CHOCON_CH0OP_Pos) /*!< BCCU CHOCON: CH0OP Mask */\r
+#define BCCU_CHOCON_CH1OP_Pos 1 /*!< BCCU CHOCON: CH1OP Position */\r
+#define BCCU_CHOCON_CH1OP_Msk (0x01UL << BCCU_CHOCON_CH1OP_Pos) /*!< BCCU CHOCON: CH1OP Mask */\r
+#define BCCU_CHOCON_CH2OP_Pos 2 /*!< BCCU CHOCON: CH2OP Position */\r
+#define BCCU_CHOCON_CH2OP_Msk (0x01UL << BCCU_CHOCON_CH2OP_Pos) /*!< BCCU CHOCON: CH2OP Mask */\r
+#define BCCU_CHOCON_CH3OP_Pos 3 /*!< BCCU CHOCON: CH3OP Position */\r
+#define BCCU_CHOCON_CH3OP_Msk (0x01UL << BCCU_CHOCON_CH3OP_Pos) /*!< BCCU CHOCON: CH3OP Mask */\r
+#define BCCU_CHOCON_CH4OP_Pos 4 /*!< BCCU CHOCON: CH4OP Position */\r
+#define BCCU_CHOCON_CH4OP_Msk (0x01UL << BCCU_CHOCON_CH4OP_Pos) /*!< BCCU CHOCON: CH4OP Mask */\r
+#define BCCU_CHOCON_CH5OP_Pos 5 /*!< BCCU CHOCON: CH5OP Position */\r
+#define BCCU_CHOCON_CH5OP_Msk (0x01UL << BCCU_CHOCON_CH5OP_Pos) /*!< BCCU CHOCON: CH5OP Mask */\r
+#define BCCU_CHOCON_CH6OP_Pos 6 /*!< BCCU CHOCON: CH6OP Position */\r
+#define BCCU_CHOCON_CH6OP_Msk (0x01UL << BCCU_CHOCON_CH6OP_Pos) /*!< BCCU CHOCON: CH6OP Mask */\r
+#define BCCU_CHOCON_CH7OP_Pos 7 /*!< BCCU CHOCON: CH7OP Position */\r
+#define BCCU_CHOCON_CH7OP_Msk (0x01UL << BCCU_CHOCON_CH7OP_Pos) /*!< BCCU CHOCON: CH7OP Mask */\r
+#define BCCU_CHOCON_CH8OP_Pos 8 /*!< BCCU CHOCON: CH8OP Position */\r
+#define BCCU_CHOCON_CH8OP_Msk (0x01UL << BCCU_CHOCON_CH8OP_Pos) /*!< BCCU CHOCON: CH8OP Mask */\r
+#define BCCU_CHOCON_CH0TPE_Pos 16 /*!< BCCU CHOCON: CH0TPE Position */\r
+#define BCCU_CHOCON_CH0TPE_Msk (0x01UL << BCCU_CHOCON_CH0TPE_Pos) /*!< BCCU CHOCON: CH0TPE Mask */\r
+#define BCCU_CHOCON_CH1TPE_Pos 17 /*!< BCCU CHOCON: CH1TPE Position */\r
+#define BCCU_CHOCON_CH1TPE_Msk (0x01UL << BCCU_CHOCON_CH1TPE_Pos) /*!< BCCU CHOCON: CH1TPE Mask */\r
+#define BCCU_CHOCON_CH2TPE_Pos 18 /*!< BCCU CHOCON: CH2TPE Position */\r
+#define BCCU_CHOCON_CH2TPE_Msk (0x01UL << BCCU_CHOCON_CH2TPE_Pos) /*!< BCCU CHOCON: CH2TPE Mask */\r
+#define BCCU_CHOCON_CH3TPE_Pos 19 /*!< BCCU CHOCON: CH3TPE Position */\r
+#define BCCU_CHOCON_CH3TPE_Msk (0x01UL << BCCU_CHOCON_CH3TPE_Pos) /*!< BCCU CHOCON: CH3TPE Mask */\r
+#define BCCU_CHOCON_CH4TPE_Pos 20 /*!< BCCU CHOCON: CH4TPE Position */\r
+#define BCCU_CHOCON_CH4TPE_Msk (0x01UL << BCCU_CHOCON_CH4TPE_Pos) /*!< BCCU CHOCON: CH4TPE Mask */\r
+#define BCCU_CHOCON_CH5TPE_Pos 21 /*!< BCCU CHOCON: CH5TPE Position */\r
+#define BCCU_CHOCON_CH5TPE_Msk (0x01UL << BCCU_CHOCON_CH5TPE_Pos) /*!< BCCU CHOCON: CH5TPE Mask */\r
+#define BCCU_CHOCON_CH6TPE_Pos 22 /*!< BCCU CHOCON: CH6TPE Position */\r
+#define BCCU_CHOCON_CH6TPE_Msk (0x01UL << BCCU_CHOCON_CH6TPE_Pos) /*!< BCCU CHOCON: CH6TPE Mask */\r
+#define BCCU_CHOCON_CH7TPE_Pos 23 /*!< BCCU CHOCON: CH7TPE Position */\r
+#define BCCU_CHOCON_CH7TPE_Msk (0x01UL << BCCU_CHOCON_CH7TPE_Pos) /*!< BCCU CHOCON: CH7TPE Mask */\r
+#define BCCU_CHOCON_CH8TPE_Pos 24 /*!< BCCU CHOCON: CH8TPE Position */\r
+#define BCCU_CHOCON_CH8TPE_Msk (0x01UL << BCCU_CHOCON_CH8TPE_Pos) /*!< BCCU CHOCON: CH8TPE Mask */\r
+\r
+/* --------------------------------- BCCU_CHTRIG -------------------------------- */\r
+#define BCCU_CHTRIG_ET0_Pos 0 /*!< BCCU CHTRIG: ET0 Position */\r
+#define BCCU_CHTRIG_ET0_Msk (0x01UL << BCCU_CHTRIG_ET0_Pos) /*!< BCCU CHTRIG: ET0 Mask */\r
+#define BCCU_CHTRIG_ET1_Pos 1 /*!< BCCU CHTRIG: ET1 Position */\r
+#define BCCU_CHTRIG_ET1_Msk (0x01UL << BCCU_CHTRIG_ET1_Pos) /*!< BCCU CHTRIG: ET1 Mask */\r
+#define BCCU_CHTRIG_ET2_Pos 2 /*!< BCCU CHTRIG: ET2 Position */\r
+#define BCCU_CHTRIG_ET2_Msk (0x01UL << BCCU_CHTRIG_ET2_Pos) /*!< BCCU CHTRIG: ET2 Mask */\r
+#define BCCU_CHTRIG_ET3_Pos 3 /*!< BCCU CHTRIG: ET3 Position */\r
+#define BCCU_CHTRIG_ET3_Msk (0x01UL << BCCU_CHTRIG_ET3_Pos) /*!< BCCU CHTRIG: ET3 Mask */\r
+#define BCCU_CHTRIG_ET4_Pos 4 /*!< BCCU CHTRIG: ET4 Position */\r
+#define BCCU_CHTRIG_ET4_Msk (0x01UL << BCCU_CHTRIG_ET4_Pos) /*!< BCCU CHTRIG: ET4 Mask */\r
+#define BCCU_CHTRIG_ET5_Pos 5 /*!< BCCU CHTRIG: ET5 Position */\r
+#define BCCU_CHTRIG_ET5_Msk (0x01UL << BCCU_CHTRIG_ET5_Pos) /*!< BCCU CHTRIG: ET5 Mask */\r
+#define BCCU_CHTRIG_ET6_Pos 6 /*!< BCCU CHTRIG: ET6 Position */\r
+#define BCCU_CHTRIG_ET6_Msk (0x01UL << BCCU_CHTRIG_ET6_Pos) /*!< BCCU CHTRIG: ET6 Mask */\r
+#define BCCU_CHTRIG_ET7_Pos 7 /*!< BCCU CHTRIG: ET7 Position */\r
+#define BCCU_CHTRIG_ET7_Msk (0x01UL << BCCU_CHTRIG_ET7_Pos) /*!< BCCU CHTRIG: ET7 Mask */\r
+#define BCCU_CHTRIG_ET8_Pos 8 /*!< BCCU CHTRIG: ET8 Position */\r
+#define BCCU_CHTRIG_ET8_Msk (0x01UL << BCCU_CHTRIG_ET8_Pos) /*!< BCCU CHTRIG: ET8 Mask */\r
+#define BCCU_CHTRIG_TOS0_Pos 16 /*!< BCCU CHTRIG: TOS0 Position */\r
+#define BCCU_CHTRIG_TOS0_Msk (0x01UL << BCCU_CHTRIG_TOS0_Pos) /*!< BCCU CHTRIG: TOS0 Mask */\r
+#define BCCU_CHTRIG_TOS1_Pos 17 /*!< BCCU CHTRIG: TOS1 Position */\r
+#define BCCU_CHTRIG_TOS1_Msk (0x01UL << BCCU_CHTRIG_TOS1_Pos) /*!< BCCU CHTRIG: TOS1 Mask */\r
+#define BCCU_CHTRIG_TOS2_Pos 18 /*!< BCCU CHTRIG: TOS2 Position */\r
+#define BCCU_CHTRIG_TOS2_Msk (0x01UL << BCCU_CHTRIG_TOS2_Pos) /*!< BCCU CHTRIG: TOS2 Mask */\r
+#define BCCU_CHTRIG_TOS3_Pos 19 /*!< BCCU CHTRIG: TOS3 Position */\r
+#define BCCU_CHTRIG_TOS3_Msk (0x01UL << BCCU_CHTRIG_TOS3_Pos) /*!< BCCU CHTRIG: TOS3 Mask */\r
+#define BCCU_CHTRIG_TOS4_Pos 20 /*!< BCCU CHTRIG: TOS4 Position */\r
+#define BCCU_CHTRIG_TOS4_Msk (0x01UL << BCCU_CHTRIG_TOS4_Pos) /*!< BCCU CHTRIG: TOS4 Mask */\r
+#define BCCU_CHTRIG_TOS5_Pos 21 /*!< BCCU CHTRIG: TOS5 Position */\r
+#define BCCU_CHTRIG_TOS5_Msk (0x01UL << BCCU_CHTRIG_TOS5_Pos) /*!< BCCU CHTRIG: TOS5 Mask */\r
+#define BCCU_CHTRIG_TOS6_Pos 22 /*!< BCCU CHTRIG: TOS6 Position */\r
+#define BCCU_CHTRIG_TOS6_Msk (0x01UL << BCCU_CHTRIG_TOS6_Pos) /*!< BCCU CHTRIG: TOS6 Mask */\r
+#define BCCU_CHTRIG_TOS7_Pos 23 /*!< BCCU CHTRIG: TOS7 Position */\r
+#define BCCU_CHTRIG_TOS7_Msk (0x01UL << BCCU_CHTRIG_TOS7_Pos) /*!< BCCU CHTRIG: TOS7 Mask */\r
+#define BCCU_CHTRIG_TOS8_Pos 24 /*!< BCCU CHTRIG: TOS8 Position */\r
+#define BCCU_CHTRIG_TOS8_Msk (0x01UL << BCCU_CHTRIG_TOS8_Pos) /*!< BCCU CHTRIG: TOS8 Mask */\r
+\r
+/* -------------------------------- BCCU_CHSTRCON ------------------------------- */\r
+#define BCCU_CHSTRCON_CH0S_Pos 0 /*!< BCCU CHSTRCON: CH0S Position */\r
+#define BCCU_CHSTRCON_CH0S_Msk (0x01UL << BCCU_CHSTRCON_CH0S_Pos) /*!< BCCU CHSTRCON: CH0S Mask */\r
+#define BCCU_CHSTRCON_CH1S_Pos 1 /*!< BCCU CHSTRCON: CH1S Position */\r
+#define BCCU_CHSTRCON_CH1S_Msk (0x01UL << BCCU_CHSTRCON_CH1S_Pos) /*!< BCCU CHSTRCON: CH1S Mask */\r
+#define BCCU_CHSTRCON_CH2S_Pos 2 /*!< BCCU CHSTRCON: CH2S Position */\r
+#define BCCU_CHSTRCON_CH2S_Msk (0x01UL << BCCU_CHSTRCON_CH2S_Pos) /*!< BCCU CHSTRCON: CH2S Mask */\r
+#define BCCU_CHSTRCON_CH3S_Pos 3 /*!< BCCU CHSTRCON: CH3S Position */\r
+#define BCCU_CHSTRCON_CH3S_Msk (0x01UL << BCCU_CHSTRCON_CH3S_Pos) /*!< BCCU CHSTRCON: CH3S Mask */\r
+#define BCCU_CHSTRCON_CH4S_Pos 4 /*!< BCCU CHSTRCON: CH4S Position */\r
+#define BCCU_CHSTRCON_CH4S_Msk (0x01UL << BCCU_CHSTRCON_CH4S_Pos) /*!< BCCU CHSTRCON: CH4S Mask */\r
+#define BCCU_CHSTRCON_CH5S_Pos 5 /*!< BCCU CHSTRCON: CH5S Position */\r
+#define BCCU_CHSTRCON_CH5S_Msk (0x01UL << BCCU_CHSTRCON_CH5S_Pos) /*!< BCCU CHSTRCON: CH5S Mask */\r
+#define BCCU_CHSTRCON_CH6S_Pos 6 /*!< BCCU CHSTRCON: CH6S Position */\r
+#define BCCU_CHSTRCON_CH6S_Msk (0x01UL << BCCU_CHSTRCON_CH6S_Pos) /*!< BCCU CHSTRCON: CH6S Mask */\r
+#define BCCU_CHSTRCON_CH7S_Pos 7 /*!< BCCU CHSTRCON: CH7S Position */\r
+#define BCCU_CHSTRCON_CH7S_Msk (0x01UL << BCCU_CHSTRCON_CH7S_Pos) /*!< BCCU CHSTRCON: CH7S Mask */\r
+#define BCCU_CHSTRCON_CH8S_Pos 8 /*!< BCCU CHSTRCON: CH8S Position */\r
+#define BCCU_CHSTRCON_CH8S_Msk (0x01UL << BCCU_CHSTRCON_CH8S_Pos) /*!< BCCU CHSTRCON: CH8S Mask */\r
+#define BCCU_CHSTRCON_CH0A_Pos 16 /*!< BCCU CHSTRCON: CH0A Position */\r
+#define BCCU_CHSTRCON_CH0A_Msk (0x01UL << BCCU_CHSTRCON_CH0A_Pos) /*!< BCCU CHSTRCON: CH0A Mask */\r
+#define BCCU_CHSTRCON_CH1A_Pos 17 /*!< BCCU CHSTRCON: CH1A Position */\r
+#define BCCU_CHSTRCON_CH1A_Msk (0x01UL << BCCU_CHSTRCON_CH1A_Pos) /*!< BCCU CHSTRCON: CH1A Mask */\r
+#define BCCU_CHSTRCON_CH2A_Pos 18 /*!< BCCU CHSTRCON: CH2A Position */\r
+#define BCCU_CHSTRCON_CH2A_Msk (0x01UL << BCCU_CHSTRCON_CH2A_Pos) /*!< BCCU CHSTRCON: CH2A Mask */\r
+#define BCCU_CHSTRCON_CH3A_Pos 19 /*!< BCCU CHSTRCON: CH3A Position */\r
+#define BCCU_CHSTRCON_CH3A_Msk (0x01UL << BCCU_CHSTRCON_CH3A_Pos) /*!< BCCU CHSTRCON: CH3A Mask */\r
+#define BCCU_CHSTRCON_CH4A_Pos 20 /*!< BCCU CHSTRCON: CH4A Position */\r
+#define BCCU_CHSTRCON_CH4A_Msk (0x01UL << BCCU_CHSTRCON_CH4A_Pos) /*!< BCCU CHSTRCON: CH4A Mask */\r
+#define BCCU_CHSTRCON_CH5A_Pos 21 /*!< BCCU CHSTRCON: CH5A Position */\r
+#define BCCU_CHSTRCON_CH5A_Msk (0x01UL << BCCU_CHSTRCON_CH5A_Pos) /*!< BCCU CHSTRCON: CH5A Mask */\r
+#define BCCU_CHSTRCON_CH6A_Pos 22 /*!< BCCU CHSTRCON: CH6A Position */\r
+#define BCCU_CHSTRCON_CH6A_Msk (0x01UL << BCCU_CHSTRCON_CH6A_Pos) /*!< BCCU CHSTRCON: CH6A Mask */\r
+#define BCCU_CHSTRCON_CH7A_Pos 23 /*!< BCCU CHSTRCON: CH7A Position */\r
+#define BCCU_CHSTRCON_CH7A_Msk (0x01UL << BCCU_CHSTRCON_CH7A_Pos) /*!< BCCU CHSTRCON: CH7A Mask */\r
+#define BCCU_CHSTRCON_CH8A_Pos 24 /*!< BCCU CHSTRCON: CH8A Position */\r
+#define BCCU_CHSTRCON_CH8A_Msk (0x01UL << BCCU_CHSTRCON_CH8A_Pos) /*!< BCCU CHSTRCON: CH8A Mask */\r
+\r
+/* --------------------------------- BCCU_LTCHOL -------------------------------- */\r
+#define BCCU_LTCHOL_LTOL0_Pos 0 /*!< BCCU LTCHOL: LTOL0 Position */\r
+#define BCCU_LTCHOL_LTOL0_Msk (0x01UL << BCCU_LTCHOL_LTOL0_Pos) /*!< BCCU LTCHOL: LTOL0 Mask */\r
+#define BCCU_LTCHOL_LTOL1_Pos 1 /*!< BCCU LTCHOL: LTOL1 Position */\r
+#define BCCU_LTCHOL_LTOL1_Msk (0x01UL << BCCU_LTCHOL_LTOL1_Pos) /*!< BCCU LTCHOL: LTOL1 Mask */\r
+#define BCCU_LTCHOL_LTOL2_Pos 2 /*!< BCCU LTCHOL: LTOL2 Position */\r
+#define BCCU_LTCHOL_LTOL2_Msk (0x01UL << BCCU_LTCHOL_LTOL2_Pos) /*!< BCCU LTCHOL: LTOL2 Mask */\r
+#define BCCU_LTCHOL_LTOL3_Pos 3 /*!< BCCU LTCHOL: LTOL3 Position */\r
+#define BCCU_LTCHOL_LTOL3_Msk (0x01UL << BCCU_LTCHOL_LTOL3_Pos) /*!< BCCU LTCHOL: LTOL3 Mask */\r
+#define BCCU_LTCHOL_LTOL4_Pos 4 /*!< BCCU LTCHOL: LTOL4 Position */\r
+#define BCCU_LTCHOL_LTOL4_Msk (0x01UL << BCCU_LTCHOL_LTOL4_Pos) /*!< BCCU LTCHOL: LTOL4 Mask */\r
+#define BCCU_LTCHOL_LTOL5_Pos 5 /*!< BCCU LTCHOL: LTOL5 Position */\r
+#define BCCU_LTCHOL_LTOL5_Msk (0x01UL << BCCU_LTCHOL_LTOL5_Pos) /*!< BCCU LTCHOL: LTOL5 Mask */\r
+#define BCCU_LTCHOL_LTOL6_Pos 6 /*!< BCCU LTCHOL: LTOL6 Position */\r
+#define BCCU_LTCHOL_LTOL6_Msk (0x01UL << BCCU_LTCHOL_LTOL6_Pos) /*!< BCCU LTCHOL: LTOL6 Mask */\r
+#define BCCU_LTCHOL_LTOL7_Pos 7 /*!< BCCU LTCHOL: LTOL7 Position */\r
+#define BCCU_LTCHOL_LTOL7_Msk (0x01UL << BCCU_LTCHOL_LTOL7_Pos) /*!< BCCU LTCHOL: LTOL7 Mask */\r
+#define BCCU_LTCHOL_LTOL8_Pos 8 /*!< BCCU LTCHOL: LTOL8 Position */\r
+#define BCCU_LTCHOL_LTOL8_Msk (0x01UL << BCCU_LTCHOL_LTOL8_Pos) /*!< BCCU LTCHOL: LTOL8 Mask */\r
+\r
+/* ---------------------------------- BCCU_DEEN --------------------------------- */\r
+#define BCCU_DEEN_EDE0_Pos 0 /*!< BCCU DEEN: EDE0 Position */\r
+#define BCCU_DEEN_EDE0_Msk (0x01UL << BCCU_DEEN_EDE0_Pos) /*!< BCCU DEEN: EDE0 Mask */\r
+#define BCCU_DEEN_EDE1_Pos 1 /*!< BCCU DEEN: EDE1 Position */\r
+#define BCCU_DEEN_EDE1_Msk (0x01UL << BCCU_DEEN_EDE1_Pos) /*!< BCCU DEEN: EDE1 Mask */\r
+#define BCCU_DEEN_EDE2_Pos 2 /*!< BCCU DEEN: EDE2 Position */\r
+#define BCCU_DEEN_EDE2_Msk (0x01UL << BCCU_DEEN_EDE2_Pos) /*!< BCCU DEEN: EDE2 Mask */\r
+\r
+/* -------------------------------- BCCU_DESTRCON ------------------------------- */\r
+#define BCCU_DESTRCON_DE0S_Pos 0 /*!< BCCU DESTRCON: DE0S Position */\r
+#define BCCU_DESTRCON_DE0S_Msk (0x01UL << BCCU_DESTRCON_DE0S_Pos) /*!< BCCU DESTRCON: DE0S Mask */\r
+#define BCCU_DESTRCON_DE1S_Pos 1 /*!< BCCU DESTRCON: DE1S Position */\r
+#define BCCU_DESTRCON_DE1S_Msk (0x01UL << BCCU_DESTRCON_DE1S_Pos) /*!< BCCU DESTRCON: DE1S Mask */\r
+#define BCCU_DESTRCON_DE2S_Pos 2 /*!< BCCU DESTRCON: DE2S Position */\r
+#define BCCU_DESTRCON_DE2S_Msk (0x01UL << BCCU_DESTRCON_DE2S_Pos) /*!< BCCU DESTRCON: DE2S Mask */\r
+#define BCCU_DESTRCON_DE0A_Pos 16 /*!< BCCU DESTRCON: DE0A Position */\r
+#define BCCU_DESTRCON_DE0A_Msk (0x01UL << BCCU_DESTRCON_DE0A_Pos) /*!< BCCU DESTRCON: DE0A Mask */\r
+#define BCCU_DESTRCON_DE1A_Pos 17 /*!< BCCU DESTRCON: DE1A Position */\r
+#define BCCU_DESTRCON_DE1A_Msk (0x01UL << BCCU_DESTRCON_DE1A_Pos) /*!< BCCU DESTRCON: DE1A Mask */\r
+#define BCCU_DESTRCON_DE2A_Pos 18 /*!< BCCU DESTRCON: DE2A Position */\r
+#define BCCU_DESTRCON_DE2A_Msk (0x01UL << BCCU_DESTRCON_DE2A_Pos) /*!< BCCU DESTRCON: DE2A Mask */\r
+\r
+/* -------------------------------- BCCU_GLOBDIM -------------------------------- */\r
+#define BCCU_GLOBDIM_GLOBDIM_Pos 0 /*!< BCCU GLOBDIM: GLOBDIM Position */\r
+#define BCCU_GLOBDIM_GLOBDIM_Msk (0x00000fffUL << BCCU_GLOBDIM_GLOBDIM_Pos) /*!< BCCU GLOBDIM: GLOBDIM Mask */\r
+\r
+/* --------------------------------- BCCU_EVIER --------------------------------- */\r
+#define BCCU_EVIER_T0IEN_Pos 0 /*!< BCCU EVIER: T0IEN Position */\r
+#define BCCU_EVIER_T0IEN_Msk (0x01UL << BCCU_EVIER_T0IEN_Pos) /*!< BCCU EVIER: T0IEN Mask */\r
+#define BCCU_EVIER_T1IEN_Pos 1 /*!< BCCU EVIER: T1IEN Position */\r
+#define BCCU_EVIER_T1IEN_Msk (0x01UL << BCCU_EVIER_T1IEN_Pos) /*!< BCCU EVIER: T1IEN Mask */\r
+#define BCCU_EVIER_FIEN_Pos 2 /*!< BCCU EVIER: FIEN Position */\r
+#define BCCU_EVIER_FIEN_Msk (0x01UL << BCCU_EVIER_FIEN_Pos) /*!< BCCU EVIER: FIEN Mask */\r
+#define BCCU_EVIER_EIEN_Pos 3 /*!< BCCU EVIER: EIEN Position */\r
+#define BCCU_EVIER_EIEN_Msk (0x01UL << BCCU_EVIER_EIEN_Pos) /*!< BCCU EVIER: EIEN Mask */\r
+#define BCCU_EVIER_TPIEN_Pos 4 /*!< BCCU EVIER: TPIEN Position */\r
+#define BCCU_EVIER_TPIEN_Msk (0x01UL << BCCU_EVIER_TPIEN_Pos) /*!< BCCU EVIER: TPIEN Mask */\r
+\r
+/* ---------------------------------- BCCU_EVFR --------------------------------- */\r
+#define BCCU_EVFR_T0F_Pos 0 /*!< BCCU EVFR: T0F Position */\r
+#define BCCU_EVFR_T0F_Msk (0x01UL << BCCU_EVFR_T0F_Pos) /*!< BCCU EVFR: T0F Mask */\r
+#define BCCU_EVFR_T1F_Pos 1 /*!< BCCU EVFR: T1F Position */\r
+#define BCCU_EVFR_T1F_Msk (0x01UL << BCCU_EVFR_T1F_Pos) /*!< BCCU EVFR: T1F Mask */\r
+#define BCCU_EVFR_FF_Pos 2 /*!< BCCU EVFR: FF Position */\r
+#define BCCU_EVFR_FF_Msk (0x01UL << BCCU_EVFR_FF_Pos) /*!< BCCU EVFR: FF Mask */\r
+#define BCCU_EVFR_EF_Pos 3 /*!< BCCU EVFR: EF Position */\r
+#define BCCU_EVFR_EF_Msk (0x01UL << BCCU_EVFR_EF_Pos) /*!< BCCU EVFR: EF Mask */\r
+#define BCCU_EVFR_TPF_Pos 4 /*!< BCCU EVFR: TPF Position */\r
+#define BCCU_EVFR_TPF_Msk (0x01UL << BCCU_EVFR_TPF_Pos) /*!< BCCU EVFR: TPF Mask */\r
+#define BCCU_EVFR_TPSF_Pos 6 /*!< BCCU EVFR: TPSF Position */\r
+#define BCCU_EVFR_TPSF_Msk (0x01UL << BCCU_EVFR_TPSF_Pos) /*!< BCCU EVFR: TPSF Mask */\r
+#define BCCU_EVFR_TPINL_Pos 7 /*!< BCCU EVFR: TPINL Position */\r
+#define BCCU_EVFR_TPINL_Msk (0x01UL << BCCU_EVFR_TPINL_Pos) /*!< BCCU EVFR: TPINL Mask */\r
+\r
+/* --------------------------------- BCCU_EVFSR --------------------------------- */\r
+#define BCCU_EVFSR_T0FS_Pos 0 /*!< BCCU EVFSR: T0FS Position */\r
+#define BCCU_EVFSR_T0FS_Msk (0x01UL << BCCU_EVFSR_T0FS_Pos) /*!< BCCU EVFSR: T0FS Mask */\r
+#define BCCU_EVFSR_T1FS_Pos 1 /*!< BCCU EVFSR: T1FS Position */\r
+#define BCCU_EVFSR_T1FS_Msk (0x01UL << BCCU_EVFSR_T1FS_Pos) /*!< BCCU EVFSR: T1FS Mask */\r
+#define BCCU_EVFSR_FFS_Pos 2 /*!< BCCU EVFSR: FFS Position */\r
+#define BCCU_EVFSR_FFS_Msk (0x01UL << BCCU_EVFSR_FFS_Pos) /*!< BCCU EVFSR: FFS Mask */\r
+#define BCCU_EVFSR_EFS_Pos 3 /*!< BCCU EVFSR: EFS Position */\r
+#define BCCU_EVFSR_EFS_Msk (0x01UL << BCCU_EVFSR_EFS_Pos) /*!< BCCU EVFSR: EFS Mask */\r
+#define BCCU_EVFSR_TPFS_Pos 4 /*!< BCCU EVFSR: TPFS Position */\r
+#define BCCU_EVFSR_TPFS_Msk (0x01UL << BCCU_EVFSR_TPFS_Pos) /*!< BCCU EVFSR: TPFS Mask */\r
+#define BCCU_EVFSR_TPS_Pos 6 /*!< BCCU EVFSR: TPS Position */\r
+#define BCCU_EVFSR_TPS_Msk (0x01UL << BCCU_EVFSR_TPS_Pos) /*!< BCCU EVFSR: TPS Mask */\r
+\r
+/* --------------------------------- BCCU_EVFCR --------------------------------- */\r
+#define BCCU_EVFCR_T0FC_Pos 0 /*!< BCCU EVFCR: T0FC Position */\r
+#define BCCU_EVFCR_T0FC_Msk (0x01UL << BCCU_EVFCR_T0FC_Pos) /*!< BCCU EVFCR: T0FC Mask */\r
+#define BCCU_EVFCR_T1FC_Pos 1 /*!< BCCU EVFCR: T1FC Position */\r
+#define BCCU_EVFCR_T1FC_Msk (0x01UL << BCCU_EVFCR_T1FC_Pos) /*!< BCCU EVFCR: T1FC Mask */\r
+#define BCCU_EVFCR_FFC_Pos 2 /*!< BCCU EVFCR: FFC Position */\r
+#define BCCU_EVFCR_FFC_Msk (0x01UL << BCCU_EVFCR_FFC_Pos) /*!< BCCU EVFCR: FFC Mask */\r
+#define BCCU_EVFCR_EFC_Pos 3 /*!< BCCU EVFCR: EFC Position */\r
+#define BCCU_EVFCR_EFC_Msk (0x01UL << BCCU_EVFCR_EFC_Pos) /*!< BCCU EVFCR: EFC Mask */\r
+#define BCCU_EVFCR_TPFC_Pos 4 /*!< BCCU EVFCR: TPFC Position */\r
+#define BCCU_EVFCR_TPFC_Msk (0x01UL << BCCU_EVFCR_TPFC_Pos) /*!< BCCU EVFCR: TPFC Mask */\r
+#define BCCU_EVFCR_TPC_Pos 6 /*!< BCCU EVFCR: TPC Position */\r
+#define BCCU_EVFCR_TPC_Msk (0x01UL << BCCU_EVFCR_TPC_Pos) /*!< BCCU EVFCR: TPC Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'BCCU_CH' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* -------------------------------- BCCU_CH_INTS -------------------------------- */\r
+#define BCCU_CH_INTS_TCHINT_Pos 0 /*!< BCCU_CH INTS: TCHINT Position */\r
+#define BCCU_CH_INTS_TCHINT_Msk (0x00000fffUL << BCCU_CH_INTS_TCHINT_Pos) /*!< BCCU_CH INTS: TCHINT Mask */\r
+\r
+/* --------------------------------- BCCU_CH_INT -------------------------------- */\r
+#define BCCU_CH_INT_CHINT_Pos 0 /*!< BCCU_CH INT: CHINT Position */\r
+#define BCCU_CH_INT_CHINT_Msk (0x00000fffUL << BCCU_CH_INT_CHINT_Pos) /*!< BCCU_CH INT: CHINT Mask */\r
+\r
+/* ------------------------------ BCCU_CH_CHCONFIG ------------------------------ */\r
+#define BCCU_CH_CHCONFIG_PKTH_Pos 0 /*!< BCCU_CH CHCONFIG: PKTH Position */\r
+#define BCCU_CH_CHCONFIG_PKTH_Msk (0x07UL << BCCU_CH_CHCONFIG_PKTH_Pos) /*!< BCCU_CH CHCONFIG: PKTH Mask */\r
+#define BCCU_CH_CHCONFIG_PEN_Pos 3 /*!< BCCU_CH CHCONFIG: PEN Position */\r
+#define BCCU_CH_CHCONFIG_PEN_Msk (0x01UL << BCCU_CH_CHCONFIG_PEN_Pos) /*!< BCCU_CH CHCONFIG: PEN Mask */\r
+#define BCCU_CH_CHCONFIG_DSEL_Pos 4 /*!< BCCU_CH CHCONFIG: DSEL Position */\r
+#define BCCU_CH_CHCONFIG_DSEL_Msk (0x07UL << BCCU_CH_CHCONFIG_DSEL_Pos) /*!< BCCU_CH CHCONFIG: DSEL Mask */\r
+#define BCCU_CH_CHCONFIG_DBP_Pos 7 /*!< BCCU_CH CHCONFIG: DBP Position */\r
+#define BCCU_CH_CHCONFIG_DBP_Msk (0x01UL << BCCU_CH_CHCONFIG_DBP_Pos) /*!< BCCU_CH CHCONFIG: DBP Mask */\r
+#define BCCU_CH_CHCONFIG_GEN_Pos 8 /*!< BCCU_CH CHCONFIG: GEN Position */\r
+#define BCCU_CH_CHCONFIG_GEN_Msk (0x01UL << BCCU_CH_CHCONFIG_GEN_Pos) /*!< BCCU_CH CHCONFIG: GEN Mask */\r
+#define BCCU_CH_CHCONFIG_WEN_Pos 9 /*!< BCCU_CH CHCONFIG: WEN Position */\r
+#define BCCU_CH_CHCONFIG_WEN_Msk (0x01UL << BCCU_CH_CHCONFIG_WEN_Pos) /*!< BCCU_CH CHCONFIG: WEN Mask */\r
+#define BCCU_CH_CHCONFIG_TRED_Pos 10 /*!< BCCU_CH CHCONFIG: TRED Position */\r
+#define BCCU_CH_CHCONFIG_TRED_Msk (0x01UL << BCCU_CH_CHCONFIG_TRED_Pos) /*!< BCCU_CH CHCONFIG: TRED Mask */\r
+#define BCCU_CH_CHCONFIG_ENFT_Pos 11 /*!< BCCU_CH CHCONFIG: ENFT Position */\r
+#define BCCU_CH_CHCONFIG_ENFT_Msk (0x01UL << BCCU_CH_CHCONFIG_ENFT_Pos) /*!< BCCU_CH CHCONFIG: ENFT Mask */\r
+#define BCCU_CH_CHCONFIG_LINPRES_Pos 16 /*!< BCCU_CH CHCONFIG: LINPRES Position */\r
+#define BCCU_CH_CHCONFIG_LINPRES_Msk (0x000003ffUL << BCCU_CH_CHCONFIG_LINPRES_Pos) /*!< BCCU_CH CHCONFIG: LINPRES Mask */\r
+\r
+/* -------------------------------- BCCU_CH_PKCMP ------------------------------- */\r
+#define BCCU_CH_PKCMP_OFFCMP_Pos 0 /*!< BCCU_CH PKCMP: OFFCMP Position */\r
+#define BCCU_CH_PKCMP_OFFCMP_Msk (0x000000ffUL << BCCU_CH_PKCMP_OFFCMP_Pos) /*!< BCCU_CH PKCMP: OFFCMP Mask */\r
+#define BCCU_CH_PKCMP_ONCMP_Pos 16 /*!< BCCU_CH PKCMP: ONCMP Position */\r
+#define BCCU_CH_PKCMP_ONCMP_Msk (0x000000ffUL << BCCU_CH_PKCMP_ONCMP_Pos) /*!< BCCU_CH PKCMP: ONCMP Mask */\r
+\r
+/* ------------------------------- BCCU_CH_PKCNTR ------------------------------- */\r
+#define BCCU_CH_PKCNTR_OFFCNTVAL_Pos 0 /*!< BCCU_CH PKCNTR: OFFCNTVAL Position */\r
+#define BCCU_CH_PKCNTR_OFFCNTVAL_Msk (0x000000ffUL << BCCU_CH_PKCNTR_OFFCNTVAL_Pos) /*!< BCCU_CH PKCNTR: OFFCNTVAL Mask */\r
+#define BCCU_CH_PKCNTR_ONCNTVAL_Pos 16 /*!< BCCU_CH PKCNTR: ONCNTVAL Position */\r
+#define BCCU_CH_PKCNTR_ONCNTVAL_Msk (0x000000ffUL << BCCU_CH_PKCNTR_ONCNTVAL_Pos) /*!< BCCU_CH PKCNTR: ONCNTVAL Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Group 'BCCU_DE' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* --------------------------------- BCCU_DE_DLS -------------------------------- */\r
+#define BCCU_DE_DLS_TDLEV_Pos 0 /*!< BCCU_DE DLS: TDLEV Position */\r
+#define BCCU_DE_DLS_TDLEV_Msk (0x00000fffUL << BCCU_DE_DLS_TDLEV_Pos) /*!< BCCU_DE DLS: TDLEV Mask */\r
+\r
+/* --------------------------------- BCCU_DE_DL --------------------------------- */\r
+#define BCCU_DE_DL_DLEV_Pos 0 /*!< BCCU_DE DL: DLEV Position */\r
+#define BCCU_DE_DL_DLEV_Msk (0x00000fffUL << BCCU_DE_DL_DLEV_Pos) /*!< BCCU_DE DL: DLEV Mask */\r
+\r
+/* --------------------------------- BCCU_DE_DTT -------------------------------- */\r
+#define BCCU_DE_DTT_DIMDIV_Pos 0 /*!< BCCU_DE DTT: DIMDIV Position */\r
+#define BCCU_DE_DTT_DIMDIV_Msk (0x000003ffUL << BCCU_DE_DTT_DIMDIV_Pos) /*!< BCCU_DE DTT: DIMDIV Mask */\r
+#define BCCU_DE_DTT_DTEN_Pos 16 /*!< BCCU_DE DTT: DTEN Position */\r
+#define BCCU_DE_DTT_DTEN_Msk (0x01UL << BCCU_DE_DTT_DTEN_Pos) /*!< BCCU_DE DTT: DTEN Mask */\r
+#define BCCU_DE_DTT_CSEL_Pos 17 /*!< BCCU_DE DTT: CSEL Position */\r
+#define BCCU_DE_DTT_CSEL_Msk (0x01UL << BCCU_DE_DTT_CSEL_Pos) /*!< BCCU_DE DTT: CSEL Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PORT0' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- PORT0_OUT --------------------------------- */\r
+#define PORT0_OUT_P0_Pos 0 /*!< PORT0 OUT: P0 Position */\r
+#define PORT0_OUT_P0_Msk (0x01UL << PORT0_OUT_P0_Pos) /*!< PORT0 OUT: P0 Mask */\r
+#define PORT0_OUT_P1_Pos 1 /*!< PORT0 OUT: P1 Position */\r
+#define PORT0_OUT_P1_Msk (0x01UL << PORT0_OUT_P1_Pos) /*!< PORT0 OUT: P1 Mask */\r
+#define PORT0_OUT_P2_Pos 2 /*!< PORT0 OUT: P2 Position */\r
+#define PORT0_OUT_P2_Msk (0x01UL << PORT0_OUT_P2_Pos) /*!< PORT0 OUT: P2 Mask */\r
+#define PORT0_OUT_P3_Pos 3 /*!< PORT0 OUT: P3 Position */\r
+#define PORT0_OUT_P3_Msk (0x01UL << PORT0_OUT_P3_Pos) /*!< PORT0 OUT: P3 Mask */\r
+#define PORT0_OUT_P4_Pos 4 /*!< PORT0 OUT: P4 Position */\r
+#define PORT0_OUT_P4_Msk (0x01UL << PORT0_OUT_P4_Pos) /*!< PORT0 OUT: P4 Mask */\r
+#define PORT0_OUT_P5_Pos 5 /*!< PORT0 OUT: P5 Position */\r
+#define PORT0_OUT_P5_Msk (0x01UL << PORT0_OUT_P5_Pos) /*!< PORT0 OUT: P5 Mask */\r
+#define PORT0_OUT_P6_Pos 6 /*!< PORT0 OUT: P6 Position */\r
+#define PORT0_OUT_P6_Msk (0x01UL << PORT0_OUT_P6_Pos) /*!< PORT0 OUT: P6 Mask */\r
+#define PORT0_OUT_P7_Pos 7 /*!< PORT0 OUT: P7 Position */\r
+#define PORT0_OUT_P7_Msk (0x01UL << PORT0_OUT_P7_Pos) /*!< PORT0 OUT: P7 Mask */\r
+#define PORT0_OUT_P8_Pos 8 /*!< PORT0 OUT: P8 Position */\r
+#define PORT0_OUT_P8_Msk (0x01UL << PORT0_OUT_P8_Pos) /*!< PORT0 OUT: P8 Mask */\r
+#define PORT0_OUT_P9_Pos 9 /*!< PORT0 OUT: P9 Position */\r
+#define PORT0_OUT_P9_Msk (0x01UL << PORT0_OUT_P9_Pos) /*!< PORT0 OUT: P9 Mask */\r
+#define PORT0_OUT_P10_Pos 10 /*!< PORT0 OUT: P10 Position */\r
+#define PORT0_OUT_P10_Msk (0x01UL << PORT0_OUT_P10_Pos) /*!< PORT0 OUT: P10 Mask */\r
+#define PORT0_OUT_P11_Pos 11 /*!< PORT0 OUT: P11 Position */\r
+#define PORT0_OUT_P11_Msk (0x01UL << PORT0_OUT_P11_Pos) /*!< PORT0 OUT: P11 Mask */\r
+#define PORT0_OUT_P12_Pos 12 /*!< PORT0 OUT: P12 Position */\r
+#define PORT0_OUT_P12_Msk (0x01UL << PORT0_OUT_P12_Pos) /*!< PORT0 OUT: P12 Mask */\r
+#define PORT0_OUT_P13_Pos 13 /*!< PORT0 OUT: P13 Position */\r
+#define PORT0_OUT_P13_Msk (0x01UL << PORT0_OUT_P13_Pos) /*!< PORT0 OUT: P13 Mask */\r
+#define PORT0_OUT_P14_Pos 14 /*!< PORT0 OUT: P14 Position */\r
+#define PORT0_OUT_P14_Msk (0x01UL << PORT0_OUT_P14_Pos) /*!< PORT0 OUT: P14 Mask */\r
+#define PORT0_OUT_P15_Pos 15 /*!< PORT0 OUT: P15 Position */\r
+#define PORT0_OUT_P15_Msk (0x01UL << PORT0_OUT_P15_Pos) /*!< PORT0 OUT: P15 Mask */\r
+\r
+/* ---------------------------------- PORT0_OMR --------------------------------- */\r
+#define PORT0_OMR_PS0_Pos 0 /*!< PORT0 OMR: PS0 Position */\r
+#define PORT0_OMR_PS0_Msk (0x01UL << PORT0_OMR_PS0_Pos) /*!< PORT0 OMR: PS0 Mask */\r
+#define PORT0_OMR_PS1_Pos 1 /*!< PORT0 OMR: PS1 Position */\r
+#define PORT0_OMR_PS1_Msk (0x01UL << PORT0_OMR_PS1_Pos) /*!< PORT0 OMR: PS1 Mask */\r
+#define PORT0_OMR_PS2_Pos 2 /*!< PORT0 OMR: PS2 Position */\r
+#define PORT0_OMR_PS2_Msk (0x01UL << PORT0_OMR_PS2_Pos) /*!< PORT0 OMR: PS2 Mask */\r
+#define PORT0_OMR_PS3_Pos 3 /*!< PORT0 OMR: PS3 Position */\r
+#define PORT0_OMR_PS3_Msk (0x01UL << PORT0_OMR_PS3_Pos) /*!< PORT0 OMR: PS3 Mask */\r
+#define PORT0_OMR_PS4_Pos 4 /*!< PORT0 OMR: PS4 Position */\r
+#define PORT0_OMR_PS4_Msk (0x01UL << PORT0_OMR_PS4_Pos) /*!< PORT0 OMR: PS4 Mask */\r
+#define PORT0_OMR_PS5_Pos 5 /*!< PORT0 OMR: PS5 Position */\r
+#define PORT0_OMR_PS5_Msk (0x01UL << PORT0_OMR_PS5_Pos) /*!< PORT0 OMR: PS5 Mask */\r
+#define PORT0_OMR_PS6_Pos 6 /*!< PORT0 OMR: PS6 Position */\r
+#define PORT0_OMR_PS6_Msk (0x01UL << PORT0_OMR_PS6_Pos) /*!< PORT0 OMR: PS6 Mask */\r
+#define PORT0_OMR_PS7_Pos 7 /*!< PORT0 OMR: PS7 Position */\r
+#define PORT0_OMR_PS7_Msk (0x01UL << PORT0_OMR_PS7_Pos) /*!< PORT0 OMR: PS7 Mask */\r
+#define PORT0_OMR_PS8_Pos 8 /*!< PORT0 OMR: PS8 Position */\r
+#define PORT0_OMR_PS8_Msk (0x01UL << PORT0_OMR_PS8_Pos) /*!< PORT0 OMR: PS8 Mask */\r
+#define PORT0_OMR_PS9_Pos 9 /*!< PORT0 OMR: PS9 Position */\r
+#define PORT0_OMR_PS9_Msk (0x01UL << PORT0_OMR_PS9_Pos) /*!< PORT0 OMR: PS9 Mask */\r
+#define PORT0_OMR_PS10_Pos 10 /*!< PORT0 OMR: PS10 Position */\r
+#define PORT0_OMR_PS10_Msk (0x01UL << PORT0_OMR_PS10_Pos) /*!< PORT0 OMR: PS10 Mask */\r
+#define PORT0_OMR_PS11_Pos 11 /*!< PORT0 OMR: PS11 Position */\r
+#define PORT0_OMR_PS11_Msk (0x01UL << PORT0_OMR_PS11_Pos) /*!< PORT0 OMR: PS11 Mask */\r
+#define PORT0_OMR_PS12_Pos 12 /*!< PORT0 OMR: PS12 Position */\r
+#define PORT0_OMR_PS12_Msk (0x01UL << PORT0_OMR_PS12_Pos) /*!< PORT0 OMR: PS12 Mask */\r
+#define PORT0_OMR_PS13_Pos 13 /*!< PORT0 OMR: PS13 Position */\r
+#define PORT0_OMR_PS13_Msk (0x01UL << PORT0_OMR_PS13_Pos) /*!< PORT0 OMR: PS13 Mask */\r
+#define PORT0_OMR_PS14_Pos 14 /*!< PORT0 OMR: PS14 Position */\r
+#define PORT0_OMR_PS14_Msk (0x01UL << PORT0_OMR_PS14_Pos) /*!< PORT0 OMR: PS14 Mask */\r
+#define PORT0_OMR_PS15_Pos 15 /*!< PORT0 OMR: PS15 Position */\r
+#define PORT0_OMR_PS15_Msk (0x01UL << PORT0_OMR_PS15_Pos) /*!< PORT0 OMR: PS15 Mask */\r
+#define PORT0_OMR_PR0_Pos 16 /*!< PORT0 OMR: PR0 Position */\r
+#define PORT0_OMR_PR0_Msk (0x01UL << PORT0_OMR_PR0_Pos) /*!< PORT0 OMR: PR0 Mask */\r
+#define PORT0_OMR_PR1_Pos 17 /*!< PORT0 OMR: PR1 Position */\r
+#define PORT0_OMR_PR1_Msk (0x01UL << PORT0_OMR_PR1_Pos) /*!< PORT0 OMR: PR1 Mask */\r
+#define PORT0_OMR_PR2_Pos 18 /*!< PORT0 OMR: PR2 Position */\r
+#define PORT0_OMR_PR2_Msk (0x01UL << PORT0_OMR_PR2_Pos) /*!< PORT0 OMR: PR2 Mask */\r
+#define PORT0_OMR_PR3_Pos 19 /*!< PORT0 OMR: PR3 Position */\r
+#define PORT0_OMR_PR3_Msk (0x01UL << PORT0_OMR_PR3_Pos) /*!< PORT0 OMR: PR3 Mask */\r
+#define PORT0_OMR_PR4_Pos 20 /*!< PORT0 OMR: PR4 Position */\r
+#define PORT0_OMR_PR4_Msk (0x01UL << PORT0_OMR_PR4_Pos) /*!< PORT0 OMR: PR4 Mask */\r
+#define PORT0_OMR_PR5_Pos 21 /*!< PORT0 OMR: PR5 Position */\r
+#define PORT0_OMR_PR5_Msk (0x01UL << PORT0_OMR_PR5_Pos) /*!< PORT0 OMR: PR5 Mask */\r
+#define PORT0_OMR_PR6_Pos 22 /*!< PORT0 OMR: PR6 Position */\r
+#define PORT0_OMR_PR6_Msk (0x01UL << PORT0_OMR_PR6_Pos) /*!< PORT0 OMR: PR6 Mask */\r
+#define PORT0_OMR_PR7_Pos 23 /*!< PORT0 OMR: PR7 Position */\r
+#define PORT0_OMR_PR7_Msk (0x01UL << PORT0_OMR_PR7_Pos) /*!< PORT0 OMR: PR7 Mask */\r
+#define PORT0_OMR_PR8_Pos 24 /*!< PORT0 OMR: PR8 Position */\r
+#define PORT0_OMR_PR8_Msk (0x01UL << PORT0_OMR_PR8_Pos) /*!< PORT0 OMR: PR8 Mask */\r
+#define PORT0_OMR_PR9_Pos 25 /*!< PORT0 OMR: PR9 Position */\r
+#define PORT0_OMR_PR9_Msk (0x01UL << PORT0_OMR_PR9_Pos) /*!< PORT0 OMR: PR9 Mask */\r
+#define PORT0_OMR_PR10_Pos 26 /*!< PORT0 OMR: PR10 Position */\r
+#define PORT0_OMR_PR10_Msk (0x01UL << PORT0_OMR_PR10_Pos) /*!< PORT0 OMR: PR10 Mask */\r
+#define PORT0_OMR_PR11_Pos 27 /*!< PORT0 OMR: PR11 Position */\r
+#define PORT0_OMR_PR11_Msk (0x01UL << PORT0_OMR_PR11_Pos) /*!< PORT0 OMR: PR11 Mask */\r
+#define PORT0_OMR_PR12_Pos 28 /*!< PORT0 OMR: PR12 Position */\r
+#define PORT0_OMR_PR12_Msk (0x01UL << PORT0_OMR_PR12_Pos) /*!< PORT0 OMR: PR12 Mask */\r
+#define PORT0_OMR_PR13_Pos 29 /*!< PORT0 OMR: PR13 Position */\r
+#define PORT0_OMR_PR13_Msk (0x01UL << PORT0_OMR_PR13_Pos) /*!< PORT0 OMR: PR13 Mask */\r
+#define PORT0_OMR_PR14_Pos 30 /*!< PORT0 OMR: PR14 Position */\r
+#define PORT0_OMR_PR14_Msk (0x01UL << PORT0_OMR_PR14_Pos) /*!< PORT0 OMR: PR14 Mask */\r
+#define PORT0_OMR_PR15_Pos 31 /*!< PORT0 OMR: PR15 Position */\r
+#define PORT0_OMR_PR15_Msk (0x01UL << PORT0_OMR_PR15_Pos) /*!< PORT0 OMR: PR15 Mask */\r
+\r
+/* --------------------------------- PORT0_IOCR0 -------------------------------- */\r
+#define PORT0_IOCR0_PC0_Pos 3 /*!< PORT0 IOCR0: PC0 Position */\r
+#define PORT0_IOCR0_PC0_Msk (0x1fUL << PORT0_IOCR0_PC0_Pos) /*!< PORT0 IOCR0: PC0 Mask */\r
+#define PORT0_IOCR0_PC1_Pos 11 /*!< PORT0 IOCR0: PC1 Position */\r
+#define PORT0_IOCR0_PC1_Msk (0x1fUL << PORT0_IOCR0_PC1_Pos) /*!< PORT0 IOCR0: PC1 Mask */\r
+#define PORT0_IOCR0_PC2_Pos 19 /*!< PORT0 IOCR0: PC2 Position */\r
+#define PORT0_IOCR0_PC2_Msk (0x1fUL << PORT0_IOCR0_PC2_Pos) /*!< PORT0 IOCR0: PC2 Mask */\r
+#define PORT0_IOCR0_PC3_Pos 27 /*!< PORT0 IOCR0: PC3 Position */\r
+#define PORT0_IOCR0_PC3_Msk (0x1fUL << PORT0_IOCR0_PC3_Pos) /*!< PORT0 IOCR0: PC3 Mask */\r
+\r
+/* --------------------------------- PORT0_IOCR4 -------------------------------- */\r
+#define PORT0_IOCR4_PC4_Pos 3 /*!< PORT0 IOCR4: PC4 Position */\r
+#define PORT0_IOCR4_PC4_Msk (0x1fUL << PORT0_IOCR4_PC4_Pos) /*!< PORT0 IOCR4: PC4 Mask */\r
+#define PORT0_IOCR4_PC5_Pos 11 /*!< PORT0 IOCR4: PC5 Position */\r
+#define PORT0_IOCR4_PC5_Msk (0x1fUL << PORT0_IOCR4_PC5_Pos) /*!< PORT0 IOCR4: PC5 Mask */\r
+#define PORT0_IOCR4_PC6_Pos 19 /*!< PORT0 IOCR4: PC6 Position */\r
+#define PORT0_IOCR4_PC6_Msk (0x1fUL << PORT0_IOCR4_PC6_Pos) /*!< PORT0 IOCR4: PC6 Mask */\r
+#define PORT0_IOCR4_PC7_Pos 27 /*!< PORT0 IOCR4: PC7 Position */\r
+#define PORT0_IOCR4_PC7_Msk (0x1fUL << PORT0_IOCR4_PC7_Pos) /*!< PORT0 IOCR4: PC7 Mask */\r
+\r
+/* --------------------------------- PORT0_IOCR8 -------------------------------- */\r
+#define PORT0_IOCR8_PC8_Pos 3 /*!< PORT0 IOCR8: PC8 Position */\r
+#define PORT0_IOCR8_PC8_Msk (0x1fUL << PORT0_IOCR8_PC8_Pos) /*!< PORT0 IOCR8: PC8 Mask */\r
+#define PORT0_IOCR8_PC9_Pos 11 /*!< PORT0 IOCR8: PC9 Position */\r
+#define PORT0_IOCR8_PC9_Msk (0x1fUL << PORT0_IOCR8_PC9_Pos) /*!< PORT0 IOCR8: PC9 Mask */\r
+#define PORT0_IOCR8_PC10_Pos 19 /*!< PORT0 IOCR8: PC10 Position */\r
+#define PORT0_IOCR8_PC10_Msk (0x1fUL << PORT0_IOCR8_PC10_Pos) /*!< PORT0 IOCR8: PC10 Mask */\r
+#define PORT0_IOCR8_PC11_Pos 27 /*!< PORT0 IOCR8: PC11 Position */\r
+#define PORT0_IOCR8_PC11_Msk (0x1fUL << PORT0_IOCR8_PC11_Pos) /*!< PORT0 IOCR8: PC11 Mask */\r
+\r
+/* -------------------------------- PORT0_IOCR12 -------------------------------- */\r
+#define PORT0_IOCR12_PC12_Pos 3 /*!< PORT0 IOCR12: PC12 Position */\r
+#define PORT0_IOCR12_PC12_Msk (0x1fUL << PORT0_IOCR12_PC12_Pos) /*!< PORT0 IOCR12: PC12 Mask */\r
+#define PORT0_IOCR12_PC13_Pos 11 /*!< PORT0 IOCR12: PC13 Position */\r
+#define PORT0_IOCR12_PC13_Msk (0x1fUL << PORT0_IOCR12_PC13_Pos) /*!< PORT0 IOCR12: PC13 Mask */\r
+#define PORT0_IOCR12_PC14_Pos 19 /*!< PORT0 IOCR12: PC14 Position */\r
+#define PORT0_IOCR12_PC14_Msk (0x1fUL << PORT0_IOCR12_PC14_Pos) /*!< PORT0 IOCR12: PC14 Mask */\r
+#define PORT0_IOCR12_PC15_Pos 27 /*!< PORT0 IOCR12: PC15 Position */\r
+#define PORT0_IOCR12_PC15_Msk (0x1fUL << PORT0_IOCR12_PC15_Pos) /*!< PORT0 IOCR12: PC15 Mask */\r
+\r
+/* ---------------------------------- PORT0_IN ---------------------------------- */\r
+#define PORT0_IN_P0_Pos 0 /*!< PORT0 IN: P0 Position */\r
+#define PORT0_IN_P0_Msk (0x01UL << PORT0_IN_P0_Pos) /*!< PORT0 IN: P0 Mask */\r
+#define PORT0_IN_P1_Pos 1 /*!< PORT0 IN: P1 Position */\r
+#define PORT0_IN_P1_Msk (0x01UL << PORT0_IN_P1_Pos) /*!< PORT0 IN: P1 Mask */\r
+#define PORT0_IN_P2_Pos 2 /*!< PORT0 IN: P2 Position */\r
+#define PORT0_IN_P2_Msk (0x01UL << PORT0_IN_P2_Pos) /*!< PORT0 IN: P2 Mask */\r
+#define PORT0_IN_P3_Pos 3 /*!< PORT0 IN: P3 Position */\r
+#define PORT0_IN_P3_Msk (0x01UL << PORT0_IN_P3_Pos) /*!< PORT0 IN: P3 Mask */\r
+#define PORT0_IN_P4_Pos 4 /*!< PORT0 IN: P4 Position */\r
+#define PORT0_IN_P4_Msk (0x01UL << PORT0_IN_P4_Pos) /*!< PORT0 IN: P4 Mask */\r
+#define PORT0_IN_P5_Pos 5 /*!< PORT0 IN: P5 Position */\r
+#define PORT0_IN_P5_Msk (0x01UL << PORT0_IN_P5_Pos) /*!< PORT0 IN: P5 Mask */\r
+#define PORT0_IN_P6_Pos 6 /*!< PORT0 IN: P6 Position */\r
+#define PORT0_IN_P6_Msk (0x01UL << PORT0_IN_P6_Pos) /*!< PORT0 IN: P6 Mask */\r
+#define PORT0_IN_P7_Pos 7 /*!< PORT0 IN: P7 Position */\r
+#define PORT0_IN_P7_Msk (0x01UL << PORT0_IN_P7_Pos) /*!< PORT0 IN: P7 Mask */\r
+#define PORT0_IN_P8_Pos 8 /*!< PORT0 IN: P8 Position */\r
+#define PORT0_IN_P8_Msk (0x01UL << PORT0_IN_P8_Pos) /*!< PORT0 IN: P8 Mask */\r
+#define PORT0_IN_P9_Pos 9 /*!< PORT0 IN: P9 Position */\r
+#define PORT0_IN_P9_Msk (0x01UL << PORT0_IN_P9_Pos) /*!< PORT0 IN: P9 Mask */\r
+#define PORT0_IN_P10_Pos 10 /*!< PORT0 IN: P10 Position */\r
+#define PORT0_IN_P10_Msk (0x01UL << PORT0_IN_P10_Pos) /*!< PORT0 IN: P10 Mask */\r
+#define PORT0_IN_P11_Pos 11 /*!< PORT0 IN: P11 Position */\r
+#define PORT0_IN_P11_Msk (0x01UL << PORT0_IN_P11_Pos) /*!< PORT0 IN: P11 Mask */\r
+#define PORT0_IN_P12_Pos 12 /*!< PORT0 IN: P12 Position */\r
+#define PORT0_IN_P12_Msk (0x01UL << PORT0_IN_P12_Pos) /*!< PORT0 IN: P12 Mask */\r
+#define PORT0_IN_P13_Pos 13 /*!< PORT0 IN: P13 Position */\r
+#define PORT0_IN_P13_Msk (0x01UL << PORT0_IN_P13_Pos) /*!< PORT0 IN: P13 Mask */\r
+#define PORT0_IN_P14_Pos 14 /*!< PORT0 IN: P14 Position */\r
+#define PORT0_IN_P14_Msk (0x01UL << PORT0_IN_P14_Pos) /*!< PORT0 IN: P14 Mask */\r
+#define PORT0_IN_P15_Pos 15 /*!< PORT0 IN: P15 Position */\r
+#define PORT0_IN_P15_Msk (0x01UL << PORT0_IN_P15_Pos) /*!< PORT0 IN: P15 Mask */\r
+\r
+/* --------------------------------- PORT0_PHCR0 -------------------------------- */\r
+#define PORT0_PHCR0_PH0_Pos 2 /*!< PORT0 PHCR0: PH0 Position */\r
+#define PORT0_PHCR0_PH0_Msk (0x01UL << PORT0_PHCR0_PH0_Pos) /*!< PORT0 PHCR0: PH0 Mask */\r
+#define PORT0_PHCR0_PH1_Pos 6 /*!< PORT0 PHCR0: PH1 Position */\r
+#define PORT0_PHCR0_PH1_Msk (0x01UL << PORT0_PHCR0_PH1_Pos) /*!< PORT0 PHCR0: PH1 Mask */\r
+#define PORT0_PHCR0_PH2_Pos 10 /*!< PORT0 PHCR0: PH2 Position */\r
+#define PORT0_PHCR0_PH2_Msk (0x01UL << PORT0_PHCR0_PH2_Pos) /*!< PORT0 PHCR0: PH2 Mask */\r
+#define PORT0_PHCR0_PH3_Pos 14 /*!< PORT0 PHCR0: PH3 Position */\r
+#define PORT0_PHCR0_PH3_Msk (0x01UL << PORT0_PHCR0_PH3_Pos) /*!< PORT0 PHCR0: PH3 Mask */\r
+#define PORT0_PHCR0_PH4_Pos 18 /*!< PORT0 PHCR0: PH4 Position */\r
+#define PORT0_PHCR0_PH4_Msk (0x01UL << PORT0_PHCR0_PH4_Pos) /*!< PORT0 PHCR0: PH4 Mask */\r
+#define PORT0_PHCR0_PH5_Pos 22 /*!< PORT0 PHCR0: PH5 Position */\r
+#define PORT0_PHCR0_PH5_Msk (0x01UL << PORT0_PHCR0_PH5_Pos) /*!< PORT0 PHCR0: PH5 Mask */\r
+#define PORT0_PHCR0_PH6_Pos 26 /*!< PORT0 PHCR0: PH6 Position */\r
+#define PORT0_PHCR0_PH6_Msk (0x01UL << PORT0_PHCR0_PH6_Pos) /*!< PORT0 PHCR0: PH6 Mask */\r
+#define PORT0_PHCR0_PH7_Pos 30 /*!< PORT0 PHCR0: PH7 Position */\r
+#define PORT0_PHCR0_PH7_Msk (0x01UL << PORT0_PHCR0_PH7_Pos) /*!< PORT0 PHCR0: PH7 Mask */\r
+\r
+/* --------------------------------- PORT0_PHCR1 -------------------------------- */\r
+#define PORT0_PHCR1_PH8_Pos 2 /*!< PORT0 PHCR1: PH8 Position */\r
+#define PORT0_PHCR1_PH8_Msk (0x01UL << PORT0_PHCR1_PH8_Pos) /*!< PORT0 PHCR1: PH8 Mask */\r
+#define PORT0_PHCR1_PH9_Pos 6 /*!< PORT0 PHCR1: PH9 Position */\r
+#define PORT0_PHCR1_PH9_Msk (0x01UL << PORT0_PHCR1_PH9_Pos) /*!< PORT0 PHCR1: PH9 Mask */\r
+#define PORT0_PHCR1_PH10_Pos 10 /*!< PORT0 PHCR1: PH10 Position */\r
+#define PORT0_PHCR1_PH10_Msk (0x01UL << PORT0_PHCR1_PH10_Pos) /*!< PORT0 PHCR1: PH10 Mask */\r
+#define PORT0_PHCR1_PH11_Pos 14 /*!< PORT0 PHCR1: PH11 Position */\r
+#define PORT0_PHCR1_PH11_Msk (0x01UL << PORT0_PHCR1_PH11_Pos) /*!< PORT0 PHCR1: PH11 Mask */\r
+#define PORT0_PHCR1_PH12_Pos 18 /*!< PORT0 PHCR1: PH12 Position */\r
+#define PORT0_PHCR1_PH12_Msk (0x01UL << PORT0_PHCR1_PH12_Pos) /*!< PORT0 PHCR1: PH12 Mask */\r
+#define PORT0_PHCR1_PH13_Pos 22 /*!< PORT0 PHCR1: PH13 Position */\r
+#define PORT0_PHCR1_PH13_Msk (0x01UL << PORT0_PHCR1_PH13_Pos) /*!< PORT0 PHCR1: PH13 Mask */\r
+#define PORT0_PHCR1_PH14_Pos 26 /*!< PORT0 PHCR1: PH14 Position */\r
+#define PORT0_PHCR1_PH14_Msk (0x01UL << PORT0_PHCR1_PH14_Pos) /*!< PORT0 PHCR1: PH14 Mask */\r
+#define PORT0_PHCR1_PH15_Pos 30 /*!< PORT0 PHCR1: PH15 Position */\r
+#define PORT0_PHCR1_PH15_Msk (0x01UL << PORT0_PHCR1_PH15_Pos) /*!< PORT0 PHCR1: PH15 Mask */\r
+\r
+/* --------------------------------- PORT0_PDISC -------------------------------- */\r
+#define PORT0_PDISC_PDIS0_Pos 0 /*!< PORT0 PDISC: PDIS0 Position */\r
+#define PORT0_PDISC_PDIS0_Msk (0x01UL << PORT0_PDISC_PDIS0_Pos) /*!< PORT0 PDISC: PDIS0 Mask */\r
+#define PORT0_PDISC_PDIS1_Pos 1 /*!< PORT0 PDISC: PDIS1 Position */\r
+#define PORT0_PDISC_PDIS1_Msk (0x01UL << PORT0_PDISC_PDIS1_Pos) /*!< PORT0 PDISC: PDIS1 Mask */\r
+#define PORT0_PDISC_PDIS2_Pos 2 /*!< PORT0 PDISC: PDIS2 Position */\r
+#define PORT0_PDISC_PDIS2_Msk (0x01UL << PORT0_PDISC_PDIS2_Pos) /*!< PORT0 PDISC: PDIS2 Mask */\r
+#define PORT0_PDISC_PDIS3_Pos 3 /*!< PORT0 PDISC: PDIS3 Position */\r
+#define PORT0_PDISC_PDIS3_Msk (0x01UL << PORT0_PDISC_PDIS3_Pos) /*!< PORT0 PDISC: PDIS3 Mask */\r
+#define PORT0_PDISC_PDIS4_Pos 4 /*!< PORT0 PDISC: PDIS4 Position */\r
+#define PORT0_PDISC_PDIS4_Msk (0x01UL << PORT0_PDISC_PDIS4_Pos) /*!< PORT0 PDISC: PDIS4 Mask */\r
+#define PORT0_PDISC_PDIS5_Pos 5 /*!< PORT0 PDISC: PDIS5 Position */\r
+#define PORT0_PDISC_PDIS5_Msk (0x01UL << PORT0_PDISC_PDIS5_Pos) /*!< PORT0 PDISC: PDIS5 Mask */\r
+#define PORT0_PDISC_PDIS6_Pos 6 /*!< PORT0 PDISC: PDIS6 Position */\r
+#define PORT0_PDISC_PDIS6_Msk (0x01UL << PORT0_PDISC_PDIS6_Pos) /*!< PORT0 PDISC: PDIS6 Mask */\r
+#define PORT0_PDISC_PDIS7_Pos 7 /*!< PORT0 PDISC: PDIS7 Position */\r
+#define PORT0_PDISC_PDIS7_Msk (0x01UL << PORT0_PDISC_PDIS7_Pos) /*!< PORT0 PDISC: PDIS7 Mask */\r
+#define PORT0_PDISC_PDIS8_Pos 8 /*!< PORT0 PDISC: PDIS8 Position */\r
+#define PORT0_PDISC_PDIS8_Msk (0x01UL << PORT0_PDISC_PDIS8_Pos) /*!< PORT0 PDISC: PDIS8 Mask */\r
+#define PORT0_PDISC_PDIS9_Pos 9 /*!< PORT0 PDISC: PDIS9 Position */\r
+#define PORT0_PDISC_PDIS9_Msk (0x01UL << PORT0_PDISC_PDIS9_Pos) /*!< PORT0 PDISC: PDIS9 Mask */\r
+#define PORT0_PDISC_PDIS10_Pos 10 /*!< PORT0 PDISC: PDIS10 Position */\r
+#define PORT0_PDISC_PDIS10_Msk (0x01UL << PORT0_PDISC_PDIS10_Pos) /*!< PORT0 PDISC: PDIS10 Mask */\r
+#define PORT0_PDISC_PDIS11_Pos 11 /*!< PORT0 PDISC: PDIS11 Position */\r
+#define PORT0_PDISC_PDIS11_Msk (0x01UL << PORT0_PDISC_PDIS11_Pos) /*!< PORT0 PDISC: PDIS11 Mask */\r
+#define PORT0_PDISC_PDIS12_Pos 12 /*!< PORT0 PDISC: PDIS12 Position */\r
+#define PORT0_PDISC_PDIS12_Msk (0x01UL << PORT0_PDISC_PDIS12_Pos) /*!< PORT0 PDISC: PDIS12 Mask */\r
+#define PORT0_PDISC_PDIS13_Pos 13 /*!< PORT0 PDISC: PDIS13 Position */\r
+#define PORT0_PDISC_PDIS13_Msk (0x01UL << PORT0_PDISC_PDIS13_Pos) /*!< PORT0 PDISC: PDIS13 Mask */\r
+#define PORT0_PDISC_PDIS14_Pos 14 /*!< PORT0 PDISC: PDIS14 Position */\r
+#define PORT0_PDISC_PDIS14_Msk (0x01UL << PORT0_PDISC_PDIS14_Pos) /*!< PORT0 PDISC: PDIS14 Mask */\r
+#define PORT0_PDISC_PDIS15_Pos 15 /*!< PORT0 PDISC: PDIS15 Position */\r
+#define PORT0_PDISC_PDIS15_Msk (0x01UL << PORT0_PDISC_PDIS15_Pos) /*!< PORT0 PDISC: PDIS15 Mask */\r
+\r
+/* ---------------------------------- PORT0_PPS --------------------------------- */\r
+#define PORT0_PPS_PPS0_Pos 0 /*!< PORT0 PPS: PPS0 Position */\r
+#define PORT0_PPS_PPS0_Msk (0x01UL << PORT0_PPS_PPS0_Pos) /*!< PORT0 PPS: PPS0 Mask */\r
+#define PORT0_PPS_PPS1_Pos 1 /*!< PORT0 PPS: PPS1 Position */\r
+#define PORT0_PPS_PPS1_Msk (0x01UL << PORT0_PPS_PPS1_Pos) /*!< PORT0 PPS: PPS1 Mask */\r
+#define PORT0_PPS_PPS2_Pos 2 /*!< PORT0 PPS: PPS2 Position */\r
+#define PORT0_PPS_PPS2_Msk (0x01UL << PORT0_PPS_PPS2_Pos) /*!< PORT0 PPS: PPS2 Mask */\r
+#define PORT0_PPS_PPS3_Pos 3 /*!< PORT0 PPS: PPS3 Position */\r
+#define PORT0_PPS_PPS3_Msk (0x01UL << PORT0_PPS_PPS3_Pos) /*!< PORT0 PPS: PPS3 Mask */\r
+#define PORT0_PPS_PPS4_Pos 4 /*!< PORT0 PPS: PPS4 Position */\r
+#define PORT0_PPS_PPS4_Msk (0x01UL << PORT0_PPS_PPS4_Pos) /*!< PORT0 PPS: PPS4 Mask */\r
+#define PORT0_PPS_PPS5_Pos 5 /*!< PORT0 PPS: PPS5 Position */\r
+#define PORT0_PPS_PPS5_Msk (0x01UL << PORT0_PPS_PPS5_Pos) /*!< PORT0 PPS: PPS5 Mask */\r
+#define PORT0_PPS_PPS6_Pos 6 /*!< PORT0 PPS: PPS6 Position */\r
+#define PORT0_PPS_PPS6_Msk (0x01UL << PORT0_PPS_PPS6_Pos) /*!< PORT0 PPS: PPS6 Mask */\r
+#define PORT0_PPS_PPS7_Pos 7 /*!< PORT0 PPS: PPS7 Position */\r
+#define PORT0_PPS_PPS7_Msk (0x01UL << PORT0_PPS_PPS7_Pos) /*!< PORT0 PPS: PPS7 Mask */\r
+#define PORT0_PPS_PPS8_Pos 8 /*!< PORT0 PPS: PPS8 Position */\r
+#define PORT0_PPS_PPS8_Msk (0x01UL << PORT0_PPS_PPS8_Pos) /*!< PORT0 PPS: PPS8 Mask */\r
+#define PORT0_PPS_PPS9_Pos 9 /*!< PORT0 PPS: PPS9 Position */\r
+#define PORT0_PPS_PPS9_Msk (0x01UL << PORT0_PPS_PPS9_Pos) /*!< PORT0 PPS: PPS9 Mask */\r
+#define PORT0_PPS_PPS10_Pos 10 /*!< PORT0 PPS: PPS10 Position */\r
+#define PORT0_PPS_PPS10_Msk (0x01UL << PORT0_PPS_PPS10_Pos) /*!< PORT0 PPS: PPS10 Mask */\r
+#define PORT0_PPS_PPS11_Pos 11 /*!< PORT0 PPS: PPS11 Position */\r
+#define PORT0_PPS_PPS11_Msk (0x01UL << PORT0_PPS_PPS11_Pos) /*!< PORT0 PPS: PPS11 Mask */\r
+#define PORT0_PPS_PPS12_Pos 12 /*!< PORT0 PPS: PPS12 Position */\r
+#define PORT0_PPS_PPS12_Msk (0x01UL << PORT0_PPS_PPS12_Pos) /*!< PORT0 PPS: PPS12 Mask */\r
+#define PORT0_PPS_PPS13_Pos 13 /*!< PORT0 PPS: PPS13 Position */\r
+#define PORT0_PPS_PPS13_Msk (0x01UL << PORT0_PPS_PPS13_Pos) /*!< PORT0 PPS: PPS13 Mask */\r
+#define PORT0_PPS_PPS14_Pos 14 /*!< PORT0 PPS: PPS14 Position */\r
+#define PORT0_PPS_PPS14_Msk (0x01UL << PORT0_PPS_PPS14_Pos) /*!< PORT0 PPS: PPS14 Mask */\r
+#define PORT0_PPS_PPS15_Pos 15 /*!< PORT0 PPS: PPS15 Position */\r
+#define PORT0_PPS_PPS15_Msk (0x01UL << PORT0_PPS_PPS15_Pos) /*!< PORT0 PPS: PPS15 Mask */\r
+\r
+/* --------------------------------- PORT0_HWSEL -------------------------------- */\r
+#define PORT0_HWSEL_HW0_Pos 0 /*!< PORT0 HWSEL: HW0 Position */\r
+#define PORT0_HWSEL_HW0_Msk (0x03UL << PORT0_HWSEL_HW0_Pos) /*!< PORT0 HWSEL: HW0 Mask */\r
+#define PORT0_HWSEL_HW1_Pos 2 /*!< PORT0 HWSEL: HW1 Position */\r
+#define PORT0_HWSEL_HW1_Msk (0x03UL << PORT0_HWSEL_HW1_Pos) /*!< PORT0 HWSEL: HW1 Mask */\r
+#define PORT0_HWSEL_HW2_Pos 4 /*!< PORT0 HWSEL: HW2 Position */\r
+#define PORT0_HWSEL_HW2_Msk (0x03UL << PORT0_HWSEL_HW2_Pos) /*!< PORT0 HWSEL: HW2 Mask */\r
+#define PORT0_HWSEL_HW3_Pos 6 /*!< PORT0 HWSEL: HW3 Position */\r
+#define PORT0_HWSEL_HW3_Msk (0x03UL << PORT0_HWSEL_HW3_Pos) /*!< PORT0 HWSEL: HW3 Mask */\r
+#define PORT0_HWSEL_HW4_Pos 8 /*!< PORT0 HWSEL: HW4 Position */\r
+#define PORT0_HWSEL_HW4_Msk (0x03UL << PORT0_HWSEL_HW4_Pos) /*!< PORT0 HWSEL: HW4 Mask */\r
+#define PORT0_HWSEL_HW5_Pos 10 /*!< PORT0 HWSEL: HW5 Position */\r
+#define PORT0_HWSEL_HW5_Msk (0x03UL << PORT0_HWSEL_HW5_Pos) /*!< PORT0 HWSEL: HW5 Mask */\r
+#define PORT0_HWSEL_HW6_Pos 12 /*!< PORT0 HWSEL: HW6 Position */\r
+#define PORT0_HWSEL_HW6_Msk (0x03UL << PORT0_HWSEL_HW6_Pos) /*!< PORT0 HWSEL: HW6 Mask */\r
+#define PORT0_HWSEL_HW7_Pos 14 /*!< PORT0 HWSEL: HW7 Position */\r
+#define PORT0_HWSEL_HW7_Msk (0x03UL << PORT0_HWSEL_HW7_Pos) /*!< PORT0 HWSEL: HW7 Mask */\r
+#define PORT0_HWSEL_HW8_Pos 16 /*!< PORT0 HWSEL: HW8 Position */\r
+#define PORT0_HWSEL_HW8_Msk (0x03UL << PORT0_HWSEL_HW8_Pos) /*!< PORT0 HWSEL: HW8 Mask */\r
+#define PORT0_HWSEL_HW9_Pos 18 /*!< PORT0 HWSEL: HW9 Position */\r
+#define PORT0_HWSEL_HW9_Msk (0x03UL << PORT0_HWSEL_HW9_Pos) /*!< PORT0 HWSEL: HW9 Mask */\r
+#define PORT0_HWSEL_HW10_Pos 20 /*!< PORT0 HWSEL: HW10 Position */\r
+#define PORT0_HWSEL_HW10_Msk (0x03UL << PORT0_HWSEL_HW10_Pos) /*!< PORT0 HWSEL: HW10 Mask */\r
+#define PORT0_HWSEL_HW11_Pos 22 /*!< PORT0 HWSEL: HW11 Position */\r
+#define PORT0_HWSEL_HW11_Msk (0x03UL << PORT0_HWSEL_HW11_Pos) /*!< PORT0 HWSEL: HW11 Mask */\r
+#define PORT0_HWSEL_HW12_Pos 24 /*!< PORT0 HWSEL: HW12 Position */\r
+#define PORT0_HWSEL_HW12_Msk (0x03UL << PORT0_HWSEL_HW12_Pos) /*!< PORT0 HWSEL: HW12 Mask */\r
+#define PORT0_HWSEL_HW13_Pos 26 /*!< PORT0 HWSEL: HW13 Position */\r
+#define PORT0_HWSEL_HW13_Msk (0x03UL << PORT0_HWSEL_HW13_Pos) /*!< PORT0 HWSEL: HW13 Mask */\r
+#define PORT0_HWSEL_HW14_Pos 28 /*!< PORT0 HWSEL: HW14 Position */\r
+#define PORT0_HWSEL_HW14_Msk (0x03UL << PORT0_HWSEL_HW14_Pos) /*!< PORT0 HWSEL: HW14 Mask */\r
+#define PORT0_HWSEL_HW15_Pos 30 /*!< PORT0 HWSEL: HW15 Position */\r
+#define PORT0_HWSEL_HW15_Msk (0x03UL << PORT0_HWSEL_HW15_Pos) /*!< PORT0 HWSEL: HW15 Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PORT1' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- PORT1_OUT --------------------------------- */\r
+#define PORT1_OUT_P0_Pos 0 /*!< PORT1 OUT: P0 Position */\r
+#define PORT1_OUT_P0_Msk (0x01UL << PORT1_OUT_P0_Pos) /*!< PORT1 OUT: P0 Mask */\r
+#define PORT1_OUT_P1_Pos 1 /*!< PORT1 OUT: P1 Position */\r
+#define PORT1_OUT_P1_Msk (0x01UL << PORT1_OUT_P1_Pos) /*!< PORT1 OUT: P1 Mask */\r
+#define PORT1_OUT_P2_Pos 2 /*!< PORT1 OUT: P2 Position */\r
+#define PORT1_OUT_P2_Msk (0x01UL << PORT1_OUT_P2_Pos) /*!< PORT1 OUT: P2 Mask */\r
+#define PORT1_OUT_P3_Pos 3 /*!< PORT1 OUT: P3 Position */\r
+#define PORT1_OUT_P3_Msk (0x01UL << PORT1_OUT_P3_Pos) /*!< PORT1 OUT: P3 Mask */\r
+#define PORT1_OUT_P4_Pos 4 /*!< PORT1 OUT: P4 Position */\r
+#define PORT1_OUT_P4_Msk (0x01UL << PORT1_OUT_P4_Pos) /*!< PORT1 OUT: P4 Mask */\r
+#define PORT1_OUT_P5_Pos 5 /*!< PORT1 OUT: P5 Position */\r
+#define PORT1_OUT_P5_Msk (0x01UL << PORT1_OUT_P5_Pos) /*!< PORT1 OUT: P5 Mask */\r
+\r
+/* ---------------------------------- PORT1_OMR --------------------------------- */\r
+#define PORT1_OMR_PS0_Pos 0 /*!< PORT1 OMR: PS0 Position */\r
+#define PORT1_OMR_PS0_Msk (0x01UL << PORT1_OMR_PS0_Pos) /*!< PORT1 OMR: PS0 Mask */\r
+#define PORT1_OMR_PS1_Pos 1 /*!< PORT1 OMR: PS1 Position */\r
+#define PORT1_OMR_PS1_Msk (0x01UL << PORT1_OMR_PS1_Pos) /*!< PORT1 OMR: PS1 Mask */\r
+#define PORT1_OMR_PS2_Pos 2 /*!< PORT1 OMR: PS2 Position */\r
+#define PORT1_OMR_PS2_Msk (0x01UL << PORT1_OMR_PS2_Pos) /*!< PORT1 OMR: PS2 Mask */\r
+#define PORT1_OMR_PS3_Pos 3 /*!< PORT1 OMR: PS3 Position */\r
+#define PORT1_OMR_PS3_Msk (0x01UL << PORT1_OMR_PS3_Pos) /*!< PORT1 OMR: PS3 Mask */\r
+#define PORT1_OMR_PS4_Pos 4 /*!< PORT1 OMR: PS4 Position */\r
+#define PORT1_OMR_PS4_Msk (0x01UL << PORT1_OMR_PS4_Pos) /*!< PORT1 OMR: PS4 Mask */\r
+#define PORT1_OMR_PS5_Pos 5 /*!< PORT1 OMR: PS5 Position */\r
+#define PORT1_OMR_PS5_Msk (0x01UL << PORT1_OMR_PS5_Pos) /*!< PORT1 OMR: PS5 Mask */\r
+#define PORT1_OMR_PR0_Pos 16 /*!< PORT1 OMR: PR0 Position */\r
+#define PORT1_OMR_PR0_Msk (0x01UL << PORT1_OMR_PR0_Pos) /*!< PORT1 OMR: PR0 Mask */\r
+#define PORT1_OMR_PR1_Pos 17 /*!< PORT1 OMR: PR1 Position */\r
+#define PORT1_OMR_PR1_Msk (0x01UL << PORT1_OMR_PR1_Pos) /*!< PORT1 OMR: PR1 Mask */\r
+#define PORT1_OMR_PR2_Pos 18 /*!< PORT1 OMR: PR2 Position */\r
+#define PORT1_OMR_PR2_Msk (0x01UL << PORT1_OMR_PR2_Pos) /*!< PORT1 OMR: PR2 Mask */\r
+#define PORT1_OMR_PR3_Pos 19 /*!< PORT1 OMR: PR3 Position */\r
+#define PORT1_OMR_PR3_Msk (0x01UL << PORT1_OMR_PR3_Pos) /*!< PORT1 OMR: PR3 Mask */\r
+#define PORT1_OMR_PR4_Pos 20 /*!< PORT1 OMR: PR4 Position */\r
+#define PORT1_OMR_PR4_Msk (0x01UL << PORT1_OMR_PR4_Pos) /*!< PORT1 OMR: PR4 Mask */\r
+#define PORT1_OMR_PR5_Pos 21 /*!< PORT1 OMR: PR5 Position */\r
+#define PORT1_OMR_PR5_Msk (0x01UL << PORT1_OMR_PR5_Pos) /*!< PORT1 OMR: PR5 Mask */\r
+\r
+/* --------------------------------- PORT1_IOCR0 -------------------------------- */\r
+#define PORT1_IOCR0_PC0_Pos 3 /*!< PORT1 IOCR0: PC0 Position */\r
+#define PORT1_IOCR0_PC0_Msk (0x1fUL << PORT1_IOCR0_PC0_Pos) /*!< PORT1 IOCR0: PC0 Mask */\r
+#define PORT1_IOCR0_PC1_Pos 11 /*!< PORT1 IOCR0: PC1 Position */\r
+#define PORT1_IOCR0_PC1_Msk (0x1fUL << PORT1_IOCR0_PC1_Pos) /*!< PORT1 IOCR0: PC1 Mask */\r
+#define PORT1_IOCR0_PC2_Pos 19 /*!< PORT1 IOCR0: PC2 Position */\r
+#define PORT1_IOCR0_PC2_Msk (0x1fUL << PORT1_IOCR0_PC2_Pos) /*!< PORT1 IOCR0: PC2 Mask */\r
+#define PORT1_IOCR0_PC3_Pos 27 /*!< PORT1 IOCR0: PC3 Position */\r
+#define PORT1_IOCR0_PC3_Msk (0x1fUL << PORT1_IOCR0_PC3_Pos) /*!< PORT1 IOCR0: PC3 Mask */\r
+\r
+/* --------------------------------- PORT1_IOCR4 -------------------------------- */\r
+#define PORT1_IOCR4_PC4_Pos 3 /*!< PORT1 IOCR4: PC4 Position */\r
+#define PORT1_IOCR4_PC4_Msk (0x1fUL << PORT1_IOCR4_PC4_Pos) /*!< PORT1 IOCR4: PC4 Mask */\r
+#define PORT1_IOCR4_PC5_Pos 11 /*!< PORT1 IOCR4: PC5 Position */\r
+#define PORT1_IOCR4_PC5_Msk (0x1fUL << PORT1_IOCR4_PC5_Pos) /*!< PORT1 IOCR4: PC5 Mask */\r
+\r
+/* ---------------------------------- PORT1_IN ---------------------------------- */\r
+#define PORT1_IN_P0_Pos 0 /*!< PORT1 IN: P0 Position */\r
+#define PORT1_IN_P0_Msk (0x01UL << PORT1_IN_P0_Pos) /*!< PORT1 IN: P0 Mask */\r
+#define PORT1_IN_P1_Pos 1 /*!< PORT1 IN: P1 Position */\r
+#define PORT1_IN_P1_Msk (0x01UL << PORT1_IN_P1_Pos) /*!< PORT1 IN: P1 Mask */\r
+#define PORT1_IN_P2_Pos 2 /*!< PORT1 IN: P2 Position */\r
+#define PORT1_IN_P2_Msk (0x01UL << PORT1_IN_P2_Pos) /*!< PORT1 IN: P2 Mask */\r
+#define PORT1_IN_P3_Pos 3 /*!< PORT1 IN: P3 Position */\r
+#define PORT1_IN_P3_Msk (0x01UL << PORT1_IN_P3_Pos) /*!< PORT1 IN: P3 Mask */\r
+#define PORT1_IN_P4_Pos 4 /*!< PORT1 IN: P4 Position */\r
+#define PORT1_IN_P4_Msk (0x01UL << PORT1_IN_P4_Pos) /*!< PORT1 IN: P4 Mask */\r
+#define PORT1_IN_P5_Pos 5 /*!< PORT1 IN: P5 Position */\r
+#define PORT1_IN_P5_Msk (0x01UL << PORT1_IN_P5_Pos) /*!< PORT1 IN: P5 Mask */\r
+\r
+/* --------------------------------- PORT1_PHCR0 -------------------------------- */\r
+#define PORT1_PHCR0_PH0_Pos 2 /*!< PORT1 PHCR0: PH0 Position */\r
+#define PORT1_PHCR0_PH0_Msk (0x01UL << PORT1_PHCR0_PH0_Pos) /*!< PORT1 PHCR0: PH0 Mask */\r
+#define PORT1_PHCR0_PH1_Pos 6 /*!< PORT1 PHCR0: PH1 Position */\r
+#define PORT1_PHCR0_PH1_Msk (0x01UL << PORT1_PHCR0_PH1_Pos) /*!< PORT1 PHCR0: PH1 Mask */\r
+#define PORT1_PHCR0_PH2_Pos 10 /*!< PORT1 PHCR0: PH2 Position */\r
+#define PORT1_PHCR0_PH2_Msk (0x01UL << PORT1_PHCR0_PH2_Pos) /*!< PORT1 PHCR0: PH2 Mask */\r
+#define PORT1_PHCR0_PH3_Pos 14 /*!< PORT1 PHCR0: PH3 Position */\r
+#define PORT1_PHCR0_PH3_Msk (0x01UL << PORT1_PHCR0_PH3_Pos) /*!< PORT1 PHCR0: PH3 Mask */\r
+#define PORT1_PHCR0_PH4_Pos 18 /*!< PORT1 PHCR0: PH4 Position */\r
+#define PORT1_PHCR0_PH4_Msk (0x01UL << PORT1_PHCR0_PH4_Pos) /*!< PORT1 PHCR0: PH4 Mask */\r
+#define PORT1_PHCR0_PH5_Pos 22 /*!< PORT1 PHCR0: PH5 Position */\r
+#define PORT1_PHCR0_PH5_Msk (0x01UL << PORT1_PHCR0_PH5_Pos) /*!< PORT1 PHCR0: PH5 Mask */\r
+\r
+/* --------------------------------- PORT1_PDISC -------------------------------- */\r
+#define PORT1_PDISC_PDIS0_Pos 0 /*!< PORT1 PDISC: PDIS0 Position */\r
+#define PORT1_PDISC_PDIS0_Msk (0x01UL << PORT1_PDISC_PDIS0_Pos) /*!< PORT1 PDISC: PDIS0 Mask */\r
+#define PORT1_PDISC_PDIS1_Pos 1 /*!< PORT1 PDISC: PDIS1 Position */\r
+#define PORT1_PDISC_PDIS1_Msk (0x01UL << PORT1_PDISC_PDIS1_Pos) /*!< PORT1 PDISC: PDIS1 Mask */\r
+#define PORT1_PDISC_PDIS2_Pos 2 /*!< PORT1 PDISC: PDIS2 Position */\r
+#define PORT1_PDISC_PDIS2_Msk (0x01UL << PORT1_PDISC_PDIS2_Pos) /*!< PORT1 PDISC: PDIS2 Mask */\r
+#define PORT1_PDISC_PDIS3_Pos 3 /*!< PORT1 PDISC: PDIS3 Position */\r
+#define PORT1_PDISC_PDIS3_Msk (0x01UL << PORT1_PDISC_PDIS3_Pos) /*!< PORT1 PDISC: PDIS3 Mask */\r
+#define PORT1_PDISC_PDIS4_Pos 4 /*!< PORT1 PDISC: PDIS4 Position */\r
+#define PORT1_PDISC_PDIS4_Msk (0x01UL << PORT1_PDISC_PDIS4_Pos) /*!< PORT1 PDISC: PDIS4 Mask */\r
+#define PORT1_PDISC_PDIS5_Pos 5 /*!< PORT1 PDISC: PDIS5 Position */\r
+#define PORT1_PDISC_PDIS5_Msk (0x01UL << PORT1_PDISC_PDIS5_Pos) /*!< PORT1 PDISC: PDIS5 Mask */\r
+\r
+/* ---------------------------------- PORT1_PPS --------------------------------- */\r
+#define PORT1_PPS_PPS0_Pos 0 /*!< PORT1 PPS: PPS0 Position */\r
+#define PORT1_PPS_PPS0_Msk (0x01UL << PORT1_PPS_PPS0_Pos) /*!< PORT1 PPS: PPS0 Mask */\r
+#define PORT1_PPS_PPS1_Pos 1 /*!< PORT1 PPS: PPS1 Position */\r
+#define PORT1_PPS_PPS1_Msk (0x01UL << PORT1_PPS_PPS1_Pos) /*!< PORT1 PPS: PPS1 Mask */\r
+#define PORT1_PPS_PPS2_Pos 2 /*!< PORT1 PPS: PPS2 Position */\r
+#define PORT1_PPS_PPS2_Msk (0x01UL << PORT1_PPS_PPS2_Pos) /*!< PORT1 PPS: PPS2 Mask */\r
+#define PORT1_PPS_PPS3_Pos 3 /*!< PORT1 PPS: PPS3 Position */\r
+#define PORT1_PPS_PPS3_Msk (0x01UL << PORT1_PPS_PPS3_Pos) /*!< PORT1 PPS: PPS3 Mask */\r
+#define PORT1_PPS_PPS4_Pos 4 /*!< PORT1 PPS: PPS4 Position */\r
+#define PORT1_PPS_PPS4_Msk (0x01UL << PORT1_PPS_PPS4_Pos) /*!< PORT1 PPS: PPS4 Mask */\r
+#define PORT1_PPS_PPS5_Pos 5 /*!< PORT1 PPS: PPS5 Position */\r
+#define PORT1_PPS_PPS5_Msk (0x01UL << PORT1_PPS_PPS5_Pos) /*!< PORT1 PPS: PPS5 Mask */\r
+\r
+/* --------------------------------- PORT1_HWSEL -------------------------------- */\r
+#define PORT1_HWSEL_HW0_Pos 0 /*!< PORT1 HWSEL: HW0 Position */\r
+#define PORT1_HWSEL_HW0_Msk (0x03UL << PORT1_HWSEL_HW0_Pos) /*!< PORT1 HWSEL: HW0 Mask */\r
+#define PORT1_HWSEL_HW1_Pos 2 /*!< PORT1 HWSEL: HW1 Position */\r
+#define PORT1_HWSEL_HW1_Msk (0x03UL << PORT1_HWSEL_HW1_Pos) /*!< PORT1 HWSEL: HW1 Mask */\r
+#define PORT1_HWSEL_HW2_Pos 4 /*!< PORT1 HWSEL: HW2 Position */\r
+#define PORT1_HWSEL_HW2_Msk (0x03UL << PORT1_HWSEL_HW2_Pos) /*!< PORT1 HWSEL: HW2 Mask */\r
+#define PORT1_HWSEL_HW3_Pos 6 /*!< PORT1 HWSEL: HW3 Position */\r
+#define PORT1_HWSEL_HW3_Msk (0x03UL << PORT1_HWSEL_HW3_Pos) /*!< PORT1 HWSEL: HW3 Mask */\r
+#define PORT1_HWSEL_HW4_Pos 8 /*!< PORT1 HWSEL: HW4 Position */\r
+#define PORT1_HWSEL_HW4_Msk (0x03UL << PORT1_HWSEL_HW4_Pos) /*!< PORT1 HWSEL: HW4 Mask */\r
+#define PORT1_HWSEL_HW5_Pos 10 /*!< PORT1 HWSEL: HW5 Position */\r
+#define PORT1_HWSEL_HW5_Msk (0x03UL << PORT1_HWSEL_HW5_Pos) /*!< PORT1 HWSEL: HW5 Mask */\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ struct 'PORT2' Position & Mask ================ */\r
+/* ================================================================================ */\r
+\r
+\r
+/* ---------------------------------- PORT2_OUT --------------------------------- */\r
+#define PORT2_OUT_P0_Pos 0 /*!< PORT2 OUT: P0 Position */\r
+#define PORT2_OUT_P0_Msk (0x01UL << PORT2_OUT_P0_Pos) /*!< PORT2 OUT: P0 Mask */\r
+#define PORT2_OUT_P1_Pos 1 /*!< PORT2 OUT: P1 Position */\r
+#define PORT2_OUT_P1_Msk (0x01UL << PORT2_OUT_P1_Pos) /*!< PORT2 OUT: P1 Mask */\r
+#define PORT2_OUT_P2_Pos 2 /*!< PORT2 OUT: P2 Position */\r
+#define PORT2_OUT_P2_Msk (0x01UL << PORT2_OUT_P2_Pos) /*!< PORT2 OUT: P2 Mask */\r
+#define PORT2_OUT_P3_Pos 3 /*!< PORT2 OUT: P3 Position */\r
+#define PORT2_OUT_P3_Msk (0x01UL << PORT2_OUT_P3_Pos) /*!< PORT2 OUT: P3 Mask */\r
+#define PORT2_OUT_P4_Pos 4 /*!< PORT2 OUT: P4 Position */\r
+#define PORT2_OUT_P4_Msk (0x01UL << PORT2_OUT_P4_Pos) /*!< PORT2 OUT: P4 Mask */\r
+#define PORT2_OUT_P5_Pos 5 /*!< PORT2 OUT: P5 Position */\r
+#define PORT2_OUT_P5_Msk (0x01UL << PORT2_OUT_P5_Pos) /*!< PORT2 OUT: P5 Mask */\r
+#define PORT2_OUT_P6_Pos 6 /*!< PORT2 OUT: P6 Position */\r
+#define PORT2_OUT_P6_Msk (0x01UL << PORT2_OUT_P6_Pos) /*!< PORT2 OUT: P6 Mask */\r
+#define PORT2_OUT_P7_Pos 7 /*!< PORT2 OUT: P7 Position */\r
+#define PORT2_OUT_P7_Msk (0x01UL << PORT2_OUT_P7_Pos) /*!< PORT2 OUT: P7 Mask */\r
+#define PORT2_OUT_P8_Pos 8 /*!< PORT2 OUT: P8 Position */\r
+#define PORT2_OUT_P8_Msk (0x01UL << PORT2_OUT_P8_Pos) /*!< PORT2 OUT: P8 Mask */\r
+#define PORT2_OUT_P9_Pos 9 /*!< PORT2 OUT: P9 Position */\r
+#define PORT2_OUT_P9_Msk (0x01UL << PORT2_OUT_P9_Pos) /*!< PORT2 OUT: P9 Mask */\r
+#define PORT2_OUT_P10_Pos 10 /*!< PORT2 OUT: P10 Position */\r
+#define PORT2_OUT_P10_Msk (0x01UL << PORT2_OUT_P10_Pos) /*!< PORT2 OUT: P10 Mask */\r
+#define PORT2_OUT_P11_Pos 11 /*!< PORT2 OUT: P11 Position */\r
+#define PORT2_OUT_P11_Msk (0x01UL << PORT2_OUT_P11_Pos) /*!< PORT2 OUT: P11 Mask */\r
+\r
+/* ---------------------------------- PORT2_OMR --------------------------------- */\r
+#define PORT2_OMR_PS0_Pos 0 /*!< PORT2 OMR: PS0 Position */\r
+#define PORT2_OMR_PS0_Msk (0x01UL << PORT2_OMR_PS0_Pos) /*!< PORT2 OMR: PS0 Mask */\r
+#define PORT2_OMR_PS1_Pos 1 /*!< PORT2 OMR: PS1 Position */\r
+#define PORT2_OMR_PS1_Msk (0x01UL << PORT2_OMR_PS1_Pos) /*!< PORT2 OMR: PS1 Mask */\r
+#define PORT2_OMR_PS2_Pos 2 /*!< PORT2 OMR: PS2 Position */\r
+#define PORT2_OMR_PS2_Msk (0x01UL << PORT2_OMR_PS2_Pos) /*!< PORT2 OMR: PS2 Mask */\r
+#define PORT2_OMR_PS3_Pos 3 /*!< PORT2 OMR: PS3 Position */\r
+#define PORT2_OMR_PS3_Msk (0x01UL << PORT2_OMR_PS3_Pos) /*!< PORT2 OMR: PS3 Mask */\r
+#define PORT2_OMR_PS4_Pos 4 /*!< PORT2 OMR: PS4 Position */\r
+#define PORT2_OMR_PS4_Msk (0x01UL << PORT2_OMR_PS4_Pos) /*!< PORT2 OMR: PS4 Mask */\r
+#define PORT2_OMR_PS5_Pos 5 /*!< PORT2 OMR: PS5 Position */\r
+#define PORT2_OMR_PS5_Msk (0x01UL << PORT2_OMR_PS5_Pos) /*!< PORT2 OMR: PS5 Mask */\r
+#define PORT2_OMR_PS6_Pos 6 /*!< PORT2 OMR: PS6 Position */\r
+#define PORT2_OMR_PS6_Msk (0x01UL << PORT2_OMR_PS6_Pos) /*!< PORT2 OMR: PS6 Mask */\r
+#define PORT2_OMR_PS7_Pos 7 /*!< PORT2 OMR: PS7 Position */\r
+#define PORT2_OMR_PS7_Msk (0x01UL << PORT2_OMR_PS7_Pos) /*!< PORT2 OMR: PS7 Mask */\r
+#define PORT2_OMR_PS8_Pos 8 /*!< PORT2 OMR: PS8 Position */\r
+#define PORT2_OMR_PS8_Msk (0x01UL << PORT2_OMR_PS8_Pos) /*!< PORT2 OMR: PS8 Mask */\r
+#define PORT2_OMR_PS9_Pos 9 /*!< PORT2 OMR: PS9 Position */\r
+#define PORT2_OMR_PS9_Msk (0x01UL << PORT2_OMR_PS9_Pos) /*!< PORT2 OMR: PS9 Mask */\r
+#define PORT2_OMR_PS10_Pos 10 /*!< PORT2 OMR: PS10 Position */\r
+#define PORT2_OMR_PS10_Msk (0x01UL << PORT2_OMR_PS10_Pos) /*!< PORT2 OMR: PS10 Mask */\r
+#define PORT2_OMR_PS11_Pos 11 /*!< PORT2 OMR: PS11 Position */\r
+#define PORT2_OMR_PS11_Msk (0x01UL << PORT2_OMR_PS11_Pos) /*!< PORT2 OMR: PS11 Mask */\r
+#define PORT2_OMR_PR0_Pos 16 /*!< PORT2 OMR: PR0 Position */\r
+#define PORT2_OMR_PR0_Msk (0x01UL << PORT2_OMR_PR0_Pos) /*!< PORT2 OMR: PR0 Mask */\r
+#define PORT2_OMR_PR1_Pos 17 /*!< PORT2 OMR: PR1 Position */\r
+#define PORT2_OMR_PR1_Msk (0x01UL << PORT2_OMR_PR1_Pos) /*!< PORT2 OMR: PR1 Mask */\r
+#define PORT2_OMR_PR2_Pos 18 /*!< PORT2 OMR: PR2 Position */\r
+#define PORT2_OMR_PR2_Msk (0x01UL << PORT2_OMR_PR2_Pos) /*!< PORT2 OMR: PR2 Mask */\r
+#define PORT2_OMR_PR3_Pos 19 /*!< PORT2 OMR: PR3 Position */\r
+#define PORT2_OMR_PR3_Msk (0x01UL << PORT2_OMR_PR3_Pos) /*!< PORT2 OMR: PR3 Mask */\r
+#define PORT2_OMR_PR4_Pos 20 /*!< PORT2 OMR: PR4 Position */\r
+#define PORT2_OMR_PR4_Msk (0x01UL << PORT2_OMR_PR4_Pos) /*!< PORT2 OMR: PR4 Mask */\r
+#define PORT2_OMR_PR5_Pos 21 /*!< PORT2 OMR: PR5 Position */\r
+#define PORT2_OMR_PR5_Msk (0x01UL << PORT2_OMR_PR5_Pos) /*!< PORT2 OMR: PR5 Mask */\r
+#define PORT2_OMR_PR6_Pos 22 /*!< PORT2 OMR: PR6 Position */\r
+#define PORT2_OMR_PR6_Msk (0x01UL << PORT2_OMR_PR6_Pos) /*!< PORT2 OMR: PR6 Mask */\r
+#define PORT2_OMR_PR7_Pos 23 /*!< PORT2 OMR: PR7 Position */\r
+#define PORT2_OMR_PR7_Msk (0x01UL << PORT2_OMR_PR7_Pos) /*!< PORT2 OMR: PR7 Mask */\r
+#define PORT2_OMR_PR8_Pos 24 /*!< PORT2 OMR: PR8 Position */\r
+#define PORT2_OMR_PR8_Msk (0x01UL << PORT2_OMR_PR8_Pos) /*!< PORT2 OMR: PR8 Mask */\r
+#define PORT2_OMR_PR9_Pos 25 /*!< PORT2 OMR: PR9 Position */\r
+#define PORT2_OMR_PR9_Msk (0x01UL << PORT2_OMR_PR9_Pos) /*!< PORT2 OMR: PR9 Mask */\r
+#define PORT2_OMR_PR10_Pos 26 /*!< PORT2 OMR: PR10 Position */\r
+#define PORT2_OMR_PR10_Msk (0x01UL << PORT2_OMR_PR10_Pos) /*!< PORT2 OMR: PR10 Mask */\r
+#define PORT2_OMR_PR11_Pos 27 /*!< PORT2 OMR: PR11 Position */\r
+#define PORT2_OMR_PR11_Msk (0x01UL << PORT2_OMR_PR11_Pos) /*!< PORT2 OMR: PR11 Mask */\r
+\r
+/* --------------------------------- PORT2_IOCR0 -------------------------------- */\r
+#define PORT2_IOCR0_PC0_Pos 3 /*!< PORT2 IOCR0: PC0 Position */\r
+#define PORT2_IOCR0_PC0_Msk (0x1fUL << PORT2_IOCR0_PC0_Pos) /*!< PORT2 IOCR0: PC0 Mask */\r
+#define PORT2_IOCR0_PC1_Pos 11 /*!< PORT2 IOCR0: PC1 Position */\r
+#define PORT2_IOCR0_PC1_Msk (0x1fUL << PORT2_IOCR0_PC1_Pos) /*!< PORT2 IOCR0: PC1 Mask */\r
+#define PORT2_IOCR0_PC2_Pos 19 /*!< PORT2 IOCR0: PC2 Position */\r
+#define PORT2_IOCR0_PC2_Msk (0x1fUL << PORT2_IOCR0_PC2_Pos) /*!< PORT2 IOCR0: PC2 Mask */\r
+#define PORT2_IOCR0_PC3_Pos 27 /*!< PORT2 IOCR0: PC3 Position */\r
+#define PORT2_IOCR0_PC3_Msk (0x1fUL << PORT2_IOCR0_PC3_Pos) /*!< PORT2 IOCR0: PC3 Mask */\r
+\r
+/* --------------------------------- PORT2_IOCR4 -------------------------------- */\r
+#define PORT2_IOCR4_PC4_Pos 3 /*!< PORT2 IOCR4: PC4 Position */\r
+#define PORT2_IOCR4_PC4_Msk (0x1fUL << PORT2_IOCR4_PC4_Pos) /*!< PORT2 IOCR4: PC4 Mask */\r
+#define PORT2_IOCR4_PC5_Pos 11 /*!< PORT2 IOCR4: PC5 Position */\r
+#define PORT2_IOCR4_PC5_Msk (0x1fUL << PORT2_IOCR4_PC5_Pos) /*!< PORT2 IOCR4: PC5 Mask */\r
+#define PORT2_IOCR4_PC6_Pos 19 /*!< PORT2 IOCR4: PC6 Position */\r
+#define PORT2_IOCR4_PC6_Msk (0x1fUL << PORT2_IOCR4_PC6_Pos) /*!< PORT2 IOCR4: PC6 Mask */\r
+#define PORT2_IOCR4_PC7_Pos 27 /*!< PORT2 IOCR4: PC7 Position */\r
+#define PORT2_IOCR4_PC7_Msk (0x1fUL << PORT2_IOCR4_PC7_Pos) /*!< PORT2 IOCR4: PC7 Mask */\r
+\r
+/* --------------------------------- PORT2_IOCR8 -------------------------------- */\r
+#define PORT2_IOCR8_PC8_Pos 3 /*!< PORT2 IOCR8: PC8 Position */\r
+#define PORT2_IOCR8_PC8_Msk (0x1fUL << PORT2_IOCR8_PC8_Pos) /*!< PORT2 IOCR8: PC8 Mask */\r
+#define PORT2_IOCR8_PC9_Pos 11 /*!< PORT2 IOCR8: PC9 Position */\r
+#define PORT2_IOCR8_PC9_Msk (0x1fUL << PORT2_IOCR8_PC9_Pos) /*!< PORT2 IOCR8: PC9 Mask */\r
+#define PORT2_IOCR8_PC10_Pos 19 /*!< PORT2 IOCR8: PC10 Position */\r
+#define PORT2_IOCR8_PC10_Msk (0x1fUL << PORT2_IOCR8_PC10_Pos) /*!< PORT2 IOCR8: PC10 Mask */\r
+#define PORT2_IOCR8_PC11_Pos 27 /*!< PORT2 IOCR8: PC11 Position */\r
+#define PORT2_IOCR8_PC11_Msk (0x1fUL << PORT2_IOCR8_PC11_Pos) /*!< PORT2 IOCR8: PC11 Mask */\r
+\r
+/* ---------------------------------- PORT2_IN ---------------------------------- */\r
+#define PORT2_IN_P0_Pos 0 /*!< PORT2 IN: P0 Position */\r
+#define PORT2_IN_P0_Msk (0x01UL << PORT2_IN_P0_Pos) /*!< PORT2 IN: P0 Mask */\r
+#define PORT2_IN_P1_Pos 1 /*!< PORT2 IN: P1 Position */\r
+#define PORT2_IN_P1_Msk (0x01UL << PORT2_IN_P1_Pos) /*!< PORT2 IN: P1 Mask */\r
+#define PORT2_IN_P2_Pos 2 /*!< PORT2 IN: P2 Position */\r
+#define PORT2_IN_P2_Msk (0x01UL << PORT2_IN_P2_Pos) /*!< PORT2 IN: P2 Mask */\r
+#define PORT2_IN_P3_Pos 3 /*!< PORT2 IN: P3 Position */\r
+#define PORT2_IN_P3_Msk (0x01UL << PORT2_IN_P3_Pos) /*!< PORT2 IN: P3 Mask */\r
+#define PORT2_IN_P4_Pos 4 /*!< PORT2 IN: P4 Position */\r
+#define PORT2_IN_P4_Msk (0x01UL << PORT2_IN_P4_Pos) /*!< PORT2 IN: P4 Mask */\r
+#define PORT2_IN_P5_Pos 5 /*!< PORT2 IN: P5 Position */\r
+#define PORT2_IN_P5_Msk (0x01UL << PORT2_IN_P5_Pos) /*!< PORT2 IN: P5 Mask */\r
+#define PORT2_IN_P6_Pos 6 /*!< PORT2 IN: P6 Position */\r
+#define PORT2_IN_P6_Msk (0x01UL << PORT2_IN_P6_Pos) /*!< PORT2 IN: P6 Mask */\r
+#define PORT2_IN_P7_Pos 7 /*!< PORT2 IN: P7 Position */\r
+#define PORT2_IN_P7_Msk (0x01UL << PORT2_IN_P7_Pos) /*!< PORT2 IN: P7 Mask */\r
+#define PORT2_IN_P8_Pos 8 /*!< PORT2 IN: P8 Position */\r
+#define PORT2_IN_P8_Msk (0x01UL << PORT2_IN_P8_Pos) /*!< PORT2 IN: P8 Mask */\r
+#define PORT2_IN_P9_Pos 9 /*!< PORT2 IN: P9 Position */\r
+#define PORT2_IN_P9_Msk (0x01UL << PORT2_IN_P9_Pos) /*!< PORT2 IN: P9 Mask */\r
+#define PORT2_IN_P10_Pos 10 /*!< PORT2 IN: P10 Position */\r
+#define PORT2_IN_P10_Msk (0x01UL << PORT2_IN_P10_Pos) /*!< PORT2 IN: P10 Mask */\r
+#define PORT2_IN_P11_Pos 11 /*!< PORT2 IN: P11 Position */\r
+#define PORT2_IN_P11_Msk (0x01UL << PORT2_IN_P11_Pos) /*!< PORT2 IN: P11 Mask */\r
+\r
+/* --------------------------------- PORT2_PHCR0 -------------------------------- */\r
+#define PORT2_PHCR0_PH0_Pos 2 /*!< PORT2 PHCR0: PH0 Position */\r
+#define PORT2_PHCR0_PH0_Msk (0x01UL << PORT2_PHCR0_PH0_Pos) /*!< PORT2 PHCR0: PH0 Mask */\r
+#define PORT2_PHCR0_PH1_Pos 6 /*!< PORT2 PHCR0: PH1 Position */\r
+#define PORT2_PHCR0_PH1_Msk (0x01UL << PORT2_PHCR0_PH1_Pos) /*!< PORT2 PHCR0: PH1 Mask */\r
+#define PORT2_PHCR0_PH2_Pos 10 /*!< PORT2 PHCR0: PH2 Position */\r
+#define PORT2_PHCR0_PH2_Msk (0x01UL << PORT2_PHCR0_PH2_Pos) /*!< PORT2 PHCR0: PH2 Mask */\r
+#define PORT2_PHCR0_PH3_Pos 14 /*!< PORT2 PHCR0: PH3 Position */\r
+#define PORT2_PHCR0_PH3_Msk (0x01UL << PORT2_PHCR0_PH3_Pos) /*!< PORT2 PHCR0: PH3 Mask */\r
+#define PORT2_PHCR0_PH4_Pos 18 /*!< PORT2 PHCR0: PH4 Position */\r
+#define PORT2_PHCR0_PH4_Msk (0x01UL << PORT2_PHCR0_PH4_Pos) /*!< PORT2 PHCR0: PH4 Mask */\r
+#define PORT2_PHCR0_PH5_Pos 22 /*!< PORT2 PHCR0: PH5 Position */\r
+#define PORT2_PHCR0_PH5_Msk (0x01UL << PORT2_PHCR0_PH5_Pos) /*!< PORT2 PHCR0: PH5 Mask */\r
+#define PORT2_PHCR0_PH6_Pos 26 /*!< PORT2 PHCR0: PH6 Position */\r
+#define PORT2_PHCR0_PH6_Msk (0x01UL << PORT2_PHCR0_PH6_Pos) /*!< PORT2 PHCR0: PH6 Mask */\r
+#define PORT2_PHCR0_PH7_Pos 30 /*!< PORT2 PHCR0: PH7 Position */\r
+#define PORT2_PHCR0_PH7_Msk (0x01UL << PORT2_PHCR0_PH7_Pos) /*!< PORT2 PHCR0: PH7 Mask */\r
+\r
+/* --------------------------------- PORT2_PHCR1 -------------------------------- */\r
+#define PORT2_PHCR1_PH8_Pos 2 /*!< PORT2 PHCR1: PH8 Position */\r
+#define PORT2_PHCR1_PH8_Msk (0x01UL << PORT2_PHCR1_PH8_Pos) /*!< PORT2 PHCR1: PH8 Mask */\r
+#define PORT2_PHCR1_PH9_Pos 6 /*!< PORT2 PHCR1: PH9 Position */\r
+#define PORT2_PHCR1_PH9_Msk (0x01UL << PORT2_PHCR1_PH9_Pos) /*!< PORT2 PHCR1: PH9 Mask */\r
+#define PORT2_PHCR1_PH10_Pos 10 /*!< PORT2 PHCR1: PH10 Position */\r
+#define PORT2_PHCR1_PH10_Msk (0x01UL << PORT2_PHCR1_PH10_Pos) /*!< PORT2 PHCR1: PH10 Mask */\r
+#define PORT2_PHCR1_PH11_Pos 14 /*!< PORT2 PHCR1: PH11 Position */\r
+#define PORT2_PHCR1_PH11_Msk (0x01UL << PORT2_PHCR1_PH11_Pos) /*!< PORT2 PHCR1: PH11 Mask */\r
+\r
+/* --------------------------------- PORT2_PDISC -------------------------------- */\r
+#define PORT2_PDISC_PDIS0_Pos 0 /*!< PORT2 PDISC: PDIS0 Position */\r
+#define PORT2_PDISC_PDIS0_Msk (0x01UL << PORT2_PDISC_PDIS0_Pos) /*!< PORT2 PDISC: PDIS0 Mask */\r
+#define PORT2_PDISC_PDIS1_Pos 1 /*!< PORT2 PDISC: PDIS1 Position */\r
+#define PORT2_PDISC_PDIS1_Msk (0x01UL << PORT2_PDISC_PDIS1_Pos) /*!< PORT2 PDISC: PDIS1 Mask */\r
+#define PORT2_PDISC_PDIS2_Pos 2 /*!< PORT2 PDISC: PDIS2 Position */\r
+#define PORT2_PDISC_PDIS2_Msk (0x01UL << PORT2_PDISC_PDIS2_Pos) /*!< PORT2 PDISC: PDIS2 Mask */\r
+#define PORT2_PDISC_PDIS3_Pos 3 /*!< PORT2 PDISC: PDIS3 Position */\r
+#define PORT2_PDISC_PDIS3_Msk (0x01UL << PORT2_PDISC_PDIS3_Pos) /*!< PORT2 PDISC: PDIS3 Mask */\r
+#define PORT2_PDISC_PDIS4_Pos 4 /*!< PORT2 PDISC: PDIS4 Position */\r
+#define PORT2_PDISC_PDIS4_Msk (0x01UL << PORT2_PDISC_PDIS4_Pos) /*!< PORT2 PDISC: PDIS4 Mask */\r
+#define PORT2_PDISC_PDIS5_Pos 5 /*!< PORT2 PDISC: PDIS5 Position */\r
+#define PORT2_PDISC_PDIS5_Msk (0x01UL << PORT2_PDISC_PDIS5_Pos) /*!< PORT2 PDISC: PDIS5 Mask */\r
+#define PORT2_PDISC_PDIS6_Pos 6 /*!< PORT2 PDISC: PDIS6 Position */\r
+#define PORT2_PDISC_PDIS6_Msk (0x01UL << PORT2_PDISC_PDIS6_Pos) /*!< PORT2 PDISC: PDIS6 Mask */\r
+#define PORT2_PDISC_PDIS7_Pos 7 /*!< PORT2 PDISC: PDIS7 Position */\r
+#define PORT2_PDISC_PDIS7_Msk (0x01UL << PORT2_PDISC_PDIS7_Pos) /*!< PORT2 PDISC: PDIS7 Mask */\r
+#define PORT2_PDISC_PDIS8_Pos 8 /*!< PORT2 PDISC: PDIS8 Position */\r
+#define PORT2_PDISC_PDIS8_Msk (0x01UL << PORT2_PDISC_PDIS8_Pos) /*!< PORT2 PDISC: PDIS8 Mask */\r
+#define PORT2_PDISC_PDIS9_Pos 9 /*!< PORT2 PDISC: PDIS9 Position */\r
+#define PORT2_PDISC_PDIS9_Msk (0x01UL << PORT2_PDISC_PDIS9_Pos) /*!< PORT2 PDISC: PDIS9 Mask */\r
+#define PORT2_PDISC_PDIS10_Pos 10 /*!< PORT2 PDISC: PDIS10 Position */\r
+#define PORT2_PDISC_PDIS10_Msk (0x01UL << PORT2_PDISC_PDIS10_Pos) /*!< PORT2 PDISC: PDIS10 Mask */\r
+#define PORT2_PDISC_PDIS11_Pos 11 /*!< PORT2 PDISC: PDIS11 Position */\r
+#define PORT2_PDISC_PDIS11_Msk (0x01UL << PORT2_PDISC_PDIS11_Pos) /*!< PORT2 PDISC: PDIS11 Mask */\r
+\r
+/* ---------------------------------- PORT2_PPS --------------------------------- */\r
+#define PORT2_PPS_PPS0_Pos 0 /*!< PORT2 PPS: PPS0 Position */\r
+#define PORT2_PPS_PPS0_Msk (0x01UL << PORT2_PPS_PPS0_Pos) /*!< PORT2 PPS: PPS0 Mask */\r
+#define PORT2_PPS_PPS1_Pos 1 /*!< PORT2 PPS: PPS1 Position */\r
+#define PORT2_PPS_PPS1_Msk (0x01UL << PORT2_PPS_PPS1_Pos) /*!< PORT2 PPS: PPS1 Mask */\r
+#define PORT2_PPS_PPS2_Pos 2 /*!< PORT2 PPS: PPS2 Position */\r
+#define PORT2_PPS_PPS2_Msk (0x01UL << PORT2_PPS_PPS2_Pos) /*!< PORT2 PPS: PPS2 Mask */\r
+#define PORT2_PPS_PPS3_Pos 3 /*!< PORT2 PPS: PPS3 Position */\r
+#define PORT2_PPS_PPS3_Msk (0x01UL << PORT2_PPS_PPS3_Pos) /*!< PORT2 PPS: PPS3 Mask */\r
+#define PORT2_PPS_PPS4_Pos 4 /*!< PORT2 PPS: PPS4 Position */\r
+#define PORT2_PPS_PPS4_Msk (0x01UL << PORT2_PPS_PPS4_Pos) /*!< PORT2 PPS: PPS4 Mask */\r
+#define PORT2_PPS_PPS5_Pos 5 /*!< PORT2 PPS: PPS5 Position */\r
+#define PORT2_PPS_PPS5_Msk (0x01UL << PORT2_PPS_PPS5_Pos) /*!< PORT2 PPS: PPS5 Mask */\r
+#define PORT2_PPS_PPS6_Pos 6 /*!< PORT2 PPS: PPS6 Position */\r
+#define PORT2_PPS_PPS6_Msk (0x01UL << PORT2_PPS_PPS6_Pos) /*!< PORT2 PPS: PPS6 Mask */\r
+#define PORT2_PPS_PPS7_Pos 7 /*!< PORT2 PPS: PPS7 Position */\r
+#define PORT2_PPS_PPS7_Msk (0x01UL << PORT2_PPS_PPS7_Pos) /*!< PORT2 PPS: PPS7 Mask */\r
+#define PORT2_PPS_PPS8_Pos 8 /*!< PORT2 PPS: PPS8 Position */\r
+#define PORT2_PPS_PPS8_Msk (0x01UL << PORT2_PPS_PPS8_Pos) /*!< PORT2 PPS: PPS8 Mask */\r
+#define PORT2_PPS_PPS9_Pos 9 /*!< PORT2 PPS: PPS9 Position */\r
+#define PORT2_PPS_PPS9_Msk (0x01UL << PORT2_PPS_PPS9_Pos) /*!< PORT2 PPS: PPS9 Mask */\r
+#define PORT2_PPS_PPS10_Pos 10 /*!< PORT2 PPS: PPS10 Position */\r
+#define PORT2_PPS_PPS10_Msk (0x01UL << PORT2_PPS_PPS10_Pos) /*!< PORT2 PPS: PPS10 Mask */\r
+#define PORT2_PPS_PPS11_Pos 11 /*!< PORT2 PPS: PPS11 Position */\r
+#define PORT2_PPS_PPS11_Msk (0x01UL << PORT2_PPS_PPS11_Pos) /*!< PORT2 PPS: PPS11 Mask */\r
+\r
+/* --------------------------------- PORT2_HWSEL -------------------------------- */\r
+#define PORT2_HWSEL_HW0_Pos 0 /*!< PORT2 HWSEL: HW0 Position */\r
+#define PORT2_HWSEL_HW0_Msk (0x03UL << PORT2_HWSEL_HW0_Pos) /*!< PORT2 HWSEL: HW0 Mask */\r
+#define PORT2_HWSEL_HW1_Pos 2 /*!< PORT2 HWSEL: HW1 Position */\r
+#define PORT2_HWSEL_HW1_Msk (0x03UL << PORT2_HWSEL_HW1_Pos) /*!< PORT2 HWSEL: HW1 Mask */\r
+#define PORT2_HWSEL_HW2_Pos 4 /*!< PORT2 HWSEL: HW2 Position */\r
+#define PORT2_HWSEL_HW2_Msk (0x03UL << PORT2_HWSEL_HW2_Pos) /*!< PORT2 HWSEL: HW2 Mask */\r
+#define PORT2_HWSEL_HW3_Pos 6 /*!< PORT2 HWSEL: HW3 Position */\r
+#define PORT2_HWSEL_HW3_Msk (0x03UL << PORT2_HWSEL_HW3_Pos) /*!< PORT2 HWSEL: HW3 Mask */\r
+#define PORT2_HWSEL_HW4_Pos 8 /*!< PORT2 HWSEL: HW4 Position */\r
+#define PORT2_HWSEL_HW4_Msk (0x03UL << PORT2_HWSEL_HW4_Pos) /*!< PORT2 HWSEL: HW4 Mask */\r
+#define PORT2_HWSEL_HW5_Pos 10 /*!< PORT2 HWSEL: HW5 Position */\r
+#define PORT2_HWSEL_HW5_Msk (0x03UL << PORT2_HWSEL_HW5_Pos) /*!< PORT2 HWSEL: HW5 Mask */\r
+#define PORT2_HWSEL_HW6_Pos 12 /*!< PORT2 HWSEL: HW6 Position */\r
+#define PORT2_HWSEL_HW6_Msk (0x03UL << PORT2_HWSEL_HW6_Pos) /*!< PORT2 HWSEL: HW6 Mask */\r
+#define PORT2_HWSEL_HW7_Pos 14 /*!< PORT2 HWSEL: HW7 Position */\r
+#define PORT2_HWSEL_HW7_Msk (0x03UL << PORT2_HWSEL_HW7_Pos) /*!< PORT2 HWSEL: HW7 Mask */\r
+#define PORT2_HWSEL_HW8_Pos 16 /*!< PORT2 HWSEL: HW8 Position */\r
+#define PORT2_HWSEL_HW8_Msk (0x03UL << PORT2_HWSEL_HW8_Pos) /*!< PORT2 HWSEL: HW8 Mask */\r
+#define PORT2_HWSEL_HW9_Pos 18 /*!< PORT2 HWSEL: HW9 Position */\r
+#define PORT2_HWSEL_HW9_Msk (0x03UL << PORT2_HWSEL_HW9_Pos) /*!< PORT2 HWSEL: HW9 Mask */\r
+#define PORT2_HWSEL_HW10_Pos 20 /*!< PORT2 HWSEL: HW10 Position */\r
+#define PORT2_HWSEL_HW10_Msk (0x03UL << PORT2_HWSEL_HW10_Pos) /*!< PORT2 HWSEL: HW10 Mask */\r
+#define PORT2_HWSEL_HW11_Pos 22 /*!< PORT2 HWSEL: HW11 Position */\r
+#define PORT2_HWSEL_HW11_Msk (0x03UL << PORT2_HWSEL_HW11_Pos) /*!< PORT2 HWSEL: HW11 Mask */\r
+\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Peripheral memory map ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB_BASE 0xE000E000UL\r
+#define ERU0_BASE 0x40010600UL\r
+#define PAU_BASE 0x40000000UL\r
+#define NVM_BASE 0x40050000UL\r
+#define WDT_BASE 0x40020000UL\r
+#define RTC_BASE 0x40010A00UL\r
+#define PRNG_BASE 0x48020000UL\r
+#define LEDTS0_BASE 0x50020000UL\r
+#define LEDTS1_BASE 0x50020400UL\r
+#define USIC0_BASE 0x48000008UL\r
+#define USIC0_CH0_BASE 0x48000000UL\r
+#define USIC0_CH1_BASE 0x48000200UL\r
+#define SCU_GENERAL_BASE 0x40010000UL\r
+#define SCU_INTERRUPT_BASE 0x40010038UL\r
+#define SCU_POWER_BASE 0x40010200UL\r
+#define SCU_CLK_BASE 0x40010300UL\r
+#define SCU_RESET_BASE 0x40010400UL\r
+#define COMPARATOR_BASE 0x40010500UL\r
+#define SCU_ANALOG_BASE 0x40011000UL\r
+#define CCU40_BASE 0x48040000UL\r
+#define CCU40_CC40_BASE 0x48040100UL\r
+#define CCU40_CC41_BASE 0x48040200UL\r
+#define CCU40_CC42_BASE 0x48040300UL\r
+#define CCU40_CC43_BASE 0x48040400UL\r
+#define VADC_BASE 0x48030000UL\r
+#define VADC_G0_BASE 0x48030400UL\r
+#define VADC_G1_BASE 0x48030800UL\r
+#define SHS0_BASE 0x48034000UL\r
+#define BCCU0_BASE 0x50030000UL\r
+#define BCCU0_CH0_BASE 0x5003003CUL\r
+#define BCCU0_CH1_BASE 0x50030050UL\r
+#define BCCU0_CH2_BASE 0x50030064UL\r
+#define BCCU0_CH3_BASE 0x50030078UL\r
+#define BCCU0_CH4_BASE 0x5003008CUL\r
+#define BCCU0_CH5_BASE 0x500300A0UL\r
+#define BCCU0_CH6_BASE 0x500300B4UL\r
+#define BCCU0_CH7_BASE 0x500300C8UL\r
+#define BCCU0_CH8_BASE 0x500300DCUL\r
+#define BCCU0_DE0_BASE 0x5003017CUL\r
+#define BCCU0_DE1_BASE 0x50030188UL\r
+#define BCCU0_DE2_BASE 0x50030194UL\r
+#define PORT0_BASE 0x40040000UL\r
+#define PORT1_BASE 0x40040100UL\r
+#define PORT2_BASE 0x40040200UL\r
+\r
+\r
+/* ================================================================================ */\r
+/* ================ Peripheral declaration ================ */\r
+/* ================================================================================ */\r
+\r
+#define PPB ((PPB_Type *) PPB_BASE)\r
+#define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE)\r
+#define PAU ((PAU_Type *) PAU_BASE)\r
+#define NVM ((NVM_Type *) NVM_BASE)\r
+#define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE)\r
+#define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE)\r
+#define PRNG ((PRNG_Type *) PRNG_BASE)\r
+#define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE)\r
+#define LEDTS1 ((LEDTS0_GLOBAL_TypeDef *) LEDTS1_BASE)\r
+#define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE)\r
+#define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE)\r
+#define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE)\r
+#define SCU_GENERAL ((SCU_GENERAL_Type *) SCU_GENERAL_BASE)\r
+#define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE)\r
+#define SCU_POWER ((SCU_POWER_Type *) SCU_POWER_BASE)\r
+#define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE)\r
+#define SCU_RESET ((SCU_RESET_Type *) SCU_RESET_BASE)\r
+#define COMPARATOR ((COMPARATOR_Type *) COMPARATOR_BASE)\r
+#define SCU_ANALOG ((SCU_ANALOG_Type *) SCU_ANALOG_BASE)\r
+#define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE)\r
+#define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE)\r
+#define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE)\r
+#define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE)\r
+#define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE)\r
+#define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE)\r
+#define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE)\r
+#define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE)\r
+#define SHS0 ((SHS_Type *) SHS0_BASE)\r
+#define BCCU0 ((BCCU_Type *) BCCU0_BASE)\r
+#define BCCU0_CH0 ((BCCU_CH_Type *) BCCU0_CH0_BASE)\r
+#define BCCU0_CH1 ((BCCU_CH_Type *) BCCU0_CH1_BASE)\r
+#define BCCU0_CH2 ((BCCU_CH_Type *) BCCU0_CH2_BASE)\r
+#define BCCU0_CH3 ((BCCU_CH_Type *) BCCU0_CH3_BASE)\r
+#define BCCU0_CH4 ((BCCU_CH_Type *) BCCU0_CH4_BASE)\r
+#define BCCU0_CH5 ((BCCU_CH_Type *) BCCU0_CH5_BASE)\r
+#define BCCU0_CH6 ((BCCU_CH_Type *) BCCU0_CH6_BASE)\r
+#define BCCU0_CH7 ((BCCU_CH_Type *) BCCU0_CH7_BASE)\r
+#define BCCU0_CH8 ((BCCU_CH_Type *) BCCU0_CH8_BASE)\r
+#define BCCU0_DE0 ((BCCU_DE_Type *) BCCU0_DE0_BASE)\r
+#define BCCU0_DE1 ((BCCU_DE_Type *) BCCU0_DE1_BASE)\r
+#define BCCU0_DE2 ((BCCU_DE_Type *) BCCU0_DE2_BASE)\r
+#define PORT0 ((PORT0_Type *) PORT0_BASE)\r
+#define PORT1 ((PORT1_Type *) PORT1_BASE)\r
+#define PORT2 ((PORT2_Type *) PORT2_BASE)\r
+\r
+\r
+/** @} */ /* End of group Device_Peripheral_Registers */\r
+/** @} */ /* End of group XMC1200 */\r
+/** @} */ /* End of group Infineon */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif /* XMC1200_H */\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the simply blinky style version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_blinky() creates one queue, and two tasks. It then starts the\r
+ * scheduler.\r
+ *\r
+ * The Queue Send Task:\r
+ * The queue send task is implemented by the prvQueueSendTask() function in\r
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly\r
+ * block for 200 milliseconds, before sending the value 100 to the queue that\r
+ * was created within main_blinky(). Once the value is sent, the task loops\r
+ * back around to block for another 200 milliseconds.\r
+ *\r
+ * The Queue Receive Task:\r
+ * The queue receive task is implemented by the prvQueueReceiveTask() function\r
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly\r
+ * blocks on attempts to read data from the queue that was created within\r
+ * main_blinky(). When data is received, the task checks the value of the\r
+ * data, and if the value equals the expected 100, toggles LED 1. The 'block\r
+ * time' parameter passed to the queue receive function specifies that the\r
+ * task should be held in the Blocked state indefinitely to wait for data to\r
+ * be available on the queue. The queue receive task will only leave the\r
+ * Blocked state when the queue send task writes to the queue. As the queue\r
+ * send task writes to the queue every 200 milliseconds, the queue receive\r
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles\r
+ * the LED every 200 milliseconds.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+\r
+/* Demo includes. */\r
+#include "ParTest.h"\r
+\r
+/* Priorities at which the tasks are created. */\r
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )\r
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )\r
+\r
+/* The rate at which data is sent to the queue. The 200ms value is converted\r
+to ticks using the portTICK_RATE_MS constant. */\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
+\r
+/* The number of items the queue can hold. This is 1 as the receive task\r
+will remove items as they are added, meaning the send task should always find\r
+the queue empty. */\r
+#define mainQUEUE_LENGTH ( 1 )\r
+\r
+/* Values passed to the two tasks just to check the task parameter\r
+functionality. */\r
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )\r
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )\r
+\r
+/* The number of the LED that is toggled. */\r
+#define mainLED_TO_TOGGLE ( 0 )\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * The tasks as described in the comments at the top of this file.\r
+ */\r
+static void prvQueueReceiveTask( void *pvParameters );\r
+static void prvQueueSendTask( void *pvParameters );\r
+\r
+/*\r
+ * Called by main() to create the simply blinky style application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ */\r
+void main_blinky( void );\r
+\r
+/*\r
+ * The hardware only has a single LED. Simply toggle it.\r
+ */\r
+extern void vMainToggleLED( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The queue used by both tasks. */\r
+static xQueueHandle xQueue = NULL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_blinky( void )\r
+{\r
+ /* Create the queue. */\r
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );\r
+\r
+ if( xQueue != NULL )\r
+ {\r
+ /* Start the two tasks as described in the comments at the top of this\r
+ file. */\r
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */\r
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */\r
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */\r
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */\r
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */\r
+ NULL ); /* The task handle is not required, so NULL is passed. */\r
+\r
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );\r
+\r
+ /* Start the tasks and timer running. */\r
+ vTaskStartScheduler();\r
+ }\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then\r
+ there was insufficient FreeRTOS heap memory available for the idle and/or\r
+ timer tasks to be created. See the memory management section on the\r
+ FreeRTOS web site for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueSendTask( void *pvParameters )\r
+{\r
+portTickType xNextWakeTime;\r
+const unsigned long ulValueToSend = 100UL;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );\r
+\r
+ /* Initialise xNextWakeTime - this only needs to be done once. */\r
+ xNextWakeTime = xTaskGetTickCount();\r
+\r
+ for( ;; )\r
+ {\r
+ /* Place this task in the blocked state until it is time to run again.\r
+ The block time is specified in ticks, the constant used converts ticks\r
+ to ms. While in the Blocked state this task will not consume any CPU\r
+ time. */\r
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );\r
+\r
+ /* Send to the queue - causing the queue receive task to unblock and\r
+ toggle the LED. 0 is used as the block time so the sending operation\r
+ will not block - it shouldn't need to block as the queue should always\r
+ be empty at this point in the code. */\r
+ xQueueSend( xQueue, &ulValueToSend, 0U );\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvQueueReceiveTask( void *pvParameters )\r
+{\r
+unsigned long ulReceivedValue;\r
+\r
+ /* Check the task parameter is as expected. */\r
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );\r
+\r
+ for( ;; )\r
+ {\r
+ /* Wait until something arrives in the queue - this task will block\r
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in\r
+ FreeRTOSConfig.h. */\r
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );\r
+\r
+ /* To get here something must have been received from the queue, but\r
+ is it the expected value? If it is, toggle the LED. */\r
+ if( ulReceivedValue == 100UL )\r
+ {\r
+ vParTestToggleLED( mainLED_TO_TOGGLE );\r
+ ulReceivedValue = 0U;\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * NOTE 1: This project provides two demo applications. A simple blinky style\r
+ * project, and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select\r
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY\r
+ * in main.c. This file implements the comprehensive test and demo version.\r
+ *\r
+ * NOTE 2: This file only contains the source code that is specific to the\r
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions\r
+ * required to configure the hardware, are defined in main.c.\r
+ ******************************************************************************\r
+ *\r
+ * main_full() creates a set of standard demo tasks, some application specific\r
+ * tasks, and four timers. It then starts the scheduler. The web documentation\r
+ * provides more details of the standard demo application tasks, which provide\r
+ * no particular functionality, but do provide a good example of how to use the\r
+ * FreeRTOS API.\r
+ *\r
+ * In addition to the standard demo tasks, the following tasks and timer are\r
+ * defined and/or created within this file:\r
+ *\r
+ * "Reg test" tasks - These fill the registers with known values, then check\r
+ * that each register maintains its expected value for the lifetime of the\r
+ * task. Each task uses a different set of values. The reg test tasks execute\r
+ * with a very low priority, so get preempted very frequently. A register\r
+ * containing an unexpected value is indicative of an error in the context\r
+ * switching mechanism.\r
+ *\r
+ * "Flash timers" - A software timer callback function is defined that does\r
+ * nothing but toggle an LED. Three software timers are created that each\r
+ * use the same callback function, but each toggles a different LED at a\r
+ * different frequency. One software timer uses LED1, another LED2 and the\r
+ * third LED3.\r
+ *\r
+ * "Check" software timer - The check timer period is initially set to three\r
+ * seconds. Its callback function checks that all the standard demo tasks, and\r
+ * the register check tasks, are not only still executing, but are executing\r
+ * without reporting any errors. If the check timer callback discovers that a\r
+ * task has either stalled, or reported an error, then it changes the period of\r
+ * the check timer from the initial three seconds, to just 200ms. The callback\r
+ * function also toggles LED 4 each time it is called. This provides a visual\r
+ * indication of the system status: If the LED toggles every three seconds,\r
+ * then no issues have been discovered. If the LED toggles every 200ms, then\r
+ * an issue has been discovered with at least one task.\r
+ */\r
+\r
+/* Kernel includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+#include "queue.h"\r
+#include "timers.h"\r
+\r
+/* Common demo includes. */\r
+#include "blocktim.h"\r
+#include "countsem.h"\r
+#include "recmutex.h"\r
+#include "ParTest.h"\r
+#include "dynamic.h"\r
+\r
+/* The period after which the check timer will expire provided no errors have\r
+been reported by any of the standard demo tasks. ms are converted to the\r
+equivalent in ticks using the portTICK_RATE_MS constant. */\r
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )\r
+\r
+/* The period at which the check timer will expire if an error has been\r
+reported in one of the standard demo tasks. ms are converted to the equivalent\r
+in ticks using the portTICK_RATE_MS constant. */\r
+#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS )\r
+\r
+/* A block time of zero simply means "don't block". */\r
+#define mainDONT_BLOCK ( 0UL )\r
+\r
+/* The base toggle rate used by the flash timers. Each toggle rate is a\r
+multiple of this. */\r
+#define mainFLASH_TIMER_BASE_RATE ( 200UL / portTICK_RATE_MS )\r
+\r
+/* The LED toggle by the check timer. */\r
+#define mainCHECK_LED ( 4 )\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Register check tasks, as described at the top of this file. The nature of\r
+ * these files necessitates that they are written in an assembly.\r
+ */\r
+extern void vRegTest1Task( void *pvParameters );\r
+extern void vRegTest2Task( void *pvParameters );\r
+\r
+/*\r
+ * The hardware only has a single LED. Simply toggle it.\r
+ */\r
+extern void vMainToggleLED( void );\r
+\r
+/*\r
+ * The check timer callback function, as described at the top of this file.\r
+ */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * The flash timer callback function, as described at the top of this file.\r
+ * This callback function is assigned to three separate software timers.\r
+ */\r
+static void prvFlashTimerCallback( xTimerHandle xTimer );\r
+\r
+/*\r
+ * Called by main() to create the comprehensive test/demo application if\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1.\r
+ */\r
+void main_full( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/* The following two variables are used to communicate the status of the\r
+register check tasks to the check software timer. If the variables keep\r
+incrementing, then the register check tasks has not discovered any errors. If\r
+a variable stops incrementing, then an error has been found. */\r
+volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+void main_full( void )\r
+{\r
+xTimerHandle xTimer = NULL;\r
+unsigned long ulTimer;\r
+const unsigned long ulTimersToCreate = 3L;\r
+/* The register test tasks are asm functions that don't use a stack. The\r
+stack allocated just has to be large enough to hold the task context, and\r
+for the additional required for the stack overflow checking to work (if\r
+configured). */\r
+const size_t xRegTestStackSize = 25U;\r
+\r
+ /* Create the standard demo tasks */\r
+ vCreateBlockTimeTasks();\r
+ vStartCountingSemaphoreTasks();\r
+ vStartRecursiveMutexTasks();\r
+ vStartDynamicPriorityTasks();\r
+\r
+ /* Create the register test tasks as described at the top of this file.\r
+ These are naked functions that don't use any stack. A stack still has\r
+ to be allocated to hold the task context. */\r
+ xTaskCreate( vRegTest1Task, /* Function that implements the task. */\r
+ ( signed char * ) "Reg1", /* Text name of the task. */\r
+ xRegTestStackSize, /* Stack allocated to the task. */\r
+ NULL, /* The task parameter is not used. */\r
+ tskIDLE_PRIORITY, /* The priority to assign to the task. */\r
+ NULL ); /* Don't receive a handle back, it is not needed. */\r
+\r
+ xTaskCreate( vRegTest2Task, /* Function that implements the task. */\r
+ ( signed char * ) "Reg2", /* Text name of the task. */\r
+ xRegTestStackSize, /* Stack allocated to the task. */\r
+ NULL, /* The task parameter is not used. */\r
+ tskIDLE_PRIORITY, /* The priority to assign to the task. */\r
+ NULL ); /* Don't receive a handle back, it is not needed. */\r
+\r
+ /* Create the three flash timers. */\r
+ for( ulTimer = 0UL; ulTimer < ulTimersToCreate; ulTimer++ )\r
+ {\r
+ xTimer = xTimerCreate( ( const signed char * ) "FlashTimer", /* A text name, purely to help debugging. */\r
+ ( mainFLASH_TIMER_BASE_RATE * ( ulTimer + 1UL ) ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) ulTimer, /* The ID is used to hold the number of the LED that will be flashed. */\r
+ prvFlashTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+\r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, mainDONT_BLOCK );\r
+ }\r
+ }\r
+\r
+ /* Create the software timer that performs the 'check' functionality,\r
+ as described at the top of this file. */\r
+ xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */\r
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */\r
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */\r
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */\r
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */\r
+ );\r
+\r
+ /* If the software timer was created successfully, start it. It won't\r
+ actually start running until the scheduler starts. A block time of\r
+ zero is used in this call, although any value could be used as the block\r
+ time will be ignored because the scheduler has not started yet. */\r
+ if( xTimer != NULL )\r
+ {\r
+ xTimerStart( xTimer, mainDONT_BLOCK );\r
+ }\r
+\r
+ /* Start the kernel. From here on, only tasks and interrupts will run. */\r
+ vTaskStartScheduler();\r
+\r
+ /* If all is well, the scheduler will now be running, and the following\r
+ line will never be reached. If the following line does execute, then there\r
+ was insufficient FreeRTOS heap memory available for the idle and/or timer\r
+ tasks to be created. See the memory management section on the FreeRTOS web\r
+ site, or the FreeRTOS tutorial books for more details. */\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+/* See the description at the top of this file. */\r
+static void prvCheckTimerCallback( xTimerHandle xTimer )\r
+{\r
+static long lChangedTimerPeriodAlready = pdFALSE;\r
+static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;\r
+unsigned long ulErrorFound = pdFALSE;\r
+\r
+ /* Check all the demo and test tasks to ensure that they are all still\r
+ running, and that none have detected an error. */\r
+ if( xAreDynamicPriorityTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 0UL );\r
+ }\r
+\r
+ if( xAreBlockTimeTestTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 1UL );\r
+ }\r
+\r
+ if( xAreCountingSemaphoreTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 2UL );\r
+ }\r
+\r
+ if( xAreRecursiveMutexTasksStillRunning() != pdPASS )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 3UL );\r
+ }\r
+\r
+ /* Check that the register test 1 task is still running. */\r
+ if( ulLastRegTest1Value == ulRegTest1LoopCounter )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 4UL );\r
+ }\r
+ ulLastRegTest1Value = ulRegTest1LoopCounter;\r
+\r
+ /* Check that the register test 2 task is still running. */\r
+ if( ulLastRegTest2Value == ulRegTest2LoopCounter )\r
+ {\r
+ ulErrorFound |= ( 0x01UL << 5UL );\r
+ }\r
+ ulLastRegTest2Value = ulRegTest2LoopCounter;\r
+\r
+ /* Toggle the check LED to give an indication of the system status. If\r
+ the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then\r
+ everything is ok. A faster toggle indicates an error. */\r
+ vParTestToggleLED( mainCHECK_LED );\r
+\r
+ /* Have any errors been latched in ulErrorFound? If so, shorten the\r
+ period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.\r
+ This will result in an increase in the rate at which mainCHECK_LED\r
+ toggles. */\r
+ if( ulErrorFound != pdFALSE )\r
+ {\r
+ if( lChangedTimerPeriodAlready == pdFALSE )\r
+ {\r
+ lChangedTimerPeriodAlready = pdTRUE;\r
+\r
+ /* This call to xTimerChangePeriod() uses a zero block time.\r
+ Functions called from inside of a timer callback function must\r
+ *never* attempt to block. */\r
+ xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );\r
+ }\r
+ }\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvFlashTimerCallback( xTimerHandle xTimer )\r
+{\r
+unsigned long ulLED;\r
+\r
+ /* This callback function is assigned to three separate software timers.\r
+ Each timer toggles a different LED. Obtain the number of the LED that\r
+ this timer is toggling. */\r
+ ulLED = ( unsigned long ) pvTimerGetTimerID( xTimer );\r
+\r
+ /* Toggle the LED. */\r
+ vParTestToggleLED( ulLED );\r
+}\r
+\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+/******************************************************************************\r
+ * This project provides two demo applications. A simple blinky style project,\r
+ * and a more comprehensive test and demo application. The\r
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to\r
+ * select between the two. The simply blinky demo is implemented and described\r
+ * in main_blinky.c. The more comprehensive test and demo application is\r
+ * implemented and described in main_full.c.\r
+ *\r
+ * This file implements the code that is not demo specific, including the\r
+ * hardware setup and FreeRTOS hook functions. It also contains a dummy\r
+ * interrupt service routine called Dummy_IRQHandler() that is provided as an\r
+ * example of how to use interrupt safe FreeRTOS API functions (those that end\r
+ * in "FromISR").\r
+ *\r
+ *****************************************************************************/\r
+\r
+\r
+/* Standard includes. */\r
+#include "string.h"\r
+\r
+/* FreeRTOS includes. */\r
+#include "FreeRTOS.h"\r
+#include "task.h"\r
+\r
+/* Demo application include. */\r
+#include "ParTest.h"\r
+\r
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,\r
+or 0 to run the more comprehensive test and demo application. */\r
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0\r
+\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+/*\r
+ * Perform any application specific hardware configuration. The clocks,\r
+ * memory, etc. are configured before main() is called.\r
+ */\r
+static void prvSetupHardware( void );\r
+\r
+/*\r
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.\r
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.\r
+ */\r
+extern void main_blinky( void );\r
+extern void main_full( void );\r
+\r
+/*\r
+ * CMSIS clock configuration function.\r
+ */\r
+extern void SystemCoreClockUpdate( void );\r
+\r
+/*-----------------------------------------------------------*/\r
+\r
+int main( void )\r
+{\r
+ /* Prepare the hardware to run this demo. */\r
+ prvSetupHardware();\r
+\r
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top\r
+ of this file. */\r
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1\r
+ {\r
+ main_blinky();\r
+ }\r
+ #else\r
+ {\r
+ main_full();\r
+ }\r
+ #endif\r
+\r
+ return 0;\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+static void prvSetupHardware( void )\r
+{\r
+ SystemCoreClockUpdate();\r
+ vParTestInitialise();\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationMallocFailedHook( void )\r
+{\r
+ /* vApplicationMallocFailedHook() will only be called if\r
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook\r
+ function that will get called if a call to pvPortMalloc() fails.\r
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,\r
+ timer or semaphore is created. It is also called by various parts of the\r
+ demo application. If heap_1.c or heap_2.c are used, then the size of the\r
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in\r
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used\r
+ to query the size of free heap space that remains (although it does not\r
+ provide information on how the remaining heap might be fragmented). */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationIdleHook( void )\r
+{\r
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set\r
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle\r
+ task. It is essential that code added to this hook function never attempts\r
+ to block in any way (for example, call xQueueReceive() with a block time\r
+ specified, or call vTaskDelay()). If the application makes use of the\r
+ vTaskDelete() API function (as this demo application does) then it is also\r
+ important that vApplicationIdleHook() is permitted to return to its calling\r
+ function, because it is the responsibility of the idle task to clean up\r
+ memory allocated by the kernel to any task that has since been deleted. */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )\r
+{\r
+ ( void ) pcTaskName;\r
+ ( void ) pxTask;\r
+\r
+ /* Run time stack overflow checking is performed if\r
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook\r
+ function is called if a stack overflow is detected. */\r
+ taskDISABLE_INTERRUPTS();\r
+ for( ;; );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vApplicationTickHook( void )\r
+{\r
+ /* This function will be called by each tick interrupt if\r
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be\r
+ added here, but the tick hook is called from an interrupt context, so\r
+ code must not attempt to block, and only the interrupt safe FreeRTOS API\r
+ functions can be used (those that end in FromISR()). */\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+#ifdef JUST_AN_EXAMPLE_ISR\r
+\r
+void Dummy_IRQHandler(void)\r
+{\r
+long lHigherPriorityTaskWoken = pdFALSE;\r
+\r
+ /* Clear the interrupt if necessary. */\r
+ Dummy_ClearITPendingBit();\r
+\r
+ /* This interrupt does nothing more than demonstrate how to synchronise a\r
+ task with an interrupt. A semaphore is used for this purpose. Note\r
+ lHigherPriorityTaskWoken is initialised to zero. Only FreeRTOS API functions\r
+ that end in "FromISR" can be called from an ISR. */\r
+ xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );\r
+\r
+ /* If there was a task that was blocked on the semaphore, and giving the\r
+ semaphore caused the task to unblock, and the unblocked task has a priority\r
+ higher than the current Running state task (the task that this interrupt\r
+ interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE\r
+ internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the\r
+ portEND_SWITCHING_ISR() macro will result in a context switch being pended to\r
+ ensure this interrupt returns directly to the unblocked, higher priority,\r
+ task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */\r
+ portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );\r
+}\r
+\r
+#endif /* JUST_AN_EXAMPLE_ISR */\r
+\r
+\r
+\r
+\r
--- /dev/null
+@REM This batch file has been generated by the IAR Embedded Workbench\r
+@REM C-SPY Debugger, as an aid to preparing a command line for running\r
+@REM the cspybat command line utility using the appropriate settings.\r
+@REM\r
+@REM Note that this file is generated every time a new debug session\r
+@REM is initialized, so you may want to move or rename the file before\r
+@REM making changes.\r
+@REM\r
+@REM You can launch cspybat by typing the name of this batch file followed\r
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).\r
+@REM\r
+@REM Read about available command line parameters in the C-SPY Debugging\r
+@REM Guide. Hints about additional command line parameters that may be\r
+@REM useful in specific cases:\r
+@REM --download_only Downloads a code image without starting a debug\r
+@REM session afterwards.\r
+@REM --silent Omits the sign-on message.\r
+@REM --timeout Limits the maximum allowed execution time.\r
+@REM \r
+\r
+\r
+"C:\devtools\IAR Systems\Embedded Workbench 6.5\common\bin\cspybat" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armproc.dll" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armjlink.dll" %1 --plugin "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\bin\armbat.dll" --flash_loader "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\Infineon\FlashXMC1200.board" --backend -B "--endian=little" "--cpu=Cortex-M0" "--fpu=None" "-p" "C:\devtools\IAR Systems\Embedded Workbench 6.5\arm\CONFIG\debugger\Infineon\xmc1200.ddf" "--drv_verify_download" "--semihosting" "--device=xmc1200" "--drv_communication=USB0" "--jlink_speed=auto" "--jlink_initial_speed=32" "--jlink_reset_strategy=0,0" "--jlink_interface=SWD" "--drv_catch_exceptions=0x000" "--drv_swo_clock_setup=72000000,0,2000000" \r
+\r
+\r
--- /dev/null
+[DebugChecksum]\r
+Checksum=-2111807952\r
+[Stack]\r
+FillEnabled=0\r
+OverflowWarningsEnabled=1\r
+WarningThreshold=90\r
+SpWarningsEnabled=1\r
+WarnLogOnly=1\r
+UseTrigger=1\r
+TriggerName=main\r
+LimitSize=0\r
+ByteLimit=50\r
+[Exceptions]\r
+StopOnUncaught=_ 0\r
+StopOnThrow=_ 0\r
+[CallStack]\r
+ShowArgs=0\r
+[Disassembly]\r
+MixedMode=1\r
+[JLinkDriver]\r
+CStepIntDis=_ 0\r
+[SWOTraceHWSettings]\r
+OverrideDefaultClocks=0\r
+CpuClock=72000000\r
+ClockAutoDetect=0\r
+ClockWanted=1000000\r
+JtagSpeed=1000000\r
+Prescaler=72\r
+TimeStampPrescIndex=0\r
+TimeStampPrescData=0\r
+PcSampCYCTAP=1\r
+PcSampPOSTCNT=15\r
+PcSampIndex=0\r
+DataLogMode=0\r
+ITMportsEnable=0\r
+ITMportsTermIO=0\r
+ITMportsLogFile=0\r
+ITMlogFile=$PROJ_DIR$\ITM.log\r
+[PowerLog]\r
+LogEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=0\r
+Title0=I0\r
+Symbol0=0 4 1\r
+LiveEnabled=0\r
+LiveFile=PowerLogLive.log\r
+[DataLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+[EventLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+Title0=Ch0\r
+Symbol0=0 4 1\r
+Title1=Ch1\r
+Symbol1=0 4 1\r
+Title2=Ch2\r
+Symbol2=0 4 1\r
+Title3=Ch3\r
+Symbol3=0 4 1\r
+SumSortOrder=0\r
+[InterruptLog]\r
+LogEnabled=0\r
+SumEnabled=0\r
+GraphEnabled=0\r
+ShowTimeLog=1\r
+ShowTimeSum=1\r
+SumSortOrder=0\r
+[Log file]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+Category=_ 0\r
+[TermIOLog]\r
+LoggingEnabled=_ 0\r
+LogFile=_ ""\r
+[Trace2]\r
+Enabled=0\r
+ShowSource=0\r
+[SWOTraceWindow]\r
+PcSampling=0\r
+InterruptLogs=0\r
+ForcedTimeStamps=0\r
+EventCPI=0\r
+EventEXC=0\r
+EventFOLD=0\r
+EventLSU=0\r
+EventSLEEP=0\r
+[PowerProbe]\r
+Frequency=10000\r
+Probe0=I0\r
+ProbeSetup0=2 1 1 2 0 0\r
+[CallStackLog]\r
+Enabled=0\r
+[DriverProfiling]\r
+Enabled=0\r
+Mode=3\r
+Graph=0\r
+Symbiont=0\r
+Exclusions=\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Count=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
--- /dev/null
+<?xml version="1.0" encoding="iso-8859-1"?>\r
+\r
+<Workspace>\r
+ <ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
+ <Desktop>\r
+ <Static>\r
+ <Workspace>\r
+ <ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>236</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
+ </Workspace>\r
+ <Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
+ <TerminalIO/>\r
+ </Static>\r
+ <Windows>\r
+ \r
+ \r
+ <Wnd0>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-23707-15152</Identity>\r
+ <TabName>Workspace</TabName>\r
+ <Factory>Workspace</Factory>\r
+ <Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/System</ExpandedNode></NodeDict></Session>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
+ <Tabs>\r
+ <Tab>\r
+ <Identity>TabID-19002-15240</Identity>\r
+ <TabName>Build</TabName>\r
+ <Factory>Build</Factory>\r
+ <Session/>\r
+ </Tab>\r
+ </Tabs>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
+ <Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>99</YPos2><SelStart2>5509</SelStart2><SelEnd2>5509</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main-full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>111</YPos2><SelStart2>7445</SelStart2><SelEnd2>7445</SelEnd2></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
+ <Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-01348f40><key>iaridepm.enu1</key></Toolbar-01348f40></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>310</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>185714</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
+ </Desktop>\r
+</Workspace>\r
+\r
+\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1200.c\r
+ * @brief Device specific initialization for the XMC1200-Series according\r
+ * to CMSIS\r
+ * @version V1.4\r
+ * @date 01 Feb 2013\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with\r
+ * Infineon\92s microcontrollers.\r
+ *\r
+ * This file can be freely distributed within development tools that are\r
+ * supporting such microcontrollers.\r
+ *\r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ * V1.3, 20 Dec 2012, PKB : Fixed SystemCoreClock computation\r
+ * V1.4, 01 Feb 2013, PKB : SCU_CLOCK -> SCU_CLK\r
+ */\r
+\r
+#include "system_XMC1200.h"\r
+#include <XMC1200.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions\r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+#define DCO_DCLK_MULTIPLIER 16384000UL\r
+#define DCO_DCLK_DIVIDER 9UL\r
+#define MCLK_MHZ 32000000UL\r
+#define KHZ_MULTIPLIER 1000UL\r
+#define FRACBITS 8UL\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock) (MCLK on TIMM1) */\r
+uint32_t SystemCoreClock;\r
+\r
+/*----------------------------------------------------------------------------\r
+ Fixed point math definitions\r
+ *----------------------------------------------------------------------------*/\r
+typedef int32_t Q_24_8;\r
+typedef int32_t Q_15_0;\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{\r
+\r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */\r
+ if(AllowClkInitByStartup()){\r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note -\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, FDIV, CLKCR, Clock;\r
+\r
+ CLKCR = SCU_CLK -> CLKCR;\r
+ IDIV = (CLKCR & SCU_CLK_CLKCR_IDIV_Msk) >> SCU_CLK_CLKCR_IDIV_Pos;\r
+ FDIV = (CLKCR & SCU_CLK_CLKCR_FDIV_Msk) >> SCU_CLK_CLKCR_FDIV_Pos;\r
+\r
+ if(IDIV)\r
+ {\r
+ /* Divider is enabled and used */\r
+ if(0 == FDIV)\r
+ {\r
+ /* No fractional divider, so MCLK = DCO_Clk / (2 * IDIV) */\r
+ Clock = MCLK_MHZ / IDIV;\r
+ }\r
+ else\r
+ {\r
+ /* Both integer and fractional divider must be considered */\r
+ /* 1. IDIV + FDIV/256 */\r
+ Q_24_8 FDiv_IDiv_Sum = (IDIV << FRACBITS) + FDIV;\r
+\r
+ /* 2. Fixed point division Q24.8 / Q9.8 = Q15.0 */\r
+ Q_15_0 ClockVal = (DCO_DCLK_MULTIPLIER << FRACBITS)/ FDiv_IDiv_Sum;\r
+ Clock = ((uint32_t)ClockVal) * KHZ_MULTIPLIER;\r
+ Clock = Clock >> DCO_DCLK_DIVIDER;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed. Simply divide DCO_DCLK by 2 */\r
+ Clock = MCLK_MHZ;\r
+ }\r
+\r
+ /* Finally with the math class over, update SystemCoreClock */\r
+ SystemCoreClock = Clock;\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1200.h\r
+ * @brief Device specific initialization for the XMC1200-Series according \r
+ * to CMSIS\r
+ * @version V1.1\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/* \r
+ * **************************** Change history *******************************\r
+ * V1.1, 13 Dec 2012, PKB : Created this table, added extern and stdint\r
+ */\r
+\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+extern uint32_t SystemCoreClock;\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * Initialize the PLL and update the \r
+ * SystemCoreClock variable.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void);\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void);\r
+\r
#define BLOCKQ_1 1\r
\r
\r
-\r
-\r
-/* A task is created to test the behaviour of the interrupt controller during\r
-context switches. This macro is just used to set a variable to true each time\r
-the test task is switched out - the task itself needs to know when this happens\r
-in order to complete its tests. This macro will slow down the context switch\r
-and can normally be removed (just delete the whole macro, although doing so will\r
-cause the test task to indicate an error). */\r
-extern void *xICTestTask;\r
-extern volatile unsigned long ulTaskSwitchedOut;\r
-#define traceTASK_SWITCHED_OUT() if( pxCurrentTCB == xICTestTask ) ulTaskSwitchedOut = pdTRUE\r
-\r
-\r
-\r
#endif /* FREERTOS_CONFIG_H */\r
\r
\r
static void vRegTest1( void *pvParameters );\r
static void vRegTest2( void *pvParameters );\r
\r
-/*\r
- * A task that tests the management of the Interrupt Controller (IC) during a\r
- * context switch. The state of the IC current mask level must be maintained\r
- * across context switches. Also, yields must be able to be performed when the\r
- * interrupt controller mask is not zero. This task tests both these\r
- * requirements.\r
- */\r
-static void prvICCheck1Task( void *pvParameters );\r
-\r
/* Counters used to ensure the tasks are still running. */\r
-static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL, ulICTestCounter = 0UL;\r
+static volatile unsigned long ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL;\r
\r
-/* Handle to the task that checks the interrupt controller behaviour. This is\r
-used by the traceTASK_SWITCHED_OUT() macro, which is defined in\r
-FreeRTOSConfig.h and can be removed - it is just for the purpose of this test. */\r
-xTaskHandle xICTestTask = NULL;\r
-\r
-/* Variable that gets set to pdTRUE by traceTASK_SWITCHED_OUT each time\r
-is switched out. */\r
-volatile unsigned long ulTaskSwitchedOut;\r
/*-----------------------------------------------------------*/\r
\r
void vStartRegTestTasks( void )\r
{\r
xTaskCreate( vRegTest1, ( signed char * ) "RTest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
xTaskCreate( vRegTest2, ( signed char * ) "RTest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\r
- xTaskCreate( prvICCheck1Task, ( signed char * ) "ICCheck", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xICTestTask );\r
}\r
/*-----------------------------------------------------------*/\r
\r
}\r
/*-----------------------------------------------------------*/\r
\r
-static void prvICCheck1Task( void *pvParameters )\r
-{\r
-long lICCheckStatus = pdPASS;\r
-\r
- for( ;; )\r
- {\r
- /* At this point the interrupt mask should be zero. */\r
- if( ic->cpl != 0 )\r
- {\r
- lICCheckStatus = pdFAIL;\r
- }\r
-\r
- /* If we yield here, it should still be 0 when the task next runs.\r
- ulTaskSwitchedOut is just used to check that a switch does actually\r
- happen. */\r
- ulTaskSwitchedOut = pdFALSE;\r
- taskYIELD();\r
- if( ( ulTaskSwitchedOut != pdTRUE ) || ( ic->cpl != 0 ) )\r
- {\r
- lICCheckStatus = pdFAIL;\r
- }\r
-\r
- /* Set the interrupt mask to portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1,\r
- before checking it is as expected. */\r
- taskENTER_CRITICAL();\r
- if( ic->cpl != ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 ) )\r
- {\r
- lICCheckStatus = pdFAIL;\r
- }\r
-\r
- /* If we yield here, it should still be\r
- portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 10 when the task next runs. */\r
- ulTaskSwitchedOut = pdFALSE;\r
- taskYIELD();\r
- if( ( ulTaskSwitchedOut != pdTRUE ) || ( ic->cpl != ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 ) ) )\r
- {\r
- lICCheckStatus = pdFAIL;\r
- }\r
-\r
- /* Return the interrupt mask to its default state. */\r
- taskEXIT_CRITICAL();\r
-\r
- /* Just increment a loop counter so the check task knows if this task\r
- is still running or not. */\r
- if( lICCheckStatus == pdPASS )\r
- {\r
- ulICTestCounter++;\r
- }\r
- }\r
-}\r
-/*-----------------------------------------------------------*/\r
-\r
portBASE_TYPE xAreRegTestTasksStillRunning( void )\r
{\r
-static unsigned long ulLastCounter1 = 0UL, ulLastCounter2 = 0UL, ulLastICTestCounter = 0UL;\r
+static unsigned long ulLastCounter1 = 0UL, ulLastCounter2 = 0UL;\r
long lReturn;\r
\r
/* Check that both loop counters are still incrementing, indicating that\r
{\r
lReturn = pdFAIL;\r
}\r
- else if( ulLastICTestCounter == ulICTestCounter )\r
- {\r
- lReturn = pdFAIL;\r
- }\r
else\r
{\r
lReturn = pdPASS;\r
\r
ulLastCounter1 = ulRegTest1Counter;\r
ulLastCounter2 = ulRegTest2Counter;\r
- ulLastICTestCounter = ulICTestCounter;\r
\r
return lReturn;\r
}\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
transmitted. */\r
static xQueueHandle xRxedChars;\r
static xQueueHandle xCharsForTx;\r
-extern unsigned portBASE_TYPE *pxVectorTable;\r
/*-----------------------------------------------------------*/\r
\r
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )\r
uart1->tx_mask = 0;\r
uart1->rx_mask = 1;\r
irq[IRQ_UART1_TX].ien = 1;\r
- irq[IRQ_UART1_TX].ipl = portSYSTEM_INTERRUPT_PRIORITY_LEVEL;\r
irq[IRQ_UART1_RX].ien = 1;\r
- irq[IRQ_UART1_RX].ipl = portSYSTEM_INTERRUPT_PRIORITY_LEVEL;\r
}\r
\r
return ( xComPortHandle ) 0;\r
projects / freertos / commitdiff