--- /dev/null
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>\r
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">\r
+ <storageModule moduleId="org.eclipse.cdt.core.settings">\r
+ <cconfiguration id="com.atollic.truestudio.exe.debug.2093031755">\r
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.atollic.truestudio.exe.debug.2093031755" moduleId="org.eclipse.cdt.core.settings" name="Debug">\r
+ <externalSettings/>\r
+ <extensions>\r
+ <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>\r
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>\r
+ </extensions>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="com.atollic.truestudio.exe.debug.2093031755" name="Debug" parent="com.atollic.truestudio.exe.debug">\r
+ <folderInfo id="com.atollic.truestudio.exe.debug.2093031755." name="/" resourcePath="">\r
+ <toolChain id="com.atollic.truestudio.exe.debug.toolchain.695580378" name="Atollic ARM Tools" superClass="com.atollic.truestudio.exe.debug.toolchain">\r
+ <targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.atollic.truestudio.exe.debug.toolchain.platform.2131771238" isAbstract="false" name="Debug platform" superClass="com.atollic.truestudio.exe.debug.toolchain.platform"/>\r
+ <builder buildPath="${workspace_loc:/RTOSDemo/Debug}" id="com.atollic.truestudio.mbs.builder1.1523343795" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="CDT Internal Builder" superClass="com.atollic.truestudio.mbs.builder1">\r
+ <outputEntries>\r
+ <entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>\r
+ </outputEntries>\r
+ </builder>\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.as.97785284" name="Assembler" superClass="com.atollic.truestudio.exe.debug.toolchain.as">\r
+ <option id="com.atollic.truestudio.common_options.target.fpucore.859341639" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="None" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.endianess.460598916" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>\r
+ <option id="com.atollic.truestudio.common_options.target.mcpu.1991364094" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="XMC1200-T038F0200" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.instr_set.1178677075" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpu.1312129520" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>\r
+ <option id="com.atollic.truestudio.as.symbols.defined.824610384" name="Defined symbols" superClass="com.atollic.truestudio.as.symbols.defined" valueType="definedSymbols">\r
+ <listOptionValue builtIn="false" value="XMC1200"/>\r
+ </option>\r
+ <option id="com.atollic.truestudio.as.general.incpath.1440953599" name="Include path" superClass="com.atollic.truestudio.as.general.incpath" valueType="includePath">\r
+ <listOptionValue builtIn="false" value="C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Libraries/Device/Infineon/XMC1200_series/Include"/>\r
+ <listOptionValue builtIn="false" value="C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/Libraries/CMSIS/Include"/>\r
+ <listOptionValue builtIn="false" value="C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/src"/>\r
+ </option>\r
+ <inputType id="com.atollic.truestudio.as.input.1065597400" name="Input" superClass="com.atollic.truestudio.as.input"/>\r
+ </tool>\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.gcc.37591077" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc">\r
+ <option id="com.atollic.truestudio.common_options.target.mcpu.1203399414" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="XMC1200-T038F0200" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.instr_set.505304009" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.interwork.1573626780" name="Mix ARM/Thumb" superClass="com.atollic.truestudio.common_options.target.interwork"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpu.640300337" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpucore.1302488824" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="None" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.gcc.symbols.defined.213458231" name="Defined symbols" superClass="com.atollic.truestudio.gcc.symbols.defined" valueType="definedSymbols">\r
+ <listOptionValue builtIn="false" value="XMC1200"/>\r
+ </option>\r
+ <option id="com.atollic.truestudio.gcc.directories.select.50847705" name="Include path" superClass="com.atollic.truestudio.gcc.directories.select" valueType="includePath">\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/CMSIS}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Common_Demo_Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Atollic_Specific}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/include}""/>\r
+ <listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/ARM_CM0}""/>\r
+ </option>\r
+ <option id="com.atollic.truestudio.common_options.target.endianess.1238437628" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>\r
+ <option id="com.atollic.truestudio.gcc.optimization.prep_garbage.1914199267" name="Prepare dead code removal" superClass="com.atollic.truestudio.gcc.optimization.prep_garbage" value="true" valueType="boolean"/>\r
+ <option id="com.atollic.truestudio.gcc.optimization.prep_data.989109200" name="Prepare dead data removal" superClass="com.atollic.truestudio.gcc.optimization.prep_data" value="true" valueType="boolean"/>\r
+ <inputType id="com.atollic.truestudio.gcc.input.1008000819" superClass="com.atollic.truestudio.gcc.input"/>\r
+ </tool>\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.ld.298485676" name="C Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ld">\r
+ <option id="com.atollic.truestudio.common_options.target.fpucore.370646558" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="None" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.endianess.775626288" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>\r
+ <option id="com.atollic.truestudio.common_options.target.mcpu.822857371" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="XMC1200-T038F0200" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.instr_set.1027082086" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpu.2097263765" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>\r
+ <option id="com.atollic.truestudio.ld.general.clib.1499111687" name="Runtime Library:" superClass="com.atollic.truestudio.ld.general.clib" value="com.atollic.truestudio.ld.general.clib.small" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.ld.general.scriptfile.1390912393" name="Linker script" superClass="com.atollic.truestudio.ld.general.scriptfile" value="../Atollic_Specific/xmc1000_flash.ld" valueType="string"/>\r
+ <option id="com.atollic.truestudio.ld.optimization.do_garbage.1726089101" name="Dead code removal" superClass="com.atollic.truestudio.ld.optimization.do_garbage" value="true" valueType="boolean"/>\r
+ <inputType id="com.atollic.truestudio.ld.input.715750125" name="Input" superClass="com.atollic.truestudio.ld.input">\r
+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>\r
+ <additionalInput kind="additionalinput" paths="$(LIBS)"/>\r
+ </inputType>\r
+ </tool>\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.gpp.1902950101" name="C++ Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gpp">\r
+ <option id="com.atollic.truestudio.gpp.symbols.defined.579464539" name="Defined symbols" superClass="com.atollic.truestudio.gpp.symbols.defined" valueType="definedSymbols">\r
+ <listOptionValue builtIn="false" value="XMC1200"/>\r
+ </option>\r
+ <option id="com.atollic.truestudio.gpp.directories.select.837492116" name="Include path" superClass="com.atollic.truestudio.gpp.directories.select" valueType="includePath">\r
+ <listOptionValue builtIn="false" value="../Libraries/Device/Infineon/XMC1200_series/Include"/>\r
+ <listOptionValue builtIn="false" value="../Libraries/CMSIS/Include"/>\r
+ <listOptionValue builtIn="false" value="../src"/>\r
+ </option>\r
+ <option id="com.atollic.truestudio.common_options.target.endianess.1746048697" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>\r
+ <option id="com.atollic.truestudio.common_options.target.mcpu.1737655603" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="XMC1200-T038F0200" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.instr_set.2050062206" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpucore.1899868679" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="None" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpu.142457111" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>\r
+ <option id="com.atollic.truestudio.gpp.optimization.prep_garbage.810923636" name="Prepare dead code removal" superClass="com.atollic.truestudio.gpp.optimization.prep_garbage" value="true" valueType="boolean"/>\r
+ <option id="com.atollic.truestudio.gpp.optimization.prep_data.717306270" name="Prepare dead data removal" superClass="com.atollic.truestudio.gpp.optimization.prep_data" value="true" valueType="boolean"/>\r
+ <option id="com.atollic.truestudio.gpp.optimization.fno_rtti.1460543604" name="Disable RTTI" superClass="com.atollic.truestudio.gpp.optimization.fno_rtti"/>\r
+ <option id="com.atollic.truestudio.gpp.optimization.fno_exceptions.350384352" name="Disable exception handling" superClass="com.atollic.truestudio.gpp.optimization.fno_exceptions"/>\r
+ </tool>\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.ldcc.447187775" name="C++ Linker" superClass="com.atollic.truestudio.exe.debug.toolchain.ldcc">\r
+ <option id="com.atollic.truestudio.common_options.target.endianess.1650031295" name="Endianess" superClass="com.atollic.truestudio.common_options.target.endianess"/>\r
+ <option id="com.atollic.truestudio.common_options.target.mcpu.1471501166" name="Microcontroller" superClass="com.atollic.truestudio.common_options.target.mcpu" value="XMC1200-T038F0200" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.instr_set.408817938" name="Instruction set" superClass="com.atollic.truestudio.common_options.target.instr_set" value="com.atollic.truestudio.common_options.target.instr_set.thumb2" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpucore.1060198968" name="FPU" superClass="com.atollic.truestudio.common_options.target.fpucore" value="None" valueType="enumerated"/>\r
+ <option id="com.atollic.truestudio.common_options.target.fpu.270724373" name="Floating point" superClass="com.atollic.truestudio.common_options.target.fpu"/>\r
+ <option id="com.atollic.truestudio.ld.general.cclib.2106093589" name="Runtime Library:" superClass="com.atollic.truestudio.ld.general.cclib"/>\r
+ <option id="com.atollic.truestudio.ldcc.optimization.do_garbage.643141574" name="Dead code removal" superClass="com.atollic.truestudio.ldcc.optimization.do_garbage" value="true" valueType="boolean"/>\r
+ <option id="com.atollic.truestudio.ldcc.general.scriptfile.865762444" name="Linker script" superClass="com.atollic.truestudio.ldcc.general.scriptfile" value="..\xmc1000_flash.ld" valueType="string"/>\r
+ </tool>\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.secoutput.31389710" name="Other" superClass="com.atollic.truestudio.exe.debug.toolchain.secoutput"/>\r
+ </toolChain>\r
+ </folderInfo>\r
+ <fileInfo id="com.atollic.truestudio.exe.debug.2093031755.1258798340" name="main-full.c" rcbsApplicability="disable" resourcePath="main-full.c" toolsToInvoke="com.atollic.truestudio.exe.debug.toolchain.gcc.37591077.227330701">\r
+ <tool id="com.atollic.truestudio.exe.debug.toolchain.gcc.37591077.227330701" name="C Compiler" superClass="com.atollic.truestudio.exe.debug.toolchain.gcc.37591077"/>\r
+ </fileInfo>\r
+ <sourceEntries>\r
+ <entry excluding="Keil_Specific|IAR_Specific" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>\r
+ </sourceEntries>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>\r
+ </cconfiguration>\r
+ </storageModule>\r
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">\r
+ <project id="RTOSDemo.com.atollic.truestudio.exe.1513105543" name="Executable" projectType="com.atollic.truestudio.exe"/>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>\r
+ <storageModule moduleId="refreshScope" versionNumber="2">\r
+ <configuration configurationName="Debug">\r
+ <resource resourceType="PROJECT" workspacePath="/RTOSDemo"/>\r
+ </configuration>\r
+ </storageModule>\r
+ <storageModule moduleId="scannerConfiguration">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>\r
+ <scannerConfigBuildInfo instanceId="com.atollic.truestudio.exe.debug.2093031755;com.atollic.truestudio.exe.debug.2093031755.;com.atollic.truestudio.exe.debug.toolchain.gcc.37591077;com.atollic.truestudio.gcc.input.1008000819">\r
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.atollic.truestudio.mbs.ARMToolsPerProjectProfileC"/>\r
+ </scannerConfigBuildInfo>\r
+ </storageModule>\r
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>\r
+</cproject>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<projectDescription>\r
+ <name>RTOSDemo</name>\r
+ <comment></comment>\r
+ <projects>\r
+ </projects>\r
+ <buildSpec>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\r
+ <triggers>clean,full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ <buildCommand>\r
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\r
+ <triggers>full,incremental,</triggers>\r
+ <arguments>\r
+ </arguments>\r
+ </buildCommand>\r
+ </buildSpec>\r
+ <natures>\r
+ <nature>org.eclipse.cdt.core.cnature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\r
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\r
+ </natures>\r
+ <linkedResources>\r
+ <link>\r
+ <name>Common_Demo_Source</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source</name>\r
+ <type>2</type>\r
+ <locationURI>virtual:/virtual</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/blocktim.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/Minimal/blocktim.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/countsem.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/Minimal/countsem.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/dynamic.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/Minimal/dynamic.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>Common_Demo_Source/recmutex.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Demo/Common/Minimal/recmutex.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/ARM_CM0</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_BASE/Source/portable/GCC/ARM_CM0</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/heap_4.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/portable/MemMang/heap_4.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/include</name>\r
+ <type>2</type>\r
+ <locationURI>FREERTOS_BASE/Source/include</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/list.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/list.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/queue.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/queue.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/tasks.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/tasks.c</locationURI>\r
+ </link>\r
+ <link>\r
+ <name>FreeRTOS_Source/timers.c</name>\r
+ <type>1</type>\r
+ <locationURI>FREERTOS_BASE/Source/timers.c</locationURI>\r
+ </link>\r
+ </linkedResources>\r
+ <variableList>\r
+ <variable>\r
+ <name>FREERTOS_BASE</name>\r
+ <value>$%7BPARENT-2-PROJECT_LOC%7D</value>\r
+ </variable>\r
+ </variableList>\r
+</projectDescription>\r
--- /dev/null
+BOARD=XMC1200_Boot_Kit\r
+CODE_LOCATION=FLASH\r
+ENDIAN=Little-endian\r
+MCU=XMC1200-T038F0200\r
+MCU_VENDOR=Infineon\r
+MODEL=Pro\r
+PROBE=SEGGER J-LINK\r
+PROJECT_FORMAT_VERSION=2\r
+TARGET=ARM\u00AE\r
+VERSION=4.1.0\r
+eclipse.preferences.version=1\r
--- /dev/null
+eclipse.preferences.version=1\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/delimiter=;\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/CPATH/operation=remove\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/delimiter=;\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/C_INCLUDE_PATH/operation=remove\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/append=true\r
+environment/buildEnvironmentInclude/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/delimiter=;\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/LIBRARY_PATH/operation=remove\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/append=true\r
+environment/buildEnvironmentLibrary/com.atollic.truestudio.exe.debug.2093031755/appendContributed=true\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+void vRegTest1Task( void ) __attribute__((naked));\r
+void vRegTest2Task( void ) __attribute__((naked));\r
+\r
+void vRegTest1Task( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest1LoopCounter \n"\r
+ " \n"\r
+ " /* Fill the core registers with known values. */ \n"\r
+ " movs r1, #101 \n"\r
+ " movs r2, #102 \n"\r
+ " movs r3, #103 \n"\r
+ " movs r4, #104 \n"\r
+ " movs r5, #105 \n"\r
+ " movs r6, #106 \n"\r
+ " movs r7, #107 \n"\r
+ " movs r0, #108 \n"\r
+ " mov r8, r0 \n"\r
+ " movs r0, #109 \n"\r
+ " mov r9, r0 \n"\r
+ " movs r0, #110 \n"\r
+ " mov r10, r0 \n"\r
+ " movs r0, #111 \n"\r
+ " mov r11, r0 \n"\r
+ " movs r0, #112 \n"\r
+ " mov r12, r0 \n"\r
+ " movs r0, #100 \n"\r
+ " \n"\r
+ "reg1_loop: \n"\r
+ " \n"\r
+ " cmp r0, #100 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r1, #101 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r2, #102 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r3, #103 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r4, #104 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r5, #105 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r6, #106 \n"\r
+ " bne reg1_error_loop \n"\r
+ " cmp r7, #107 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #108 \n"\r
+ " cmp r8, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #109 \n"\r
+ " cmp r9, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #110 \n"\r
+ " cmp r10, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #111 \n"\r
+ " cmp r11, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " movs r0, #112 \n"\r
+ " cmp r12, r0 \n"\r
+ " bne reg1_error_loop \n"\r
+ " \n"\r
+ " /* Everything passed, increment the loop counter. */ \n"\r
+ " push { r1 } \n"\r
+ " ldr r0, =ulRegTest1LoopCounter \n"\r
+ " ldr r1, [r0] \n"\r
+ " add r1, r1, #1 \n"\r
+ " str r1, [r0] \n"\r
+ " pop { r1 } \n"\r
+ " \n"\r
+ " /* Start again. */ \n"\r
+ " movs r0, #100 \n"\r
+ " b reg1_loop \n"\r
+ " \n"\r
+ "reg1_error_loop: \n"\r
+ " /* If this line is hit then there was an error in a core register value. \n"\r
+ " The loop ensures the loop counter stops incrementing. */ \n"\r
+ " b reg1_error_loop \n"\r
+ " nop \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+void vRegTest2Task( void )\r
+{\r
+ __asm volatile\r
+ (\r
+ ".extern ulRegTest2LoopCounter \n"\r
+ " \n"\r
+ " /* Fill the core registers with known values. */ \n"\r
+ " movs r1, #1 \n"\r
+ " movs r2, #2 \n"\r
+ " movs r3, #3 \n"\r
+ " movs r4, #4 \n"\r
+ " movs r5, #5 \n"\r
+ " movs r6, #6 \n"\r
+ " movs r7, #7 \n"\r
+ " movs r0, #8 \n"\r
+ " movs r8, r0 \n"\r
+ " movs r0, #9 \n"\r
+ " mov r9, r0 \n"\r
+ " movs r0, #10 \n"\r
+ " mov r10, r0 \n"\r
+ " movs r0, #11 \n"\r
+ " mov r11, r0 \n"\r
+ " movs r0, #12 \n"\r
+ " mov r12, r0 \n"\r
+ " movs r0, #10 \n"\r
+ " \n"\r
+ "reg2_loop: \n"\r
+ " \n"\r
+ " cmp r0, #10 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r1, #1 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r2, #2 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r3, #3 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r4, #4 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r5, #5 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r6, #6 \n"\r
+ " bne reg2_error_loop \n"\r
+ " cmp r7, #7 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #8 \n"\r
+ " cmp r8, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #9 \n"\r
+ " cmp r9, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #10 \n"\r
+ " cmp r10, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #11 \n"\r
+ " cmp r11, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " movs r0, #12 \n"\r
+ " cmp r12, r0 \n"\r
+ " bne reg2_error_loop \n"\r
+ " \n"\r
+ " /* Everything passed, increment the loop counter. */ \n"\r
+ " push { r1 } \n"\r
+ " ldr r0, =ulRegTest2LoopCounter \n"\r
+ " ldr r1, [r0] \n"\r
+ " add r1, r1, #1 \n"\r
+ " str r1, [r0] \n"\r
+ " pop { r1 } \n"\r
+ " \n"\r
+ " /* Start again. */ \n"\r
+ " movs r0, #10 \n"\r
+ " b reg2_loop \n"\r
+ " \n"\r
+ "reg2_error_loop: \n"\r
+ " /* If this line is hit then there was an error in a core register value. \n"\r
+ " The loop ensures the loop counter stops incrementing. */ \n"\r
+ " b reg2_error_loop \n"\r
+ " nop \n"\r
+ );\r
+}\r
+/*-----------------------------------------------------------*/\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**
+*****************************************************************************
+**
+** File : startup_XMC1200.s
+**
+** Abstract : This assembler file contains interrupt vector and
+** startup code for ARM.
+**
+** Functions : Reset_Handler
+** Default_Handler
+** XMCVeneer code
+**
+** Target : Infineon $(DEVICE) Device
+**
+** Environment : Atollic TrueSTUDIO(R)
+**
+** Distribution: The file is distributed \93as is,\94 without any warranty
+** of any kind.
+**
+** (c)Copyright Atollic AB.
+** You may use this file as-is or modify it according to the needs of your
+** project. This file may only be built (assembled or compiled and linked)
+** using the Atollic TrueSTUDIO(R) product. The use of this file together
+** with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+#ifdef DAVE_CE
+#include <Device_Data.h>
+#else
+#define CLKVAL1_SSW 0x80000000
+#define CLKVAL2_SSW 0x80000000
+#endif
+
+ .syntax unified
+ .cpu cortex-m0
+ .fpu softvfp
+ .thumb
+
+.global Reset_Handler
+.global InterruptVector
+.global Default_Handler
+
+/* Linker script definitions */
+/* start address for the initialization values of the .data section */
+.word _sidata
+/* start address for the .data section */
+.word _sdata
+/* end address for the .data section */
+.word _edata
+/* start address for the .bss section */
+.word _sbss
+/* end address for the .bss section */
+.word _ebss
+
+.word VeneerLoadAddr
+.word VeneerStart
+.word VeneerSize
+
+
+/**
+**===========================================================================
+** Program - Reset_Handler
+** Abstract: This code gets called after reset.
+**===========================================================================
+*/
+ .section .text.Reset_Handler,"ax", %progbits
+ .type Reset_Handler, %function
+Reset_Handler:
+ /* Set stack pointer */
+ ldr r0, =_estack
+ mov sp, r0
+
+ /* Branch to SystemInit function */
+ bl SystemInit
+
+ /* Copy data initialization values */
+ ldr r1,=_sidata
+ ldr r2,=_sdata
+ ldr r3,=_edata
+ b cmpdata
+CopyLoop:
+ ldr r0, [r1]
+ str r0, [r2]
+ adds r1, r1, #4
+ adds r2, r2, #4
+cmpdata:
+ cmp r2, r3
+ blt CopyLoop
+
+ /* Clear BSS section */
+ movs r0, #0
+ ldr r2,=_sbss
+ ldr r3,=_ebss
+ b cmpbss
+ClearLoop:
+ str r0, [r2]
+ adds r2, r2, #4
+cmpbss:
+ cmp r2, r3
+ blt ClearLoop
+
+ /* VENEER COPY */
+ /* R0 = Start address, R1 = Destination address, R2 = Size */
+ ldr r0, =VeneerLoadAddr
+ ldr r1, =VeneerStart
+ ldr r2, =VeneerSize
+
+STARTVENEERCOPY:
+ /* R2 contains byte count. Change it to word count. It is ensured in the
+ linker script that the length is always word aligned.
+ */
+ lsrs r2,r2,#2 /* Divide by 4 to obtain word count */
+ beq SKIPVENEERCOPY
+
+ /* The proverbial loop from the schooldays */
+VENEERCOPYLOOP:
+ ldr r3,[R0]
+ str r3,[R1]
+ subs r2,#1
+ beq SKIPVENEERCOPY
+ adds r0,#4
+ adds r1,#4
+ b VENEERCOPYLOOP
+
+SKIPVENEERCOPY:
+ /* Update System Clock */
+ ldr r0,=SystemCoreClockUpdate
+ blx r0
+
+ /* Call static constructors */
+ bl __libc_init_array
+
+ /* Branch to main */
+ bl main
+
+ /* If main returns, branch to Default_Handler. */
+ b Default_Handler
+
+ .size Reset_Handler, .-Reset_Handler
+
+/**
+**===========================================================================
+** Program - Default_Handler
+** Abstract: This code gets called when the processor receives an
+** unexpected interrupt.
+**===========================================================================
+*/
+ .section .text.Default_Handler,"ax", %progbits
+Default_Handler:
+ b Default_Handler
+
+ .size Default_Handler, .-Default_Handler
+
+/**
+**===========================================================================
+** Interrupt vector table
+**===========================================================================
+*/
+ .section .isr_vector,"a", %progbits
+ .globl InterruptVector
+ .type InterruptVector, %object
+
+InterruptVector:
+ .word _estack /* 0 - Stack pointer */
+ .word Reset_Handler /* 1 - Reset */
+ .word NMI_Handler /* 2 - NMI */
+ .word HardFault_Handler /* 3 - Hard fault */
+ .word CLKVAL1_SSW /* Clock configuration value */
+ .word CLKVAL2_SSW /* Clock gating configuration */
+
+ .size InterruptVector, . - InterruptVector
+
+/**
+**===========================================================================
+** Weak interrupt handlers redirected to Default_Handler. These can be
+** overridden in user code.
+**===========================================================================
+*/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler, Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler, Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler, Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler, Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler, Default_Handler
+
+/* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */
+
+/* IRQ Handlers */
+ .weak SCU_0_IRQHandler
+ .type SCU_0_IRQHandler, %function
+SCU_0_IRQHandler:
+ B .
+ .size SCU_0_IRQHandler, . - SCU_0_IRQHandler
+/* ======================================================================== */
+ .weak SCU_1_IRQHandler
+ .type SCU_1_IRQHandler, %function
+SCU_1_IRQHandler:
+ B .
+ .size SCU_1_IRQHandler, . - SCU_1_IRQHandler
+/* ======================================================================== */
+ .weak SCU_2_IRQHandler
+ .type SCU_2_IRQHandler, %function
+SCU_2_IRQHandler:
+ B .
+ .size SCU_2_IRQHandler, . - SCU_2_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_0_IRQHandler
+ .type ERU0_0_IRQHandler, %function
+ERU0_0_IRQHandler:
+ B .
+ .size ERU0_0_IRQHandler, . - ERU0_0_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_1_IRQHandler
+ .type ERU0_1_IRQHandler, %function
+ERU0_1_IRQHandler:
+ B .
+ .size ERU0_1_IRQHandler, . - ERU0_1_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_2_IRQHandler
+ .type ERU0_2_IRQHandler, %function
+ERU0_2_IRQHandler:
+ B .
+ .size ERU0_2_IRQHandler, . - ERU0_2_IRQHandler
+/* ======================================================================== */
+ .weak ERU0_3_IRQHandler
+ .type ERU0_3_IRQHandler, %function
+ERU0_3_IRQHandler:
+ B .
+ .size ERU0_3_IRQHandler, . - ERU0_3_IRQHandler
+/* ======================================================================== */
+ .weak MATH0_0_IRQHandler
+ .type MATH0_0_IRQHandler, %function
+MATH0_0_IRQHandler:
+ B .
+ .size MATH0_0_IRQHandler, . - MATH0_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_C0_0_IRQHandler
+ .type VADC0_C0_0_IRQHandler , %function
+VADC0_C0_0_IRQHandler:
+ B .
+ .size VADC0_C0_0_IRQHandler , . - VADC0_C0_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_C0_1_IRQHandler
+ .type VADC0_C0_1_IRQHandler , %function
+VADC0_C0_1_IRQHandler:
+ B .
+ .size VADC0_C0_1_IRQHandler , . - VADC0_C0_1_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G0_0_IRQHandler
+ .type VADC0_G0_0_IRQHandler, %function
+VADC0_G0_0_IRQHandler:
+ B .
+ .size VADC0_G0_0_IRQHandler, . - VADC0_G0_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G0_1_IRQHandler
+ .type VADC0_G0_1_IRQHandler, %function
+VADC0_G0_1_IRQHandler:
+ B .
+ .size VADC0_G0_1_IRQHandler, . - VADC0_G0_1_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G1_0_IRQHandler
+ .type VADC0_G1_0_IRQHandler, %function
+VADC0_G1_0_IRQHandler:
+ B .
+ .size VADC0_G1_0_IRQHandler, . - VADC0_G1_0_IRQHandler
+/* ======================================================================== */
+ .weak VADC0_G1_1_IRQHandler
+ .type VADC0_G1_1_IRQHandler, %function
+VADC0_G1_1_IRQHandler:
+ B .
+ .size VADC0_G1_1_IRQHandler, . - VADC0_G1_1_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_0_IRQHandler
+ .type CCU40_0_IRQHandler, %function
+CCU40_0_IRQHandler:
+ B .
+ .size CCU40_0_IRQHandler, . - CCU40_0_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_1_IRQHandler
+ .type CCU40_1_IRQHandler, %function
+
+CCU40_1_IRQHandler:
+ B .
+ .size CCU40_1_IRQHandler, . - CCU40_1_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_2_IRQHandler
+ .type CCU40_2_IRQHandler, %function
+CCU40_2_IRQHandler:
+ B .
+ .size CCU40_2_IRQHandler, . - CCU40_2_IRQHandler
+/* ======================================================================== */
+ .weak CCU40_3_IRQHandler
+ .type CCU40_3_IRQHandler, %function
+CCU40_3_IRQHandler:
+ B .
+ .size CCU40_3_IRQHandler, . - CCU40_3_IRQHandler
+/* ======================================================================== */
+ .weak CCU80_0_IRQHandler
+ .type CCU80_0_IRQHandler, %function
+CCU80_0_IRQHandler:
+ B .
+ .size CCU80_0_IRQHandler, . - CCU80_0_IRQHandler
+/* ======================================================================== */
+ .weak CCU80_1_IRQHandler
+ .type CCU80_1_IRQHandler, %function
+CCU80_1_IRQHandler:
+ B .
+ .size CCU80_1_IRQHandler, . - CCU80_1_IRQHandler
+/* ======================================================================== */
+ .weak POSIF0_0_IRQHandler
+ .type POSIF0_0_IRQHandler, %function
+
+POSIF0_0_IRQHandler:
+ B .
+ .size POSIF0_0_IRQHandler, . - POSIF0_0_IRQHandler
+/* ======================================================================== */
+ .weak POSIF0_1_IRQHandler
+ .type POSIF0_1_IRQHandler, %function
+POSIF0_1_IRQHandler:
+ B .
+ .size POSIF0_1_IRQHandler, . - POSIF0_1_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_0_IRQHandler
+ .type USIC0_0_IRQHandler, %function
+USIC0_0_IRQHandler:
+ B .
+ .size USIC0_0_IRQHandler, . - USIC0_0_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_1_IRQHandler
+ .type USIC0_1_IRQHandler, %function
+USIC0_1_IRQHandler:
+ B .
+ .size USIC0_1_IRQHandler, . - USIC0_1_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_2_IRQHandler
+ .type USIC0_2_IRQHandler, %function
+USIC0_2_IRQHandler:
+ B .
+ .size USIC0_2_IRQHandler, . - USIC0_2_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_3_IRQHandler
+ .type USIC0_3_IRQHandler, %function
+USIC0_3_IRQHandler:
+ B .
+ .size USIC0_3_IRQHandler, . - USIC0_3_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_4_IRQHandler
+ .type USIC0_4_IRQHandler, %function
+USIC0_4_IRQHandler:
+ B .
+ .size USIC0_4_IRQHandler, . - USIC0_4_IRQHandler
+/* ======================================================================== */
+ .weak USIC0_5_IRQHandler
+ .type USIC0_5_IRQHandler, %function
+USIC0_5_IRQHandler:
+ B .
+ .size USIC0_5_IRQHandler, . - USIC0_5_IRQHandler
+/* ======================================================================== */
+ .weak LEDTS0_0_IRQHandler
+ .type LEDTS0_0_IRQHandler, %function
+LEDTS0_0_IRQHandler:
+ B .
+ .size LEDTS0_0_IRQHandler, . - LEDTS0_0_IRQHandler
+/* ======================================================================== */
+ .weak LEDTS1_0_IRQHandler
+ .type LEDTS1_0_IRQHandler, %function
+LEDTS1_0_IRQHandler:
+ B .
+ .size LEDTS1_0_IRQHandler, . - LEDTS1_0_IRQHandler
+/* ======================================================================== */
+ .weak BCCU0_0_IRQHandler
+ .type BCCU0_0_IRQHandler, %function
+BCCU0_0_IRQHandler:
+ B .
+ .size BCCU0_0_IRQHandler, . - BCCU0_0_IRQHandler
+/* ======================================================================== */
+/* ======================================================================== */
+
+/* ==================VENEERS VENEERS VENEERS VENEERS VENEERS=============== */
+ .section ".XmcVeneerCode","ax",%progbits
+.globl HardFault_Veneer
+HardFault_Veneer:
+ LDR R0, =HardFault_Handler
+ MOV PC,R0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+
+/* ======================================================================== */
+.globl SVC_Veneer
+SVC_Veneer:
+ LDR R0, =SVC_Handler
+ MOV PC,R0
+ .long 0
+ .long 0
+/* ======================================================================== */
+.globl PendSV_Veneer
+PendSV_Veneer:
+ LDR R0, =PendSV_Handler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SysTick_Veneer
+SysTick_Veneer:
+ LDR R0, =SysTick_Handler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_0_Veneer
+SCU_0_Veneer:
+ LDR R0, =SCU_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_1_Veneer
+SCU_1_Veneer:
+ LDR R0, =SCU_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_2_Veneer
+SCU_2_Veneer:
+ LDR R0, =SCU_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_3_Veneer
+SCU_3_Veneer:
+ LDR R0, =ERU0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_4_Veneer
+SCU_4_Veneer:
+ LDR R0, =ERU0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_5_Veneer
+SCU_5_Veneer:
+ LDR R0, =ERU0_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_6_Veneer
+SCU_6_Veneer:
+ LDR R0, =ERU0_3_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl SCU_7_Veneer
+SCU_7_Veneer:
+ LDR R0, =MATH0_0_IRQHandler
+ MOV PC,R0
+ .long 0
+/* ======================================================================== */
+.globl VADC0_C0_0_Veneer
+VADC0_C0_0_Veneer:
+ LDR R0, =VADC0_C0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_C0_1_Veneer
+VADC0_C0_1_Veneer:
+ LDR R0, =VADC0_C0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G0_0_Veneer
+VADC0_G0_0_Veneer:
+ LDR R0, =VADC0_G0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G0_1_Veneer
+VADC0_G0_1_Veneer:
+ LDR R0, =VADC0_G0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G1_0_Veneer
+VADC0_G1_0_Veneer:
+ LDR R0, =VADC0_G1_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl VADC0_G1_1_Veneer
+VADC0_G1_1_Veneer:
+ LDR R0, =VADC0_G1_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_0_Veneer
+CCU40_0_Veneer:
+ LDR R0, =CCU40_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_1_Veneer
+CCU40_1_Veneer:
+ LDR R0, =CCU40_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_2_Veneer
+CCU40_2_Veneer:
+ LDR R0, =CCU40_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU40_3_Veneer
+CCU40_3_Veneer:
+ LDR R0, =CCU40_3_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU80_0_Veneer
+CCU80_0_Veneer:
+ LDR R0, =CCU80_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl CCU80_1_Veneer
+CCU80_1_Veneer:
+ LDR R0, =CCU80_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl POSIF0_0_Veneer
+POSIF0_0_Veneer:
+ LDR R0, =POSIF0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl POSIF0_1_Veneer
+POSIF0_1_Veneer:
+ LDR R0, =POSIF0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_0_Veneer
+USIC0_0_Veneer:
+ LDR R0, =USIC0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_1_Veneer
+USIC0_1_Veneer:
+ LDR R0, =USIC0_1_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_2_Veneer
+USIC0_2_Veneer:
+ LDR R0, =USIC0_2_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_3_Veneer
+USIC0_3_Veneer:
+ LDR R0, =USIC0_3_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_4_Veneer
+USIC0_4_Veneer:
+ LDR R0, =USIC0_4_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl USIC0_5_Veneer
+USIC0_5_Veneer:
+ LDR R0, =USIC0_5_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl LEDTS0_0_Veneer
+LEDTS0_0_Veneer:
+ LDR R0, =LEDTS0_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+.globl LEDTS1_0_Veneer
+LEDTS1_0_Veneer:
+ LDR R0, =LEDTS1_0_IRQHandler
+ MOV PC,R0
+/* ======================================================================== */
+ .globl BCCU0_0_Veneer
+BCCU0_0_Veneer:
+ LDR R0, =BCCU0_0_IRQHandler
+ MOV PC,R0
+
+/* ======================================================================== */
+
+/* ===== Decision function queried by CMSIS startup for Clock tree setup === */
+/* In the absence of DAVE code engine, CMSIS SystemInit() must perform clock
+ tree setup.
+
+ This decision routine defined here will always return TRUE.
+
+ When overridden by a definition defined in DAVE code engine, this routine
+ returns FALSE indicating that the code engine has performed the clock setup
+*/
+ .section ".XmcStartup"
+ .weak AllowClkInitByStartup
+ .type AllowClkInitByStartup, %function
+AllowClkInitByStartup:
+ MOVS R0,#1
+ BX LR
+ .size AllowClkInitByStartup, . - AllowClkInitByStartup
+
+/* ====== Definition of the default weak SystemInit_DAVE3 function =========
+If DAVE3 requires an extended SystemInit it will create its own version of
+SystemInit_DAVE3 which overrides this weak definition. Example includes
+setting up of external memory interfaces.
+*/
+ .weak SystemInit_DAVE3
+ .type SystemInit_DAVE3, %function
+SystemInit_DAVE3:
+ NOP
+ BX LR
+ .size SystemInit_DAVE3, . - SystemInit_DAVE3
+
+ .end
--- /dev/null
+/*
+*****************************************************************************
+**
+** File : xmc1000_flash.ld
+**
+** Abstract : Linker script for XMC1200-T038F0200 Device with
+** 200KByte FLASH, 16KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Target : Infineon XMC1000 Microcontrollers
+**
+** Environment : Atollic TrueSTUDIO(R)
+**
+** Distribution: The file is distributed \93as is,\94 without any warranty
+** of any kind.
+**
+** (c)Copyright Atollic AB.
+** You may use this file as-is or modify it according to the needs of your
+** project. This file may only be built (assembled or compiled and linked)
+** using the Atollic TrueSTUDIO(R) product. The use of this file together
+** with other tools than Atollic TrueSTUDIO(R) is not permitted.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20004000; /* end of 16K RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0; /* required amount of heap */
+_Min_Stack_Size = 0x80; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x10001000, LENGTH = 200K
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
+ MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.XmcStartup);
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ . = ALIGN(4);
+ eROData = . ;
+
+ /* Initialize XMC Veneer interrupt code */
+ VeneerLoadAddr = ABSOLUTE(eROData);
+ .VENEER_Code ABSOLUTE(0x2000000C) :
+ {
+ VeneerStart = .;
+ KEEP(*(.XmcVeneerCode)) /* Keep the VeneerCode */
+ *(.XmcVeneerCode);
+ . = ALIGN(4);
+ VeneerEnd = .;
+
+ } >RAM AT> FLASH
+
+ VeneerSize = ABSOLUTE(VeneerEnd) - ABSOLUTE(VeneerStart);
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(4);
+ } >RAM
+
+ /* MEMORY_bank1 section, code must be located here explicitly */
+ /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
+ .memory_b1_text :
+ {
+ *(.mb1text) /* .mb1text sections (code) */
+ *(.mb1text*) /* .mb1text* sections (code) */
+ *(.mb1rodata) /* read-only data (constants) */
+ *(.mb1rodata*)
+ } >MEMORY_B1
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm0.h\r
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+#ifndef __CORE_CM0_H_GENERIC\r
+#define __CORE_CM0_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M0\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM0 definitions */\r
+#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+#endif\r
+\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM0_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM0_H_DEPENDANT\r
+#define __CORE_CM0_H_DEPENDANT\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM0_REV\r
+ #define __CM0_REV 0x0000\r
+ #warning "__CM0_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 2\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M0 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[31];\r
+ __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[31];\r
+ __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[31];\r
+ __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[31];\r
+ uint32_t RESERVED4[64];\r
+ __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
+} NVIC_Type;\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ uint32_t RESERVED1;\r
+ __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
+ are only accessible over DAP and not via processor. Therefore\r
+ they are not covered by the Cortex-M0 header file.\r
+ @{\r
+ */\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M0 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
+/* The following MACROS handle generation of the register offset and byte masks */\r
+#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
+#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
+#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
+\r
+\r
+/** \brief Enable External Interrupt\r
+\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Disable External Interrupt\r
+\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Get Pending Interrupt\r
+\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
+}\r
+\r
+\r
+/** \brief Set Pending Interrupt\r
+\r
+ The function sets the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
+}\r
+\r
+\r
+/** \brief Clear Pending Interrupt\r
+\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+\r
+/** \brief Set Interrupt Priority\r
+\r
+ The function sets the priority of an interrupt.\r
+\r
+ \note The priority cannot be set for every core interrupt.\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+ else {\r
+ NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
+ (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
+}\r
+\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
+ else {\r
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/** \brief System Reset\r
+\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk);\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0)\r
+\r
+/** \brief System Tick Configuration\r
+\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+\r
+#endif /* __CORE_CM0_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.20\r
+ * @date 05. March 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constrant "l"\r
+ * Otherwise, use general registers, specified by constrant "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32 - op2)); \r
+}\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/*\r
+ FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+\r
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * FreeRTOS provides completely free yet professionally developed, *\r
+ * robust, strictly quality controlled, supported, and cross *\r
+ * platform software that has become a de facto standard. *\r
+ * *\r
+ * Help yourself get started quickly and support the FreeRTOS *\r
+ * project by purchasing a FreeRTOS tutorial book, reference *\r
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+ * *\r
+ * Thank you! *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ This file is part of the FreeRTOS distribution.\r
+\r
+ FreeRTOS is free software; you can redistribute it and/or modify it under\r
+ the terms of the GNU General Public License (version 2) as published by the\r
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+\r
+ >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+ >>! a combined work that includes FreeRTOS without being obliged to provide\r
+ >>! the source code for proprietary components outside of the FreeRTOS\r
+ >>! kernel.\r
+\r
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+ link: http://www.freertos.org/a00114.html\r
+\r
+ 1 tab == 4 spaces!\r
+\r
+ ***************************************************************************\r
+ * *\r
+ * Having a problem? Start by reading the FAQ "My application does *\r
+ * not run, what could be wrong?" *\r
+ * *\r
+ * http://www.FreeRTOS.org/FAQHelp.html *\r
+ * *\r
+ ***************************************************************************\r
+\r
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+ license and Real Time Engineers Ltd. contact details.\r
+\r
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+\r
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+ licenses offer ticketed support, indemnification and middleware.\r
+\r
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+ engineered and independently SIL3 certified version for use in safety and\r
+ mission critical applications that require provable dependability.\r
+\r
+ 1 tab == 4 spaces!\r
+*/\r
+\r
+ RSEG CODE:CODE(2)\r
+ thumb\r
+\r
+\r
+ EXTERN ulRegTest1LoopCounter\r
+ EXTERN ulRegTest2LoopCounter\r
+\r
+ PUBLIC vRegTest1Task\r
+ PUBLIC vRegTest2Task\r
+\r
+/*-----------------------------------------------------------*/\r
+vRegTest1Task\r
+\r
+ /* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #101\r
+ movs r2, #102\r
+ movs r3, #103\r
+ movs r4, #104\r
+ movs r5, #105\r
+ movs r6, #106\r
+ movs r7, #107\r
+ movs r0, #108\r
+ mov r8, r0\r
+ movs r0, #109\r
+ mov r9, r0\r
+ movs r0, #110\r
+ mov r10, r0\r
+ movs r0, #111\r
+ mov r11, r0\r
+ movs r0, #112\r
+ mov r12, r0\r
+ movs r0, #100\r
+\r
+reg1_loop\r
+ /* Repeatedly check that each register still contains the value written to\r
+ it when the task started. */\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ movs r0, #108\r
+ cmp r8, r0\r
+ bne reg1_error_loop\r
+ movs r0, #109\r
+ cmp r9, r0\r
+ bne reg1_error_loop\r
+ movs r0, #110\r
+ cmp r10, r0\r
+ bne reg1_error_loop\r
+ movs r0, #111\r
+ cmp r11, r0\r
+ bne reg1_error_loop\r
+ movs r0, #112\r
+ cmp r12, r0\r
+ bne reg1_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ /* Start again. */\r
+ movs r0, #100\r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ /* If this line is hit then there was an error in a core register value.\r
+ The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+\r
+\r
+\r
+vRegTest2Task\r
+\r
+ /* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #1\r
+ movs r2, #2\r
+ movs r3, #3\r
+ movs r4, #4\r
+ movs r5, #5\r
+ movs r6, #6\r
+ movs r7, #7\r
+ movs r0, #8\r
+ mov r8, r0\r
+ movs r0, #9\r
+ mov r9, r0\r
+ movs r0, #10\r
+ mov r10, r0\r
+ movs r0, #11\r
+ mov r11, r0\r
+ movs r0, #12\r
+ mov r12, r0\r
+ movs r0, #10\r
+\r
+reg2_loop\r
+ /* Repeatedly check that each register still contains the value written to\r
+ it when the task started. */\r
+ cmp r0, #10\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ movs r0, #8\r
+ cmp r8, r0\r
+ bne reg2_error_loop\r
+ movs r0, #9\r
+ cmp r9, r0\r
+ bne reg2_error_loop\r
+ movs r0, #10\r
+ cmp r10, r0\r
+ bne reg2_error_loop\r
+ movs r0, #11\r
+ cmp r11, r0\r
+ bne reg2_error_loop\r
+ movs r0, #12\r
+ cmp r12, r0\r
+ bne reg2_error_loop\r
+\r
+ /* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ /* Start again. */\r
+ movs r0, #10\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ ;/* If this line is hit then there was an error in a core register value.\r
+ ;The loop ensures the loop counter stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+\r
+ END\r
--- /dev/null
+;************************************************\r
+;*\r
+;* Part one of the system initialization code, contains low-level\r
+;* initialization, plain thumb variant.\r
+;*\r
+;* Copyright 2013 IAR Systems. All rights reserved.\r
+;*\r
+;* $Revision: 64600 $\r
+;*\r
+;******************* Version History **********************************************\r
+;\r
+; V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc\r
+;\r
+;**********************************************************************************\r
+;\r
+; The modules in this file are included in the libraries, and may be replaced\r
+; by any user-defined modules that define the PUBLIC symbol _program_start or\r
+; a user defined start symbol.\r
+; To override the cstartup defined in the library, simply add your modified\r
+; version to the workbench project.\r
+;\r
+; Cortex-M version\r
+;\r
+\r
+ MODULE ?cstartup\r
+#ifdef DAVE_CE\r
+#include "XMC1200_SCU.inc"\r
+#include "Device_Data.h"\r
+#else\r
+#define CLKVAL1_SSW 0x00000100\r
+#define CLKVAL2_SSW 0x00000000\r
+#endif\r
+\r
+ ;; Forward declaration of sections.\r
+ SECTION CSTACK:DATA:NOROOT(3)\r
+ SECTION .intvec:CODE:NOROOT(2)\r
+\r
+ EXTERN __iar_program_start\r
+ PUBLIC __vector_table\r
+\r
+ DATA\r
+__vector_table\r
+ DCD sfe(CSTACK)\r
+ DCD Reset_Handler ; Reset Handler\r
+ DCD 0 ; 0x8\r
+ DCD 0 ; 0xC\r
+ DCD CLKVAL1_SSW ; 0x10 CLK_VAL1 - (CLKCR default)\r
+ DCD CLKVAL2_SSW ; 0x14 CLK_VAL2 - (CGATCLR0 default)\r
+\r
+ SECTION .vect_table:CODE:ROOT(2)\r
+ THUMB\r
+ LDR R0,=HardFault_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=SVC_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=Undef_Handler\r
+ BX R0\r
+ LDR R0,=PendSV_Handler\r
+ BX R0\r
+ LDR R0,=SysTick_Handler\r
+ BX R0\r
+\r
+ ; External Interrupts\r
+ LDR R0,=SCU_0_IRQHandler ; Handler name for SR SCU_0\r
+ BX R0\r
+ LDR R0,=SCU_1_IRQHandler ; Handler name for SR SCU_1\r
+ BX R0\r
+ LDR R0,=SCU_2_IRQHandler ; Handler name for SR SCU_2\r
+ BX R0\r
+ LDR R0,=ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
+ BX R0\r
+ LDR R0,=ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
+ BX R0\r
+ LDR R0,=ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
+ BX R0\r
+ LDR R0,=ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
+ BX R0\r
+ LDR R0,=USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
+ BX R0\r
+ LDR R0,=USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
+ BX R0\r
+ LDR R0,=USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
+ BX R0\r
+ LDR R0,=USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
+ BX R0\r
+ LDR R0,=USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
+ BX R0\r
+ LDR R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
+ BX R0\r
+ LDR R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
+ BX R0\r
+ LDR R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
+ BX R0\r
+ LDR R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
+ BX R0\r
+ LDR R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
+ BX R0\r
+ LDR R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
+ BX R0\r
+ LDR R0,=CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
+ BX R0\r
+ LDR R0,=CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
+ BX R0\r
+ LDR R0,=CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
+ BX R0\r
+ LDR R0,=CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=Undef_Handler ; Not Available\r
+ BX R0\r
+ LDR R0,=LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
+ BX R0\r
+ LDR R0,=LEDTS1_0_IRQHandler ; Handler name for SR LEDTS1_0\r
+ BX R0\r
+ LDR R0,=BCCU0_0_IRQHandler ; Handler name for SR BCCU0_0\r
+ BX R0\r
+\r
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
+;;\r
+;; Default interrupt handlers.\r
+;;\r
+ EXTERN SystemInit\r
+ SECTION .text:CODE:NOROOT(2)\r
+\r
+ THUMB\r
+\r
+ PUBWEAK Reset_Handler\r
+ SECTION .text:CODE:REORDER(2)\r
+Reset_Handler\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+ LDR R0, =SystemInit_DAVE3\r
+ BLX R0\r
+ LDR R0, =__iar_program_start\r
+ BX R0\r
+\r
+ PUBWEAK Undef_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+Undef_Handler\r
+ B Undef_Handler\r
+\r
+\r
+ PUBWEAK HardFault_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+HardFault_Handler\r
+ B HardFault_Handler\r
+\r
+\r
+ PUBWEAK SVC_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SVC_Handler\r
+ B SVC_Handler\r
+\r
+\r
+ PUBWEAK PendSV_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+PendSV_Handler\r
+ B PendSV_Handler\r
+\r
+\r
+ PUBWEAK SysTick_Handler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SysTick_Handler\r
+ B SysTick_Handler\r
+\r
+\r
+ PUBWEAK SCU_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SCU_0_IRQHandler\r
+ B SCU_0_IRQHandler\r
+\r
+ PUBWEAK SCU_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SCU_1_IRQHandler\r
+ B SCU_1_IRQHandler\r
+\r
+\r
+ PUBWEAK SCU_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+SCU_2_IRQHandler\r
+ B SCU_2_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_0_IRQHandler\r
+ B ERU0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_1_IRQHandler\r
+ B ERU0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_2_IRQHandler\r
+ B ERU0_2_IRQHandler\r
+\r
+\r
+ PUBWEAK ERU0_3_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+ERU0_3_IRQHandler\r
+ B ERU0_3_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_0_IRQHandler\r
+ B USIC0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_1_IRQHandler\r
+ B USIC0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_2_IRQHandler\r
+ B USIC0_2_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_3_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_3_IRQHandler\r
+ B USIC0_3_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_4_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_4_IRQHandler\r
+ B USIC0_4_IRQHandler\r
+\r
+\r
+ PUBWEAK USIC0_5_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+USIC0_5_IRQHandler\r
+ B USIC0_5_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_C0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_C0_0_IRQHandler\r
+ B VADC0_C0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_C0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_C0_1_IRQHandler\r
+ B VADC0_C0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G0_0_IRQHandler\r
+ B VADC0_G0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G0_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G0_1_IRQHandler\r
+ B VADC0_G0_1_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G1_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G1_0_IRQHandler\r
+ B VADC0_G1_0_IRQHandler\r
+\r
+\r
+ PUBWEAK VADC0_G1_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+VADC0_G1_1_IRQHandler\r
+ B VADC0_G1_1_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_0_IRQHandler\r
+ B CCU40_0_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_1_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_1_IRQHandler\r
+ B CCU40_1_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_2_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_2_IRQHandler\r
+ B CCU40_2_IRQHandler\r
+\r
+\r
+ PUBWEAK CCU40_3_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+CCU40_3_IRQHandler\r
+ B CCU40_3_IRQHandler\r
+\r
+\r
+ PUBWEAK LEDTS0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+LEDTS0_0_IRQHandler\r
+ B LEDTS0_0_IRQHandler\r
+\r
+\r
+ PUBWEAK LEDTS1_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+LEDTS1_0_IRQHandler\r
+ B LEDTS1_0_IRQHandler\r
+\r
+\r
+ PUBWEAK BCCU0_0_IRQHandler\r
+ SECTION .text:CODE:REORDER:NOROOT(1)\r
+BCCU0_0_IRQHandler\r
+ B BCCU0_0_IRQHandler\r
+\r
+; Definition of the default weak SystemInit_DAVE3 function\r
+;If DAVE3 requires an extended SystemInit it will create its own version of\r
+;SystemInit_DAVE3 which overrides this weak definition. Example includes\r
+;setting up of external memory interfaces.\r
+\r
+ PUBWEAK SystemInit_DAVE3\r
+ SECTION .text:CODE:REORDER:NOROOT(2)\r
+SystemInit_DAVE3\r
+ NOP\r
+ BX LR\r
+\r
+;Decision function queried by CMSIS startup for Clock tree setup ======== */\r
+;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.\r
+;This decision routine defined here will always return TRUE.\r
+;When overridden by a definition defined in DAVE code engine, this routine\r
+;returns FALSE indicating that the code engine has performed the clock setup\r
+\r
+ PUBWEAK AllowClkInitByStartup\r
+ SECTION .text:CODE:REORDER:NOROOT(2)\r
+AllowClkInitByStartup\r
+ MOVS R0,#1\r
+ BX LR\r
+\r
+ END\r
--- /dev/null
+[BREAKPOINTS]\r
+ShowInfoWin = 1\r
+EnableFlashBP = 2\r
+BPDuringExecution = 0\r
+[CFI]\r
+CFISize = 0x00\r
+CFIAddr = 0x00\r
+[CPU]\r
+OverrideMemMap = 0\r
+AllowSimulation = 1\r
+ScriptFile=""\r
+[FLASH]\r
+CacheExcludeSize = 0x00\r
+CacheExcludeAddr = 0x00\r
+MinNumBytesFlashDL = 0\r
+SkipProgOnCRCMatch = 1\r
+VerifyDownload = 1\r
+AllowCaching = 1\r
+EnableFlashDL = 2\r
+Override = 0\r
+Device="UNSPECIFIED"\r
+[GENERAL]\r
+WorkRAMSize = 0x00\r
+WorkRAMAddr = 0x00\r
+RAMUsageLimit = 0x00\r
+[SWO]\r
+SWOLogFile=""\r
+[MEM]\r
+RdOverrideOrMask = 0x00\r
+RdOverrideAndMask = 0xFFFFFFFF\r
+RdOverrideAddr = 0xFFFFFFFF\r
+WrOverrideOrMask = 0x00\r
+WrOverrideAndMask = 0xFFFFFFFF\r
+WrOverrideAddr = 0xFFFFFFFF\r
--- /dev/null
+;/*\r
+; FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
+;\r
+; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * FreeRTOS provides completely free yet professionally developed, *\r
+; * robust, strictly quality controlled, supported, and cross *\r
+; * platform software that has become a de facto standard. *\r
+; * *\r
+; * Help yourself get started quickly and support the FreeRTOS *\r
+; * project by purchasing a FreeRTOS tutorial book, reference *\r
+; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
+; * *\r
+; * Thank you! *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; This file is part of the FreeRTOS distribution.\r
+;\r
+; FreeRTOS is free software; you can redistribute it and/or modify it under\r
+; the terms of the GNU General Public License (version 2) as published by the\r
+; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
+;\r
+; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
+; >>! a combined work that includes FreeRTOS without being obliged to provide\r
+; >>! the source code for proprietary components outside of the FreeRTOS\r
+; >>! kernel.\r
+;\r
+; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
+; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
+; link: http://www.freertos.org/a00114.html\r
+;\r
+; 1 tab == 4 spaces!\r
+;\r
+; ***************************************************************************\r
+; * *\r
+; * Having a problem? Start by reading the FAQ "My application does *\r
+; * not run, what could be wrong?" *\r
+; * *\r
+; * http://www.FreeRTOS.org/FAQHelp.html *\r
+; * *\r
+; ***************************************************************************\r
+;\r
+; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
+; license and Real Time Engineers Ltd. contact details.\r
+;\r
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
+; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
+; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
+;\r
+; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
+; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
+; licenses offer ticketed support, indemnification and middleware.\r
+;\r
+; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
+; engineered and independently SIL3 certified version for use in safety and\r
+; mission critical applications that require provable dependability.\r
+;\r
+; 1 tab == 4 spaces!\r
+;*/\r
+\r
+ PRESERVE8\r
+ THUMB\r
+ \r
+\r
+ IMPORT ulRegTest1LoopCounter\r
+ IMPORT ulRegTest2LoopCounter\r
+\r
+ EXTERN vPortYield ;////////////////////////////////////////////////////////////////////////////////////////\r
+\r
+ EXPORT vRegTest1Task\r
+ EXPORT vRegTest2Task\r
+ \r
+ AREA |.text|, CODE, READONLY\r
+\r
+;/*-----------------------------------------------------------*/\r
+vRegTest1Task PROC\r
+\r
+ ;/* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #101\r
+ movs r2, #102\r
+ movs r3, #103\r
+ movs r4, #104\r
+ movs r5, #105\r
+ movs r6, #106\r
+ movs r7, #107\r
+ movs r0, #108\r
+ mov r8, r0\r
+ movs r0, #109\r
+ mov r9, r0\r
+ movs r0, #110\r
+ mov r10, r0\r
+ movs r0, #111\r
+ mov r11, r0\r
+ movs r0, #112\r
+ mov r12, r0\r
+ movs r0, #100\r
+\r
+reg1_loop\r
+ ;/* Repeatedly check that each register still contains the value written to\r
+ ;it when the task started. */\r
+ cmp r0, #100\r
+ bne reg1_error_loop\r
+ cmp r1, #101\r
+ bne reg1_error_loop\r
+ cmp r2, #102\r
+ bne reg1_error_loop\r
+ cmp r3, #103\r
+ bne reg1_error_loop\r
+ cmp r4, #104\r
+ bne reg1_error_loop\r
+ cmp r5, #105\r
+ bne reg1_error_loop\r
+ cmp r6, #106\r
+ bne reg1_error_loop\r
+ cmp r7, #107\r
+ bne reg1_error_loop\r
+ movs r0, #108\r
+ cmp r8, r0\r
+ bne reg1_error_loop\r
+ movs r0, #109\r
+ cmp r9, r0\r
+ bne reg1_error_loop\r
+ movs r0, #110\r
+ cmp r10, r0\r
+ bne reg1_error_loop\r
+ movs r0, #111\r
+ cmp r11, r0\r
+ bne reg1_error_loop\r
+ movs r0, #112\r
+ cmp r12, r0\r
+ bne reg1_error_loop\r
+\r
+ ;/* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest1LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ ;/* Start again. */\r
+ movs r0, #100\r
+ \r
+ push {r0-r1}\r
+ bl vPortYield ;;///////////////////////////////////////////////////////////////////////////////////////////////////\r
+ pop {r0-r1}\r
+ \r
+ b reg1_loop\r
+\r
+reg1_error_loop\r
+ ;/* If this line is hit then there was an error in a core register value.\r
+ ;The loop ensures the loop counter stops incrementing. */\r
+ b reg1_error_loop\r
+ nop\r
+ ENDP\r
+\r
+\r
+\r
+vRegTest2Task PROC\r
+\r
+ ;/* Fill the core registers with known values. This is only done once. */\r
+ movs r1, #1\r
+ movs r2, #2\r
+ movs r3, #3\r
+ movs r4, #4\r
+ movs r5, #5\r
+ movs r6, #6\r
+ movs r7, #7\r
+ movs r0, #8\r
+ mov r8, r0\r
+ movs r0, #9\r
+ mov r9, r0\r
+ movs r0, #10\r
+ mov r10, r0\r
+ movs r0, #11\r
+ mov r11, r0\r
+ movs r0, #12\r
+ mov r12, r0\r
+ movs r0, #10\r
+\r
+reg2_loop\r
+ ;/* Repeatedly check that each register still contains the value written to\r
+ ;it when the task started. */\r
+ cmp r0, #10\r
+ bne reg2_error_loop\r
+ cmp r1, #1\r
+ bne reg2_error_loop\r
+ cmp r2, #2\r
+ bne reg2_error_loop\r
+ cmp r3, #3\r
+ bne reg2_error_loop\r
+ cmp r4, #4\r
+ bne reg2_error_loop\r
+ cmp r5, #5\r
+ bne reg2_error_loop\r
+ cmp r6, #6\r
+ bne reg2_error_loop\r
+ cmp r7, #7\r
+ bne reg2_error_loop\r
+ movs r0, #8\r
+ cmp r8, r0\r
+ bne reg2_error_loop\r
+ movs r0, #9\r
+ cmp r9, r0\r
+ bne reg2_error_loop\r
+ movs r0, #10\r
+ cmp r10, r0\r
+ bne reg2_error_loop\r
+ movs r0, #11\r
+ cmp r11, r0\r
+ bne reg2_error_loop\r
+ movs r0, #12\r
+ cmp r12, r0\r
+ bne reg2_error_loop\r
+\r
+ ;/* Everything passed, increment the loop counter. */\r
+ push { r1 }\r
+ ldr r0, =ulRegTest2LoopCounter\r
+ ldr r1, [r0]\r
+ adds r1, r1, #1\r
+ str r1, [r0]\r
+ pop { r1 }\r
+\r
+ ;/* Start again. */\r
+ movs r0, #10\r
+ b reg2_loop\r
+\r
+reg2_error_loop\r
+ ;/* If this line is hit then there was an error in a core register value.\r
+ ;The loop ensures the loop counter stops incrementing. */\r
+ b reg2_error_loop\r
+ nop\r
+ ENDP\r
+\r
+ END\r
--- /dev/null
+;*****************************************************************************/\r
+; * @file startup_XMC1300.s\r
+; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
+; * Infineon XMC1300 Device Series\r
+; * @version V1.00\r
+; * @date 21. Jan. 2013\r
+; *\r
+; * @note\r
+; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
+; *\r
+; * @par\r
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
+; * processor based microcontrollers. This file can be freely distributed\r
+; * within development tools that are supporting such ARM based processors.\r
+; *\r
+; * @par\r
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+; *\r
+; ******************************************************************************/\r
+\r
+\r
+;* <<< Use Configuration Wizard in Context Menu >>>\r
+\r
+; Amount of memory (in bytes) allocated for Stack\r
+; Tailor this value to your application needs\r
+; <h> Stack Configuration\r
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Stack_Size EQU 0x00000400\r
+\r
+ AREA STACK, NOINIT, READWRITE, ALIGN=3\r
+Stack_Mem SPACE Stack_Size\r
+__initial_sp\r
+\r
+\r
+; <h> Heap Configuration\r
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
+; </h>\r
+\r
+Heap_Size EQU 0x00000000\r
+\r
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
+__heap_base\r
+Heap_Mem SPACE Heap_Size\r
+__heap_limit\r
+\r
+; <h> Clock system handling by SSW\r
+; <h> CLK_VAL1 Configuration\r
+; <o0.0..7> FDIV Fractional Divider Selection\r
+; <o0.8..15> IDIV Divider Selection\r
+; <0=> Divider is bypassed\r
+; <1=> MCLK = 32 MHz\r
+; <2=> MCLK = 16 MHz\r
+; <3=> MCLK = 10.67 MHz\r
+; <4=> MCLK = 8 MHz\r
+; <254=> MCLK = 126 kHz\r
+; <255=> MCLK = 125.5 kHz\r
+; <o0.16> PCLKSEL PCLK Clock Select\r
+; <0=> PCLK = MCLK\r
+; <1=> PCLK = 2 x MCLK\r
+; <o0.17..19> RTCCLKSEL RTC Clock Select\r
+; <0=> 32.768kHz standby clock\r
+; <1=> 32.768kHz external clock from ERU0.IOUT0\r
+; <2=> 32.768kHz external clock from ACMP0.OUT\r
+; <3=> 32.768kHz external clock from ACMP1.OUT\r
+; <4=> 32.768kHz external clock from ACMP2.OUT\r
+; <5=> Reserved\r
+; <6=> Reserved\r
+; <7=> Reserved\r
+; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
+; </h>\r
+CLK_VAL1_Val EQU 0x00000100 ; 0xF0000000\r
+\r
+; <h> CLK_VAL2 Configuration\r
+; <o0.0> disable VADC and SHS Gating\r
+; <o0.1> disable CCU80 Gating\r
+; <o0.2> disable CCU40 Gating\r
+; <o0.3> disable USIC0 Gating\r
+; <o0.4> disable BCCU0 Gating\r
+; <o0.5> disable LEDTS0 Gating\r
+; <o0.6> disable LEDTS1 Gating\r
+; <o0.7> disable POSIF0 Gating\r
+; <o0.8> disable MATH Gating\r
+; <o0.9> disable WDT Gating\r
+; <o0.10> disable RTC Gating\r
+; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
+; </h>\r
+CLK_VAL2_Val EQU 0x00000000 ; 0xF0000000\r
+; </h>\r
+\r
+ PRESERVE8\r
+ THUMB\r
+\r
+;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
+;* Vector Table Mapped to Address 0 at Reset\r
+ AREA RESET, DATA, READONLY\r
+ EXPORT __Vectors\r
+ EXPORT __Vectors_End\r
+ EXPORT __Vectors_Size\r
+\r
+\r
+\r
+__Vectors\r
+ DCD __initial_sp ;* Top of Stack\r
+ DCD Reset_Handler ;* Reset Handler\r
+ DCD 0 ;* Not used\r
+ DCD 0 ;* Not Used\r
+ DCD CLK_VAL1_Val ;* CLK_VAL1\r
+ DCD CLK_VAL2_Val ;* CLK_VAL2\r
+__Vectors_End\r
+\r
+__Vectors_Size EQU __Vectors_End - __Vectors\r
+\r
+;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
+\r
+\r
+;* ================== START OF VECTOR ROUTINES ============================== */\r
+ AREA |.text|, CODE, READONLY\r
+\r
+;* Reset Handler\r
+Reset_Handler PROC\r
+ EXPORT Reset_Handler [WEAK]\r
+ IMPORT __main\r
+ IMPORT SystemInit\r
+\r
+ ;* C routines are likely to be called. Setup the stack now\r
+ LDR R0, =__initial_sp\r
+ MOV SP, R0\r
+\r
+ ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
+ ; The real veneers will be copied later from the scatter loader before reaching main.\r
+ ; This init code should handle an exception before the real veneers are copied.\r
+SRAM_BASE EQU 0x20000000\r
+VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
+\r
+ LDR R1, =SRAM_BASE\r
+ LDR R2, =VENEER_INIT_CODE \r
+ MOVS R0, #48 ; Veneer 0..47\r
+Init_Veneers\r
+ STR R2, [R1]\r
+ ADDS R1, #4\r
+ SUBS R0, R0, #1\r
+ BNE Init_Veneers\r
+\r
+\r
+ LDR R0, =SystemInit\r
+ BLX R0\r
+\r
+\r
+ ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
+ ; weakly defined here though for a potential override.\r
+\r
+ LDR R0, = SystemInit_DAVE3\r
+ BLX R0\r
+\r
+\r
+ LDR R0, =__main\r
+ BX R0\r
+\r
+\r
+ ALIGN\r
+ ENDP\r
+\r
+;* ========================================================================== */\r
+\r
+\r
+\r
+;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
+;* Default exception Handlers - Users may override this default functionality\r
+\r
+NMI_Handler PROC\r
+ EXPORT NMI_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+HardFault_Handler\\r
+ PROC\r
+ EXPORT HardFault_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SVC_Handler\\r
+ PROC\r
+ EXPORT SVC_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+PendSV_Handler\\r
+ PROC\r
+ EXPORT PendSV_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+SysTick_Handler\\r
+ PROC\r
+ EXPORT SysTick_Handler [WEAK]\r
+ B .\r
+ ENDP\r
+\r
+;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
+\r
+\r
+;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
+;* IRQ Handlers\r
+\r
+Default_Handler PROC\r
+ EXPORT SCU_0_IRQHandler [WEAK]\r
+ EXPORT SCU_1_IRQHandler [WEAK]\r
+ EXPORT SCU_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_0_IRQHandler [WEAK]\r
+ EXPORT ERU0_1_IRQHandler [WEAK]\r
+ EXPORT ERU0_2_IRQHandler [WEAK]\r
+ EXPORT ERU0_3_IRQHandler [WEAK]\r
+ EXPORT MATH0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_0_IRQHandler [WEAK]\r
+ EXPORT USIC0_1_IRQHandler [WEAK]\r
+ EXPORT USIC0_2_IRQHandler [WEAK]\r
+ EXPORT USIC0_3_IRQHandler [WEAK]\r
+ EXPORT USIC0_4_IRQHandler [WEAK]\r
+ EXPORT USIC0_5_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
+ EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_0_IRQHandler [WEAK]\r
+ EXPORT CCU40_1_IRQHandler [WEAK]\r
+ EXPORT CCU40_2_IRQHandler [WEAK]\r
+ EXPORT CCU40_3_IRQHandler [WEAK]\r
+ EXPORT CCU80_0_IRQHandler [WEAK]\r
+ EXPORT CCU80_1_IRQHandler [WEAK]\r
+ EXPORT POSIF0_0_IRQHandler [WEAK]\r
+ EXPORT POSIF0_1_IRQHandler [WEAK]\r
+ EXPORT LEDTS0_0_IRQHandler [WEAK]\r
+ EXPORT LEDTS1_0_IRQHandler [WEAK]\r
+ EXPORT BCCU0_0_IRQHandler [WEAK]\r
+\r
+SCU_0_IRQHandler\r
+SCU_1_IRQHandler\r
+SCU_2_IRQHandler\r
+ERU0_0_IRQHandler\r
+ERU0_1_IRQHandler\r
+ERU0_2_IRQHandler\r
+ERU0_3_IRQHandler\r
+MATH0_0_IRQHandler\r
+USIC0_0_IRQHandler\r
+USIC0_1_IRQHandler\r
+USIC0_2_IRQHandler\r
+USIC0_3_IRQHandler\r
+USIC0_4_IRQHandler\r
+USIC0_5_IRQHandler\r
+VADC0_C0_0_IRQHandler\r
+VADC0_C0_1_IRQHandler\r
+VADC0_G0_0_IRQHandler\r
+VADC0_G0_1_IRQHandler\r
+VADC0_G1_0_IRQHandler\r
+VADC0_G1_1_IRQHandler\r
+CCU40_0_IRQHandler\r
+CCU40_1_IRQHandler\r
+CCU40_2_IRQHandler\r
+CCU40_3_IRQHandler\r
+CCU80_0_IRQHandler\r
+CCU80_1_IRQHandler\r
+POSIF0_0_IRQHandler\r
+POSIF0_1_IRQHandler\r
+LEDTS0_0_IRQHandler\r
+LEDTS1_0_IRQHandler\r
+BCCU0_0_IRQHandler\r
+\r
+ B .\r
+\r
+ ENDP\r
+\r
+ ALIGN\r
+\r
+;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
+\r
+;* Definition of the default weak SystemInit_DAVE3 function.\r
+;* This function will be called by the CMSIS SystemInit function.\r
+;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
+;* which will overule this weak definition\r
+SystemInit_DAVE3 PROC\r
+ EXPORT SystemInit_DAVE3 [WEAK]\r
+ NOP\r
+ BX LR\r
+ ENDP\r
+\r
+;* Definition of the default weak DAVE3 function for clock App usage.\r
+;* AllowClkInitByStartup Handler */\r
+AllowClkInitByStartup PROC\r
+ EXPORT AllowClkInitByStartup [WEAK]\r
+ MOVS R0,#1\r
+ BX LR\r
+ ENDP\r
+\r
+\r
+;*******************************************************************************\r
+; User Stack and Heap initialization\r
+;*******************************************************************************\r
+ IF :DEF:__MICROLIB\r
+\r
+ EXPORT __initial_sp\r
+ EXPORT __heap_base\r
+ EXPORT __heap_limit\r
+\r
+ ELSE\r
+\r
+ IMPORT __use_two_region_memory\r
+ EXPORT __user_initial_stackheap\r
+\r
+__user_initial_stackheap\r
+\r
+ LDR R0, = Heap_Mem\r
+ LDR R1, =(Stack_Mem + Stack_Size)\r
+ LDR R2, = (Heap_Mem + Heap_Size)\r
+ LDR R3, = Stack_Mem\r
+ BX LR\r
+\r
+ ALIGN\r
+\r
+ ENDIF\r
+\r
+\r
+;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
+; Veneers are located to fix SRAM Address 0x2000'0000\r
+ AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
+\r
+; Each Veneer has exactly a lengs of 4 Byte\r
+\r
+ MACRO\r
+ STAYHERE $IrqNumber\r
+ LDR R0, =$IrqNumber\r
+ B .\r
+ MEND\r
+\r
+ MACRO\r
+ JUMPTO $Handler\r
+ LDR R0, =$Handler\r
+ BX R0\r
+ MEND\r
+\r
+ STAYHERE 0x0 ;* Reserved\r
+ STAYHERE 0x1 ;* Reserved \r
+ STAYHERE 0x2 ;* Reserved \r
+ JUMPTO HardFault_Handler ;* HardFault Veneer \r
+ STAYHERE 0x4 ;* Reserved \r
+ STAYHERE 0x5 ;* Reserved \r
+ STAYHERE 0x6 ;* Reserved \r
+ STAYHERE 0x7 ;* Reserved \r
+ STAYHERE 0x8 ;* Reserved \r
+ STAYHERE 0x9 ;* Reserved \r
+ STAYHERE 0xA ;* Reserved\r
+ JUMPTO SVC_Handler ;* SVC Veneer \r
+ STAYHERE 0xC ;* Reserved\r
+ STAYHERE 0xD ;* Reserved\r
+ JUMPTO PendSV_Handler ;* PendSV Veneer \r
+ JUMPTO SysTick_Handler ;* SysTick Veneer \r
+ JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
+ JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
+ JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
+ JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
+ JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
+ JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
+ JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
+ JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
+ STAYHERE 0x18 ;* Reserved\r
+ JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
+ JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
+ JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
+ JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
+ JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
+ JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
+ JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
+ JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
+ JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
+ JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
+ JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
+ JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
+ JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
+ JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
+ JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
+ JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
+ JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
+ JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
+ JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
+ JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
+ JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
+ JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
+\r
+ ALIGN\r
+\r
+;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
+\r
+ END\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1100.c\r
+ * @brief Device specific initialization for the XMC1100-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ */\r
+\r
+#include "system_XMC1100.h"\r
+#include <XMC1100.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1200.c\r
+ * @brief Device specific initialization for the XMC1200-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * *************************** Change history ********************************\r
+ * V1.2, 13 Dec 2012, PKB : Created change history table\r
+ */\r
+\r
+#include "System_XMC1200.h"\r
+#include <XMC1200.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
--- /dev/null
+/******************************************************************************\r
+ * @file system_XMC1300.c\r
+ * @brief Device specific initialization for the XMC1300-Series according \r
+ * to CMSIS\r
+ * @version V1.2\r
+ * @date 13 Dec 2012\r
+ *\r
+ * @note\r
+ * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
+\r
+ *\r
+ * @par\r
+ * Infineon Technologies AG (Infineon) is supplying this software for use with \r
+ * Infineon\92s microcontrollers.\r
+ * \r
+ * This file can be freely distributed within development tools that are \r
+ * supporting such microcontrollers.\r
+ * \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
+ * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+/*\r
+ * ************************** Change history *********************************\r
+ * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_\r
+ */\r
+\r
+#include "system_XMC1300.h"\r
+#include <XMC1300.h>\r
+\r
+/*---------------------------------------------------------------------------\r
+ Extern definitions \r
+ *--------------------------------------------------------------------------*/\r
+extern uint32_t AllowClkInitByStartup(void);\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Global defines\r
+ *----------------------------------------------------------------------------*/\r
+#define DCO_DCLK 64000000UL\r
+\r
+/*----------------------------------------------------------------------------\r
+ Clock Variable definitions\r
+ *----------------------------------------------------------------------------*/\r
+/*!< System Clock Frequency (Core Clock)*/\r
+uint32_t SystemCoreClock;\r
+\r
+\r
+/**\r
+ * @brief Setup the microcontroller system.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemInit(void)\r
+{ \r
+ /*\r
+ * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
+ * Clock app.\r
+ */ \r
+ if(AllowClkInitByStartup()){ \r
+ /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
+ /* ====== Default configuration ======= */\r
+ /*\r
+ * MCLK = DCO_DCLK\r
+ * PCLK = MCLK\r
+ * RTC CLK = Standby clock\r
+ */\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Update SystemCoreClock according to Clock Register Values\r
+ * @note - \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SystemCoreClockUpdate(void)\r
+{\r
+ uint32_t IDIV, CLKCR;\r
+\r
+ CLKCR = SCU_CLOCK -> CLKCR;\r
+ \r
+ IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
+ \r
+ if(IDIV)\r
+ {\r
+ SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
+ }\r
+ else\r
+ {\r
+ /* Divider bypassed */\r
+ SystemCoreClock = DCO_DCLK;\r
+ }\r
+}\r
+\r
</option>\r
<option>\r
<name>CCIncludePath2</name>\r
- <state>$PROJ_DIR$\Dave\Generated\inc\DAVESupport</state>\r
- <state>$PROJ_DIR$\..\..\source\include</state>\r
- <state>$PROJ_DIR$\..\..\source\portable\IAR\ARM_CM0</state>\r
<state>$PROJ_DIR$\.</state>\r
- <state>$PROJ_DIR$\System_IAR</state>\r
+ <state>$PROJ_DIR$\CMSIS</state>\r
<state>$PROJ_DIR$\..\common\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\include</state>\r
+ <state>$PROJ_DIR$\..\..\source\portable\IAR\ARM_CM0</state>\r
</option>\r
<option>\r
<name>CCStdIncCheck</name>\r
<data/>\r
</settings>\r
</configuration>\r
- <group>\r
- <name>System</name>\r
- <file>\r
- <name>$PROJ_DIR$\System_IAR\startup_XMC1200.s</name>\r
- </file>\r
- <file>\r
- <name>$PROJ_DIR$\system_XMC1200.c</name>\r
- </file>\r
- </group>\r
<group>\r
<name>Common Demo Source</name>\r
<file>\r
<name>$PROJ_DIR$\..\..\Source\timers.c</name>\r
</file>\r
</group>\r
+ <group>\r
+ <name>System</name>\r
+ <file>\r
+ <name>$PROJ_DIR$\IAR_Specific\startup_XMC1200.s</name>\r
+ </file>\r
+ <file>\r
+ <name>$PROJ_DIR$\system_XMC1200.c</name>\r
+ </file>\r
+ </group>\r
<file>\r
<name>$PROJ_DIR$\main-blinky.c</name>\r
</file>\r
<name>$PROJ_DIR$\ParTest_XMC1200.c</name>\r
</file>\r
<file>\r
- <name>$PROJ_DIR$\RegTest_IAR.s</name>\r
+ <name>$PROJ_DIR$\IAR_Specific\RegTest_IAR.s</name>\r
</file>\r
</project>\r
\r
<Group>
<GroupName>System</GroupName>
- <tvExp>1</tvExp>
+ <tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>0</TopLine>
- <CurrentLine>0</CurrentLine>
+ <TopLine>90</TopLine>
+ <CurrentLine>128</CurrentLine>
<bDave2>0</bDave2>
- <PathWithFileName>.\System_Keil\system_XMC1300.c</PathWithFileName>
- <FilenameWithoutPath>system_XMC1300.c</FilenameWithoutPath>
+ <PathWithFileName>.\system_XMC1200.c</PathWithFileName>
+ <FilenameWithoutPath>system_XMC1200.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
- <FileType>1</FileType>
+ <FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<TopLine>0</TopLine>
<CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
- <PathWithFileName>.\System_Keil\system_XMC1100.c</PathWithFileName>
- <FilenameWithoutPath>system_XMC1100.c</FilenameWithoutPath>
- <RteFlg>0</RteFlg>
- <bShared>0</bShared>
- </File>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>3</FileNumber>
- <FileType>2</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>120</TopLine>
- <CurrentLine>132</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\System_Keil\startup_XMC1300.s</PathWithFileName>
+ <PathWithFileName>.\Keil_Specific\startup_XMC1300.s</PathWithFileName>
<FilenameWithoutPath>startup_XMC1300.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
- <File>
- <GroupNumber>1</GroupNumber>
- <FileNumber>4</FileNumber>
- <FileType>1</FileType>
- <tvExp>0</tvExp>
- <Focus>0</Focus>
- <ColumnNumber>0</ColumnNumber>
- <tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>77</TopLine>
- <CurrentLine>128</CurrentLine>
- <bDave2>0</bDave2>
- <PathWithFileName>.\system_XMC1200.c</PathWithFileName>
- <FilenameWithoutPath>system_XMC1200.c</FilenameWithoutPath>
- <RteFlg>0</RteFlg>
- <bShared>0</bShared>
- </File>
</Group>
<Group>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>5</FileNumber>
+ <FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>6</FileNumber>
+ <FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>7</FileNumber>
+ <FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>8</FileNumber>
+ <FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>9</FileNumber>
+ <FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>2</GroupNumber>
- <FileNumber>10</FileNumber>
+ <FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<Group>
<GroupName>Demo App Source</GroupName>
- <tvExp>0</tvExp>
+ <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
- <FileNumber>11</FileNumber>
+ <FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>133</TopLine>
+ <TopLine>134</TopLine>
<CurrentLine>142</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName>
</File>
<File>
<GroupNumber>3</GroupNumber>
- <FileNumber>12</FileNumber>
+ <FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>3</GroupNumber>
- <FileNumber>13</FileNumber>
+ <FileNumber>11</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>3</GroupNumber>
- <FileNumber>14</FileNumber>
+ <FileNumber>12</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>3</GroupNumber>
- <FileNumber>15</FileNumber>
+ <FileNumber>13</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>3</GroupNumber>
- <FileNumber>16</FileNumber>
+ <FileNumber>14</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
- <TopLine>184</TopLine>
- <CurrentLine>192</CurrentLine>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
<bDave2>0</bDave2>
- <PathWithFileName>.\RegTest_Keil.s</PathWithFileName>
+ <PathWithFileName>.\Keil_Specific\RegTest_Keil.s</PathWithFileName>
<FilenameWithoutPath>RegTest_Keil.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
<Group>
<GroupName>Common Demo Tasks</GroupName>
- <tvExp>0</tvExp>
+ <tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>17</FileNumber>
+ <FileNumber>15</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>18</FileNumber>
+ <FileNumber>16</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>19</FileNumber>
+ <FileNumber>17</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
</File>
<File>
<GroupNumber>4</GroupNumber>
- <FileNumber>20</FileNumber>
+ <FileNumber>18</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<GroupName>System</GroupName>
<Files>
<File>
- <FileName>system_XMC1300.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\System_Keil\system_XMC1300.c</FilePath>
- </File>
- <File>
- <FileName>system_XMC1100.c</FileName>
+ <FileName>system_XMC1200.c</FileName>
<FileType>1</FileType>
- <FilePath>.\System_Keil\system_XMC1100.c</FilePath>
+ <FilePath>.\system_XMC1200.c</FilePath>
</File>
<File>
<FileName>startup_XMC1300.s</FileName>
<FileType>2</FileType>
- <FilePath>.\System_Keil\startup_XMC1300.s</FilePath>
- </File>
- <File>
- <FileName>system_XMC1200.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\system_XMC1200.c</FilePath>
+ <FilePath>.\Keil_Specific\startup_XMC1300.s</FilePath>
</File>
</Files>
</Group>
<File>
<FileName>RegTest_Keil.s</FileName>
<FileType>2</FileType>
- <FilePath>.\RegTest_Keil.s</FilePath>
+ <FilePath>.\Keil_Specific\RegTest_Keil.s</FilePath>
</File>
</Files>
</Group>
<MiscControls>--c99</MiscControls>
<Define></Define>
<Undefine></Undefine>
- <IncludePath>.;..\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include</IncludePath>
+ <IncludePath>.;..\Common\include;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;.\CMSIS</IncludePath>
</VariousControls>
</Cads>
<Aads>
<GroupName>System</GroupName>
<Files>
<File>
- <FileName>system_XMC1300.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\System_Keil\system_XMC1300.c</FilePath>
- <FileOption>
- <CommonProperty>
- <UseCPPCompiler>2</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>0</IncludeInBuild>
- <AlwaysBuild>2</AlwaysBuild>
- <GenerateAssemblyFile>2</GenerateAssemblyFile>
- <AssembleAssemblyFile>2</AssembleAssemblyFile>
- <PublicsOnly>2</PublicsOnly>
- <StopOnExitCode>11</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- </CommonProperty>
- <FileArmAds>
- <Cads>
- <interw>2</interw>
- <Optim>0</Optim>
- <oTime>2</oTime>
- <SplitLS>2</SplitLS>
- <OneElfS>2</OneElfS>
- <Strict>2</Strict>
- <EnumInt>2</EnumInt>
- <PlainCh>2</PlainCh>
- <Ropi>2</Ropi>
- <Rwpi>2</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>2</uThumb>
- <uSurpInc>2</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Cads>
- </FileArmAds>
- </FileOption>
- </File>
- <File>
- <FileName>system_XMC1100.c</FileName>
+ <FileName>system_XMC1200.c</FileName>
<FileType>1</FileType>
- <FilePath>.\System_Keil\system_XMC1100.c</FilePath>
- <FileOption>
- <CommonProperty>
- <UseCPPCompiler>2</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>0</IncludeInBuild>
- <AlwaysBuild>2</AlwaysBuild>
- <GenerateAssemblyFile>2</GenerateAssemblyFile>
- <AssembleAssemblyFile>2</AssembleAssemblyFile>
- <PublicsOnly>2</PublicsOnly>
- <StopOnExitCode>11</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- </CommonProperty>
- <FileArmAds>
- <Cads>
- <interw>2</interw>
- <Optim>0</Optim>
- <oTime>2</oTime>
- <SplitLS>2</SplitLS>
- <OneElfS>2</OneElfS>
- <Strict>2</Strict>
- <EnumInt>2</EnumInt>
- <PlainCh>2</PlainCh>
- <Ropi>2</Ropi>
- <Rwpi>2</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>2</uThumb>
- <uSurpInc>2</uSurpInc>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Cads>
- </FileArmAds>
- </FileOption>
+ <FilePath>.\system_XMC1200.c</FilePath>
</File>
<File>
<FileName>startup_XMC1300.s</FileName>
<FileType>2</FileType>
- <FilePath>.\System_Keil\startup_XMC1300.s</FilePath>
- </File>
- <File>
- <FileName>system_XMC1200.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\system_XMC1200.c</FilePath>
+ <FilePath>.\Keil_Specific\startup_XMC1300.s</FilePath>
</File>
</Files>
</Group>
<File>
<FileName>RegTest_Keil.s</FileName>
<FileType>2</FileType>
- <FilePath>.\RegTest_Keil.s</FilePath>
+ <FilePath>.\Keil_Specific\RegTest_Keil.s</FilePath>
</File>
</Files>
</Group>
+++ /dev/null
-/*\r
- FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-\r
- VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-\r
- ***************************************************************************\r
- * *\r
- * FreeRTOS provides completely free yet professionally developed, *\r
- * robust, strictly quality controlled, supported, and cross *\r
- * platform software that has become a de facto standard. *\r
- * *\r
- * Help yourself get started quickly and support the FreeRTOS *\r
- * project by purchasing a FreeRTOS tutorial book, reference *\r
- * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
- * *\r
- * Thank you! *\r
- * *\r
- ***************************************************************************\r
-\r
- This file is part of the FreeRTOS distribution.\r
-\r
- FreeRTOS is free software; you can redistribute it and/or modify it under\r
- the terms of the GNU General Public License (version 2) as published by the\r
- Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-\r
- >>! NOTE: The modification to the GPL is included to allow you to distribute\r
- >>! a combined work that includes FreeRTOS without being obliged to provide\r
- >>! the source code for proprietary components outside of the FreeRTOS\r
- >>! kernel.\r
-\r
- FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
- FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
- link: http://www.freertos.org/a00114.html\r
-\r
- 1 tab == 4 spaces!\r
-\r
- ***************************************************************************\r
- * *\r
- * Having a problem? Start by reading the FAQ "My application does *\r
- * not run, what could be wrong?" *\r
- * *\r
- * http://www.FreeRTOS.org/FAQHelp.html *\r
- * *\r
- ***************************************************************************\r
-\r
- http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
- license and Real Time Engineers Ltd. contact details.\r
-\r
- http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
- including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
- compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-\r
- http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
- Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
- licenses offer ticketed support, indemnification and middleware.\r
-\r
- http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
- engineered and independently SIL3 certified version for use in safety and\r
- mission critical applications that require provable dependability.\r
-\r
- 1 tab == 4 spaces!\r
-*/\r
-\r
- RSEG CODE:CODE(2)\r
- thumb\r
-\r
-\r
- EXTERN ulRegTest1LoopCounter\r
- EXTERN ulRegTest2LoopCounter\r
-\r
- PUBLIC vRegTest1Task\r
- PUBLIC vRegTest2Task\r
-\r
-/*-----------------------------------------------------------*/\r
-vRegTest1Task\r
-\r
- /* Fill the core registers with known values. This is only done once. */\r
- movs r1, #101\r
- movs r2, #102\r
- movs r3, #103\r
- movs r4, #104\r
- movs r5, #105\r
- movs r6, #106\r
- movs r7, #107\r
- movs r0, #108\r
- mov r8, r0\r
- movs r0, #109\r
- mov r9, r0\r
- movs r0, #110\r
- mov r10, r0\r
- movs r0, #111\r
- mov r11, r0\r
- movs r0, #112\r
- mov r12, r0\r
- movs r0, #100\r
-\r
-reg1_loop\r
- /* Repeatedly check that each register still contains the value written to\r
- it when the task started. */\r
- cmp r0, #100\r
- bne reg1_error_loop\r
- cmp r1, #101\r
- bne reg1_error_loop\r
- cmp r2, #102\r
- bne reg1_error_loop\r
- cmp r3, #103\r
- bne reg1_error_loop\r
- cmp r4, #104\r
- bne reg1_error_loop\r
- cmp r5, #105\r
- bne reg1_error_loop\r
- cmp r6, #106\r
- bne reg1_error_loop\r
- cmp r7, #107\r
- bne reg1_error_loop\r
- movs r0, #108\r
- cmp r8, r0\r
- bne reg1_error_loop\r
- movs r0, #109\r
- cmp r9, r0\r
- bne reg1_error_loop\r
- movs r0, #110\r
- cmp r10, r0\r
- bne reg1_error_loop\r
- movs r0, #111\r
- cmp r11, r0\r
- bne reg1_error_loop\r
- movs r0, #112\r
- cmp r12, r0\r
- bne reg1_error_loop\r
-\r
- /* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest1LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- /* Start again. */\r
- movs r0, #100\r
- b reg1_loop\r
-\r
-reg1_error_loop\r
- /* If this line is hit then there was an error in a core register value.\r
- The loop ensures the loop counter stops incrementing. */\r
- b reg1_error_loop\r
- nop\r
-\r
-\r
-\r
-vRegTest2Task\r
-\r
- /* Fill the core registers with known values. This is only done once. */\r
- movs r1, #1\r
- movs r2, #2\r
- movs r3, #3\r
- movs r4, #4\r
- movs r5, #5\r
- movs r6, #6\r
- movs r7, #7\r
- movs r0, #8\r
- mov r8, r0\r
- movs r0, #9\r
- mov r9, r0\r
- movs r0, #10\r
- mov r10, r0\r
- movs r0, #11\r
- mov r11, r0\r
- movs r0, #12\r
- mov r12, r0\r
- movs r0, #10\r
-\r
-reg2_loop\r
- /* Repeatedly check that each register still contains the value written to\r
- it when the task started. */\r
- cmp r0, #10\r
- bne reg2_error_loop\r
- cmp r1, #1\r
- bne reg2_error_loop\r
- cmp r2, #2\r
- bne reg2_error_loop\r
- cmp r3, #3\r
- bne reg2_error_loop\r
- cmp r4, #4\r
- bne reg2_error_loop\r
- cmp r5, #5\r
- bne reg2_error_loop\r
- cmp r6, #6\r
- bne reg2_error_loop\r
- cmp r7, #7\r
- bne reg2_error_loop\r
- movs r0, #8\r
- cmp r8, r0\r
- bne reg2_error_loop\r
- movs r0, #9\r
- cmp r9, r0\r
- bne reg2_error_loop\r
- movs r0, #10\r
- cmp r10, r0\r
- bne reg2_error_loop\r
- movs r0, #11\r
- cmp r11, r0\r
- bne reg2_error_loop\r
- movs r0, #12\r
- cmp r12, r0\r
- bne reg2_error_loop\r
-\r
- /* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest2LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- /* Start again. */\r
- movs r0, #10\r
- b reg2_loop\r
-\r
-reg2_error_loop\r
- ;/* If this line is hit then there was an error in a core register value.\r
- ;The loop ensures the loop counter stops incrementing. */\r
- b reg2_error_loop\r
- nop\r
-\r
- END\r
+++ /dev/null
-;/*\r
-; FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
-;\r
-; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * FreeRTOS provides completely free yet professionally developed, *\r
-; * robust, strictly quality controlled, supported, and cross *\r
-; * platform software that has become a de facto standard. *\r
-; * *\r
-; * Help yourself get started quickly and support the FreeRTOS *\r
-; * project by purchasing a FreeRTOS tutorial book, reference *\r
-; * manual, or both from: http://www.FreeRTOS.org/Documentation *\r
-; * *\r
-; * Thank you! *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; This file is part of the FreeRTOS distribution.\r
-;\r
-; FreeRTOS is free software; you can redistribute it and/or modify it under\r
-; the terms of the GNU General Public License (version 2) as published by the\r
-; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
-;\r
-; >>! NOTE: The modification to the GPL is included to allow you to distribute\r
-; >>! a combined work that includes FreeRTOS without being obliged to provide\r
-; >>! the source code for proprietary components outside of the FreeRTOS\r
-; >>! kernel.\r
-;\r
-; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
-; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
-; FOR A PARTICULAR PURPOSE. Full license text is available from the following\r
-; link: http://www.freertos.org/a00114.html\r
-;\r
-; 1 tab == 4 spaces!\r
-;\r
-; ***************************************************************************\r
-; * *\r
-; * Having a problem? Start by reading the FAQ "My application does *\r
-; * not run, what could be wrong?" *\r
-; * *\r
-; * http://www.FreeRTOS.org/FAQHelp.html *\r
-; * *\r
-; ***************************************************************************\r
-;\r
-; http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
-; license and Real Time Engineers Ltd. contact details.\r
-;\r
-; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
-; including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
-; compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
-;\r
-; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
-; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS\r
-; licenses offer ticketed support, indemnification and middleware.\r
-;\r
-; http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
-; engineered and independently SIL3 certified version for use in safety and\r
-; mission critical applications that require provable dependability.\r
-;\r
-; 1 tab == 4 spaces!\r
-;*/\r
-\r
- PRESERVE8\r
- THUMB\r
- \r
-\r
- IMPORT ulRegTest1LoopCounter\r
- IMPORT ulRegTest2LoopCounter\r
-\r
- EXTERN vPortYield ;////////////////////////////////////////////////////////////////////////////////////////\r
-\r
- EXPORT vRegTest1Task\r
- EXPORT vRegTest2Task\r
- \r
- AREA |.text|, CODE, READONLY\r
-\r
-;/*-----------------------------------------------------------*/\r
-vRegTest1Task PROC\r
-\r
- ;/* Fill the core registers with known values. This is only done once. */\r
- movs r1, #101\r
- movs r2, #102\r
- movs r3, #103\r
- movs r4, #104\r
- movs r5, #105\r
- movs r6, #106\r
- movs r7, #107\r
- movs r0, #108\r
- mov r8, r0\r
- movs r0, #109\r
- mov r9, r0\r
- movs r0, #110\r
- mov r10, r0\r
- movs r0, #111\r
- mov r11, r0\r
- movs r0, #112\r
- mov r12, r0\r
- movs r0, #100\r
-\r
-reg1_loop\r
- ;/* Repeatedly check that each register still contains the value written to\r
- ;it when the task started. */\r
- cmp r0, #100\r
- bne reg1_error_loop\r
- cmp r1, #101\r
- bne reg1_error_loop\r
- cmp r2, #102\r
- bne reg1_error_loop\r
- cmp r3, #103\r
- bne reg1_error_loop\r
- cmp r4, #104\r
- bne reg1_error_loop\r
- cmp r5, #105\r
- bne reg1_error_loop\r
- cmp r6, #106\r
- bne reg1_error_loop\r
- cmp r7, #107\r
- bne reg1_error_loop\r
- movs r0, #108\r
- cmp r8, r0\r
- bne reg1_error_loop\r
- movs r0, #109\r
- cmp r9, r0\r
- bne reg1_error_loop\r
- movs r0, #110\r
- cmp r10, r0\r
- bne reg1_error_loop\r
- movs r0, #111\r
- cmp r11, r0\r
- bne reg1_error_loop\r
- movs r0, #112\r
- cmp r12, r0\r
- bne reg1_error_loop\r
-\r
- ;/* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest1LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- ;/* Start again. */\r
- movs r0, #100\r
- \r
- push {r0-r1}\r
- bl vPortYield ;;///////////////////////////////////////////////////////////////////////////////////////////////////\r
- pop {r0-r1}\r
- \r
- b reg1_loop\r
-\r
-reg1_error_loop\r
- ;/* If this line is hit then there was an error in a core register value.\r
- ;The loop ensures the loop counter stops incrementing. */\r
- b reg1_error_loop\r
- nop\r
- ENDP\r
-\r
-\r
-\r
-vRegTest2Task PROC\r
-\r
- ;/* Fill the core registers with known values. This is only done once. */\r
- movs r1, #1\r
- movs r2, #2\r
- movs r3, #3\r
- movs r4, #4\r
- movs r5, #5\r
- movs r6, #6\r
- movs r7, #7\r
- movs r0, #8\r
- mov r8, r0\r
- movs r0, #9\r
- mov r9, r0\r
- movs r0, #10\r
- mov r10, r0\r
- movs r0, #11\r
- mov r11, r0\r
- movs r0, #12\r
- mov r12, r0\r
- movs r0, #10\r
-\r
-reg2_loop\r
- ;/* Repeatedly check that each register still contains the value written to\r
- ;it when the task started. */\r
- cmp r0, #10\r
- bne reg2_error_loop\r
- cmp r1, #1\r
- bne reg2_error_loop\r
- cmp r2, #2\r
- bne reg2_error_loop\r
- cmp r3, #3\r
- bne reg2_error_loop\r
- cmp r4, #4\r
- bne reg2_error_loop\r
- cmp r5, #5\r
- bne reg2_error_loop\r
- cmp r6, #6\r
- bne reg2_error_loop\r
- cmp r7, #7\r
- bne reg2_error_loop\r
- movs r0, #8\r
- cmp r8, r0\r
- bne reg2_error_loop\r
- movs r0, #9\r
- cmp r9, r0\r
- bne reg2_error_loop\r
- movs r0, #10\r
- cmp r10, r0\r
- bne reg2_error_loop\r
- movs r0, #11\r
- cmp r11, r0\r
- bne reg2_error_loop\r
- movs r0, #12\r
- cmp r12, r0\r
- bne reg2_error_loop\r
-\r
- ;/* Everything passed, increment the loop counter. */\r
- push { r1 }\r
- ldr r0, =ulRegTest2LoopCounter\r
- ldr r1, [r0]\r
- adds r1, r1, #1\r
- str r1, [r0]\r
- pop { r1 }\r
-\r
- ;/* Start again. */\r
- movs r0, #10\r
- b reg2_loop\r
-\r
-reg2_error_loop\r
- ;/* If this line is hit then there was an error in a core register value.\r
- ;The loop ensures the loop counter stops incrementing. */\r
- b reg2_error_loop\r
- nop\r
- ENDP\r
-\r
- END\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm0.h\r
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#endif\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-#ifndef __CORE_CM0_H_GENERIC\r
-#define __CORE_CM0_H_GENERIC\r
-\r
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
- CMSIS violates the following MISRA-C:2004 rules:\r
-\r
- \li Required Rule 8.5, object/function definition in header file.<br>\r
- Function definitions in header files are used to allow 'inlining'.\r
-\r
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
- Unions are used for effective representation of core registers.\r
-\r
- \li Advisory Rule 19.7, Function-like macro defined.<br>\r
- Function-like macros are used to allow more efficient code.\r
- */\r
-\r
-\r
-/*******************************************************************************\r
- * CMSIS definitions\r
- ******************************************************************************/\r
-/** \ingroup Cortex_M0\r
- @{\r
- */\r
-\r
-/* CMSIS CM0 definitions */\r
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \\r
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
- #define __STATIC_INLINE static __inline\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
- #define __STATIC_INLINE static inline\r
-\r
-#endif\r
-\r
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
-*/\r
-#define __FPU_USED 0\r
-\r
-#if defined ( __CC_ARM )\r
- #if defined __TARGET_FPU_VFP\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __ICCARM__ )\r
- #if defined __ARMVFP__\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __TASKING__ )\r
- #if defined __FPU_VFP__\r
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-#endif\r
-\r
-#include <stdint.h> /* standard types definitions */\r
-#include <core_cmInstr.h> /* Core Instruction Access */\r
-#include <core_cmFunc.h> /* Core Function Access */\r
-\r
-#endif /* __CORE_CM0_H_GENERIC */\r
-\r
-#ifndef __CMSIS_GENERIC\r
-\r
-#ifndef __CORE_CM0_H_DEPENDANT\r
-#define __CORE_CM0_H_DEPENDANT\r
-\r
-/* check device defines and use defaults */\r
-#if defined __CHECK_DEVICE_DEFINES\r
- #ifndef __CM0_REV\r
- #define __CM0_REV 0x0000\r
- #warning "__CM0_REV not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 2\r
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
- #endif\r
-\r
- #ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
- #endif\r
-#endif\r
-\r
-/* IO definitions (access restrictions to peripheral registers) */\r
-/**\r
- \defgroup CMSIS_glob_defs CMSIS Global Defines\r
-\r
- <strong>IO Type Qualifiers</strong> are used\r
- \li to specify the access to peripheral variables.\r
- \li for automatic generation of peripheral register debug information.\r
-*/\r
-#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
-#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
-\r
-/*@} end of group Cortex_M0 */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- Core Register contain:\r
- - Core Register\r
- - Core NVIC Register\r
- - Core SCB Register\r
- - Core SysTick Register\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
-*/\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
- @{\r
- */\r
-\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} APSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} IPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} xPSR_Type;\r
-\r
-\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
- */\r
-typedef union\r
-{\r
- struct\r
- {\r
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
-} CONTROL_Type;\r
-\r
-/*@} end of group CMSIS_CORE */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[31];\r
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[31];\r
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[31];\r
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[31];\r
- uint32_t RESERVED4[64];\r
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */\r
-} NVIC_Type;\r
-\r
-/*@} end of group CMSIS_NVIC */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Control Block (SCB).\r
- */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- uint32_t RESERVED0;\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- uint32_t RESERVED1;\r
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
-} SCB_Type;\r
-\r
-/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
-\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
-\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
-\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
-\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
-\r
-/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
-\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
-\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
-\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
-\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
-\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
-\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
-\r
-/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
-\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
-\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
-\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
-\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
-\r
-/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
-\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
-\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
-\r
-/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
-\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
-\r
-/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
-\r
-/*@} end of group CMSIS_SCB */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
- @{\r
- */\r
-\r
-/** \brief Structure type to access the System Timer (SysTick).\r
- */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
-\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
-\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
-\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
-\r
-/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
-\r
-/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
-\r
-/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
-\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
-\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-\r
-/*@} end of group CMSIS_SysTick */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)\r
- are only accessible over DAP and not via processor. Therefore\r
- they are not covered by the Cortex-M0 header file.\r
- @{\r
- */\r
-/*@} end of group CMSIS_CoreDebug */\r
-\r
-\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
- @{\r
- */\r
-\r
-/* Memory mapping of Cortex-M0 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
-\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-\r
-\r
-/*@} */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- Core Function Interface contains:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Register Access Functions\r
- ******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
-*/\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
- */\r
-\r
-/* Interrupt Priorities are WORD accessible only under ARMv6M */\r
-/* The following MACROS handle generation of the register offset and byte masks */\r
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )\r
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )\r
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )\r
-\r
-\r
-/** \brief Enable External Interrupt\r
-\r
- The function enables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
-}\r
-\r
-\r
-/** \brief Disable External Interrupt\r
-\r
- The function disables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
-}\r
-\r
-\r
-/** \brief Get Pending Interrupt\r
-\r
- The function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\r
-}\r
-\r
-\r
-/** \brief Set Pending Interrupt\r
-\r
- The function sets the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));\r
-}\r
-\r
-\r
-/** \brief Clear Pending Interrupt\r
-\r
- The function clears the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
- */\r
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-\r
-/** \brief Set Interrupt Priority\r
-\r
- The function sets the priority of an interrupt.\r
-\r
- \note The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
- */\r
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
- else {\r
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |\r
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }\r
-}\r
-\r
-\r
-/** \brief Get Interrupt Priority\r
-\r
- The function reads the priority of an interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
-\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented\r
- priority bits of the microcontroller.\r
- */\r
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */\r
- else {\r
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/** \brief System Reset\r
-\r
- The function initiates a system reset request to reset the MCU.\r
- */\r
-__STATIC_INLINE void NVIC_SystemReset(void)\r
-{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- SCB_AIRCR_SYSRESETREQ_Msk);\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
-}\r
-\r
-/*@} end of CMSIS_Core_NVICFunctions */\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
- @{\r
- */\r
-\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts.\r
-\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
-\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
-\r
- */\r
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
- SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_SysTickFunctions */\r
-\r
-\r
-\r
-\r
-#endif /* __CORE_CM0_H_DEPENDANT */\r
-\r
-#endif /* __CMSIS_GENERIC */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmFunc.h\r
- * @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CORE_CMFUNC_H\r
-#define __CORE_CMFUNC_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/** \brief Enable IRQ Interrupts\r
-\r
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable IRQ Interrupts\r
-\r
- This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- uint32_t result;\r
-\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-#endif /* __CORE_CMFUNC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmInstr.h\r
- * @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V3.20\r
- * @date 05. March 2013\r
- *\r
- * @note\r
- *\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CORE_CMINSTR_H\r
-#define __CORE_CMINSTR_H\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-#define __ISB() __isb(0xF)\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __dsb(0xF)\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __dmb(0xF)\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __RBIT __rbit\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constrant "l"\r
- * Otherwise, use general registers, specified by constrant "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb");\r
-}\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb");\r
-}\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb");\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32 - op2)); \r
-}\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-#endif /* __CORE_CMINSTR_H */\r
+++ /dev/null
-;************************************************\r
-;*\r
-;* Part one of the system initialization code, contains low-level\r
-;* initialization, plain thumb variant.\r
-;*\r
-;* Copyright 2013 IAR Systems. All rights reserved.\r
-;*\r
-;* $Revision: 64600 $\r
-;*\r
-;******************* Version History **********************************************\r
-;\r
-; V6, May, 16,2013 TYS:a) Add XMC1200_SCU.inc\r
-;\r
-;**********************************************************************************\r
-;\r
-; The modules in this file are included in the libraries, and may be replaced\r
-; by any user-defined modules that define the PUBLIC symbol _program_start or\r
-; a user defined start symbol.\r
-; To override the cstartup defined in the library, simply add your modified\r
-; version to the workbench project.\r
-;\r
-; Cortex-M version\r
-;\r
-\r
- MODULE ?cstartup\r
-#ifdef DAVE_CE\r
-#include "XMC1200_SCU.inc"\r
-#include "Device_Data.h"\r
-#else\r
-#define CLKVAL1_SSW 0x00000100\r
-#define CLKVAL2_SSW 0x00000000\r
-#endif\r
-\r
- ;; Forward declaration of sections.\r
- SECTION CSTACK:DATA:NOROOT(3)\r
- SECTION .intvec:CODE:NOROOT(2)\r
-\r
- EXTERN __iar_program_start\r
- PUBLIC __vector_table\r
-\r
- DATA\r
-__vector_table\r
- DCD sfe(CSTACK)\r
- DCD Reset_Handler ; Reset Handler\r
- DCD 0 ; 0x8\r
- DCD 0 ; 0xC\r
- DCD CLKVAL1_SSW ; 0x10 CLK_VAL1 - (CLKCR default)\r
- DCD CLKVAL2_SSW ; 0x14 CLK_VAL2 - (CGATCLR0 default)\r
-\r
- SECTION .vect_table:CODE:ROOT(2)\r
- THUMB\r
- LDR R0,=HardFault_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=SVC_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=Undef_Handler\r
- BX R0\r
- LDR R0,=PendSV_Handler\r
- BX R0\r
- LDR R0,=SysTick_Handler\r
- BX R0\r
-\r
- ; External Interrupts\r
- LDR R0,=SCU_0_IRQHandler ; Handler name for SR SCU_0\r
- BX R0\r
- LDR R0,=SCU_1_IRQHandler ; Handler name for SR SCU_1\r
- BX R0\r
- LDR R0,=SCU_2_IRQHandler ; Handler name for SR SCU_2\r
- BX R0\r
- LDR R0,=ERU0_0_IRQHandler ; Handler name for SR ERU0_0\r
- BX R0\r
- LDR R0,=ERU0_1_IRQHandler ; Handler name for SR ERU0_1\r
- BX R0\r
- LDR R0,=ERU0_2_IRQHandler ; Handler name for SR ERU0_2\r
- BX R0\r
- LDR R0,=ERU0_3_IRQHandler ; Handler name for SR ERU0_3\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=USIC0_0_IRQHandler ; Handler name for SR USIC0_0\r
- BX R0\r
- LDR R0,=USIC0_1_IRQHandler ; Handler name for SR USIC0_1\r
- BX R0\r
- LDR R0,=USIC0_2_IRQHandler ; Handler name for SR USIC0_2\r
- BX R0\r
- LDR R0,=USIC0_3_IRQHandler ; Handler name for SR USIC0_3\r
- BX R0\r
- LDR R0,=USIC0_4_IRQHandler ; Handler name for SR USIC0_4\r
- BX R0\r
- LDR R0,=USIC0_5_IRQHandler ; Handler name for SR USIC0_5\r
- BX R0\r
- LDR R0,=VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0\r
- BX R0\r
- LDR R0,=VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1\r
- BX R0\r
- LDR R0,=VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0\r
- BX R0\r
- LDR R0,=VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1\r
- BX R0\r
- LDR R0,=VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0\r
- BX R0\r
- LDR R0,=VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1\r
- BX R0\r
- LDR R0,=CCU40_0_IRQHandler ; Handler name for SR CCU40_0\r
- BX R0\r
- LDR R0,=CCU40_1_IRQHandler ; Handler name for SR CCU40_1\r
- BX R0\r
- LDR R0,=CCU40_2_IRQHandler ; Handler name for SR CCU40_2\r
- BX R0\r
- LDR R0,=CCU40_3_IRQHandler ; Handler name for SR CCU40_3\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=Undef_Handler ; Not Available\r
- BX R0\r
- LDR R0,=LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0\r
- BX R0\r
- LDR R0,=LEDTS1_0_IRQHandler ; Handler name for SR LEDTS1_0\r
- BX R0\r
- LDR R0,=BCCU0_0_IRQHandler ; Handler name for SR BCCU0_0\r
- BX R0\r
-\r
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
-;;\r
-;; Default interrupt handlers.\r
-;;\r
- EXTERN SystemInit\r
- SECTION .text:CODE:NOROOT(2)\r
-\r
- THUMB\r
-\r
- PUBWEAK Reset_Handler\r
- SECTION .text:CODE:REORDER(2)\r
-Reset_Handler\r
- LDR R0, =SystemInit\r
- BLX R0\r
- LDR R0, =SystemInit_DAVE3\r
- BLX R0\r
- LDR R0, =__iar_program_start\r
- BX R0\r
-\r
- PUBWEAK Undef_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-Undef_Handler\r
- B Undef_Handler\r
-\r
-\r
- PUBWEAK HardFault_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-HardFault_Handler\r
- B HardFault_Handler\r
-\r
-\r
- PUBWEAK SVC_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SVC_Handler\r
- B SVC_Handler\r
-\r
-\r
- PUBWEAK PendSV_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-PendSV_Handler\r
- B PendSV_Handler\r
-\r
-\r
- PUBWEAK SysTick_Handler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SysTick_Handler\r
- B SysTick_Handler\r
-\r
-\r
- PUBWEAK SCU_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SCU_0_IRQHandler\r
- B SCU_0_IRQHandler\r
-\r
- PUBWEAK SCU_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SCU_1_IRQHandler\r
- B SCU_1_IRQHandler\r
-\r
-\r
- PUBWEAK SCU_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-SCU_2_IRQHandler\r
- B SCU_2_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_0_IRQHandler\r
- B ERU0_0_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_1_IRQHandler\r
- B ERU0_1_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_2_IRQHandler\r
- B ERU0_2_IRQHandler\r
-\r
-\r
- PUBWEAK ERU0_3_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-ERU0_3_IRQHandler\r
- B ERU0_3_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_0_IRQHandler\r
- B USIC0_0_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_1_IRQHandler\r
- B USIC0_1_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_2_IRQHandler\r
- B USIC0_2_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_3_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_3_IRQHandler\r
- B USIC0_3_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_4_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_4_IRQHandler\r
- B USIC0_4_IRQHandler\r
-\r
-\r
- PUBWEAK USIC0_5_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-USIC0_5_IRQHandler\r
- B USIC0_5_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_C0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_C0_0_IRQHandler\r
- B VADC0_C0_0_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_C0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_C0_1_IRQHandler\r
- B VADC0_C0_1_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G0_0_IRQHandler\r
- B VADC0_G0_0_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G0_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G0_1_IRQHandler\r
- B VADC0_G0_1_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G1_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G1_0_IRQHandler\r
- B VADC0_G1_0_IRQHandler\r
-\r
-\r
- PUBWEAK VADC0_G1_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-VADC0_G1_1_IRQHandler\r
- B VADC0_G1_1_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_0_IRQHandler\r
- B CCU40_0_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_1_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_1_IRQHandler\r
- B CCU40_1_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_2_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_2_IRQHandler\r
- B CCU40_2_IRQHandler\r
-\r
-\r
- PUBWEAK CCU40_3_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-CCU40_3_IRQHandler\r
- B CCU40_3_IRQHandler\r
-\r
-\r
- PUBWEAK LEDTS0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-LEDTS0_0_IRQHandler\r
- B LEDTS0_0_IRQHandler\r
-\r
-\r
- PUBWEAK LEDTS1_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-LEDTS1_0_IRQHandler\r
- B LEDTS1_0_IRQHandler\r
-\r
-\r
- PUBWEAK BCCU0_0_IRQHandler\r
- SECTION .text:CODE:REORDER:NOROOT(1)\r
-BCCU0_0_IRQHandler\r
- B BCCU0_0_IRQHandler\r
-\r
-; Definition of the default weak SystemInit_DAVE3 function\r
-;If DAVE3 requires an extended SystemInit it will create its own version of\r
-;SystemInit_DAVE3 which overrides this weak definition. Example includes\r
-;setting up of external memory interfaces.\r
-\r
- PUBWEAK SystemInit_DAVE3\r
- SECTION .text:CODE:REORDER:NOROOT(2)\r
-SystemInit_DAVE3\r
- NOP\r
- BX LR\r
-\r
-;Decision function queried by CMSIS startup for Clock tree setup ======== */\r
-;In the absence of DAVE code engine, CMSIS SystemInit() must perform clock tree setup.\r
-;This decision routine defined here will always return TRUE.\r
-;When overridden by a definition defined in DAVE code engine, this routine\r
-;returns FALSE indicating that the code engine has performed the clock setup\r
-\r
- PUBWEAK AllowClkInitByStartup\r
- SECTION .text:CODE:REORDER:NOROOT(2)\r
-AllowClkInitByStartup\r
- MOVS R0,#1\r
- BX LR\r
-\r
- END\r
+++ /dev/null
-;*****************************************************************************/\r
-; * @file startup_XMC1300.s\r
-; * @brief CMSIS Cortex-M4 Core Device Startup File for\r
-; * Infineon XMC1300 Device Series\r
-; * @version V1.00\r
-; * @date 21. Jan. 2013\r
-; *\r
-; * @note\r
-; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.\r
-; *\r
-; * @par\r
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M\r
-; * processor based microcontrollers. This file can be freely distributed\r
-; * within development tools that are supporting such ARM based processors.\r
-; *\r
-; * @par\r
-; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
-; *\r
-; ******************************************************************************/\r
-\r
-\r
-;* <<< Use Configuration Wizard in Context Menu >>>\r
-\r
-; Amount of memory (in bytes) allocated for Stack\r
-; Tailor this value to your application needs\r
-; <h> Stack Configuration\r
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Stack_Size EQU 0x00000400\r
-\r
- AREA STACK, NOINIT, READWRITE, ALIGN=3\r
-Stack_Mem SPACE Stack_Size\r
-__initial_sp\r
-\r
-\r
-; <h> Heap Configuration\r
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\r
-; </h>\r
-\r
-Heap_Size EQU 0x00000000\r
-\r
- AREA HEAP, NOINIT, READWRITE, ALIGN=3\r
-__heap_base\r
-Heap_Mem SPACE Heap_Size\r
-__heap_limit\r
-\r
-; <h> Clock system handling by SSW\r
-; <h> CLK_VAL1 Configuration\r
-; <o0.0..7> FDIV Fractional Divider Selection\r
-; <o0.8..15> IDIV Divider Selection\r
-; <0=> Divider is bypassed\r
-; <1=> MCLK = 32 MHz\r
-; <2=> MCLK = 16 MHz\r
-; <3=> MCLK = 10.67 MHz\r
-; <4=> MCLK = 8 MHz\r
-; <254=> MCLK = 126 kHz\r
-; <255=> MCLK = 125.5 kHz\r
-; <o0.16> PCLKSEL PCLK Clock Select\r
-; <0=> PCLK = MCLK\r
-; <1=> PCLK = 2 x MCLK\r
-; <o0.17..19> RTCCLKSEL RTC Clock Select\r
-; <0=> 32.768kHz standby clock\r
-; <1=> 32.768kHz external clock from ERU0.IOUT0\r
-; <2=> 32.768kHz external clock from ACMP0.OUT\r
-; <3=> 32.768kHz external clock from ACMP1.OUT\r
-; <4=> 32.768kHz external clock from ACMP2.OUT\r
-; <5=> Reserved\r
-; <6=> Reserved\r
-; <7=> Reserved\r
-; <o0.31> do not move CLK_VAL1 to SCU_CLKCR[0..19]\r
-; </h>\r
-CLK_VAL1_Val EQU 0x00000100 ; 0xF0000000\r
-\r
-; <h> CLK_VAL2 Configuration\r
-; <o0.0> disable VADC and SHS Gating\r
-; <o0.1> disable CCU80 Gating\r
-; <o0.2> disable CCU40 Gating\r
-; <o0.3> disable USIC0 Gating\r
-; <o0.4> disable BCCU0 Gating\r
-; <o0.5> disable LEDTS0 Gating\r
-; <o0.6> disable LEDTS1 Gating\r
-; <o0.7> disable POSIF0 Gating\r
-; <o0.8> disable MATH Gating\r
-; <o0.9> disable WDT Gating\r
-; <o0.10> disable RTC Gating\r
-; <o0.31> do not move CLK_VAL2 to SCU_CGATCLR0[0..10]\r
-; </h>\r
-CLK_VAL2_Val EQU 0x00000000 ; 0xF0000000\r
-; </h>\r
-\r
- PRESERVE8\r
- THUMB\r
-\r
-;* ================== START OF VECTOR TABLE DEFINITION ====================== */\r
-;* Vector Table Mapped to Address 0 at Reset\r
- AREA RESET, DATA, READONLY\r
- EXPORT __Vectors\r
- EXPORT __Vectors_End\r
- EXPORT __Vectors_Size\r
-\r
-\r
-\r
-__Vectors\r
- DCD __initial_sp ;* Top of Stack\r
- DCD Reset_Handler ;* Reset Handler\r
- DCD 0 ;* Not used\r
- DCD 0 ;* Not Used\r
- DCD CLK_VAL1_Val ;* CLK_VAL1\r
- DCD CLK_VAL2_Val ;* CLK_VAL2\r
-__Vectors_End\r
-\r
-__Vectors_Size EQU __Vectors_End - __Vectors\r
-\r
-;* ================== END OF VECTOR TABLE DEFINITION ======================== */\r
-\r
-\r
-;* ================== START OF VECTOR ROUTINES ============================== */\r
- AREA |.text|, CODE, READONLY\r
-\r
-;* Reset Handler\r
-Reset_Handler PROC\r
- EXPORT Reset_Handler [WEAK]\r
- IMPORT __main\r
- IMPORT SystemInit\r
-\r
- ;* C routines are likely to be called. Setup the stack now\r
- LDR R0, =__initial_sp\r
- MOV SP, R0\r
-\r
- ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself"\r
- ; The real veneers will be copied later from the scatter loader before reaching main.\r
- ; This init code should handle an exception before the real veneers are copied.\r
-SRAM_BASE EQU 0x20000000\r
-VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B .\r
-\r
- LDR R1, =SRAM_BASE\r
- LDR R2, =VENEER_INIT_CODE \r
- MOVS R0, #48 ; Veneer 0..47\r
-Init_Veneers\r
- STR R2, [R1]\r
- ADDS R1, #4\r
- SUBS R0, R0, #1\r
- BNE Init_Veneers\r
-\r
-\r
- LDR R0, =SystemInit\r
- BLX R0\r
-\r
-\r
- ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is\r
- ; weakly defined here though for a potential override.\r
-\r
- LDR R0, = SystemInit_DAVE3\r
- BLX R0\r
-\r
-\r
- LDR R0, =__main\r
- BX R0\r
-\r
-\r
- ALIGN\r
- ENDP\r
-\r
-;* ========================================================================== */\r
-\r
-\r
-\r
-;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */\r
-;* Default exception Handlers - Users may override this default functionality\r
-\r
-NMI_Handler PROC\r
- EXPORT NMI_Handler [WEAK]\r
- B .\r
- ENDP\r
-HardFault_Handler\\r
- PROC\r
- EXPORT HardFault_Handler [WEAK]\r
- B .\r
- ENDP\r
-SVC_Handler\\r
- PROC\r
- EXPORT SVC_Handler [WEAK]\r
- B .\r
- ENDP\r
-PendSV_Handler\\r
- PROC\r
- EXPORT PendSV_Handler [WEAK]\r
- B .\r
- ENDP\r
-SysTick_Handler\\r
- PROC\r
- EXPORT SysTick_Handler [WEAK]\r
- B .\r
- ENDP\r
-\r
-;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */\r
-\r
-\r
-;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */\r
-;* IRQ Handlers\r
-\r
-Default_Handler PROC\r
- EXPORT SCU_0_IRQHandler [WEAK]\r
- EXPORT SCU_1_IRQHandler [WEAK]\r
- EXPORT SCU_2_IRQHandler [WEAK]\r
- EXPORT ERU0_0_IRQHandler [WEAK]\r
- EXPORT ERU0_1_IRQHandler [WEAK]\r
- EXPORT ERU0_2_IRQHandler [WEAK]\r
- EXPORT ERU0_3_IRQHandler [WEAK]\r
- EXPORT MATH0_0_IRQHandler [WEAK]\r
- EXPORT USIC0_0_IRQHandler [WEAK]\r
- EXPORT USIC0_1_IRQHandler [WEAK]\r
- EXPORT USIC0_2_IRQHandler [WEAK]\r
- EXPORT USIC0_3_IRQHandler [WEAK]\r
- EXPORT USIC0_4_IRQHandler [WEAK]\r
- EXPORT USIC0_5_IRQHandler [WEAK]\r
- EXPORT VADC0_C0_0_IRQHandler [WEAK]\r
- EXPORT VADC0_C0_1_IRQHandler [WEAK]\r
- EXPORT VADC0_G0_0_IRQHandler [WEAK]\r
- EXPORT VADC0_G0_1_IRQHandler [WEAK]\r
- EXPORT VADC0_G1_0_IRQHandler [WEAK]\r
- EXPORT VADC0_G1_1_IRQHandler [WEAK]\r
- EXPORT CCU40_0_IRQHandler [WEAK]\r
- EXPORT CCU40_1_IRQHandler [WEAK]\r
- EXPORT CCU40_2_IRQHandler [WEAK]\r
- EXPORT CCU40_3_IRQHandler [WEAK]\r
- EXPORT CCU80_0_IRQHandler [WEAK]\r
- EXPORT CCU80_1_IRQHandler [WEAK]\r
- EXPORT POSIF0_0_IRQHandler [WEAK]\r
- EXPORT POSIF0_1_IRQHandler [WEAK]\r
- EXPORT LEDTS0_0_IRQHandler [WEAK]\r
- EXPORT LEDTS1_0_IRQHandler [WEAK]\r
- EXPORT BCCU0_0_IRQHandler [WEAK]\r
-\r
-SCU_0_IRQHandler\r
-SCU_1_IRQHandler\r
-SCU_2_IRQHandler\r
-ERU0_0_IRQHandler\r
-ERU0_1_IRQHandler\r
-ERU0_2_IRQHandler\r
-ERU0_3_IRQHandler\r
-MATH0_0_IRQHandler\r
-USIC0_0_IRQHandler\r
-USIC0_1_IRQHandler\r
-USIC0_2_IRQHandler\r
-USIC0_3_IRQHandler\r
-USIC0_4_IRQHandler\r
-USIC0_5_IRQHandler\r
-VADC0_C0_0_IRQHandler\r
-VADC0_C0_1_IRQHandler\r
-VADC0_G0_0_IRQHandler\r
-VADC0_G0_1_IRQHandler\r
-VADC0_G1_0_IRQHandler\r
-VADC0_G1_1_IRQHandler\r
-CCU40_0_IRQHandler\r
-CCU40_1_IRQHandler\r
-CCU40_2_IRQHandler\r
-CCU40_3_IRQHandler\r
-CCU80_0_IRQHandler\r
-CCU80_1_IRQHandler\r
-POSIF0_0_IRQHandler\r
-POSIF0_1_IRQHandler\r
-LEDTS0_0_IRQHandler\r
-LEDTS1_0_IRQHandler\r
-BCCU0_0_IRQHandler\r
-\r
- B .\r
-\r
- ENDP\r
-\r
- ALIGN\r
-\r
-;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */\r
-\r
-;* Definition of the default weak SystemInit_DAVE3 function.\r
-;* This function will be called by the CMSIS SystemInit function.\r
-;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3\r
-;* which will overule this weak definition\r
-SystemInit_DAVE3 PROC\r
- EXPORT SystemInit_DAVE3 [WEAK]\r
- NOP\r
- BX LR\r
- ENDP\r
-\r
-;* Definition of the default weak DAVE3 function for clock App usage.\r
-;* AllowClkInitByStartup Handler */\r
-AllowClkInitByStartup PROC\r
- EXPORT AllowClkInitByStartup [WEAK]\r
- MOVS R0,#1\r
- BX LR\r
- ENDP\r
-\r
-\r
-;*******************************************************************************\r
-; User Stack and Heap initialization\r
-;*******************************************************************************\r
- IF :DEF:__MICROLIB\r
-\r
- EXPORT __initial_sp\r
- EXPORT __heap_base\r
- EXPORT __heap_limit\r
-\r
- ELSE\r
-\r
- IMPORT __use_two_region_memory\r
- EXPORT __user_initial_stackheap\r
-\r
-__user_initial_stackheap\r
-\r
- LDR R0, = Heap_Mem\r
- LDR R1, =(Stack_Mem + Stack_Size)\r
- LDR R2, = (Heap_Mem + Heap_Size)\r
- LDR R3, = Stack_Mem\r
- BX LR\r
-\r
- ALIGN\r
-\r
- ENDIF\r
-\r
-\r
-;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */\r
-; Veneers are located to fix SRAM Address 0x2000'0000\r
- AREA |.ARM.__at_0x20000000|, CODE, READWRITE\r
-\r
-; Each Veneer has exactly a lengs of 4 Byte\r
-\r
- MACRO\r
- STAYHERE $IrqNumber\r
- LDR R0, =$IrqNumber\r
- B .\r
- MEND\r
-\r
- MACRO\r
- JUMPTO $Handler\r
- LDR R0, =$Handler\r
- BX R0\r
- MEND\r
-\r
- STAYHERE 0x0 ;* Reserved\r
- STAYHERE 0x1 ;* Reserved \r
- STAYHERE 0x2 ;* Reserved \r
- JUMPTO HardFault_Handler ;* HardFault Veneer \r
- STAYHERE 0x4 ;* Reserved \r
- STAYHERE 0x5 ;* Reserved \r
- STAYHERE 0x6 ;* Reserved \r
- STAYHERE 0x7 ;* Reserved \r
- STAYHERE 0x8 ;* Reserved \r
- STAYHERE 0x9 ;* Reserved \r
- STAYHERE 0xA ;* Reserved\r
- JUMPTO SVC_Handler ;* SVC Veneer \r
- STAYHERE 0xC ;* Reserved\r
- STAYHERE 0xD ;* Reserved\r
- JUMPTO PendSV_Handler ;* PendSV Veneer \r
- JUMPTO SysTick_Handler ;* SysTick Veneer \r
- JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer \r
- JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer \r
- JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer \r
- JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer \r
- JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer \r
- JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer \r
- JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer \r
- JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer \r
- STAYHERE 0x18 ;* Reserved\r
- JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer \r
- JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer \r
- JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer \r
- JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer \r
- JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer \r
- JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer \r
- JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer \r
- JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer \r
- JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer \r
- JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer \r
- JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer \r
- JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer \r
- JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer \r
- JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer \r
- JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer \r
- JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer \r
- JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer \r
- JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer \r
- JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer \r
- JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer \r
- JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer \r
- JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer \r
- JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer \r
-\r
- ALIGN\r
-\r
-;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */\r
-\r
- END\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1100.c\r
- * @brief Device specific initialization for the XMC1100-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * *************************** Change history ********************************\r
- * V1.2, 13 Dec 2012, PKB : Created change history table\r
- */\r
-\r
-#include "system_XMC1100.h"\r
-#include <XMC1100.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1200.c\r
- * @brief Device specific initialization for the XMC1200-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * *************************** Change history ********************************\r
- * V1.2, 13 Dec 2012, PKB : Created change history table\r
- */\r
-\r
-#include "System_XMC1200.h"\r
-#include <XMC1200.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
+++ /dev/null
-/******************************************************************************\r
- * @file system_XMC1300.c\r
- * @brief Device specific initialization for the XMC1300-Series according \r
- * to CMSIS\r
- * @version V1.2\r
- * @date 13 Dec 2012\r
- *\r
- * @note\r
- * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved.\r
-\r
- *\r
- * @par\r
- * Infineon Technologies AG (Infineon) is supplying this software for use with \r
- * Infineon\92s microcontrollers.\r
- * \r
- * This file can be freely distributed within development tools that are \r
- * supporting such microcontrollers.\r
- * \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,\r
- * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-/*\r
- * ************************** Change history *********************************\r
- * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_\r
- */\r
-\r
-#include "system_XMC1300.h"\r
-#include <XMC1300.h>\r
-\r
-/*---------------------------------------------------------------------------\r
- Extern definitions \r
- *--------------------------------------------------------------------------*/\r
-extern uint32_t AllowClkInitByStartup(void);\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Global defines\r
- *----------------------------------------------------------------------------*/\r
-#define DCO_DCLK 64000000UL\r
-\r
-/*----------------------------------------------------------------------------\r
- Clock Variable definitions\r
- *----------------------------------------------------------------------------*/\r
-/*!< System Clock Frequency (Core Clock)*/\r
-uint32_t SystemCoreClock;\r
-\r
-\r
-/**\r
- * @brief Setup the microcontroller system.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit(void)\r
-{ \r
- /*\r
- * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE\r
- * Clock app.\r
- */ \r
- if(AllowClkInitByStartup()){ \r
- /* Do not change default values of IDIV,FDIV and RTCCLKSEL */\r
- /* ====== Default configuration ======= */\r
- /*\r
- * MCLK = DCO_DCLK\r
- * PCLK = MCLK\r
- * RTC CLK = Standby clock\r
- */\r
- }\r
-}\r
-\r
-/**\r
- * @brief Update SystemCoreClock according to Clock Register Values\r
- * @note - \r
- * @param None\r
- * @retval None\r
- */\r
-void SystemCoreClockUpdate(void)\r
-{\r
- uint32_t IDIV, CLKCR;\r
-\r
- CLKCR = SCU_CLOCK -> CLKCR;\r
- \r
- IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos;\r
- \r
- if(IDIV)\r
- {\r
- SystemCoreClock = DCO_DCLK / (2 * IDIV );\r
- }\r
- else\r
- {\r
- /* Divider bypassed */\r
- SystemCoreClock = DCO_DCLK;\r
- }\r
-}\r
-\r
\r
/* The rate at which data is sent to the queue. The 200ms value is converted\r
to ticks using the portTICK_RATE_MS constant. */\r
-#define mainQUEUE_SEND_FREQUENCY_MS ( 1000 / portTICK_RATE_MS )\r
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )\r
\r
/* The number of items the queue can hold. This is 1 as the receive task\r
will remove items as they are added, meaning the send task should always find\r
ShowTimeLog=1\r
ShowTimeSum=1\r
SumSortOrder=0\r
-[Disassemble mode]\r
-mode=0\r
-[Breakpoints2]\r
-Count=0\r
[Log file]\r
LoggingEnabled=_ 0\r
LogFile=_ ""\r
[TermIOLog]\r
LoggingEnabled=_ 0\r
LogFile=_ ""\r
-[Aliases]\r
-Count=0\r
-SuppressDialog=0\r
[Trace2]\r
Enabled=0\r
ShowSource=0\r
Graph=0\r
Symbiont=0\r
Exclusions=\r
+[Disassemble mode]\r
+mode=0\r
+[Breakpoints2]\r
+Count=0\r
+[Aliases]\r
+Count=0\r
+SuppressDialog=0\r
\r
<Workspace>\r
<ConfigDictionary>\r
- <CurrentConfigs>\r
- <Project>RTOSDemo/Debug</Project>\r
- </CurrentConfigs>\r
- </ConfigDictionary>\r
+ \r
+ <CurrentConfigs><Project>RTOSDemo/Debug</Project></CurrentConfigs></ConfigDictionary>\r
<Desktop>\r
<Static>\r
<Workspace>\r
<ColumnWidths>\r
- <Column0>236</Column0>\r
- <Column1>27</Column1>\r
- <Column2>27</Column2>\r
- <Column3>27</Column3>\r
- </ColumnWidths>\r
+ \r
+ \r
+ \r
+ \r
+ <Column0>236</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>\r
</Workspace>\r
<Build>\r
- <ColumnWidth0>20</ColumnWidth0>\r
- <ColumnWidth1>1216</ColumnWidth1>\r
- <ColumnWidth2>324</ColumnWidth2>\r
- <ColumnWidth3>81</ColumnWidth3>\r
- </Build>\r
+ \r
+ \r
+ \r
+ \r
+ <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1216</ColumnWidth1><ColumnWidth2>324</ColumnWidth2><ColumnWidth3>81</ColumnWidth3></Build>\r
<TerminalIO/>\r
</Static>\r
<Windows>\r
- <Wnd2>\r
+ \r
+ \r
+ <Wnd0>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-23707-15152</Identity>\r
<TabName>Workspace</TabName>\r
<Factory>Workspace</Factory>\r
<Session>\r
- <NodeDict>\r
- <ExpandedNode>RTOSDemo</ExpandedNode>\r
- <ExpandedNode>RTOSDemo/System</ExpandedNode>\r
- </NodeDict>\r
- </Session>\r
+ \r
+ <NodeDict><ExpandedNode>RTOSDemo</ExpandedNode><ExpandedNode>RTOSDemo/System</ExpandedNode></NodeDict></Session>\r
</Tab>\r
</Tabs>\r
- <SelectedTab>0</SelectedTab>\r
- </Wnd2>\r
- <Wnd3>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd0><Wnd1>\r
<Tabs>\r
<Tab>\r
<Identity>TabID-19002-15240</Identity>\r
<Session/>\r
</Tab>\r
</Tabs>\r
- <SelectedTab>0</SelectedTab>\r
- </Wnd3>\r
- </Windows>\r
+ \r
+ <SelectedTab>0</SelectedTab></Wnd1></Windows>\r
<Editor>\r
- <Pane>\r
- <Tab>\r
- <Factory>TextEditor</Factory>\r
- <Filename>$WS_DIR$\main.c</Filename>\r
- <XPos>0</XPos>\r
- <YPos>0</YPos>\r
- <SelStart>0</SelStart>\r
- <SelEnd>0</SelEnd>\r
- <XPos2>0</XPos2>\r
- <YPos2>99</YPos2>\r
- <SelStart2>5509</SelStart2>\r
- <SelEnd2>5509</SelEnd2>\r
- </Tab>\r
- <ActiveTab>0</ActiveTab>\r
- </Pane>\r
- <ActivePane>0</ActivePane>\r
- <Sizes>\r
- <Pane>\r
- <X>1000000</X>\r
- <Y>1000000</Y>\r
- </Pane>\r
- </Sizes>\r
- <SplitMode>1</SplitMode>\r
- </Editor>\r
+ \r
+ \r
+ \r
+ \r
+ <Pane><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>99</YPos2><SelStart2>5509</SelStart2><SelEnd2>5509</SelEnd2></Tab><Tab><Factory>TextEditor</Factory><Filename>$WS_DIR$\main-full.c</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd><XPos2>0</XPos2><YPos2>111</YPos2><SelStart2>7445</SelStart2><SelEnd2>7445</SelEnd2></Tab><ActiveTab>1</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>\r
<Positions>\r
- <Top>\r
- <Row0>\r
- <Sizes>\r
- <Toolbar-01348f40>\r
- <key>iaridepm.enu1</key>\r
- </Toolbar-01348f40>\r
- </Sizes>\r
- </Row0>\r
- <Row1>\r
- <Sizes/>\r
- </Row1>\r
- </Top>\r
- <Left>\r
- <Row0>\r
- <Sizes>\r
- <Wnd2>\r
- <Rect>\r
- <Top>-2</Top>\r
- <Left>-2</Left>\r
- <Bottom>740</Bottom>\r
- <Right>310</Right>\r
- <x>-2</x>\r
- <y>-2</y>\r
- <xscreen>200</xscreen>\r
- <yscreen>200</yscreen>\r
- <sizeHorzCX>119048</sizeHorzCX>\r
- <sizeHorzCY>203666</sizeHorzCY>\r
- <sizeVertCX>185714</sizeVertCX>\r
- <sizeVertCY>755601</sizeVertCY>\r
- </Rect>\r
- </Wnd2>\r
- </Sizes>\r
- </Row0>\r
- </Left>\r
- <Right>\r
- <Row0>\r
- <Sizes/>\r
- </Row0>\r
- </Right>\r
- <Bottom>\r
- <Row0>\r
- <Sizes>\r
- <Wnd3>\r
- <Rect>\r
- <Top>-2</Top>\r
- <Left>-2</Left>\r
- <Bottom>198</Bottom>\r
- <Right>1682</Right>\r
- <x>-2</x>\r
- <y>-2</y>\r
- <xscreen>1684</xscreen>\r
- <yscreen>200</yscreen>\r
- <sizeHorzCX>1002381</sizeHorzCX>\r
- <sizeHorzCY>203666</sizeHorzCY>\r
- <sizeVertCX>119048</sizeVertCX>\r
- <sizeVertCY>203666</sizeVertCY>\r
- </Rect>\r
- </Wnd3>\r
- </Sizes>\r
- </Row0>\r
- </Bottom>\r
- <Float>\r
- <Sizes/>\r
- </Float>\r
- </Positions>\r
+ \r
+ \r
+ \r
+ \r
+ \r
+ <Top><Row0><Sizes><Toolbar-01348f40><key>iaridepm.enu1</key></Toolbar-01348f40></Sizes></Row0></Top><Left><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>740</Bottom><Right>310</Right><x>-2</x><y>-2</y><xscreen>200</xscreen><yscreen>200</yscreen><sizeHorzCX>119048</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>185714</sizeVertCX><sizeVertCY>755601</sizeVertCY></Rect></Wnd0></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>198</Bottom><Right>1682</Right><x>-2</x><y>-2</y><xscreen>1684</xscreen><yscreen>200</yscreen><sizeHorzCX>1002381</sizeHorzCX><sizeHorzCY>203666</sizeHorzCY><sizeVertCX>119048</sizeVertCX><sizeVertCY>203666</sizeVertCY></Rect></Wnd1></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>\r
</Desktop>\r
</Workspace>\r
\r
projects / freertos / commitdiff