if( ctrl & NAND_ALE )
                        IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
                else
-                       IO_ADDR_W = CFG_NAND_BASE;                      
+                       IO_ADDR_W = CFG_NAND_BASE;
                this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
        }
        this->IO_ADDR_R = this->IO_ADDR_W;
        SSYNC();
 
        if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W);   
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 int bfin_device_ready(struct mtd_info *mtd)
 
        }
 
     if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W);   
+               writeb(cmd, this->IO_ADDR_W);
 }
 
 
 
        }
 
     if (cmd != NAND_CMD_NONE)
-               writeb(cmd, this->IO_ADDR_W);   
+               writeb(cmd, this->IO_ADDR_W);
 }
 #elif defined(CONFIG_IDS852_REV2)
 /*
 
                        IO_ADDR_W |= MASK_ALE;
        }
        this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
-       
+
     if (cmd != NAND_CMD_NONE)
                writeb(cmd, this->IO_ADDR_W);
 }
 
  * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
  */
 static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{      
+{
     struct nand_chip *this = mtd->priv;
 
        if (ctrl & NAND_CTRL_CHANGE) {
 
                if ( ctrl & NAND_CLE )
                        set_bit (SC3_NAND_CLE, sc3_control_base);
                else
-                       clear_bit (SC3_NAND_CLE, sc3_control_base);                     
+                       clear_bit (SC3_NAND_CLE, sc3_control_base);
                if ( ctrl & NAND_ALE )
                        set_bit (SC3_NAND_ALE, sc3_control_base);
                else
                if ( ctrl & NAND_NCE )
                        set_bit (SC3_NAND_CE, sc3_control_base);
                else
-                       clear_bit (SC3_NAND_CE, sc3_control_base);              
+                       clear_bit (SC3_NAND_CE, sc3_control_base);
        }
 
     if (cmd != NAND_CMD_NONE)
 
                printf("\nNAND %s: ", read ? "read" : "write");
                if (arg_off_size(argc - 3, argv + 3, nand, &off, &size) != 0)
                        return 1;
-               
+
                s = strchr(cmd, '.');
                if (s != NULL &&
                        (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
 
 //     nand->autooob     = &davinci_nand_oobinfo;
        nand->ecc.calculate = nand_davinci_calculate_ecc;
        nand->ecc.correct  = nand_davinci_correct_data;
-       nand->ecc.hwctl  = nand_davinci_enable_hwecc;   
+       nand->ecc.hwctl  = nand_davinci_enable_hwecc;
 #else
        nand->ecc.mode     = NAND_ECC_SOFT;
 #endif
 
 
        /* Calculate pages in each block */
        pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
-       
+
        /* Select the NAND device */
        chip->select_chip(mtd, chipnr);
 
                BUG();
        }
 #endif
-       
+
        ret = nand_scan_ident(mtd, maxchips);
        if (!ret)
                ret = nand_scan_tail(mtd);
 
        for (;
             erase.addr < opts->offset + erase_length;
             erase.addr += meminfo->erasesize) {
-               
+
                WATCHDOG_RESET ();
 
                if (!opts->scrub && bbtest) {
                        chip->ops.datbuf = NULL;
                        chip->ops.oobbuf = buf;
                        chip->ops.ooboffs = chip->badblockpos & ~0x01;
-                       
+
                        result = meminfo->write_oob(meminfo,
                                                        erase.addr + meminfo->oobsize,
                                                        &chip->ops);
  * @chip:      nand chip structure
  * @oob:       oob data buffer
  * @ops:       oob ops structure
- * 
+ *
  * Copied from nand_base.c
  */
 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
        uint8_t *oob = ops->oobbuf;
        uint8_t *buf = ops->datbuf;
        int ret, subpage;
-       
+
        ops->retlen = 0;
        if (!writelen)
                return 0;
 
        printk("nand_write_opts: to: 0x%08x, ops->len: 0x%08x\n", to, ops->len);
-       
+
        /* reject writes, which are not page aligned */
        if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
                printk(KERN_NOTICE "nand_write: "
 
 
        struct nand_ecc_ctrl ecc;
        struct nand_buffers *buffers;
-       
+
        struct nand_hw_control hwcontrol;
 
        struct mtd_oob_ops ops;