+commit 635e5f8fc82365e6e9734b3132bc95135a6de679
+Author: Wolfgang Denk <wd@denx.de>
+Date: Sun Jan 18 21:37:48 2009 +0100
+
+ Prepare 2009.01-rc3
+
+ Update CHANGELOG
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 4cda437898f7873752f0201757cd33f12196ce87
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Jan 17 13:32:42 2009 -0500
+
+ build system: treat all Darwin's alike
+
+ The x86 based version of Darwin behaves the same quirky way as the powerpc
+ Darwin, so only check HOSTOS when setting up Darwin workarounds.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit c088a108c75db565e07292fd668dfa5491e85bc2
+Author: Peter Korsgaard <jacmet@sunsite.dk>
+Date: Wed Jan 14 13:52:24 2009 +0100
+
+ fdt_resize(): fix actualsize calculations with unaligned blobs
+
+ The code in fdt_resize() to extend the fdt size to end on a page boundary
+ is wrong for fdt's not located at an address aligned on a page boundary.
+ What's even worse, the code would make actualsize shrink rather than grow
+ if (blob & 0xfff) was bigger than the amount of padding added by ALIGN(),
+ causing fdt_add_mem_rsv to fail.
+
+ Fix it by aligning end address (blob + size) to a page boundary instead.
+ For aligned fdt's this is equivalent to what we had before.
+
+ Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
+
+commit fadad1573fb16c90025f08a2861d6047d093cba7
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Jan 9 04:38:17 2009 -0500
+
+ ncb: use socklen_t
+
+ The recvfrom() function takes a socklen_t, not an int.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit fc83c9273cec6e6e542f4a0ea3b653b7d0513ffa
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Jan 11 16:35:16 2009 +0100
+
+ sh: serial: use readx/writex accessors
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 9e1fa628bdb64745811cdd26c4f953846c076180
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sun Jan 11 16:35:15 2009 +0100
+
+ sh: serial: coding style cleanup
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit c9935c992575922b7ef13eec0656ed8665d324e3
+Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+Date: Sun Jan 11 17:48:56 2009 +0900
+
+ sh: Fix compile error on lowlevel_init file
+
+ lowlevel_init of SH was corrected to use the write/readXX macro.
+ However, there was a problem that was not able to be compiled partially.
+ This patch corrected this.
+
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit a5b04d00bfeb940c62232972ce644d50b45797f9
+Author: Kieran Bingham <kieranbingham@gmail.com>
+Date: Tue Dec 30 01:16:03 2008 +0000
+
+ sh: Fix up rsk7203 target for out of tree build
+
+ Fix up rsk7203 target to build successfully using out-of-tree build.
+
+ Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit f7e78f3b74aae9caca2997bad865a72338326c0a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Dec 20 19:29:49 2008 +0100
+
+ sh: use write{8,16,32} in all lowlevel_init
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit e4430779623af500de1cee7892c379f07ef59813
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Dec 20 19:29:48 2008 +0100
+
+ sh: lowlevel_init coding style cleanup
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 85cb052ee41675ca361e6a4c69455dc715c8f2d9
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Dec 20 15:27:45 2008 +0100
+
+ sh: update sh2/sh2a timer coding style
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 1e15ff999322e81af4c0c0c548908f38944ba39c
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Dec 20 15:25:22 2008 +0100
+
+ sh: update sh timer coding style
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+
+commit 0e3ece33801e377be67ffa29f083421ad820f28b
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 14 23:26:05 2009 +0100
+
+ Prepare 2009.01-rc2
+
+ Update CHANGELOG.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit e92c9a860e44c14513c8909ce4299e253a775eeb
+Author: Wolfgang Denk <wd@denx.de>
+Date: Wed Jan 14 22:35:30 2009 +0100
+
+ cpu/mpc824x/Makefile: fix warning with parallel builds
+
+ Parallel builds would occasionally issue this build warning:
+
+ ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists
+
+ Use "ln -sf" as quick work around for the issue.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 3ba605d4beec649438539e7df97b5fedb26592fb
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Fri Jan 2 12:18:49 2009 +0100
+
+ ppc4xx: Add loadpci command to esd's CPCI4052 and CPCI405AB boards
+
+ This patch adds esd's loadpci BSP command to CPCI4052 and
+ CPCI405AB board. This requires CONFIG_CMD_BSP and CONFIG_PRAM.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 600fe46fb3dab7f07604f9009904f31584415114
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Fri Jan 2 12:18:12 2009 +0100
+
+ ppc4xx: Disable pci node in device tree on CPCI405 pci adapters
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit f6a1f490d224c600a09137e58d1026d150b8e679
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Fri Jan 2 12:17:36 2009 +0100
+
+ ppc4xx: Cleanup CPCI405 board code
+
+ This patch cleans up CPCI405 board support:
+ - wrap long lines
+ - unification of spaces in function calls
+ - remove dead code
+
+ Use correct io accessors on peripherals.
+
+ Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit fceebb45a0b97e92f9889861f8c3b9cb885e706f
+Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Date: Fri Jan 2 12:16:35 2009 +0100
+
+ ppc4xx: Enable auto RS485 mode on PLU405 boards
+
+ This patch turns on the auto RS485 mode in the 2nd external
+ uart on PLU405 boards. This is a special mode of the used
+ Exar XR16C2850 uart. Because these boards only have a 485 physical
+ layer connected it's a good idea to turn it on by default.
+
+ Signed-off-by: Matthias Fuchs <mf@esd.eu>
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue Jan 13 16:29:28 2009 -0500
+
+ Some changes of TLB entry setting for MPC8572DS
+
+ - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
+ all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
+ can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
+
+ - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 950264317eb9594b2b5ee2fb65206200a1c6007a
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Tue Jan 13 16:29:22 2009 -0500
+
+ Change DDR tlb start entry to CONFIG param for 85xx
+
+ So that we can locate the DDR tlb start entry to the value other than 8. By
+ default, it is still 8.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit 6d3a10f73ece7ffb736890c10e023222612a4aa0
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Fri Jan 9 16:02:35 2009 +0800
+
+ Change PCIE1&2 deciide logic on MPC8544DS board more readable
+
+ The IO port selection for MPC8544DS board:
+ Port cfg_io_ports
+ PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
+ PCIE2 0x4, 0x5, 0x6, 0x7
+ PCIE3 0x6, 0x7
+ This patch changes the PCIE12 and PCIE2 logic more readable.
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 028e116811d28a031660f1ad9e20ac1293b3c5c7
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Fri Jan 9 16:01:52 2009 +0800
+
+ PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit
+
+ PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of
+ PCIE1 bit.
+ On MPC8572DS board, PCIE refers to PCIE1.
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 9afc2ef0307aecf52482df67c31b75d5f9e66b47
+Author: Roy Zang <tie-fei.zang@freescale.com>
+Date: Fri Jan 9 16:00:55 2009 +0800
+
+ Fix IO port selection issue on MPC8544DS and MPC8572DS boards
+
+ The IO port selection is not correct on MPC8572DS and MPC8544DS board.
+ This patch fixes this issue.
+ For MPC8572
+ Port cfg_io_ports
+ PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf
+ PCIE2 0x3, 0x7
+ PCIE3 0x7
+
+ For MPC8544
+ Port cfg_io_ports
+ PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7
+ PCIE2 0x4, 0x5, 0x6, 0x7
+ PCIE3 0x6, 0x7
+ Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
+
+commit 3e3fffe3baf3befde287fec1fcbfe55052fb8946
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Wed Dec 3 22:36:44 2008 -0600
+
+ mpc8610hpcd: Fix PCI mapping concepts
+
+ Rename _BASE to _BUS, as it's actually a PCI bus address,
+ separate virtual and physical addresses into _VIRT and _PHYS,
+ and use each appopriately. This makes the code easier to read
+ and understand, and facilitates mapping changes going forward.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit 79e436cad3b4a7db88408c3f05175028f30d700d
+Author: Becky Bruce <beckyb@kernel.crashing.org>
+Date: Wed Dec 3 22:36:26 2008 -0600
+
+ sbc8641d: Fix PCI mapping concepts
+
+ Rename _BASE to _BUS, as it's actually a PCI bus address,
+ separate virtual and physical addresses into _VIRT and _PHYS,
+ and use each appopriately. This makes the code easier to read
+ and understand, and facilitates mapping changes going forward.
+
+ Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
+
+commit a9f3acbcd07da72b5446ce557531a3ed8b8beff0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Mon Jan 12 14:50:35 2009 +0100
+
+ MPC86xx: fix build warnings
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 032a1c934ef4dc003281f57302b6e693062c1868
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Mon Jan 5 16:09:44 2009 -0500
+
+ bf537-stamp/nand: fix board_nand_init prototype
+
+ The board_nand_init() function should return an int, not void.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 687f952e4119594ab913be11c90f7f018c2a7a79
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Thu Dec 11 07:04:48 2008 -0500
+
+ Blackfin: drop CONFIG_SPI handling in board init
+
+ The eeprom SPI init functions are duplicated as the common code already
+ executes these for us.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit e7e684b10d73a303902208594c7c3e7e0d753282
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Oct 24 17:51:57 2008 -0400
+
+ Blackfin: fix out-of-tree building with ldscripts
+
+ Many of the Blackfin board linker scripts are preprocessed, so make sure we
+ output the linker script into the build tree rather than the source tree.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit b9eecc342f767b50e1476fbc1aad7d88dd4ce5eb
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Fri Oct 24 17:48:54 2008 -0400
+
+ Blackfin: fix linker scripts to work with --gc-sections
+
+ Make sure all .text sections get pulled in and the entry point is properly
+ referenced so they don't get discarded when linking with --gc-sections.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 509fc553bc6087a6f705b3bf52f3950d7d1eaa58
+Author: Mike Frysinger <vapier@gentoo.org>
+Date: Sat Oct 11 20:45:44 2008 -0400
+
+ Blackfin: set proper LDRFLAGS for parallel booting LDRs
+
+ In order to boot an LDR out of parallel flash, the ldr utility needs a few
+ flags to tell it to generate the right header.
+
+ Signed-off-by: Mike Frysinger <vapier@gentoo.org>
+
+commit 3dd9395a0d7ce69a335d0e743c04b9caedd681d3
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Jan 6 21:41:59 2009 +0100
+
+ at91rm9200: move define from lowlevel_init to header
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 8a48686fac2030287765f1970ea046bd5734b733
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 3 17:22:26 2009 +0100
+
+ m501sk: move to the common memory setup
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit d481c80d78f954133c035dae6c7d22de3625795d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 3 17:22:25 2009 +0100
+
+ at91rm9200: rename lowlevel init value to CONFIG_SYS_
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 4e170b16625291aa10d0d9abc3f34e8a5945d157
+Author: Nicolas Ferre <nicolas.ferre@atmel.com>
+Date: Tue Jan 6 21:13:14 2009 +0100
+
+ at91: add at91sam9xeek board support
+
+ At91sam9xe is basically an at91sam9260 with embedded flash. We can manage
+ it as another entry for at91sam9260 in the Makefile.
+
+ Check documentation at :
+ http://www.atmel.com/dyn/products/product_card.asp?part_id=4263
+
+ Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 9ffd53db870a7da134f9a1ae76894a6b31237be5
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Jan 6 21:15:57 2009 +0100
+
+ fix bmp_logo.h make dependencies to allow parallel build
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit e12d9a8fb48d24176efffccc072b445e60a3afe4
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Sat Jan 3 17:22:24 2009 +0100
+
+ at91: Fix Atmel's at91sam9 boards out of tree build
+
+ introduced in commit 89a7a87f084c
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 0668236bafaa1c11c521652a2facebc74beecbf0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Dec 30 22:56:11 2008 +0100
+
+ README: update mailing list name and hits to patch submission.
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit d9011f9b75561a0bd9254934c2bb2bc799d4f645
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Dec 23 16:32:01 2008 -0600
+
+ 85xx: Enable inbound PCI config cycles for X-ES boards cleanup
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 1f03cbfae221b24ba1341a0a3f62ff01c5c874df
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Tue Dec 23 16:32:00 2008 -0600
+
+ XPedite5200 board support cleanup
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit fea91edee8ae0295e3c30b1ff544df51f4d668e1
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Dec 2 21:58:04 2008 +0100
+
+ usb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enable
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Remy Böhmer <linux@bohmer.net>
+
+commit ada591d2a0ecff5f9bc5ed1ebf310f439c3d0a28
+Author: Trent Piepho <tpiepho@freescale.com>
+Date: Wed Dec 3 15:16:37 2008 -0800
+
+ mpc8[56]xx: Put localbus clock in sysinfo and gd
+
+ Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
+ and print it out, but don't save it.
+
+ This changes where its calculated and stored to be more consistent with the
+ CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.
+
+ The localbus frequency is added to sysinfo and calculated when sysinfo is
+ set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.
+
+ get_clocks() copies the frequency into the global data, as the other
+ frequencies are, into a new field that is only enabled for MPC85xx and
+ MPC86xx.
+
+ checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
+ from sysinfo, like the other frequencies, instead of calculating it on the
+ spot.
+
+ Signed-off-by: Trent Piepho <tpiepho@freescale.com>
+ Acked-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 9863d6aca11405e1e0d8aba2045d78aeec4d4ee7
+Author: Trent Piepho <tpiepho@freescale.com>
+Date: Wed Dec 3 15:16:36 2008 -0800
+
+ mpc86xx: Double local bus clock divider
+
+ The local bus clock divider should be doubled for both 8610 and 8641.
+
+ Signed-off-by: Trent Piepho <tpiepho@freescale.com>
+ Acked-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 446c381e3e16f19857b72ea0d06241267b8b9d58
+Author: Trent Piepho <tpiepho@freescale.com>
+Date: Wed Dec 3 15:16:35 2008 -0800
+
+ mpc8568: Double local bus clock divider
+
+ The clock divider for the MPC8568 local bus should be doubled, like the
+ other newer MPC85xx chips.
+
+ Since there are now more chips with a 2x divider than a 1x, and any new
+ 85xx chips will probably be 2x, invert the sense of the #if so that it
+ lists the 1x chips instead of the 2x ones.
+
+ Signed-off-by: Trent Piepho <tpiepho@freescale.com>
+ Acked-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit f51f07eb58fad12de9294ba4ee6c09a0ddeaee03
+Author: Dave Liu <daveliu@freescale.com>
+Date: Tue Dec 16 12:09:27 2008 +0800
+
+ 85xx: Fix the boot window issue
+
+ If one custom board is using the 8MB flash, it is set
+ as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
+ The current start.S code will be broken at switch_as.
+
+ It is because the TLB1[15] is set as 16MB page size,
+ EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.
+
+ For the 8MB flash case, the EPN = 0xefxxxxxx,
+ RPN = 0xffxxxxxx. Assume the virt address of switch_as
+ is 0xef7ff18c, the real address of the instruction at
+ switch_as should be 0xff7ff18c. the 0xff7ff18c is out
+ of the range of the default 8MB boot LAW window
+ 0xff800000 - 0xffffffff.
+
+ So when we switch to AS1 address space at switch_as,
+ the core can't fetch the instruction at switch_as any
+ more. It will cause broken issue.
+
+ Signed-off-by: Dave Liu <daveliu@freescale.com>
+
+commit 58da8890d5fbd074746037722a423de9ac408616
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date: Thu Dec 11 15:47:50 2008 -0500
+
+ sbc8548: use proper PHY address
+
+ The values given for the PHY address were wrong, so the code
+ read no valid PHY ID, and fell through to the generic PHY
+ support, which would work on 1000M but would not auto negotiate
+ down to 100M or 10M.
+
+ Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit ad22f9273c6f24fbfa917e867680e9688e0c59c5
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date: Thu Dec 11 15:47:51 2008 -0500
+
+ sbc8548: enable command line editing by default.
+
+ Lets make things a bit more user friendly. It isn't 1985 anymore.
+
+ Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit bd93105fa171184a71ca8b22be03dc2705cfbd3f
+Author: Paul Gortmaker <paul.gortmaker@windriver.com>
+Date: Thu Dec 11 15:47:49 2008 -0500
+
+ sbc8548: don't enable the 3rd and 4th eTSEC
+
+ These interfaces don't have usable connectors on the board, so don't
+ bother enumerating or configuring them.
+
+ Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+commit 181a3650113883728927928b3ac81ad6dade4b2c
+Author: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed Dec 3 10:08:19 2008 -0500
+
+ Set IVPR to kenrel entry point in second core boot page
+
+ Assuming the OSes exception vectors start from the base of kernel address, and
+ the kernel physical starting address can be relocated to an non-zero address.
+ This patch enables the second core to have a valid IVPR for debugger before
+ kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
+ value for second core which runs kernel at different physical address other
+ than 0x0.
+
+ Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+
+commit a5d212a263c58cc746481bf1fc878510533ce7d6
+Author: Trent Piepho <tpiepho@freescale.com>
+Date: Wed Dec 3 15:16:34 2008 -0800
+
+ mpc8xxx: LCRR[CLKDIV] is sometimes five bits
+
+ On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
+ instead of four.
+
+ In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It
+ should be safe as the fifth bit was defined as reserved and set to 0.
+
+ Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
+
+ Signed-off-by: Trent Piepho <tpiepho@freescale.com>
+ Acked-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 58ec4866ed916c7e422f5107bb27b0822084728e
+Author: Trent Piepho <tpiepho@freescale.com>
+Date: Wed Dec 3 15:16:38 2008 -0800
+
+ mpc8[56]xx: Put localbus clock in device tree
+
+ Export the localbus frequency in the device tree, the same way the CPU, TB,
+ CCB, and various other frequencies are exported in their respective device
+ tree nodes.
+
+ Some localbus devices need this information to be programed correctly, so
+ it makes sense to export it along with the other frequencies.
+
+ Unfortunately, when someone wrote the localbus dts bindings, they didn't
+ bother to define what the "compatible" property should be. So it seems no
+ one was quite sure what to put in their dts files.
+
+ Based on current existing dts files in the kernel source, I've used
+ "fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
+ of the 85xx devices, and are looked for by the Linux code. The eLBC is
+ apparently not entirely backward compatible with the pq3 LBC and so eLBC
+ equipped platforms like 8572 won't use pq3-localbus.
+
+ For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
+ and is also looked for by the Linux code. On MPC8641, I've also used
+ "fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
+ which don't use "fsl,elbc" or any other acceptable name to match on.
+
+ Signed-off-by: Trent Piepho <tpiepho@freescale.com>
+ Acked-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Jon Loeliger <jdl@freescale.com>
+
+commit 9d94aff699eed38b286814fcbb335f3eb8516a0e
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Dec 16 14:59:22 2008 -0600
+
+ NAND FSL elbc: Use virt_to_phys to determine which bank is in use
+
+ The current code that determines which bank/chipselect is used for a
+ given NAND instance only worked for 32-bit addresses and assumed
+ a 1:1 mapping. This breaks in 36-bit physical configs.
+
+ The proper way to handle this is to use the virt_to_phys() and
+ BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address
+ with the the virtual address the NAND code uses.
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+ Acked-by: Scott Wood <scottwood@freescale.com>
+
+commit 77c8115b1f1871811633eae77a5a700fac1f0e50
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Dec 16 14:59:21 2008 -0600
+
+ ppc: Use addrmap in virt_to_phys and map_physmem.
+
+ If we have addr map support enabled use the mapping functions to
+ implement virt_to_phys() and map_physmem().
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit ecf5b98c7a6a2e2256dfddd48fab26678dcd6b90
+Author: Kumar Gala <galak@kernel.crashing.org>
+Date: Tue Dec 16 14:59:20 2008 -0600
+
+ 85xx: Add support to populate addr map based on TLB settings
+
+ Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+
+commit 78bbc5ce151c5a484bb51bf1866b4a993ffc16ec
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Mon Dec 1 13:47:13 2008 -0600
+
+ XPedite5200 board support
+
+ Initial support for Extreme Engineering Solutions XPedite5200 -
+ a MPC8548-based PMC single board computer.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 487dcb4fb89be0992bc06ec1341090017bd9cf2f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Oct 29 12:39:27 2008 -0500
+
+ 85xx: Enable inbound PCI config cycles for X-ES boards
+
+ Update X-ES Freescale boards to allow inbound PCI configuration
+ cycles when configured as agent/endpoint.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit ccf0fdd02b97323f8caae18d06cc9daeac2f192f
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Dec 17 16:36:23 2008 -0600
+
+ XPedite5370 board support
+
+ Initial support for Extreme Engineering Solutions XPedite5370 -
+ a MPC8572-based 3U VPX single board computer with a PMC/XMC
+ site.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit e92739d34e2d6b6aca93b2598248210710897ce8
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Dec 17 16:36:21 2008 -0600
+
+ Add support for PCA953x I2C gpio devices
+
+ Initial support for NXP's 4 and 8 bit I2C gpio expanders
+ (eg pca9537, pca9557, etc). The CONFIG_PCA953X define
+ enables support for the devices while the CONFIG_CMD_PCA953X
+ define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO
+ define enables an 'info' sub-command which provides summary
+ information for the given pca953x device.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit 7a8979591171676417ab36852d8811a8c46accd8
+Author: Peter Tyser <ptyser@xes-inc.com>
+Date: Wed Oct 29 12:39:26 2008 -0500
+
+ pci/fsl_pci_init: Enable inbound PCI config cycles
+
+ Add fsl_pci_config_unlock() function to enable a
+ PCI/PCIe interface configured in agent/endpoint mode to
+ respond to inbound PCI configuration cycles.
+
+ Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
+
+commit b616f2b545f73757669b37386f0b37bb61fc6797
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Mon Sep 8 22:27:18 2008 +0200
+
+ MIPS: qemu_mips: update doc to generate and to use qemu flash, ide file
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 16cdf816779f5b602a9b3b4d2ea4dea05095c35b
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Dec 16 22:10:31 2008 +0100
+
+ MIPS: qemu_mips: update doc to use all disk and boot linux kernel
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit 13095b2f07dacb1f863772266c1789d47a523a8a
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Tue Dec 16 22:10:30 2008 +0100
+
+ MIPS: qemu_mips: move env storage just after u-boot
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
+
+commit aced78d852d0b009e8aaa1445af8cb40861ee549
+Author: Wolfgang Denk <wd@denx.de>
+Date: Tue Dec 16 23:48:27 2008 +0100
+
+ Prepare 2009.01-rc1
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
commit 9e2a79b4c585ad31138fb90b68fd0234d64a8da8
Author: Wolfgang Denk <wd@denx.de>
Date: Tue Dec 16 23:13:46 2008 +0100
Signed-off-by: Wolfgang Denk <wd@denx.de>
+commit ff49ea8977b56916edd5b1766d9939010e30b181
+Author: Scott Wood <scottwood@freescale.com>
+Date: Tue Dec 16 14:24:16 2008 -0600
+
+ NAND: Mark the BBT as scanned prior to calling scan_bbt.
+
+ Otherwise, recursion can occur if scan_bbt does not find a bad block
+ table, and tries to write one, and the attempt to erase the BBT area
+ causes a bad block check.
+
+ Signed-off-by: Scott Wood <scottwood@freescale.com>
+
commit 584eedab66d0828f2d571a24b10526c4e65f547b
Author: Ilya Yanok <yanok@emcraft.com>
Date: Thu Dec 11 05:51:57 2008 +0300
MPC8266ADS MPC8266
+Peter Tyser <ptyser@xes-inc.com>
+
+ XPEDITE5200 MPC8548
+ XPEDITE5370 MPC8572
David Updegraff <dave@cray.com>
TQM8548 \
TQM8555 \
TQM8560 \
+ XPEDITE5200 \
+ XPEDITE5370 \
"
#########################################################################
VERSION = 2009
PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
LIBS += drivers/block/libblock.a
LIBS += drivers/dma/libdma.a
LIBS += drivers/fpga/libfpga.a
+LIBS += drivers/gpio/libgpio.a
LIBS += drivers/hwmon/libhwmon.a
LIBS += drivers/i2c/libi2c.a
LIBS += drivers/input/libinput.a
$(OBJS): depend $(obj)include/autoconf.mk
$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
-$(LIBS): depend $(obj)include/autoconf.mk
+$(LIBS): depend $(obj)include/autoconf.mk $(SUBDIRS)
$(MAKE) -C $(dir $(subst $(obj),,$@))
$(LIBBOARD): depend $(LIBS) $(obj)include/autoconf.mk
TAG_SUBDIRS += common
TAG_SUBDIRS += drivers/bios_emulator
TAG_SUBDIRS += drivers/block
+TAG_SUBDIRS += drivers/gpio
TAG_SUBDIRS += drivers/hwmon
TAG_SUBDIRS += drivers/i2c
TAG_SUBDIRS += drivers/input
echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>$(obj)include/config.h;
@$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
+XPEDITE5200_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
+
+XPEDITE5370_config: unconfig
+ @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
+
#########################################################################
## MPC86xx Systems
#########################################################################
at91sam9260ek_dataflash_cs0_config \
at91sam9260ek_dataflash_cs1_config \
at91sam9260ek_config : unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
fi;
@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
+at91sam9xeek_nandflash_config \
+at91sam9xeek_dataflash_cs0_config \
+at91sam9xeek_dataflash_cs1_config \
+at91sam9xeek_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _nandflash,$@)" ] ; then \
+ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in NAND FLASH" ; \
+ elif [ "$(findstring dataflash_cs0,$@)" ] ; then \
+ echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+ else \
+ echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in SPI DATAFLASH CS1" ; \
+ fi;
+ @$(MKCONFIG) -n at91sam9xeek -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91sam9
+
at91sam9261ek_nandflash_config \
at91sam9261ek_dataflash_cs0_config \
at91sam9261ek_dataflash_cs3_config \
at91sam9261ek_config : unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
at91sam9263ek_dataflash_config \
at91sam9263ek_dataflash_cs0_config \
at91sam9263ek_config : unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
at91sam9rlek_dataflash_config \
at91sam9rlek_dataflash_cs0_config \
at91sam9rlek_config : unconfig
+ @mkdir -p $(obj)include
@if [ "$(findstring _nandflash,$@)" ] ; then \
echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \
$(XECHO) "... with environment variable in NAND FLASH" ; \
## sh2 (Renesas SuperH)
#########################################################################
rsk7203_config: unconfig
- @ >include/config.h
- @echo "#define CONFIG_RSK7203 1" >> include/config.h
+ @mkdir -p $(obj)include
+ @echo "#define CONFIG_RSK7203 1" > $(obj)/include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh2 rsk7203 renesas
#########################################################################
CONFIG_CMD_MII * MII utility commands
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NET bootp, tftpboot, rarpboot
+ CONFIG_CMD_PCA953X * PCA953x I2C gpio commands
+ CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
CONFIG_CMD_PCI * pciinfo
CONFIG_CMD_PCMCIA * PCMCIA support
CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network
Note that if the RTC uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
+- GPIO Support:
+ CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO
+ CONFIG_PCA953X_INFO - enable pca953x info command
+
+ Note that if the GPIO device uses I2C, then the I2C interface
+ must also be configured. See I2C Support, below.
+
- Timestamp Support:
When CONFIG_TIMESTAMP is selected, the timestamp
locked as (mis-) used as memory, etc.
Chris Hallinan posted a good summary of these issues to the
- u-boot-users mailing list:
+ U-Boot mailing list:
Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)?
From: "Chris Hallinan" <clh@net1plus.com>
Download latest U-Boot source;
- Subscribe to u-boot-users mailing list;
+ Subscribe to u-boot mailing list;
if (clueless) {
email ("Hi, I am new to U-Boot, how do I get started?");
establish some rules. Submissions which do not conform to these rules
may be rejected, even when they contain important and valuable stuff.
-Patches shall be sent to the u-boot-users mailing list.
-
Please see http://www.denx.de/wiki/U-Boot/Patches for details.
+Patches shall be sent to the u-boot mailing list <u-boot@lists.denx.de>;
+see http://lists.denx.de/mailman/listinfo/u-boot
+
When you send a patch, please include the following information with
it:
disabled must not need more memory than the old code without your
modification.
-* Remember that there is a size limit of 40 kB per message on the
- u-boot-users mailing list. Bigger patches will be moderated. If
- they are reasonable and not bigger than 100 kB, they will be
- acknowledged. Even bigger patches should be avoided.
+* Remember that there is a size limit of 100 kB per message on the
+ u-boot mailing list. Bigger patches will be moderated. If they are
+ reasonable and not too big, they will be acknowledged. But patches
+ bigger than the size limit should be avoided.
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
- mv -f $@.tmp $@
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
+#undef ENTRY
+#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
+ENTRY(_start)
SECTIONS
{
.text :
{
- cpu/blackfin/start.o (.text)
+ cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* it linked after the configuration sector.
*/
- cpu/blackfin/traps.o (.text)
- cpu/blackfin/interrupt.o (.text)
- cpu/blackfin/serial.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- board/bf533-ezkit/bf533-ezkit.o (.text)
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+ lib_generic/zlib.o (.text .text.*)
+ board/bf533-ezkit/bf533-ezkit.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
- cpu/blackfin/initcode.o (.text)
+ cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
- mv -f $@.tmp $@
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
+#undef ENTRY
+#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
+ENTRY(_start)
SECTIONS
{
.text :
{
- cpu/blackfin/start.o (.text)
+ cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* it linked after the configuration sector.
*/
- cpu/blackfin/traps.o (.text)
- cpu/blackfin/interrupt.o (.text)
- cpu/blackfin/serial.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
- cpu/blackfin/initcode.o (.text)
+ cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
- mv -f $@.tmp $@
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
# Set some default LDR flags based on boot mode.
-LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
* Members with a "?" were not set in the merged testing-NAND branch,
* so they are not set here either.
*/
-void board_nand_init(struct nand_chip *nand)
+int board_nand_init(struct nand_chip *nand)
{
*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
nand->ecc.mode = NAND_ECC_SOFT;
nand->dev_ready = bfin_device_ready;
nand->chip_delay = 30;
+
+ return 0;
}
#endif
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
+#undef ENTRY
+#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
+ENTRY(_start)
SECTIONS
{
.text :
{
- cpu/blackfin/start.o (.text)
+ cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* it linked after the configuration sector.
*/
- cpu/blackfin/traps.o (.text)
- cpu/blackfin/interrupt.o (.text)
- cpu/blackfin/serial.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
- cpu/blackfin/initcode.o (.text)
+ cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds
+$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-u-boot.lds: u-boot.lds.S
- $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp
- mv -f $@.tmp $@
+$(obj)u-boot.lds: u-boot.lds.S
+ $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
clean:
rm -f $(SOBJS) $(OBJS)
#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
# (C) Copyright 2001
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# This is not actually used for Blackfin boards so do not change it
#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
#include <config.h>
#include <asm/blackfin.h>
#undef ALIGN
+#undef ENTRY
+#undef bfin
/* If we don't actually load anything into L1 data, this will avoid
* a syntax error. If we do actually load something into L1 data,
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
+ENTRY(_start)
SECTIONS
{
.text :
{
- cpu/blackfin/start.o (.text)
+ cpu/blackfin/start.o (.text .text.*)
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* it linked after the configuration sector.
*/
- cpu/blackfin/traps.o (.text)
- cpu/blackfin/interrupt.o (.text)
- cpu/blackfin/serial.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_generic/zlib.o (.text)
- board/bf561-ezkit/bf561-ezkit.o (.text)
+ cpu/blackfin/traps.o (.text .text.*)
+ cpu/blackfin/interrupt.o (.text .text.*)
+ cpu/blackfin/serial.o (.text .text.*)
+ common/dlmalloc.o (.text .text.*)
+ lib_generic/crc32.o (.text .text.*)
+ lib_generic/zlib.o (.text .text.*)
+ board/bf561-ezkit/bf561-ezkit.o (.text .text.*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text .text.*)
#endif
__initcode_start = .;
- cpu/blackfin/initcode.o (.text)
+ cpu/blackfin/initcode.o (.text .text.*)
__initcode_end = .;
*(.text .text.*)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS += ../common/cmd_loadpci.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
-#if 0
-#define FPGA_DEBUG
-#endif
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void __ft_board_setup(void *blob, bd_t *bd);
+
+#undef FPGA_DEBUG
/* fpga configuration data - generated by bin2cc */
const unsigned char fpgadata[] =
{
-#ifdef CONFIG_CPCI405_VER2
-# ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405_VER2)
+# if defined(CONFIG_CPCI405AB)
# include "fpgadata_cpci405ab.c"
# else
# include "fpgadata_cpci4052.c"
#include "../common/fpga.c"
#include "../common/auto_update.h"
-#ifdef CONFIG_CPCI405AB
+#if defined(CONFIG_CPCI405AB)
au_image_t au_image[] = {
{"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
{"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
{"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
};
#else
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
au_image_t au_image[] = {
{"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
{"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
-int board_early_init_f (void)
+int board_early_init_f(void)
{
#ifndef CONFIG_CPCI405_VER2
int index, len, i;
#ifdef FPGA_DEBUG
/* set up serial port with default baudrate */
- (void) get_clocks ();
+ (void)get_clocks();
gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
+ serial_init();
console_init_f();
#endif
/*
- * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
+ * First pull fpga-prg pin low,
+ * to disable fpga logic (on version 2 board)
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
out32(GPIO0_OR, 0); /* pull prg low */
/*
/* booting FPGA failed */
#ifndef FPGA_DEBUG
/* set up serial port with default baudrate */
- (void) get_clocks ();
+ (void)get_clocks();
gd->baudrate = CONFIG_BAUDRATE;
- serial_init ();
+ serial_init();
console_init_f();
#endif
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not low after "
+ "asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not high after "
+ "deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
+ printf("(Timeout: DONE not high after "
+ "programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
- for (i=0; i<4; i++) {
+ for (i = 0; i < 4; i++) {
len = fpgadata[index];
- printf("FPGA: %s\n", &(fpgadata[index+1]));
- index += len+3;
+ printf("FPGA: %s\n", &(fpgadata[index + 1]));
+ index += len + 3;
}
- putc ('\n');
+ putc('\n');
/* delayed reboot */
- for (i=20; i>0; i--) {
+ for (i = 20; i > 0; i--) {
printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
+ for (index = 0; index < 1000; index++)
udelay(1000);
}
- putc ('\n');
+ putc('\n');
do_reset(NULL, 0, 0, NULL);
}
}
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
+ * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens.
* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,
+ * INT0 highest priority */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
-/* ------------------------------------------------------------------------- */
-
int ctermm2(void)
{
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
return 0; /* no, board is cpci405 */
#else
- if ((*(unsigned char *)0xf0000400 == 0x00) &&
- (*(unsigned char *)0xf0000401 == 0x01))
+ if ((in_8((void*)0xf0000400) == 0x00) &&
+ (in_8((void*)0xf0000401) == 0x01))
return 0; /* no, board is cpci405 */
else
return -1; /* yes, board is cterm-m2 */
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
-#ifdef CONFIG_CPCI405_VER2
+#if defined(CONFIG_CPCI405_VER2)
{
unsigned char *dst;
ulong len = sizeof(fpgadata);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
+ (uchar *)fpgadata, &len) != 0) {
+ printf("GUNZIP ERROR - must RESET board to recover\n");
+ do_reset(NULL, 0, 0, NULL);
}
status = fpga_boot(dst, len);
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not low after "
+ "asserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not high after "
+ "deasserting PROGRAM*)\n ");
break;
case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
+ printf("(Timeout: DONE not high after "
+ "programming FPGA)\n ");
break;
}
/* display infos on fpgaimage */
index = 15;
- for (i=0; i<4; i++) {
+ for (i = 0; i < 4; i++) {
len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
+ printf("FPGA: %s\n", &(dst[index + 1]));
+ index += len + 3;
}
- putc ('\n');
+ putc('\n');
/* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
+ for (i = 20; i > 0; i--) {
+ printf("Rebooting in %2d seconds \r", i);
+ for (index = 0; index < 1000; index++)
udelay(1000);
}
- putc ('\n');
+ putc('\n');
do_reset(NULL, 0, 0, NULL);
}
/* display infos on fpgaimage */
index = 15;
- for (i=0; i<4; i++) {
+ for (i = 0; i < 4; i++) {
len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
+ printf("%s ", &(dst[index + 1]));
+ index += len + 3;
}
- putc ('\n');
+ putc('\n');
free(dst);
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
-#ifdef CONFIG_CPCI405_6U
+#if defined(CONFIG_CPCI405_6U)
+#error HIER GETH ES WEITER MIT IO ACCESSORS
if (cpci405_version() == 3) {
- volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
- volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
-
/*
* Enable outputs in fpga on version 3 board
*/
- *fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+ CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT);
/*
* Set outputs to 0
*/
- *leds = 0x00;
+ out_8((void*)CONFIG_SYS_LED_ADDR, 0x00);
/*
* Reset external DUART
*/
- *fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+ CONFIG_SYS_FPGA_MODE_DUART_RESET);
udelay(100);
- *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+ ~CONFIG_SYS_FPGA_MODE_DUART_RESET);
}
#endif
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Version 1.x detected!\n");
- puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n");
+ puts("*** Please use correct U-Boot version "
+ "(CPCI405 instead of CPCI4052)!\n\n");
}
}
-
#else /* CONFIG_CPCI405_VER2 */
-
-#if 0 /* test-only: code-plug now not relavant for ip-address any more */
- /*
- * Generate last byte of ip-addr from code-plug @ 0xf0000400
- */
- if (ctermm2()) {
- char str[32];
- unsigned char ipbyte = *(unsigned char *)0xf0000400;
-
- /*
- * Only overwrite ip-addr with allowed values
- */
- if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
- bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
- sprintf(str, "%ld.%ld.%ld.%ld",
- (bd->bi_ip_addr & 0xff000000) >> 24,
- (bd->bi_ip_addr & 0x00ff0000) >> 16,
- (bd->bi_ip_addr & 0x0000ff00) >> 8,
- (bd->bi_ip_addr & 0x000000ff));
- setenv("ipaddr", str);
- }
- }
-#endif
-
if (cpci405_version() >= 2) {
puts("\n*** U-Boot Version does not match Board Version!\n");
puts("*** CPCI-405 Board Version 2.x detected!\n");
- puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
+ puts("*** Please use correct U-Boot version "
+ "(CPCI4052 instead of CPCI405)!\n\n");
}
-
#endif /* CONFIG_CPCI405_VER2 */
/*
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00001000);
- return (0);
+ return 0;
}
/*
* Check Board Identity:
*/
-int checkboard (void)
+int checkboard(void)
{
#ifndef CONFIG_CPCI405_VER2
int index;
int len;
#endif
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_r("serial#", str, sizeof(str));
unsigned short ver;
- puts ("Board: ");
+ puts("Board: ");
- if (i == -1) {
- puts ("### No HW ID - assuming CPCI405");
- } else {
+ if (i == -1)
+ puts("### No HW ID - assuming CPCI405");
+ else
puts(str);
- }
ver = cpci405_version();
printf(" (Ver %d.x, ", ver);
-#if 0 /* test-only */
- if (ver >= 2) {
- volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
-
- if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
- puts ("FLASH Bank B, ");
- } else {
- puts ("FLASH Bank A, ");
- }
- }
-#endif
-
if (ctermm2()) {
char str[4];
setenv("boardid", str);
printf("CTERM-M2 - Id=%s)", str);
} else {
- if (cpci405_host()) {
- puts ("PCI Host Version)");
- } else {
- puts ("PCI Adapter Version)");
- }
+ if (cpci405_host())
+ puts("PCI Host Version)");
+ else
+ puts("PCI Adapter Version)");
}
#ifndef CONFIG_CPCI405_VER2
- puts ("\nFPGA: ");
+ puts("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
- for (i=0; i<4; i++) {
+ for (i = 0; i < 4; i++) {
len = fpgadata[index];
- printf("%s ", &(fpgadata[index+1]));
- index += len+3;
+ printf("%s ", &(fpgadata[index + 1]));
+ index += len + 3;
}
#endif
- putc ('\n');
+ putc('\n');
return 0;
}
void reset_phy(void)
{
-#ifdef CONFIG_LXT971_NO_SLEEP
+#if defined(CONFIG_LXT971_NO_SLEEP)
/*
* Disable sleep mode in LXT971
#endif
}
-#ifdef CONFIG_CPCI405_VER2
-#ifdef CONFIG_IDE_RESET
-
+#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET)
void ide_set_reset(int on)
{
- volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
-
/*
* Assert or deassert CompactFlash Reset Pin
*/
- if (on) { /* assert RESET */
- *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
- } else { /* release RESET */
- *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
+ if (on) { /* assert RESET */
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) &
+ ~CONFIG_SYS_FPGA_MODE_CF_RESET);
+ } else { /* release RESET */
+ out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR,
+ in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) |
+ CONFIG_SYS_FPGA_MODE_CF_RESET);
}
}
-#endif /* CONFIG_IDE_RESET */
-#endif /* CONFIG_CPCI405_VER2 */
+#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */
#if defined(CONFIG_PCI)
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
}
#endif /* defined(CONFIG_PCI) */
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+
+ __ft_board_setup(blob, bd);
+
+ /*
+ * Disable PCI in adapter mode.
+ */
+ if (!cpci405_host()) {
+ rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ if (rc) {
+ printf("Unable to update property status in PCI node, "
+ "err=%s\n",
+ fdt_strerror(rc));
+ }
+ }
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_CPCI405AB)
+#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE), \
+ in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE)) | \
+ CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#ifdef CONFIG_CPCI405AB
+#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE), \
+ in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_MODE)) & \
+ ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
- |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
- &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
- & CONFIG_SYS_FPGA_MODE_1WIRE)
+#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
+ CONFIG_SYS_FPGA_STATUS)) & \
+ CONFIG_SYS_FPGA_MODE_1WIRE)
/*
* Generate a 1-wire reset, return 1 if no presence detect was found,
{
int loop;
- for (loop=0; loop<8; loop++) {
+ for (loop = 0; loop < 8; loop++) {
OWWriteBit(data & 0x01);
data >>= 1;
}
{
int loop, result = 0;
- for (loop=0; loop<8; loop++) {
+ for (loop = 0; loop < 8; loop++) {
result >>= 1;
- if (OWReadBit()) {
+ if (OWReadBit())
result |= 0x80;
- }
}
return result;
int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- volatile unsigned short val;
+ unsigned short val;
int result;
int i;
unsigned char ow_id[6];
/*
* Clear 1-wire bit (open drain with pull-up)
*/
- val = *(volatile unsigned short *)0xf0400000;
- val &= ~0x1000; /* clear 1-wire bit */
- *(volatile unsigned short *)0xf0400000 = val;
+ val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+ CONFIG_SYS_FPGA_MODE));
+ val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
+ out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
+ CONFIG_SYS_FPGA_MODE), val);
result = OWTouchReset();
- if (result != 0) {
+ if (result != 0)
puts("No 1-wire device detected!\n");
- }
OWWriteByte(0x33); /* send read rom command */
OWReadByte(); /* skip family code ( == 0x01) */
- for (i=0; i<6; i++) {
+ for (i = 0; i < 6; i++)
ow_id[i] = OWReadByte();
- }
ow_crc = OWReadByte(); /* read crc */
- sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
+ sprintf(str, "%08X%04X",
+ *(unsigned int *)&ow_id[0],
+ *(unsigned short *)&ow_id[4]);
printf("Setting environment variable 'ow_id' to %s\n", str);
setenv("ow_id", str);
NULL
);
-#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
-#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
/*
* Write backplane ip-address...
IPaddr_t ipaddr;
buf = malloc(CONFIG_ENV_SIZE_2);
- if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
+ (uchar *)buf, CONFIG_ENV_SIZE_2))
puts("\nError reading backplane EEPROM!\n");
- } else {
- crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+ else {
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
if (crc != *(ulong *)buf) {
- printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
+ printf("ERROR: crc mismatch %08lx %08lx\n",
+ crc, *(ulong *)buf);
return -1;
}
memset(buf, 0, CONFIG_ENV_SIZE_2);
sprintf(str, "bp_ip=%s", argv[1]);
strcpy(buf+4, str);
- crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
*(ulong *)buf = crc;
- if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+ if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
+ 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
puts("\nError writing backplane EEPROM!\n");
- }
free(buf);
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned char *dst;
+ unsigned char fctr;
ulong len = sizeof(fpgadata);
int status;
int index;
out_8(duart0_mcr, 0x08);
out_8(duart1_mcr, 0x08);
+ /*
+ * Enable auto RS485 mode in 2nd external uart
+ */
+ out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */
+ fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */
+ fctr |= 0x08; /* enable RS485 mode */
+ out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */
+ out_8((void *)DUART1_BA + 3, 0); /* write LCR */
+
return (0);
}
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
- int pcie_configured = io_sel >= 1;
+ int pcie_configured = io_sel >= 6;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
- int pcie_configured = io_sel & 6;
+ int pcie_configured = io_sel >= 2;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
- int pcie_configured = io_sel & 4;
+ int pcie_configured = io_sel >= 4;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
(host_agent == 5) || (host_agent == 6);
- int pcie_configured = io_sel >= 1;
+ int pcie_configured = (io_sel == 0x7);
struct pci_region *r = hose->regions;
u32 temp32;
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
(host_agent == 6) || (host_agent == 0);
- int pcie_configured = io_sel & 4;
+ int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
struct pci_region *r = hose->regions;
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
- int pcie_configured = io_sel & 6;
+ int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
+ (io_sel == 0x7) || (io_sel == 0xb) ||
+ (io_sel == 0xc) || (io_sel == 0xf);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
- SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
COBJS := m501sk.o eeprom.o
-SOBJS := memsetup.o
-
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifdef CONFIG_BOOTBINFUNC
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP 0xFFFFFF50
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER 0xFFFFFF54
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR 0xFFFFFF04
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR 0xFFFFFF08
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR 0xFFFFFF64
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0 0xFFFFFF70
-#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR 0xFFFFFC2C
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR 0xFFFFFC30
-/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
-#define MCKR_VAL 0x00000202
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR 0xFFFFF804
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA 0xFFFFFF60
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR 0xFFFFFF94
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl lowlevelinit
-lowlevelinit:
- /* memory control configuration */
- /* this isn't very elegant, but what the heck */
- ldr r0, =SMRDATA
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- add r2, r0, #80
-0:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 0b
- /* delay - this is all done by guess */
- ldr r0, =0x00010000
-1:
- subs r0, r0, #1
- bhi 1b
- ldr r0, =SMRDATA1
- ldr r1, _TEXT_BASE
- sub r0, r0, r1
- add r2, r0, #176
-2:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 2b
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-
-SMRDATA:
- .word MC_PUIA
- .word MC_PUIA_VAL
- .word MC_PUP
- .word MC_PUP_VAL
- .word MC_PUER
- .word MC_PUER_VAL
- .word MC_ASR
- .word MC_ASR_VAL
- .word MC_AASR
- .word MC_AASR_VAL
- .word EBI_CFGR
- .word EBI_CFGR_VAL
- .word SMC_CSR0
- .word SMC_CSR0_VAL
- .word PLLAR
- .word PLLAR_VAL
- .word PLLBR
- .word PLLBR_VAL
- .word MCKR
- .word MCKR_VAL
- /* SMRDATA is 80 bytes long */
- /* here there's a delay of 100 */
-SMRDATA1:
- .word PIOC_ASR
- .word PIOC_ASR_VAL
- .word PIOC_BSR
- .word PIOC_BSR_VAL
- .word PIOC_PDR
- .word PIOC_PDR_VAL
- .word EBI_CSA
- .word EBI_CSA_VAL
- .word SDRC_CR
- .word SDRC_CR_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL1
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL2
- .word SDRAM1
- .word SDRAM_VAL
- .word SDRC_TR
- .word SDRC_TR_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL3
- .word SDRAM
- .word SDRAM_VAL
- /* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_BOOTBINFUNC */
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
- if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
} else {
lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include <asm/macro.h>
.global lowlevel_init
/*
* Set frequency multipliers and dividers in FRQCR.
*/
- mov.l WTCSR_A,r1
- mov.l WTCSR_D,r0
- mov.w r0,@r1
+ write16 WTCSR_A, WTCSR_D
- mov.l WTCNT_A,r1
- mov.l WTCNT_D,r0
- mov.w r0,@r1
+ write16 WTCNT_A, WTCNT_D
- mov.l FRQCR_A,r1
- mov.l FRQCR_D,r0
- mov.w r0,@r1
+ write16 FRQCR_A, FRQCR_D
/*
* Setup CS0 (Flash).
*/
- mov.l CS0BCR_A, r1
- mov.l CS0BCR_D, r0
- mov.l r0, @r1
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS0WCR_A, r1
- mov.l CS0WCR_D, r0
- mov.l r0, @r1
+ write32 CS0WCR_A, CS0WCR_D
/*
* Setup CS3 (SDRAM).
*/
- mov.l CS3BCR_A, r1
- mov.l CS3BCR_D, r0
- mov.l r0, @r1
+ write32 CS3BCR_A, CS3BCR_D
- mov.l CS3WCR_A, r1
- mov.l CS3WCR_D, r0
- mov.l r0, @r1
+ write32 CS3WCR_A, CS3WCR_D
- mov.l SDCR_A, r1
- mov.l SDCR_D1, r0
- mov.l r0, @r1
+ write32 SDCR_A, SDCR_D1
- mov.l RTCSR_A, r1
- mov.l RTCSR_D, r0
- mov.l r0, @r1
+ write32 RTCSR_A, RTCSR_D
- mov.l RTCNT_A, r1
- mov.l RTCNT_D, r0
- mov.l r0, @r1
+ write32 RTCNT_A, RTCNT_D
- mov.l RTCOR_A, r1
- mov.l RTCOR_D, r0
- mov.l r0, @r1
+ write32 RTCOR_A, RTCOR_D
- mov.l SDCR_A, r1
- mov.l SDCR_D2, r0
- mov.l r0, @r1
+ write32 SDCR_A, SDCR_D2
mov.l SDMR3_A, r1
mov.l SDMR3_D, r0
/*
* Spansion S29GL256N11 @ 48 MHz
*/
-CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */
-CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+/* 1 idle cycle inserted, normal space, 16 bit */
+CS0BCR_D: .long 0x12490400
+/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
+CS0WCR_D: .long 0x00000340
/*
* Samsung K4S511632B-UL75 @ 48 MHz
* Micron MT48LC32M16A2-75 @ 48 MHz
*/
-CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
-CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
-SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */
-SDCR_D2: .long 0x00000812 /* refresh */
-RTCSR_D: .long 0xA55A0008 /* 1/4, once */
-RTCNT_D: .long 0xA55A005D /* count 93 */
-RTCOR_D: .long 0xa55a005d /* count 93 */
-SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */
+/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
+CS3BCR_D: .long 0x10004400
+/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
+CS3WCR_D: .long 0x00000091
+/* no refresh, 13 rows, 10 cols, NO bank active mode */
+SDCR_D1: .long 0x00000012
+SDCR_D2: .long 0x00000812 /* refresh */
+RTCSR_D: .long 0xA55A0008 /* 1/4, once */
+RTCNT_D: .long 0xA55A005D /* count 93 */
+RTCOR_D: .long 0xa55a005d /* count 93 */
+/* mode register CL2, burst read and SINGLE WRITE */
+SDMR3_D: .long 0x440
/*
* Registers
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
*
- * (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
lowlevel_init:
- /* Address of Cache Control Register */
- mov.l CCR_A, r1
- /*Instruction Cache Invalidate */
- mov.l CCR_D, r0
- mov.l r0, @r1
+ /*
+ * Cache Control Register
+ * Instruction Cache Invalidate
+ */
+ write32 CCR_A, CCR_D
- /* Address of MMU Control Register */
- mov.l MMUCR_A, r1
- /* TI == TLB Invalidate bit */
- mov.l MMUCR_D, r0
- mov.l r0, @r1
+ /*
+ * Address of MMU Control Register
+ * TI == TLB Invalidate bit
+ */
+ write32 MMUCR_A, MMUCR_D
/* Address of Power Control Register 0 */
- mov.l MSTPCR0_A, r1
- mov.l MSTPCR0_D, r0
- mov.l r0, @r1
+ write32 MSTPCR0_A, MSTPCR0_D
/* Address of Power Control Register 2 */
- mov.l MSTPCR2_A, r1
- mov.l MSTPCR2_D, r0
- mov.l r0, @r1
+ write32 MSTPCR2_A, MSTPCR2_D
- mov.l SBSCR_A, r1
- mov.w SBSCR_D, r0
- mov.w r0, @r1
+ write16 SBSCR_A, SBSCR_D
- mov.l PSCR_A, r1
- mov.w PSCR_D, r0
- mov.w r0, @r1
+ write16 PSCR_A, PSCR_D
/* 0xA4520004 (Watchdog Control / Status Register) */
-! mov.l RWTCSR_A, r1
- /* 0xA507 -> timer_STOP/WDT_CLK=max */
-! mov.w RWTCSR_D_1, r0
-! mov.w r0, @r1
+! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
/* 0xA4520000 (Watchdog Count Register) */
- mov.l RWTCNT_A, r1
- /*0x5A00 -> Clear */
- mov.w RWTCNT_D, r0
- mov.w r0, @r1
+ write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
/* 0xA4520004 (Watchdog Control / Status Register) */
- mov.l RWTCSR_A, r1
- /* 0xA504 -> timer_STOP/CLK=500ms */
- mov.w RWTCSR_D_2, r0
- mov.w r0, @r1
+ write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
/* 0xA4150000 Frequency control register */
- mov.l FRQCR_A, r1
- mov.l FRQCR_D, r0 !
- mov.l r0, @r1
+ write32 FRQCR_A, FRQCR_D
- mov.l CCR_A, r1
- mov.l CCR_D_2, r0
- mov.l r0, @r1
+ write32 CCR_A, CCR_D_2
bsc_init:
- mov.l PSELA_A, r1
- mov.w PSELA_D, r0
- mov.w r0, @r1
+ write16 PSELA_A, PSELA_D
- mov.l DRVCR_A, r1
- mov.w DRVCR_D, r0
- mov.w r0, @r1
+ write16 DRVCR_A, DRVCR_D
- mov.l PCCR_A, r1
- mov.w PCCR_D, r0
- mov.w r0, @r1
+ write16 PCCR_A, PCCR_D
- mov.l PECR_A, r1
- mov.w PECR_D, r0
- mov.w r0, @r1
+ write16 PECR_A, PECR_D
- mov.l PJCR_A, r1
- mov.w PJCR_D, r0
- mov.w r0, @r1
+ write16 PJCR_A, PJCR_D
- mov.l PXCR_A, r1
- mov.w PXCR_D, r0
- mov.w r0, @r1
+ write16 PXCR_A, PXCR_D
- mov.l CMNCR_A, r1 ! CMNCR address -> R1
- mov.l CMNCR_D, r0 ! CMNCR data -> R0
- mov.l r0, @r1 ! CMNCR set
+ write32 CMNCR_A, CMNCR_D
- mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
- mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
- mov.l r0, @r1 ! CS0BCR set
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
- mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
- mov.l r0, @r1 ! CS2BCR set
+ write32 CS2BCR_A, CS2BCR_D
- mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
- mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
- mov.l r0, @r1 ! CS4BCR set
+ write32 CS4BCR_A, CS4BCR_D
- mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
- mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
- mov.l r0, @r1 ! CS5ABCR set
+ write32 CS5ABCR_A, CS5ABCR_D
- mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
- mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
- mov.l r0, @r1 ! CS5BBCR set
+ write32 CS5BBCR_A, CS5BBCR_D
- mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
- mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
- mov.l r0, @r1 ! CS6ABCR set
+ write32 CS6ABCR_A, CS6ABCR_D
- mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
- mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
- mov.l r0, @r1 ! CS0WCR set
+ write32 CS0WCR_A, CS0WCR_D
- mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
- mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
- mov.l r0, @r1 ! CS2WCR set
+ write32 CS2WCR_A, CS2WCR_D
- mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
- mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
- mov.l r0, @r1 ! CS4WCR set
+ write32 CS4WCR_A, CS4WCR_D
- mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
- mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
- mov.l r0, @r1 ! CS5AWCR set
+ write32 CS5AWCR_A, CS5AWCR_D
- mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
- mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
- mov.l r0, @r1 ! CS5BWCR set
+ write32 CS5BWCR_A, CS5BWCR_D
- mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
- mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
- mov.l r0, @r1 ! CS6AWCR set
+ write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
- mov.l SDCR_A, r1 ! SB_SDCR address -> R1
- mov.l SDCR_D, r0 ! SB_SDCR data -> R0
- mov.l r0, @r1 ! SB_SDCR set
+ write32 SDCR_A, SDCR_D
- mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
- mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
- mov.l r0, @r1 ! SB_SDWCR set
+ write32 SDWCR_A, SDWCR_D
- mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
- mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
- mov.l r0, @r1 ! SB_SDPCR set
+ write32 SDPCR_A, SDPCR_D
- mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
- mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
- mov.l r0, @r1 ! SB_RTCOR set
+ write32 RTCOR_A, RTCOR_D
- mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
- mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
- mov.l r0, @r1 ! SB_RTCSR set
+ write32 RTCSR_A, RTCSR_D
- mov.l SDMR3_A, r1 ! SDMR3 address -> R1
- mov #0x00, r0 ! SDMR3 data -> R0
- mov.b r0, @r1 ! SDMR3 set
+ write8 SDMR3_A, SDMR3_D
- ! BL bit off (init = ON) (?!?)
+ ! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
MSTPCR2_D: .long 0xffffffff
FRQCR_D: .long 0x07022538
-PSELA_A: .long 0xa405014E
-PSELA_D: .word 0x0A10
+PSELA_A: .long 0xa405014E
+PSELA_D: .word 0x0A10
.align 2
-DRVCR_A: .long 0xa405018A
-DRVCR_D: .word 0x0554
+DRVCR_A: .long 0xa405018A
+DRVCR_D: .word 0x0554
.align 2
-PCCR_A: .long 0xa4050104
-PCCR_D: .word 0x8800
+PCCR_A: .long 0xa4050104
+PCCR_D: .word 0x8800
.align 2
-PECR_A: .long 0xa4050108
-PECR_D: .word 0x0000
+PECR_A: .long 0xa4050108
+PECR_D: .word 0x0000
.align 2
-PJCR_A: .long 0xa4050110
-PJCR_D: .word 0x1000
+PJCR_A: .long 0xa4050110
+PJCR_D: .word 0x1000
.align 2
-PXCR_A: .long 0xa4050148
-PXCR_D: .word 0x0AAA
+PXCR_A: .long 0xa4050148
+PXCR_D: .word 0x0AAA
.align 2
CMNCR_A: .long CMNCR
RTCSR_A: .long SBSC_RTCSR
RTCSR_D: .long 0xA55A0010
SDMR3_A: .long 0xFE500180
+SDMR3_D: .long 0x0
.align 1
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
#ifdef CONFIG_CPU_SH7751
-#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
-#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
+#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
+#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MARUBUN_PCCARD
-#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
- A3:2 A2:15 A1:15 A0:6 A0B:7 */
+#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:6 A0B:7 */
#else /* CONFIG_MARUBUN_PCCARD */
-#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
- A3:2 A2:15 A1:15 A0:6 A0B:7 */
+#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:6 A0B:7 */
#endif /* CONFIG_MARUBUN_PCCARD */
-#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
- A2: 1-3 A1: 1-3 A0: 0-1 */
-#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
-#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
-#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
-#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
+#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
+ A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
+#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
+#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#else /* CONFIG_CPU_SH7751 */
-#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
-#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
-#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
- A3:2 A2:15 A1:15 A0:15 A0B:7 */
-#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
- A2: 1-3 A1: 1-3 A0: 0-1 */
-#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
-#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
-#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
-#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
+#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
+#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
+#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
+ A3:2 A2:15 A1:15 A0:15 A0B:7 */
+#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
+ A2: 1-3 A1: 1-3 A0: 0-1 */
+#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
+#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
+#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
+#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#endif /* CONFIG_CPU_SH7751 */
.global lowlevel_init
.text
- .align 2
+ .align 2
lowlevel_init:
- mov.l CCR_A, r1 ! CCR Address
- mov.l CCR_D_DISABLE, r0 ! CCR Data
- mov.l r0, @r1
+ write32 CCR_A, CCR_D_DISABLE
init_bsc:
- mov.l FRQCR_A,r1 /* FRQCR Address */
- mov.l FRQCR_D,r0 /* FRQCR Data */
- mov.w r0,@r1
+ write16 FRQCR_A, FRQCR_D
- mov.l BCR1_A,r1 /* BCR1 Address */
- mov.l BCR1_D,r0 /* BCR1 Data */
- mov.l r0,@r1
+ write32 BCR1_A, BCR1_D
- mov.l BCR2_A,r1 /* BCR2 Address */
- mov.l BCR2_D,r0 /* BCR2 Data */
- mov.w r0,@r1
+ write16 BCR2_A, BCR2_D
- mov.l WCR1_A,r1 /* WCR1 Address */
- mov.l WCR1_D,r0 /* WCR1 Data */
- mov.l r0,@r1
+ write32 WCR1_A, WCR1_D
- mov.l WCR2_A,r1 /* WCR2 Address */
- mov.l WCR2_D,r0 /* WCR2 Data */
- mov.l r0,@r1
+ write32 WCR2_A, WCR2_D
- mov.l WCR3_A,r1 /* WCR3 Address */
- mov.l WCR3_D,r0 /* WCR3 Data */
- mov.l r0,@r1
+ write32 WCR3_A, WCR3_D
- mov.l MCR_A,r1 /* MCR Address */
- mov.l MCR_D1,r0 /* MCR Data1 */
- mov.l r0,@r1
+ write32 MCR_A, MCR_D1
- mov.l SDMR3_A,r1 /* Set SDRAM mode */
- mov #0,r0
- mov.b r0,@r1
+ /* Set SDRAM mode */
+ write8 SDMR3_A, SDMR3_D
! Do you need PCMCIA setting?
! If so, please add the lines here...
- mov.l RTCNT_A,r1 /* RTCNT Address */
- mov.l RTCNT_D,r0 /* RTCNT Data */
- mov.w r0,@r1
+ write16 RTCNT_A, RTCNT_D
+
+ write16 RTCOR_A, RTCOR_D
- mov.l RTCOR_A,r1 /* RTCOR Address */
- mov.l RTCOR_D,r0 /* RTCOR Data */
- mov.w r0,@r1
+ write16 RTCSR_A, RTCSR_D
- mov.l RTCSR_A,r1 /* RTCSR Address */
- mov.l RTCSR_D,r0 /* RTCSR Data */
- mov.w r0,@r1
+ write16 RFCR_A, RFCR_D
- mov.l RFCR_A,r1 /* RFCR Address */
- mov.l RFCR_D,r0 /* RFCR Data */
- mov.w r0,@r1 /* Clear reflesh counter */
/* Wait DRAM refresh 30 times */
- mov #30,r3
+ mov #30, r3
1:
- mov.w @r1,r0
- extu.w r0,r2
- cmp/hi r3,r2
+ mov.w @r1, r0
+ extu.w r0, r2
+ cmp/hi r3, r2
bf 1b
- mov.l MCR_A,r1 /* MCR Address */
- mov.l MCR_D2,r0 /* MCR Data2 */
- mov.l r0,@r1
+ write32 MCR_A, MCR_D2
- mov.l SDMR3_A,r1 /* Set SDRAM mode */
- mov #0,r0
- mov.b r0,@r1
+ /* Set SDRAM mode */
+ write8 SDMR3_A, SDMR3_D
rts
- nop
+ nop
.align 2
-CCR_A: .long CCR
-CCR_D_DISABLE: .long 0x0808
+CCR_A: .long CCR
+CCR_D_DISABLE: .long 0x0808
FRQCR_A: .long FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R
RTCOR_A: .long RTCOR
RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
SDMR3_A: .long SDMR3_ADDRESS
+SDMR3_D: .long 0x00
MCR_A: .long MCR
MCR_D1: .long MCR_D1_VALUE
MCR_D2: .long MCR_D2_VALUE
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
*
- * (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
.align 2
lowlevel_init:
- mov.l CCR_A, r1 ! Address of Cache Control Register
- mov.l CCR_D, r0 ! Instruction Cache Invalidate
- mov.l r0, @r1
+ write32 CCR_A, CCR_D ! Address of Cache Control Register
+ ! Instruction Cache Invalidate
- mov.l MMUCR_A, r1 ! Address of MMU Control Register
- mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
- mov.l r0, @r1
+ write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
+ ! TI == TLB Invalidate bit
- mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
- mov.l MSTPCR0_D, r0 !
- mov.l r0, @r1
+ write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0
- mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
- mov.l MSTPCR2_D, r0 !
- mov.l r0, @r1
+ write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2
- mov.l PFC_PULCR_A, r1
- mov.w PFC_PULCR_D, r0
- mov.w r0,@r1
+ write16 PFC_PULCR_A, PFC_PULCR_D
- mov.l PFC_DRVCR_A, r1
- mov.w PFC_DRVCR_D, r0
- mov.w r0, @r1
+ write16 PFC_DRVCR_A, PFC_DRVCR_D
- mov.l SBSCR_A, r1 !
- mov.w SBSCR_D, r0 !
- mov.w r0, @r1
+ write16 SBSCR_A, SBSCR_D
- mov.l PSCR_A, r1 !
- mov.w PSCR_D, r0 !
- mov.w r0, @r1
+ write16 PSCR_A, PSCR_D
- mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
- mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
- mov.w r0, @r1
+ write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register)
+ ! 0xA507 -> timer_STOP / WDT_CLK = max
- mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
- mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
- mov.w r0, @r1
+ write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register)
+ ! 0x5A00 -> Clear
- mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
- mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
- mov.w r0, @r1
+ write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register)
+ ! 0xA504 -> timer_STOP / CLK = 500ms
- mov.l DLLFRQ_A, r1 ! 20080115
- mov.l DLLFRQ_D, r0 ! 20080115
- mov.l r0, @r1
+ write32 DLLFRQ_A, DLLFRQ_D ! 20080115
+ ! 20080115
- mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
- mov.l FRQCR_D, r0 ! 20080115
- mov.l r0, @r1
+ write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register
+ ! 20080115
- mov.l CCR_A, r1 ! Address of Cache Control Register
- mov.l CCR_D_2, r0 ! ??
- mov.l r0, @r1
+ write32 CCR_A, CCR_D_2 ! Address of Cache Control Register
+ ! ??
bsc_init:
- mov.l CMNCR_A, r1 ! CMNCR address -> R1
- mov.l CMNCR_D, r0 ! CMNCR data -> R0
- mov.l r0, @r1 ! CMNCR set
+ write32 CMNCR_A, CMNCR_D
- mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
- mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
- mov.l r0, @r1 ! CS0BCR set
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
- mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
- mov.l r0, @r1 ! CS4BCR set
+ write32 CS4BCR_A, CS4BCR_D
- mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
- mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
- mov.l r0, @r1 ! CS5ABCR set
+ write32 CS5ABCR_A, CS5ABCR_D
- mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
- mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
- mov.l r0, @r1 ! CS5BBCR set
+ write32 CS5BBCR_A, CS5BBCR_D
- mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
- mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
- mov.l r0, @r1 ! CS6ABCR set
+ write32 CS6ABCR_A, CS6ABCR_D
- mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
- mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
- mov.l r0, @r1 ! CS0WCR set
+ write32 CS0WCR_A, CS0WCR_D
- mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
- mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
- mov.l r0, @r1 ! CS4WCR set
+ write32 CS4WCR_A, CS4WCR_D
- mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
- mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
- mov.l r0, @r1 ! CS5AWCR set
+ write32 CS5AWCR_A, CS5AWCR_D
- mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
- mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
- mov.l r0, @r1 ! CS5BWCR set
+ write32 CS5BWCR_A, CS5BWCR_D
- mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
- mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
- mov.l r0, @r1 ! CS6AWCR set
+ write32 CS6AWCR_A, CS6AWCR_D
! SDRAM initialization
- mov.l SDCR_A, r1 ! SB_SDCR address -> R1
- mov.l SDCR_D, r0 ! SB_SDCR data -> R0
- mov.l r0, @r1 ! SB_SDCR set
+ write32 SDCR_A, SDCR_D
- mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
- mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
- mov.l r0, @r1 ! SB_SDWCR set
+ write32 SDWCR_A, SDWCR_D
- mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
- mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
- mov.l r0, @r1 ! SB_SDPCR set
+ write32 SDPCR_A, SDPCR_D
- mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
- mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
- mov.l r0, @r1 ! SB_RTCOR set
+ write32 RTCOR_A, RTCOR_D
- mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1
- mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0
- mov.l r0, @r1
+ write32 RTCNT_A, RTCNT_D
- mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
- mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
- mov.l r0, @r1 ! SB_RTCSR set
+ write32 RTCSR_A, RTCSR_D
- mov.l RFCR_A, r1 ! SB_RFCR address -> R1
- mov.l RFCR_D, r0 ! SB_RFCR data -> R0
- mov.l r0, @r1
+ write32 RFCR_A, RFCR_D
- mov.l SDMR3_A, r1 ! SDMR3 address -> R1
- mov #0x00, r0 ! SDMR3 data -> R0
- mov.b r0, @r1 ! SDMR3 set
+ write8 SDMR3_A, SDMR3_D
- ! BL bit off (init = ON) (?!?)
+ ! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
RFCR_D: .long 0xA55A0221
RTCSR_D: .long 0xA55A009a
SDMR3_A: .long 0xFE581180
+SDMR3_D: .long 0x0
SR_MASK_D: .long 0xEFFFFF0F
#include <config.h>
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
/*
* Board specific low level init code, called _very_ early in the
.align 2
lowlevel_init:
- mov.l DRVCRA_A, r1
- mov.l DRVCRA_D, r0
- mov.w r0, @r1
+ write16 DRVCRA_A, DRVCRA_D
- mov.l DRVCRB_A, r1
- mov.l DRVCRB_D, r0
- mov.w r0, @r1
+ write16 DRVCRB_A, DRVCRB_D
- mov.l RWTCSR_A, r1
- mov.l RWTCSR_D1, r0
- mov.w r0, @r1
+ write16 RWTCSR_A, RWTCSR_D1
- mov.l RWTCNT_A, r1
- mov.l RWTCNT_D, r0
- mov.w r0, @r1
+ write16 RWTCNT_A, RWTCNT_D
- mov.l RWTCSR_A, r1
- mov.l RWTCSR_D2, r0
- mov.w r0, @r1
+ write16 RWTCSR_A, RWTCSR_D2
- mov.l FRQCR_A, r1
- mov.l FRQCR_D, r0
- mov.l r0, @r1
+ write32 FRQCR_A, FRQCR_D
- mov.l CMNCR_A, r1
- mov.l CMNCR_D, r0
- mov.l r0, @r1
+ write32 CMNCR_A, CMNCR_D
- mov.l CS0BCR_A ,r1
- mov.l CS0BCR_D ,r0
- mov.l r0, @r1
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS4BCR_A ,r1
- mov.l CS4BCR_D ,r0
- mov.l r0, @r1
+ write32 CS4BCR_A, CS4BCR_D
- mov.l CS5ABCR_A ,r1
- mov.l CS5ABCR_D ,r0
- mov.l r0, @r1
+ write32 CS5ABCR_A, CS5ABCR_D
- mov.l CS5BBCR_A ,r1
- mov.l CS5BBCR_D ,r0
- mov.l r0, @r1
+ write32 CS5BBCR_A, CS5BBCR_D
- mov.l CS6ABCR_A ,r1
- mov.l CS6ABCR_D ,r0
- mov.l r0, @r1
+ write32 CS6ABCR_A, CS6ABCR_D
- mov.l CS6BBCR_A ,r1
- mov.l CS6BBCR_D ,r0
- mov.l r0, @r1
+ write32 CS6BBCR_A, CS6BBCR_D
- mov.l CS0WCR_A ,r1
- mov.l CS0WCR_D ,r0
- mov.l r0, @r1
+ write32 CS0WCR_A, CS0WCR_D
- mov.l CS4WCR_A ,r1
- mov.l CS4WCR_D ,r0
- mov.l r0, @r1
+ write32 CS4WCR_A, CS4WCR_D
- mov.l CS5AWCR_A ,r1
- mov.l CS5AWCR_D ,r0
- mov.l r0, @r1
+ write32 CS5AWCR_A, CS5AWCR_D
- mov.l CS5BWCR_A ,r1
- mov.l CS5BWCR_D ,r0
- mov.l r0, @r1
+ write32 CS5BWCR_A, CS5BWCR_D
- mov.l CS6AWCR_A ,r1
- mov.l CS6AWCR_D ,r0
- mov.l r0, @r1
+ write32 CS6AWCR_A, CS6AWCR_D
- mov.l CS6BWCR_A ,r1
- mov.l CS6BWCR_D ,r0
- mov.l r0, @r1
+ write32 CS6BWCR_A, CS6BWCR_D
- mov.l SBSC_SDCR_A, r1
- mov.l SBSC_SDCR_D1, r0
- mov.l r0, @r1
+ write32 SBSC_SDCR_A, SBSC_SDCR_D1
- mov.l SBSC_SDWCR_A, r1
- mov.l SBSC_SDWCR_D, r0
- mov.l r0, @r1
+ write32 SBSC_SDWCR_A, SBSC_SDWCR_D
- mov.l SBSC_SDPCR_A, r1
- mov.l SBSC_SDPCR_D, r0
- mov.l r0, @r1
+ write32 SBSC_SDPCR_A, SBSC_SDPCR_D
- mov.l SBSC_RTCSR_A, r1
- mov.l SBSC_RTCSR_D, r0
- mov.l r0, @r1
+ write32 SBSC_RTCSR_A, SBSC_RTCSR_D
- mov.l SBSC_RTCNT_A, r1
- mov.l SBSC_RTCNT_D, r0
- mov.l r0, @r1
+ write32 SBSC_RTCNT_A, SBSC_RTCNT_D
- mov.l SBSC_RTCOR_A, r1
- mov.l SBSC_RTCOR_D, r0
- mov.l r0, @r1
+ write32 SBSC_RTCOR_A, SBSC_RTCOR_D
- mov.l SBSC_SDMR3_A1, r1
- mov.l SBSC_SDMR3_D, r0
- mov.b r0, @r1
+ write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
- mov.l SBSC_SDMR3_A2, r1
- mov.l SBSC_SDMR3_D, r0
- mov.b r0, @r1
+ write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
mov.l SLEEP_CNT, r1
2: tst r1, r1
bf/s 2b
dt r1
- mov.l SBSC_SDMR3_A3, r1
- mov.l SBSC_SDMR3_D, r0
- mov.b r0, @r1
+ write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
- mov.l SBSC_SDCR_A, r1
- mov.l SBSC_SDCR_D2, r0
- mov.l r0, @r1
+ write32 SBSC_SDCR_A, SBSC_SDCR_D2
- mov.l CCR_A, r1
- mov.l CCR_D, r0
- mov.l r0, @r1
+ write32 CCR_A, CCR_D
- ! BL bit off (init = ON) (?!?)
+ ! BL bit off (init = ON) (?!?)
stc sr, r0 ! BL bit off(init=ON)
mov.l SR_MASK_D, r1
CMNCR_A: .long CMNCR
CS0BCR_A: .long CS0BCR
CS4BCR_A: .long CS4BCR
-CS5ABCR_A: .long CS5ABCR
+CS5ABCR_A: .long CS5ABCR
CS5BBCR_A: .long CS5BBCR
CS6ABCR_A: .long CS6ABCR
CS6BBCR_A: .long CS6BBCR
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
.global lowlevel_init
.text
lowlevel_init:
- mov.l CCR_A, r1
- mov.l CCR_D_D, r0
- mov.l r0,@r1
+ write32 CCR_A, CCR_D_D
- mov.l MMUCR_A,r1
- mov.l MMUCR_D,r0
- mov.l r0,@r1
+ write32 MMUCR_A, MMUCR_D
- mov.l BCR1_A,r1
- mov.l BCR1_D,r0
- mov.l r0,@r1
+ write32 BCR1_A, BCR1_D
- mov.l BCR2_A,r1
- mov.l BCR2_D,r0
- mov.w r0,@r1
+ write16 BCR2_A, BCR2_D
- mov.l BCR3_A,r1
- mov.l BCR3_D,r0
- mov.w r0,@r1
+ write16 BCR3_A, BCR3_D
- mov.l BCR4_A,r1
- mov.l BCR4_D,r0
- mov.l r0,@r1
+ write32 BCR4_A, BCR4_D
- mov.l WCR1_A,r1
- mov.l WCR1_D,r0
- mov.l r0,@r1
+ write32 WCR1_A, WCR1_D
- mov.l WCR2_A,r1
- mov.l WCR2_D,r0
- mov.l r0,@r1
+ write32 WCR2_A, WCR2_D
- mov.l WCR3_A,r1
- mov.l WCR3_D,r0
- mov.l r0,@r1
+ write32 WCR3_A, WCR3_D
- mov.l PCR_A,r1
- mov.l PCR_D,r0
- mov.w r0,@r1
+ write16 PCR_A, PCR_D
- mov.l LED_A,r1
- mov #0xff,r0
- mov.w r0,@r1
+ write16 LED_A, LED_D
- mov.l MCR_A,r1
- mov.l MCR_D1,r0
- mov.l r0,@r1
+ write32 MCR_A, MCR_D1
- mov.l RTCNT_A,r1
- mov.l RTCNT_D,r0
- mov.w r0,@r1
+ write16 RTCNT_A, RTCNT_D
- mov.l RTCOR_A,r1
- mov.l RTCOR_D,r0
- mov.w r0,@r1
+ write16 RTCOR_A, RTCOR_D
- mov.l RFCR_A,r1
- mov.l RFCR_D,r0
- mov.w r0,@r1
+ write16 RFCR_A, RFCR_D
- mov.l RTCSR_A,r1
- mov.l RTCSR_D,r0
- mov.w r0,@r1
+ write16 RTCSR_A, RTCSR_D
- mov.l SDMR3_A,r1
- mov #0x55,r0
- mov.b r0,@r1
+ write8 SDMR3_A, SDMR3_D0
/* Wait DRAM refresh 30 times */
- mov.l RFCR_A,r1
- mov #30,r3
+ mov.l RFCR_A, r1
+ mov #30, r3
1:
- mov.w @r1,r0
- extu.w r0,r2
- cmp/hi r3,r2
+ mov.w @r1, r0
+ extu.w r0, r2
+ cmp/hi r3, r2
bf 1b
- mov.l MCR_A,r1
- mov.l MCR_D2,r0
- mov.l r0,@r1
+ write32 MCR_A, MCR_D2
- mov.l SDMR3_A,r1
- mov #0,r0
- mov.b r0,@r1
+ write8 SDMR3_A, SDMR3_D1
- mov.l IRLMASK_A,r1
- mov.l IRLMASK_D,r0
- mov.l r0,@r1
+ write32 IRLMASK_A, IRLMASK_D
- mov.l CCR_A, r1
- mov.l CCR_D_E, r0
- mov.l r0, @r1
+ write32 CCR_A, CCR_D_E
rts
nop
WCR3_A: .long WCR3 /* WCR3 Address */
WCR3_D: .long 0x07777707
LED_A: .long 0x04000036 /* LED Address */
+LED_D: .long 0xFF /* LED Data */
RTCNT_A: .long RTCNT /* RTCNT Address */
RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
RTCOR_A: .long RTCOR /* RTCOR Address */
RTCSR_A: .long RTCSR /* RTCSR Address */
RTCSR_D: .long 0xA510 /* RTCSR Write Code */
SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */
-SDMR3_D: .long 0x55
+SDMR3_D0: .long 0x55
+SDMR3_D1: .long 0x00
MCR_A: .long MCR /* MCR Address */
MCR_D1: .long 0x081901F4 /* MRSET:'0' */
MCR_D2: .long 0x481901F4 /* MRSET:'1' */
#include <config.h>
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
/*
- * Board specific low level init code, called _very_ early in the
- * startup sequence. Relocation to SDRAM has not happened yet, no
- * stack is available, bss section has not been initialised, etc.
+ * Board specific low level init code, called _very_ early in the
+ * startup sequence. Relocation to SDRAM has not happened yet, no
+ * stack is available, bss section has not been initialised, etc.
*
- * (Note: As no stack is available, no subroutines can be called...).
+ * (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
lowlevel_init:
- mov.l CCR_A, r1 /* Address of Cache Control Register */
- mov.l CCR_D, r0 /* Instruction Cache Invalidate */
- mov.l r0, @r1
+ write32 CCR_A, CCR_D /* Address of Cache Control Register */
+ /* Instruction Cache Invalidate */
- mov.l FRQCR_A, r1 /* Frequency control register */
- mov.l FRQCR_D, r0
- mov.l r0, @r1
+ write32 FRQCR_A, FRQCR_D /* Frequency control register */
/* pin_multi_setting */
- mov.l BBG_PMMR_A,r1
- mov.l BBG_PMMR_D_PMSR1,r0
- mov.l r0,@r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1
- mov.l BBG_PMSR1_A,r1
- mov.l BBG_PMSR1_D,r0
- mov.l r0,@r1
+ write32 BBG_PMSR1_A, BBG_PMSR1_D
- mov.l BBG_PMMR_A,r1
- mov.l BBG_PMMR_D_PMSR2,r0
- mov.l r0,@r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2
- mov.l BBG_PMSR2_A,r1
- mov.l BBG_PMSR2_D,r0
- mov.l r0,@r1
+ write32 BBG_PMSR2_A, BBG_PMSR2_D
- mov.l BBG_PMMR_A,r1
- mov.l BBG_PMMR_D_PMSR3,r0
- mov.l r0,@r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3
- mov.l BBG_PMSR3_A,r1
- mov.l BBG_PMSR3_D,r0
- mov.l r0,@r1
+ write32 BBG_PMSR3_A, BBG_PMSR3_D
- mov.l BBG_PMMR_A,r1
- mov.l BBG_PMMR_D_PMSR4,r0
- mov.l r0,@r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4
- mov.l BBG_PMSR4_A,r1
- mov.l BBG_PMSR4_D,r0
- mov.l r0,@r1
+ write32 BBG_PMSR4_A, BBG_PMSR4_D
- mov.l BBG_PMMR_A,r1
- mov.l BBG_PMMR_D_PMSRG,r0
- mov.l r0,@r1
+ write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG
- mov.l BBG_PMSRG_A,r1
- mov.l BBG_PMSRG_D,r0
- mov.l r0,@r1
+ write32 BBG_PMSRG_A, BBG_PMSRG_D
/* cpg_setting */
- mov.l FRQCR_A,r1
- mov.l FRQCR_D,r0
- mov.l r0,@r1
+ write32 FRQCR_A, FRQCR_D
- mov.l DLLCSR_A,r1
- mov.l DLLCSR_D,r0
- mov.l r0,@r1
+ write32 DLLCSR_A, DLLCSR_D
nop
nop
nop
/* wait 200us */
- mov.l REPEAT0_R3,r3
- mov #0,r2
+ mov.l REPEAT0_R3, r3
+ mov #0, r2
repeat0:
- add #1,r2
- cmp/hs r3,r2
- bf repeat0
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
nop
/* bsc_setting */
- mov.l MMSELR_A,r1
- mov.l MMSELR_D,r0
- mov.l r0,@r1
+ write32 MMSELR_A, MMSELR_D
- mov.l BCR_A,r1
- mov.l BCR_D,r0
- mov.l r0,@r1
+ write32 BCR_A, BCR_D
- mov.l CS0BCR_A,r1
- mov.l CS0BCR_D,r0
- mov.l r0,@r1
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS1BCR_A,r1
- mov.l CS1BCR_D,r0
- mov.l r0,@r1
+ write32 CS1BCR_A, CS1BCR_D
- mov.l CS2BCR_A,r1
- mov.l CS2BCR_D,r0
- mov.l r0,@r1
+ write32 CS2BCR_A, CS2BCR_D
- mov.l CS4BCR_A,r1
- mov.l CS4BCR_D,r0
- mov.l r0,@r1
+ write32 CS4BCR_A, CS4BCR_D
- mov.l CS5BCR_A,r1
- mov.l CS5BCR_D,r0
- mov.l r0,@r1
+ write32 CS5BCR_A, CS5BCR_D
- mov.l CS6BCR_A,r1
- mov.l CS6BCR_D,r0
- mov.l r0,@r1
+ write32 CS6BCR_A, CS6BCR_D
- mov.l CS0WCR_A,r1
- mov.l CS0WCR_D,r0
- mov.l r0,@r1
+ write32 CS0WCR_A, CS0WCR_D
- mov.l CS1WCR_A,r1
- mov.l CS1WCR_D,r0
- mov.l r0,@r1
+ write32 CS1WCR_A, CS1WCR_D
- mov.l CS2WCR_A,r1
- mov.l CS2WCR_D,r0
- mov.l r0,@r1
+ write32 CS2WCR_A, CS2WCR_D
- mov.l CS4WCR_A,r1
- mov.l CS4WCR_D,r0
- mov.l r0,@r1
+ write32 CS4WCR_A, CS4WCR_D
- mov.l CS5WCR_A,r1
- mov.l CS5WCR_D,r0
- mov.l r0,@r1
+ write32 CS5WCR_A, CS5WCR_D
- mov.l CS6WCR_A,r1
- mov.l CS6WCR_D,r0
- mov.l r0,@r1
+ write32 CS6WCR_A, CS6WCR_D
- mov.l CS5PCR_A,r1
- mov.l CS5PCR_D,r0
- mov.l r0,@r1
+ write32 CS5PCR_A, CS5PCR_D
- mov.l CS6PCR_A,r1
- mov.l CS6PCR_D,r0
- mov.l r0,@r1
+ write32 CS6PCR_A, CS6PCR_D
/* ddr_setting */
/* wait 200us */
- mov.l REPEAT0_R3,r3
- mov #0,r2
+ mov.l REPEAT0_R3, r3
+ mov #0, r2
repeat1:
- add #1,r2
- cmp/hs r3,r2
- bf repeat1
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat1
nop
- mov.l MIM_U_A,r0
- mov.l MIM_U_D,r1
+ mov.l MIM_U_A, r0
+ mov.l MIM_U_D, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
- mov.l MIM_L_A,r0
- mov.l MIM_L_D0,r1
+ mov.l MIM_L_A, r0
+ mov.l MIM_L_D0, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
- mov.l STR_L_A,r0
- mov.l STR_L_D,r1
+ mov.l STR_L_A, r0
+ mov.l STR_L_D, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
- mov.l SDR_L_A,r0
- mov.l SDR_L_D,r1
+ mov.l SDR_L_A, r0
+ mov.l SDR_L_D, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l SCR_L_A,r0
- mov.l SCR_L_D0,r1
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D0, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
- mov.l SCR_L_A,r0
- mov.l SCR_L_D1,r1
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D1, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l EMRS_A,r0
- mov.l EMRS_D,r1
+ mov.l EMRS_A, r0
+ mov.l EMRS_D, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l MRS1_A,r0
- mov.l MRS1_D,r1
+ mov.l MRS1_A, r0
+ mov.l MRS1_D, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l SCR_L_A,r0
- mov.l SCR_L_D2,r1
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D2, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l SCR_L_A,r0
- mov.l SCR_L_D3,r1
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D3, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l SCR_L_A,r0
- mov.l SCR_L_D4,r1
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D4, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l MRS2_A,r0
- mov.l MRS2_D,r1
+ mov.l MRS2_A, r0
+ mov.l MRS2_D, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
nop
nop
nop
- mov.l SCR_L_A,r0
- mov.l SCR_L_D5,r1
+ mov.l SCR_L_A, r0
+ mov.l SCR_L_D5, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
/* wait 200us */
- mov.l REPEAT0_R1,r3
- mov #0,r2
+ mov.l REPEAT0_R1, r3
+ mov #0, r2
repeat2:
- add #1,r2
- cmp/hs r3,r2
- bf repeat2
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat2
synco
- mov.l MIM_L_A,r0
- mov.l MIM_L_D1,r1
+ mov.l MIM_L_A, r0
+ mov.l MIM_L_D1, r1
synco
- mov.l r1,@r0
+ mov.l r1, @r0
synco
rts
nop
.align 4
-RWTCSR_D_1: .word 0xA507
-RWTCSR_D_2: .word 0xA507
-RWTCNT_D: .word 0x5A00
+RWTCSR_D_1: .word 0xA507
+RWTCSR_D_2: .word 0xA507
+RWTCNT_D: .word 0x5A00
.align 2
-BBG_PMMR_A: .long 0xFF800010
-BBG_PMSR1_A: .long 0xFF800014
-BBG_PMSR2_A: .long 0xFF800018
-BBG_PMSR3_A: .long 0xFF80001C
-BBG_PMSR4_A: .long 0xFF800020
-BBG_PMSRG_A: .long 0xFF800024
-
-BBG_PMMR_D_PMSR1: .long 0xffffbffd
-BBG_PMSR1_D: .long 0x00004002
-BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
-BBG_PMSR2_D: .long 0x03de5800
-BBG_PMMR_D_PMSR3: .long 0xfffffff8
-BBG_PMSR3_D: .long 0x00000007
-BBG_PMMR_D_PMSR4: .long 0xdffdfff9
-BBG_PMSR4_D: .long 0x20020006
-BBG_PMMR_D_PMSRG: .long 0xffffffff
-BBG_PMSRG_D: .long 0x00000000
-
-FRQCR_A: .long FRQCR
-DLLCSR_A: .long 0xffc40010
-FRQCR_D: .long 0x40233035
-DLLCSR_D: .long 0x00000000
+BBG_PMMR_A: .long 0xFF800010
+BBG_PMSR1_A: .long 0xFF800014
+BBG_PMSR2_A: .long 0xFF800018
+BBG_PMSR3_A: .long 0xFF80001C
+BBG_PMSR4_A: .long 0xFF800020
+BBG_PMSRG_A: .long 0xFF800024
+
+BBG_PMMR_D_PMSR1: .long 0xffffbffd
+BBG_PMSR1_D: .long 0x00004002
+BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
+BBG_PMSR2_D: .long 0x03de5800
+BBG_PMMR_D_PMSR3: .long 0xfffffff8
+BBG_PMSR3_D: .long 0x00000007
+BBG_PMMR_D_PMSR4: .long 0xdffdfff9
+BBG_PMSR4_D: .long 0x20020006
+BBG_PMMR_D_PMSRG: .long 0xffffffff
+BBG_PMSRG_D: .long 0x00000000
+
+FRQCR_A: .long FRQCR
+DLLCSR_A: .long 0xffc40010
+FRQCR_D: .long 0x40233035
+DLLCSR_D: .long 0x00000000
/* for DDR-SDRAM */
-MIM_U_A: .long MIM_1
-MIM_L_A: .long MIM_2
-SCR_U_A: .long SCR_1
-SCR_L_A: .long SCR_2
-STR_U_A: .long STR_1
-STR_L_A: .long STR_2
-SDR_U_A: .long SDR_1
-SDR_L_A: .long SDR_2
-
-EMRS_A: .long 0xFEC02000
-MRS1_A: .long 0xFEC00B08
-MRS2_A: .long 0xFEC00308
-
-MIM_U_D: .long 0x00004000
-MIM_L_D0: .long 0x03e80009
-MIM_L_D1: .long 0x03e80209
-SCR_L_D0: .long 0x3
-SCR_L_D1: .long 0x2
-SCR_L_D2: .long 0x2
-SCR_L_D3: .long 0x4
-SCR_L_D4: .long 0x4
-SCR_L_D5: .long 0x0
-STR_L_D: .long 0x000f0000
-SDR_L_D: .long 0x00000400
-EMRS_D: .long 0x0
-MRS1_D: .long 0x0
-MRS2_D: .long 0x0
+MIM_U_A: .long MIM_1
+MIM_L_A: .long MIM_2
+SCR_U_A: .long SCR_1
+SCR_L_A: .long SCR_2
+STR_U_A: .long STR_1
+STR_L_A: .long STR_2
+SDR_U_A: .long SDR_1
+SDR_L_A: .long SDR_2
+
+EMRS_A: .long 0xFEC02000
+MRS1_A: .long 0xFEC00B08
+MRS2_A: .long 0xFEC00308
+
+MIM_U_D: .long 0x00004000
+MIM_L_D0: .long 0x03e80009
+MIM_L_D1: .long 0x03e80209
+SCR_L_D0: .long 0x3
+SCR_L_D1: .long 0x2
+SCR_L_D2: .long 0x2
+SCR_L_D3: .long 0x4
+SCR_L_D4: .long 0x4
+SCR_L_D5: .long 0x0
+STR_L_D: .long 0x000f0000
+SDR_L_D: .long 0x00000400
+EMRS_D: .long 0x0
+MRS1_D: .long 0x0
+MRS2_D: .long 0x0
/* Cache Controller */
-CCR_A: .long CCR
-MMUCR_A: .long MMUCR
-RWTCNT_A: .long WTCNT
+CCR_A: .long CCR
+MMUCR_A: .long MMUCR
+RWTCNT_A: .long WTCNT
-CCR_D: .long 0x0000090b
-CCR_D_2: .long 0x00000103
-MMUCR_D: .long 0x00000004
-MSTPCR0_D: .long 0x00001001
-MSTPCR2_D: .long 0xffffffff
+CCR_D: .long 0x0000090b
+CCR_D_2: .long 0x00000103
+MMUCR_D: .long 0x00000004
+MSTPCR0_D: .long 0x00001001
+MSTPCR2_D: .long 0xffffffff
/* local Bus State Controller */
-MMSELR_A: .long MMSELR
-BCR_A: .long BCR
-CS0BCR_A: .long CS0BCR
-CS1BCR_A: .long CS1BCR
-CS2BCR_A: .long CS2BCR
-CS4BCR_A: .long CS4BCR
-CS5BCR_A: .long CS5BCR
-CS6BCR_A: .long CS6BCR
-CS0WCR_A: .long CS0WCR
-CS1WCR_A: .long CS1WCR
-CS2WCR_A: .long CS2WCR
-CS4WCR_A: .long CS4WCR
-CS5WCR_A: .long CS5WCR
-CS6WCR_A: .long CS6WCR
-CS5PCR_A: .long CS5PCR
-CS6PCR_A: .long CS6PCR
+MMSELR_A: .long MMSELR
+BCR_A: .long BCR
+CS0BCR_A: .long CS0BCR
+CS1BCR_A: .long CS1BCR
+CS2BCR_A: .long CS2BCR
+CS4BCR_A: .long CS4BCR
+CS5BCR_A: .long CS5BCR
+CS6BCR_A: .long CS6BCR
+CS0WCR_A: .long CS0WCR
+CS1WCR_A: .long CS1WCR
+CS2WCR_A: .long CS2WCR
+CS4WCR_A: .long CS4WCR
+CS5WCR_A: .long CS5WCR
+CS6WCR_A: .long CS6WCR
+CS5PCR_A: .long CS5PCR
+CS6PCR_A: .long CS6PCR
MMSELR_D: .long 0xA5A50003
BCR_D: .long 0x00000000
CS5PCR_D: .long 0x77000000
CS6PCR_D: .long 0x77000000
-REPEAT0_R3: .long 0x00002000
-REPEAT0_R1: .long 0x0000200
+REPEAT0_R3: .long 0x00002000
+REPEAT0_R1: .long 0x0000200
OBJS := rsk7203.o
SOBJS := lowlevel_init.o
+LIB := $(addprefix $(obj),$(LIB))
+OBJS := $(addprefix $(obj),$(OBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
.global lowlevel_init
lowlevel_init:
/* Cache setting */
- mov.l CCR1_A ,r1
- mov.l CCR1_D ,r0
- mov.l r0,@r1
+ write32 CCR1_A ,CCR1_D
/* ConfigurePortPins */
- mov.l PECRL3_A, r1
- mov.l PECRL3_D, r0
- mov.w r0,@r1
+ write16 PECRL3_A, PECRL3_D
- mov.l PCCRL4_A, r1
- mov.l PCCRL4_D0, r0
- mov.w r0,@r1
+ write16 PCCRL4_A, PCCRL4_D0
- mov.l PECRL4_A, r1
- mov.l PECRL4_D0, r0
- mov.w r0,@r1
+ write16 PECRL4_A, PECRL4_D0
- mov.l PEIORL_A, r1
- mov.l PEIORL_D0, r0
- mov.w r0,@r1
+ write16 PEIORL_A, PEIORL_D0
- mov.l PCIORL_A, r1
- mov.l PCIORL_D, r0
- mov.w r0,@r1
+ write16 PCIORL_A, PCIORL_D
- mov.l PFCRH2_A, r1
- mov.l PFCRH2_D, r0
- mov.w r0,@r1
+ write16 PFCRH2_A, PFCRH2_D
- mov.l PFCRH3_A, r1
- mov.l PFCRH3_D, r0
- mov.w r0,@r1
+ write16 PFCRH3_A, PFCRH3_D
- mov.l PFCRH1_A, r1
- mov.l PFCRH1_D, r0
- mov.w r0,@r1
+ write16 PFCRH1_A, PFCRH1_D
- mov.l PFIORH_A, r1
- mov.l PFIORH_D, r0
- mov.w r0,@r1
+ write16 PFIORH_A, PFIORH_D
- mov.l PECRL1_A, r1
- mov.l PECRL1_D0, r0
- mov.w r0,@r1
+ write16 PECRL1_A, PECRL1_D0
- mov.l PEIORL_A, r1
- mov.l PEIORL_D1, r0
- mov.w r0,@r1
+ write16 PEIORL_A, PEIORL_D1
/* Configure Operating Frequency */
- mov.l WTCSR_A ,r1
- mov.l WTCSR_D0 ,r0
- mov.w r0,@r1
+ write16 WTCSR_A, WTCSR_D0
- mov.l WTCSR_A ,r1
- mov.l WTCSR_D1 ,r0
- mov.w r0,@r1
+ write16 WTCSR_A, WTCSR_D1
- mov.l WTCNT_A ,r1
- mov.l WTCNT_D ,r0
- mov.w r0,@r1
+ write16 WTCNT_A, WTCNT_D
/* Set clock mode*/
- mov.l FRQCR_A,r1
- mov.l FRQCR_D,r0
- mov.w r0,@r1
+ write16 FRQCR_A, FRQCR_D
/* Configure Bus And Memory */
init_bsc_cs0:
- mov.l PCCRL4_A,r1
- mov.l PCCRL4_D1,r0
- mov.w r0,@r1
+ write16 PCCRL4_A, PCCRL4_D1
- mov.l PECRL1_A,r1
- mov.l PECRL1_D1,r0
- mov.w r0,@r1
+ write16 PECRL1_A, PECRL1_D1
- mov.l CMNCR_A,r1
- mov.l CMNCR_D,r0
- mov.l r0,@r1
+ write32 CMNCR_A, CMNCR_D
- mov.l SC0BCR_A,r1
- mov.l SC0BCR_D,r0
- mov.l r0,@r1
+ write32 SC0BCR_A, SC0BCR_D
- mov.l CS0WCR_A,r1
- mov.l CS0WCR_D,r0
- mov.l r0,@r1
+ write32 CS0WCR_A, CS0WCR_D
init_bsc_cs1:
- mov.l PECRL4_A,r1
- mov.l PECRL4_D1,r0
- mov.w r0,@r1
+ write16 PECRL4_A, PECRL4_D1
- mov.l CS1WCR_A,r1
- mov.l CS1WCR_D,r0
- mov.l r0,@r1
+ write32 CS1WCR_A, CS1WCR_D
init_sdram:
- mov.l PCCRL2_A,r1
- mov.l PCCRL2_D,r0
- mov.w r0,@r1
+ write16 PCCRL2_A, PCCRL2_D
- mov.l PCCRL4_A,r1
- mov.l PCCRL4_D2,r0
- mov.w r0,@r1
+ write16 PCCRL4_A, PCCRL4_D2
- mov.l PCCRL1_A,r1
- mov.l PCCRL1_D,r0
- mov.w r0,@r1
+ write16 PCCRL1_A, PCCRL1_D
- mov.l PCCRL3_A,r1
- mov.l PCCRL3_D,r0
- mov.w r0,@r1
+ write16 PCCRL3_A, PCCRL3_D
- mov.l CS3BCR_A,r1
- mov.l CS3BCR_D,r0
- mov.l r0,@r1
+ write32 CS3BCR_A, CS3BCR_D
- mov.l CS3WCR_A,r1
- mov.l CS3WCR_D,r0
- mov.l r0,@r1
+ write32 CS3WCR_A, CS3WCR_D
- mov.l SDCR_A,r1
- mov.l SDCR_D,r0
- mov.l r0,@r1
+ write32 SDCR_A, SDCR_D
- mov.l RTCOR_A,r1
- mov.l RTCOR_D,r0
- mov.l r0,@r1
+ write32 RTCOR_A, RTCOR_D
- mov.l RTCSR_A,r1
- mov.l RTCSR_D,r0
- mov.l r0,@r1
+ write32 RTCSR_A, RTCSR_D
/* wait 200us */
- mov.l REPEAT_D,r3
- mov #0,r2
+ mov.l REPEAT_D, r3
+ mov #0, r2
repeat0:
- add #1,r2
- cmp/hs r3,r2
- bf repeat0
+ add #1, r2
+ cmp/hs r3, r2
+ bf repeat0
nop
- mov.l SDRAM_MODE, r1
- mov #0,r0
- mov.l r0, @r1
+ mov.l SDRAM_MODE, r1
+ mov #0, r0
+ mov.l r0, @r1
nop
rts
WTCSR_A: .long 0xFFFE0000
-WTCSR_D0: .long 0x0000A518
-WTCSR_D1: .long 0x0000A51D
+WTCSR_D0: .long 0x0000A518
+WTCSR_D1: .long 0x0000A51D
WTCNT_A: .long 0xFFFE0002
WTCNT_D: .long 0x00005A84
FRQCR_A: .long 0xFFFE0010
STBCR4_D: .long 0x00000008
STBCR5_A: .long 0xFFFE0410
STBCR5_D: .long 0x00000000
-STBCR6_A: .long 0xFFFE0414
+STBCR6_A: .long 0xFFFE0414
STBCR6_D: .long 0x00000002
SDRAM_MODE: .long 0xFFFC5040
REPEAT_D: .long 0x00009C40
#include <version.h>
#include <asm/processor.h>
+#include <asm/macro.h>
.global lowlevel_init
lowlevel_init:
- mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */
- mov.l WDTCSR_D, r0
- mov.l r0, @r1
+ write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */
- mov.l WDTST_A, r1 /* Watchdog Stop Time Register */
- mov.l WDTST_D, r0
- mov.l r0, @r1
+ write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */
- mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */
- mov.l WDTBST_D, r0
- mov.l r0, @r1
+ write32 WDTBST_A, WDTBST_D /*
+ * 0xFFCC0008
+ * Watchdog Base Stop Time Register
+ */
- mov.l CCR_A, r1 /* Address of Cache Control Register */
- mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */
- mov.l r0, @r1
+ write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */
+ /* Instruction Cache Invalidate */
- mov.l MMUCR_A, r1 /* Address of MMU Control Register */
- mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */
- mov.l r0, @r1
+ write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */
+ /* TI == TLB Invalidate bit */
- mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */
- mov.l MSTPCR0_D, r0
- mov.l r0, @r1
+ write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
- mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */
- mov.l MSTPCR1_D, r0
- mov.l r0, @r1
+ write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */
- mov.l RAMCR_A,r1
- mov.l RAMCR_D,r0
- mov.l r0, @r1
+ write32 RAMCR_A, RAMCR_D
- mov.l MMSELR_A,r1
- mov.l MMSELR_D,r0
+ mov.l MMSELR_A, r1
+ mov.l MMSELR_D, r0
synco
mov.l r0, @r1
- mov.l @r1,r2 /* execute two reads after setting MMSELR*/
- mov.l @r1,r2
+ mov.l @r1, r2 /* execute two reads after setting MMSELR */
+ mov.l @r1, r2
synco
/* issue memory read */
- mov.l DDRSD_START_A,r1 /* memory address to read*/
- mov.l @r1,r0
+ mov.l DDRSD_START_A, r1 /* memory address to read*/
+ mov.l @r1, r0
synco
- mov.l MIM8_A,r1
- mov.l MIM8_D,r0
- mov.l r0,@r1
+ write32 MIM8_A, MIM8_D
- mov.l MIMC_A,r1
- mov.l MIMC_D1,r0
- mov.l r0,@r1
+ write32 MIMC_A, MIMC_D1
- mov.l STRC_A,r1
- mov.l STRC_D,r0
- mov.l r0,@r1
+ write32 STRC_A, STRC_D
- mov.l SDR4_A,r1
- mov.l SDR4_D,r0
- mov.l r0,@r1
+ write32 SDR4_A, SDR4_D
- mov.l MIMC_A,r1
- mov.l MIMC_D2,r0
- mov.l r0,@r1
+ write32 MIMC_A, MIMC_D2
nop
nop
nop
- mov.l SCR4_A,r1
- mov.l SCR4_D3,r0
- mov.l r0,@r1
+ write32 SCR4_A, SCR4_D3
- mov.l SCR4_A,r1
- mov.l SCR4_D2,r0
- mov.l r0,@r1
+ write32 SCR4_A, SCR4_D2
- mov.l SDMR02000_A,r1
- mov.l SDMR02000_D,r0
- mov.l r0,@r1
+ write32 SDMR02000_A, SDMR02000_D
- mov.l SDMR00B08_A,r1
- mov.l SDMR00B08_D,r0
- mov.l r0,@r1
+ write32 SDMR00B08_A, SDMR00B08_D
- mov.l SCR4_A,r1
- mov.l SCR4_D2,r0
- mov.l r0,@r1
+ write32 SCR4_A, SCR4_D2
- mov.l SCR4_A,r1
- mov.l SCR4_D4,r0
- mov.l r0,@r1
+ write32 SCR4_A, SCR4_D4
nop
nop
nop
nop
- mov.l SCR4_A,r1
- mov.l SCR4_D4,r0
- mov.l r0,@r1
+ write32 SCR4_A, SCR4_D4
nop
nop
nop
nop
- mov.l SDMR00308_A,r1
- mov.l SDMR00308_D,r0
- mov.l r0,@r1
+ write32 SDMR00308_A, SDMR00308_D
- mov.l MIMC_A,r1
- mov.l MIMC_D3,r0
- mov.l r0,@r1
+ write32 MIMC_A, MIMC_D3
- mov.l SCR4_A,r1
- mov.l SCR4_D1,r0
- mov.l DELAY60_D,r3
+ mov.l SCR4_A, r1
+ mov.l SCR4_D1, r0
+ mov.l DELAY60_D, r3
delay_loop_60:
- mov.l r0,@r1
+ mov.l r0, @r1
dt r3
bf delay_loop_60
nop
- mov.l CCR_A, r1 /* Address of Cache Control Register */
- mov.l CCR_CACHE_D_2, r0
- mov.l r0, @r1
+ write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */
bsc_init:
- mov.l BCR_A, r1
- mov.l BCR_D, r0
- mov.l r0, @r1
+ write32 BCR_A, BCR_D
- mov.l CS0BCR_A, r1
- mov.l CS0BCR_D, r0
- mov.l r0, @r1
+ write32 CS0BCR_A, CS0BCR_D
- mov.l CS1BCR_A,r1
- mov.l CS1BCR_D,r0
- mov.l r0,@r1
+ write32 CS1BCR_A, CS1BCR_D
- mov.l CS2BCR_A, r1
- mov.l CS2BCR_D, r0
- mov.l r0, @r1
+ write32 CS2BCR_A, CS2BCR_D
- mov.l CS4BCR_A, r1
- mov.l CS4BCR_D, r0
- mov.l r0, @r1
+ write32 CS4BCR_A, CS4BCR_D
- mov.l CS5BCR_A, r1
- mov.l CS5BCR_D, r0
- mov.l r0, @r1
+ write32 CS5BCR_A, CS5BCR_D
- mov.l CS6BCR_A, r1
- mov.l CS6BCR_D, r0
- mov.l r0, @r1
+ write32 CS6BCR_A, CS6BCR_D
- mov.l CS0WCR_A, r1
- mov.l CS0WCR_D, r0
- mov.l r0, @r1
+ write32 CS0WCR_A, CS0WCR_D
- mov.l CS1WCR_A, r1
- mov.l CS1WCR_D, r0
- mov.l r0, @r1
+ write32 CS1WCR_A, CS1WCR_D
- mov.l CS2WCR_A, r1
- mov.l CS2WCR_D, r0
- mov.l r0, @r1
+ write32 CS2WCR_A, CS2WCR_D
- mov.l CS4WCR_A, r1
- mov.l CS4WCR_D, r0
- mov.l r0, @r1
+ write32 CS4WCR_A, CS4WCR_D
- mov.l CS5WCR_A, r1
- mov.l CS5WCR_D, r0
- mov.l r0, @r1
+ write32 CS5WCR_A, CS5WCR_D
- mov.l CS6WCR_A, r1
- mov.l CS6WCR_D, r0
- mov.l r0, @r1
+ write32 CS6WCR_A, CS6WCR_D
- mov.l CS5PCR_A, r1
- mov.l CS5PCR_D, r0
- mov.l r0, @r1
+ write32 CS5PCR_A, CS5PCR_D
- mov.l CS6PCR_A, r1
- mov.l CS6PCR_D, r0
- mov.l r0, @r1
+ write32 CS6PCR_A, CS6PCR_D
- mov.l DELAY200_D,r3
+ mov.l DELAY200_D, r3
delay_loop_200:
dt r3
bf delay_loop_200
nop
- mov.l PSEL0_A,r1
- mov.l PSEL0_D,r0
- mov.w r0,@r1
+ write16 PSEL0_A, PSEL0_D
- mov.l PSEL1_A,r1
- mov.l PSEL1_D,r0
- mov.w r0,@r1
+ write16 PSEL1_A, PSEL1_D
- mov.l ICR0_A,r1
- mov.l ICR0_D,r0
- mov.l r0,@r1
+ write32 ICR0_A, ICR0_D
stc sr, r0 /* BL bit off(init=ON) */
- mov.l SR_MASK_D, r1
+ mov.l SR_MASK_D, r1
and r1, r0
ldc r0, sr
CS5BCR_D: .long 0x77777670
CS6BCR_D: .long 0x77777670
CS0WCR_D: .long 0x7777770F
-CS1WCR_D: .long 0x22000002
+CS1WCR_D: .long 0x22000002
CS2WCR_D: .long 0x7777770F
CS4WCR_D: .long 0x7777770F
CS5WCR_D: .long 0x7777770F
#include <config.h>
#include <version.h>
#include <asm/processor.h>
-
-.macro write32, addr, data
- mov.l \addr ,r1
- mov.l \data ,r0
- mov.l r0, @r1
-.endm
-
-.macro write16, addr, data
- mov.l \addr ,r1
- mov.l \data ,r0
- mov.w r0, @r1
-.endm
-
-.macro write8, addr, data
- mov.l \addr ,r1
- mov.l \data ,r0
- mov.b r0, @r1
-.endm
-
-.macro wait_timer, time
- mov.l \time ,r3
-1:
- nop
- tst r3, r3
- bf/s 1b
- dt r3
-.endm
+#include <asm/macro.h>
#include <asm/processor.h>
CS_USB_BCR_D: .long 0x11111200
CS_USB_WCR_D: .long 0x00020004
-/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
+/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */
CS_SD_BCR_D: .long 0x00000300
CS_SD_WCR_D: .long 0x00030108
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
- SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
- SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
uint lcrr = CONFIG_SYS_LBC_LCRR;
get_sys_info (&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
sys_info_t sys_info;
- ulong clkdiv = lbc->lcrr & 0x0f;
+ ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
get_sys_info (&sys_info);
--- /dev/null
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB = $(obj)lib$(VENDOR).a
+
+COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
+COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
+COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
+COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This driver support NAND devices which have address lines
+ * connected as ALE and CLE inputs.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
+ CONFIG_SYS_NAND_ACTL_ALE |
+ CONFIG_SYS_NAND_ACTL_NCE);
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
+ if (ctrl & NAND_NCE)
+ IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
+
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_addr_hwcontrol;
+ nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/*
+ * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
+ */
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 gpporcr = gur->gpporcr;
+
+ if (gpporcr & 0x10000)
+ return 66666666;
+ else
+ return 50000000;
+}
+
+/*
+ * Return DDR input clock - synchronous with SYSCLK or 66 MHz
+ */
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+
+ if (ddr_ratio == 0x7)
+ return get_board_sys_clk(dummy);
+
+ return 66666666;
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/mmu.h>
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+
+ dram_size *= 0x100000;
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /* Initialize and enable DDR ECC */
+ ddr_enable_ecc(dram_size);
+#endif
+
+ return dram_size;
+}
+
+#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
+void board_add_ram_info(int use_default)
+{
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#endif
+
+ puts(" (");
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ /* Print interleaving information */
+ if (ddr1->cs0_config & 0x20000000) {
+ switch ((ddr1->cs0_config >> 24) & 0xf) {
+ case 0:
+ puts("cache line");
+ break;
+ case 1:
+ puts("page");
+ break;
+ case 2:
+ puts("bank");
+ break;
+ case 3:
+ puts("super-bank");
+ break;
+ default:
+ puts("invalid");
+ break;
+ }
+ } else {
+ puts("no");
+ }
+
+ puts(" interleaving");
+#endif
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
+ puts(", ");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ puts("ECC enabled");
+#endif
+
+ puts(")");
+}
+#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_config_unlock(struct pci_controller *hose);
+extern void fsl_pci_init(struct pci_controller *hose);
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+#ifdef CONFIG_MPC8572
+/* Correlate host/agent POR bits to usable info. Table 4-14 */
+struct host_agent_cfg_t {
+ uchar pcie_root[3];
+ uchar rio_host;
+} host_agent_cfg[8] = {
+ {{0, 0, 0}, 0},
+ {{0, 1, 1}, 1},
+ {{1, 0, 1}, 0},
+ {{1, 1, 0}, 1},
+ {{0, 0, 1}, 0},
+ {{0, 1, 0}, 1},
+ {{1, 0, 0}, 0},
+ {{1, 1, 1}, 1}
+};
+
+/* Correlate port width POR bits to usable info. Table 4-15 */
+struct io_port_cfg_t {
+ uchar pcie_width[3];
+ uchar rio_width;
+} io_port_cfg[16] = {
+ {{0, 0, 0}, 0},
+ {{0, 0, 0}, 0},
+ {{4, 0, 0}, 0},
+ {{4, 4, 0}, 0},
+ {{0, 0, 0}, 0},
+ {{0, 0, 0}, 0},
+ {{0, 0, 0}, 4},
+ {{4, 2, 2}, 0},
+ {{0, 0, 0}, 0},
+ {{0, 0, 0}, 0},
+ {{0, 0, 0}, 0},
+ {{4, 0, 0}, 4},
+ {{4, 0, 0}, 4},
+ {{0, 0, 0}, 4},
+ {{0, 0, 0}, 4},
+ {{8, 0, 0}, 0},
+};
+#elif defined CONFIG_MPC8548
+/* Correlate host/agent POR bits to usable info. Table 4-12 */
+struct host_agent_cfg_t {
+ uchar pci_host[2];
+ uchar pcie_root[1];
+ uchar rio_host;
+} host_agent_cfg[8] = {
+ {{1, 1}, {0}, 0},
+ {{1, 1}, {1}, 0},
+ {{1, 1}, {0}, 1},
+ {{0, 0}, {0}, 0}, /* reserved */
+ {{0, 1}, {1}, 0},
+ {{1, 1}, {1}, 0},
+ {{0, 1}, {1}, 1},
+ {{1, 1}, {1}, 1}
+};
+
+/* Correlate port width POR bits to usable info. Table 4-13 */
+struct io_port_cfg_t {
+ uchar pcie_width[1];
+ uchar rio_width;
+} io_port_cfg[8] = {
+ {{0}, 0},
+ {{0}, 0},
+ {{0}, 0},
+ {{4}, 4},
+ {{4}, 4},
+ {{0}, 4},
+ {{0}, 4},
+ {{8}, 0},
+};
+#endif
+
+void pci_init_board(void)
+{
+ struct pci_controller *hose;
+ volatile ccsr_fsl_pci_t *pci;
+ int width;
+ int host;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ struct pci_region *r;
+
+#ifdef CONFIG_PCI1
+ uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD);
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1;
+ uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
+
+ width = 0; /* Silence compiler warning... */
+ io_sel &= 0xf; /* Silence compiler warning... */
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
+ hose = &pci1_hose;
+ host = host_agent_cfg[host_agent].pci_host[0];
+ r = hose->regions;
+
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
+ pci_32 ? 32 : 64,
+ pcix ? "PCIX" : "PCI",
+ pci_spd_norm ? ">=" : "<=",
+ pcix ? freq * 2 : freq,
+ host ? "host" : "agent",
+ pci_arb ? "arbiter" : "external-arbiter");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ /* Unlock inbound PCI configuration cycles */
+ if (!host)
+ fsl_pci_config_unlock(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCI1 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+ } else {
+ printf(" PCI1: disabled\n");
+ }
+#elif defined CONFIG_MPC8548
+ /* PCI1 not present on MPC8572 */
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+#ifdef CONFIG_PCIE1
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+ hose = &pcie1_hose;
+ host = host_agent_cfg[host_agent].pcie_root[0];
+ width = io_port_cfg[io_sel].pcie_width[0];
+ r = hose->regions;
+
+ if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ printf("\n PCIE1 connected as %s (x%d)",
+ host ? "Root Complex" : "End Point", width);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ /* Unlock inbound PCI configuration cycles */
+ if (!host)
+ fsl_pci_config_unlock(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCIE1 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif /* CONFIG_PCIE1 */
+
+#ifdef CONFIG_PCIE2
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
+ hose = &pcie2_hose;
+ host = host_agent_cfg[host_agent].pcie_root[1];
+ width = io_port_cfg[io_sel].pcie_width[1];
+ r = hose->regions;
+
+ if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
+ printf("\n PCIE2 connected as %s (x%d)",
+ host ? "Root Complex" : "End Point", width);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ /* Unlock inbound PCI configuration cycles */
+ if (!host)
+ fsl_pci_config_unlock(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCIE2 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif /* CONFIG_PCIE2 */
+
+#ifdef CONFIG_PCIE3
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
+ hose = &pcie3_hose;
+ host = host_agent_cfg[host_agent].pcie_root[2];
+ width = io_port_cfg[io_sel].pcie_width[2];
+ r = hose->regions;
+
+ if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
+ printf("\n PCIE3 connected as %s (x%d)",
+ host ? "Root Complex" : "End Point", width);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE3_MEM_BASE,
+ CONFIG_SYS_PCIE3_MEM_PHYS,
+ CONFIG_SYS_PCIE3_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE3_IO_BASE,
+ CONFIG_SYS_PCIE3_IO_PHYS,
+ CONFIG_SYS_PCIE3_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ /* Unlock inbound PCI configuration cycles */
+ if (!host)
+ fsl_pci_config_unlock(hose);
+
+ first_free_busno = hose->last_busno + 1;
+ printf(" PCIE3 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif /* CONFIG_PCIE3 */
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
+void ft_board_pci_setup(void *blob, bd_t *bd)
+{
+ /* TODO - make node name (eg pci0) dynamic */
+#ifdef CONFIG_PCI1
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#endif
+#ifdef CONFIG_PCIE1
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+#ifdef CONFIG_PCIE2
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE3
+ ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
+#endif
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2004, 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# xpedite5200 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
+PLATFORM_CPPFLAGS += -mrelocatable
--- /dev/null
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
+
+ /* We use soldered memory, but use an SPD EEPROM to describe it.
+ * The SPD has an unspecified dimm type, but the DDR2 initialization
+ * code requires a specific type to be specified. This sets the type
+ * as a standard unregistered SO-DIMM. */
+ if (spd->dimm_type == 0) {
+ spd->dimm_type = 0x4;
+ ((uchar *)spd)[63] += 0x4;
+ }
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+
+ if (ctrl_num) {
+ printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num);
+ return;
+ }
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++)
+ get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS);
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 7;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 9;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 3;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#if CONFIG_SYS_PCI1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1),
+#endif
+#if CONFIG_SYS_PCI2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#if CONFIG_PCI1
+ /* *I*G* - PCI MEM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#if CONFIG_PCI2
+ /* *I*G* - PCI MEM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+ /* *I*G* - PCI IO */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+int checkboard(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+ char *s;
+
+ printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
+ printf(" ");
+ s = getenv("board_rev");
+ if (s)
+ printf("Rev %s, ", s);
+ s = getenv("serial#");
+ if (s)
+ printf("Serial# %s, ", s);
+ s = getenv("board_cfg");
+ if (s)
+ printf("Cfg %s", s);
+ printf("\n");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
+
+ return 0;
+}
+
+static void flash_cs_fixup(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_FLASH_PASS_CS));
+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ lbc->br0 = CONFIG_SYS_BR1_PRELIM;
+ lbc->or0 = CONFIG_SYS_OR1_PRELIM;
+
+ lbc->br1 = CONFIG_SYS_BR0_PRELIM;
+ lbc->or1 = CONFIG_SYS_OR0_PRELIM;
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+}
+#endif
--- /dev/null
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright 2008 Extreme Engineering Solutions, Inc.
+# Copyright 2007-2008 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# xpedite5370 board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_RELFLAGS += -mrelocatable
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
+ sizeof(ddr2_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0)
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ if (ctrl_num == 1)
+ i2c_address = SPD_EEPROM_ADDRESS2;
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+/*
+ * There are four board-specific SDRAM timing parameters which must be
+ * calculated based on the particular PCB artwork. These are:
+ * 1.) CPO (Read Capture Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths and
+ * chip-specific internal delays.
+ * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
+ * - TIMING_CFG_2 register
+ * Source: Calculation based on board trace lengths.
+ * Unless clock and DQ lanes are very different
+ * lengths (>2"), this should be set to the nominal value
+ * of 1/2 clock delay.
+ * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
+ * - DDR_SDRAM_CLK_CNTL register
+ * Source: Signal Integrity Simulations
+ * 4.) 2T Timing on Addr/Ctl
+ * - TIMING_CFG_2 register
+ * Source: Signal Integrity Simulations
+ * Usually only needed with heavy load/very high speed (>DDR2-800)
+ *
+ * ====== XPedite5370 DDR2-600 read delay calculations ======
+ *
+ * See Freescale's App Note AN2583 as refrence. This document also
+ * contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ * For MPC8572E
+ * Minimum chip delay (Ch 0): 1.372ns
+ * Maximum chip delay (Ch 0): 2.914ns
+ * Minimum chip delay (Ch 1): 1.220ns
+ * Maximum chip delay (Ch 1): 2.595ns
+ *
+ * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
+ *
+ * Minimum delay calc (Ch 0):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
+ * = 3808ps
+ * = 3.808ns
+ *
+ * Maximum delay calc (Ch 0):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps
+ * = 6240ps
+ * = 6.240ns
+ *
+ * Minimum delay calc (Ch 1):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
+ * = 3288ps
+ * = 3.288ns
+ *
+ * Maximum delay calc (Ch 1):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps
+ * = 5536ps
+ * = 5.536ns
+ *
+ * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
+ * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
+ * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
+ *
+ *
+ * ====== XPedite5370 DDR2-800 read delay calculations ======
+ *
+ * See Freescale's App Note AN2583 as refrence. This document also
+ * contains the chip-specific delays for 8548E, 8572, etc.
+ *
+ * For MPC8572E
+ * Minimum chip delay (Ch 0): 1.372ns
+ * Maximum chip delay (Ch 0): 2.914ns
+ * Minimum chip delay (Ch 1): 1.220ns
+ * Maximum chip delay (Ch 1): 2.595ns
+ *
+ * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
+ *
+ * Minimum delay calc (Ch 0):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
+ * = 3341ps
+ * = 3.341ns
+ *
+ * Maximum delay calc (Ch 0):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
+ * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps
+ * = 5673ps
+ * = 5.673ns
+ *
+ * Minimum delay calc (Ch 1):
+ * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
+ * = 2822ps
+ * = 2.822ns
+ *
+ * Maximum delay calc (Ch 1):
+ * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
+ * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps
+ * = 4968ps
+ * = 4.968ns
+ *
+ * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
+ * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
+ * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
+ * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
+ *
+ * Write latency (WR_DATA_DELAY) is calculated by doing the following:
+ *
+ * The DDR SDRAM specification requires DQS be received no sooner than
+ * 75% of an SDRAM clock period—and no later than 125% of a clock
+ * period—from the capturing clock edge of the command/address at the
+ * SDRAM.
+ *
+ * Based on the above tracelengths, the following are calculated:
+ * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
+ * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
+ * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
+ * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
+ *
+ * Difference in arrival time CLK vs. DQS:
+ * Ch. 0 0.072ns
+ * Ch. 1 0.138ns
+ *
+ * Both of these values are much less than 25% of the clock
+ * period at DDR2-600 or DDR2-800, so no additional delay is needed over
+ * the 1/2 cycle which normally aligns the first DQS transition
+ * exactly WL (CAS latency minus one cycle) after the CAS strobe.
+ * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
+ * terminology corresponds to exactly one clock period delay after
+ * the CAS strobe. (due to the fact that the "delay" is referenced
+ * from the *falling* edge of the CLK, just after the rising edge
+ * which the CAS strobe is latched on.
+ */
+
+typedef struct board_memctl_options {
+ uint16_t datarate_mhz_low;
+ uint16_t datarate_mhz_high;
+ uint8_t clk_adjust;
+ uint8_t cpo_override;
+ uint8_t write_data_delay;
+} board_memctl_options_t;
+
+static struct board_memctl_options bopts_ctrl[][2] = {
+ {
+ /* Controller 0 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 9,
+ .write_data_delay = 2,
+ },
+ },
+ {
+ /* Controller 1 */
+ {
+ /* DDR2 600/667 */
+ .datarate_mhz_low = 500,
+ .datarate_mhz_high = 750,
+ .clk_adjust = 5,
+ .cpo_override = 7,
+ .write_data_delay = 2,
+ },
+ {
+ /* DDR2 800 */
+ .datarate_mhz_low = 750,
+ .datarate_mhz_high = 850,
+ .clk_adjust = 5,
+ .cpo_override = 8,
+ .write_data_delay = 2,
+ },
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ struct board_memctl_options *bopts = bopts_ctrl[ctrl_num];
+ sys_info_t sysinfo;
+ int i;
+ unsigned int datarate;
+
+ get_sys_info(&sysinfo);
+ datarate = sysinfo.freqDDRBus / 1000 / 1000;
+
+ for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
+ if ((bopts[i].datarate_mhz_low <= datarate) &&
+ (bopts[i].datarate_mhz_high >= datarate)) {
+ debug("controller %d:\n", ctrl_num);
+ debug(" clk_adjust = %d\n", bopts[i].clk_adjust);
+ debug(" cpo = %d\n", bopts[i].cpo_override);
+ debug(" write_data_delay = %d\n",
+ bopts[i].write_data_delay);
+ popts->clk_adjust = bopts[i].clk_adjust;
+ popts->cpo_override = bopts[i].cpo_override;
+ popts->write_data_delay = bopts[i].write_data_delay;
+ }
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ */
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
+#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
+#endif
+#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* W**G* - NOR flashes */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* *I*G* - NAND flash */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_PCIE1
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCIE2
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#ifdef CONFIG_PCIE3
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
+ /* *I*G* - PCIe */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pca953x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void ft_board_pci_setup(void *blob, bd_t *bd);
+
+int checkboard(void)
+{
+ char *s;
+
+ printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
+ printf(" ");
+ s = getenv("board_rev");
+ if (s)
+ printf("Rev %s, ", s);
+ s = getenv("serial#");
+ if (s)
+ printf("Serial# %s, ", s);
+ s = getenv("board_cfg");
+ if (s)
+ printf("Cfg %s", s);
+ printf("\n");
+
+ return 0;
+}
+
+static void flash_cs_fixup(void)
+{
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ int flash_sel;
+
+ /*
+ * Print boot dev and swap flash flash chip selects if booted from 2nd
+ * flash. Swapping chip selects presents user with a common memory
+ * map regardless of which flash was booted from.
+ */
+ flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
+ CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
+ printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
+
+ if (flash_sel) {
+ lbc->br0 = CONFIG_SYS_BR1_PRELIM;
+ lbc->or0 = CONFIG_SYS_OR1_PRELIM;
+
+ lbc->br1 = CONFIG_SYS_BR0_PRELIM;
+ lbc->or1 = CONFIG_SYS_OR0_PRELIM;
+ }
+}
+
+int board_early_init_r(void)
+{
+ /* Initialize PCA9557 devices */
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+ pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
+
+ /*
+ * Remap NOR flash region to caching-inhibited
+ * so that flash can be erased/programmed properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* Invalidate existing TLB entry for NOR flash */
+ disable_tlb(0);
+ set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1);
+
+ flash_cs_fixup();
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_PCI
+ ft_board_pci_setup(blob, bd);
+#endif
+ ft_cpu_setup(blob, bd);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
fdt_size_dt_strings(blob) + sizeof(struct fdt_reserve_entry);
/* Make it so the fdt ends on a page boundary */
- actualsize = ALIGN(actualsize, 0x1000);
+ actualsize = ALIGN(actualsize + ((uint)blob & 0xfff), 0x1000);
actualsize = actualsize - ((uint)blob & 0xfff);
/* Change the fdt header to reflect the correct size */
/* deregistering the keyboard */
int usb_kbd_deregister(void)
{
+#ifdef CONFIG_SYS_DEVICE_DEREGISTER
return device_deregister(DEVNAME);
+#else
+ return 1;
+#endif
}
/**************************************************************************
#########################################################################
-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
+ifeq ($(HOSTOS),darwin)
HOSTCC = cc
else
HOSTCC = gcc
#
# So far, this is used only by tools/gdb/Makefile.
-ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc)
+ifeq ($(HOSTOS),darwin)
BFD_ROOT_DIR = /usr/local/tools
else
ifeq ($(HOSTARCH),$(ARCH))
* turn is based on the boot.bin code from ATMEL
*
*/
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUP 0xFFFFFF50
-#define MC_PUER 0xFFFFFF54
-#define MC_ASR 0xFFFFFF04
-#define MC_AASR 0xFFFFFF08
-#define EBI_CFGR 0xFFFFFF64
-#define SMC_CSR0 0xFFFFFF70
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLBR 0xFFFFFC2C
-#define MCKR 0xFFFFFC30
-
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_PDR 0xFFFFF804
-#define EBI_CSA 0xFFFFFF60
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_TR 0xFFFFFF94
-
+#include <asm/arch/AT91RM9200.h>
_MTEXT_BASE:
#undef START_FROM_MEM
#else
ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
#endif
- str r0, [r1, #CKGR_MOR]
+ str r0, [r1, #AT91C_CKGR_MOR]
/* Add loop to compensate Main Oscillator startup time */
ldr r0, =0x00000010
LoopOsc:
.ltorg
SMRDATA:
- .word MC_PUIA
- .word MC_PUIA_VAL
- .word MC_PUP
- .word MC_PUP_VAL
- .word MC_PUER
- .word MC_PUER_VAL
- .word MC_ASR
- .word MC_ASR_VAL
- .word MC_AASR
- .word MC_AASR_VAL
- .word EBI_CFGR
- .word EBI_CFGR_VAL
- .word SMC_CSR0
- .word SMC_CSR0_VAL
- .word PLLAR
- .word PLLAR_VAL
- .word PLLBR
- .word PLLBR_VAL
- .word MCKR
- .word MCKR_VAL
+ .word AT91C_MC_PUIA
+ .word CONFIG_SYS_MC_PUIA_VAL
+ .word AT91C_MC_PUP
+ .word CONFIG_SYS_MC_PUP_VAL
+ .word AT91C_MC_PUER
+ .word CONFIG_SYS_MC_PUER_VAL
+ .word AT91C_MC_ASR
+ .word CONFIG_SYS_MC_ASR_VAL
+ .word AT91C_MC_AASR
+ .word CONFIG_SYS_MC_AASR_VAL
+ .word AT91C_EBI_CFGR
+ .word CONFIG_SYS_EBI_CFGR_VAL
+ .word AT91C_SMC_CSR0
+ .word CONFIG_SYS_SMC_CSR0_VAL
+ .word AT91C_PLLAR
+ .word CONFIG_SYS_PLLAR_VAL
+ .word AT91C_PLLBR
+ .word CONFIG_SYS_PLLBR_VAL
+ .word AT91C_MCKR
+ .word CONFIG_SYS_MCKR_VAL
/* SMRDATA is 80 bytes long */
/* here there's a delay of 100 */
SMRDATA1:
- .word PIOC_ASR
- .word PIOC_ASR_VAL
- .word PIOC_BSR
- .word PIOC_BSR_VAL
- .word PIOC_PDR
- .word PIOC_PDR_VAL
- .word EBI_CSA
- .word EBI_CSA_VAL
- .word SDRC_CR
- .word SDRC_CR_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL1
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL2
- .word SDRAM1
- .word SDRAM_VAL
- .word SDRC_TR
- .word SDRC_TR_VAL
- .word SDRAM
- .word SDRAM_VAL
- .word SDRC_MR
- .word SDRC_MR_VAL3
- .word SDRAM
- .word SDRAM_VAL
+ .word AT91C_PIOC_ASR
+ .word CONFIG_SYS_PIOC_ASR_VAL
+ .word AT91C_PIOC_BSR
+ .word CONFIG_SYS_PIOC_BSR_VAL
+ .word AT91C_PIOC_PDR
+ .word CONFIG_SYS_PIOC_PDR_VAL
+ .word AT91C_EBI_CSA
+ .word CONFIG_SYS_EBI_CSA_VAL
+ .word AT91C_SDRC_CR
+ .word CONFIG_SYS_SDRC_CR_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CONFIG_SYS_SDRAM1
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_TR
+ .word CONFIG_SYS_SDRC_TR_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91C_SDRC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
$(AR) $(ARFLAGS) $@ $(OBJS)
$(obj)bedbug_603e.c:
- ln -s $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
+ ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c
#########################################################################
int checkcpu (void)
{
sys_info_t sysinfo;
- uint lcrr; /* local bus clock ratio register */
- uint clkdiv; /* clock divider portion of lcrr */
uint pvr, svr;
uint fam;
uint ver;
break;
}
-#if defined(CONFIG_SYS_LBC_LCRR)
- lcrr = CONFIG_SYS_LBC_LCRR;
-#else
- {
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
-
- lcrr = lbc->lcrr;
- }
-#endif
- clkdiv = lcrr & 0x0f;
- if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
- defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
- /*
- * Yes, the entire PQ38 family use the same
- * bit-representation for twice the clock divider values.
- */
- clkdiv *= 2;
-#endif
- printf("LBC:%-4s MHz\n",
- strmhz(buf1, sysinfo.freqSystemBus / clkdiv));
- } else {
- printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
- }
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV)
+ printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+ else
+ printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+ sysinfo.freqLocalBus);
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#include <fdt_support.h>
#include <asm/processor.h>
+DECLARE_GLOBAL_DATA_PTR;
+
extern void ft_qe_setup(void *blob);
#ifdef CONFIG_MP
#include "mp.h"
-DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_cpu(void *blob, u64 memory_limit)
{
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
+
+ do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
+ "bus-frequency", gd->lbc_clk, 1);
+ do_fixup_by_compat_u32(blob, "fsl,elbc",
+ "bus-frequency", gd->lbc_clk, 1);
#ifdef CONFIG_QE
ft_qe_setup(blob);
#endif
mfspr r0,SPRN_PIR
stw r0,ENTRY_PIR(r10)
+ mtspr IVPR,r12
/*
* Coming here, we know the cpu has one TLB mapping in TLB1[0]
* which maps 0xfffff000-0xffffffff one-to-one. We set up a
#include <common.h>
#include <ppc_asm.tmpl>
#include <asm/processor.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint plat_ratio,e500_ratio,half_freqSystemBus;
+ uint lcrr_div;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
}
#endif
+
+#if defined(CONFIG_SYS_LBC_LCRR)
+ /* We will program LCRR to this value later */
+ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
+#else
+ {
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
+ }
+#endif
+ if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
+ !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+ /*
+ * Yes, the entire PQ38 family use the same
+ * bit-representation for twice the clock divider values.
+ */
+ lcrr_div *= 2;
+#endif
+ sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
+ } else {
+ /* In case anyone cares what the unknown value is */
+ sysInfo->freqLocalBus = lcrr_div;
+ }
}
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
+ gd->lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
mtspr DBCR0,r0
#endif
- /* create a temp mapping in AS=1 to the boot window */
+ /* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16M)@l
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
- /* Align the mapping to 16MB */
- lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xff000000, (MAS2_I|MAS2_G))@l
+ lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
- lis r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(0xff000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
+ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
mtspr MAS0,r6
mtspr MAS1,r7
#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
void set_tlb(u8 tlb, u32 epn, u64 rpn,
u8 perms, u8 wimge,
mtspr(MAS7, _mas7);
#endif
asm volatile("isync;msync;tlbwe;isync");
+
+#ifdef CONFIG_ADDR_MAP
+ if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
+ addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
+#endif
}
void disable_tlb(u8 esel)
mtspr(MAS7, _mas7);
#endif
asm volatile("isync;msync;tlbwe;isync");
+
+#ifdef CONFIG_ADDR_MAP
+ if (gd->flags & GD_FLG_RELOC)
+ addrmap_set_entry(0, 0, 0, esel);
+#endif
}
void invalidate_tlb(u8 tlb)
return ;
}
+#ifdef CONFIG_ADDR_MAP
+void init_addr_map(void)
+{
+ int i;
+
+ for (i = 0; i < num_tlb_entries; i++) {
+ if (tlb_table[i].tlb == 0)
+ continue;
+
+ addrmap_set_entry(tlb_table[i].epn,
+ tlb_table[i].rpn,
+ (1UL << ((tlb_table[i].tsize * 2) + 10)),
+ tlb_table[i].esel);
+ }
+
+ return ;
+}
+#endif
+
+#ifndef CONFIG_SYS_DDR_TLB_START
+#define CONFIG_SYS_DDR_TLB_START 8
+#endif
+
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
unsigned int tlb_size;
* Configure DDR TLB1 entries.
* Starting at TLB1 8, use no more than 8 TLB1 entries.
*/
- ram_tlb_index = 8;
+ ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
&& ram_tlb_index < 16) {
uint pvr, svr;
uint ver;
uint major, minor;
- uint lcrr; /* local bus clock ratio register */
- uint clkdiv; /* clock divider portion of lcrr */
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
-#if defined(CONFIG_SYS_LBC_LCRR)
- lcrr = CONFIG_SYS_LBC_LCRR;
-#else
- {
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-
- lcrr = lbc->lcrr;
- }
-#endif
- clkdiv = lcrr & 0x0f;
- if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
- printf("LBC:%4lu MHz\n",
- sysinfo.freqSystemBus / 1000000 / clkdiv);
+ if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
+ printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000);
} else {
- printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
+ printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
+ sysinfo.freqLocalBus);
}
puts(" L2: ");
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
+#if defined(CONFIG_MPC8641)
+ do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
+ "bus-frequency", gd->lbc_clk, 1);
+#endif
+ do_fixup_by_compat_u32(blob, "fsl,elbc",
+ "bus-frequency", gd->lbc_clk, 1);
+
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \
#include <common.h>
#include <mpc86xx.h>
#include <asm/processor.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
uint plat_ratio, e600_ratio;
+ uint lcrr_div;
plat_ratio = (gur->porpllsr) & 0x0000003e;
plat_ratio >>= 1;
sysInfo->freqProcessor = e600_ratio + sysInfo->freqSystemBus;
break;
}
+
+#if defined(CONFIG_SYS_LBC_LCRR)
+ /* We will program LCRR to this value later */
+ lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
+#else
+ {
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
+ }
+#endif
+ if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+ sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
+ } else {
+ /* In case anyone cares what the unknown value is */
+ sysInfo->freqLocalBus = lcrr_div;
+ }
}
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
+ gd->lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
LIB = $(obj)lib$(CPU).a
-START = start.o
-OBJS = cpu.o interrupts.o watchdog.o
+SOBJS = start.o
+COBJS = cpu.o interrupts.o watchdog.o
-all: .depend $(START) $(LIB)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(OBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-#########################################################################
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
http://atmel.com/dyn/products/tools.asp?family_id=605#1443
------------------------------------------------------------------------------
-AT91SAM9260EK
+AT91SAM9260EK & AT91SAM9XEEK
------------------------------------------------------------------------------
Memory map
start it:
# qemu-system-mips -M mips -pflash flash -monitor null -nographic
+2) Download kernel + initrd
+
+On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
+you can downland
+
+#config to build the kernel
+qemu_mips_defconfig
+#patch to fix mips interupt init on 2.6.24.y kernel
+qemu_mips_kernel.patch
+initrd.gz
+vmlinux
+vmlinux.bin
+System.map
+
+4) Generate uImage
+
+# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
+
+5) Copy uImage to Flash
+# dd if=uImage bs=1k conv=notrunc seek=224 of=flash
+
+6) Generate Ide Disk
+
+# dd of=ide bs=1k cout=100k if=/dev/zero
+
+# sfdisk -C 261 -d ide
+# partition table of ide
+unit: sectors
+
+ ide1 : start= 63, size= 32067, Id=83
+ ide2 : start= 32130, size= 32130, Id=83
+ ide3 : start= 64260, size= 4128705, Id=83
+ ide4 : start= 0, size= 0, Id= 0
+
+7) Copy to ide
+
+# dd if=uImage bs=512 conv=notrunc seek=63 of=ide
+
+8) Generate ext2 on part 2 on Copy uImage and initrd.gz
+
+# Attached as loop device ide offset = 32130 * 512
+# losetup -o 16450560 -f ide
+# Format as ext2 ( arg2 : nb blocks)
+# mke2fs /dev/loop0 16065
+# losetup -d /dev/loop0
+# Mount and copy uImage and initrd.gz to it
+# mount -o loop,offset=16450560 -t ext2 ide /mnt
+# mkdir /mnt/boot
+# cp {initrd.gz,uImage} /mnt/boot/
+# Umount it
+# umount /mnt
+
+9) Set Environment
+
+setenv rd_start 0x80800000
+setenv rd_size 2663940
+setenv kernel BFC38000
+setenv oad_addr 80500000
+setenv load_addr2 80F00000
+setenv kernel_flash BFC38000
+setenv load_addr_hello 80200000
+setenv bootargs 'root=/dev/ram0 init=/bin/sh'
+setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
+setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
+setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
+setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
+setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
+setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
+setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
+setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
+setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
+setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
+setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
+setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
+setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
+setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
+setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
+setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
+setenv bootcmd 'run boot_tftp_flash'
+
+10) Now you can boot from flash, ide, ide+ext2 and tfp
+
+# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+
II) How to debug U-Boot
In order to debug U-Boot you need to start qemu with gdb server support (-s)
and waiting the connection to start the CPU (-S)
-# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic
+# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
in an other console you start gdb
1) Debugging of U-Boot Before Relocation
Before relocation, the addresses in the ELF file can be used without any problems
-buy connecting to the gdb server localhost:1234
+by connecting to the gdb server localhost:1234
# mipsel-unknown-linux-gnu-gdb u-boot
GNU gdb 6.6
--- /dev/null
+#
+# Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)libgpio.a
+
+COBJS-$(CONFIG_PCA953X) += pca953x.o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+########################################################################
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Driver for NXP's 4 and 8 bit I2C gpio expanders (eg pca9537, pca9557, etc)
+ * TODO: support additional devices with more than 8-bits GPIO
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <pca953x.h>
+
+/* Default to an address that hopefully won't corrupt other i2c devices */
+#ifndef CONFIG_SYS_I2C_PCA953X_ADDR
+#define CONFIG_SYS_I2C_PCA953X_ADDR (~0)
+#endif
+
+enum {
+ PCA953X_CMD_INFO,
+ PCA953X_CMD_DEVICE,
+ PCA953X_CMD_OUTPUT,
+ PCA953X_CMD_INPUT,
+ PCA953X_CMD_INVERT,
+};
+
+/*
+ * Modify masked bits in register
+ */
+static int pca953x_reg_write(uint8_t chip, uint addr, uint mask, uint data)
+{
+ uint8_t val;
+
+ if (i2c_read(chip, addr, 1, &val, 1))
+ return -1;
+
+ val &= ~mask;
+ val |= data;
+
+ return i2c_write(chip, addr, 1, &val, 1);
+}
+
+/*
+ * Set output value of IO pins in 'mask' to corresponding value in 'data'
+ * 0 = low, 1 = high
+ */
+int pca953x_set_val(uint8_t chip, uint mask, uint data)
+{
+ return pca953x_reg_write(chip, PCA953X_OUT, mask, data);
+}
+
+/*
+ * Set read polarity of IO pins in 'mask' to corresponding value in 'data'
+ * 0 = read pin value, 1 = read inverted pin value
+ */
+int pca953x_set_pol(uint8_t chip, uint mask, uint data)
+{
+ return pca953x_reg_write(chip, PCA953X_POL, mask, data);
+}
+
+/*
+ * Set direction of IO pins in 'mask' to corresponding value in 'data'
+ * 0 = output, 1 = input
+ */
+int pca953x_set_dir(uint8_t chip, uint mask, uint data)
+{
+ return pca953x_reg_write(chip, PCA953X_CONF, mask, data);
+}
+
+/*
+ * Read current logic level of all IO pins
+ */
+int pca953x_get_val(uint8_t chip)
+{
+ uint8_t val;
+
+ if (i2c_read(chip, 0, 1, &val, 1))
+ return -1;
+
+ return (int)val;
+}
+
+#ifdef CONFIG_CMD_PCA953X
+#ifdef CONFIG_CMD_PCA953X_INFO
+/*
+ * Display pca953x information
+ */
+static int pca953x_info(uint8_t chip)
+{
+ int i;
+ uint8_t data;
+
+ printf("pca953x@ 0x%x:\n\n", chip);
+ printf("gpio pins: 76543210\n");
+ printf("-------------------\n");
+
+ if (i2c_read(chip, PCA953X_CONF, 1, &data, 1))
+ return -1;
+ printf("conf: ");
+ for (i = 7; i >= 0; i--)
+ printf("%c", data & (1 << i) ? 'i' : 'o');
+ printf("\n");
+
+ if (i2c_read(chip, PCA953X_POL, 1, &data, 1))
+ return -1;
+ printf("invert: ");
+ for (i = 7; i >= 0; i--)
+ printf("%c", data & (1 << i) ? '1' : '0');
+ printf("\n");
+
+ if (i2c_read(chip, PCA953X_IN, 1, &data, 1))
+ return -1;
+ printf("input: ");
+ for (i = 7; i >= 0; i--)
+ printf("%c", data & (1 << i) ? '1' : '0');
+ printf("\n");
+
+ if (i2c_read(chip, PCA953X_OUT, 1, &data, 1))
+ return -1;
+ printf("output: ");
+ for (i = 7; i >= 0; i--)
+ printf("%c", data & (1 << i) ? '1' : '0');
+ printf("\n");
+
+ return 0;
+}
+#endif /* CONFIG_CMD_PCA953X_INFO */
+
+cmd_tbl_t cmd_pca953x[] = {
+ U_BOOT_CMD_MKENT(device, 3, 0, (void *)PCA953X_CMD_DEVICE, "", ""),
+ U_BOOT_CMD_MKENT(output, 4, 0, (void *)PCA953X_CMD_OUTPUT, "", ""),
+ U_BOOT_CMD_MKENT(input, 3, 0, (void *)PCA953X_CMD_INPUT, "", ""),
+ U_BOOT_CMD_MKENT(invert, 4, 0, (void *)PCA953X_CMD_INVERT, "", ""),
+#ifdef CONFIG_CMD_PCA953X_INFO
+ U_BOOT_CMD_MKENT(info, 2, 0, (void *)PCA953X_CMD_INFO, "", ""),
+#endif
+};
+
+int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR;
+ int val;
+ ulong ul_arg2 = 0;
+ ulong ul_arg3 = 0;
+ cmd_tbl_t *c;
+
+ c = find_cmd_tbl(argv[1], cmd_pca953x, ARRAY_SIZE(cmd_pca953x));
+
+ /* All commands but "device" require 'maxargs' arguments */
+ if (!c || !((argc == (c->maxargs)) ||
+ (((int)c->cmd == PCA953X_CMD_DEVICE) &&
+ (argc == (c->maxargs - 1))))) {
+ printf("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ /* arg2 used as chip number or pin number */
+ if (argc > 2)
+ ul_arg2 = simple_strtoul(argv[2], NULL, 16);
+
+ /* arg3 used as pin or invert value */
+ if (argc > 3)
+ ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1;
+
+ switch ((int)c->cmd) {
+#ifdef CONFIG_CMD_PCA953X_INFO
+ case PCA953X_CMD_INFO:
+ return pca953x_info(chip);
+#endif
+ case PCA953X_CMD_DEVICE:
+ if (argc == 3)
+ chip = (uint8_t)ul_arg2;
+ printf("Current device address: 0x%x\n", chip);
+ return 0;
+ case PCA953X_CMD_INPUT:
+ pca953x_set_dir(chip, (1 << ul_arg2),
+ PCA953X_DIR_IN << ul_arg2);
+ val = (pca953x_get_val(chip) & (1 << ul_arg2)) != 0;
+
+ printf("chip 0x%02x, pin 0x%lx = %d\n", chip, ul_arg2, val);
+ return val;
+ case PCA953X_CMD_OUTPUT:
+ pca953x_set_dir(chip, (1 << ul_arg2),
+ (PCA953X_DIR_OUT << ul_arg2));
+ return pca953x_set_val(chip, (1 << ul_arg2),
+ (ul_arg3 << ul_arg2));
+ case PCA953X_CMD_INVERT:
+ return pca953x_set_pol(chip, (1 << ul_arg2),
+ (ul_arg3 << ul_arg2));
+ default:
+ /* We should never get here */
+ return 1;
+ }
+}
+
+U_BOOT_CMD(
+ pca953x, 5, 1, do_pca953x,
+ "pca953x - pca953x gpio access\n",
+ "device [dev]\n"
+ " - show or set current device address\n"
+#ifdef CONFIG_CMD_PCA953X_INFO
+ "pca953x info\n"
+ " - display info for current chip\n"
+#endif
+ "pca953x output pin 0|1\n"
+ " - set pin as output and drive low or high\n"
+ "pca953x invert pin 0|1\n"
+ " - disable/enable polarity inversion for reads\n"
+ "pca953x intput pin\n"
+ " - set pin as input and read value\n"
+);
+
+#endif /* CONFIG_CMD_PCA953X */
int board_nand_init(struct nand_chip *nand)
{
struct fsl_elbc_mtd *priv;
- uint32_t br, or;
+ uint32_t br = 0, or = 0;
if (!elbc_ctrl) {
fsl_elbc_ctrl_init();
* if we could pass more than one datum to the NAND driver...
*/
for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
+ phys_addr_t base_addr = virt_to_phys(nand->IO_ADDR_R);
+
br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
- (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
+ (br & or & BR_BA) == BR_PHYS_ADDR(base_addr))
break;
}
struct nand_chip *chip = mtd->priv;
if (!(chip->options & NAND_BBT_SCANNED)) {
- chip->scan_bbt(mtd);
chip->options |= NAND_BBT_SCANNED;
+ chip->scan_bbt(mtd);
}
if (!chip->bbt)
#include <pci.h>
#include <asm/immap_fsl_pci.h>
+/* Freescale-specific PCI config registers */
+#define FSL_PCI_PBFR 0x44
+#define FSL_PCIE_CAP_ID 0x4c
+#define FSL_PCIE_CFG_RDY 0x4b0
+
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
}
}
+/* Enable inbound PCI config cycles for agent/endpoint interface */
+void fsl_pci_config_unlock(struct pci_controller *hose)
+{
+ pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
+ u8 agent;
+ u8 pcie_cap;
+ u16 pbfr;
+
+ pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
+ if (!agent)
+ return;
+
+ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+ if (pcie_cap != 0x0) {
+ /* PCIe - set CFG_READY bit of Configuration Ready Register */
+ pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+ } else {
+ /* PCI - clear ACL bit of PBFR */
+ pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
+ pbfr &= ~0x20;
+ pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
+ }
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/processor.h>
#if defined(CONFIG_CONS_SCIF0)
# define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
#else
# define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
-# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
+# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
# define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
#endif
#elif defined(CONFIG_CPU_SH7763)
# if defined(CONFIG_CONS_SCIF2)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0x1F
# else
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7203)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
-# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
+# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
# define LSR_ORER 1
# define FIFOLEVEL_MASK 0x1F
#elif defined(CONFIG_CPU_SH7720)
/* SCBRR register value setting */
#if defined(CONFIG_CPU_SH7720)
-# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk * 2) + 16 * bps) / (32 * bps) - 1)
#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)
/* SH7723 SCIFA use bus clock. So clock *2 */
-# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) (((clk * 2 * 2) + 16 * bps) / (32 * bps) - 1)
#else /* Generic SuperH */
-# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
+# define SCBRR_VALUE(bps, clk) ((clk + 16 * bps) / (32 * bps) - 1)
#endif
-#define SCR_RE (1 << 4)
-#define SCR_TE (1 << 5)
+#define SCR_RE (1 << 4)
+#define SCR_TE (1 << 5)
#define FCR_RFRST (1 << 1) /* RFCL */
#define FCR_TFRST (1 << 2) /* TFCL */
-#define FSR_DR (1 << 0)
-#define FSR_RDF (1 << 1)
-#define FSR_FER (1 << 3)
-#define FSR_BRK (1 << 4)
-#define FSR_FER (1 << 3)
-#define FSR_TEND (1 << 6)
-#define FSR_ER (1 << 7)
+#define FSR_DR (1 << 0)
+#define FSR_RDF (1 << 1)
+#define FSR_FER (1 << 3)
+#define FSR_BRK (1 << 4)
+#define FSR_FER (1 << 3)
+#define FSR_TEND (1 << 6)
+#define FSR_ER (1 << 7)
/*----------------------------------------------------------------------*/
void serial_setbrg(void)
{
DECLARE_GLOBAL_DATA_PTR;
- *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
+
+ writeb(SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ), SCBRR);
}
int serial_init(void)
{
- *SCSCR = (SCR_RE | SCR_TE);
- *SCSMR = 0;
- *SCSMR = 0;
- *SCFCR = (FCR_RFRST | FCR_TFRST);
- *SCFCR;
- *SCFCR = 0;
+ writew((SCR_RE | SCR_TE), SCSCR);
+ writew(0, SCSMR);
+ writew(0, SCSMR);
+ writew((FCR_RFRST | FCR_TFRST), SCFCR);
+ readw(SCFCR);
+ writew(0, SCFCR);
serial_setbrg();
return 0;
static int serial_rx_fifo_level(void)
{
#if defined(SCRFDR)
- return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
+ return (readw(SCRFDR) >> 0) & FIFOLEVEL_MASK;
#else
- return (*SCFDR >> 0) & FIFOLEVEL_MASK;
+ return (readw(SCFDR) >> 0) & FIFOLEVEL_MASK;
#endif
}
unsigned int fsr_bits_to_clear;
while (1) {
- if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
+ if (readw(SCFSR) & FSR_TEND) { /* Tx fifo is empty */
fsr_bits_to_clear = FSR_TEND;
break;
}
}
- *SCFTDR = c;
+ writeb(c, SCFTDR);
if (fsr_bits_to_clear != 0)
- *SCFSR &= ~fsr_bits_to_clear;
+ writew(readw(SCFSR) & ~fsr_bits_to_clear, SCFSR);
}
void serial_putc(const char c)
return serial_rx_fifo_level() ? 1 : 0;
}
-#define FSR_ERR_CLEAR 0x0063
-#define RDRF_CLEAR 0x00fc
+#define FSR_ERR_CLEAR 0x0063
+#define RDRF_CLEAR 0x00fc
void handle_error(void)
{
-
- (void)*SCFSR;
- *SCFSR = FSR_ERR_CLEAR;
- (void)*SCLSR;
- *SCLSR = 0x00;
+ readw(SCFSR);
+ writew(FSR_ERR_CLEAR, SCFSR);
+ readw(SCLSR);
+ writew(0x00, SCLSR);
}
int serial_getc_check(void)
{
unsigned short status;
- status = *SCFSR;
+ status = readw(SCFSR);
if (status & (FSR_FER | FSR_ER | FSR_BRK))
handle_error();
- if (*SCLSR & LSR_ORER)
+ if (readw(SCLSR) & LSR_ORER)
handle_error();
return status & (FSR_DR | FSR_RDF);
}
while (!serial_getc_check())
;
- ch = *SCFRDR;
- status = *SCFSR;
+ ch = readb(SCFRDR);
+ status = readw(SCFSR);
- *SCFSR = RDRF_CLEAR;
+ writew(RDRF_CLEAR, SCFSR);
if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
handle_error();
- if (*SCLSR & LSR_ORER)
+ if (readw(SCLSR) & LSR_ORER)
handle_error();
return ch;
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
+#else
+/* flash */
+#define AT91C_MC_PUIA 0xFFFFFF10
+#define AT91C_MC_PUP 0xFFFFFF50
+#define AT91C_MC_PUER 0xFFFFFF54
+#define AT91C_MC_ASR 0xFFFFFF04
+#define AT91C_MC_AASR 0xFFFFFF08
+#define AT91C_EBI_CFGR 0xFFFFFF64
+#define AT91C_SMC_CSR0 0xFFFFFF70
+
+/* clocks */
+#define AT91C_PLLAR 0xFFFFFC28
+#define AT91C_PLLBR 0xFFFFFC2C
+#define AT91C_MCKR 0xFFFFFC30
+
+#define AT91C_BASE_CKGR 0xFFFFFC20
+#define AT91C_CKGR_MOR 0
+
+/* sdram */
+#define AT91C_PIOC_ASR 0xFFFFF870
+#define AT91C_PIOC_BSR 0xFFFFF874
+#define AT91C_PIOC_PDR 0xFFFFF804
+#define AT91C_EBI_CSA 0xFFFFFF60
+#define AT91C_SDRC_CR 0xFFFFFF98
+#define AT91C_SDRC_MR 0xFFFFFF90
+#define AT91C_SDRC_TR 0xFFFFFF94
+
#endif /* __ASSEMBLY__ */
#endif /* AT91RM9200_H */
#define LCRR_EADC_2 0x00020000
#define LCRR_EADC_3 0x00030000
#define LCRR_EADC_4 0x00000000
-#define LCRR_CLKDIV 0x0000000F
+/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+ * should always be zero on older parts that have a four bit CLKDIV.
+ */
+#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
u32 sdhc_clk;
#endif
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ u32 lbc_clk;
+#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 i2c1_clk;
u32 i2c2_clk;
#include <linux/config.h>
#include <asm/byteorder.h>
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+#ifdef CONFIG_ADDR_MAP
+ return (void *)(addrmap_phys_to_virt(paddr));
+#else
return (void *)((unsigned long)paddr);
+#endif
}
/*
static inline phys_addr_t virt_to_phys(void * vaddr)
{
+#ifdef CONFIG_ADDR_MAP
+ return addrmap_virt_to_phys(vaddr);
+#else
return (phys_addr_t)((unsigned long)vaddr);
+#endif
}
#endif
extern void disable_tlb(u8 esel);
extern void invalidate_tlb(u8 tlb);
extern void init_tlbs(void);
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
--- /dev/null
+/*
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACRO_H__
+#define __MACRO_H__
+#ifdef __ASSEMBLY__
+
+.macro write32, addr, data
+ mov.l \addr ,r1
+ mov.l \data ,r0
+ mov.l r0, @r1
+.endm
+
+.macro write16, addr, data
+ mov.l \addr ,r1
+ mov.l \data ,r0
+ mov.w r0, @r1
+.endm
+
+.macro write8, addr, data
+ mov.l \addr ,r1
+ mov.l \data ,r0
+ mov.b r0, @r1
+.endm
+
+.macro wait_timer, time
+ mov.l \time ,r3
+1:
+ nop
+ tst r3, r3
+ bf/s 1b
+ dt r3
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACRO_H__ */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
+#define CONFIG_PRAM 0 /* use pram variable to overwrite */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CONFIG_PRAM 0 /* use pram variable to overwrite */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
/* DDR Setup */
+#define CONFIG_SYS_DDR_TLB_START 9
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
/* For RTL8139 */
#define _IO_BASE 0x00000000
/* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
/* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE 0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5200 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548 1
+#define CONFIG_XPEDITE5200 1
+#define CONFIG_SYS_BOARD_NAME "XPedite5200"
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS 0x54
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ 66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
+ * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
+ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE 0xef800000
+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY 25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xfc000000
+#define CONFIG_SYS_FLASH_BASE2 0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
+ {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
+ BR_PS_8 | \
+ BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
+ OR_GPCM_BCTLD | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV4 | \
+ OR_GPCM_SCY_4 | \
+ OR_GPCM_TRLX | \
+ OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
+ BR_PS_8 | \
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
+#define CONFIG_SYS_INIT_RAM_END 0x4000
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
+#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
+#define CONFIG_SYS_PCA953X_MONARCH 0x40
+#define CONFIG_SYS_PCA953X_EREADY 0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0 0x01
+#define CONFIG_SYS_PCA953X_P14_IO1 0x02
+#define CONFIG_SYS_PCA953X_P14_IO2 0x04
+#define CONFIG_SYS_PCA953X_P14_IO3 0x08
+#define CONFIG_SYS_PCA953X_P14_IO4 0x10
+#define CONFIG_SYS_PCA953X_P14_IO5 0x20
+#define CONFIG_SYS_PCA953X_P14_IO6 0x40
+#define CONFIG_SYS_PCA953X_P14_IO7 0x80
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
+#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define TSEC2_FLAGS TSEC_GIGABIT
+#define TSEC2_PHY_ADDR 2
+#define TSEC2_PHYIDX 0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3 1
+#define CONFIG_TSEC3_NAME "eTSEC3"
+#define TSEC3_FLAGS TSEC_GIGABIT
+#define TSEC3_PHY_ADDR 3
+#define TSEC3_PHYIDX 0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4 1
+#define CONFIG_TSEC4_NAME "eTSEC4"
+#define TSEC4_FLAGS TSEC_GIGABIT
+#define TSEC4_PHY_ADDR 4
+#define TSEC4_PHYIDX 0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff Pri FDT (256KB)
+ * fef00000 - ffefffff Pri OS image (16MB)
+ * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff Sec FDT (256KB)
+ * faf00000 - fbefffff Sec OS image (16MB)
+ * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_UBOOT2 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS1 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS2 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT1 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT2 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/uImage-XPedite5200\0" \
+ "fdtfile=/home/user/xpedite5200.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
+ "prog_os1="CONFIG_PROG_OS1"\0" \
+ "prog_os2="CONFIG_PROG_OS2"\0" \
+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash1=run set_bootargs; " \
+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+ "bootcmd_flash2=run set_bootargs; " \
+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+ "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * xpedite5370 board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8572 1
+#define CONFIG_XPEDITE5370 1
+#define CONFIG_SYS_BOARD_NAME "XPedite5370"
+#define CONFIG_NUM_CPUS 2 /* 2 Cores */
+#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
+#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */
+
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
+#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
+#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
+ * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
+ * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
+ * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
+ * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
+ * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
+ * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE 0xef800000
+#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xf8000000
+#define CONFIG_SYS_FLASH_BASE2 0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
+ {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
+ OR_GPCM_CSNT | \
+ OR_GPCM_XACS | \
+ OR_GPCM_ACS_DIV2 | \
+ OR_GPCM_SCY_8 | \
+ OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | \
+ OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
+ BR_PS_16 | \
+ BR_V)
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
+ (2<<BR_DECC_SHIFT) | \
+ BR_PS_8 | \
+ BR_MS_FCM | \
+ BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
+ OR_FCM_PGS | \
+ OR_FCM_CSCT | \
+ OR_FCM_CST | \
+ OR_FCM_CHT | \
+ OR_FCM_SCY_1 | \
+ OR_FCM_TRLX | \
+ OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
+ (2<<BR_DECC_SHIFT) | \
+ BR_PS_8 | \
+ BR_MS_FCM | \
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
+#define CONFIG_SYS_INIT_RAM_END 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
+#define CONFIG_DTT_DS1621
+#define CONFIG_DTT_SENSORS { 0 }
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
+
+/* GPIO/EEPROM/SRAM */
+#define CONFIG_DS4510
+#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
+#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
+#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - VPX P1 */
+#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
+
+/* PCIE2 - PEX8518 */
+#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_ETHPRIME "eTSEC2"
+
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR 1
+#define TSEC1_PHYIDX 0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR 2
+#define TSEC2_PHYIDX 0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DS4510
+#define CONFIG_CMD_DS4510_INFO
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PREBOOT /* enable preboot variable */
+#define CONFIG_FIT 1
+#define CONFIG_FIT_VERBOSE 1
+#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff Pri FDT (256KB)
+ * fef00000 - ffefffff Pri OS image (16MB)
+ * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff Sec FDT (256KB)
+ * f6f00000 - f7efffff Sec OS image (16MB)
+ * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_UBOOT2 \
+ "$download_cmd $loadaddr $ubootfile; " \
+ "if test $? -eq 0; then " \
+ "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
+ "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
+ "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
+ "if test $? -ne 0; then " \
+ "echo PROGRAM FAILED; " \
+ "else; " \
+ "echo PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_BOOT_OS_NET \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "if test -n $fdtaddr; then " \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "bootm $osaddr - $fdtaddr; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi; " \
+ "else; " \
+ "bootm $osaddr; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS1 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_OS2 \
+ "$download_cmd $osaddr $osfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
+ "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo OS PROGRAM FAILED; " \
+ "else; " \
+ "echo OS PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo OS DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT1 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_PROG_FDT2 \
+ "$download_cmd $fdtaddr $fdtfile; " \
+ "if test $? -eq 0; then " \
+ "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
+ "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
+ "if test $? -ne 0; then " \
+ "echo FDT PROGRAM FAILED; " \
+ "else; " \
+ "echo FDT PROGRAM SUCCEEDED; " \
+ "fi; " \
+ "else; " \
+ "echo FDT DOWNLOAD FAILED; " \
+ "fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "autoload=yes\0" \
+ "download_cmd=tftp\0" \
+ "console_args=console=ttyS0,115200\0" \
+ "root_args=root=/dev/nfs rw\0" \
+ "misc_args=ip=on\0" \
+ "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+ "bootfile=/home/user/file\0" \
+ "osfile=/home/user/uImage-XPedite5370\0" \
+ "fdtfile=/home/user/xpedite5370.dtb\0" \
+ "ubootfile=/home/user/u-boot.bin\0" \
+ "fdtaddr=c00000\0" \
+ "osaddr=0x1000000\0" \
+ "loadaddr=0x1000000\0" \
+ "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
+ "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
+ "prog_os1="CONFIG_PROG_OS1"\0" \
+ "prog_os2="CONFIG_PROG_OS2"\0" \
+ "prog_fdt1="CONFIG_PROG_FDT1"\0" \
+ "prog_fdt2="CONFIG_PROG_FDT2"\0" \
+ "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
+ "bootcmd_flash1=run set_bootargs; " \
+ "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+ "bootcmd_flash2=run set_bootargs; " \
+ "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+ "bootcmd=run bootcmd_flash1\0"
+#endif /* __CONFIG_H */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL 0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL 0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
/* sdram */
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#else
#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL 0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL 0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */
-#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
/* sdram */
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#else
#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL 0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL 0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
-#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
-#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
-#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */
/* sdram */
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#else
#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#define CONFIG_INITRD_TAG 1
#define CONFIG_MENUPROMPT "."
+/*
+ * LowLevel Init
+ */
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL 0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL 0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL 0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
/*
* Size of malloc() pool
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
/* flash */
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR_VAL 0x00000000
-#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
+#define CONFIG_SYS_MC_PUP_VAL 0x00000000
+#define CONFIG_SYS_MC_PUER_VAL 0x00000000
+#define CONFIG_SYS_MC_ASR_VAL 0x00000000
+#define CONFIG_SYS_MC_AASR_VAL 0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
/* clocks */
-#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
-#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
-#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
+#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */
+#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */
/* sdram */
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000020 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#else
#define CONFIG_SKIP_RELOCATE_UBOOT
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
+#define TSEC1_PHY_ADDR 0x19
+#define TSEC2_PHY_ADDR 0x1a
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
+
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
/*
* Miscellaneous configurable options
*/
+#define CONFIG_CMDLINE_EDITING /* undef to save memory */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
-#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.0.55
* General PCI
* Addresses are mapped 1-1.
*/
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE 0xe3000000
-#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BASE
+#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000
+#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS
#define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI)
* 0xa000_0000 512M PCI-Express 2 Memory
* Changed it for operating from 0xd0000000
*/
-#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
/*
* 0xe300_0000 16M PCI-Express 2 I/0
* Note that this is at 0xe0000000
*/
-#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
/*
*/
int device_register (device_t * dev);
int devices_init (void);
+#ifdef CONFIG_SYS_DEVICE_DEREGISTER
int device_deregister(char *devname);
+#endif
struct list_head* device_get_list(void);
device_t* device_get_by_name(char* name);
device_t* device_clone(device_t *dev);
unsigned long freqProcessor;
unsigned long freqSystemBus;
unsigned long freqDDRBus;
+ unsigned long freqLocalBus;
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
typedef struct {
unsigned long freqProcessor;
unsigned long freqSystemBus;
+ unsigned long freqLocalBus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable
--- /dev/null
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PCA953X_H_
+#define __PCA953X_H_
+
+#define PCA953X_IN 0x00
+#define PCA953X_OUT 0x01
+#define PCA953X_POL 0x02
+#define PCA953X_CONF 0x03
+
+#define PCA953X_OUT_LOW 0
+#define PCA953X_OUT_HIGH 1
+#define PCA953X_POL_NORMAL 0
+#define PCA953X_POL_INVERT 1
+#define PCA953X_DIR_OUT 0
+#define PCA953X_DIR_IN 1
+
+int pca953x_set_val(u8 chip, uint mask, uint data);
+int pca953x_set_pol(u8 chip, uint mask, uint data);
+int pca953x_set_dir(u8 chip, uint mask, uint data);
+int pca953x_get_val(u8 chip);
+
+#endif /* __PCA953X_H_ */
mem_malloc_init();
malloc_bin_reloc();
-#ifdef CONFIG_SPI
-# if ! defined(CONFIG_ENV_IS_IN_EEPROM)
- spi_init_f();
-# endif
- spi_init_r();
-#endif
-
#ifdef CONFIG_CMD_NAND
puts("NAND: ");
nand_init(); /* go init the NAND */
#include <keyboard.h>
#endif
+#ifdef CONFIG_ADDR_MAP
+#include <asm/mmu.h>
+#endif
+
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
extern int update_flash_size (int flash_size);
#endif
*/
trap_init (dest_addr);
+#if defined(CONFIG_ADDR_MAP) && defined(CONFIG_E500)
+ init_addr_map();
+#endif
+
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r ();
#endif
{
/* Divide clock by TMU_CLK_DIVIDER */
u16 bit = 0;
- switch( TMU_CLK_DIVIDER ){
- case 4:
- bit = 0;
- break;
- case 16:
- bit = 1;
- break;
- case 64: bit = 2;
+
+ switch (TMU_CLK_DIVIDER) {
+ case 1024:
+ bit = 4;
break;
case 256:
bit = 3;
break;
- case 1024:
- bit = 4;
+ case 64:
+ bit = 2;
break;
+ case 16:
+ bit = 1;
+ break;
+ case 4:
default:
bit = 0;
break;
writew(readw(TCR0) | bit, TCR0);
/* Clock adjustment calc */
- clk_adj = (int)(1.0/((1.0/CONFIG_SYS_HZ)*1000000));
+ clk_adj = (int)(1.0 / ((1.0 / CONFIG_SYS_HZ) * 1000000));
if (clk_adj < 1)
clk_adj = 1;
unsigned long get_timer (unsigned long base)
{
- /* return msec */
- return ((get_usec()/clk_adj)/1000) - base;
+ /* return msec */
+ return ((get_usec() / clk_adj) / 1000) - base;
}
void set_timer (unsigned long t)
#include <asm/io.h>
#include <asm/processor.h>
-#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */
+#define CMT_CMCSR_INIT 0x0001 /* PCLK/32 */
#define CMT_CMCSR_CALIB 0x0000
#define CMT_MAX_COUNTER (0xFFFFFFFF)
#define CMT_TIMER_RESET (0xFFFF)
/* return msec */
ulong get_timer(ulong base)
{
- return (get_usec()/1000) - base;
+ return (get_usec() / 1000) - base;
}
void set_timer(ulong t)
int s, len, o, port = 6666;
char buf[512];
struct sockaddr_in addr;
- int addr_len = sizeof addr;
+ socklen_t addr_len = sizeof addr;
if (argc > 1)
port = atoi (argv[1]);
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