]> git.sur5r.net Git - u-boot/commitdiff
ARM: k2g: Update PLL Multiplier and divider values
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 3 Nov 2016 10:05:02 +0000 (15:35 +0530)
committerTom Rini <trini@konsulko.com>
Sun, 13 Nov 2016 20:54:37 +0000 (15:54 -0500)
Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18

[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
board/ti/ks2_evm/board_k2g.c

index 8f16845d8e05f868882b2f019e522763a85403a9..40edbaa33f86cde12f1c1196db6b95582a48b3e6 100644 (file)
@@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
 
 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
 
 struct pll_init_data *get_pll_init_data(int pll)
 {