]> git.sur5r.net Git - u-boot/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
authorWolfgang Denk <wd@denx.de>
Tue, 5 Apr 2011 10:24:20 +0000 (12:24 +0200)
committerWolfgang Denk <wd@denx.de>
Tue, 5 Apr 2011 10:24:20 +0000 (12:24 +0200)
Conflicts:
drivers/usb/host/ehci-pci.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
51 files changed:
MAINTAINERS
MAKEALL
arch/mips/cpu/Makefile [deleted file]
arch/mips/cpu/asc_serial.c [deleted file]
arch/mips/cpu/asc_serial.h [deleted file]
arch/mips/cpu/au1x00_eth.c [deleted file]
arch/mips/cpu/au1x00_serial.c [deleted file]
arch/mips/cpu/au1x00_usb_ohci.c [deleted file]
arch/mips/cpu/au1x00_usb_ohci.h [deleted file]
arch/mips/cpu/cache.S [deleted file]
arch/mips/cpu/config.mk [deleted file]
arch/mips/cpu/cpu.c [deleted file]
arch/mips/cpu/incaip_clock.c [deleted file]
arch/mips/cpu/incaip_wdt.S [deleted file]
arch/mips/cpu/interrupts.c [deleted file]
arch/mips/cpu/mips32/Makefile [new file with mode: 0644]
arch/mips/cpu/mips32/au1x00/Makefile [new file with mode: 0644]
arch/mips/cpu/mips32/au1x00/au1x00_eth.c [new file with mode: 0644]
arch/mips/cpu/mips32/au1x00/au1x00_serial.c [new file with mode: 0644]
arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c [new file with mode: 0644]
arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h [new file with mode: 0644]
arch/mips/cpu/mips32/au1x00/config.mk [new file with mode: 0644]
arch/mips/cpu/mips32/cache.S [new file with mode: 0644]
arch/mips/cpu/mips32/config.mk [new file with mode: 0644]
arch/mips/cpu/mips32/cpu.c [new file with mode: 0644]
arch/mips/cpu/mips32/incaip/Makefile [new file with mode: 0644]
arch/mips/cpu/mips32/incaip/asc_serial.c [new file with mode: 0644]
arch/mips/cpu/mips32/incaip/asc_serial.h [new file with mode: 0644]
arch/mips/cpu/mips32/incaip/config.mk [new file with mode: 0644]
arch/mips/cpu/mips32/incaip/incaip_clock.c [new file with mode: 0644]
arch/mips/cpu/mips32/incaip/incaip_wdt.S [new file with mode: 0644]
arch/mips/cpu/mips32/interrupts.c [new file with mode: 0644]
arch/mips/cpu/mips32/start.S [new file with mode: 0644]
arch/mips/cpu/start.S [deleted file]
arch/mips/include/asm/inca-ip.h
arch/mips/lib/board.c
board/purple/Makefile [deleted file]
board/purple/config.mk [deleted file]
board/purple/flash.c [deleted file]
board/purple/lowlevel_init.S [deleted file]
board/purple/purple.c [deleted file]
board/purple/sconsole.c [deleted file]
board/purple/sconsole.h [deleted file]
board/purple/u-boot.lds [deleted file]
boards.cfg
common/usb_storage.c
doc/README.Purple [deleted file]
drivers/usb/host/ehci-pci.c
drivers/usb/musb/blackfin_usb.c
fs/fat/fat.c
include/configs/purple.h [deleted file]

index 4756f14d19b505bfc39d9ddd0464f2a33840b3b5..1d7e1f4acd4ab1738b9c08e42bc1fb6e5afef42a 100644 (file)
@@ -919,7 +919,6 @@ Daniel Engstr
 Wolfgang Denk <wd@denx.de>
 
        incaip          MIPS32 4Kc
-       purple          MIPS64 5Kc
 
 Thomas Lange <thomas@corelatus.se>
        dbau1x00        MIPS32 Au1000
diff --git a/MAKEALL b/MAKEALL
index a732e6adc384089172b66478ad4eb7609ce2a660..e1b928fdb579484484cc933e91bd2e420bbfc840 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -507,9 +507,7 @@ LIST_mips4kc="              \
        vct_premium_onenand_small       \
 "
 
-LIST_mips5kc="         \
-       purple          \
-"
+LIST_mips5kc=""
 
 LIST_au1xx0="          \
        dbau1000        \
diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile
deleted file mode 100644 (file)
index 06df8d1..0000000
+++ /dev/null
@@ -1,53 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(CPU).o
-
-START  = start.o
-SOBJS-y        = cache.o
-COBJS-y        = cpu.o interrupts.o
-
-SOBJS-$(CONFIG_INCA_IP)        += incaip_wdt.o
-COBJS-$(CONFIG_INCA_IP)        += asc_serial.o incaip_clock.o
-COBJS-$(CONFIG_PURPLE) += asc_serial.o
-COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
-
-SRCS   := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-START  := $(addprefix $(obj),$(START))
-
-all:   $(obj).depend $(START) $(LIB)
-
-$(LIB):        $(OBJS)
-       $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/mips/cpu/asc_serial.c b/arch/mips/cpu/asc_serial.c
deleted file mode 100644 (file)
index be686c2..0000000
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * (INCA) ASC UART support
- */
-
-#include <config.h>
-
-#ifdef CONFIG_PURPLE
-#define        serial_init     asc_serial_init
-#define        serial_putc     asc_serial_putc
-#define        serial_puts     asc_serial_puts
-#define        serial_getc     asc_serial_getc
-#define        serial_tstc     asc_serial_tstc
-#define        serial_setbrg   asc_serial_setbrg
-#endif
-
-#include <common.h>
-#include <asm/inca-ip.h>
-#include "asc_serial.h"
-
-#ifdef CONFIG_PURPLE
-
-#undef ASC_FIFO_PRESENT
-#define TOUT_LOOP      100000
-
-/* Set base address for second FPI interrupt control register bank */
-#define SFPI_INTCON_BASEADDR   0xBF0F0000
-
-/* Register offset from base address */
-#define FBS_ISR                0x00000000      /* Interrupt status register */
-#define FBS_IMR                0x00000008      /* Interrupt mask register */
-#define FBS_IDIS       0x00000010      /* Interrupt disable register */
-
-/* Interrupt status register bits */
-#define FBS_ISR_AT     0x00000040      /* ASC transmit interrupt */
-#define FBS_ISR_AR     0x00000020      /* ASC receive interrupt */
-#define FBS_ISR_AE     0x00000010      /* ASC error interrupt */
-#define FBS_ISR_AB     0x00000008      /* ASC transmit buffer interrupt */
-#define FBS_ISR_AS      0x00000004     /* ASC start of autobaud detection interrupt */
-#define FBS_ISR_AF     0x00000002      /* ASC end of autobaud detection interrupt */
-
-#else
-
-#define ASC_FIFO_PRESENT
-
-#endif
-
-
-#define SET_BIT(reg, mask)                  reg |= (mask)
-#define CLEAR_BIT(reg, mask)                reg &= (~mask)
-#define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
-
-extern uint incaip_get_fpiclk(void);
-
-static int serial_setopt (void);
-
-/* pointer to ASC register base address */
-static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
-
-/******************************************************************************
-*
-* serial_init - initialize a INCAASC channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-#ifdef CONFIG_INCA_IP
-    /* we have to set PMU.EN13 bit to enable an ASC device*/
-    INCAASC_PMU_ENABLE(13);
-#endif
-
-    /* and we have to set CLC register*/
-    CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
-    SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
-    /* initialy we are in async mode */
-    pAsc->asc_con = ASCCON_M_8ASYNC;
-
-    /* select input port */
-    pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
-
-#ifdef ASC_FIFO_PRESENT
-    /* TXFIFO's filling level */
-    SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
-                   ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
-    /* enable TXFIFO */
-    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
-
-    /* RXFIFO's filling level */
-    SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
-                   ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
-    /* enable RXFIFO */
-    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
-#endif
-
-    /* enable error signals */
-    SET_BIT(pAsc->asc_con, ASCCON_FEN);
-    SET_BIT(pAsc->asc_con, ASCCON_OEN);
-
-#ifdef CONFIG_INCA_IP
-    /* acknowledge ASC interrupts */
-    ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
-
-    /* disable ASC interrupts */
-    ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
-#endif
-
-#ifdef ASC_FIFO_PRESENT
-    /* set FIFOs into the transparent mode */
-    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
-    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
-#endif
-
-    /* set baud rate */
-    serial_setbrg();
-
-    /* set the options */
-    serial_setopt();
-
-    return 0;
-}
-
-void serial_setbrg (void)
-{
-    ulong      uiReloadValue, fdv;
-    ulong      f_ASC;
-
-#ifdef CONFIG_INCA_IP
-    f_ASC = incaip_get_fpiclk();
-#else
-    f_ASC = ASC_CLOCK_RATE;
-#endif
-
-#ifndef INCAASC_USE_FDV
-    fdv = 2;
-    uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
-    fdv = INCAASC_FDV_HIGH_BAUDRATE;
-    uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
-    if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
-    {
-#ifndef INCAASC_USE_FDV
-       fdv = 3;
-       uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
-       fdv = INCAASC_FDV_LOW_BAUDRATE;
-       uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
-       if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
-       {
-           return;    /* can't impossibly generate that baud rate */
-       }
-    }
-
-    /* Disable Baud Rate Generator; BG should only be written when R=0 */
-    CLEAR_BIT(pAsc->asc_con, ASCCON_R);
-
-#ifndef INCAASC_USE_FDV
-    /*
-     * Disable Fractional Divider (FDE)
-     * Divide clock by reload-value + constant (BRS)
-     */
-    /* FDE = 0 */
-    CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
-
-    if ( fdv == 2 )
-       CLEAR_BIT(pAsc->asc_con, ASCCON_BRS);   /* BRS = 0 */
-    else
-       SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
-
-#else /* INCAASC_USE_FDV */
-
-    /* Enable Fractional Divider */
-    SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
-
-    /* Set fractional divider value */
-    pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
-
-#endif /* INCAASC_USE_FDV */
-
-    /* Set reload value in BG */
-    pAsc->asc_bg = uiReloadValue;
-
-    /* Enable Baud Rate Generator */
-    SET_BIT(pAsc->asc_con, ASCCON_R);           /* R = 1 */
-}
-
-/*******************************************************************************
-*
-* serial_setopt - set the serial options
-*
-* Set the channel operating mode to that specified. Following options
-* are supported: CREAD, CSIZE, PARENB, and PARODD.
-*
-* Note, this routine disables the transmitter.  The calling routine
-* may have to re-enable it.
-*
-* RETURNS:
-* Returns 0 to indicate success, otherwise -1 is returned
-*/
-
-static int serial_setopt (void)
-{
-    ulong  con;
-
-    switch ( ASC_OPTIONS & ASCOPT_CSIZE )
-    {
-    /* 7-bit-data */
-    case ASCOPT_CS7:
-       con = ASCCON_M_7ASYNCPAR;   /* 7-bit-data and parity bit */
-       break;
-
-    /* 8-bit-data */
-    case ASCOPT_CS8:
-       if ( ASC_OPTIONS & ASCOPT_PARENB )
-           con = ASCCON_M_8ASYNCPAR;   /* 8-bit-data and parity bit */
-       else
-           con = ASCCON_M_8ASYNC;      /* 8-bit-data no parity */
-       break;
-
-    /*
-     *  only 7 and 8-bit frames are supported
-     *  if we don't use IOCTL extensions
-     */
-    default:
-       return -1;
-    }
-
-    if ( ASC_OPTIONS & ASCOPT_STOPB )
-       SET_BIT(con, ASCCON_STP);       /* 2 stop bits */
-    else
-       CLEAR_BIT(con, ASCCON_STP);     /* 1 stop bit */
-
-    if ( ASC_OPTIONS & ASCOPT_PARENB )
-       SET_BIT(con, ASCCON_PEN);           /* enable parity checking */
-    else
-       CLEAR_BIT(con, ASCCON_PEN);         /* disable parity checking */
-
-    if ( ASC_OPTIONS & ASCOPT_PARODD )
-       SET_BIT(con, ASCCON_ODD);       /* odd parity */
-    else
-       CLEAR_BIT(con, ASCCON_ODD);     /* even parity */
-
-    if ( ASC_OPTIONS & ASCOPT_CREAD )
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
-
-    pAsc->asc_con |= con;
-
-    return 0;
-}
-
-void serial_putc (const char c)
-{
-#ifdef ASC_FIFO_PRESENT
-    uint txFl = 0;
-#else
-    uint timeout = 0;
-#endif
-
-    if (c == '\n') serial_putc ('\r');
-
-#ifdef ASC_FIFO_PRESENT
-    /* check do we have a free space in the TX FIFO */
-    /* get current filling level */
-    do
-    {
-       txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
-    }
-    while ( txFl == INCAASC_TXFIFO_FULL );
-#else
-
-    while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
-                          FBS_ISR_AB))
-    {
-           if (timeout++ > TOUT_LOOP)
-           {
-                   break;
-           }
-    }
-#endif
-
-    pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
-
-#ifndef ASC_FIFO_PRESENT
-    *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
-                                                                FBS_ISR_AT;
-#endif
-
-    /* check for errors */
-    if ( pAsc->asc_con & ASCCON_OE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-       return;
-    }
-}
-
-void serial_puts (const char *s)
-{
-    while (*s)
-    {
-       serial_putc (*s++);
-    }
-}
-
-int serial_getc (void)
-{
-    ulong symbol_mask;
-    char c;
-
-    while (!serial_tstc());
-
-    symbol_mask =
-       ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-
-    c = (char)(pAsc->asc_rbuf & symbol_mask);
-
-#ifndef ASC_FIFO_PRESENT
-    *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
-#endif
-
-    return c;
-}
-
-int serial_tstc (void)
-{
-    int res = 1;
-
-#ifdef ASC_FIFO_PRESENT
-    if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
-    {
-       res = 0;
-    }
-#else
-    if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
-                                                               FBS_ISR_AR))
-
-    {
-       res = 0;
-    }
-#endif
-    else if ( pAsc->asc_con & ASCCON_FE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
-       res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_PE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
-       res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_OE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-       res = 0;
-    }
-
-    return res;
-}
diff --git a/arch/mips/cpu/asc_serial.h b/arch/mips/cpu/asc_serial.h
deleted file mode 100644 (file)
index 7ffdcfa..0000000
+++ /dev/null
@@ -1,177 +0,0 @@
-/* incaAscSio.h - (INCA) ASC UART tty driver header */
-
-#ifndef __INCincaAscSioh
-#define __INCincaAscSioh
-
-#include <asm/inca-ip.h>
-
-/* channel operating modes */
-#define        ASCOPT_CSIZE    0x00000003
-#define        ASCOPT_CS7      0x00000001
-#define        ASCOPT_CS8      0x00000002
-#define        ASCOPT_PARENB   0x00000004
-#define        ASCOPT_STOPB    0x00000008
-#define        ASCOPT_PARODD   0x00000010
-#define        ASCOPT_CREAD    0x00000020
-
-#define ASC_OPTIONS            (ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY    0
-
-/* use fractional divider for baudrate settings */
-#define INCAASC_USE_FDV
-
-#ifdef INCAASC_USE_FDV
-   #define INCAASC_FDV_LOW_BAUDRATE        71
-   #define INCAASC_FDV_HIGH_BAUDRATE       453
-#endif /*INCAASC_USE_FDV*/
-
-
-#define INCAASC_TXFIFO_FL       1
-#define INCAASC_RXFIFO_FL       1
-#define INCAASC_TXFIFO_FULL     16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define INCAASC_IRQ_LINE_ALL        0x000F0000  /* all IRQs */
-
-#define INCAASC_IRQ_LINE_TIR            0x00010000      /* TIR - Tx */
-#define INCAASC_IRQ_LINE_RIR            0x00020000      /* RIR - Rx */
-#define INCAASC_IRQ_LINE_EIR            0x00040000      /* EIR - Err */
-#define INCAASC_IRQ_LINE_TBIR           0x00080000      /* TBIR - Tx Buf*/
-
-/* interrupt controller access macros */
-#define ASC_INTERRUPTS_ENABLE(X)  \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
-#define ASC_INTERRUPTS_DISABLE(X) \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
-#define ASC_INTERRUPTS_CLEAR(X)   \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR        0x00000001
-#define ASCCLC_DISS        0x00000002
-#define ASCCLC_RMCMASK     0x0000FF00
-#define ASCCLC_RMCOFFSET   8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK 0x0007
-    #define ASCCON_M_8SYNC          0x0
-    #define ASCCON_M_8ASYNC         0x1
-    #define ASCCON_M_8IRDAASYNC     0x2
-    #define ASCCON_M_7ASYNCPAR      0x3
-    #define ASCCON_M_9ASYNC         0x4
-    #define ASCCON_M_8WAKEUPASYNC   0x5
-    #define ASCCON_M_8ASYNCPAR      0x7
-#define ASCCON_STP      0x0008
-#define ASCCON_REN      0x0010
-#define ASCCON_PEN      0x0020
-#define ASCCON_FEN      0x0040
-#define ASCCON_OEN      0x0080
-#define ASCCON_PE       0x0100
-#define ASCCON_FE       0x0200
-#define ASCCON_OE       0x0400
-#define ASCCON_FDE      0x0800
-#define ASCCON_ODD      0x1000
-#define ASCCON_BRS      0x2000
-#define ASCCON_LB       0x4000
-#define ASCCON_R        0x8000
-
-/* WHBCON register's bits and bitfields */
-#define ASCWHBCON_CLRREN    0x0010
-#define ASCWHBCON_SETREN    0x0020
-#define ASCWHBCON_CLRPE     0x0100
-#define ASCWHBCON_CLRFE     0x0200
-#define ASCWHBCON_CLROE     0x0400
-#define ASCWHBCON_SETPE     0x0800
-#define ASCWHBCON_SETFE     0x1000
-#define ASCWHBCON_SETOE     0x2000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN       0x0001
-#define ASCABCON_AUREN      0x0002
-#define ASCABCON_ABSTEN     0x0004
-#define ASCABCON_ABDETEN    0x0008
-#define ASCABCON_FCDETEN    0x0010
-#define ASCABCON_EMMASK     0x0300
-    #define ASCABCON_EMOFF          8
-       #define ASCABCON_EM_DISAB       0x0
-       #define ASCABCON_EM_DURAB       0x1
-       #define ASCABCON_EM_ALWAYS      0x2
-#define ASCABCON_TXINV      0x0400
-#define ASCABCON_RXINV      0x0800
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK     0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_SETABEN     0x0001
-#define ASCWHBABCON_CLRABEN     0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET    0x0001
-#define ASCABSTAT_FCCDET    0x0002
-#define ASCABSTAT_SCSDET    0x0004
-#define ASCABSTAT_SCCDET    0x0008
-#define ASCABSTAT_DETWAIT   0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET  0x0001
-#define ASCWHBABSTAT_SETFCSDET  0x0002
-#define ASCWHBABSTAT_CLRFCCDET  0x0004
-#define ASCWHBABSTAT_SETFCCDET  0x0008
-#define ASCWHBABSTAT_CLRSCSDET  0x0010
-#define ASCWHBABSTAT_SETSCSDET  0x0020
-#define ASCWHBABSTAT_SETSCCDET  0x0040
-#define ASCWHBABSTAT_CLRSCCDET  0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFEN         0x0001
-#define ASCTXFCON_TXFFLU        0x0002
-#define ASCTXFCON_TXTMEN        0x0004
-#define ASCTXFCON_TXFITLMASK    0x3F00
-#define ASCTXFCON_TXFITLOFF     8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFEN         0x0001
-#define ASCRXFCON_RXFFLU        0x0002
-#define ASCRXFCON_RXTMEN        0x0004
-#define ASCRXFCON_RXFITLMASK    0x3F00
-#define ASCRXFCON_RXFITLOFF     8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK      0x003F
-#define ASCFSTAT_TXFFLMASK      0x3F00
-#define ASCFSTAT_TXFFLOFF       8
-
-#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
-
-typedef  struct         /* incaAsc_t */
-{
-    volatile unsigned long  asc_clc;                            /*0x0000*/
-    volatile unsigned long  asc_pisel;                          /*0x0004*/
-    volatile unsigned long  asc_rsvd1[2];   /* for mapping */   /*0x0008*/
-    volatile unsigned long  asc_con;                            /*0x0010*/
-    volatile unsigned long  asc_bg;                             /*0x0014*/
-    volatile unsigned long  asc_fdv;                            /*0x0018*/
-    volatile unsigned long  asc_pmw;        /* not used */      /*0x001C*/
-    volatile unsigned long  asc_tbuf;                           /*0x0020*/
-    volatile unsigned long  asc_rbuf;                           /*0x0024*/
-    volatile unsigned long  asc_rsvd2[2];   /* for mapping */   /*0x0028*/
-    volatile unsigned long  asc_abcon;                          /*0x0030*/
-    volatile unsigned long  asc_abstat;     /* not used */      /*0x0034*/
-    volatile unsigned long  asc_rsvd3[2];   /* for mapping */   /*0x0038*/
-    volatile unsigned long  asc_rxfcon;                         /*0x0040*/
-    volatile unsigned long  asc_txfcon;                         /*0x0044*/
-    volatile unsigned long  asc_fstat;                          /*0x0048*/
-    volatile unsigned long  asc_rsvd4;      /* for mapping */   /*0x004C*/
-    volatile unsigned long  asc_whbcon;                         /*0x0050*/
-    volatile unsigned long  asc_whbabcon;                       /*0x0054*/
-    volatile unsigned long  asc_whbabstat;  /* not used */      /*0x0058*/
-
-} incaAsc_t;
-
-#endif /* __INCincaAscSioh */
diff --git a/arch/mips/cpu/au1x00_eth.c b/arch/mips/cpu/au1x00_eth.c
deleted file mode 100644 (file)
index c510799..0000000
+++ /dev/null
@@ -1,311 +0,0 @@
-/* Only eth0 supported for now
- *
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <config.h>
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-#error "PHY not supported yet"
-/* We just assume that we are running 100FD for now */
-/* We all use switches, right? ;-) */
-#endif
-
-/* I assume ethernet behaves like au1000 */
-
-#ifdef CONFIG_SOC_AU1000
-/* Base address differ between cpu:s */
-#define ETH0_BASE AU1000_ETH0_BASE
-#define MAC0_ENABLE AU1000_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1100
-#define ETH0_BASE AU1100_ETH0_BASE
-#define MAC0_ENABLE AU1100_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1500
-#define ETH0_BASE AU1500_ETH0_BASE
-#define MAC0_ENABLE AU1500_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1550
-#define ETH0_BASE AU1550_ETH0_BASE
-#define MAC0_ENABLE AU1550_MAC0_ENABLE
-#else
-#error "No valid cpu set"
-#endif
-#endif
-#endif
-#endif
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/au1x00.h>
-
-#if defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH  1520
-#define PKT_MAXBUF_SIZE                1518
-
-static char txbuf[DBUF_LENGTH];
-
-static int next_tx;
-static int next_rx;
-
-/* 4 rx and 4 tx fifos */
-#define NO_OF_FIFOS 4
-
-typedef struct{
-       u32 status;
-       u32 addr;
-       u32 len; /* Only used for tx */
-       u32 not_used;
-} mac_fifo_t;
-
-mac_fifo_t mac_fifo[NO_OF_FIFOS];
-
-#define MAX_WAIT 1000
-
-#if defined(CONFIG_CMD_MII)
-int  au1x00_miiphy_read(const char *devname, unsigned char addr,
-               unsigned char reg, unsigned short * value)
-{
-       volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
-       volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
-       u32 mii_control;
-       unsigned int timedout = 20;
-
-       while (*mii_control_reg & MAC_MII_BUSY) {
-               udelay(1000);
-               if (--timedout == 0) {
-                       printf("au1x00_eth: miiphy_read busy timeout!!\n");
-                       return -1;
-               }
-       }
-
-       mii_control = MAC_SET_MII_SELECT_REG(reg) |
-               MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
-
-       *mii_control_reg = mii_control;
-
-       timedout = 20;
-       while (*mii_control_reg & MAC_MII_BUSY) {
-               udelay(1000);
-               if (--timedout == 0) {
-                       printf("au1x00_eth: miiphy_read busy timeout!!\n");
-                       return -1;
-               }
-       }
-       *value = *mii_data_reg;
-       return 0;
-}
-
-int  au1x00_miiphy_write(const char *devname, unsigned char addr,
-               unsigned char reg, unsigned short value)
-{
-       volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
-       volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
-       u32 mii_control;
-       unsigned int timedout = 20;
-
-       while (*mii_control_reg & MAC_MII_BUSY) {
-               udelay(1000);
-               if (--timedout == 0) {
-                       printf("au1x00_eth: miiphy_write busy timeout!!\n");
-                       return -1;
-               }
-       }
-
-       mii_control = MAC_SET_MII_SELECT_REG(reg) |
-               MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
-
-       *mii_data_reg = value;
-       *mii_control_reg = mii_control;
-       return 0;
-}
-#endif
-
-static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
-       volatile mac_fifo_t *fifo_tx =
-               (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
-       int i;
-       int res;
-
-       /* tx fifo should always be idle */
-       fifo_tx[next_tx].len = length;
-       fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
-       au_sync();
-
-       udelay(1);
-       i=0;
-       while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
-               if(i>MAX_WAIT){
-                       printf("TX timeout\n");
-                       break;
-               }
-               udelay(1);
-               i++;
-       }
-
-       /* Clear done bit */
-       fifo_tx[next_tx].addr = 0;
-       fifo_tx[next_tx].len = 0;
-       au_sync();
-
-       res = fifo_tx[next_tx].status;
-
-       next_tx++;
-       if(next_tx>=NO_OF_FIFOS){
-               next_tx=0;
-       }
-       return(res);
-}
-
-static int au1x00_recv(struct eth_device* dev){
-       volatile mac_fifo_t *fifo_rx =
-               (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
-
-       int length;
-       u32 status;
-
-       for(;;){
-               if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
-                       /* Nothing has been received */
-                       return(-1);
-               }
-
-               status = fifo_rx[next_rx].status;
-
-               length = status&0x3FFF;
-
-               if(status&RX_ERROR){
-                       printf("Rx error 0x%x\n", status);
-               }
-               else{
-                       /* Pass the packet up to the protocol layers. */
-                       NetReceive(NetRxPackets[next_rx], length - 4);
-               }
-
-               fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
-
-               next_rx++;
-               if(next_rx>=NO_OF_FIFOS){
-                       next_rx=0;
-               }
-       } /* for */
-
-       return(0); /* Does anyone use this? */
-}
-
-static int au1x00_init(struct eth_device* dev, bd_t * bd){
-
-       volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
-       volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
-       volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
-       volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
-       volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
-       volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
-       volatile mac_fifo_t *fifo_tx =
-               (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
-       volatile mac_fifo_t *fifo_rx =
-               (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
-       int i;
-
-       next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
-       next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
-
-       /* We have to enable clocks before releasing reset */
-       *macen = MAC_EN_CLOCK_ENABLE;
-       udelay(10);
-
-       /* Enable MAC0 */
-       /* We have to release reset before accessing registers */
-       *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
-               MAC_EN_RESET1|MAC_EN_RESET2;
-       udelay(10);
-
-       for(i=0;i<NO_OF_FIFOS;i++){
-               fifo_tx[i].len = 0;
-               fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
-               fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
-       }
-
-       /* Put mac addr in little endian */
-#define ea eth_get_dev()->enetaddr
-       *mac_addr_high  =       (ea[5] <<  8) | (ea[4]      ) ;
-       *mac_addr_low   =       (ea[3] << 24) | (ea[2] << 16) |
-               (ea[1] <<  8) | (ea[0]      ) ;
-#undef ea
-       *mac_mcast_low = 0;
-       *mac_mcast_high = 0;
-
-       /* Make sure the MAC buffer is in the correct endian mode */
-#ifdef __LITTLE_ENDIAN
-       *mac_ctrl = MAC_FULL_DUPLEX;
-       udelay(1);
-       *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#else
-       *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
-       udelay(1);
-       *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#endif
-
-       return(1);
-}
-
-static void au1x00_halt(struct eth_device* dev){
-       volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
-
-       /* Put MAC0 in reset */
-       *macen = 0;
-}
-
-int au1x00_enet_initialize(bd_t *bis){
-       struct eth_device* dev;
-
-       if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
-               puts ("malloc failed\n");
-               return -1;
-       }
-
-       memset(dev, 0, sizeof *dev);
-
-       sprintf(dev->name, "Au1X00 ethernet");
-       dev->iobase = 0;
-       dev->priv   = 0;
-       dev->init   = au1x00_init;
-       dev->halt   = au1x00_halt;
-       dev->send   = au1x00_send;
-       dev->recv   = au1x00_recv;
-
-       eth_register(dev);
-
-#if defined(CONFIG_CMD_MII)
-       miiphy_register(dev->name,
-               au1x00_miiphy_read, au1x00_miiphy_write);
-#endif
-
-       return 1;
-}
diff --git a/arch/mips/cpu/au1x00_serial.c b/arch/mips/cpu/au1x00_serial.c
deleted file mode 100644 (file)
index c25ba5a..0000000
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * AU1X00 UART support
- *
- * Hardcoded to UART 0 for now
- * Speed and options also hardcoded to 115200 8N1
- *
- *  Copyright (c) 2003 Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/au1x00.h>
-
-/******************************************************************************
-*
-* serial_init - initialize a channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-       volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
-       volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
-
-       /* Enable clocks first */
-       *uart_enable = UART_EN_CE;
-
-       /* Then release reset */
-       /* Must release reset before setting other regs */
-       *uart_enable = UART_EN_CE|UART_EN_E;
-
-       /* Activate fifos, reset tx and rx */
-       /* Set tx trigger level to 12 */
-       *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
-               UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
-
-       serial_setbrg();
-
-       return 0;
-}
-
-
-void serial_setbrg (void)
-{
-       volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
-       volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
-       volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
-       int sd;
-       int divisorx2;
-
-       /* sd is system clock divisor                   */
-       /* see section 10.4.5 in au1550 datasheet       */
-       sd = (*sys_powerctrl & 0x03) + 2;
-
-       /* calulate 2x baudrate and round */
-       divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
-
-       if (divisorx2 & 0x01)
-               divisorx2 = divisorx2 + 1;
-
-       *uart_clk = divisorx2 / 2;
-
-       /* Set parity, stop bits and word length to 8N1 */
-       *uart_lcr = UART_LCR_WLEN8;
-}
-
-void serial_putc (const char c)
-{
-       volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-       volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
-
-       if (c == '\n') serial_putc ('\r');
-
-       /* Wait for fifo to shift out some bytes */
-       while((*uart_lsr&UART_LSR_THRE)==0);
-
-       *uart_tx = (u32)c;
-}
-
-void serial_puts (const char *s)
-{
-       while (*s)
-       {
-               serial_putc (*s++);
-       }
-}
-
-int serial_getc (void)
-{
-       volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
-       char c;
-
-       while (!serial_tstc());
-
-       c = (*uart_rx&0xFF);
-       return c;
-}
-
-int serial_tstc (void)
-{
-       volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-
-       if(*uart_lsr&UART_LSR_DR){
-               /* Data in rfifo */
-               return(1);
-       }
-       return 0;
-}
diff --git a/arch/mips/cpu/au1x00_usb_ohci.c b/arch/mips/cpu/au1x00_usb_ohci.c
deleted file mode 100644 (file)
index 0bc2305..0000000
+++ /dev/null
@@ -1,1726 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Note: Part of this code has been derived from linux
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <config.h>
-
-#ifdef CONFIG_USB_OHCI
-
-/* #include <pci.h> no PCI on the AU1x00 */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/au1x00.h>
-#include <usb.h>
-#include "au1x00_usb_ohci.h"
-
-#define OHCI_USE_NPS           /* force NoPowerSwitching mode */
-#define OHCI_VERBOSE_DEBUG     /* not always helpful */
-#define OHCI_FILL_TRACE
-
-#define USBH_ENABLE_BE (1<<0)
-#define USBH_ENABLE_C  (1<<1)
-#define USBH_ENABLE_E  (1<<2)
-#define USBH_ENABLE_CE (1<<3)
-#define USBH_ENABLE_RD (1<<4)
-
-#ifdef __LITTLE_ENDIAN
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
-#else
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
-#endif
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT \
-       (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#undef readl
-#undef writel
-
-#define readl(a)     au_readl((long)(a))
-#define writel(v,a)  au_writel((v),(int)(a))
-
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
-
-#define DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#define SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global ohci_t */
-static ohci_t gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-urb_priv_t urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-       u32 temp = readl (&hc->regs->roothub.register); \
-       if (hc->flags & OHCI_QUIRK_AMD756) \
-               while (temp & mask) \
-                       temp = readl (&hc->regs->roothub.register); \
-       temp; })
-
-static u32 roothub_a (struct ohci *hc)
-       { return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
-       { return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
-       { return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
-       { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
-
-/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
-       int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv (urb_priv_t * urb)
-{
-       int             i;
-       int             last;
-       struct td       * td;
-
-       last = urb->length - 1;
-       if (last >= 0) {
-               for (i = 0; i <= last; i++) {
-                       td = urb->td[i];
-                       if (td) {
-                               td->usb_dev = NULL;
-                               urb->td[i] = NULL;
-                       }
-               }
-       }
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
-       int transfer_len, struct devrequest * setup, char * str, int small)
-{
-       urb_priv_t * purb = &urb_priv;
-
-       dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
-                       str,
-                       sohci_get_current_frame_number (dev),
-                       usb_pipedevice (pipe),
-                       usb_pipeendpoint (pipe),
-                       usb_pipeout (pipe)? 'O': 'I',
-                       usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
-                               (usb_pipecontrol (pipe)? "CTRL": "BULK"),
-                       purb->actual_length,
-                       transfer_len, dev->status);
-#ifdef OHCI_VERBOSE_DEBUG
-       if (!small) {
-               int i, len;
-
-               if (usb_pipecontrol (pipe)) {
-                       printf (__FILE__ ": cmd(8):");
-                       for (i = 0; i < 8 ; i++)
-                               printf (" %02x", ((__u8 *) setup) [i]);
-                       printf ("\n");
-               }
-               if (transfer_len > 0 && buffer) {
-                       printf (__FILE__ ": data(%d/%d):",
-                               purb->actual_length,
-                               transfer_len);
-                       len = usb_pipeout (pipe)?
-                                       transfer_len: purb->actual_length;
-                       for (i = 0; i < 16 && i < len; i++)
-                               printf (" %02x", ((__u8 *) buffer) [i]);
-                       printf ("%s\n", i < len? "...": "");
-               }
-       }
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
-       int i, j;
-        __u32 * ed_p;
-       for (i= 0; i < 32; i++) {
-               j = 5;
-               ed_p = &(ohci->hcca->int_table [i]);
-               if (*ed_p == 0)
-                   continue;
-               printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
-               while (*ed_p != 0 && j--) {
-                       ed_t *ed = (ed_t *)m32_swap(ed_p);
-                       printf (" ed: %4x;", ed->hwINFO);
-                       ed_p = &ed->hwNextED;
-               }
-               printf ("\n");
-       }
-}
-
-static void ohci_dump_intr_mask (char *label, __u32 mask)
-{
-       dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
-               label,
-               mask,
-               (mask & OHCI_INTR_MIE) ? " MIE" : "",
-               (mask & OHCI_INTR_OC) ? " OC" : "",
-               (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
-               (mask & OHCI_INTR_FNO) ? " FNO" : "",
-               (mask & OHCI_INTR_UE) ? " UE" : "",
-               (mask & OHCI_INTR_RD) ? " RD" : "",
-               (mask & OHCI_INTR_SF) ? " SF" : "",
-               (mask & OHCI_INTR_WDH) ? " WDH" : "",
-               (mask & OHCI_INTR_SO) ? " SO" : ""
-               );
-}
-
-static void maybe_print_eds (char *label, __u32 value)
-{
-       ed_t *edp = (ed_t *)value;
-
-       if (value) {
-               dbg ("%s %08x", label, value);
-               dbg ("%08x", edp->hwINFO);
-               dbg ("%08x", edp->hwTailP);
-               dbg ("%08x", edp->hwHeadP);
-               dbg ("%08x", edp->hwNextED);
-       }
-}
-
-static char * hcfs2string (int state)
-{
-       switch (state) {
-               case OHCI_USB_RESET:    return "reset";
-               case OHCI_USB_RESUME:   return "resume";
-               case OHCI_USB_OPER:     return "operational";
-               case OHCI_USB_SUSPEND:  return "suspend";
-       }
-       return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
-{
-       struct ohci_regs        *regs = controller->regs;
-       __u32                   temp;
-
-       temp = readl (&regs->revision) & 0xff;
-       if (temp != 0x10)
-               dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
-       temp = readl (&regs->control);
-       dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
-               (temp & OHCI_CTRL_RWE) ? " RWE" : "",
-               (temp & OHCI_CTRL_RWC) ? " RWC" : "",
-               (temp & OHCI_CTRL_IR) ? " IR" : "",
-               hcfs2string (temp & OHCI_CTRL_HCFS),
-               (temp & OHCI_CTRL_BLE) ? " BLE" : "",
-               (temp & OHCI_CTRL_CLE) ? " CLE" : "",
-               (temp & OHCI_CTRL_IE) ? " IE" : "",
-               (temp & OHCI_CTRL_PLE) ? " PLE" : "",
-               temp & OHCI_CTRL_CBSR
-               );
-
-       temp = readl (&regs->cmdstatus);
-       dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
-               (temp & OHCI_SOC) >> 16,
-               (temp & OHCI_OCR) ? " OCR" : "",
-               (temp & OHCI_BLF) ? " BLF" : "",
-               (temp & OHCI_CLF) ? " CLF" : "",
-               (temp & OHCI_HCR) ? " HCR" : ""
-               );
-
-       ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
-       ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
-
-       maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
-
-       maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
-       maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
-
-       maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
-       maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
-
-       maybe_print_eds ("donehead", readl (&regs->donehead));
-}
-
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
-{
-       __u32                   temp, ndp, i;
-
-       temp = roothub_a (controller);
-       ndp = (temp & RH_A_NDP);
-
-       if (verbose) {
-               dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
-                       ((temp & RH_A_POTPGT) >> 24) & 0xff,
-                       (temp & RH_A_NOCP) ? " NOCP" : "",
-                       (temp & RH_A_OCPM) ? " OCPM" : "",
-                       (temp & RH_A_DT) ? " DT" : "",
-                       (temp & RH_A_NPS) ? " NPS" : "",
-                       (temp & RH_A_PSM) ? " PSM" : "",
-                       ndp
-                       );
-               temp = roothub_b (controller);
-               dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
-                       temp,
-                       (temp & RH_B_PPCM) >> 16,
-                       (temp & RH_B_DR)
-                       );
-               temp = roothub_status (controller);
-               dbg ("roothub.status: %08x%s%s%s%s%s%s",
-                       temp,
-                       (temp & RH_HS_CRWE) ? " CRWE" : "",
-                       (temp & RH_HS_OCIC) ? " OCIC" : "",
-                       (temp & RH_HS_LPSC) ? " LPSC" : "",
-                       (temp & RH_HS_DRWE) ? " DRWE" : "",
-                       (temp & RH_HS_OCI) ? " OCI" : "",
-                       (temp & RH_HS_LPS) ? " LPS" : ""
-                       );
-       }
-
-       for (i = 0; i < ndp; i++) {
-               temp = roothub_portstatus (controller, i);
-               dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
-                       i,
-                       temp,
-                       (temp & RH_PS_PRSC) ? " PRSC" : "",
-                       (temp & RH_PS_OCIC) ? " OCIC" : "",
-                       (temp & RH_PS_PSSC) ? " PSSC" : "",
-                       (temp & RH_PS_PESC) ? " PESC" : "",
-                       (temp & RH_PS_CSC) ? " CSC" : "",
-
-                       (temp & RH_PS_LSDA) ? " LSDA" : "",
-                       (temp & RH_PS_PPS) ? " PPS" : "",
-                       (temp & RH_PS_PRS) ? " PRS" : "",
-                       (temp & RH_PS_POCI) ? " POCI" : "",
-                       (temp & RH_PS_PSS) ? " PSS" : "",
-
-                       (temp & RH_PS_PES) ? " PES" : "",
-                       (temp & RH_PS_CCS) ? " CCS" : ""
-                       );
-       }
-}
-
-static void ohci_dump (ohci_t *controller, int verbose)
-{
-       dbg ("OHCI controller usb-%s state", controller->slot_name);
-
-       /* dumps some of the state we know about */
-       ohci_dump_status (controller);
-       if (verbose)
-               ep_print_int_eds (controller, "hcca");
-       dbg ("hcca frame #%04x", controller->hcca->frame_no);
-       ohci_dump_roothub (controller, 1);
-}
-
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
-               int transfer_len, struct devrequest *setup, int interval)
-{
-       ohci_t *ohci;
-       ed_t * ed;
-       urb_priv_t *purb_priv;
-       int i, size = 0;
-
-       ohci = &gohci;
-
-       /* when controller's hung, permit only roothub cleanup attempts
-        * such as powering down ports */
-       if (ohci->disabled) {
-               err("sohci_submit_job: EPIPE");
-               return -1;
-       }
-
-       /* every endpoint has a ed, locate and fill it */
-       if (!(ed = ep_add_ed (dev, pipe))) {
-               err("sohci_submit_job: ENOMEM");
-               return -1;
-       }
-
-       /* for the private part of the URB we need the number of TDs (size) */
-       switch (usb_pipetype (pipe)) {
-               case PIPE_BULK: /* one TD for every 4096 Byte */
-                       size = (transfer_len - 1) / 4096 + 1;
-                       break;
-               case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
-                       size = (transfer_len == 0)? 2:
-                                               (transfer_len - 1) / 4096 + 3;
-                       break;
-       }
-
-       if (size >= (N_URB_TD - 1)) {
-               err("need %d TDs, only have %d", size, N_URB_TD);
-               return -1;
-       }
-       purb_priv = &urb_priv;
-       purb_priv->pipe = pipe;
-
-       /* fill the private part of the URB */
-       purb_priv->length = size;
-       purb_priv->ed = ed;
-       purb_priv->actual_length = 0;
-
-       /* allocate the TDs */
-       /* note that td[0] was allocated in ep_add_ed */
-       for (i = 0; i < size; i++) {
-               purb_priv->td[i] = td_alloc (dev);
-               if (!purb_priv->td[i]) {
-                       purb_priv->length = i;
-                       urb_free_priv (purb_priv);
-                       err("sohci_submit_job: ENOMEM");
-                       return -1;
-               }
-       }
-
-       if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
-               urb_free_priv (purb_priv);
-               err("sohci_submit_job: EINVAL");
-               return -1;
-       }
-
-       /* link the ed into a chain if is not already */
-       if (ed->state != ED_OPER)
-               ep_link (ohci, ed);
-
-       /* fill the TDs and link it to the ed */
-       td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
-
-       return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
-{
-       ohci_t *ohci = &gohci;
-
-       return m16_swap (ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link (ohci_t *ohci, ed_t *edi)
-{
-       volatile ed_t *ed = edi;
-
-       ed->state = ED_OPER;
-
-       switch (ed->type) {
-       case PIPE_CONTROL:
-               ed->hwNextED = 0;
-               if (ohci->ed_controltail == NULL) {
-                       writel ((long)ed, &ohci->regs->ed_controlhead);
-               } else {
-                       ohci->ed_controltail->hwNextED = m32_swap (ed);
-               }
-               ed->ed_prev = ohci->ed_controltail;
-               if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
-                       !ohci->ed_rm_list[1] && !ohci->sleeping) {
-                       ohci->hc_control |= OHCI_CTRL_CLE;
-                       writel (ohci->hc_control, &ohci->regs->control);
-               }
-               ohci->ed_controltail = edi;
-               break;
-
-       case PIPE_BULK:
-               ed->hwNextED = 0;
-               if (ohci->ed_bulktail == NULL) {
-                       writel ((long)ed, &ohci->regs->ed_bulkhead);
-               } else {
-                       ohci->ed_bulktail->hwNextED = m32_swap (ed);
-               }
-               ed->ed_prev = ohci->ed_bulktail;
-               if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
-                       !ohci->ed_rm_list[1] && !ohci->sleeping) {
-                       ohci->hc_control |= OHCI_CTRL_BLE;
-                       writel (ohci->hc_control, &ohci->regs->control);
-               }
-               ohci->ed_bulktail = edi;
-               break;
-       }
-       return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
-{
-       ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
-
-       switch (ed->type) {
-       case PIPE_CONTROL:
-               if (ed->ed_prev == NULL) {
-                       if (!ed->hwNextED) {
-                               ohci->hc_control &= ~OHCI_CTRL_CLE;
-                               writel (ohci->hc_control, &ohci->regs->control);
-                       }
-                       writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
-               } else {
-                       ed->ed_prev->hwNextED = ed->hwNextED;
-               }
-               if (ohci->ed_controltail == ed) {
-                       ohci->ed_controltail = ed->ed_prev;
-               } else {
-                       ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
-               }
-               break;
-
-       case PIPE_BULK:
-               if (ed->ed_prev == NULL) {
-                       if (!ed->hwNextED) {
-                               ohci->hc_control &= ~OHCI_CTRL_BLE;
-                               writel (ohci->hc_control, &ohci->regs->control);
-                       }
-                       writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
-               } else {
-                       ed->ed_prev->hwNextED = ed->hwNextED;
-               }
-               if (ohci->ed_bulktail == ed) {
-                       ohci->ed_bulktail = ed->ed_prev;
-               } else {
-                       ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
-               }
-               break;
-       }
-       ed->state = ED_UNLINK;
-       return 0;
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
-
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
-{
-       td_t *td;
-       ed_t *ed_ret;
-       volatile ed_t *ed;
-
-       ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
-                       (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
-
-       if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
-               err("ep_add_ed: pending delete");
-               /* pending delete request */
-               return NULL;
-       }
-
-       if (ed->state == ED_NEW) {
-               ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
-               /* dummy td; end of td list for ed */
-               td = td_alloc (usb_dev);
-               ed->hwTailP = m32_swap (td);
-               ed->hwHeadP = ed->hwTailP;
-               ed->state = ED_UNLINK;
-               ed->type = usb_pipetype (pipe);
-               ohci_dev.ed_cnt++;
-       }
-
-       ed->hwINFO = m32_swap (usb_pipedevice (pipe)
-                       | usb_pipeendpoint (pipe) << 7
-                       | (usb_pipeisoc (pipe)? 0x8000: 0)
-                       | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
-                       | usb_pipeslow (pipe) << 13
-                       | usb_maxpacket (usb_dev, pipe) << 16);
-
-       return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill (ohci_t *ohci, unsigned int info,
-       void *data, int len,
-       struct usb_device *dev, int index, urb_priv_t *urb_priv)
-{
-       volatile td_t  *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
-       int i;
-#endif
-
-       if (index > urb_priv->length) {
-               err("index > length");
-               return;
-       }
-       /* use this td as the next dummy */
-       td_pt = urb_priv->td [index];
-       td_pt->hwNextTD = 0;
-
-       /* fill the old dummy TD */
-       td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
-
-       td->ed = urb_priv->ed;
-       td->next_dl_td = NULL;
-       td->index = index;
-       td->data = (__u32)data;
-#ifdef OHCI_FILL_TRACE
-       if (1 || (usb_pipebulk(urb_priv->pipe) &&
-                               usb_pipeout(urb_priv->pipe))) {
-               for (i = 0; i < len; i++)
-               printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
-       }
-#endif
-       if (!len)
-               data = 0;
-
-       td->hwINFO = m32_swap (info);
-       td->hwCBP = m32_swap (data);
-       if (data)
-               td->hwBE = m32_swap (data + len - 1);
-       else
-               td->hwBE = 0;
-       td->hwNextTD = m32_swap (td_pt);
-       td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
-
-       /* append to queue */
-       td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-#define kseg_to_phys(x)          ((void *)((__u32)(x) - 0x80000000))
-
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
-       int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
-{
-       ohci_t *ohci = &gohci;
-       int data_len = transfer_len;
-       void *data;
-       int cnt = 0;
-       __u32 info = 0;
-       unsigned int toggle = 0;
-
-       /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
-       if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-               toggle = TD_T_TOGGLE;
-       } else {
-               toggle = TD_T_DATA0;
-               usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
-       }
-       urb->td_cnt = 0;
-       if (data_len)
-               data = kseg_to_phys(buffer);
-       else
-               data = 0;
-
-       switch (usb_pipetype (pipe)) {
-       case PIPE_BULK:
-               info = usb_pipeout (pipe)?
-                       TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
-               while(data_len > 4096) {
-                       td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
-                       data += 4096; data_len -= 4096; cnt++;
-               }
-               info = usb_pipeout (pipe)?
-                       TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
-               td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
-               cnt++;
-
-               if (!ohci->sleeping)
-                       writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
-               break;
-
-       case PIPE_CONTROL:
-               info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
-               td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
-               if (data_len > 0) {
-                       info = usb_pipeout (pipe)?
-                               TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
-                       /* NOTE:  mishandles transfers >8K, some >4K */
-                       td_fill (ohci, info, data, data_len, dev, cnt++, urb);
-               }
-               info = usb_pipeout (pipe)?
-                       TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
-               td_fill (ohci, info, data, 0, dev, cnt++, urb);
-               if (!ohci->sleeping)
-                       writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
-               break;
-       }
-       if (urb->length != cnt)
-               dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(td_t * td)
-{
-       __u32 tdINFO, tdBE, tdCBP;
-       urb_priv_t *lurb_priv = &urb_priv;
-
-       tdINFO = m32_swap (td->hwINFO);
-       tdBE   = m32_swap (td->hwBE);
-       tdCBP  = m32_swap (td->hwCBP);
-
-
-       if (!(usb_pipecontrol(lurb_priv->pipe) &&
-           ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
-               if (tdBE != 0) {
-                       if (td->hwCBP == 0)
-                               lurb_priv->actual_length += tdBE - td->data + 1;
-                       else
-                               lurb_priv->actual_length += tdCBP - td->data;
-               }
-       }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static td_t * dl_reverse_done_list (ohci_t *ohci)
-{
-       __u32 td_list_hc;
-       td_t *td_rev = NULL;
-       td_t *td_list = NULL;
-       urb_priv_t *lurb_priv = NULL;
-
-       td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
-       ohci->hcca->done_head = 0;
-
-       while (td_list_hc) {
-               td_list = (td_t *)td_list_hc;
-
-               if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
-                       lurb_priv = &urb_priv;
-                       dbg(" USB-error/status: %x : %p",
-                                       TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
-                       if (td_list->ed->hwHeadP & m32_swap (0x1)) {
-                               if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
-                                       td_list->ed->hwHeadP =
-                                               (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
-                                                                       (td_list->ed->hwHeadP & m32_swap (0x2));
-                                       lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
-                               } else
-                                       td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
-                       }
-               }
-
-               td_list->next_dl_td = td_rev;
-               td_rev = td_list;
-               td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
-       }
-       return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
-{
-       td_t *td_list_next = NULL;
-       ed_t *ed;
-       int cc = 0;
-       int stat = 0;
-       /* urb_t *urb; */
-       urb_priv_t *lurb_priv;
-       __u32 tdINFO, edHeadP, edTailP;
-
-       while (td_list) {
-               td_list_next = td_list->next_dl_td;
-
-               lurb_priv = &urb_priv;
-               tdINFO = m32_swap (td_list->hwINFO);
-
-               ed = td_list->ed;
-
-               dl_transfer_length(td_list);
-
-               /* error code of transfer */
-               cc = TD_CC_GET (tdINFO);
-               if (cc != 0) {
-                       dbg("ConditionCode %#x", cc);
-                       stat = cc_to_error[cc];
-               }
-
-               if (ed->state != ED_NEW) {
-                       edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
-                       edTailP = m32_swap (ed->hwTailP);
-
-                       /* unlink eds if they are not busy */
-                       if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-                               ep_unlink (ohci, ed);
-               }
-
-               td_list = td_list_next;
-       }
-       return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
-       0x12,       /*  __u8  bLength; */
-       0x01,       /*  __u8  bDescriptorType; Device */
-       0x10,       /*  __u16 bcdUSB; v1.1 */
-       0x01,
-       0x09,       /*  __u8  bDeviceClass; HUB_CLASSCODE */
-       0x00,       /*  __u8  bDeviceSubClass; */
-       0x00,       /*  __u8  bDeviceProtocol; */
-       0x08,       /*  __u8  bMaxPacketSize0; 8 Bytes */
-       0x00,       /*  __u16 idVendor; */
-       0x00,
-       0x00,       /*  __u16 idProduct; */
-       0x00,
-       0x00,       /*  __u16 bcdDevice; */
-       0x00,
-       0x00,       /*  __u8  iManufacturer; */
-       0x01,       /*  __u8  iProduct; */
-       0x00,       /*  __u8  iSerialNumber; */
-       0x01        /*  __u8  bNumConfigurations; */
-};
-
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
-       0x09,       /*  __u8  bLength; */
-       0x02,       /*  __u8  bDescriptorType; Configuration */
-       0x19,       /*  __u16 wTotalLength; */
-       0x00,
-       0x01,       /*  __u8  bNumInterfaces; */
-       0x01,       /*  __u8  bConfigurationValue; */
-       0x00,       /*  __u8  iConfiguration; */
-       0x40,       /*  __u8  bmAttributes;
-                Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
-       0x00,       /*  __u8  MaxPower; */
-
-       /* interface */
-       0x09,       /*  __u8  if_bLength; */
-       0x04,       /*  __u8  if_bDescriptorType; Interface */
-       0x00,       /*  __u8  if_bInterfaceNumber; */
-       0x00,       /*  __u8  if_bAlternateSetting; */
-       0x01,       /*  __u8  if_bNumEndpoints; */
-       0x09,       /*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-       0x00,       /*  __u8  if_bInterfaceSubClass; */
-       0x00,       /*  __u8  if_bInterfaceProtocol; */
-       0x00,       /*  __u8  if_iInterface; */
-
-       /* endpoint */
-       0x07,       /*  __u8  ep_bLength; */
-       0x05,       /*  __u8  ep_bDescriptorType; Endpoint */
-       0x81,       /*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-       0x03,       /*  __u8  ep_bmAttributes; Interrupt */
-       0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-       0x00,
-       0xff        /*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] =
-{
-       0x04,                   /*  __u8  bLength; */
-       0x03,                   /*  __u8  bDescriptorType; String-descriptor */
-       0x09,                   /*  __u8  lang ID */
-       0x04,                   /*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] =
-{
-       28,                     /*  __u8  bLength; */
-       0x03,                   /*  __u8  bDescriptorType; String-descriptor */
-       'O',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'H',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'C',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'I',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       ' ',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'R',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'o',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'o',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       't',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       ' ',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'H',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'u',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-       'b',                    /*  __u8  Unicode */
-       0,                              /*  __u8  Unicode */
-};
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x)                  len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x)          {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x)      {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
-#else
-#define WR_RH_STAT(x)          writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)      writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT             roothub_status(&gohci)
-#define RD_RH_PORTSTAT         roothub_portstatus(&gohci,wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(ohci_t *controller)
-{
-       __u32 temp, ndp, i;
-       int res;
-
-       res = -1;
-       temp = roothub_a (controller);
-       ndp = (temp & RH_A_NDP);
-       for (i = 0; i < ndp; i++) {
-               temp = roothub_portstatus (controller, i);
-               /* check for a device disconnect */
-               if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
-                       (RH_PS_PESC | RH_PS_CSC)) &&
-                       ((temp & RH_PS_CCS) == 0)) {
-                       res = i;
-                       break;
-               }
-       }
-       return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-               void *buffer, int transfer_len, struct devrequest *cmd)
-{
-       void * data = buffer;
-       int leni = transfer_len;
-       int len = 0;
-       int stat = 0;
-       __u32 datab[4];
-       __u8 *data_buf = (__u8 *)datab;
-       __u16 bmRType_bReq;
-       __u16 wValue;
-       __u16 wIndex;
-       __u16 wLength;
-
-#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
-#else
-       wait_ms(1);
-#endif
-       if (usb_pipeint(pipe)) {
-               info("Root-Hub submit IRQ: NOT implemented");
-               return 0;
-       }
-
-       bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
-       wValue        = m16_swap (cmd->value);
-       wIndex        = m16_swap (cmd->index);
-       wLength       = m16_swap (cmd->length);
-
-       info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
-               dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
-       switch (bmRType_bReq) {
-       /* Request Destination:
-          without flags: Device,
-          RH_INTERFACE: interface,
-          RH_ENDPOINT: endpoint,
-          RH_CLASS means HUB here,
-          RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
-       */
-
-       case RH_GET_STATUS:
-                       *(__u16 *) data_buf = m16_swap (1); OK (2);
-       case RH_GET_STATUS | RH_INTERFACE:
-                       *(__u16 *) data_buf = m16_swap (0); OK (2);
-       case RH_GET_STATUS | RH_ENDPOINT:
-                       *(__u16 *) data_buf = m16_swap (0); OK (2);
-       case RH_GET_STATUS | RH_CLASS:
-                       *(__u32 *) data_buf = m32_swap (
-                               RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
-                       OK (4);
-       case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-                       *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
-
-       case RH_CLEAR_FEATURE | RH_ENDPOINT:
-               switch (wValue) {
-                       case (RH_ENDPOINT_STALL): OK (0);
-               }
-               break;
-
-       case RH_CLEAR_FEATURE | RH_CLASS:
-               switch (wValue) {
-                       case RH_C_HUB_LOCAL_POWER:
-                               OK(0);
-                       case (RH_C_HUB_OVER_CURRENT):
-                                       WR_RH_STAT(RH_HS_OCIC); OK (0);
-               }
-               break;
-
-       case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-               switch (wValue) {
-                       case (RH_PORT_ENABLE):
-                                       WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
-                       case (RH_PORT_SUSPEND):
-                                       WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
-                       case (RH_PORT_POWER):
-                                       WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
-                       case (RH_C_PORT_CONNECTION):
-                                       WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
-                       case (RH_C_PORT_ENABLE):
-                                       WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
-                       case (RH_C_PORT_SUSPEND):
-                                       WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
-                       case (RH_C_PORT_OVER_CURRENT):
-                                       WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
-                       case (RH_C_PORT_RESET):
-                                       WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
-               }
-               break;
-
-       case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-               switch (wValue) {
-                       case (RH_PORT_SUSPEND):
-                                       WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
-                       case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
-                                       if (RD_RH_PORTSTAT & RH_PS_CCS)
-                                           WR_RH_PORTSTAT (RH_PS_PRS);
-                                       OK (0);
-                       case (RH_PORT_POWER):
-                                       WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
-                       case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
-                                       if (RD_RH_PORTSTAT & RH_PS_CCS)
-                                           WR_RH_PORTSTAT (RH_PS_PES );
-                                       OK (0);
-               }
-               break;
-
-       case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
-
-       case RH_GET_DESCRIPTOR:
-               switch ((wValue & 0xff00) >> 8) {
-                       case (0x01): /* device descriptor */
-                               len = min_t(unsigned int,
-                                         leni,
-                                         min_t(unsigned int,
-                                             sizeof (root_hub_dev_des),
-                                             wLength));
-                               data_buf = root_hub_dev_des; OK(len);
-                       case (0x02): /* configuration descriptor */
-                               len = min_t(unsigned int,
-                                         leni,
-                                         min_t(unsigned int,
-                                             sizeof (root_hub_config_des),
-                                             wLength));
-                               data_buf = root_hub_config_des; OK(len);
-                       case (0x03): /* string descriptors */
-                               if(wValue==0x0300) {
-                                       len = min_t(unsigned int,
-                                                 leni,
-                                                 min_t(unsigned int,
-                                                     sizeof (root_hub_str_index0),
-                                                     wLength));
-                                       data_buf = root_hub_str_index0;
-                                       OK(len);
-                               }
-                               if(wValue==0x0301) {
-                                       len = min_t(unsigned int,
-                                                 leni,
-                                                 min_t(unsigned int,
-                                                     sizeof (root_hub_str_index1),
-                                                     wLength));
-                                       data_buf = root_hub_str_index1;
-                                       OK(len);
-                       }
-                       default:
-                               stat = USB_ST_STALLED;
-               }
-               break;
-
-       case RH_GET_DESCRIPTOR | RH_CLASS:
-           {
-                   __u32 temp = roothub_a (&gohci);
-
-                   data_buf [0] = 9;           /* min length; */
-                   data_buf [1] = 0x29;
-                   data_buf [2] = temp & RH_A_NDP;
-                   data_buf [3] = 0;
-                   if (temp & RH_A_PSM)        /* per-port power switching? */
-                       data_buf [3] |= 0x1;
-                   if (temp & RH_A_NOCP)       /* no overcurrent reporting? */
-                       data_buf [3] |= 0x10;
-                   else if (temp & RH_A_OCPM)  /* per-port overcurrent reporting? */
-                       data_buf [3] |= 0x8;
-
-                   /* corresponds to data_buf[4-7] */
-                   datab [1] = 0;
-                   data_buf [5] = (temp & RH_A_POTPGT) >> 24;
-                   temp = roothub_b (&gohci);
-                   data_buf [7] = temp & RH_B_DR;
-                   if (data_buf [2] < 7) {
-                       data_buf [8] = 0xff;
-                   } else {
-                       data_buf [0] += 2;
-                       data_buf [8] = (temp & RH_B_DR) >> 8;
-                       data_buf [10] = data_buf [9] = 0xff;
-                   }
-
-                   len = min_t(unsigned int, leni,
-                             min_t(unsigned int, data_buf [0], wLength));
-                   OK (len);
-               }
-
-       case RH_GET_CONFIGURATION:      *(__u8 *) data_buf = 0x01; OK (1);
-
-       case RH_SET_CONFIGURATION:      WR_RH_STAT (0x10000); OK (0);
-
-       default:
-               dbg ("unsupported root hub command");
-               stat = USB_ST_STALLED;
-       }
-
-#ifdef DEBUG
-       ohci_dump_roothub (&gohci, 1);
-#else
-       wait_ms(1);
-#endif
-
-       len = min_t(int, len, leni);
-       if (data != data_buf)
-           memcpy (data, data_buf, len);
-       dev->act_len = len;
-       dev->status = stat;
-
-#ifdef DEBUG
-       if (transfer_len)
-               urb_priv.actual_length = transfer_len;
-       pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
-#else
-       wait_ms(1);
-#endif
-
-       return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-               int transfer_len, struct devrequest *setup, int interval)
-{
-       int stat = 0;
-       int maxsize = usb_maxpacket(dev, pipe);
-       int timeout;
-
-       /* device pulled? Shortcut the action. */
-       if (devgone == dev) {
-               dev->status = USB_ST_CRC_ERR;
-               return 0;
-       }
-
-#ifdef DEBUG
-       urb_priv.actual_length = 0;
-       pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
-       wait_ms(1);
-#endif
-       if (!maxsize) {
-               err("submit_common_message: pipesize for pipe %lx is zero",
-                       pipe);
-               return -1;
-       }
-
-       if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
-               err("sohci_submit_job failed");
-               return -1;
-       }
-
-       wait_ms(10);
-       /* ohci_dump_status(&gohci); */
-
-       /* allow more time for a BULK device to react - some are slow */
-#define BULK_TO         5000   /* timeout in milliseconds */
-       if (usb_pipebulk(pipe))
-               timeout = BULK_TO;
-       else
-               timeout = 100;
-
-       timeout *= 4;
-       /* wait for it to complete */
-       for (;;) {
-               /* check whether the controller is done */
-               stat = hc_interrupt();
-               if (stat < 0) {
-                       stat = USB_ST_CRC_ERR;
-                       break;
-               }
-               if (stat >= 0 && stat != 0xff) {
-                       /* 0xff is returned for an SF-interrupt */
-                       break;
-               }
-               if (--timeout) {
-                       udelay(250); /* wait_ms(1); */
-               } else {
-                       err("CTL:TIMEOUT ");
-                       stat = USB_ST_CRC_ERR;
-                       break;
-               }
-       }
-       /* we got an Root Hub Status Change interrupt */
-       if (got_rhsc) {
-#ifdef DEBUG
-               ohci_dump_roothub (&gohci, 1);
-#endif
-               got_rhsc = 0;
-               /* abuse timeout */
-               timeout = rh_check_port_status(&gohci);
-               if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
-                       /* the called routine adds 1 to the passed value */
-                       usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
-                       /*
-                        * XXX
-                        * This is potentially dangerous because it assumes
-                        * that only one device is ever plugged in!
-                        */
-                       devgone = dev;
-               }
-       }
-
-       dev->status = stat;
-       dev->act_len = transfer_len;
-
-#ifdef DEBUG
-       pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
-#else
-       wait_ms(1);
-#endif
-
-       /* free TDs in urb_priv */
-       urb_free_priv (&urb_priv);
-       return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-               int transfer_len)
-{
-       info("submit_bulk_msg");
-       return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-               int transfer_len, struct devrequest *setup)
-{
-       int maxsize = usb_maxpacket(dev, pipe);
-
-       info("submit_control_msg");
-#ifdef DEBUG
-       urb_priv.actual_length = 0;
-       pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
-       wait_ms(1);
-#endif
-       if (!maxsize) {
-               err("submit_control_message: pipesize for pipe %lx is zero",
-                       pipe);
-               return -1;
-       }
-       if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
-               gohci.rh.dev = dev;
-               /* root hub - redirect */
-               return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-                       setup);
-       }
-
-       return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-               int transfer_len, int interval)
-{
-       info("submit_int_msg");
-       return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset (ohci_t *ohci)
-{
-       int timeout = 30;
-       int smm_timeout = 50; /* 0,5 sec */
-
-       if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
-               writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
-               info("USB HC TakeOver from SMM");
-               while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
-                       wait_ms (10);
-                       if (--smm_timeout == 0) {
-                               err("USB HC TakeOver failed!");
-                               return -1;
-                       }
-               }
-       }
-
-       /* Disable HC interrupts */
-       writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
-       dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
-               ohci->slot_name,
-               readl (&ohci->regs->control));
-
-       /* Reset USB (needed by some controllers) */
-       writel (0, &ohci->regs->control);
-
-       /* HC Reset requires max 10 us delay */
-       writel (OHCI_HCR,  &ohci->regs->cmdstatus);
-       while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-               if (--timeout == 0) {
-                       err("USB HC reset timed out!");
-                       return -1;
-               }
-               udelay (1);
-       }
-       return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start (ohci_t * ohci)
-{
-       __u32 mask;
-       unsigned int fminterval;
-
-       ohci->disabled = 1;
-
-       /* Tell the controller where the control and bulk lists are
-        * The lists are empty now. */
-
-       writel (0, &ohci->regs->ed_controlhead);
-       writel (0, &ohci->regs->ed_bulkhead);
-
-       writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
-
-       fminterval = 0x2edf;
-       writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
-       fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-       writel (fminterval, &ohci->regs->fminterval);
-       writel (0x628, &ohci->regs->lsthresh);
-
-       /* start controller operations */
-       ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
-       ohci->disabled = 0;
-       writel (ohci->hc_control, &ohci->regs->control);
-
-       /* disable all interrupts */
-       mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
-                       OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
-                       OHCI_INTR_OC | OHCI_INTR_MIE);
-       writel (mask, &ohci->regs->intrdisable);
-       /* clear all interrupts */
-       mask &= ~OHCI_INTR_MIE;
-       writel (mask, &ohci->regs->intrstatus);
-       /* Choose the interrupts we care about now  - but w/o MIE */
-       mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-       writel (mask, &ohci->regs->intrenable);
-
-#ifdef OHCI_USE_NPS
-       /* required for AMD-756 and some Mac platforms */
-       writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
-               &ohci->regs->roothub.a);
-       writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
-#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
-       /* POTPGT delay is bits 24-31, in 2 ms units. */
-       mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
-
-       /* connect the virtual root hub */
-       ohci->rh.devnum = 0;
-
-       return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int
-hc_interrupt (void)
-{
-       ohci_t *ohci = &gohci;
-       struct ohci_regs *regs = ohci->regs;
-       int ints;
-       int stat = -1;
-
-       if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
-               ints =  OHCI_INTR_WDH;
-       } else {
-               ints = readl (&regs->intrstatus);
-       }
-
-       /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
-
-       if (ints & OHCI_INTR_RHSC) {
-               got_rhsc = 1;
-       }
-
-       if (ints & OHCI_INTR_UE) {
-               ohci->disabled++;
-               err ("OHCI Unrecoverable Error, controller usb-%s disabled",
-                       ohci->slot_name);
-               /* e.g. due to PCI Master/Target Abort */
-
-#ifdef DEBUG
-               ohci_dump (ohci, 1);
-#else
-       wait_ms(1);
-#endif
-               /* FIXME: be optimistic, hope that bug won't repeat often. */
-               /* Make some non-interrupt context restart the controller. */
-               /* Count and limit the retries though; either hardware or */
-               /* software errors can go forever... */
-               hc_reset (ohci);
-               return -1;
-       }
-
-       if (ints & OHCI_INTR_WDH) {
-               wait_ms(1);
-               writel (OHCI_INTR_WDH, &regs->intrdisable);
-               stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
-               writel (OHCI_INTR_WDH, &regs->intrenable);
-       }
-
-       if (ints & OHCI_INTR_SO) {
-               dbg("USB Schedule overrun\n");
-               writel (OHCI_INTR_SO, &regs->intrenable);
-               stat = -1;
-       }
-
-       /* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
-       if (ints & OHCI_INTR_SF) {
-               unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
-               wait_ms(1);
-               writel (OHCI_INTR_SF, &regs->intrdisable);
-               if (ohci->ed_rm_list[frame] != NULL)
-                       writel (OHCI_INTR_SF, &regs->intrenable);
-               stat = 0xff;
-       }
-
-       writel (ints, &regs->intrstatus);
-       return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci (ohci_t *ohci)
-{
-       dbg ("USB HC release ohci usb-%s", ohci->slot_name);
-
-       if (!ohci->disabled)
-               hc_reset (ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#define __read_32bit_c0_register(source, sel)                          \
-({ int __res;                                                          \
-       if (sel == 0)                                                   \
-               __asm__ __volatile__(                                   \
-                       "mfc0\t%0, " #source "\n\t"                     \
-                       : "=r" (__res));                                \
-       else                                                            \
-               __asm__ __volatile__(                                   \
-                       ".set\tmips32\n\t"                              \
-                       "mfc0\t%0, " #source ", " #sel "\n\t"           \
-                       ".set\tmips0\n\t"                               \
-                       : "=r" (__res));                                \
-       __res;                                                          \
-})
-
-#define read_c0_prid()         __read_32bit_c0_register($15, 0)
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(void)
-{
-       u32 pin_func;
-       u32 sys_freqctrl, sys_clksrc;
-       u32 prid = read_c0_prid();
-
-       dbg("in usb_lowlevel_init\n");
-
-       /* zero and disable FREQ2 */
-       sys_freqctrl = au_readl(SYS_FREQCTRL0);
-       sys_freqctrl &= ~0xFFF00000;
-       au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
-       /* zero and disable USBH/USBD clocks */
-       sys_clksrc = au_readl(SYS_CLKSRC);
-       sys_clksrc &= ~0x00007FE0;
-       au_writel(sys_clksrc, SYS_CLKSRC);
-
-       sys_freqctrl = au_readl(SYS_FREQCTRL0);
-       sys_freqctrl &= ~0xFFF00000;
-
-       sys_clksrc = au_readl(SYS_CLKSRC);
-       sys_clksrc &= ~0x00007FE0;
-
-       switch (prid & 0x000000FF) {
-       case 0x00: /* DA */
-       case 0x01: /* HA */
-       case 0x02: /* HB */
-               /* CPU core freq to 48MHz to slow it way down... */
-               au_writel(4, SYS_CPUPLL);
-
-               /*
-                * Setup 48MHz FREQ2 from CPUPLL for USB Host
-                */
-               /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
-               sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
-               au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
-               /* CPU core freq to 384MHz */
-               au_writel(0x20, SYS_CPUPLL);
-
-               printf("Au1000: 48MHz OHCI workaround enabled\n");
-               break;
-
-       default:  /* HC and newer */
-               /* FREQ2 = aux/2 = 48 MHz */
-               sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
-               au_writel(sys_freqctrl, SYS_FREQCTRL0);
-               break;
-       }
-
-       /*
-        * Route 48MHz FREQ2 into USB Host and/or Device
-        */
-       sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
-       au_writel(sys_clksrc, SYS_CLKSRC);
-
-       /* configure pins GPIO[14:9] as GPIO */
-       pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
-
-       au_writel(pin_func, SYS_PINFUNC);
-       au_writel(0x2800, SYS_TRIOUTCLR);
-       au_writel(0x0030, SYS_OUTPUTCLR);
-
-       dbg("OHCI board setup complete\n");
-
-       /* enable host controller */
-       au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
-       udelay(1000);
-       au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
-       udelay(1000);
-
-       /* wait for reset complete (read register twice; see au1500 errata) */
-       while (au_readl(USB_HOST_CONFIG),
-              !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
-               udelay(1000);
-
-       dbg("OHCI clock running\n");
-
-       memset (&gohci, 0, sizeof (ohci_t));
-       memset (&urb_priv, 0, sizeof (urb_priv_t));
-
-       /* align the storage */
-       if ((__u32)&ghcca[0] & 0xff) {
-               err("HCCA not aligned!!");
-               return -1;
-       }
-       phcca = &ghcca[0];
-       info("aligned ghcca %p", phcca);
-       memset(&ohci_dev, 0, sizeof(struct ohci_device));
-       if ((__u32)&ohci_dev.ed[0] & 0x7) {
-               err("EDs not aligned!!");
-               return -1;
-       }
-       memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
-       if ((__u32)gtd & 0x7) {
-               err("TDs not aligned!!");
-               return -1;
-       }
-       ptd = gtd;
-       gohci.hcca = phcca;
-       memset (phcca, 0, sizeof (struct ohci_hcca));
-
-       gohci.disabled = 1;
-       gohci.sleeping = 0;
-       gohci.irq = -1;
-       gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
-
-       gohci.flags = 0;
-       gohci.slot_name = "au1x00";
-
-       dbg("OHCI revision: 0x%08x\n"
-              "  RH: a: 0x%08x b: 0x%08x\n",
-              readl(&gohci.regs->revision),
-              readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
-
-       if (hc_reset (&gohci) < 0)
-               goto errout;
-
-       /* FIXME this is a second HC reset; why?? */
-       writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
-       wait_ms (10);
-
-       if (hc_start (&gohci) < 0)
-               goto errout;
-
-#ifdef DEBUG
-       ohci_dump (&gohci, 1);
-#else
-       wait_ms(1);
-#endif
-       ohci_inited = 1;
-       return 0;
-
-  errout:
-       err("OHCI initialization error\n");
-       hc_release_ohci (&gohci);
-       /* Initialization failed */
-       au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
-       return -1;
-}
-
-int usb_lowlevel_stop(void)
-{
-       /* this gets called really early - before the controller has */
-       /* even been initialized! */
-       if (!ohci_inited)
-               return 0;
-       /* TODO release any interrupts, etc. */
-       /* call hc_release_ohci() here ? */
-       hc_reset (&gohci);
-       /* may not want to do this */
-       /* Disable clock */
-       au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
-       return 0;
-}
-
-#endif /* CONFIG_USB_OHCI */
diff --git a/arch/mips/cpu/au1x00_usb_ohci.h b/arch/mips/cpu/au1x00_usb_ohci.h
deleted file mode 100644 (file)
index bb9f351..0000000
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
-       /* No  Error  */        0,
-       /* CRC Error  */        USB_ST_CRC_ERR,
-       /* Bit Stuff  */        USB_ST_BIT_ERR,
-       /* Data Togg  */        USB_ST_CRC_ERR,
-       /* Stall      */        USB_ST_STALLED,
-       /* DevNotResp */        -1,
-       /* PIDCheck   */        USB_ST_BIT_ERR,
-       /* UnExpPID   */        USB_ST_BIT_ERR,
-       /* DataOver   */        USB_ST_BUF_ERR,
-       /* DataUnder  */        USB_ST_BUF_ERR,
-       /* reservd    */        -1,
-       /* reservd    */        -1,
-       /* BufferOver */        USB_ST_BUF_ERR,
-       /* BuffUnder  */        USB_ST_BUF_ERR,
-       /* Not Access */        -1,
-       /* Not Access */        -1
-};
-
-/* ED States */
-
-#define ED_NEW         0x00
-#define ED_UNLINK      0x01
-#define ED_OPER                0x02
-#define ED_DEL         0x04
-#define ED_URB_DEL     0x08
-
-/* usb_ohci_ed */
-struct ed {
-       __u32 hwINFO;
-       __u32 hwTailP;
-       __u32 hwHeadP;
-       __u32 hwNextED;
-
-       struct ed *ed_prev;
-       __u8 int_period;
-       __u8 int_branch;
-       __u8 int_load;
-       __u8 int_interval;
-       __u8 state;
-       __u8 type;
-       __u16 last_iso;
-       struct ed *ed_rm_list;
-
-       struct usb_device *usb_dev;
-       __u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
-
-/* TD info field */
-#define TD_CC                  0xf0000000
-#define TD_CC_GET(td_p)                ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc)    (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC                  0x0C000000
-#define TD_T                   0x03000000
-#define TD_T_DATA0             0x02000000
-#define TD_T_DATA1             0x03000000
-#define TD_T_TOGGLE            0x00000000
-#define TD_R                   0x00040000
-#define TD_DI                  0x00E00000
-#define TD_DI_SET(X)           (((X) & 0x07)<< 21)
-#define TD_DP                  0x00180000
-#define TD_DP_SETUP            0x00000000
-#define TD_DP_IN               0x00100000
-#define TD_DP_OUT              0x00080000
-
-#define TD_ISO                 0x00010000
-#define TD_DEL                 0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR          0x00
-#define TD_CC_CRC              0x01
-#define TD_CC_BITSTUFFING      0x02
-#define TD_CC_DATATOGGLEM      0x03
-#define TD_CC_STALL            0x04
-#define TD_DEVNOTRESP          0x05
-#define TD_PIDCHECKFAIL                0x06
-#define TD_UNEXPECTEDPID       0x07
-#define TD_DATAOVERRUN         0x08
-#define TD_DATAUNDERRUN                0x09
-#define TD_BUFFEROVERRUN       0x0C
-#define TD_BUFFERUNDERRUN      0x0D
-#define TD_NOTACCESSED         0x0F
-
-
-#define MAXPSW 1
-
-struct td {
-       __u32 hwINFO;
-       __u32 hwCBP;            /* Current Buffer Pointer */
-       __u32 hwNextTD;         /* Next TD Pointer */
-       __u32 hwBE;             /* Memory Buffer End Pointer */
-
-       __u16 hwPSW[MAXPSW];
-       __u8 unused;
-       __u8 index;
-       struct ed *ed;
-       struct td *next_dl_td;
-       struct usb_device *usb_dev;
-       int transfer_len;
-       __u32 data;
-
-       __u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
-
-#define OHCI_ED_SKIP   (1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of.  It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32    /* part of the OHCI standard */
-struct ohci_hcca {
-       __u32   int_table[NUM_INTS];    /* Interrupt ED table */
-       __u16   frame_no;               /* current frame number */
-       __u16   pad1;                   /* set to 0 on each frame_no change */
-       __u32   done_head;              /* info returned for an interrupt */
-       u8              reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS 15      /* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O. You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
-       /* control and status registers */
-       __u32   revision;
-       __u32   control;
-       __u32   cmdstatus;
-       __u32   intrstatus;
-       __u32   intrenable;
-       __u32   intrdisable;
-       /* memory pointers */
-       __u32   hcca;
-       __u32   ed_periodcurrent;
-       __u32   ed_controlhead;
-       __u32   ed_controlcurrent;
-       __u32   ed_bulkhead;
-       __u32   ed_bulkcurrent;
-       __u32   donehead;
-       /* frame counters */
-       __u32   fminterval;
-       __u32   fmremaining;
-       __u32   fmnumber;
-       __u32   periodicstart;
-       __u32   lsthresh;
-       /* Root hub ports */
-       struct  ohci_roothub_regs {
-               __u32   a;
-               __u32   b;
-               __u32   status;
-               __u32   portstatus[MAX_ROOT_PORTS];
-       } roothub;
-} __attribute__((aligned(32)));
-
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR (3 << 0)        /* control/bulk service ratio */
-#define OHCI_CTRL_PLE  (1 << 2)        /* periodic list enable */
-#define OHCI_CTRL_IE   (1 << 3)        /* isochronous enable */
-#define OHCI_CTRL_CLE  (1 << 4)        /* control list enable */
-#define OHCI_CTRL_BLE  (1 << 5)        /* bulk list enable */
-#define OHCI_CTRL_HCFS (3 << 6)        /* host controller functional state */
-#define OHCI_CTRL_IR   (1 << 8)        /* interrupt routing */
-#define OHCI_CTRL_RWC  (1 << 9)        /* remote wakeup connected */
-#define OHCI_CTRL_RWE  (1 << 10)       /* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-#      define OHCI_USB_RESET   (0 << 6)
-#      define OHCI_USB_RESUME  (1 << 6)
-#      define OHCI_USB_OPER    (2 << 6)
-#      define OHCI_USB_SUSPEND (3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR       (1 << 0)        /* host controller reset */
-#define OHCI_CLF       (1 << 1)        /* control list filled */
-#define OHCI_BLF       (1 << 2)        /* bulk list filled */
-#define OHCI_OCR       (1 << 3)        /* ownership change request */
-#define OHCI_SOC       (3 << 16)       /* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO   (1 << 0)        /* scheduling overrun */
-#define OHCI_INTR_WDH  (1 << 1)        /* writeback of done_head */
-#define OHCI_INTR_SF   (1 << 2)        /* start frame */
-#define OHCI_INTR_RD   (1 << 3)        /* resume detect */
-#define OHCI_INTR_UE   (1 << 4)        /* unrecoverable error */
-#define OHCI_INTR_FNO  (1 << 5)        /* frame number overflow */
-#define OHCI_INTR_RHSC (1 << 6)        /* root hub status change */
-#define OHCI_INTR_OC   (1 << 30)       /* ownership change */
-#define OHCI_INTR_MIE  (1 << 31)       /* master interrupt enable */
-
-
-/* Virtual Root HUB */
-struct virt_root_hub {
-       int devnum; /* Address of Root Hub endpoint */
-       void *dev;  /* was urb */
-       void *int_addr;
-       int send;
-       int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE           0x01
-#define RH_ENDPOINT            0x02
-#define RH_OTHER               0x03
-
-#define RH_CLASS               0x20
-#define RH_VENDOR              0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS          0x0080
-#define RH_CLEAR_FEATURE       0x0100
-#define RH_SET_FEATURE         0x0300
-#define RH_SET_ADDRESS         0x0500
-#define RH_GET_DESCRIPTOR      0x0680
-#define RH_SET_DESCRIPTOR      0x0700
-#define RH_GET_CONFIGURATION   0x0880
-#define RH_SET_CONFIGURATION   0x0900
-#define RH_GET_STATE           0x0280
-#define RH_GET_INTERFACE       0x0A80
-#define RH_SET_INTERFACE       0x0B00
-#define RH_SYNC_FRAME          0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP              0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION     0x00
-#define RH_PORT_ENABLE         0x01
-#define RH_PORT_SUSPEND                0x02
-#define RH_PORT_OVER_CURRENT   0x03
-#define RH_PORT_RESET          0x04
-#define RH_PORT_POWER          0x08
-#define RH_PORT_LOW_SPEED      0x09
-
-#define RH_C_PORT_CONNECTION   0x10
-#define RH_C_PORT_ENABLE       0x11
-#define RH_C_PORT_SUSPEND      0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET                0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER   0x00
-#define RH_C_HUB_OVER_CURRENT  0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL      0x01
-
-#define RH_ACK                 0x01
-#define RH_REQ_ERR             -1
-#define RH_NACK                        0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS              0x00000001      /* current connect status */
-#define RH_PS_PES              0x00000002      /* port enable status*/
-#define RH_PS_PSS              0x00000004      /* port suspend status */
-#define RH_PS_POCI             0x00000008      /* port over current indicator */
-#define RH_PS_PRS              0x00000010      /* port reset status */
-#define RH_PS_PPS              0x00000100      /* port power status */
-#define RH_PS_LSDA             0x00000200      /* low speed device attached */
-#define RH_PS_CSC              0x00010000      /* connect status change */
-#define RH_PS_PESC             0x00020000      /* port enable status change */
-#define RH_PS_PSSC             0x00040000      /* port suspend status change */
-#define RH_PS_OCIC             0x00080000      /* over current indicator change */
-#define RH_PS_PRSC             0x00100000      /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS              0x00000001      /* local power status */
-#define RH_HS_OCI              0x00000002      /* over current indicator */
-#define RH_HS_DRWE             0x00008000      /* device remote wakeup enable */
-#define RH_HS_LPSC             0x00010000      /* local power status change */
-#define RH_HS_OCIC             0x00020000      /* over current indicator change */
-#define RH_HS_CRWE             0x80000000      /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR                        0x0000ffff      /* device removable flags */
-#define RH_B_PPCM              0xffff0000      /* port power control mask */
-
-/* roothub.a masks */
-#define        RH_A_NDP                (0xff << 0)     /* number of downstream ports */
-#define        RH_A_PSM                (1 << 8)        /* power switching mode */
-#define        RH_A_NPS                (1 << 9)        /* no power switching */
-#define        RH_A_DT                 (1 << 10)       /* device type (mbz) */
-#define        RH_A_OCPM               (1 << 11)       /* over current protection mode */
-#define        RH_A_NOCP               (1 << 12)       /* no over current protection */
-#define        RH_A_POTPGT             (0xff << 24)    /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-typedef struct
-{
-       ed_t *ed;
-       __u16 length;           /* number of tds associated with this request */
-       __u16 td_cnt;           /* number of tds already serviced */
-       int   state;
-       unsigned long pipe;
-       int actual_length;
-       td_t *td[N_URB_TD];     /* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-typedef struct ohci {
-       struct ohci_hcca *hcca;         /* hcca */
-       /*dma_addr_t hcca_dma;*/
-
-       int irq;
-       int disabled;                   /* e.g. got a UE, we're hung */
-       int sleeping;
-       unsigned long flags;            /* for HC bugs */
-
-       struct ohci_regs *regs;         /* OHCI controller's memory */
-
-       ed_t *ed_rm_list[2];            /* lists of all endpoints to be removed */
-       ed_t *ed_bulktail;              /* last endpoint of bulk list */
-       ed_t *ed_controltail;           /* last endpoint of control list */
-       int intrstatus;
-       __u32 hc_control;               /* copy of the hc control reg */
-       struct usb_device *dev[32];
-       struct virt_root_hub rh;
-
-       const char      *slot_name;
-} ohci_t;
-
-#define NUM_EDS 8              /* num of preallocated endpoint descriptors */
-
-struct ohci_device {
-       ed_t    ed[NUM_EDS];
-       int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-td_t gtd[NUM_TD+1];
-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *
-td_alloc (struct usb_device *usb_dev)
-{
-       int i;
-       struct td       *td;
-
-       td = NULL;
-       for (i = 0; i < NUM_TD; i++) {
-               if (ptd[i].usb_dev == NULL) {
-                       td = &ptd[i];
-                       td->usb_dev = usb_dev;
-                       break;
-               }
-       }
-       return td;
-}
-
-static inline void
-ed_free (struct ed *ed)
-{
-       ed->usb_dev = NULL;
-}
diff --git a/arch/mips/cpu/cache.S b/arch/mips/cpu/cache.S
deleted file mode 100644 (file)
index 4b30c89..0000000
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- *  Cache-handling routined for MIPS CPUs
- *
- *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/asm.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-#define RA             t8
-
-/*
- * 16kB is the maximum size of instruction and data caches on MIPS 4K,
- * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
- *
- * Note that the above size is the maximum size of primary cache. U-Boot
- * doesn't have L2 cache support for now.
- */
-#define MIPS_MAX_CACHE_SIZE    0x10000
-
-#define INDEX_BASE     CKSEG0
-
-       .macro  cache_op op addr
-       .set    push
-       .set    noreorder
-       .set    mips3
-       cache   \op, 0(\addr)
-       .set    pop
-       .endm
-
-/*
- * cacheop macro to automate cache operations
- * first some helpers...
- */
-#define _mincache(size, maxsize) \
-   bltu  size,maxsize,9f ; \
-   move  size,maxsize ;    \
-9:
-
-#define _align(minaddr, maxaddr, linesize) \
-   .set noat ; \
-   subu  AT,linesize,1 ;   \
-   not   AT ;        \
-   and   minaddr,AT ;      \
-   addu  maxaddr,-1 ;      \
-   and   maxaddr,AT ;      \
-   .set at
-
-/* general operations */
-#define doop1(op1) \
-   cache op1,0(a0)
-#define doop2(op1, op2) \
-   cache op1,0(a0) ;    \
-   nop ;          \
-   cache op2,0(a0)
-
-/* specials for cache initialisation */
-#define doop1lw(op1) \
-   lw zero,0(a0)
-#define doop1lw1(op1) \
-   cache op1,0(a0) ;    \
-   lw zero,0(a0) ;      \
-   cache op1,0(a0)
-#define doop121(op1,op2) \
-   cache op1,0(a0) ;    \
-   nop;           \
-   cache op2,0(a0) ;    \
-   nop;           \
-   cache op1,0(a0)
-
-#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
-   .set  noreorder ;    \
-10:   doop##tag##ops ;  \
-   bne     minaddr,maxaddr,10b ; \
-   add      minaddr,linesize ;   \
-   .set  reorder
-
-/* finally the cache operation macros */
-#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
-   blez  n,11f ;        \
-   addu  n,kva ;        \
-   _align(kva, n, cacheLineSize) ; \
-   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
-11:
-
-#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
-   _mincache(n, cacheSize);   \
-   blez  n,11f ;        \
-   addu  n,kva ;        \
-   _align(kva, n, cacheLineSize) ; \
-   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
-11:
-
-#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
-   vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
-
-#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
-   icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
-
-       .macro  f_fill64 dst, offset, val
-       LONG_S  \val, (\offset +  0 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  1 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  2 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  3 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  4 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  5 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  6 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  7 * LONGSIZE)(\dst)
-#if LONGSIZE == 4
-       LONG_S  \val, (\offset +  8 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset +  9 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset + 10 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset + 11 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset + 12 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset + 13 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset + 14 * LONGSIZE)(\dst)
-       LONG_S  \val, (\offset + 15 * LONGSIZE)(\dst)
-#endif
-       .endm
-
-/*
- * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
- */
-LEAF(mips_init_icache)
-       blez    a1, 9f
-       mtc0    zero, CP0_TAGLO
-       /* clear tag to invalidate */
-       PTR_LI          t0, INDEX_BASE
-       PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_I t0
-       PTR_ADDU        t0, a2
-       bne             t0, t1, 1b
-       /* fill once, so data field parity is correct */
-       PTR_LI          t0, INDEX_BASE
-2:     cache_op        Fill t0
-       PTR_ADDU        t0, a2
-       bne             t0, t1, 2b
-       /* invalidate again - prudent but not strictly neccessary */
-       PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_I t0
-       PTR_ADDU        t0, a2
-       bne             t0, t1, 1b
-9:     jr      ra
-       END(mips_init_icache)
-
-/*
- * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
- */
-LEAF(mips_init_dcache)
-       blez    a1, 9f
-       mtc0    zero, CP0_TAGLO
-       /* clear all tags */
-       PTR_LI          t0, INDEX_BASE
-       PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_D t0
-       PTR_ADDU        t0, a2
-       bne             t0, t1, 1b
-       /* load from each line (in cached space) */
-       PTR_LI          t0, INDEX_BASE
-2:     LONG_L          zero, 0(t0)
-       PTR_ADDU        t0, a2
-       bne             t0, t1, 2b
-       /* clear all tags */
-       PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_D t0
-       PTR_ADDU        t0, a2
-       bne             t0, t1, 1b
-9:     jr      ra
-       END(mips_init_dcache)
-
-/*******************************************************************************
-*
-* mips_cache_reset - low level initialisation of the primary caches
-*
-* This routine initialises the primary caches to ensure that they
-* have good parity.  It must be called by the ROM before any cached locations
-* are used to prevent the possibility of data with bad parity being written to
-* memory.
-* To initialise the instruction cache it is essential that a source of data
-* with good parity is available. This routine
-* will initialise an area of memory starting at location zero to be used as
-* a source of parity.
-*
-* RETURNS: N/A
-*
-*/
-NESTED(mips_cache_reset, 0, ra)
-       move    RA, ra
-       li      t2, CONFIG_SYS_ICACHE_SIZE
-       li      t3, CONFIG_SYS_DCACHE_SIZE
-       li      t4, CONFIG_SYS_CACHELINE_SIZE
-       move    t5, t4
-
-       li      v0, MIPS_MAX_CACHE_SIZE
-
-       /*
-        * Now clear that much memory starting from zero.
-        */
-       PTR_LI          a0, CKSEG1
-       PTR_ADDU        a1, a0, v0
-2:     PTR_ADDIU       a0, 64
-       f_fill64        a0, -64, zero
-       bne             a0, a1, 2b
-
-       /*
-        * The caches are probably in an indeterminate state,
-        * so we force good parity into them by doing an
-        * invalidate, load/fill, invalidate for each line.
-        */
-
-       /*
-        * Assume bottom of RAM will generate good parity for the cache.
-        */
-
-       /*
-        * Initialize the I-cache first,
-        */
-       move    a1, t2
-       move    a2, t4
-       PTR_LA  t7, mips_init_icache
-       jalr    t7
-
-       /*
-        * then initialize D-cache.
-        */
-       move    a1, t3
-       move    a2, t5
-       PTR_LA  t7, mips_init_dcache
-       jalr    t7
-
-       jr      RA
-       END(mips_cache_reset)
-
-/*******************************************************************************
-*
-* dcache_status - get cache status
-*
-* RETURNS: 0 - cache disabled; 1 - cache enabled
-*
-*/
-LEAF(dcache_status)
-       mfc0    t0, CP0_CONFIG
-       li      t1, CONF_CM_UNCACHED
-       andi    t0, t0, CONF_CM_CMASK
-       move    v0, zero
-       beq     t0, t1, 2f
-       li      v0, 1
-2:     jr      ra
-       END(dcache_status)
-
-/*******************************************************************************
-*
-* dcache_disable - disable cache
-*
-* RETURNS: N/A
-*
-*/
-LEAF(dcache_disable)
-       mfc0    t0, CP0_CONFIG
-       li      t1, -8
-       and     t0, t0, t1
-       ori     t0, t0, CONF_CM_UNCACHED
-       mtc0    t0, CP0_CONFIG
-       jr      ra
-       END(dcache_disable)
-
-/*******************************************************************************
-*
-* dcache_enable - enable cache
-*
-* RETURNS: N/A
-*
-*/
-LEAF(dcache_enable)
-       mfc0    t0, CP0_CONFIG
-       ori     t0, CONF_CM_CMASK
-       xori    t0, CONF_CM_CMASK
-       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
-       mtc0    t0, CP0_CONFIG
-       jr      ra
-       END(dcache_enable)
-
-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
-/*******************************************************************************
-*
-* mips_cache_lock - lock RAM area pointed to by a0 in cache.
-*
-* RETURNS: N/A
-*
-*/
-#if defined(CONFIG_PURPLE)
-# define       CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
-#else
-# define       CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
-#endif
-       .globl  mips_cache_lock
-       .ent    mips_cache_lock
-mips_cache_lock:
-       li      a1, CKSEG0 - CACHE_LOCK_SIZE
-       addu    a0, a1
-       li      a2, CACHE_LOCK_SIZE
-       li      a3, CONFIG_SYS_CACHELINE_SIZE
-       move    a1, a2
-       icacheop(a0,a1,a2,a3,0x1d)
-
-       jr      ra
-
-       .end    mips_cache_lock
-#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
diff --git a/arch/mips/cpu/config.mk b/arch/mips/cpu/config.mk
deleted file mode 100644 (file)
index a173c54..0000000
+++ /dev/null
@@ -1,39 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
-MIPSFLAGS:=$(shell \
-if [ "$v" -lt "14" ]; then \
-       echo "-mcpu=4kc"; \
-else \
-       echo "-march=4kc -mtune=4kc"; \
-fi)
-
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS = -EL
-else
-ENDIANNESS = -EB
-endif
-
-MIPSFLAGS += $(ENDIANNESS)
-
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
deleted file mode 100644 (file)
index 3ae397c..0000000
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#define cache_op(op,addr)                                              \
-       __asm__ __volatile__(                                           \
-       "       .set    push                                    \n"     \
-       "       .set    noreorder                               \n"     \
-       "       .set    mips3\n\t                               \n"     \
-       "       cache   %0, %1                                  \n"     \
-       "       .set    pop                                     \n"     \
-       :                                                               \
-       : "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       _machine_restart();
-
-       fprintf(stderr, "*** reset failed ***\n");
-       return 0;
-}
-
-void flush_cache(ulong start_addr, ulong size)
-{
-       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
-
-       while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
-               if (addr == aend)
-                       break;
-               addr += lsize;
-       }
-}
-
-void flush_dcache_range(ulong start_addr, ulong stop)
-{
-       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-       while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               if (addr == aend)
-                       break;
-               addr += lsize;
-       }
-}
-
-void invalidate_dcache_range(ulong start_addr, ulong stop)
-{
-       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (stop - 1) & ~(lsize - 1);
-
-       while (1) {
-               cache_op(Hit_Invalidate_D, addr);
-               if (addr == aend)
-                       break;
-               addr += lsize;
-       }
-}
-
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
-       write_c0_entrylo0(low0);
-       write_c0_pagemask(pagemask);
-       write_c0_entrylo1(low1);
-       write_c0_entryhi(hi);
-       write_c0_index(index);
-       tlb_write_indexed();
-}
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SOC_AU1X00
-       au1x00_enet_initialize(bis);
-#endif
-       return 0;
-}
diff --git a/arch/mips/cpu/incaip_clock.c b/arch/mips/cpu/incaip_clock.c
deleted file mode 100644 (file)
index b65dfe0..0000000
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/inca-ip.h>
-
-
-/*******************************************************************************
-*
-* get_cpuclk - returns the frequency of the CPU.
-*
-* Gets the value directly from the INCA-IP hardware.
-*
-* RETURNS:
-*          150.000.000 for 150 MHz
-*          133.333.333 for 133 MHz (= 400MHz/3)
-*          100.000.000 for 100 MHz (= 400MHz/4)
-* NOTE:
-*   This functions should be used by the hardware driver to get the correct
-*   frequency of the CPU. Don't use the macros, which are set to init the CPU
-*   frequency in the ROM code.
-*/
-uint incaip_get_cpuclk (void)
-{
-       /*-------------------------------------------------------------------------*/
-       /* CPU Clock Input Multiplexer (MUX I)                                     */
-       /* Multiplexer MUX I selects the maximum input clock to the CPU.           */
-       /*-------------------------------------------------------------------------*/
-       if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
-           INCA_IP_CGU_CGU_MUXCR_MUXI) {
-               /* MUX I set to 150 MHz clock */
-               return 150000000;
-       } else {
-               /* MUX I set to 100/133 MHz clock */
-               if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
-                       /* Division value is 1/3, maximum CPU operating */
-                       /* frequency is 133.3 MHz                       */
-                       return 133333333;
-               } else {
-                       /* Division value is 1/4, maximum CPU operating */
-                       /* frequency is 100 MHz                         */
-                       return 100000000;
-               }
-       }
-}
-
-/*******************************************************************************
-*
-* get_fpiclk - returns the frequency of the FPI bus.
-*
-* Gets the value directly from the INCA-IP hardware.
-*
-* RETURNS: Frquency in Hz
-*
-* NOTE:
-*   This functions should be used by the hardware driver to get the correct
-*   frequency of the CPU. Don't use the macros, which are set to init the CPU
-*   frequency in the ROM code.
-*   The calculation for the
-*/
-uint incaip_get_fpiclk (void)
-{
-       uint clkCPU;
-
-       clkCPU = incaip_get_cpuclk ();
-
-       switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
-       case 0x4:
-               return clkCPU >> 1;     /* devided by 2 */
-               break;
-       case 0x8:
-               return clkCPU >> 2;     /* devided by 4 */
-               break;
-       default:
-               return clkCPU;
-               break;
-       }
-}
-
-int incaip_set_cpuclk (void)
-{
-       extern void ebu_init(long);
-       extern void cgu_init(long);
-       extern void sdram_init(long);
-       char tmp[64];
-       ulong cpuclk;
-
-       if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
-               cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
-               cgu_init (cpuclk);
-               ebu_init (cpuclk);
-               sdram_init (cpuclk);
-       }
-
-       return 0;
-}
diff --git a/arch/mips/cpu/incaip_wdt.S b/arch/mips/cpu/incaip_wdt.S
deleted file mode 100644 (file)
index 3ade3cd..0000000
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *  INCA-IP Watchdog timer management code.
- *
- *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <asm/regdef.h>
-
-
-#define WD_BASE            0xb8000000
-#define WD_CON0(value)     0x0020(value)
-#define WD_CON1(value)     0x0024(value)
-#define WD_DISABLE         0x00000008
-#define WD_ENABLE          0x00000000
-#define WD_WRITE_PW        0xFFFC00F8
-#define WD_WRITE_ENDINIT   0xFFFC00F3
-#define WD_WRITE_INIT      0xFFFC00F2
-
-
-       .globl  disable_incaip_wdt
-disable_incaip_wdt:
-       li      t0, WD_BASE
-
-       /* Calculate password.
-        */
-       lw      t2, WD_CON1(t0)
-       and     t2, 0xC
-
-       lw      t3, WD_CON0(t0)
-       and     t3, 0xFFFFFF01
-
-       or      t3, t2
-       or      t3, 0xF0
-
-       sw      t3, WD_CON0(t0)         /* write password */
-
-       /* Clear ENDINIT.
-        */
-       li      t1, WD_WRITE_INIT
-       sw      t1, WD_CON0(t0)
-
-
-       li      t1, WD_DISABLE
-       sw      t1, WD_CON1(t0)         /* disable watchdog */
-       li      t1, WD_WRITE_PW
-       sw      t1, WD_CON0(t0)         /* write password */
-       li      t1, WD_WRITE_ENDINIT
-       sw      t1, WD_CON0(t0)         /* end command */
-
-       jr      ra
-       nop
diff --git a/arch/mips/cpu/interrupts.c b/arch/mips/cpu/interrupts.c
deleted file mode 100644 (file)
index 87f7a9f..0000000
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-void enable_interrupts(void)
-{
-}
-
-int disable_interrupts(void)
-{
-       return 0;
-}
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile
new file mode 100644 (file)
index 0000000..e315c1b
--- /dev/null
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(CPU).o
+
+START  = start.o
+SOBJS-y        = cache.o
+COBJS-y        = cpu.o interrupts.o
+
+SRCS   := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START  := $(addprefix $(obj),$(START))
+
+all:   $(obj).depend $(START) $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile
new file mode 100644 (file)
index 0000000..dc58475
--- /dev/null
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).o
+
+COBJS  = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_eth.c b/arch/mips/cpu/mips32/au1x00/au1x00_eth.c
new file mode 100644 (file)
index 0000000..c510799
--- /dev/null
@@ -0,0 +1,311 @@
+/* Only eth0 supported for now
+ *
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+#if defined(CONFIG_SYS_DISCOVER_PHY)
+#error "PHY not supported yet"
+/* We just assume that we are running 100FD for now */
+/* We all use switches, right? ;-) */
+#endif
+
+/* I assume ethernet behaves like au1000 */
+
+#ifdef CONFIG_SOC_AU1000
+/* Base address differ between cpu:s */
+#define ETH0_BASE AU1000_ETH0_BASE
+#define MAC0_ENABLE AU1000_MAC0_ENABLE
+#else
+#ifdef CONFIG_SOC_AU1100
+#define ETH0_BASE AU1100_ETH0_BASE
+#define MAC0_ENABLE AU1100_MAC0_ENABLE
+#else
+#ifdef CONFIG_SOC_AU1500
+#define ETH0_BASE AU1500_ETH0_BASE
+#define MAC0_ENABLE AU1500_MAC0_ENABLE
+#else
+#ifdef CONFIG_SOC_AU1550
+#define ETH0_BASE AU1550_ETH0_BASE
+#define MAC0_ENABLE AU1550_MAC0_ENABLE
+#else
+#error "No valid cpu set"
+#endif
+#endif
+#endif
+#endif
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/au1x00.h>
+
+#if defined(CONFIG_CMD_MII)
+#include <miiphy.h>
+#endif
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH  1520
+#define PKT_MAXBUF_SIZE                1518
+
+static char txbuf[DBUF_LENGTH];
+
+static int next_tx;
+static int next_rx;
+
+/* 4 rx and 4 tx fifos */
+#define NO_OF_FIFOS 4
+
+typedef struct{
+       u32 status;
+       u32 addr;
+       u32 len; /* Only used for tx */
+       u32 not_used;
+} mac_fifo_t;
+
+mac_fifo_t mac_fifo[NO_OF_FIFOS];
+
+#define MAX_WAIT 1000
+
+#if defined(CONFIG_CMD_MII)
+int  au1x00_miiphy_read(const char *devname, unsigned char addr,
+               unsigned char reg, unsigned short * value)
+{
+       volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+       volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+       u32 mii_control;
+       unsigned int timedout = 20;
+
+       while (*mii_control_reg & MAC_MII_BUSY) {
+               udelay(1000);
+               if (--timedout == 0) {
+                       printf("au1x00_eth: miiphy_read busy timeout!!\n");
+                       return -1;
+               }
+       }
+
+       mii_control = MAC_SET_MII_SELECT_REG(reg) |
+               MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
+
+       *mii_control_reg = mii_control;
+
+       timedout = 20;
+       while (*mii_control_reg & MAC_MII_BUSY) {
+               udelay(1000);
+               if (--timedout == 0) {
+                       printf("au1x00_eth: miiphy_read busy timeout!!\n");
+                       return -1;
+               }
+       }
+       *value = *mii_data_reg;
+       return 0;
+}
+
+int  au1x00_miiphy_write(const char *devname, unsigned char addr,
+               unsigned char reg, unsigned short value)
+{
+       volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
+       volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
+       u32 mii_control;
+       unsigned int timedout = 20;
+
+       while (*mii_control_reg & MAC_MII_BUSY) {
+               udelay(1000);
+               if (--timedout == 0) {
+                       printf("au1x00_eth: miiphy_write busy timeout!!\n");
+                       return -1;
+               }
+       }
+
+       mii_control = MAC_SET_MII_SELECT_REG(reg) |
+               MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
+
+       *mii_data_reg = value;
+       *mii_control_reg = mii_control;
+       return 0;
+}
+#endif
+
+static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
+       volatile mac_fifo_t *fifo_tx =
+               (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+       int i;
+       int res;
+
+       /* tx fifo should always be idle */
+       fifo_tx[next_tx].len = length;
+       fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
+       au_sync();
+
+       udelay(1);
+       i=0;
+       while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
+               if(i>MAX_WAIT){
+                       printf("TX timeout\n");
+                       break;
+               }
+               udelay(1);
+               i++;
+       }
+
+       /* Clear done bit */
+       fifo_tx[next_tx].addr = 0;
+       fifo_tx[next_tx].len = 0;
+       au_sync();
+
+       res = fifo_tx[next_tx].status;
+
+       next_tx++;
+       if(next_tx>=NO_OF_FIFOS){
+               next_tx=0;
+       }
+       return(res);
+}
+
+static int au1x00_recv(struct eth_device* dev){
+       volatile mac_fifo_t *fifo_rx =
+               (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+
+       int length;
+       u32 status;
+
+       for(;;){
+               if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
+                       /* Nothing has been received */
+                       return(-1);
+               }
+
+               status = fifo_rx[next_rx].status;
+
+               length = status&0x3FFF;
+
+               if(status&RX_ERROR){
+                       printf("Rx error 0x%x\n", status);
+               }
+               else{
+                       /* Pass the packet up to the protocol layers. */
+                       NetReceive(NetRxPackets[next_rx], length - 4);
+               }
+
+               fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
+
+               next_rx++;
+               if(next_rx>=NO_OF_FIFOS){
+                       next_rx=0;
+               }
+       } /* for */
+
+       return(0); /* Does anyone use this? */
+}
+
+static int au1x00_init(struct eth_device* dev, bd_t * bd){
+
+       volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
+       volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
+       volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
+       volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
+       volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
+       volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
+       volatile mac_fifo_t *fifo_tx =
+               (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+       volatile mac_fifo_t *fifo_rx =
+               (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+       int i;
+
+       next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
+       next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
+
+       /* We have to enable clocks before releasing reset */
+       *macen = MAC_EN_CLOCK_ENABLE;
+       udelay(10);
+
+       /* Enable MAC0 */
+       /* We have to release reset before accessing registers */
+       *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
+               MAC_EN_RESET1|MAC_EN_RESET2;
+       udelay(10);
+
+       for(i=0;i<NO_OF_FIFOS;i++){
+               fifo_tx[i].len = 0;
+               fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
+               fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
+       }
+
+       /* Put mac addr in little endian */
+#define ea eth_get_dev()->enetaddr
+       *mac_addr_high  =       (ea[5] <<  8) | (ea[4]      ) ;
+       *mac_addr_low   =       (ea[3] << 24) | (ea[2] << 16) |
+               (ea[1] <<  8) | (ea[0]      ) ;
+#undef ea
+       *mac_mcast_low = 0;
+       *mac_mcast_high = 0;
+
+       /* Make sure the MAC buffer is in the correct endian mode */
+#ifdef __LITTLE_ENDIAN
+       *mac_ctrl = MAC_FULL_DUPLEX;
+       udelay(1);
+       *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#else
+       *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
+       udelay(1);
+       *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+#endif
+
+       return(1);
+}
+
+static void au1x00_halt(struct eth_device* dev){
+       volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
+
+       /* Put MAC0 in reset */
+       *macen = 0;
+}
+
+int au1x00_enet_initialize(bd_t *bis){
+       struct eth_device* dev;
+
+       if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
+               puts ("malloc failed\n");
+               return -1;
+       }
+
+       memset(dev, 0, sizeof *dev);
+
+       sprintf(dev->name, "Au1X00 ethernet");
+       dev->iobase = 0;
+       dev->priv   = 0;
+       dev->init   = au1x00_init;
+       dev->halt   = au1x00_halt;
+       dev->send   = au1x00_send;
+       dev->recv   = au1x00_recv;
+
+       eth_register(dev);
+
+#if defined(CONFIG_CMD_MII)
+       miiphy_register(dev->name,
+               au1x00_miiphy_read, au1x00_miiphy_write);
+#endif
+
+       return 1;
+}
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
new file mode 100644 (file)
index 0000000..c25ba5a
--- /dev/null
@@ -0,0 +1,131 @@
+/*
+ * AU1X00 UART support
+ *
+ * Hardcoded to UART 0 for now
+ * Speed and options also hardcoded to 115200 8N1
+ *
+ *  Copyright (c) 2003 Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/au1x00.h>
+
+/******************************************************************************
+*
+* serial_init - initialize a channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+       volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
+       volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
+
+       /* Enable clocks first */
+       *uart_enable = UART_EN_CE;
+
+       /* Then release reset */
+       /* Must release reset before setting other regs */
+       *uart_enable = UART_EN_CE|UART_EN_E;
+
+       /* Activate fifos, reset tx and rx */
+       /* Set tx trigger level to 12 */
+       *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
+               UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
+
+       serial_setbrg();
+
+       return 0;
+}
+
+
+void serial_setbrg (void)
+{
+       volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
+       volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
+       volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
+       int sd;
+       int divisorx2;
+
+       /* sd is system clock divisor                   */
+       /* see section 10.4.5 in au1550 datasheet       */
+       sd = (*sys_powerctrl & 0x03) + 2;
+
+       /* calulate 2x baudrate and round */
+       divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
+
+       if (divisorx2 & 0x01)
+               divisorx2 = divisorx2 + 1;
+
+       *uart_clk = divisorx2 / 2;
+
+       /* Set parity, stop bits and word length to 8N1 */
+       *uart_lcr = UART_LCR_WLEN8;
+}
+
+void serial_putc (const char c)
+{
+       volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+       volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
+
+       if (c == '\n') serial_putc ('\r');
+
+       /* Wait for fifo to shift out some bytes */
+       while((*uart_lsr&UART_LSR_THRE)==0);
+
+       *uart_tx = (u32)c;
+}
+
+void serial_puts (const char *s)
+{
+       while (*s)
+       {
+               serial_putc (*s++);
+       }
+}
+
+int serial_getc (void)
+{
+       volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
+       char c;
+
+       while (!serial_tstc());
+
+       c = (*uart_rx&0xFF);
+       return c;
+}
+
+int serial_tstc (void)
+{
+       volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+
+       if(*uart_lsr&UART_LSR_DR){
+               /* Data in rfifo */
+               return(1);
+       }
+       return 0;
+}
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c
new file mode 100644 (file)
index 0000000..0bc2305
--- /dev/null
@@ -0,0 +1,1726 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+/*
+ * IMPORTANT NOTES
+ * 1 - this driver is intended for use with USB Mass Storage Devices
+ *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_USB_OHCI
+
+/* #include <pci.h> no PCI on the AU1x00 */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/au1x00.h>
+#include <usb.h>
+#include "au1x00_usb_ohci.h"
+
+#define OHCI_USE_NPS           /* force NoPowerSwitching mode */
+#define OHCI_VERBOSE_DEBUG     /* not always helpful */
+#define OHCI_FILL_TRACE
+
+#define USBH_ENABLE_BE (1<<0)
+#define USBH_ENABLE_C  (1<<1)
+#define USBH_ENABLE_E  (1<<2)
+#define USBH_ENABLE_CE (1<<3)
+#define USBH_ENABLE_RD (1<<4)
+
+#ifdef __LITTLE_ENDIAN
+#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
+#else
+#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
+#endif
+
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+       (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+#undef readl
+#undef writel
+
+#define readl(a)     au_readl((long)(a))
+#define writel(v,a)  au_writel((v),(int)(a))
+
+#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+#define DEBUG
+#ifdef DEBUG
+#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
+#else
+#define dbg(format, arg...) do {} while(0)
+#endif /* DEBUG */
+#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
+#define SHOW_INFO
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\n", ## arg)
+#else
+#define info(format, arg...) do {} while(0)
+#endif
+
+#define m16_swap(x) swap_16(x)
+#define m32_swap(x) swap_32(x)
+
+/* global ohci_t */
+static ohci_t gohci;
+/* this must be aligned to a 256 byte boundary */
+struct ohci_hcca ghcca[1];
+/* a pointer to the aligned storage */
+struct ohci_hcca *phcca;
+/* this allocates EDs for all possible endpoints */
+struct ohci_device ohci_dev;
+/* urb_priv */
+urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;
+
+/*-------------------------------------------------------------------------*/
+
+/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
+ * The erratum (#4) description is incorrect.  AMD's workaround waits
+ * till some bits (mostly reserved) are clear; ok for all revs.
+ */
+#define OHCI_QUIRK_AMD756 0xabcd
+#define read_roothub(hc, register, mask) ({ \
+       u32 temp = readl (&hc->regs->roothub.register); \
+       if (hc->flags & OHCI_QUIRK_AMD756) \
+               while (temp & mask) \
+                       temp = readl (&hc->regs->roothub.register); \
+       temp; })
+
+static u32 roothub_a (struct ohci *hc)
+       { return read_roothub (hc, a, 0xfc0fe000); }
+static inline u32 roothub_b (struct ohci *hc)
+       { return readl (&hc->regs->roothub.b); }
+static inline u32 roothub_status (struct ohci *hc)
+       { return readl (&hc->regs->roothub.status); }
+static u32 roothub_portstatus (struct ohci *hc, int i)
+       { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
+
+
+/* forward declaration */
+static int hc_interrupt (void);
+static void
+td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
+       int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv (urb_priv_t * urb)
+{
+       int             i;
+       int             last;
+       struct td       * td;
+
+       last = urb->length - 1;
+       if (last >= 0) {
+               for (i = 0; i <= last; i++) {
+                       td = urb->td[i];
+                       if (td) {
+                               td->usb_dev = NULL;
+                               urb->td[i] = NULL;
+                       }
+               }
+       }
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+static int sohci_get_current_frame_number (struct usb_device * dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
+       int transfer_len, struct devrequest * setup, char * str, int small)
+{
+       urb_priv_t * purb = &urb_priv;
+
+       dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
+                       str,
+                       sohci_get_current_frame_number (dev),
+                       usb_pipedevice (pipe),
+                       usb_pipeendpoint (pipe),
+                       usb_pipeout (pipe)? 'O': 'I',
+                       usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+                               (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+                       purb->actual_length,
+                       transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+       if (!small) {
+               int i, len;
+
+               if (usb_pipecontrol (pipe)) {
+                       printf (__FILE__ ": cmd(8):");
+                       for (i = 0; i < 8 ; i++)
+                               printf (" %02x", ((__u8 *) setup) [i]);
+                       printf ("\n");
+               }
+               if (transfer_len > 0 && buffer) {
+                       printf (__FILE__ ": data(%d/%d):",
+                               purb->actual_length,
+                               transfer_len);
+                       len = usb_pipeout (pipe)?
+                                       transfer_len: purb->actual_length;
+                       for (i = 0; i < 16 && i < len; i++)
+                               printf (" %02x", ((__u8 *) buffer) [i]);
+                       printf ("%s\n", i < len? "...": "");
+               }
+       }
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
+void ep_print_int_eds (ohci_t *ohci, char * str) {
+       int i, j;
+        __u32 * ed_p;
+       for (i= 0; i < 32; i++) {
+               j = 5;
+               ed_p = &(ohci->hcca->int_table [i]);
+               if (*ed_p == 0)
+                   continue;
+               printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+               while (*ed_p != 0 && j--) {
+                       ed_t *ed = (ed_t *)m32_swap(ed_p);
+                       printf (" ed: %4x;", ed->hwINFO);
+                       ed_p = &ed->hwNextED;
+               }
+               printf ("\n");
+       }
+}
+
+static void ohci_dump_intr_mask (char *label, __u32 mask)
+{
+       dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+               label,
+               mask,
+               (mask & OHCI_INTR_MIE) ? " MIE" : "",
+               (mask & OHCI_INTR_OC) ? " OC" : "",
+               (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+               (mask & OHCI_INTR_FNO) ? " FNO" : "",
+               (mask & OHCI_INTR_UE) ? " UE" : "",
+               (mask & OHCI_INTR_RD) ? " RD" : "",
+               (mask & OHCI_INTR_SF) ? " SF" : "",
+               (mask & OHCI_INTR_WDH) ? " WDH" : "",
+               (mask & OHCI_INTR_SO) ? " SO" : ""
+               );
+}
+
+static void maybe_print_eds (char *label, __u32 value)
+{
+       ed_t *edp = (ed_t *)value;
+
+       if (value) {
+               dbg ("%s %08x", label, value);
+               dbg ("%08x", edp->hwINFO);
+               dbg ("%08x", edp->hwTailP);
+               dbg ("%08x", edp->hwHeadP);
+               dbg ("%08x", edp->hwNextED);
+       }
+}
+
+static char * hcfs2string (int state)
+{
+       switch (state) {
+               case OHCI_USB_RESET:    return "reset";
+               case OHCI_USB_RESUME:   return "resume";
+               case OHCI_USB_OPER:     return "operational";
+               case OHCI_USB_SUSPEND:  return "suspend";
+       }
+       return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status (ohci_t *controller)
+{
+       struct ohci_regs        *regs = controller->regs;
+       __u32                   temp;
+
+       temp = readl (&regs->revision) & 0xff;
+       if (temp != 0x10)
+               dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+       temp = readl (&regs->control);
+       dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+               (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+               (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+               (temp & OHCI_CTRL_IR) ? " IR" : "",
+               hcfs2string (temp & OHCI_CTRL_HCFS),
+               (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+               (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+               (temp & OHCI_CTRL_IE) ? " IE" : "",
+               (temp & OHCI_CTRL_PLE) ? " PLE" : "",
+               temp & OHCI_CTRL_CBSR
+               );
+
+       temp = readl (&regs->cmdstatus);
+       dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+               (temp & OHCI_SOC) >> 16,
+               (temp & OHCI_OCR) ? " OCR" : "",
+               (temp & OHCI_BLF) ? " BLF" : "",
+               (temp & OHCI_CLF) ? " CLF" : "",
+               (temp & OHCI_HCR) ? " HCR" : ""
+               );
+
+       ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
+       ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
+
+       maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
+
+       maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
+       maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
+
+       maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
+       maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
+
+       maybe_print_eds ("donehead", readl (&regs->donehead));
+}
+
+static void ohci_dump_roothub (ohci_t *controller, int verbose)
+{
+       __u32                   temp, ndp, i;
+
+       temp = roothub_a (controller);
+       ndp = (temp & RH_A_NDP);
+
+       if (verbose) {
+               dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+                       ((temp & RH_A_POTPGT) >> 24) & 0xff,
+                       (temp & RH_A_NOCP) ? " NOCP" : "",
+                       (temp & RH_A_OCPM) ? " OCPM" : "",
+                       (temp & RH_A_DT) ? " DT" : "",
+                       (temp & RH_A_NPS) ? " NPS" : "",
+                       (temp & RH_A_PSM) ? " PSM" : "",
+                       ndp
+                       );
+               temp = roothub_b (controller);
+               dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
+                       temp,
+                       (temp & RH_B_PPCM) >> 16,
+                       (temp & RH_B_DR)
+                       );
+               temp = roothub_status (controller);
+               dbg ("roothub.status: %08x%s%s%s%s%s%s",
+                       temp,
+                       (temp & RH_HS_CRWE) ? " CRWE" : "",
+                       (temp & RH_HS_OCIC) ? " OCIC" : "",
+                       (temp & RH_HS_LPSC) ? " LPSC" : "",
+                       (temp & RH_HS_DRWE) ? " DRWE" : "",
+                       (temp & RH_HS_OCI) ? " OCI" : "",
+                       (temp & RH_HS_LPS) ? " LPS" : ""
+                       );
+       }
+
+       for (i = 0; i < ndp; i++) {
+               temp = roothub_portstatus (controller, i);
+               dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+                       i,
+                       temp,
+                       (temp & RH_PS_PRSC) ? " PRSC" : "",
+                       (temp & RH_PS_OCIC) ? " OCIC" : "",
+                       (temp & RH_PS_PSSC) ? " PSSC" : "",
+                       (temp & RH_PS_PESC) ? " PESC" : "",
+                       (temp & RH_PS_CSC) ? " CSC" : "",
+
+                       (temp & RH_PS_LSDA) ? " LSDA" : "",
+                       (temp & RH_PS_PPS) ? " PPS" : "",
+                       (temp & RH_PS_PRS) ? " PRS" : "",
+                       (temp & RH_PS_POCI) ? " POCI" : "",
+                       (temp & RH_PS_PSS) ? " PSS" : "",
+
+                       (temp & RH_PS_PES) ? " PES" : "",
+                       (temp & RH_PS_CCS) ? " CCS" : ""
+                       );
+       }
+}
+
+static void ohci_dump (ohci_t *controller, int verbose)
+{
+       dbg ("OHCI controller usb-%s state", controller->slot_name);
+
+       /* dumps some of the state we know about */
+       ohci_dump_status (controller);
+       if (verbose)
+               ep_print_int_eds (controller, "hcca");
+       dbg ("hcca frame #%04x", controller->hcca->frame_no);
+       ohci_dump_roothub (controller, 1);
+}
+
+
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
+               int transfer_len, struct devrequest *setup, int interval)
+{
+       ohci_t *ohci;
+       ed_t * ed;
+       urb_priv_t *purb_priv;
+       int i, size = 0;
+
+       ohci = &gohci;
+
+       /* when controller's hung, permit only roothub cleanup attempts
+        * such as powering down ports */
+       if (ohci->disabled) {
+               err("sohci_submit_job: EPIPE");
+               return -1;
+       }
+
+       /* every endpoint has a ed, locate and fill it */
+       if (!(ed = ep_add_ed (dev, pipe))) {
+               err("sohci_submit_job: ENOMEM");
+               return -1;
+       }
+
+       /* for the private part of the URB we need the number of TDs (size) */
+       switch (usb_pipetype (pipe)) {
+               case PIPE_BULK: /* one TD for every 4096 Byte */
+                       size = (transfer_len - 1) / 4096 + 1;
+                       break;
+               case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+                       size = (transfer_len == 0)? 2:
+                                               (transfer_len - 1) / 4096 + 3;
+                       break;
+       }
+
+       if (size >= (N_URB_TD - 1)) {
+               err("need %d TDs, only have %d", size, N_URB_TD);
+               return -1;
+       }
+       purb_priv = &urb_priv;
+       purb_priv->pipe = pipe;
+
+       /* fill the private part of the URB */
+       purb_priv->length = size;
+       purb_priv->ed = ed;
+       purb_priv->actual_length = 0;
+
+       /* allocate the TDs */
+       /* note that td[0] was allocated in ep_add_ed */
+       for (i = 0; i < size; i++) {
+               purb_priv->td[i] = td_alloc (dev);
+               if (!purb_priv->td[i]) {
+                       purb_priv->length = i;
+                       urb_free_priv (purb_priv);
+                       err("sohci_submit_job: ENOMEM");
+                       return -1;
+               }
+       }
+
+       if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
+               urb_free_priv (purb_priv);
+               err("sohci_submit_job: EINVAL");
+               return -1;
+       }
+
+       /* link the ed into a chain if is not already */
+       if (ed->state != ED_OPER)
+               ep_link (ohci, ed);
+
+       /* fill the TDs and link it to the ed */
+       td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+
+       return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef DEBUG
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+{
+       ohci_t *ohci = &gohci;
+
+       return m16_swap (ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link (ohci_t *ohci, ed_t *edi)
+{
+       volatile ed_t *ed = edi;
+
+       ed->state = ED_OPER;
+
+       switch (ed->type) {
+       case PIPE_CONTROL:
+               ed->hwNextED = 0;
+               if (ohci->ed_controltail == NULL) {
+                       writel ((long)ed, &ohci->regs->ed_controlhead);
+               } else {
+                       ohci->ed_controltail->hwNextED = m32_swap (ed);
+               }
+               ed->ed_prev = ohci->ed_controltail;
+               if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
+                       !ohci->ed_rm_list[1] && !ohci->sleeping) {
+                       ohci->hc_control |= OHCI_CTRL_CLE;
+                       writel (ohci->hc_control, &ohci->regs->control);
+               }
+               ohci->ed_controltail = edi;
+               break;
+
+       case PIPE_BULK:
+               ed->hwNextED = 0;
+               if (ohci->ed_bulktail == NULL) {
+                       writel ((long)ed, &ohci->regs->ed_bulkhead);
+               } else {
+                       ohci->ed_bulktail->hwNextED = m32_swap (ed);
+               }
+               ed->ed_prev = ohci->ed_bulktail;
+               if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
+                       !ohci->ed_rm_list[1] && !ohci->sleeping) {
+                       ohci->hc_control |= OHCI_CTRL_BLE;
+                       writel (ohci->hc_control, &ohci->regs->control);
+               }
+               ohci->ed_bulktail = edi;
+               break;
+       }
+       return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink (ohci_t *ohci, ed_t *ed)
+{
+       ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+
+       switch (ed->type) {
+       case PIPE_CONTROL:
+               if (ed->ed_prev == NULL) {
+                       if (!ed->hwNextED) {
+                               ohci->hc_control &= ~OHCI_CTRL_CLE;
+                               writel (ohci->hc_control, &ohci->regs->control);
+                       }
+                       writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+               } else {
+                       ed->ed_prev->hwNextED = ed->hwNextED;
+               }
+               if (ohci->ed_controltail == ed) {
+                       ohci->ed_controltail = ed->ed_prev;
+               } else {
+                       ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+               }
+               break;
+
+       case PIPE_BULK:
+               if (ed->ed_prev == NULL) {
+                       if (!ed->hwNextED) {
+                               ohci->hc_control &= ~OHCI_CTRL_BLE;
+                               writel (ohci->hc_control, &ohci->regs->control);
+                       }
+                       writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+               } else {
+                       ed->ed_prev->hwNextED = ed->hwNextED;
+               }
+               if (ohci->ed_bulktail == ed) {
+                       ohci->ed_bulktail = ed->ed_prev;
+               } else {
+                       ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+               }
+               break;
+       }
+       ed->state = ED_UNLINK;
+       return 0;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
+ * but the USB stack is a little bit stateless so we do it at every transaction
+ * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
+ * in all other cases the state is left unchanged
+ * the ed info fields are setted anyway even though most of them should not change */
+
+static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+{
+       td_t *td;
+       ed_t *ed_ret;
+       volatile ed_t *ed;
+
+       ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
+                       (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+
+       if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
+               err("ep_add_ed: pending delete");
+               /* pending delete request */
+               return NULL;
+       }
+
+       if (ed->state == ED_NEW) {
+               ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+               /* dummy td; end of td list for ed */
+               td = td_alloc (usb_dev);
+               ed->hwTailP = m32_swap (td);
+               ed->hwHeadP = ed->hwTailP;
+               ed->state = ED_UNLINK;
+               ed->type = usb_pipetype (pipe);
+               ohci_dev.ed_cnt++;
+       }
+
+       ed->hwINFO = m32_swap (usb_pipedevice (pipe)
+                       | usb_pipeendpoint (pipe) << 7
+                       | (usb_pipeisoc (pipe)? 0x8000: 0)
+                       | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
+                       | usb_pipeslow (pipe) << 13
+                       | usb_maxpacket (usb_dev, pipe) << 16);
+
+       return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill (ohci_t *ohci, unsigned int info,
+       void *data, int len,
+       struct usb_device *dev, int index, urb_priv_t *urb_priv)
+{
+       volatile td_t  *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+       int i;
+#endif
+
+       if (index > urb_priv->length) {
+               err("index > length");
+               return;
+       }
+       /* use this td as the next dummy */
+       td_pt = urb_priv->td [index];
+       td_pt->hwNextTD = 0;
+
+       /* fill the old dummy TD */
+       td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+
+       td->ed = urb_priv->ed;
+       td->next_dl_td = NULL;
+       td->index = index;
+       td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+       if (1 || (usb_pipebulk(urb_priv->pipe) &&
+                               usb_pipeout(urb_priv->pipe))) {
+               for (i = 0; i < len; i++)
+               printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
+       }
+#endif
+       if (!len)
+               data = 0;
+
+       td->hwINFO = m32_swap (info);
+       td->hwCBP = m32_swap (data);
+       if (data)
+               td->hwBE = m32_swap (data + len - 1);
+       else
+               td->hwBE = 0;
+       td->hwNextTD = m32_swap (td_pt);
+       td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
+
+       /* append to queue */
+       td->ed->hwTailP = td->hwNextTD;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+#define kseg_to_phys(x)          ((void *)((__u32)(x) - 0x80000000))
+
+static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
+       int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+       ohci_t *ohci = &gohci;
+       int data_len = transfer_len;
+       void *data;
+       int cnt = 0;
+       __u32 info = 0;
+       unsigned int toggle = 0;
+
+       /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
+       if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+               toggle = TD_T_TOGGLE;
+       } else {
+               toggle = TD_T_DATA0;
+               usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+       }
+       urb->td_cnt = 0;
+       if (data_len)
+               data = kseg_to_phys(buffer);
+       else
+               data = 0;
+
+       switch (usb_pipetype (pipe)) {
+       case PIPE_BULK:
+               info = usb_pipeout (pipe)?
+                       TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+               while(data_len > 4096) {
+                       td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
+                       data += 4096; data_len -= 4096; cnt++;
+               }
+               info = usb_pipeout (pipe)?
+                       TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+               td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+               cnt++;
+
+               if (!ohci->sleeping)
+                       writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+               break;
+
+       case PIPE_CONTROL:
+               info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+               td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
+               if (data_len > 0) {
+                       info = usb_pipeout (pipe)?
+                               TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+                       /* NOTE:  mishandles transfers >8K, some >4K */
+                       td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+               }
+               info = usb_pipeout (pipe)?
+                       TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
+               td_fill (ohci, info, data, 0, dev, cnt++, urb);
+               if (!ohci->sleeping)
+                       writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+               break;
+       }
+       if (urb->length != cnt)
+               dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t * td)
+{
+       __u32 tdINFO, tdBE, tdCBP;
+       urb_priv_t *lurb_priv = &urb_priv;
+
+       tdINFO = m32_swap (td->hwINFO);
+       tdBE   = m32_swap (td->hwBE);
+       tdCBP  = m32_swap (td->hwCBP);
+
+
+       if (!(usb_pipecontrol(lurb_priv->pipe) &&
+           ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+               if (tdBE != 0) {
+                       if (td->hwCBP == 0)
+                               lurb_priv->actual_length += tdBE - td->data + 1;
+                       else
+                               lurb_priv->actual_length += tdCBP - td->data;
+               }
+       }
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+
+static td_t * dl_reverse_done_list (ohci_t *ohci)
+{
+       __u32 td_list_hc;
+       td_t *td_rev = NULL;
+       td_t *td_list = NULL;
+       urb_priv_t *lurb_priv = NULL;
+
+       td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+       ohci->hcca->done_head = 0;
+
+       while (td_list_hc) {
+               td_list = (td_t *)td_list_hc;
+
+               if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+                       lurb_priv = &urb_priv;
+                       dbg(" USB-error/status: %x : %p",
+                                       TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
+                       if (td_list->ed->hwHeadP & m32_swap (0x1)) {
+                               if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+                                       td_list->ed->hwHeadP =
+                                               (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
+                                                                       (td_list->ed->hwHeadP & m32_swap (0x2));
+                                       lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+                               } else
+                                       td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+                       }
+               }
+
+               td_list->next_dl_td = td_rev;
+               td_rev = td_list;
+               td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+       }
+       return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* td done list */
+static int dl_done_list (ohci_t *ohci, td_t *td_list)
+{
+       td_t *td_list_next = NULL;
+       ed_t *ed;
+       int cc = 0;
+       int stat = 0;
+       /* urb_t *urb; */
+       urb_priv_t *lurb_priv;
+       __u32 tdINFO, edHeadP, edTailP;
+
+       while (td_list) {
+               td_list_next = td_list->next_dl_td;
+
+               lurb_priv = &urb_priv;
+               tdINFO = m32_swap (td_list->hwINFO);
+
+               ed = td_list->ed;
+
+               dl_transfer_length(td_list);
+
+               /* error code of transfer */
+               cc = TD_CC_GET (tdINFO);
+               if (cc != 0) {
+                       dbg("ConditionCode %#x", cc);
+                       stat = cc_to_error[cc];
+               }
+
+               if (ed->state != ED_NEW) {
+                       edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+                       edTailP = m32_swap (ed->hwTailP);
+
+                       /* unlink eds if they are not busy */
+                       if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+                               ep_unlink (ohci, ed);
+               }
+
+               td_list = td_list_next;
+       }
+       return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+       0x12,       /*  __u8  bLength; */
+       0x01,       /*  __u8  bDescriptorType; Device */
+       0x10,       /*  __u16 bcdUSB; v1.1 */
+       0x01,
+       0x09,       /*  __u8  bDeviceClass; HUB_CLASSCODE */
+       0x00,       /*  __u8  bDeviceSubClass; */
+       0x00,       /*  __u8  bDeviceProtocol; */
+       0x08,       /*  __u8  bMaxPacketSize0; 8 Bytes */
+       0x00,       /*  __u16 idVendor; */
+       0x00,
+       0x00,       /*  __u16 idProduct; */
+       0x00,
+       0x00,       /*  __u16 bcdDevice; */
+       0x00,
+       0x00,       /*  __u8  iManufacturer; */
+       0x01,       /*  __u8  iProduct; */
+       0x00,       /*  __u8  iSerialNumber; */
+       0x01        /*  __u8  bNumConfigurations; */
+};
+
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+       0x09,       /*  __u8  bLength; */
+       0x02,       /*  __u8  bDescriptorType; Configuration */
+       0x19,       /*  __u16 wTotalLength; */
+       0x00,
+       0x01,       /*  __u8  bNumInterfaces; */
+       0x01,       /*  __u8  bConfigurationValue; */
+       0x00,       /*  __u8  iConfiguration; */
+       0x40,       /*  __u8  bmAttributes;
+                Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+       0x00,       /*  __u8  MaxPower; */
+
+       /* interface */
+       0x09,       /*  __u8  if_bLength; */
+       0x04,       /*  __u8  if_bDescriptorType; Interface */
+       0x00,       /*  __u8  if_bInterfaceNumber; */
+       0x00,       /*  __u8  if_bAlternateSetting; */
+       0x01,       /*  __u8  if_bNumEndpoints; */
+       0x09,       /*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+       0x00,       /*  __u8  if_bInterfaceSubClass; */
+       0x00,       /*  __u8  if_bInterfaceProtocol; */
+       0x00,       /*  __u8  if_iInterface; */
+
+       /* endpoint */
+       0x07,       /*  __u8  ep_bLength; */
+       0x05,       /*  __u8  ep_bDescriptorType; Endpoint */
+       0x81,       /*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+       0x03,       /*  __u8  ep_bmAttributes; Interrupt */
+       0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+       0x00,
+       0xff        /*  __u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+       0x04,                   /*  __u8  bLength; */
+       0x03,                   /*  __u8  bDescriptorType; String-descriptor */
+       0x09,                   /*  __u8  lang ID */
+       0x04,                   /*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+       28,                     /*  __u8  bLength; */
+       0x03,                   /*  __u8  bDescriptorType; String-descriptor */
+       'O',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'H',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'C',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'I',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       ' ',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'R',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'o',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'o',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       't',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       ' ',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'H',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'u',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+       'b',                    /*  __u8  Unicode */
+       0,                              /*  __u8  Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x)                  len = (x); break
+#ifdef DEBUG
+#define WR_RH_STAT(x)          {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
+#define WR_RH_PORTSTAT(x)      {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#else
+#define WR_RH_STAT(x)          writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)      writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT             roothub_status(&gohci)
+#define RD_RH_PORTSTAT         roothub_portstatus(&gohci,wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+       __u32 temp, ndp, i;
+       int res;
+
+       res = -1;
+       temp = roothub_a (controller);
+       ndp = (temp & RH_A_NDP);
+       for (i = 0; i < ndp; i++) {
+               temp = roothub_portstatus (controller, i);
+               /* check for a device disconnect */
+               if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+                       (RH_PS_PESC | RH_PS_CSC)) &&
+                       ((temp & RH_PS_CCS) == 0)) {
+                       res = i;
+                       break;
+               }
+       }
+       return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+               void *buffer, int transfer_len, struct devrequest *cmd)
+{
+       void * data = buffer;
+       int leni = transfer_len;
+       int len = 0;
+       int stat = 0;
+       __u32 datab[4];
+       __u8 *data_buf = (__u8 *)datab;
+       __u16 bmRType_bReq;
+       __u16 wValue;
+       __u16 wIndex;
+       __u16 wLength;
+
+#ifdef DEBUG
+urb_priv.actual_length = 0;
+pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+       wait_ms(1);
+#endif
+       if (usb_pipeint(pipe)) {
+               info("Root-Hub submit IRQ: NOT implemented");
+               return 0;
+       }
+
+       bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
+       wValue        = m16_swap (cmd->value);
+       wIndex        = m16_swap (cmd->index);
+       wLength       = m16_swap (cmd->length);
+
+       info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+               dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+
+       switch (bmRType_bReq) {
+       /* Request Destination:
+          without flags: Device,
+          RH_INTERFACE: interface,
+          RH_ENDPOINT: endpoint,
+          RH_CLASS means HUB here,
+          RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
+       */
+
+       case RH_GET_STATUS:
+                       *(__u16 *) data_buf = m16_swap (1); OK (2);
+       case RH_GET_STATUS | RH_INTERFACE:
+                       *(__u16 *) data_buf = m16_swap (0); OK (2);
+       case RH_GET_STATUS | RH_ENDPOINT:
+                       *(__u16 *) data_buf = m16_swap (0); OK (2);
+       case RH_GET_STATUS | RH_CLASS:
+                       *(__u32 *) data_buf = m32_swap (
+                               RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+                       OK (4);
+       case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+                       *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+
+       case RH_CLEAR_FEATURE | RH_ENDPOINT:
+               switch (wValue) {
+                       case (RH_ENDPOINT_STALL): OK (0);
+               }
+               break;
+
+       case RH_CLEAR_FEATURE | RH_CLASS:
+               switch (wValue) {
+                       case RH_C_HUB_LOCAL_POWER:
+                               OK(0);
+                       case (RH_C_HUB_OVER_CURRENT):
+                                       WR_RH_STAT(RH_HS_OCIC); OK (0);
+               }
+               break;
+
+       case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+               switch (wValue) {
+                       case (RH_PORT_ENABLE):
+                                       WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
+                       case (RH_PORT_SUSPEND):
+                                       WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
+                       case (RH_PORT_POWER):
+                                       WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
+                       case (RH_C_PORT_CONNECTION):
+                                       WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
+                       case (RH_C_PORT_ENABLE):
+                                       WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
+                       case (RH_C_PORT_SUSPEND):
+                                       WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
+                       case (RH_C_PORT_OVER_CURRENT):
+                                       WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
+                       case (RH_C_PORT_RESET):
+                                       WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+               }
+               break;
+
+       case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+               switch (wValue) {
+                       case (RH_PORT_SUSPEND):
+                                       WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
+                       case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+                                       if (RD_RH_PORTSTAT & RH_PS_CCS)
+                                           WR_RH_PORTSTAT (RH_PS_PRS);
+                                       OK (0);
+                       case (RH_PORT_POWER):
+                                       WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
+                       case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+                                       if (RD_RH_PORTSTAT & RH_PS_CCS)
+                                           WR_RH_PORTSTAT (RH_PS_PES );
+                                       OK (0);
+               }
+               break;
+
+       case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+
+       case RH_GET_DESCRIPTOR:
+               switch ((wValue & 0xff00) >> 8) {
+                       case (0x01): /* device descriptor */
+                               len = min_t(unsigned int,
+                                         leni,
+                                         min_t(unsigned int,
+                                             sizeof (root_hub_dev_des),
+                                             wLength));
+                               data_buf = root_hub_dev_des; OK(len);
+                       case (0x02): /* configuration descriptor */
+                               len = min_t(unsigned int,
+                                         leni,
+                                         min_t(unsigned int,
+                                             sizeof (root_hub_config_des),
+                                             wLength));
+                               data_buf = root_hub_config_des; OK(len);
+                       case (0x03): /* string descriptors */
+                               if(wValue==0x0300) {
+                                       len = min_t(unsigned int,
+                                                 leni,
+                                                 min_t(unsigned int,
+                                                     sizeof (root_hub_str_index0),
+                                                     wLength));
+                                       data_buf = root_hub_str_index0;
+                                       OK(len);
+                               }
+                               if(wValue==0x0301) {
+                                       len = min_t(unsigned int,
+                                                 leni,
+                                                 min_t(unsigned int,
+                                                     sizeof (root_hub_str_index1),
+                                                     wLength));
+                                       data_buf = root_hub_str_index1;
+                                       OK(len);
+                       }
+                       default:
+                               stat = USB_ST_STALLED;
+               }
+               break;
+
+       case RH_GET_DESCRIPTOR | RH_CLASS:
+           {
+                   __u32 temp = roothub_a (&gohci);
+
+                   data_buf [0] = 9;           /* min length; */
+                   data_buf [1] = 0x29;
+                   data_buf [2] = temp & RH_A_NDP;
+                   data_buf [3] = 0;
+                   if (temp & RH_A_PSM)        /* per-port power switching? */
+                       data_buf [3] |= 0x1;
+                   if (temp & RH_A_NOCP)       /* no overcurrent reporting? */
+                       data_buf [3] |= 0x10;
+                   else if (temp & RH_A_OCPM)  /* per-port overcurrent reporting? */
+                       data_buf [3] |= 0x8;
+
+                   /* corresponds to data_buf[4-7] */
+                   datab [1] = 0;
+                   data_buf [5] = (temp & RH_A_POTPGT) >> 24;
+                   temp = roothub_b (&gohci);
+                   data_buf [7] = temp & RH_B_DR;
+                   if (data_buf [2] < 7) {
+                       data_buf [8] = 0xff;
+                   } else {
+                       data_buf [0] += 2;
+                       data_buf [8] = (temp & RH_B_DR) >> 8;
+                       data_buf [10] = data_buf [9] = 0xff;
+                   }
+
+                   len = min_t(unsigned int, leni,
+                             min_t(unsigned int, data_buf [0], wLength));
+                   OK (len);
+               }
+
+       case RH_GET_CONFIGURATION:      *(__u8 *) data_buf = 0x01; OK (1);
+
+       case RH_SET_CONFIGURATION:      WR_RH_STAT (0x10000); OK (0);
+
+       default:
+               dbg ("unsupported root hub command");
+               stat = USB_ST_STALLED;
+       }
+
+#ifdef DEBUG
+       ohci_dump_roothub (&gohci, 1);
+#else
+       wait_ms(1);
+#endif
+
+       len = min_t(int, len, leni);
+       if (data != data_buf)
+           memcpy (data, data_buf, len);
+       dev->act_len = len;
+       dev->status = stat;
+
+#ifdef DEBUG
+       if (transfer_len)
+               urb_priv.actual_length = transfer_len;
+       pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+       wait_ms(1);
+#endif
+
+       return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub */
+/* accesses. */
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+               int transfer_len, struct devrequest *setup, int interval)
+{
+       int stat = 0;
+       int maxsize = usb_maxpacket(dev, pipe);
+       int timeout;
+
+       /* device pulled? Shortcut the action. */
+       if (devgone == dev) {
+               dev->status = USB_ST_CRC_ERR;
+               return 0;
+       }
+
+#ifdef DEBUG
+       urb_priv.actual_length = 0;
+       pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+       wait_ms(1);
+#endif
+       if (!maxsize) {
+               err("submit_common_message: pipesize for pipe %lx is zero",
+                       pipe);
+               return -1;
+       }
+
+       if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+               err("sohci_submit_job failed");
+               return -1;
+       }
+
+       wait_ms(10);
+       /* ohci_dump_status(&gohci); */
+
+       /* allow more time for a BULK device to react - some are slow */
+#define BULK_TO         5000   /* timeout in milliseconds */
+       if (usb_pipebulk(pipe))
+               timeout = BULK_TO;
+       else
+               timeout = 100;
+
+       timeout *= 4;
+       /* wait for it to complete */
+       for (;;) {
+               /* check whether the controller is done */
+               stat = hc_interrupt();
+               if (stat < 0) {
+                       stat = USB_ST_CRC_ERR;
+                       break;
+               }
+               if (stat >= 0 && stat != 0xff) {
+                       /* 0xff is returned for an SF-interrupt */
+                       break;
+               }
+               if (--timeout) {
+                       udelay(250); /* wait_ms(1); */
+               } else {
+                       err("CTL:TIMEOUT ");
+                       stat = USB_ST_CRC_ERR;
+                       break;
+               }
+       }
+       /* we got an Root Hub Status Change interrupt */
+       if (got_rhsc) {
+#ifdef DEBUG
+               ohci_dump_roothub (&gohci, 1);
+#endif
+               got_rhsc = 0;
+               /* abuse timeout */
+               timeout = rh_check_port_status(&gohci);
+               if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+                       /* the called routine adds 1 to the passed value */
+                       usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+                       /*
+                        * XXX
+                        * This is potentially dangerous because it assumes
+                        * that only one device is ever plugged in!
+                        */
+                       devgone = dev;
+               }
+       }
+
+       dev->status = stat;
+       dev->act_len = transfer_len;
+
+#ifdef DEBUG
+       pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+       wait_ms(1);
+#endif
+
+       /* free TDs in urb_priv */
+       urb_free_priv (&urb_priv);
+       return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+               int transfer_len)
+{
+       info("submit_bulk_msg");
+       return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+               int transfer_len, struct devrequest *setup)
+{
+       int maxsize = usb_maxpacket(dev, pipe);
+
+       info("submit_control_msg");
+#ifdef DEBUG
+       urb_priv.actual_length = 0;
+       pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+       wait_ms(1);
+#endif
+       if (!maxsize) {
+               err("submit_control_message: pipesize for pipe %lx is zero",
+                       pipe);
+               return -1;
+       }
+       if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+               gohci.rh.dev = dev;
+               /* root hub - redirect */
+               return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
+                       setup);
+       }
+
+       return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+               int transfer_len, int interval)
+{
+       info("submit_int_msg");
+       return -1;
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset (ohci_t *ohci)
+{
+       int timeout = 30;
+       int smm_timeout = 50; /* 0,5 sec */
+
+       if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
+               writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+               info("USB HC TakeOver from SMM");
+               while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
+                       wait_ms (10);
+                       if (--smm_timeout == 0) {
+                               err("USB HC TakeOver failed!");
+                               return -1;
+                       }
+               }
+       }
+
+       /* Disable HC interrupts */
+       writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+
+       dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
+               ohci->slot_name,
+               readl (&ohci->regs->control));
+
+       /* Reset USB (needed by some controllers) */
+       writel (0, &ohci->regs->control);
+
+       /* HC Reset requires max 10 us delay */
+       writel (OHCI_HCR,  &ohci->regs->cmdstatus);
+       while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+               if (--timeout == 0) {
+                       err("USB HC reset timed out!");
+                       return -1;
+               }
+               udelay (1);
+       }
+       return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start (ohci_t * ohci)
+{
+       __u32 mask;
+       unsigned int fminterval;
+
+       ohci->disabled = 1;
+
+       /* Tell the controller where the control and bulk lists are
+        * The lists are empty now. */
+
+       writel (0, &ohci->regs->ed_controlhead);
+       writel (0, &ohci->regs->ed_bulkhead);
+
+       writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+
+       fminterval = 0x2edf;
+       writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+       fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+       writel (fminterval, &ohci->regs->fminterval);
+       writel (0x628, &ohci->regs->lsthresh);
+
+       /* start controller operations */
+       ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+       ohci->disabled = 0;
+       writel (ohci->hc_control, &ohci->regs->control);
+
+       /* disable all interrupts */
+       mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+                       OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+                       OHCI_INTR_OC | OHCI_INTR_MIE);
+       writel (mask, &ohci->regs->intrdisable);
+       /* clear all interrupts */
+       mask &= ~OHCI_INTR_MIE;
+       writel (mask, &ohci->regs->intrstatus);
+       /* Choose the interrupts we care about now  - but w/o MIE */
+       mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+       writel (mask, &ohci->regs->intrenable);
+
+#ifdef OHCI_USE_NPS
+       /* required for AMD-756 and some Mac platforms */
+       writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
+               &ohci->regs->roothub.a);
+       writel (RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+
+#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
+       /* POTPGT delay is bits 24-31, in 2 ms units. */
+       mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+
+       /* connect the virtual root hub */
+       ohci->rh.devnum = 0;
+
+       return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* an interrupt happens */
+
+static int
+hc_interrupt (void)
+{
+       ohci_t *ohci = &gohci;
+       struct ohci_regs *regs = ohci->regs;
+       int ints;
+       int stat = -1;
+
+       if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+               ints =  OHCI_INTR_WDH;
+       } else {
+               ints = readl (&regs->intrstatus);
+       }
+
+       /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+
+       if (ints & OHCI_INTR_RHSC) {
+               got_rhsc = 1;
+       }
+
+       if (ints & OHCI_INTR_UE) {
+               ohci->disabled++;
+               err ("OHCI Unrecoverable Error, controller usb-%s disabled",
+                       ohci->slot_name);
+               /* e.g. due to PCI Master/Target Abort */
+
+#ifdef DEBUG
+               ohci_dump (ohci, 1);
+#else
+       wait_ms(1);
+#endif
+               /* FIXME: be optimistic, hope that bug won't repeat often. */
+               /* Make some non-interrupt context restart the controller. */
+               /* Count and limit the retries though; either hardware or */
+               /* software errors can go forever... */
+               hc_reset (ohci);
+               return -1;
+       }
+
+       if (ints & OHCI_INTR_WDH) {
+               wait_ms(1);
+               writel (OHCI_INTR_WDH, &regs->intrdisable);
+               stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
+               writel (OHCI_INTR_WDH, &regs->intrenable);
+       }
+
+       if (ints & OHCI_INTR_SO) {
+               dbg("USB Schedule overrun\n");
+               writel (OHCI_INTR_SO, &regs->intrenable);
+               stat = -1;
+       }
+
+       /* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
+       if (ints & OHCI_INTR_SF) {
+               unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+               wait_ms(1);
+               writel (OHCI_INTR_SF, &regs->intrdisable);
+               if (ohci->ed_rm_list[frame] != NULL)
+                       writel (OHCI_INTR_SF, &regs->intrenable);
+               stat = 0xff;
+       }
+
+       writel (ints, &regs->intrstatus);
+       return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci (ohci_t *ohci)
+{
+       dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+
+       if (!ohci->disabled)
+               hc_reset (ohci);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#define __read_32bit_c0_register(source, sel)                          \
+({ int __res;                                                          \
+       if (sel == 0)                                                   \
+               __asm__ __volatile__(                                   \
+                       "mfc0\t%0, " #source "\n\t"                     \
+                       : "=r" (__res));                                \
+       else                                                            \
+               __asm__ __volatile__(                                   \
+                       ".set\tmips32\n\t"                              \
+                       "mfc0\t%0, " #source ", " #sel "\n\t"           \
+                       ".set\tmips0\n\t"                               \
+                       : "=r" (__res));                                \
+       __res;                                                          \
+})
+
+#define read_c0_prid()         __read_32bit_c0_register($15, 0)
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+static char ohci_inited = 0;
+
+int usb_lowlevel_init(void)
+{
+       u32 pin_func;
+       u32 sys_freqctrl, sys_clksrc;
+       u32 prid = read_c0_prid();
+
+       dbg("in usb_lowlevel_init\n");
+
+       /* zero and disable FREQ2 */
+       sys_freqctrl = au_readl(SYS_FREQCTRL0);
+       sys_freqctrl &= ~0xFFF00000;
+       au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+       /* zero and disable USBH/USBD clocks */
+       sys_clksrc = au_readl(SYS_CLKSRC);
+       sys_clksrc &= ~0x00007FE0;
+       au_writel(sys_clksrc, SYS_CLKSRC);
+
+       sys_freqctrl = au_readl(SYS_FREQCTRL0);
+       sys_freqctrl &= ~0xFFF00000;
+
+       sys_clksrc = au_readl(SYS_CLKSRC);
+       sys_clksrc &= ~0x00007FE0;
+
+       switch (prid & 0x000000FF) {
+       case 0x00: /* DA */
+       case 0x01: /* HA */
+       case 0x02: /* HB */
+               /* CPU core freq to 48MHz to slow it way down... */
+               au_writel(4, SYS_CPUPLL);
+
+               /*
+                * Setup 48MHz FREQ2 from CPUPLL for USB Host
+                */
+               /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
+               sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
+               au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+               /* CPU core freq to 384MHz */
+               au_writel(0x20, SYS_CPUPLL);
+
+               printf("Au1000: 48MHz OHCI workaround enabled\n");
+               break;
+
+       default:  /* HC and newer */
+               /* FREQ2 = aux/2 = 48 MHz */
+               sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
+               au_writel(sys_freqctrl, SYS_FREQCTRL0);
+               break;
+       }
+
+       /*
+        * Route 48MHz FREQ2 into USB Host and/or Device
+        */
+       sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
+       au_writel(sys_clksrc, SYS_CLKSRC);
+
+       /* configure pins GPIO[14:9] as GPIO */
+       pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
+
+       au_writel(pin_func, SYS_PINFUNC);
+       au_writel(0x2800, SYS_TRIOUTCLR);
+       au_writel(0x0030, SYS_OUTPUTCLR);
+
+       dbg("OHCI board setup complete\n");
+
+       /* enable host controller */
+       au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
+       udelay(1000);
+       au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
+       udelay(1000);
+
+       /* wait for reset complete (read register twice; see au1500 errata) */
+       while (au_readl(USB_HOST_CONFIG),
+              !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
+               udelay(1000);
+
+       dbg("OHCI clock running\n");
+
+       memset (&gohci, 0, sizeof (ohci_t));
+       memset (&urb_priv, 0, sizeof (urb_priv_t));
+
+       /* align the storage */
+       if ((__u32)&ghcca[0] & 0xff) {
+               err("HCCA not aligned!!");
+               return -1;
+       }
+       phcca = &ghcca[0];
+       info("aligned ghcca %p", phcca);
+       memset(&ohci_dev, 0, sizeof(struct ohci_device));
+       if ((__u32)&ohci_dev.ed[0] & 0x7) {
+               err("EDs not aligned!!");
+               return -1;
+       }
+       memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
+       if ((__u32)gtd & 0x7) {
+               err("TDs not aligned!!");
+               return -1;
+       }
+       ptd = gtd;
+       gohci.hcca = phcca;
+       memset (phcca, 0, sizeof (struct ohci_hcca));
+
+       gohci.disabled = 1;
+       gohci.sleeping = 0;
+       gohci.irq = -1;
+       gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
+
+       gohci.flags = 0;
+       gohci.slot_name = "au1x00";
+
+       dbg("OHCI revision: 0x%08x\n"
+              "  RH: a: 0x%08x b: 0x%08x\n",
+              readl(&gohci.regs->revision),
+              readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
+
+       if (hc_reset (&gohci) < 0)
+               goto errout;
+
+       /* FIXME this is a second HC reset; why?? */
+       writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
+       wait_ms (10);
+
+       if (hc_start (&gohci) < 0)
+               goto errout;
+
+#ifdef DEBUG
+       ohci_dump (&gohci, 1);
+#else
+       wait_ms(1);
+#endif
+       ohci_inited = 1;
+       return 0;
+
+  errout:
+       err("OHCI initialization error\n");
+       hc_release_ohci (&gohci);
+       /* Initialization failed */
+       au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
+       return -1;
+}
+
+int usb_lowlevel_stop(void)
+{
+       /* this gets called really early - before the controller has */
+       /* even been initialized! */
+       if (!ohci_inited)
+               return 0;
+       /* TODO release any interrupts, etc. */
+       /* call hc_release_ohci() here ? */
+       hc_reset (&gohci);
+       /* may not want to do this */
+       /* Disable clock */
+       au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
+       return 0;
+}
+
+#endif /* CONFIG_USB_OHCI */
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h b/arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h
new file mode 100644 (file)
index 0000000..bb9f351
--- /dev/null
@@ -0,0 +1,416 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+       /* No  Error  */        0,
+       /* CRC Error  */        USB_ST_CRC_ERR,
+       /* Bit Stuff  */        USB_ST_BIT_ERR,
+       /* Data Togg  */        USB_ST_CRC_ERR,
+       /* Stall      */        USB_ST_STALLED,
+       /* DevNotResp */        -1,
+       /* PIDCheck   */        USB_ST_BIT_ERR,
+       /* UnExpPID   */        USB_ST_BIT_ERR,
+       /* DataOver   */        USB_ST_BUF_ERR,
+       /* DataUnder  */        USB_ST_BUF_ERR,
+       /* reservd    */        -1,
+       /* reservd    */        -1,
+       /* BufferOver */        USB_ST_BUF_ERR,
+       /* BuffUnder  */        USB_ST_BUF_ERR,
+       /* Not Access */        -1,
+       /* Not Access */        -1
+};
+
+/* ED States */
+
+#define ED_NEW         0x00
+#define ED_UNLINK      0x01
+#define ED_OPER                0x02
+#define ED_DEL         0x04
+#define ED_URB_DEL     0x08
+
+/* usb_ohci_ed */
+struct ed {
+       __u32 hwINFO;
+       __u32 hwTailP;
+       __u32 hwHeadP;
+       __u32 hwNextED;
+
+       struct ed *ed_prev;
+       __u8 int_period;
+       __u8 int_branch;
+       __u8 int_load;
+       __u8 int_interval;
+       __u8 state;
+       __u8 type;
+       __u16 last_iso;
+       struct ed *ed_rm_list;
+
+       struct usb_device *usb_dev;
+       __u32 unused[3];
+} __attribute__((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC                  0xf0000000
+#define TD_CC_GET(td_p)                ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc)    (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC                  0x0C000000
+#define TD_T                   0x03000000
+#define TD_T_DATA0             0x02000000
+#define TD_T_DATA1             0x03000000
+#define TD_T_TOGGLE            0x00000000
+#define TD_R                   0x00040000
+#define TD_DI                  0x00E00000
+#define TD_DI_SET(X)           (((X) & 0x07)<< 21)
+#define TD_DP                  0x00180000
+#define TD_DP_SETUP            0x00000000
+#define TD_DP_IN               0x00100000
+#define TD_DP_OUT              0x00080000
+
+#define TD_ISO                 0x00010000
+#define TD_DEL                 0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR          0x00
+#define TD_CC_CRC              0x01
+#define TD_CC_BITSTUFFING      0x02
+#define TD_CC_DATATOGGLEM      0x03
+#define TD_CC_STALL            0x04
+#define TD_DEVNOTRESP          0x05
+#define TD_PIDCHECKFAIL                0x06
+#define TD_UNEXPECTEDPID       0x07
+#define TD_DATAOVERRUN         0x08
+#define TD_DATAUNDERRUN                0x09
+#define TD_BUFFEROVERRUN       0x0C
+#define TD_BUFFERUNDERRUN      0x0D
+#define TD_NOTACCESSED         0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+       __u32 hwINFO;
+       __u32 hwCBP;            /* Current Buffer Pointer */
+       __u32 hwNextTD;         /* Next TD Pointer */
+       __u32 hwBE;             /* Memory Buffer End Pointer */
+
+       __u16 hwPSW[MAXPSW];
+       __u8 unused;
+       __u8 index;
+       struct ed *ed;
+       struct td *next_dl_td;
+       struct usb_device *usb_dev;
+       int transfer_len;
+       __u32 data;
+
+       __u32 unused2[2];
+} __attribute__((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP   (1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32    /* part of the OHCI standard */
+struct ohci_hcca {
+       __u32   int_table[NUM_INTS];    /* Interrupt ED table */
+       __u16   frame_no;               /* current frame number */
+       __u16   pad1;                   /* set to 0 on each frame_no change */
+       __u32   done_head;              /* info returned for an interrupt */
+       u8              reserved_for_hc[116];
+} __attribute__((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#define MAX_ROOT_PORTS 15      /* maximum OHCI root hub ports */
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O. You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+       /* control and status registers */
+       __u32   revision;
+       __u32   control;
+       __u32   cmdstatus;
+       __u32   intrstatus;
+       __u32   intrenable;
+       __u32   intrdisable;
+       /* memory pointers */
+       __u32   hcca;
+       __u32   ed_periodcurrent;
+       __u32   ed_controlhead;
+       __u32   ed_controlcurrent;
+       __u32   ed_bulkhead;
+       __u32   ed_bulkcurrent;
+       __u32   donehead;
+       /* frame counters */
+       __u32   fminterval;
+       __u32   fmremaining;
+       __u32   fmnumber;
+       __u32   periodicstart;
+       __u32   lsthresh;
+       /* Root hub ports */
+       struct  ohci_roothub_regs {
+               __u32   a;
+               __u32   b;
+               __u32   status;
+               __u32   portstatus[MAX_ROOT_PORTS];
+       } roothub;
+} __attribute__((aligned(32)));
+
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR (3 << 0)        /* control/bulk service ratio */
+#define OHCI_CTRL_PLE  (1 << 2)        /* periodic list enable */
+#define OHCI_CTRL_IE   (1 << 3)        /* isochronous enable */
+#define OHCI_CTRL_CLE  (1 << 4)        /* control list enable */
+#define OHCI_CTRL_BLE  (1 << 5)        /* bulk list enable */
+#define OHCI_CTRL_HCFS (3 << 6)        /* host controller functional state */
+#define OHCI_CTRL_IR   (1 << 8)        /* interrupt routing */
+#define OHCI_CTRL_RWC  (1 << 9)        /* remote wakeup connected */
+#define OHCI_CTRL_RWE  (1 << 10)       /* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#      define OHCI_USB_RESET   (0 << 6)
+#      define OHCI_USB_RESUME  (1 << 6)
+#      define OHCI_USB_OPER    (2 << 6)
+#      define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR       (1 << 0)        /* host controller reset */
+#define OHCI_CLF       (1 << 1)        /* control list filled */
+#define OHCI_BLF       (1 << 2)        /* bulk list filled */
+#define OHCI_OCR       (1 << 3)        /* ownership change request */
+#define OHCI_SOC       (3 << 16)       /* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO   (1 << 0)        /* scheduling overrun */
+#define OHCI_INTR_WDH  (1 << 1)        /* writeback of done_head */
+#define OHCI_INTR_SF   (1 << 2)        /* start frame */
+#define OHCI_INTR_RD   (1 << 3)        /* resume detect */
+#define OHCI_INTR_UE   (1 << 4)        /* unrecoverable error */
+#define OHCI_INTR_FNO  (1 << 5)        /* frame number overflow */
+#define OHCI_INTR_RHSC (1 << 6)        /* root hub status change */
+#define OHCI_INTR_OC   (1 << 30)       /* ownership change */
+#define OHCI_INTR_MIE  (1 << 31)       /* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+       int devnum; /* Address of Root Hub endpoint */
+       void *dev;  /* was urb */
+       void *int_addr;
+       int send;
+       int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE           0x01
+#define RH_ENDPOINT            0x02
+#define RH_OTHER               0x03
+
+#define RH_CLASS               0x20
+#define RH_VENDOR              0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS          0x0080
+#define RH_CLEAR_FEATURE       0x0100
+#define RH_SET_FEATURE         0x0300
+#define RH_SET_ADDRESS         0x0500
+#define RH_GET_DESCRIPTOR      0x0680
+#define RH_SET_DESCRIPTOR      0x0700
+#define RH_GET_CONFIGURATION   0x0880
+#define RH_SET_CONFIGURATION   0x0900
+#define RH_GET_STATE           0x0280
+#define RH_GET_INTERFACE       0x0A80
+#define RH_SET_INTERFACE       0x0B00
+#define RH_SYNC_FRAME          0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP              0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION     0x00
+#define RH_PORT_ENABLE         0x01
+#define RH_PORT_SUSPEND                0x02
+#define RH_PORT_OVER_CURRENT   0x03
+#define RH_PORT_RESET          0x04
+#define RH_PORT_POWER          0x08
+#define RH_PORT_LOW_SPEED      0x09
+
+#define RH_C_PORT_CONNECTION   0x10
+#define RH_C_PORT_ENABLE       0x11
+#define RH_C_PORT_SUSPEND      0x12
+#define RH_C_PORT_OVER_CURRENT 0x13
+#define RH_C_PORT_RESET                0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER   0x00
+#define RH_C_HUB_OVER_CURRENT  0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP 0x00
+#define RH_ENDPOINT_STALL      0x01
+
+#define RH_ACK                 0x01
+#define RH_REQ_ERR             -1
+#define RH_NACK                        0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS              0x00000001      /* current connect status */
+#define RH_PS_PES              0x00000002      /* port enable status*/
+#define RH_PS_PSS              0x00000004      /* port suspend status */
+#define RH_PS_POCI             0x00000008      /* port over current indicator */
+#define RH_PS_PRS              0x00000010      /* port reset status */
+#define RH_PS_PPS              0x00000100      /* port power status */
+#define RH_PS_LSDA             0x00000200      /* low speed device attached */
+#define RH_PS_CSC              0x00010000      /* connect status change */
+#define RH_PS_PESC             0x00020000      /* port enable status change */
+#define RH_PS_PSSC             0x00040000      /* port suspend status change */
+#define RH_PS_OCIC             0x00080000      /* over current indicator change */
+#define RH_PS_PRSC             0x00100000      /* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS              0x00000001      /* local power status */
+#define RH_HS_OCI              0x00000002      /* over current indicator */
+#define RH_HS_DRWE             0x00008000      /* device remote wakeup enable */
+#define RH_HS_LPSC             0x00010000      /* local power status change */
+#define RH_HS_OCIC             0x00020000      /* over current indicator change */
+#define RH_HS_CRWE             0x80000000      /* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR                        0x0000ffff      /* device removable flags */
+#define RH_B_PPCM              0xffff0000      /* port power control mask */
+
+/* roothub.a masks */
+#define        RH_A_NDP                (0xff << 0)     /* number of downstream ports */
+#define        RH_A_PSM                (1 << 8)        /* power switching mode */
+#define        RH_A_NPS                (1 << 9)        /* no power switching */
+#define        RH_A_DT                 (1 << 10)       /* device type (mbz) */
+#define        RH_A_OCPM               (1 << 11)       /* over current protection mode */
+#define        RH_A_NOCP               (1 << 12)       /* no over current protection */
+#define        RH_A_POTPGT             (0xff << 24)    /* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+       ed_t *ed;
+       __u16 length;           /* number of tds associated with this request */
+       __u16 td_cnt;           /* number of tds already serviced */
+       int   state;
+       unsigned long pipe;
+       int actual_length;
+       td_t *td[N_URB_TD];     /* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+
+typedef struct ohci {
+       struct ohci_hcca *hcca;         /* hcca */
+       /*dma_addr_t hcca_dma;*/
+
+       int irq;
+       int disabled;                   /* e.g. got a UE, we're hung */
+       int sleeping;
+       unsigned long flags;            /* for HC bugs */
+
+       struct ohci_regs *regs;         /* OHCI controller's memory */
+
+       ed_t *ed_rm_list[2];            /* lists of all endpoints to be removed */
+       ed_t *ed_bulktail;              /* last endpoint of bulk list */
+       ed_t *ed_controltail;           /* last endpoint of control list */
+       int intrstatus;
+       __u32 hc_control;               /* copy of the hc control reg */
+       struct usb_device *dev[32];
+       struct virt_root_hub rh;
+
+       const char      *slot_name;
+} ohci_t;
+
+#define NUM_EDS 8              /* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+       ed_t    ed[NUM_EDS];
+       int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+       int i;
+       struct td       *td;
+
+       td = NULL;
+       for (i = 0; i < NUM_TD; i++) {
+               if (ptd[i].usb_dev == NULL) {
+                       td = &ptd[i];
+                       td->usb_dev = usb_dev;
+                       break;
+               }
+       }
+       return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+       ed->usb_dev = NULL;
+}
diff --git a/arch/mips/cpu/mips32/au1x00/config.mk b/arch/mips/cpu/mips32/au1x00/config.mk
new file mode 100644 (file)
index 0000000..568f333
--- /dev/null
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -mtune=4kc
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
new file mode 100644 (file)
index 0000000..2965938
--- /dev/null
@@ -0,0 +1,328 @@
+/*
+ *  Cache-handling routined for MIPS CPUs
+ *
+ *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA             t8
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE    0x10000
+
+#define INDEX_BASE     CKSEG0
+
+       .macro  cache_op op addr
+       .set    push
+       .set    noreorder
+       .set    mips3
+       cache   \op, 0(\addr)
+       .set    pop
+       .endm
+
+/*
+ * cacheop macro to automate cache operations
+ * first some helpers...
+ */
+#define _mincache(size, maxsize) \
+   bltu  size,maxsize,9f ; \
+   move  size,maxsize ;    \
+9:
+
+#define _align(minaddr, maxaddr, linesize) \
+   .set noat ; \
+   subu  AT,linesize,1 ;   \
+   not   AT ;        \
+   and   minaddr,AT ;      \
+   addu  maxaddr,-1 ;      \
+   and   maxaddr,AT ;      \
+   .set at
+
+/* general operations */
+#define doop1(op1) \
+   cache op1,0(a0)
+#define doop2(op1, op2) \
+   cache op1,0(a0) ;    \
+   nop ;          \
+   cache op2,0(a0)
+
+/* specials for cache initialisation */
+#define doop1lw(op1) \
+   lw zero,0(a0)
+#define doop1lw1(op1) \
+   cache op1,0(a0) ;    \
+   lw zero,0(a0) ;      \
+   cache op1,0(a0)
+#define doop121(op1,op2) \
+   cache op1,0(a0) ;    \
+   nop;           \
+   cache op2,0(a0) ;    \
+   nop;           \
+   cache op1,0(a0)
+
+#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
+   .set  noreorder ;    \
+10:   doop##tag##ops ;  \
+   bne     minaddr,maxaddr,10b ; \
+   add      minaddr,linesize ;   \
+   .set  reorder
+
+/* finally the cache operation macros */
+#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
+   blez  n,11f ;        \
+   addu  n,kva ;        \
+   _align(kva, n, cacheLineSize) ; \
+   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
+11:
+
+#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
+   _mincache(n, cacheSize);   \
+   blez  n,11f ;        \
+   addu  n,kva ;        \
+   _align(kva, n, cacheLineSize) ; \
+   _oploopn(kva, n, cacheLineSize, tag, ops) ; \
+11:
+
+#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
+   vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
+
+#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
+   icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
+
+       .macro  f_fill64 dst, offset, val
+       LONG_S  \val, (\offset +  0 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  1 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  2 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  3 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  4 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  5 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  6 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+       LONG_S  \val, (\offset +  8 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  9 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 10 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 11 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 12 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 13 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 14 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+       .endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+       blez    a1, 9f
+       mtc0    zero, CP0_TAGLO
+       /* clear tag to invalidate */
+       PTR_LI          t0, INDEX_BASE
+       PTR_ADDU        t1, t0, a1
+1:     cache_op        Index_Store_Tag_I t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+       /* fill once, so data field parity is correct */
+       PTR_LI          t0, INDEX_BASE
+2:     cache_op        Fill t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 2b
+       /* invalidate again - prudent but not strictly neccessary */
+       PTR_LI          t0, INDEX_BASE
+1:     cache_op        Index_Store_Tag_I t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+9:     jr      ra
+       END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+       blez    a1, 9f
+       mtc0    zero, CP0_TAGLO
+       /* clear all tags */
+       PTR_LI          t0, INDEX_BASE
+       PTR_ADDU        t1, t0, a1
+1:     cache_op        Index_Store_Tag_D t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+       /* load from each line (in cached space) */
+       PTR_LI          t0, INDEX_BASE
+2:     LONG_L          zero, 0(t0)
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 2b
+       /* clear all tags */
+       PTR_LI          t0, INDEX_BASE
+1:     cache_op        Index_Store_Tag_D t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+9:     jr      ra
+       END(mips_init_dcache)
+
+/*******************************************************************************
+*
+* mips_cache_reset - low level initialisation of the primary caches
+*
+* This routine initialises the primary caches to ensure that they
+* have good parity.  It must be called by the ROM before any cached locations
+* are used to prevent the possibility of data with bad parity being written to
+* memory.
+* To initialise the instruction cache it is essential that a source of data
+* with good parity is available. This routine
+* will initialise an area of memory starting at location zero to be used as
+* a source of parity.
+*
+* RETURNS: N/A
+*
+*/
+NESTED(mips_cache_reset, 0, ra)
+       move    RA, ra
+       li      t2, CONFIG_SYS_ICACHE_SIZE
+       li      t3, CONFIG_SYS_DCACHE_SIZE
+       li      t4, CONFIG_SYS_CACHELINE_SIZE
+       move    t5, t4
+
+       li      v0, MIPS_MAX_CACHE_SIZE
+
+       /*
+        * Now clear that much memory starting from zero.
+        */
+       PTR_LI          a0, CKSEG1
+       PTR_ADDU        a1, a0, v0
+2:     PTR_ADDIU       a0, 64
+       f_fill64        a0, -64, zero
+       bne             a0, a1, 2b
+
+       /*
+        * The caches are probably in an indeterminate state,
+        * so we force good parity into them by doing an
+        * invalidate, load/fill, invalidate for each line.
+        */
+
+       /*
+        * Assume bottom of RAM will generate good parity for the cache.
+        */
+
+       /*
+        * Initialize the I-cache first,
+        */
+       move    a1, t2
+       move    a2, t4
+       PTR_LA  t7, mips_init_icache
+       jalr    t7
+
+       /*
+        * then initialize D-cache.
+        */
+       move    a1, t3
+       move    a2, t5
+       PTR_LA  t7, mips_init_dcache
+       jalr    t7
+
+       jr      RA
+       END(mips_cache_reset)
+
+/*******************************************************************************
+*
+* dcache_status - get cache status
+*
+* RETURNS: 0 - cache disabled; 1 - cache enabled
+*
+*/
+LEAF(dcache_status)
+       mfc0    t0, CP0_CONFIG
+       li      t1, CONF_CM_UNCACHED
+       andi    t0, t0, CONF_CM_CMASK
+       move    v0, zero
+       beq     t0, t1, 2f
+       li      v0, 1
+2:     jr      ra
+       END(dcache_status)
+
+/*******************************************************************************
+*
+* dcache_disable - disable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_disable)
+       mfc0    t0, CP0_CONFIG
+       li      t1, -8
+       and     t0, t0, t1
+       ori     t0, t0, CONF_CM_UNCACHED
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_disable)
+
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+       mfc0    t0, CP0_CONFIG
+       ori     t0, CONF_CM_CMASK
+       xori    t0, CONF_CM_CMASK
+       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_enable)
+
+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
+/*******************************************************************************
+*
+* mips_cache_lock - lock RAM area pointed to by a0 in cache.
+*
+* RETURNS: N/A
+*
+*/
+# define       CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
+       .globl  mips_cache_lock
+       .ent    mips_cache_lock
+mips_cache_lock:
+       li      a1, CKSEG0 - CACHE_LOCK_SIZE
+       addu    a0, a1
+       li      a2, CACHE_LOCK_SIZE
+       li      a3, CONFIG_SYS_CACHELINE_SIZE
+       move    a1, a2
+       icacheop(a0,a1,a2,a3,0x1d)
+
+       jr      ra
+
+       .end    mips_cache_lock
+#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk
new file mode 100644 (file)
index 0000000..4d1b273
--- /dev/null
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS32
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips32r2
+
+ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ENDIANNESS = -EL
+else
+ENDIANNESS = -EB
+endif
+
+MIPSFLAGS += $(ENDIANNESS)
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
new file mode 100644 (file)
index 0000000..3ae397c
--- /dev/null
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op,addr)                                              \
+       __asm__ __volatile__(                                           \
+       "       .set    push                                    \n"     \
+       "       .set    noreorder                               \n"     \
+       "       .set    mips3\n\t                               \n"     \
+       "       cache   %0, %1                                  \n"     \
+       "       .set    pop                                     \n"     \
+       :                                                               \
+       : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       _machine_restart();
+
+       fprintf(stderr, "*** reset failed ***\n");
+       return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(Hit_Invalidate_I, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Invalidate_D, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+       write_c0_entrylo0(low0);
+       write_c0_pagemask(pagemask);
+       write_c0_entrylo1(low1);
+       write_c0_entryhi(hi);
+       write_c0_index(index);
+       tlb_write_indexed();
+}
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SOC_AU1X00
+       au1x00_enet_initialize(bis);
+#endif
+       return 0;
+}
diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile
new file mode 100644 (file)
index 0000000..9c2b1aa
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).o
+
+SOBJS  = incaip_wdt.o
+COBJS  = incaip_clock.o asc_serial.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c
new file mode 100644 (file)
index 0000000..7239804
--- /dev/null
@@ -0,0 +1,285 @@
+/*
+ * (INCA) ASC UART support
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/inca-ip.h>
+#include "asc_serial.h"
+
+
+#define SET_BIT(reg, mask)                  reg |= (mask)
+#define CLEAR_BIT(reg, mask)                reg &= (~mask)
+#define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
+#define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
+#define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
+
+extern uint incaip_get_fpiclk(void);
+
+static int serial_setopt (void);
+
+/* pointer to ASC register base address */
+static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
+
+/******************************************************************************
+*
+* serial_init - initialize a INCAASC channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+    /* we have to set PMU.EN13 bit to enable an ASC device*/
+    INCAASC_PMU_ENABLE(13);
+
+    /* and we have to set CLC register*/
+    CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
+    SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
+
+    /* initialy we are in async mode */
+    pAsc->asc_con = ASCCON_M_8ASYNC;
+
+    /* select input port */
+    pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
+
+    /* TXFIFO's filling level */
+    SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
+                   ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
+    /* enable TXFIFO */
+    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
+
+    /* RXFIFO's filling level */
+    SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
+                   ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
+    /* enable RXFIFO */
+    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
+
+    /* enable error signals */
+    SET_BIT(pAsc->asc_con, ASCCON_FEN);
+    SET_BIT(pAsc->asc_con, ASCCON_OEN);
+
+    /* acknowledge ASC interrupts */
+    ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
+
+    /* disable ASC interrupts */
+    ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
+
+    /* set FIFOs into the transparent mode */
+    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
+    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
+
+    /* set baud rate */
+    serial_setbrg();
+
+    /* set the options */
+    serial_setopt();
+
+    return 0;
+}
+
+void serial_setbrg (void)
+{
+    ulong      uiReloadValue, fdv;
+    ulong      f_ASC;
+
+    f_ASC = incaip_get_fpiclk();
+
+#ifndef INCAASC_USE_FDV
+    fdv = 2;
+    uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+    fdv = INCAASC_FDV_HIGH_BAUDRATE;
+    uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+#endif /* INCAASC_USE_FDV */
+
+    if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+    {
+#ifndef INCAASC_USE_FDV
+       fdv = 3;
+       uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+       fdv = INCAASC_FDV_LOW_BAUDRATE;
+       uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+#endif /* INCAASC_USE_FDV */
+
+       if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+       {
+           return;    /* can't impossibly generate that baud rate */
+       }
+    }
+
+    /* Disable Baud Rate Generator; BG should only be written when R=0 */
+    CLEAR_BIT(pAsc->asc_con, ASCCON_R);
+
+#ifndef INCAASC_USE_FDV
+    /*
+     * Disable Fractional Divider (FDE)
+     * Divide clock by reload-value + constant (BRS)
+     */
+    /* FDE = 0 */
+    CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
+
+    if ( fdv == 2 )
+       CLEAR_BIT(pAsc->asc_con, ASCCON_BRS);   /* BRS = 0 */
+    else
+       SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
+
+#else /* INCAASC_USE_FDV */
+
+    /* Enable Fractional Divider */
+    SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
+
+    /* Set fractional divider value */
+    pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
+
+#endif /* INCAASC_USE_FDV */
+
+    /* Set reload value in BG */
+    pAsc->asc_bg = uiReloadValue;
+
+    /* Enable Baud Rate Generator */
+    SET_BIT(pAsc->asc_con, ASCCON_R);           /* R = 1 */
+}
+
+/*******************************************************************************
+*
+* serial_setopt - set the serial options
+*
+* Set the channel operating mode to that specified. Following options
+* are supported: CREAD, CSIZE, PARENB, and PARODD.
+*
+* Note, this routine disables the transmitter.  The calling routine
+* may have to re-enable it.
+*
+* RETURNS:
+* Returns 0 to indicate success, otherwise -1 is returned
+*/
+
+static int serial_setopt (void)
+{
+    ulong  con;
+
+    switch ( ASC_OPTIONS & ASCOPT_CSIZE )
+    {
+    /* 7-bit-data */
+    case ASCOPT_CS7:
+       con = ASCCON_M_7ASYNCPAR;   /* 7-bit-data and parity bit */
+       break;
+
+    /* 8-bit-data */
+    case ASCOPT_CS8:
+       if ( ASC_OPTIONS & ASCOPT_PARENB )
+           con = ASCCON_M_8ASYNCPAR;   /* 8-bit-data and parity bit */
+       else
+           con = ASCCON_M_8ASYNC;      /* 8-bit-data no parity */
+       break;
+
+    /*
+     *  only 7 and 8-bit frames are supported
+     *  if we don't use IOCTL extensions
+     */
+    default:
+       return -1;
+    }
+
+    if ( ASC_OPTIONS & ASCOPT_STOPB )
+       SET_BIT(con, ASCCON_STP);       /* 2 stop bits */
+    else
+       CLEAR_BIT(con, ASCCON_STP);     /* 1 stop bit */
+
+    if ( ASC_OPTIONS & ASCOPT_PARENB )
+       SET_BIT(con, ASCCON_PEN);           /* enable parity checking */
+    else
+       CLEAR_BIT(con, ASCCON_PEN);         /* disable parity checking */
+
+    if ( ASC_OPTIONS & ASCOPT_PARODD )
+       SET_BIT(con, ASCCON_ODD);       /* odd parity */
+    else
+       CLEAR_BIT(con, ASCCON_ODD);     /* even parity */
+
+    if ( ASC_OPTIONS & ASCOPT_CREAD )
+       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
+
+    pAsc->asc_con |= con;
+
+    return 0;
+}
+
+void serial_putc (const char c)
+{
+    uint txFl = 0;
+
+    if (c == '\n') serial_putc ('\r');
+
+    /* check do we have a free space in the TX FIFO */
+    /* get current filling level */
+    do
+    {
+       txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
+    }
+    while ( txFl == INCAASC_TXFIFO_FULL );
+
+    pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
+
+    /* check for errors */
+    if ( pAsc->asc_con & ASCCON_OE )
+    {
+       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+       return;
+    }
+}
+
+void serial_puts (const char *s)
+{
+    while (*s)
+    {
+       serial_putc (*s++);
+    }
+}
+
+int serial_getc (void)
+{
+    ulong symbol_mask;
+    char c;
+
+    while (!serial_tstc());
+
+    symbol_mask =
+       ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
+
+    c = (char)(pAsc->asc_rbuf & symbol_mask);
+
+    return c;
+}
+
+int serial_tstc (void)
+{
+    int res = 1;
+
+    if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
+    {
+       res = 0;
+    }
+    else if ( pAsc->asc_con & ASCCON_FE )
+    {
+       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
+       res = 0;
+    }
+    else if ( pAsc->asc_con & ASCCON_PE )
+    {
+       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
+       res = 0;
+    }
+    else if ( pAsc->asc_con & ASCCON_OE )
+    {
+       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+       res = 0;
+    }
+
+    return res;
+}
diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h
new file mode 100644 (file)
index 0000000..7ffdcfa
--- /dev/null
@@ -0,0 +1,177 @@
+/* incaAscSio.h - (INCA) ASC UART tty driver header */
+
+#ifndef __INCincaAscSioh
+#define __INCincaAscSioh
+
+#include <asm/inca-ip.h>
+
+/* channel operating modes */
+#define        ASCOPT_CSIZE    0x00000003
+#define        ASCOPT_CS7      0x00000001
+#define        ASCOPT_CS8      0x00000002
+#define        ASCOPT_PARENB   0x00000004
+#define        ASCOPT_STOPB    0x00000008
+#define        ASCOPT_PARODD   0x00000010
+#define        ASCOPT_CREAD    0x00000020
+
+#define ASC_OPTIONS            (ASCOPT_CREAD | ASCOPT_CS8)
+
+/* ASC input select (0 or 1) */
+#define CONSOLE_TTY    0
+
+/* use fractional divider for baudrate settings */
+#define INCAASC_USE_FDV
+
+#ifdef INCAASC_USE_FDV
+   #define INCAASC_FDV_LOW_BAUDRATE        71
+   #define INCAASC_FDV_HIGH_BAUDRATE       453
+#endif /*INCAASC_USE_FDV*/
+
+
+#define INCAASC_TXFIFO_FL       1
+#define INCAASC_RXFIFO_FL       1
+#define INCAASC_TXFIFO_FULL     16
+
+/* interrupt lines masks for the ASC device interrupts*/
+/* change these macroses if it's necessary */
+#define INCAASC_IRQ_LINE_ALL        0x000F0000  /* all IRQs */
+
+#define INCAASC_IRQ_LINE_TIR            0x00010000      /* TIR - Tx */
+#define INCAASC_IRQ_LINE_RIR            0x00020000      /* RIR - Rx */
+#define INCAASC_IRQ_LINE_EIR            0x00040000      /* EIR - Err */
+#define INCAASC_IRQ_LINE_TBIR           0x00080000      /* TBIR - Tx Buf*/
+
+/* interrupt controller access macros */
+#define ASC_INTERRUPTS_ENABLE(X)  \
+   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
+#define ASC_INTERRUPTS_DISABLE(X) \
+   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
+#define ASC_INTERRUPTS_CLEAR(X)   \
+   *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
+
+/* CLC register's bits and bitfields */
+#define ASCCLC_DISR        0x00000001
+#define ASCCLC_DISS        0x00000002
+#define ASCCLC_RMCMASK     0x0000FF00
+#define ASCCLC_RMCOFFSET   8
+
+/* CON register's bits and bitfields */
+#define ASCCON_MODEMASK 0x0007
+    #define ASCCON_M_8SYNC          0x0
+    #define ASCCON_M_8ASYNC         0x1
+    #define ASCCON_M_8IRDAASYNC     0x2
+    #define ASCCON_M_7ASYNCPAR      0x3
+    #define ASCCON_M_9ASYNC         0x4
+    #define ASCCON_M_8WAKEUPASYNC   0x5
+    #define ASCCON_M_8ASYNCPAR      0x7
+#define ASCCON_STP      0x0008
+#define ASCCON_REN      0x0010
+#define ASCCON_PEN      0x0020
+#define ASCCON_FEN      0x0040
+#define ASCCON_OEN      0x0080
+#define ASCCON_PE       0x0100
+#define ASCCON_FE       0x0200
+#define ASCCON_OE       0x0400
+#define ASCCON_FDE      0x0800
+#define ASCCON_ODD      0x1000
+#define ASCCON_BRS      0x2000
+#define ASCCON_LB       0x4000
+#define ASCCON_R        0x8000
+
+/* WHBCON register's bits and bitfields */
+#define ASCWHBCON_CLRREN    0x0010
+#define ASCWHBCON_SETREN    0x0020
+#define ASCWHBCON_CLRPE     0x0100
+#define ASCWHBCON_CLRFE     0x0200
+#define ASCWHBCON_CLROE     0x0400
+#define ASCWHBCON_SETPE     0x0800
+#define ASCWHBCON_SETFE     0x1000
+#define ASCWHBCON_SETOE     0x2000
+
+/* ABCON register's bits and bitfields */
+#define ASCABCON_ABEN       0x0001
+#define ASCABCON_AUREN      0x0002
+#define ASCABCON_ABSTEN     0x0004
+#define ASCABCON_ABDETEN    0x0008
+#define ASCABCON_FCDETEN    0x0010
+#define ASCABCON_EMMASK     0x0300
+    #define ASCABCON_EMOFF          8
+       #define ASCABCON_EM_DISAB       0x0
+       #define ASCABCON_EM_DURAB       0x1
+       #define ASCABCON_EM_ALWAYS      0x2
+#define ASCABCON_TXINV      0x0400
+#define ASCABCON_RXINV      0x0800
+
+/* FDV register mask, offset and bitfields*/
+#define ASCFDV_VALUE_MASK     0x000001FF
+
+/* WHBABCON register's bits and bitfields */
+#define ASCWHBABCON_SETABEN     0x0001
+#define ASCWHBABCON_CLRABEN     0x0002
+
+/* ABSTAT register's bits and bitfields */
+#define ASCABSTAT_FCSDET    0x0001
+#define ASCABSTAT_FCCDET    0x0002
+#define ASCABSTAT_SCSDET    0x0004
+#define ASCABSTAT_SCCDET    0x0008
+#define ASCABSTAT_DETWAIT   0x0010
+
+/* WHBABSTAT register's bits and bitfields */
+#define ASCWHBABSTAT_CLRFCSDET  0x0001
+#define ASCWHBABSTAT_SETFCSDET  0x0002
+#define ASCWHBABSTAT_CLRFCCDET  0x0004
+#define ASCWHBABSTAT_SETFCCDET  0x0008
+#define ASCWHBABSTAT_CLRSCSDET  0x0010
+#define ASCWHBABSTAT_SETSCSDET  0x0020
+#define ASCWHBABSTAT_SETSCCDET  0x0040
+#define ASCWHBABSTAT_CLRSCCDET  0x0080
+#define ASCWHBABSTAT_CLRDETWAIT 0x0100
+#define ASCWHBABSTAT_SETDETWAIT 0x0200
+
+/* TXFCON register's bits and bitfields */
+#define ASCTXFCON_TXFEN         0x0001
+#define ASCTXFCON_TXFFLU        0x0002
+#define ASCTXFCON_TXTMEN        0x0004
+#define ASCTXFCON_TXFITLMASK    0x3F00
+#define ASCTXFCON_TXFITLOFF     8
+
+/* RXFCON register's bits and bitfields */
+#define ASCRXFCON_RXFEN         0x0001
+#define ASCRXFCON_RXFFLU        0x0002
+#define ASCRXFCON_RXTMEN        0x0004
+#define ASCRXFCON_RXFITLMASK    0x3F00
+#define ASCRXFCON_RXFITLOFF     8
+
+/* FSTAT register's bits and bitfields */
+#define ASCFSTAT_RXFFLMASK      0x003F
+#define ASCFSTAT_TXFFLMASK      0x3F00
+#define ASCFSTAT_TXFFLOFF       8
+
+#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
+
+typedef  struct         /* incaAsc_t */
+{
+    volatile unsigned long  asc_clc;                            /*0x0000*/
+    volatile unsigned long  asc_pisel;                          /*0x0004*/
+    volatile unsigned long  asc_rsvd1[2];   /* for mapping */   /*0x0008*/
+    volatile unsigned long  asc_con;                            /*0x0010*/
+    volatile unsigned long  asc_bg;                             /*0x0014*/
+    volatile unsigned long  asc_fdv;                            /*0x0018*/
+    volatile unsigned long  asc_pmw;        /* not used */      /*0x001C*/
+    volatile unsigned long  asc_tbuf;                           /*0x0020*/
+    volatile unsigned long  asc_rbuf;                           /*0x0024*/
+    volatile unsigned long  asc_rsvd2[2];   /* for mapping */   /*0x0028*/
+    volatile unsigned long  asc_abcon;                          /*0x0030*/
+    volatile unsigned long  asc_abstat;     /* not used */      /*0x0034*/
+    volatile unsigned long  asc_rsvd3[2];   /* for mapping */   /*0x0038*/
+    volatile unsigned long  asc_rxfcon;                         /*0x0040*/
+    volatile unsigned long  asc_txfcon;                         /*0x0044*/
+    volatile unsigned long  asc_fstat;                          /*0x0048*/
+    volatile unsigned long  asc_rsvd4;      /* for mapping */   /*0x004C*/
+    volatile unsigned long  asc_whbcon;                         /*0x0050*/
+    volatile unsigned long  asc_whbabcon;                       /*0x0054*/
+    volatile unsigned long  asc_whbabstat;  /* not used */      /*0x0058*/
+
+} incaAsc_t;
+
+#endif /* __INCincaAscSioh */
diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk
new file mode 100644 (file)
index 0000000..568f333
--- /dev/null
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -mtune=4kc
diff --git a/arch/mips/cpu/mips32/incaip/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c
new file mode 100644 (file)
index 0000000..b65dfe0
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/inca-ip.h>
+
+
+/*******************************************************************************
+*
+* get_cpuclk - returns the frequency of the CPU.
+*
+* Gets the value directly from the INCA-IP hardware.
+*
+* RETURNS:
+*          150.000.000 for 150 MHz
+*          133.333.333 for 133 MHz (= 400MHz/3)
+*          100.000.000 for 100 MHz (= 400MHz/4)
+* NOTE:
+*   This functions should be used by the hardware driver to get the correct
+*   frequency of the CPU. Don't use the macros, which are set to init the CPU
+*   frequency in the ROM code.
+*/
+uint incaip_get_cpuclk (void)
+{
+       /*-------------------------------------------------------------------------*/
+       /* CPU Clock Input Multiplexer (MUX I)                                     */
+       /* Multiplexer MUX I selects the maximum input clock to the CPU.           */
+       /*-------------------------------------------------------------------------*/
+       if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
+           INCA_IP_CGU_CGU_MUXCR_MUXI) {
+               /* MUX I set to 150 MHz clock */
+               return 150000000;
+       } else {
+               /* MUX I set to 100/133 MHz clock */
+               if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
+                       /* Division value is 1/3, maximum CPU operating */
+                       /* frequency is 133.3 MHz                       */
+                       return 133333333;
+               } else {
+                       /* Division value is 1/4, maximum CPU operating */
+                       /* frequency is 100 MHz                         */
+                       return 100000000;
+               }
+       }
+}
+
+/*******************************************************************************
+*
+* get_fpiclk - returns the frequency of the FPI bus.
+*
+* Gets the value directly from the INCA-IP hardware.
+*
+* RETURNS: Frquency in Hz
+*
+* NOTE:
+*   This functions should be used by the hardware driver to get the correct
+*   frequency of the CPU. Don't use the macros, which are set to init the CPU
+*   frequency in the ROM code.
+*   The calculation for the
+*/
+uint incaip_get_fpiclk (void)
+{
+       uint clkCPU;
+
+       clkCPU = incaip_get_cpuclk ();
+
+       switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
+       case 0x4:
+               return clkCPU >> 1;     /* devided by 2 */
+               break;
+       case 0x8:
+               return clkCPU >> 2;     /* devided by 4 */
+               break;
+       default:
+               return clkCPU;
+               break;
+       }
+}
+
+int incaip_set_cpuclk (void)
+{
+       extern void ebu_init(long);
+       extern void cgu_init(long);
+       extern void sdram_init(long);
+       char tmp[64];
+       ulong cpuclk;
+
+       if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
+               cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
+               cgu_init (cpuclk);
+               ebu_init (cpuclk);
+               sdram_init (cpuclk);
+       }
+
+       return 0;
+}
diff --git a/arch/mips/cpu/mips32/incaip/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S
new file mode 100644 (file)
index 0000000..3ade3cd
--- /dev/null
@@ -0,0 +1,71 @@
+/*
+ *  INCA-IP Watchdog timer management code.
+ *
+ *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <asm/regdef.h>
+
+
+#define WD_BASE            0xb8000000
+#define WD_CON0(value)     0x0020(value)
+#define WD_CON1(value)     0x0024(value)
+#define WD_DISABLE         0x00000008
+#define WD_ENABLE          0x00000000
+#define WD_WRITE_PW        0xFFFC00F8
+#define WD_WRITE_ENDINIT   0xFFFC00F3
+#define WD_WRITE_INIT      0xFFFC00F2
+
+
+       .globl  disable_incaip_wdt
+disable_incaip_wdt:
+       li      t0, WD_BASE
+
+       /* Calculate password.
+        */
+       lw      t2, WD_CON1(t0)
+       and     t2, 0xC
+
+       lw      t3, WD_CON0(t0)
+       and     t3, 0xFFFFFF01
+
+       or      t3, t2
+       or      t3, 0xF0
+
+       sw      t3, WD_CON0(t0)         /* write password */
+
+       /* Clear ENDINIT.
+        */
+       li      t1, WD_WRITE_INIT
+       sw      t1, WD_CON0(t0)
+
+
+       li      t1, WD_DISABLE
+       sw      t1, WD_CON1(t0)         /* disable watchdog */
+       li      t1, WD_WRITE_PW
+       sw      t1, WD_CON0(t0)         /* write password */
+       li      t1, WD_WRITE_ENDINIT
+       sw      t1, WD_CON0(t0)         /* end command */
+
+       jr      ra
+       nop
diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/mips32/interrupts.c
new file mode 100644 (file)
index 0000000..87f7a9f
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+       return 0;
+}
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S
new file mode 100644 (file)
index 0000000..e661d46
--- /dev/null
@@ -0,0 +1,390 @@
+/*
+ *  Startup Code for MIPS32 CPU-core
+ *
+ *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+       /*
+        * For the moment disable interrupts, mark the kernel mode and
+        * set ST0_KX so that the CPU does not spit fire when using
+        * 64-bit addresses.
+        */
+       .macro  setup_c0_status set clr
+       .set    push
+       mfc0    t0, CP0_STATUS
+       or      t0, ST0_CU0 | \set | 0x1f | \clr
+       xor     t0, 0x1f | \clr
+       mtc0    t0, CP0_STATUS
+       .set    noreorder
+       sll     zero, 3                         # ehb
+       .set    pop
+       .endm
+
+       .macro  setup_c0_status_reset
+#ifdef CONFIG_64BIT
+       setup_c0_status ST0_KX 0
+#else
+       setup_c0_status 0 0
+#endif
+       .endm
+
+#define RVECENT(f,n) \
+   b f; nop
+#define XVECENT(f,bev) \
+   b f     ;           \
+   li k0,bev
+
+       .set noreorder
+
+       .globl _start
+       .text
+_start:
+       RVECENT(reset,0)        /* U-boot entry point */
+       RVECENT(reset,1)        /* software reboot */
+#if defined(CONFIG_INCA_IP)
+       .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+       .word 0x00000000           /* phase of the flash                    */
+#else
+       RVECENT(romReserved,2)
+#endif
+       RVECENT(romReserved,3)
+       RVECENT(romReserved,4)
+       RVECENT(romReserved,5)
+       RVECENT(romReserved,6)
+       RVECENT(romReserved,7)
+       RVECENT(romReserved,8)
+       RVECENT(romReserved,9)
+       RVECENT(romReserved,10)
+       RVECENT(romReserved,11)
+       RVECENT(romReserved,12)
+       RVECENT(romReserved,13)
+       RVECENT(romReserved,14)
+       RVECENT(romReserved,15)
+       RVECENT(romReserved,16)
+       RVECENT(romReserved,17)
+       RVECENT(romReserved,18)
+       RVECENT(romReserved,19)
+       RVECENT(romReserved,20)
+       RVECENT(romReserved,21)
+       RVECENT(romReserved,22)
+       RVECENT(romReserved,23)
+       RVECENT(romReserved,24)
+       RVECENT(romReserved,25)
+       RVECENT(romReserved,26)
+       RVECENT(romReserved,27)
+       RVECENT(romReserved,28)
+       RVECENT(romReserved,29)
+       RVECENT(romReserved,30)
+       RVECENT(romReserved,31)
+       RVECENT(romReserved,32)
+       RVECENT(romReserved,33)
+       RVECENT(romReserved,34)
+       RVECENT(romReserved,35)
+       RVECENT(romReserved,36)
+       RVECENT(romReserved,37)
+       RVECENT(romReserved,38)
+       RVECENT(romReserved,39)
+       RVECENT(romReserved,40)
+       RVECENT(romReserved,41)
+       RVECENT(romReserved,42)
+       RVECENT(romReserved,43)
+       RVECENT(romReserved,44)
+       RVECENT(romReserved,45)
+       RVECENT(romReserved,46)
+       RVECENT(romReserved,47)
+       RVECENT(romReserved,48)
+       RVECENT(romReserved,49)
+       RVECENT(romReserved,50)
+       RVECENT(romReserved,51)
+       RVECENT(romReserved,52)
+       RVECENT(romReserved,53)
+       RVECENT(romReserved,54)
+       RVECENT(romReserved,55)
+       RVECENT(romReserved,56)
+       RVECENT(romReserved,57)
+       RVECENT(romReserved,58)
+       RVECENT(romReserved,59)
+       RVECENT(romReserved,60)
+       RVECENT(romReserved,61)
+       RVECENT(romReserved,62)
+       RVECENT(romReserved,63)
+       XVECENT(romExcHandle,0x200)     /* bfc00200: R4000 tlbmiss vector */
+       RVECENT(romReserved,65)
+       RVECENT(romReserved,66)
+       RVECENT(romReserved,67)
+       RVECENT(romReserved,68)
+       RVECENT(romReserved,69)
+       RVECENT(romReserved,70)
+       RVECENT(romReserved,71)
+       RVECENT(romReserved,72)
+       RVECENT(romReserved,73)
+       RVECENT(romReserved,74)
+       RVECENT(romReserved,75)
+       RVECENT(romReserved,76)
+       RVECENT(romReserved,77)
+       RVECENT(romReserved,78)
+       RVECENT(romReserved,79)
+       XVECENT(romExcHandle,0x280)     /* bfc00280: R4000 xtlbmiss vector */
+       RVECENT(romReserved,81)
+       RVECENT(romReserved,82)
+       RVECENT(romReserved,83)
+       RVECENT(romReserved,84)
+       RVECENT(romReserved,85)
+       RVECENT(romReserved,86)
+       RVECENT(romReserved,87)
+       RVECENT(romReserved,88)
+       RVECENT(romReserved,89)
+       RVECENT(romReserved,90)
+       RVECENT(romReserved,91)
+       RVECENT(romReserved,92)
+       RVECENT(romReserved,93)
+       RVECENT(romReserved,94)
+       RVECENT(romReserved,95)
+       XVECENT(romExcHandle,0x300)     /* bfc00300: R4000 cache vector */
+       RVECENT(romReserved,97)
+       RVECENT(romReserved,98)
+       RVECENT(romReserved,99)
+       RVECENT(romReserved,100)
+       RVECENT(romReserved,101)
+       RVECENT(romReserved,102)
+       RVECENT(romReserved,103)
+       RVECENT(romReserved,104)
+       RVECENT(romReserved,105)
+       RVECENT(romReserved,106)
+       RVECENT(romReserved,107)
+       RVECENT(romReserved,108)
+       RVECENT(romReserved,109)
+       RVECENT(romReserved,110)
+       RVECENT(romReserved,111)
+       XVECENT(romExcHandle,0x380)     /* bfc00380: R4000 general vector */
+       RVECENT(romReserved,113)
+       RVECENT(romReserved,114)
+       RVECENT(romReserved,115)
+       RVECENT(romReserved,116)
+       RVECENT(romReserved,116)
+       RVECENT(romReserved,118)
+       RVECENT(romReserved,119)
+       RVECENT(romReserved,120)
+       RVECENT(romReserved,121)
+       RVECENT(romReserved,122)
+       RVECENT(romReserved,123)
+       RVECENT(romReserved,124)
+       RVECENT(romReserved,125)
+       RVECENT(romReserved,126)
+       RVECENT(romReserved,127)
+
+       /* We hope there are no more reserved vectors!
+        * 128 * 8 == 1024 == 0x400
+        * so this is address R_VEC+0x400 == 0xbfc00400
+        */
+       .align 4
+reset:
+
+       /* Clear watch registers.
+        */
+       mtc0    zero, CP0_WATCHLO
+       mtc0    zero, CP0_WATCHHI
+
+       /* WP(Watch Pending), SW0/1 should be cleared. */
+       mtc0    zero, CP0_CAUSE
+
+       setup_c0_status_reset
+
+       /* Init Timer */
+       mtc0    zero, CP0_COUNT
+       mtc0    zero, CP0_COMPARE
+
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
+       /* CONFIG0 register */
+       li      t0, CONF_CM_UNCACHED
+       mtc0    t0, CP0_CONFIG
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
+
+       /* Initialize $gp.
+        */
+       bal     1f
+       nop
+       .word   _gp
+1:
+       lw      gp, 0(ra)
+
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
+       /* Initialize any external memory.
+        */
+       la      t9, lowlevel_init
+       jalr    t9
+       nop
+
+       /* Initialize caches...
+        */
+       la      t9, mips_cache_reset
+       jalr    t9
+       nop
+
+       /* ... and enable them.
+        */
+       li      t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
+
+       /* Set up temporary stack.
+        */
+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
+       li      a0, CONFIG_SYS_INIT_SP_OFFSET
+       la      t9, mips_cache_lock
+       jalr    t9
+       nop
+#endif
+
+       li      t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+       la      sp, 0(t0)
+
+       la      t9, board_init_f
+       jr      t9
+       nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+       .globl  relocate_code
+       .ent    relocate_code
+relocate_code:
+       move    sp, a0          /* Set new stack pointer        */
+
+       li      t0, CONFIG_SYS_MONITOR_BASE
+       la      t3, in_ram
+       lw      t2, -12(t3)     /* t2 <-- uboot_end_data        */
+       move    t1, a2
+       move    s2, a2          /* s2 <-- destination address   */
+
+       /*
+        * Fix $gp:
+        *
+        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+        */
+       move    t6, gp
+       sub     gp, CONFIG_SYS_MONITOR_BASE
+       add     gp, a2          /* gp now adjusted              */
+       sub     s1, gp, t6      /* s1 <-- relocation offset     */
+
+       /*
+        * t0 = source address
+        * t1 = target address
+        * t2 = source end address
+        */
+
+       /*
+        * Save destination address and size for later usage in flush_cache()
+        */
+       move    s0, a1          /* save gd in s0                */
+       move    a0, t1          /* a0 <-- destination addr      */
+       sub     a1, t2, t0      /* a1 <-- size                  */
+
+1:
+       lw      t3, 0(t0)
+       sw      t3, 0(t1)
+       addu    t0, 4
+       ble     t0, t2, 1b
+       addu    t1, 4           /* delay slot                   */
+
+       /* If caches were enabled, we would have to flush them here.
+        */
+
+       /* a0 & a1 are already set up for flush_cache(start, size) */
+       la      t9, flush_cache
+       jalr    t9
+       nop
+
+       /* Jump to where we've relocated ourselves.
+        */
+       addi    t0, s2, in_ram - _start
+       jr      t0
+       nop
+
+       .word   _gp
+       .word   _GLOBAL_OFFSET_TABLE_
+       .word   uboot_end_data
+       .word   uboot_end
+       .word   num_got_entries
+
+in_ram:
+       /*
+        * Now we want to update GOT.
+        *
+        * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+        * generated by GNU ld. Skip these reserved entries from relocation.
+        */
+       lw      t3, -4(t0)      /* t3 <-- num_got_entries       */
+       lw      t4, -16(t0)     /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
+       lw      t5, -20(t0)     /* t5 <-- _gp   */
+       sub     t4, t5          /* compute offset*/
+       add     t4, t4, gp      /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
+       addi    t4, t4, 8       /* Skipping first two entries.  */
+       li      t2, 2
+1:
+       lw      t1, 0(t4)
+       beqz    t1, 2f
+       add     t1, s1
+       sw      t1, 0(t4)
+2:
+       addi    t2, 1
+       blt     t2, t3, 1b
+       addi    t4, 4           /* delay slot                   */
+
+       /* Clear BSS.
+        */
+       lw      t1, -12(t0)     /* t1 <-- uboot_end_data        */
+       lw      t2, -8(t0)      /* t2 <-- uboot_end             */
+       add     t1, s1          /* adjust pointers              */
+       add     t2, s1
+
+       sub     t1, 4
+1:
+       addi    t1, 4
+       bltl    t1, t2, 1b
+       sw      zero, 0(t1)     /* delay slot                   */
+
+       move    a0, s0          /* a0 <-- gd                    */
+       la      t9, board_init_r
+       jr      t9
+       move    a1, s2          /* delay slot                   */
+
+       .end    relocate_code
+
+       /* Exception handlers.
+        */
+romReserved:
+       b       romReserved
+
+romExcHandle:
+       b       romExcHandle
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
deleted file mode 100644 (file)
index d6bcef6..0000000
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- *  Startup Code for MIPS32 CPU-core
- *
- *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-       /*
-        * For the moment disable interrupts, mark the kernel mode and
-        * set ST0_KX so that the CPU does not spit fire when using
-        * 64-bit addresses.
-        */
-       .macro  setup_c0_status set clr
-       .set    push
-       mfc0    t0, CP0_STATUS
-       or      t0, ST0_CU0 | \set | 0x1f | \clr
-       xor     t0, 0x1f | \clr
-       mtc0    t0, CP0_STATUS
-       .set    noreorder
-       sll     zero, 3                         # ehb
-       .set    pop
-       .endm
-
-       .macro  setup_c0_status_reset
-#ifdef CONFIG_64BIT
-       setup_c0_status ST0_KX 0
-#else
-       setup_c0_status 0 0
-#endif
-       .endm
-
-#define RVECENT(f,n) \
-   b f; nop
-#define XVECENT(f,bev) \
-   b f     ;           \
-   li k0,bev
-
-       .set noreorder
-
-       .globl _start
-       .text
-_start:
-       RVECENT(reset,0)        /* U-boot entry point */
-       RVECENT(reset,1)        /* software reboot */
-#if defined(CONFIG_INCA_IP)
-       .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
-       .word 0x00000000           /* phase of the flash                    */
-#elif defined(CONFIG_PURPLE)
-       .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
-       .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
-#else
-       RVECENT(romReserved,2)
-#endif
-       RVECENT(romReserved,3)
-       RVECENT(romReserved,4)
-       RVECENT(romReserved,5)
-       RVECENT(romReserved,6)
-       RVECENT(romReserved,7)
-       RVECENT(romReserved,8)
-       RVECENT(romReserved,9)
-       RVECENT(romReserved,10)
-       RVECENT(romReserved,11)
-       RVECENT(romReserved,12)
-       RVECENT(romReserved,13)
-       RVECENT(romReserved,14)
-       RVECENT(romReserved,15)
-       RVECENT(romReserved,16)
-       RVECENT(romReserved,17)
-       RVECENT(romReserved,18)
-       RVECENT(romReserved,19)
-       RVECENT(romReserved,20)
-       RVECENT(romReserved,21)
-       RVECENT(romReserved,22)
-       RVECENT(romReserved,23)
-       RVECENT(romReserved,24)
-       RVECENT(romReserved,25)
-       RVECENT(romReserved,26)
-       RVECENT(romReserved,27)
-       RVECENT(romReserved,28)
-       RVECENT(romReserved,29)
-       RVECENT(romReserved,30)
-       RVECENT(romReserved,31)
-       RVECENT(romReserved,32)
-       RVECENT(romReserved,33)
-       RVECENT(romReserved,34)
-       RVECENT(romReserved,35)
-       RVECENT(romReserved,36)
-       RVECENT(romReserved,37)
-       RVECENT(romReserved,38)
-       RVECENT(romReserved,39)
-       RVECENT(romReserved,40)
-       RVECENT(romReserved,41)
-       RVECENT(romReserved,42)
-       RVECENT(romReserved,43)
-       RVECENT(romReserved,44)
-       RVECENT(romReserved,45)
-       RVECENT(romReserved,46)
-       RVECENT(romReserved,47)
-       RVECENT(romReserved,48)
-       RVECENT(romReserved,49)
-       RVECENT(romReserved,50)
-       RVECENT(romReserved,51)
-       RVECENT(romReserved,52)
-       RVECENT(romReserved,53)
-       RVECENT(romReserved,54)
-       RVECENT(romReserved,55)
-       RVECENT(romReserved,56)
-       RVECENT(romReserved,57)
-       RVECENT(romReserved,58)
-       RVECENT(romReserved,59)
-       RVECENT(romReserved,60)
-       RVECENT(romReserved,61)
-       RVECENT(romReserved,62)
-       RVECENT(romReserved,63)
-       XVECENT(romExcHandle,0x200)     /* bfc00200: R4000 tlbmiss vector */
-       RVECENT(romReserved,65)
-       RVECENT(romReserved,66)
-       RVECENT(romReserved,67)
-       RVECENT(romReserved,68)
-       RVECENT(romReserved,69)
-       RVECENT(romReserved,70)
-       RVECENT(romReserved,71)
-       RVECENT(romReserved,72)
-       RVECENT(romReserved,73)
-       RVECENT(romReserved,74)
-       RVECENT(romReserved,75)
-       RVECENT(romReserved,76)
-       RVECENT(romReserved,77)
-       RVECENT(romReserved,78)
-       RVECENT(romReserved,79)
-       XVECENT(romExcHandle,0x280)     /* bfc00280: R4000 xtlbmiss vector */
-       RVECENT(romReserved,81)
-       RVECENT(romReserved,82)
-       RVECENT(romReserved,83)
-       RVECENT(romReserved,84)
-       RVECENT(romReserved,85)
-       RVECENT(romReserved,86)
-       RVECENT(romReserved,87)
-       RVECENT(romReserved,88)
-       RVECENT(romReserved,89)
-       RVECENT(romReserved,90)
-       RVECENT(romReserved,91)
-       RVECENT(romReserved,92)
-       RVECENT(romReserved,93)
-       RVECENT(romReserved,94)
-       RVECENT(romReserved,95)
-       XVECENT(romExcHandle,0x300)     /* bfc00300: R4000 cache vector */
-       RVECENT(romReserved,97)
-       RVECENT(romReserved,98)
-       RVECENT(romReserved,99)
-       RVECENT(romReserved,100)
-       RVECENT(romReserved,101)
-       RVECENT(romReserved,102)
-       RVECENT(romReserved,103)
-       RVECENT(romReserved,104)
-       RVECENT(romReserved,105)
-       RVECENT(romReserved,106)
-       RVECENT(romReserved,107)
-       RVECENT(romReserved,108)
-       RVECENT(romReserved,109)
-       RVECENT(romReserved,110)
-       RVECENT(romReserved,111)
-       XVECENT(romExcHandle,0x380)     /* bfc00380: R4000 general vector */
-       RVECENT(romReserved,113)
-       RVECENT(romReserved,114)
-       RVECENT(romReserved,115)
-       RVECENT(romReserved,116)
-       RVECENT(romReserved,116)
-       RVECENT(romReserved,118)
-       RVECENT(romReserved,119)
-       RVECENT(romReserved,120)
-       RVECENT(romReserved,121)
-       RVECENT(romReserved,122)
-       RVECENT(romReserved,123)
-       RVECENT(romReserved,124)
-       RVECENT(romReserved,125)
-       RVECENT(romReserved,126)
-       RVECENT(romReserved,127)
-
-       /* We hope there are no more reserved vectors!
-        * 128 * 8 == 1024 == 0x400
-        * so this is address R_VEC+0x400 == 0xbfc00400
-        */
-#ifdef CONFIG_PURPLE
-/* 0xbfc00400 */
-       .word   0xdc870000
-       .word   0xfca70000
-       .word   0x20840008
-       .word   0x20a50008
-       .word   0x20c6ffff
-       .word   0x14c0fffa
-       .word   0x00000000
-       .word   0x03e00008
-       .word   0x00000000
-       .word   0x00000000
-/* 0xbfc00428 */
-       .word   0xdc870000
-       .word   0xfca70000
-       .word   0x20840008
-       .word   0x20a50008
-       .word   0x20c6ffff
-       .word   0x14c0fffa
-       .word   0x00000000
-       .word   0x03e00008
-       .word   0x00000000
-       .word   0x00000000
-#endif /* CONFIG_PURPLE */
-       .align 4
-reset:
-
-       /* Clear watch registers.
-        */
-       mtc0    zero, CP0_WATCHLO
-       mtc0    zero, CP0_WATCHHI
-
-       /* WP(Watch Pending), SW0/1 should be cleared. */
-       mtc0    zero, CP0_CAUSE
-
-       setup_c0_status_reset
-
-       /* Init Timer */
-       mtc0    zero, CP0_COUNT
-       mtc0    zero, CP0_COMPARE
-
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
-       /* CONFIG0 register */
-       li      t0, CONF_CM_UNCACHED
-       mtc0    t0, CP0_CONFIG
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
-
-       /* Initialize $gp.
-        */
-       bal     1f
-       nop
-       .word   _gp
-1:
-       lw      gp, 0(ra)
-
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
-       /* Initialize any external memory.
-        */
-       la      t9, lowlevel_init
-       jalr    t9
-       nop
-
-       /* Initialize caches...
-        */
-       la      t9, mips_cache_reset
-       jalr    t9
-       nop
-
-       /* ... and enable them.
-        */
-       li      t0, CONF_CM_CACHABLE_NONCOHERENT
-       mtc0    t0, CP0_CONFIG
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
-
-       /* Set up temporary stack.
-        */
-#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
-       li      a0, CONFIG_SYS_INIT_SP_OFFSET
-       la      t9, mips_cache_lock
-       jalr    t9
-       nop
-#endif
-
-       li      t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       la      sp, 0(t0)
-
-       la      t9, board_init_f
-       jr      t9
-       nop
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * a0 = addr_sp
- * a1 = gd
- * a2 = destination address
- */
-       .globl  relocate_code
-       .ent    relocate_code
-relocate_code:
-       move    sp, a0          /* Set new stack pointer        */
-
-       li      t0, CONFIG_SYS_MONITOR_BASE
-       la      t3, in_ram
-       lw      t2, -12(t3)     /* t2 <-- uboot_end_data        */
-       move    t1, a2
-       move    s2, a2          /* s2 <-- destination address   */
-
-       /*
-        * Fix $gp:
-        *
-        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-        */
-       move    t6, gp
-       sub     gp, CONFIG_SYS_MONITOR_BASE
-       add     gp, a2          /* gp now adjusted              */
-       sub     s1, gp, t6      /* s1 <-- relocation offset     */
-
-       /*
-        * t0 = source address
-        * t1 = target address
-        * t2 = source end address
-        */
-
-       /*
-        * Save destination address and size for later usage in flush_cache()
-        */
-       move    s0, a1          /* save gd in s0                */
-       move    a0, t1          /* a0 <-- destination addr      */
-       sub     a1, t2, t0      /* a1 <-- size                  */
-
-       /* On the purple board we copy the code earlier in a special way
-        * in order to solve flash problems
-        */
-#ifndef CONFIG_PURPLE
-1:
-       lw      t3, 0(t0)
-       sw      t3, 0(t1)
-       addu    t0, 4
-       ble     t0, t2, 1b
-       addu    t1, 4           /* delay slot                   */
-#endif
-
-       /* If caches were enabled, we would have to flush them here.
-        */
-
-       /* a0 & a1 are already set up for flush_cache(start, size) */
-       la      t9, flush_cache
-       jalr    t9
-       nop
-
-       /* Jump to where we've relocated ourselves.
-        */
-       addi    t0, s2, in_ram - _start
-       jr      t0
-       nop
-
-       .word   _gp
-       .word   _GLOBAL_OFFSET_TABLE_
-       .word   uboot_end_data
-       .word   uboot_end
-       .word   num_got_entries
-
-in_ram:
-       /*
-        * Now we want to update GOT.
-        *
-        * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
-        * generated by GNU ld. Skip these reserved entries from relocation.
-        */
-       lw      t3, -4(t0)      /* t3 <-- num_got_entries       */
-       lw      t4, -16(t0)     /* t4 <-- _GLOBAL_OFFSET_TABLE_ */
-       lw      t5, -20(t0)     /* t5 <-- _gp   */
-       sub     t4, t5          /* compute offset*/
-       add     t4, t4, gp      /* t4 now holds relocated _GLOBAL_OFFSET_TABLE_ */
-       addi    t4, t4, 8       /* Skipping first two entries.  */
-       li      t2, 2
-1:
-       lw      t1, 0(t4)
-       beqz    t1, 2f
-       add     t1, s1
-       sw      t1, 0(t4)
-2:
-       addi    t2, 1
-       blt     t2, t3, 1b
-       addi    t4, 4           /* delay slot                   */
-
-       /* Clear BSS.
-        */
-       lw      t1, -12(t0)     /* t1 <-- uboot_end_data        */
-       lw      t2, -8(t0)      /* t2 <-- uboot_end             */
-       add     t1, s1          /* adjust pointers              */
-       add     t2, s1
-
-       sub     t1, 4
-1:
-       addi    t1, 4
-       bltl    t1, t2, 1b
-       sw      zero, 0(t1)     /* delay slot                   */
-
-       move    a0, s0          /* a0 <-- gd                    */
-       la      t9, board_init_r
-       jr      t9
-       move    a1, s2          /* delay slot                   */
-
-       .end    relocate_code
-
-       /* Exception handlers.
-        */
-romReserved:
-       b       romReserved
-
-romExcHandle:
-       b       romExcHandle
index e787a1dee656906fc29712fd7bd1ba74aa06e9c4..26f100290c0f483c5df4235cfb6c9cd6a3f3ee35 100644 (file)
 /*  Module      :  EBU register address and bits                       */
 /***********************************************************************/
 
-#if defined(CONFIG_INCA_IP)
 #define INCA_IP_EBU                          (0xB8000200)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_EBU                          (0xB800D800)
-#endif
-
 /***********************************************************************/
 
 
@@ -1495,12 +1490,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not
 /*  Module      :  ASC register address and bits                       */
 /***********************************************************************/
 
-#if defined(CONFIG_INCA_IP)
 #define INCA_IP_ASC                          (0xB8000400)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_ASC                          (0xBE500000)
-#endif
-
 /***********************************************************************/
 
 
index f3171241556a9e3ae59eb3b4058d1379cfa00146..623c4d7f0d58a2ee0018c3dbecfdf2ed07c51e04 100644 (file)
@@ -162,9 +162,6 @@ void board_init_f(ulong bootflag)
        init_fnc_t **init_fnc_ptr;
        ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_SYS_MONITOR_BASE;
        ulong *s;
-#ifdef CONFIG_PURPLE
-       void copy_code (ulong);
-#endif
 
        /* Pointer is writable since we allocated a register for it.
         */
@@ -253,13 +250,6 @@ void board_init_f(ulong bootflag)
 
        memcpy (id, (void *)gd, sizeof (gd_t));
 
-       /* On the purple board we copy the code in a special way
-        * in order to solve flash problems
-        */
-#ifdef CONFIG_PURPLE
-       copy_code(addr);
-#endif
-
        relocate_code (addr_sp, id, addr);
 
        /* NOTREACHED - relocate_code() does not return */
diff --git a/board/purple/Makefile b/board/purple/Makefile
deleted file mode 100644 (file)
index 10e566d..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(BOARD).o
-
-COBJS  = $(BOARD).o flash.o sconsole.o
-SOBJS  = lowlevel_init.o
-
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
-
-$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
-       $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/purple/config.mk b/board/purple/config.mk
deleted file mode 100644 (file)
index 404c3fb..0000000
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Purple board with MIPS 5Kc CPU core
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xB0000000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80100000
diff --git a/board/purple/flash.c b/board/purple/flash.c
deleted file mode 100644 (file)
index 5cee35e..0000000
+++ /dev/null
@@ -1,595 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/inca-ip.h>
-
-flash_info_t   flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-
-#define        FLASH_ID_MASK   0xFFFFFFFF
-
-#define FPW    FLASH_PORT_WIDTH
-#define FPWV   FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#define FLASH29_REG_ADRS(reg) ((FPWV *)PHYS_FLASH_1 + (reg))
-
-/* FLASH29 command register addresses */
-
-#define FLASH29_REG_FIRST_CYCLE                FLASH29_REG_ADRS (0x1555)
-#define FLASH29_REG_SECOND_CYCLE       FLASH29_REG_ADRS (0x2aaa)
-#define FLASH29_REG_THIRD_CYCLE                FLASH29_REG_ADRS (0x3555)
-#define        FLASH29_REG_FOURTH_CYCLE        FLASH29_REG_ADRS (0x4555)
-#define        FLASH29_REG_FIFTH_CYCLE         FLASH29_REG_ADRS (0x5aaa)
-#define        FLASH29_REG_SIXTH_CYCLE         FLASH29_REG_ADRS (0x6555)
-
-/* FLASH29 command definitions */
-
-#define        FLASH29_CMD_FIRST               0xaaaaaaaa
-#define        FLASH29_CMD_SECOND              0x55555555
-#define        FLASH29_CMD_FOURTH              0xaaaaaaaa
-#define        FLASH29_CMD_FIFTH               0x55555555
-#define        FLASH29_CMD_SIXTH               0x10101010
-
-#define        FLASH29_CMD_SECTOR              0x30303030
-#define        FLASH29_CMD_PROGRAM             0xa0a0a0a0
-#define        FLASH29_CMD_CHIP_ERASE          0x80808080
-#define        FLASH29_CMD_READ_RESET          0xf0f0f0f0
-#define        FLASH29_CMD_AUTOSELECT          0x90909090
-#define FLASH29_CMD_READ               0x70707070
-
-#define IN_RAM_CMD_READ                0x1
-#define IN_RAM_CMD_WRITE       0x2
-
-#define FLASH_WRITE_CMD        ((ulong)(flash_write_cmd) & 0x7)+0xbf008000
-#define FLASH_READ_CMD  ((ulong)(flash_read_cmd) & 0x7)+0xbf008000
-
-typedef void (*FUNCPTR_CP)(ulong *source, ulong *destination, ulong nlongs);
-typedef void (*FUNCPTR_RD)(int cmd, FPWV * pFA, char * string, int strLen);
-typedef void (*FUNCPTR_WR)(int cmd, FPWV * pFA, FPW value);
-
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static int write_word(flash_info_t *info, FPWV *dest, FPW data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
-
-static void load_cmd(ulong cmd);
-static ulong in_ram_cmd = 0;
-
-
-/******************************************************************************
-*
-* Don't change the program architecture
-* This architecture assure the program
-* can be relocated to scratch ram
-*/
-static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
-{
-       int i,j;
-       FPW temp,temp1;
-       FPWV *str;
-
-       str = (FPWV *)string;
-
-       j=  strLen/4;
-
-       if(cmd == FLASH29_CMD_AUTOSELECT)
-          {
-           *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
-           *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
-           *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_AUTOSELECT;
-          }
-
-       if(cmd == FLASH29_CMD_READ)
-          {
-           i = 0;
-           while(i<j)
-           {
-               temp = *pFA++;
-               temp1 = *(int *)0xa0000000;
-               *(int *)0xbf0081f8 = temp1 + temp;
-               *str++ = temp;
-               i++;
-           }
-          }
-
-        if(cmd == FLASH29_CMD_READ_RESET)
-        {
-           *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
-           *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
-           *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_READ_RESET;
-        }
-
-       *(int *)0xbf0081f8 = *(int *)0xa0000000;        /* dummy read switch back to sdram interface */
-}
-
-/******************************************************************************
-*
-* Don't change the program architecture
-* This architecture assure the program
-* can be relocated to scratch ram
-*/
-static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
-{
-       *(FLASH29_REG_FIRST_CYCLE)  = FLASH29_CMD_FIRST;
-       *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
-
-       if (cmd == FLASH29_CMD_SECTOR)
-          {
-           *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_CHIP_ERASE;
-           *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
-           *(FLASH29_REG_FIFTH_CYCLE)  = FLASH29_CMD_FIFTH;
-           *pFA                        = FLASH29_CMD_SECTOR;
-          }
-
-       if (cmd == FLASH29_CMD_SIXTH)
-          {
-           *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_CHIP_ERASE;
-           *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
-           *(FLASH29_REG_FIFTH_CYCLE)  = FLASH29_CMD_FIFTH;
-           *(FLASH29_REG_SIXTH_CYCLE)  = FLASH29_CMD_SIXTH;
-          }
-
-       if (cmd == FLASH29_CMD_PROGRAM)
-          {
-           *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_PROGRAM;
-           *pFA = value;
-          }
-
-       if (cmd == FLASH29_CMD_READ_RESET)
-          {
-           *(FLASH29_REG_THIRD_CYCLE)  = FLASH29_CMD_READ_RESET;
-          }
-
-       *(int *)0xbf0081f8 = *(int *)0xa0000000;        /* dummy read switch back to sdram interface */
-}
-
-static void load_cmd(ulong cmd)
-{
-       ulong *src;
-       ulong *dst;
-       FUNCPTR_CP absEntry;
-       ulong func;
-
-       if (in_ram_cmd & cmd) return;
-
-       if (cmd == IN_RAM_CMD_READ)
-       {
-               func = (ulong)flash_read_cmd;
-       }
-       else
-       {
-               func = (ulong)flash_write_cmd;
-       }
-
-       src = (ulong *)(func & 0xfffffff8);
-       dst = (ulong *)0xbf008000;
-       absEntry = (FUNCPTR_CP)(0xbf0081d0);
-       absEntry(src,dst,0x38);
-
-       in_ram_cmd = cmd;
-}
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-       unsigned long size = 0;
-       int i;
-
-       load_cmd(IN_RAM_CMD_READ);
-
-       /* Init: no FLASHes known */
-       for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-               ulong flashbase = PHYS_FLASH_1;
-               ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
-
-               /* Disable write protection */
-               *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
-
-#if 1
-               memset(&flash_info[i], 0, sizeof(flash_info_t));
-#endif
-
-               flash_info[i].size =
-                       flash_get_size((FPW *)flashbase, &flash_info[i]);
-
-               if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-                       printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
-                       i, flash_info[i].size);
-               }
-
-               size += flash_info[i].size;
-       }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_SYS_MONITOR_BASE,
-                     CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-                     flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-       /* ENV protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_ENV_ADDR,
-                     CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-                     flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-       return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-       int i;
-
-       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
-                && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM160B) {
-
-               int bootsect_size[4];   /* number of bytes/boot sector  */
-               int sect_size;          /* number of bytes/regular sector */
-
-               bootsect_size[0] = 0x00008000;
-               bootsect_size[1] = 0x00004000;
-               bootsect_size[2] = 0x00004000;
-               bootsect_size[3] = 0x00010000;
-               sect_size =        0x00020000;
-
-               /* set sector offsets for bottom boot block type        */
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base;
-                       base += i < 4 ? bootsect_size[i] : sect_size;
-               }
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-       int i;
-       flash_info_t * info;
-
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
-               info = & flash_info[i];
-               if (info->start[0] <= base && base < info->start[0] + info->size)
-                       break;
-       }
-
-       return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-       int i;
-       uchar *boottype;
-       uchar *bootletter;
-       char *fmt;
-       uchar botbootletter[] = "B";
-       uchar topbootletter[] = "T";
-       uchar botboottype[] = "bottom boot sector";
-       uchar topboottype[] = "top boot sector";
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_AMD:     printf ("AMD ");                break;
-       case FLASH_MAN_BM:      printf ("BRIGHT MICRO ");       break;
-       case FLASH_MAN_FUJ:     printf ("FUJITSU ");            break;
-       case FLASH_MAN_SST:     printf ("SST ");                break;
-       case FLASH_MAN_STM:     printf ("STM ");                break;
-       case FLASH_MAN_INTEL:   printf ("INTEL ");              break;
-       default:                printf ("Unknown Vendor ");     break;
-       }
-
-       /* check for top or bottom boot, if it applies */
-       if (info->flash_id & FLASH_BTYPE) {
-               boottype = botboottype;
-               bootletter = botbootletter;
-       }
-       else {
-               boottype = topboottype;
-               bootletter = topbootletter;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM160B:
-               fmt = "29LV160B%s (16 Mbit, %s)\n";
-               break;
-       case FLASH_28F800C3B:
-       case FLASH_28F800C3T:
-               fmt = "28F800C3%s (8 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL800B:
-       case FLASH_INTEL800T:
-               fmt = "28F800B3%s (8 Mbit, %s)\n";
-               break;
-       case FLASH_28F160C3B:
-       case FLASH_28F160C3T:
-               fmt = "28F160C3%s (16 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL160B:
-       case FLASH_INTEL160T:
-               fmt = "28F160B3%s (16 Mbit, %s)\n";
-               break;
-       case FLASH_28F320C3B:
-       case FLASH_28F320C3T:
-               fmt = "28F320C3%s (32 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL320B:
-       case FLASH_INTEL320T:
-               fmt = "28F320B3%s (32 Mbit, %s)\n";
-               break;
-       case FLASH_28F640C3B:
-       case FLASH_28F640C3T:
-               fmt = "28F640C3%s (64 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL640B:
-       case FLASH_INTEL640T:
-               fmt = "28F640B3%s (64 Mbit, %s)\n";
-               break;
-       default:
-               fmt = "Unknown Chip Type\n";
-               break;
-       }
-
-       printf (fmt, bootletter, boottype);
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20,
-               info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-
-       for (i=0; i<info->sector_count; ++i) {
-               if ((i % 5) == 0) {
-                       printf ("\n   ");
-               }
-
-               printf (" %08lX%s", info->start[i],
-                       info->protect[i] ? " (RO)" : "     ");
-       }
-
-       printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-       FUNCPTR_RD absEntry;
-       FPW retValue;
-       int flag;
-
-       load_cmd(IN_RAM_CMD_READ);
-       absEntry = (FUNCPTR_RD)FLASH_READ_CMD;
-
-       flag = disable_interrupts();
-       absEntry(FLASH29_CMD_AUTOSELECT,0,0,0);
-       if (flag) enable_interrupts();
-
-       udelay(100);
-
-       flag = disable_interrupts();
-       absEntry(FLASH29_CMD_READ, addr + 1, (char *)&retValue, sizeof(retValue));
-       absEntry(FLASH29_CMD_READ_RESET,0,0,0);
-       if (flag) enable_interrupts();
-
-       udelay(100);
-
-       switch (retValue) {
-
-       case (FPW)AMD_ID_LV160B:
-               info->flash_id += FLASH_AM160B;
-               info->sector_count = 35;
-               info->size = 0x00400000;
-               break;                          /* => 8 or 16 MB        */
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               return (0);                     /* => no or unknown flash */
-       }
-
-       flash_get_offsets((ulong)addr, info);
-
-       return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int    flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-       FPWV *addr;
-       int flag, prot, sect;
-       ulong start, now, last;
-       FUNCPTR_WR absEntry;
-
-       load_cmd(IN_RAM_CMD_WRITE);
-       absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM160B:
-               break;
-       case FLASH_UNKNOWN:
-       default:
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect=s_first; sect<=s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf ("- Warning: %d protected sectors will not be erased!\n",
-                       prot);
-       } else {
-               printf ("\n");
-       }
-
-       last  = get_timer(0);
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect<=s_last; sect++) {
-
-               if (info->protect[sect] != 0)   /* protected, skip it */
-                       continue;
-
-               /* Disable interrupts which might cause a timeout here */
-               flag = disable_interrupts();
-
-               addr = (FPWV *)(info->start[sect]);
-               absEntry(FLASH29_CMD_SECTOR, addr, 0);
-
-               /* re-enable interrupts if necessary */
-               if (flag)
-                       enable_interrupts();
-
-               start = get_timer(0);
-
-               while ((now = get_timer(start)) <= CONFIG_SYS_FLASH_ERASE_TOUT) {
-
-                       /* show that we're waiting */
-                       if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
-                               putc ('.');
-                               last = get_timer(0);
-                       }
-               }
-
-               flag = disable_interrupts();
-               absEntry(FLASH29_CMD_READ_RESET,0,0);
-               if (flag)
-                       enable_interrupts();
-       }
-
-       printf (" done\n");
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
-    int bytes;   /* number of bytes to program in current word         */
-    int left;    /* number of bytes left to program                    */
-    int i, res;
-
-    for (left = cnt, res = 0;
-        left > 0 && res == 0;
-        addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-       bytes = addr & (sizeof(data) - 1);
-       addr &= ~(sizeof(data) - 1);
-
-       /* combine source and destination data so can program
-        * an entire word of 16 or 32 bits
-        */
-       for (i = 0; i < sizeof(data); i++) {
-           data <<= 8;
-           if (i < bytes || i - bytes >= left )
-               data += *((uchar *)addr + i);
-           else
-               data += *src++;
-       }
-
-       res = write_word(info, (FPWV *)addr, data);
-    }
-
-    return (res);
-}
-
-static int write_word (flash_info_t *info, FPWV *dest, FPW data)
-{
-    int res = 0;       /* result, assume success       */
-    FUNCPTR_WR absEntry;
-    int flag;
-
-    /* Check if Flash is (sufficiently) erased */
-    if ((*dest & data) != data) {
-       return (2);
-    }
-
-    if (info->start[0] != PHYS_FLASH_1)
-    {
-       return (3);
-    }
-
-    load_cmd(IN_RAM_CMD_WRITE);
-    absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
-
-    flag = disable_interrupts();
-    absEntry(FLASH29_CMD_PROGRAM,dest,data);
-    if (flag) enable_interrupts();
-
-    udelay(100);
-
-    flag = disable_interrupts();
-    absEntry(FLASH29_CMD_READ_RESET,0,0);
-    if (flag) enable_interrupts();
-
-    return (res);
-}
diff --git a/board/purple/lowlevel_init.S b/board/purple/lowlevel_init.S
deleted file mode 100644 (file)
index 1bd3edb..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  Memory sub-system initialization code for PURPLE development board.
- *
- *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-
-#define MC_IOGP        0xBF800800
-
-       .globl  lowlevel_init
-lowlevel_init:
-       li      t0, MC_IOGP
-       li      t1, 0xf24
-       sw      t1, 0(t0)
-       jr      ra
-       nop
diff --git a/board/purple/purple.c b/board/purple/purple.c
deleted file mode 100644 (file)
index 4e9e700..0000000
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/inca-ip.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#include "sconsole.h"
-
-#define cache_unroll(base,op)          \
-       __asm__ __volatile__("          \
-               .set noreorder;         \
-               .set mips3;             \
-               cache %1, (%0);         \
-               .set mips0;             \
-               .set reorder"           \
-               :                       \
-               : "r" (base),           \
-                 "i" (op));
-
-typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs);
-
-extern void    asc_serial_init         (void);
-extern void    asc_serial_putc         (char);
-extern void    asc_serial_puts         (const char *);
-extern int     asc_serial_getc         (void);
-extern int     asc_serial_tstc         (void);
-extern void    asc_serial_setbrg       (void);
-
-void _machine_restart(void)
-{
-       void (*f)(void) = (void *) 0xbfc00000;
-
-       f();
-}
-
-static void sdram_timing_init (ulong size)
-{
-       register uint pass;
-       register uint done;
-       register uint count;
-       register uint p0, p1, p2, p3, p4;
-       register uint addr;
-
-#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3;
-#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3;
-
-       done = 0;
-       p0 = 2;
-       while (p0 < 4 && done == 0) {
-           p1 = 0;
-           while (p1 < 2 && done == 0) {
-               p2 = 0;
-               while (p2 < 2 && done == 0) {
-                   p3 = 0;
-                   while (p3 < 16 && done == 0) {
-                       count = 0;
-                       p4 = 0;
-                       while (p4 < 32 && done == 0) {
-                           WRITE_MC_IOGP_1;
-
-                           for (addr = CKSEG1 + 0x4000;
-                                addr < CKSEG1ADDR (size);
-                                addr = addr + 4) {
-                                       *(uint *) addr = 0xaa55aa55;
-                           }
-
-                           pass = 1;
-
-                           for (addr = CKSEG1 + 0x4000;
-                                addr < CKSEG1ADDR (size) && pass == 1;
-                                addr = addr + 4) {
-                                       if (*(uint *) addr != 0xaa55aa55)
-                                               pass = 0;
-                           }
-
-                           if (pass == 1) {
-                               count++;
-                           } else {
-                               count = 0;
-                           }
-
-                           if (count == 32) {
-                               WRITE_MC_IOGP_2;
-                               done = 1;
-                           }
-                           p4++;
-                       }
-                       p3++;
-                   }
-                   p2++;
-               }
-               p1++;
-           }
-           p0++;
-           if (p0 == 1)
-               p0++;
-       }
-}
-
-phys_size_t initdram(int board_type)
-{
-       /* The only supported number of SDRAM banks is 4.
-        */
-#define CONFIG_SYS_NB  4
-
-       ulong   cfgpb0  = *INCA_IP_SDRAM_MC_CFGPB0;
-       ulong   cfgdw   = *INCA_IP_SDRAM_MC_CFGDW;
-       int     cols    = cfgpb0 & 0xF;
-       int     rows    = (cfgpb0 & 0xF0) >> 4;
-       int     dw      = cfgdw & 0xF;
-       ulong   size    = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
-       void (*  sdram_init) (ulong);
-
-       sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
-
-       sdram_init(0x10000);
-
-       return size;
-}
-
-int checkboard (void)
-{
-
-       unsigned long chipid = *(unsigned long *)0xB800C800;
-
-       printf ("Board: Purple PLB 2800 chip version %ld, ", chipid & 0xF);
-
-       printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
-
-       set_io_port_base(0);
-
-       return 0;
-}
-
-int misc_init_r (void)
-{
-       asc_serial_init ();
-
-       sconsole_putc   = asc_serial_putc;
-       sconsole_puts   = asc_serial_puts;
-       sconsole_getc   = asc_serial_getc;
-       sconsole_tstc   = asc_serial_tstc;
-       sconsole_setbrg = asc_serial_setbrg;
-
-       sconsole_flush ();
-       return (0);
-}
-
-/*******************************************************************************
-*
-* copydwords - copy one buffer to another a long at a time
-*
-* This routine copies the first <nlongs> longs from <source> to <destination>.
-*/
-static void copydwords (ulong *source, ulong *destination, ulong nlongs)
-{
-       ulong temp,temp1;
-       ulong *dstend = destination + nlongs;
-
-       while (destination < dstend) {
-               temp = *source++;
-               /* dummy read from sdram */
-               temp1 = *(ulong *)0xa0000000;
-               /* avoid optimization from compliler */
-               *(ulong *)0xbf0081f8 = temp1 + temp;
-               *destination++ = temp;
-
-       }
-}
-
-/*******************************************************************************
-*
-* copyLongs - copy one buffer to another a long at a time
-*
-* This routine copies the first <nlongs> longs from <source> to <destination>.
-*/
-static void copyLongs (ulong *source, ulong *destination, ulong nlongs)
-{
-       FUNCPTR absEntry;
-
-       absEntry = (FUNCPTR)(0xbf008000+((ulong)copydwords & 0x7));
-       absEntry(source, destination, nlongs);
-}
-
-/*******************************************************************************
-*
-* programLoad - load program into ram
-*
-* This routine load copydwords into ram
-*
-*/
-static void programLoad(void)
-{
-       FUNCPTR absEntry;
-       ulong *src,*dst;
-
-       src = (ulong *)(CONFIG_SYS_TEXT_BASE + 0x428);
-       dst = (ulong *)0xbf0081d0;
-
-       absEntry = (FUNCPTR)(CONFIG_SYS_TEXT_BASE + 0x400);
-       absEntry(src,dst,0x6);
-
-       src = (ulong *)((ulong)copydwords & 0xfffffff8);
-       dst = (ulong *)0xbf008000;
-
-       absEntry(src,dst,0x38);
-}
-
-/*******************************************************************************
-*
-* copy_code - copy u-boot image from flash to RAM
-*
-* This routine is needed to solve flash problems on this board
-*
-*/
-void copy_code (ulong dest_addr)
-{
-       extern long uboot_end_data;
-       unsigned long start;
-       unsigned long end;
-
-       /* load copydwords into ram
-        */
-       programLoad();
-
-       /* copy u-boot code
-        */
-       copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
-                 (ulong *)dest_addr,
-                 ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
-
-
-       /* flush caches
-        */
-
-       start = CKSEG0;
-       end = start + CONFIG_SYS_DCACHE_SIZE;
-       while(start < end) {
-               cache_unroll(start,Index_Writeback_Inv_D);
-               start += CONFIG_SYS_CACHELINE_SIZE;
-       }
-
-       start = CKSEG0;
-       end = start + CONFIG_SYS_ICACHE_SIZE;
-       while(start < end) {
-               cache_unroll(start,Index_Invalidate_I);
-               start += CONFIG_SYS_CACHELINE_SIZE;
-       }
-}
-
-#ifdef CONFIG_PLB2800_ETHER
-int board_eth_init(bd_t *bis)
-{
-       return plb2800_eth_initialize(bis);
-}
-#endif
diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c
deleted file mode 100644 (file)
index cd9d871..0000000
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-
-#include "sconsole.h"
-
-void   (*sconsole_putc) (char) = 0;
-void   (*sconsole_puts) (const char *) = 0;
-int    (*sconsole_getc) (void) = 0;
-int    (*sconsole_tstc) (void) = 0;
-void   (*sconsole_setbrg) (void) = 0;
-
-int serial_init (void)
-{
-       sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
-       sb->pos  = 0;
-       sb->size = 0;
-       sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
-
-       return (0);
-}
-
-void serial_putc (char c)
-{
-       if (sconsole_putc) {
-               (*sconsole_putc) (c);
-       } else {
-               sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
-               if (c) {
-                       sb->data[sb->pos++] = c;
-                       if (sb->pos == sb->max_size) {
-                               sb->pos = 0;
-                       }
-                       if (sb->size < sb->max_size) {
-                               sb->size++;
-                       }
-               }
-       }
-}
-
-void serial_puts (const char *s)
-{
-       if (sconsole_puts) {
-               (*sconsole_puts) (s);
-       } else {
-               sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-
-               while (*s) {
-                       sb->data[sb->pos++] = *s++;
-                       if (sb->pos == sb->max_size) {
-                               sb->pos = 0;
-                       }
-                       if (sb->size < sb->max_size) {
-                               sb->size++;
-                       }
-               }
-       }
-}
-
-int serial_getc (void)
-{
-       if (sconsole_getc) {
-               return (*sconsole_getc) ();
-       } else {
-               return 0;
-       }
-}
-
-int serial_tstc (void)
-{
-       if (sconsole_tstc) {
-               return (*sconsole_tstc) ();
-       } else {
-               return 0;
-       }
-}
-
-void serial_setbrg (void)
-{
-       if (sconsole_setbrg) {
-               (*sconsole_setbrg) ();
-       }
-}
-
-void sconsole_flush (void)
-{
-       if (sconsole_putc) {
-               sconsole_buffer_t *sb = SCONSOLE_BUFFER;
-               unsigned int end = sb->pos < sb->size
-                               ? sb->pos + sb->max_size - sb->size
-                               : sb->pos - sb->size;
-
-               while (sb->size) {
-                       (*sconsole_putc) (sb->data[end++]);
-                       if (end == sb->max_size) {
-                               end = 0;
-                       }
-                       sb->size--;
-               }
-       }
-}
diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h
deleted file mode 100644 (file)
index baed5fb..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SCONSOLE_H_
-#define _SCONSOLE_H_
-
-#include <config.h>
-
-typedef struct sconsole_buffer_s {
-       unsigned long size;
-       unsigned long max_size;
-       unsigned long pos;
-       char data[1];
-} sconsole_buffer_t;
-
-#define SCONSOLE_BUFFER                ((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
-
-extern void    (* sconsole_putc)       (char);
-extern void    (* sconsole_puts)       (const char *);
-extern int     (* sconsole_getc)       (void);
-extern int     (* sconsole_tstc)       (void);
-extern void    (* sconsole_setbrg)     (void);
-
-extern void    sconsole_flush          (void);
-
-#endif
diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds
deleted file mode 100644 (file)
index 719f268..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
-       . = 0x00000000;
-
-       . = ALIGN(4);
-       .text       :
-       {
-         arch/mips/cpu/start.o         (.text)
-         board/purple/lowlevel_init.o  (.text)
-         . = DEFINED(env_offset) ? env_offset : .;
-         common/env_embedded.o (.ppcenv)
-
-         *(.text)
-       }
-
-       . = ALIGN(4);
-       .rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-       . = ALIGN(4);
-       .data  : { *(.data) }
-
-       . = .;
-       _gp = ALIGN(16) + 0x7ff0;
-
-       .got : {
-         __got_start = .;
-         *(.got)
-         __got_end = .;
-       }
-
-       .sdata  : { *(.sdata) }
-
-       .u_boot_cmd : {
-         __u_boot_cmd_start = .;
-         *(.u_boot_cmd)
-         __u_boot_cmd_end = .;
-       }
-
-       uboot_end_data = .;
-       num_got_entries = (__got_end - __got_start) >> 2;
-
-       . = ALIGN(4);
-       .sbss (NOLOAD)  : { *(.sbss) }
-       .bss (NOLOAD)  : { *(.bss) . = ALIGN(4); }
-       uboot_end = .;
-}
index a96e7cf5f560cc5e19a345caeaec23e2a36aeb35..d25f3f2392786e6590317a6ad0b589c4e435b1bb 100644 (file)
@@ -217,32 +217,31 @@ M5282EVB                     m68k        mcf52x2     m5282evb            freesca
 M53017EVB                    m68k        mcf52x2     m53017evb           freescale
 EP2500                       m68k        mcf52x2     ep2500              Mercury
 microblaze-generic           microblaze  microblaze  microblaze-generic  xilinx
-dbau1000                     mips        mips        dbau1x00            -              -           dbau1x00:DBAU1000
-dbau1100                     mips        mips        dbau1x00            -              -           dbau1x00:DBAU1100
-dbau1500                     mips        mips        dbau1x00            -              -           dbau1x00:DBAU1500
-dbau1550                     mips        mips        dbau1x00            -              -           dbau1x00:DBAU1550
-dbau1550_el                  mips        mips        dbau1x00            -              -           dbau1x00:DBAU1550
-gth2                         mips        mips
-incaip                       mips        mips
-incaip_100MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=100000000
-incaip_133MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=133000000
-incaip_150MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=150000000
-pb1000                       mips        mips        pb1x00              -              -           pb1x00:PB1000
-purple                       mips        mips
-qemu_mips                    mips        mips        qemu-mips           -              -           qemu-mips
-tb0229                       mips        mips
-vct_premium                  mips        mips        vct                 micronas       -           vct:VCT_PREMIUM
-vct_premium_small            mips        mips        vct                 micronas       -           vct:VCT_PREMIUM,VCT_SMALL_IMAGE
-vct_premium_onenand          mips        mips        vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND
-vct_premium_onenand_small    mips        mips        vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
-vct_platinum                 mips        mips        vct                 micronas       -           vct:VCT_PLATINUM
-vct_platinum_small           mips        mips        vct                 micronas       -           vct:VCT_PLATINUM,VCT_SMALL_IMAGE
-vct_platinum_onenand         mips        mips        vct                 micronas       -           vct:VCT_PLATINUM,VCT_ONENAND
-vct_platinum_onenand_small   mips        mips        vct                 micronas       -           vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE
-vct_platinumavc              mips        mips        vct                 micronas       -           vct:VCT_PLATINUMAVC
-vct_platinumavc_small        mips        mips        vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
-vct_platinumavc_onenand      mips        mips        vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
-vct_platinumavc_onenand_small mips       mips        vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
+dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
+dbau1100                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1100
+dbau1500                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1500
+dbau1550                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+dbau1550_el                  mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+gth2                         mips        mips32      -                   -              au1x00
+incaip                       mips        mips32      incaip              -              incaip
+incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
+incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
+incaip_150MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=150000000
+pb1000                       mips        mips32      pb1x00              -              au1x00      pb1x00:PB1000
+qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips
+tb0229                       mips        mips32
+vct_premium                  mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM
+vct_premium_small            mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_SMALL_IMAGE
+vct_premium_onenand          mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND
+vct_premium_onenand_small    mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
+vct_platinum                 mips        mips32      vct                 micronas       -           vct:VCT_PLATINUM
+vct_platinum_small           mips        mips32      vct                 micronas       -           vct:VCT_PLATINUM,VCT_SMALL_IMAGE
+vct_platinum_onenand         mips        mips32      vct                 micronas       -           vct:VCT_PLATINUM,VCT_ONENAND
+vct_platinum_onenand_small   mips        mips32      vct                 micronas       -           vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE
+vct_platinumavc              mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC
+vct_platinumavc_small        mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
+vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
+vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
 EVB64260                     powerpc     74xx_7xx    evb64260            -              -           EVB64260
index 1e6cd6af27491467870ad76cc61d7c631a8a277f..6963e6dcc89458f92a4c6f2148d5c019aed29972 100644 (file)
@@ -1346,31 +1346,6 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
        unsigned long *capacity, *blksz;
        ccb *pccb = &usb_ccb;
 
-       /* for some reasons a couple of devices would not survive this reset */
-       if (
-           /* Sony USM256E */
-           (dev->descriptor.idVendor == 0x054c &&
-            dev->descriptor.idProduct == 0x019e)
-           ||
-           /* USB007 Mini-USB2 Flash Drive */
-           (dev->descriptor.idVendor == 0x066f &&
-            dev->descriptor.idProduct == 0x2010)
-           ||
-           /* SanDisk Corporation Cruzer Micro 20044318410546613953 */
-           (dev->descriptor.idVendor == 0x0781 &&
-            dev->descriptor.idProduct == 0x5151)
-           ||
-           /*
-            * SanDisk Corporation U3 Cruzer Micro 1/4GB
-            * Flash Drive 000016244373FFB4
-            */
-           (dev->descriptor.idVendor == 0x0781 &&
-            dev->descriptor.idProduct == 0x5406)
-           )
-               USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n");
-       else
-               ss->transport_reset(ss);
-
        pccb->pdata = usb_stor_buf;
 
        dev_desc->target = dev->devnum;
diff --git a/doc/README.Purple b/doc/README.Purple
deleted file mode 100644 (file)
index 0098e26..0000000
+++ /dev/null
@@ -1,84 +0,0 @@
-Installation Instructions:
---------------------------
-
-1. Put the s2 switch into the following position:
-
-       Off On
-       ------
-       |x   |
-       |   x|
-       |x   |
-       |   X|
-       ------
-
-   Put the s3 switch into the following position:
-
-       Off On
-       ------
-       | x  |
-       | x  |
-       |   x|
-       |   x|
-       ------
-
-   Put the s4 switch into the following position:
-
-       Off On
-       ------
-       |x   |
-       |x   |
-       |x   |
-       |x   |
-       |x   |
-       |   x|
-       |   x|
-       |x   |
-       ------
-
-2. Connect to the serial console and to the BDI. Power on. On the
-   serial line, you should see:
-
-       PURPLE@1.2>
-
-3. Type '8'. No echo will be displayed. In response, you should get:
-
-       7A(pass)
-
-4. From BDI, enter command:
-
-       mmw 0xb800d860 0x0042c7ff
-
-5. Then, from BDI:
-
-       erase 0xB0000000
-       erase 0xB0008000
-       erase 0xB000C000
-       erase 0xB0010000
-       erase 0xB0020000
-
-       prog 0xB0000000 <u-boot.bin> bin
-
-6. Power off. Restore the original S2 switch position:
-
-       Off On
-       ------
-       |   x|
-       |   x|
-       |x   |
-       |   X|
-       ------
-
-   Power on.  U-Boot should come up.
-
-
-Implementation Notes:
----------------------
-
-Due to the RAM/flash bus arbitration problem the suggested workaround
-had to be implemented. It works okay. On the downside is that you
-can't really check whether 'erase' is complete by polling flash as it
-is usually done. Instead, the flash driver simply waits for a given
-time and assumes that erase then has passed. This behaviour is
-identical to what the VxWorks driver does; also, the same timeout (6
-seconds) was chosen. Note that this timeout applies for each erase
-operation, i. e. per erased sector.
index bf490b0d32cd45062b29da4b4e201f86a0e2ea46..4abe5e3b59a56946515ee1fff790d713d3973f3b 100644 (file)
@@ -28,8 +28,9 @@
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
        /* Please add supported PCI EHCI controller ids here */
-       {0x1033, 0x00E0},
-       {0x10b9, 0x5239},       /* ULI1575 PCI EHCI module ids */
+       {0x1033, 0x00E0},       /* NEC */
+       {0x10B9, 0x5239},       /* ULI1575 PCI EHCI module ids */
+       {0x12D8, 0x400F},       /* Pericom */
        {0, 0}
 };
 #endif
index 38aceb2e93d32a2a0d49dee2076d0eb55fae2b1f..35268ba58ef00b1c18e18ccecd7f0b0c85e3f0b9 100644 (file)
 
 #include "musb_core.h"
 
+#ifndef CONFIG_USB_BLACKFIN_CLKIN
+#define CONFIG_USB_BLACKFIN_CLKIN 24
+#endif
+
 /* MUSB platform configuration */
 struct musb_config musb_cfg = {
        .regs       = (struct musb_regs *)USB_FADDR,
@@ -93,10 +97,25 @@ static void __def_musb_init(void)
 }
 void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
 
-int musb_platform_init(void)
+static void bfin_anomaly_init(void)
 {
-       /* board specific initialization */
-       board_musb_init();
+       u32 revid;
+
+       if (!ANOMALY_05000346 && !ANOMALY_05000347)
+               return;
+
+       revid = bfin_revid();
+
+#ifdef __ADSPBF54x__
+       if (revid > 0)
+               return;
+#endif
+#ifdef __ADSPBF52x__
+       if (ANOMALY_BF526 && revid > 0)
+               return;
+       if (ANOMALY_BF527 && revid > 1)
+               return;
+#endif
 
        if (ANOMALY_05000346) {
                bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
@@ -107,9 +126,18 @@ int musb_platform_init(void)
                bfin_write_USB_APHY_CNTRL(0x0);
                SSYNC();
        }
+}
+
+int musb_platform_init(void)
+{
+       /* board specific initialization */
+       board_musb_init();
+
+       bfin_anomaly_init();
 
        /* Configure PLL oscillator register */
-       bfin_write_USB_PLLOSC_CTRL(0x30a8);
+       bfin_write_USB_PLLOSC_CTRL(0x3080 |
+               ((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1));
        SSYNC();
 
        bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
index a75e4f258aa1ec768f28d3fe3f8ac2a1bcc9a87d..c450bf6924431ba5d399ec3423fb854b2a4a64ea 100644 (file)
@@ -209,7 +209,7 @@ static __u32 get_fatent (fsdata *mydata, __u32 entry)
 
        /* Read a new block of FAT entries into the cache. */
        if (bufnum != mydata->fatbufnum) {
-               int getsize = FATBUFSIZE / FS_BLOCK_SIZE;
+               __u32 getsize = FATBUFSIZE / FS_BLOCK_SIZE;
                __u8 *bufptr = mydata->fatbuf;
                __u32 fatlength = mydata->fatlength;
                __u32 startblock = bufnum * FATBUFBLOCKS;
@@ -279,7 +279,7 @@ static int
 get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer,
             unsigned long size)
 {
-       int idx = 0;
+       __u32 idx = 0;
        __u32 startsect;
 
        if (clustnum > 0) {
@@ -767,12 +767,13 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
        dir_entry *dentptr;
        __u16 prevcksum = 0xffff;
        char *subname = "";
-       int cursect;
+       __u32 cursect;
        int idx, isdir = 0;
        int files = 0, dirs = 0;
        long ret = 0;
        int firsttime;
-       int root_cluster;
+       __u32 root_cluster;
+       int rootdir_size = 0;
        int j;
 
        if (read_bootsectandvi(&bs, &volinfo, &mydata->fatsize)) {
@@ -798,8 +799,6 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
                mydata->data_begin = mydata->rootdir_sect -
                                        (mydata->clust_size * 2);
        } else {
-               int rootdir_size;
-
                rootdir_size = ((bs.dir_entries[1]  * (int)256 +
                                 bs.dir_entries[0]) *
                                 sizeof(dir_entry)) /
@@ -1006,20 +1005,18 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
                 * root directory clusters when a cluster has been
                 * completely processed.
                 */
-               if ((mydata->fatsize == 32) && (++j == mydata->clust_size)) {
-                       int nxtsect;
-                       int nxt_clust;
+               ++j;
+               int fat32_end = 0;
+               if ((mydata->fatsize == 32) && (j == mydata->clust_size)) {
+                       int nxtsect = 0;
+                       int nxt_clust = 0;
 
                        nxt_clust = get_fatent(mydata, root_cluster);
+                       fat32_end = CHECK_CLUST(nxt_clust, 32);
 
                        nxtsect = mydata->data_begin +
                                (nxt_clust * mydata->clust_size);
 
-                       debug("END LOOP: sect=%d, root_clust=%d, "
-                             "n_sect=%d, n_clust=%d\n",
-                             cursect, root_cluster,
-                             nxtsect, nxt_clust);
-
                        root_cluster = nxt_clust;
 
                        cursect = nxtsect;
@@ -1027,6 +1024,18 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize,
                } else {
                        cursect++;
                }
+
+               /* If end of rootdir reached */
+               if ((mydata->fatsize == 32 && fat32_end) ||
+                   (mydata->fatsize != 32 && j == rootdir_size)) {
+                       if (dols == LS_ROOT) {
+                               printf("\n%d file(s), %d dir(s)\n\n",
+                                      files, dirs);
+                               return 0;
+                       } else {
+                               return -1;
+                       }
+               }
        }
 rootdir_done:
 
diff --git a/include/configs/purple.h b/include/configs/purple.h
deleted file mode 100644 (file)
index 25d8ebe..0000000
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the PURPLE board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32          1       /* MIPS 5Kc CPU core    */
-#define CONFIG_PURPLE          1       /* on a PURPLE Board    */
-
-#define CPU_CLOCK_RATE 125000000   /* 125 MHz clock for the MIPS core */
-#define ASC_CLOCK_RATE  62500000   /* 62.5 MHz ASC clock              */
-
-#define INFINEON_EBU_BOOTCFG   0xE0CC
-
-#define CONFIG_STACKSIZE       (128 * 1024)
-
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-
-#define CONFIG_BAUDRATE                19200
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
-
-#define        CONFIG_TIMESTAMP                /* Print image info with timestamp */
-
-#define CONFIG_PREBOOT "echo;" \
-       "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-       "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
-       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-               "nfsroot=${serverip}:${rootpath}\0"                     \
-       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-       "addip=setenv bootargs ${bootargs} "                            \
-               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
-               ":${hostname}:${netdev}:off\0"                          \
-       "addmisc=setenv bootargs ${bootargs} "                          \
-               "console=ttyS0,${baudrate} "                            \
-               "ethaddr=${ethaddr} "                                   \
-               "panic=1\0"                                             \
-       "flash_nfs=run nfsargs addip addmisc;"                          \
-               "bootm ${kernel_addr}\0"                                \
-       "flash_self=run ramargs addip addmisc;"                         \
-               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
-       "net_nfs=tftp 80500000 ${bootfile};"                            \
-               "run nfsargs addip addmisc;bootm\0"                     \
-       "rootpath=/opt/eldk/mips_5KC\0"                                 \
-       "bootfile=/tftpboot/purple/uImage\0"                            \
-       "kernel_addr=B0040000\0"                                        \
-       "ramdisk_addr=B0100000\0"                                       \
-       "u-boot=/tftpboot/purple/u-boot.bin\0"                          \
-       "load=tftp 80500000 ${u-boot}\0"                                \
-       "update=protect off 1:0-4;era 1:0-4;"                           \
-               "cp.b 80500000 B0000000 ${filesize}\0"                  \
-       ""
-#define CONFIG_BOOTCOMMAND     "run flash_self"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-
-#define CONFIG_SYS_SDRAM_BASE          0x80000000
-
-#define CONFIG_SYS_INIT_SP_OFFSET      0x400000
-
-#define CONFIG_SYS_MALLOC_LEN          128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN      128*1024
-
-/*
- * Miscellaneous configurable options
- */
-#define        CONFIG_SYS_LONGHELP                             /* undef to save memory      */
-#define        CONFIG_SYS_PROMPT               "PURPLE # "     /* Monitor Command Prompt    */
-#define        CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size   */
-#define        CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
-#define CONFIG_SYS_MIPS_TIMER_FREQ     (CPU_CLOCK_RATE/2)
-#define CONFIG_SYS_HZ                  1000
-#define        CONFIG_SYS_MAXARGS              16              /* max number of command args*/
-
-#define        CONFIG_SYS_LOAD_ADDR            0x80500000      /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START       0x80200000
-#define CONFIG_SYS_MEMTEST_END         0x80800000
-
-#define        CONFIG_MISC_INIT_R
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      (35)    /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1           0xb0000000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define        CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define        CONFIG_SYS_MONITOR_LEN          (192 << 10)
-
-#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (6 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (6 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define        CONFIG_ENV_IS_IN_FLASH  1
-
-/* Address and size of Primary Environment Sector      */
-#define CONFIG_ENV_ADDR                0xB0008000
-#define CONFIG_ENV_SIZE                0x4000
-
-#define CONFIG_FLASH_32BIT
-#define CONFIG_NR_DRAM_BANKS   1
-
-#define CONFIG_PLB2800_ETHER
-#define CONFIG_NET_MULTI
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
-/*
- * Temporary buffer for serial data until the real serial driver
- * is initialised (memtest will destroy this buffer)
- */
-#define CONFIG_SYS_SCONSOLE_ADDR     (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - \
-                              CONFIG_SYS_DCACHE_SIZE / 2)
-#define CONFIG_SYS_SCONSOLE_SIZE     (CONFIG_SYS_DCACHE_SIZE / 4)
-
-#endif /* __CONFIG_H */