]> git.sur5r.net Git - u-boot/commitdiff
ARM: keystone2: clock: add K2E clock support
authorHao Zhang <hzhang@ti.com>
Tue, 15 Jul 2014 21:59:23 +0000 (00:59 +0300)
committerTom Rini <trini@ti.com>
Fri, 25 Jul 2014 20:26:11 +0000 (16:26 -0400)
This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
arch/arm/cpu/armv7/keystone/Makefile
arch/arm/cpu/armv7/keystone/clock-k2e.c [new file with mode: 0644]
arch/arm/cpu/armv7/keystone/clock.c
arch/arm/cpu/armv7/keystone/cmd_clock.c
arch/arm/include/asm/arch-keystone/clock-k2e.h [new file with mode: 0644]
arch/arm/include/asm/arch-keystone/clock.h
include/configs/ks2_evm.h

index 74c516013acda61a36b4a0273fffa4f24be98993..f8519c040355f4202e4c701c3a710c96689051d9 100644 (file)
@@ -9,6 +9,7 @@ obj-y   += init.o
 obj-y  += psc.o
 obj-y  += clock.o
 obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
 obj-y  += cmd_clock.o
 obj-y  += cmd_mon.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
new file mode 100644 (file)
index 0000000..42092e1
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clock_defs.h>
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+       [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+       [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+       [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:       pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+       unsigned long mult = 1, prediv = 1, output_div = 2;
+       unsigned long ret;
+       u32 tmp, reg;
+
+       if (pll == CORE_PLL) {
+               ret = external_clk[sys_clk];
+               if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
+                       /* PLL mode */
+                       tmp = __raw_readl(KS2_MAINPLLCTL0);
+                       prediv = (tmp & PLL_DIV_MASK) + 1;
+                       mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
+                               (pllctl_reg_read(pll, mult) &
+                               PLLM_MULT_LO_MASK)) + 1;
+                       output_div = ((pllctl_reg_read(pll, secctl) >>
+                                      PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
+
+                       ret = ret / prediv / output_div * mult;
+               }
+       } else {
+               switch (pll) {
+               case PASS_PLL:
+                       ret = external_clk[pa_clk];
+                       reg = KS2_PASSPLLCTL0;
+                       break;
+               case DDR3_PLL:
+                       ret = external_clk[ddr3_clk];
+                       reg = KS2_DDR3APLLCTL0;
+                       break;
+               default:
+                       return 0;
+               }
+
+               tmp = __raw_readl(reg);
+
+               if (!(tmp & PLLCTL_BYPASS)) {
+                       /* Bypass disabled */
+                       prediv = (tmp & PLL_DIV_MASK) + 1;
+                       mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
+                       output_div = ((tmp >> PLL_CLKOD_SHIFT) &
+                                     PLL_CLKOD_MASK) + 1;
+                       ret = ((ret / prediv) * mult) / output_div;
+               }
+       }
+
+       return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+       switch (clk) {
+       case core_pll_clk:      return pll_freq_get(CORE_PLL);
+       case pass_pll_clk:      return pll_freq_get(PASS_PLL);
+       case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
+       case sys_clk0_1_clk:
+       case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
+       case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
+       case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
+       case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
+       case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
+       case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
+       case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
+       case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
+       case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
+       case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+       case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+       case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
+       case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
+       case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
+       case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
+       default:
+               break;
+       }
+
+       return 0;
+}
index 42b664b57625f0d30728be90dae7ed6c2c45ebd3..03c1d9f660fffcf29df7e25d999a97491f05f400 100644 (file)
@@ -106,6 +106,7 @@ void init_pll(const struct pll_init_data *data)
 
                tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
 
+#ifndef CONFIG_SOC_K2E
        } else if (data->pll == TETRIS_PLL) {
                bwadj = pllm >> 1;
                /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
@@ -156,6 +157,7 @@ void init_pll(const struct pll_init_data *data)
                 * only applicable for Kepler
                 */
                setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
+#endif
        } else {
                setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
                /*
index afd30f3853428cf78268e6040d071855b8cd5581..d97c95be11ddad8ff8b99cad1e1dafc91c5c24c6 100644 (file)
 #include <asm/arch/psc_defs.h>
 
 struct pll_init_data cmd_pll_data = {
-       .pll                    = MAIN_PLL,
-       .pll_m                  = 16,
-       .pll_d                  = 1,
-       .pll_od                 = 2,
+       .pll = MAIN_PLL,
+       .pll_m = 16,
+       .pll_d = 1,
+       .pll_od = 2,
 };
 
 int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
        if (strncmp(argv[1], "pa", 2) == 0)
                cmd_pll_data.pll = PASS_PLL;
+#ifndef CONFIG_SOC_K2E
        else if (strncmp(argv[1], "arm", 3) == 0)
                cmd_pll_data.pll = TETRIS_PLL;
+#endif
+#ifdef CONFIG_SOC_K2HK
        else if (strncmp(argv[1], "ddr3a", 5) == 0)
                cmd_pll_data.pll = DDR3A_PLL;
        else if (strncmp(argv[1], "ddr3b", 5) == 0)
                cmd_pll_data.pll = DDR3B_PLL;
+#else
+       else if (strncmp(argv[1], "ddr3", 4) == 0)
+               cmd_pll_data.pll = DDR3_PLL;
+#endif
        else
                goto pll_cmd_usage;
 
@@ -51,11 +58,20 @@ pll_cmd_usage:
        return cmd_usage(cmdtp);
 }
 
+#ifdef CONFIG_SOC_K2HK
 U_BOOT_CMD(
        pllset, 5,      0,      do_pll_cmd,
        "set pll multiplier and pre divider",
        "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
 );
+#endif
+#ifdef CONFIG_SOC_K2E
+U_BOOT_CMD(
+       pllset, 5,      0,      do_pll_cmd,
+       "set pll multiplier and pre divider",
+       "<pa|ddr3> <mult> <div> <OD>\n"
+);
+#endif
 
 int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
@@ -79,7 +95,12 @@ U_BOOT_CMD(
        getclk, 2,      0,      do_getclk_cmd,
        "get clock rate",
        "<clk index>\n"
-       "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
+#ifdef CONFIG_SOC_K2HK
+       "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
+#endif
+#ifdef CONFIG_SOC_K2E
+       "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
+#endif
 );
 
 int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
new file mode 100644 (file)
index 0000000..4147811
--- /dev/null
@@ -0,0 +1,68 @@
+/*
+ * K2E: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2E_H
+#define __ASM_ARCH_CLOCK_K2E_H
+
+enum ext_clk_e {
+       sys_clk,
+       alt_core_clk,
+       pa_clk,
+       ddr3_clk,
+       mcm_clk,
+       pcie_clk,
+       sgmii_clk,
+       xgmii_clk,
+       usb_clk,
+       ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+       core_pll_clk,
+       pass_pll_clk,
+       ddr3_pll_clk,
+       sys_clk0_clk,
+       sys_clk0_1_clk,
+       sys_clk0_2_clk,
+       sys_clk0_3_clk,
+       sys_clk0_4_clk,
+       sys_clk0_6_clk,
+       sys_clk0_8_clk,
+       sys_clk0_12_clk,
+       sys_clk0_24_clk,
+       sys_clk1_clk,
+       sys_clk1_3_clk,
+       sys_clk1_4_clk,
+       sys_clk1_6_clk,
+       sys_clk1_12_clk,
+       sys_clk2_clk,
+       sys_clk3_clk
+};
+
+#define KS2_CLK1_6     sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+       CORE_PLL,
+       PASS_PLL,
+       DDR3_PLL,
+};
+
+#define CORE_PLL_800   {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1000  {CORE_PLL, 20, 1, 2}
+#define CORE_PLL_1200  {CORE_PLL, 24, 1, 2}
+#define PASS_PLL_1000  {PASS_PLL, 20, 1, 2}
+#define DDR3_PLL_200   {DDR3_PLL, 4,  1, 2}
+#define DDR3_PLL_400   {DDR3_PLL, 16, 1, 4}
+#define DDR3_PLL_800   {DDR3_PLL, 16, 1, 2}
+#define DDR3_PLL_333   {DDR3_PLL, 20, 1, 6}
+
+#endif
index c7da3520c42a1c0527c20cf0eb44a128201e04f5..1513c76b6a0eca54199e2fc44c5443bf660d2b25 100644 (file)
 #include <asm/arch/clock-k2hk.h>
 #endif
 
+#ifdef CONFIG_SOC_K2E
+#include <asm/arch/clock-k2e.h>
+#endif
+
 #define MAIN_PLL CORE_PLL
 
 #include <asm/types.h>
index 29f0b9b621b37ce7698f398f8f83110853156e08..43db581c75deed9ceb00e9ae04eadda6abea0a4d 100644 (file)
@@ -80,7 +80,7 @@
 #define CONFIG_SPI_FLASH_STMICRO
 #define CONFIG_DAVINCI_SPI
 #define CONFIG_CMD_SPI
-#define CONFIG_SYS_SPI_CLK             clk_get_rate(KS2_LPSC_EMIF25_SPI)
+#define CONFIG_SYS_SPI_CLK             clk_get_rate(KS2_CLK1_6)
 #define CONFIG_SF_DEFAULT_SPEED                30000000
 #define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
 #define CONFIG_SYS_SPI0