addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
if (addr != FDT_ADDR_T_NONE) {
+#ifndef CONFIG_SPL_BUILD
if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS)
addr = simple_bus_translate(dev->parent, addr);
+#endif
}
return addr;
if (plat)
return 0;
- base = (struct s5p_gpio_bank *)fdtdec_get_addr(gd->fdt_blob,
- parent->of_offset, "reg");
+ base = (struct s5p_gpio_bank *)dev_get_addr(parent);
for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
node > 0;
node = fdt_next_subnode(blob, node), bank++) {
no_banks = SUNXI_GPIO_BANKS;
}
- ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
- parent->of_offset, "reg");
+ ctlr = (struct sunxi_gpio_reg *)dev_get_addr(parent);
for (bank = 0; bank < no_banks; bank++) {
struct sunxi_gpio_platdata *plat;
struct udevice *dev;
if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
return -EINVAL;
bank_count = len / 3 / sizeof(u32);
- ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
- parent->of_offset, "reg");
+ ctlr = (struct gpio_ctlr *)dev_get_addr(parent);
}
#endif
for (bank = 0; bank < bank_count; bank++) {
if (i2c_bus->is_highspeed) {
flags = PINMUX_FLAG_HS_MODE;
- i2c_bus->hsregs = (struct exynos5_hsi2c *)
- fdtdec_get_addr(blob, node, "reg");
+ i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
} else {
flags = 0;
- i2c_bus->regs = (struct s3c24x0_i2c *)
- fdtdec_get_addr(blob, node, "reg");
+ i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
}
i2c_bus->id = pinmux_decode_periph_id(blob, node);
i2c_bus->id = dev->seq;
i2c_bus->type = dev_get_driver_data(dev);
- i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev);
/*
* We don't have a binding for pinmux yet. Leave it out for now. So
fdt_addr_t addr;
/* try Processor Local Bus device first */
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = dev_get_addr(dev);
#ifdef CONFIG_PCI
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct arc_serial_platdata *plat = dev_get_platdata(dev);
DECLARE_GLOBAL_DATA_PTR;
- plat->reg = (struct arc_serial_regs *)fdtdec_get_addr(gd->fdt_blob,
- dev->of_offset, "reg");
+ plat->reg = (struct arc_serial_regs *)dev_get_addr(dev);
plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"clock-frequency", 0);
struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct s5p_serial_platdata *plat = dev->platdata;
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = dev_get_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
- plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg");
+ plat->regs = (struct dw_spi *)dev_get_addr(bus);
/* Use 500KHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
- plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
+ plat->regs = (struct exynos_spi *)dev_get_addr(bus);
plat->periph_id = pinmux_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
- addr = fdtdec_get_addr(blob, node, "reg");
+ addr = dev_get_addr(bus);
if (addr == FDT_ADDR_T_NONE) {
debug("DSPI: Can't get base address or size\n");
return -ENOMEM;
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
- plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
- plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
- plat->base = fdtdec_get_addr(blob, node, "reg");
+ plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
if (plat->periph_id == PERIPH_ID_NONE) {
const void *blob = gd->fdt_blob;
int node = bus->of_offset;
- plat->regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, "reg");
+ plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
/* FIXME: Use 250MHz as a suitable default */
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
timing[PARAM_CPCON], timing[PARAM_LFCON]);
}
-static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
+static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
const char *phy, *mode;
- config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ config->reg = (struct usb_ctlr *)dev_get_addr(dev);
mode = fdt_getprop(blob, node, "dr_mode", NULL);
if (mode) {
if (0 == strcmp(mode, "host"))
struct fdt_usb *priv = dev_get_priv(dev);
int ret;
- ret = fdt_decode_usb(gd->fdt_blob, dev->of_offset, priv);
+ ret = fdt_decode_usb(dev, priv);
if (ret)
return ret;
/*
* Get the base address for XHCI controller from the device node
*/
- plat->hcd_base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+ plat->hcd_base = dev_get_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
static int tegra_dp_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dp_plat *plat = dev_get_platdata(dev);
- const void *blob = gd->fdt_blob;
- plat->base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+ plat->base = dev_get_addr(dev);
return 0;
}