imx: mx7: psci: add system power off support

Add i.MX7 PSCI system power off support, linux
kernel can use "poweroff" command to power off
system via SNVS, PMIC power will be disabled.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c
index b26be89c787b4f7578f416fb50f988cb291ddbfb..d5db51165f9375ed406f0f08aa3831817d0330d2 100644 (file)
--- a/arch/arm/mach-imx/mx7/psci-mx7.c
+++ b/arch/arm/mach-imx/mx7/psci-mx7.c
@@ -26,6 +26,12 @@
 #define BP_SRC_A7RCR0_A7_CORE_RESET0   0
 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE  1
 
+#define SNVS_LPCR              0x38
+#define BP_SNVS_LPCR_DP_EN     0x20
+#define BP_SNVS_LPCR_TOP       0x40
+
+#define CCM_CCGR_SNVS          0x4250
+
 #define CCM_ROOT_WDOG          0xbb80
 #define CCM_CCGR_WDOG1         0x49c0
 
@@ -87,3 +93,15 @@ __secure void imx_system_reset(void)
        writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
        writew(WCR_WDE, &wdog->wcr);
 }
+
+__secure void imx_system_off(void)
+{
+       u32 val;
+
+       /* make sure SNVS clock is enabled */
+       writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
+
+       val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
+       val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
+       writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
+}

diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S
index e23db24ee9589518e81eed47a79dd85086705d59..bc2cd8ae9a5172b30f1528ffaf47d613e0de66a0 100644 (file)
--- a/arch/arm/mach-imx/mx7/psci.S
+++ b/arch/arm/mach-imx/mx7/psci.S
@@ -50,4 +50,11 @@ psci_system_reset:
 2:     wfi
        b 2b
 
+.globl psci_system_off
+psci_system_off:
+       bl      imx_system_off
+
+3:     wfi
+       b 3b
+
        .popsection