Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/RPXlite/*
- Remove board/RPXClassic/*
- Remove include/configs/RPXlite.h
- Remove include/configs/RPXClassic.h
- Clean-up defined(CONFIG_RPXCLASSIC)
- Move the entry from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
defined(CONFIG_MHPC) || \
defined(CONFIG_R360MPI) || \
defined(CONFIG_RMU) || \
- defined(CONFIG_RPXCLASSIC) || \
defined(CONFIG_RPXLITE) || \
defined(CONFIG_SPC1920) || \
defined(CONFIG_SPD823TS)
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
-#ifdef CONFIG_RPXCLASSIC
- rpxclassic_init ();
-#endif
-
#if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
rpxlite_init ();
#endif
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
-#ifdef CONFIG_RPXCLASSIC
- *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
- *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
-#endif
-
#ifdef CONFIG_RPXLITE
*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
-#elif defined(CONFIG_RPXCLASSIC)
- udelay (100000); /* wait 100 ms */
#endif
return 1;
#endif
#endif /* CONFIG_FADS */
-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
+#if defined(CONFIG_RPXLITE)
/* Enable Monitor Port Transceiver */
*((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
#endif /* CONFIG_RPXLITE */
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = RPXClassic.o flash.o eccx.o
+++ /dev/null
-# Porting U-Boot onto RPXClassic LF_BW31 board
-# Written by Pierre AUBERT
-# E-Mail p.aubert@staubli.com
-# Stäubli Faverges - <www.staubli.com>
-#
-# Sept. 20 2001
-#
-# Cross compile: Montavista Hardhat ported on HP-UX 10.20
-#
-
-Flash memories : AM29DL323B (2 banks flash memories) 16 Mb from 0xff000000
-DRAM : 16 Mb from 0
-NVRAM : 512 kb from 0xfa000000
-
-
-- environment is stored in NVRAM
-- Mac address is read from EEPROM
-- ethernet on SCC1 or fast ethernet on FEC are running (depending on the
- configuration flag CONFIG_FEC_ENET)
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- * U-Boot port on RPXClassic LF (CLLF_BW31) board
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <config.h>
-#include <mpc8xx.h>
-#include <net.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-static unsigned char aschex_to_byte (unsigned char *cp);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFCC25
-
-const uint sdram_table[] =
-{
- /*
- * Single Read. (Offset 00h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
- 0x3FBFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Read. (Offset 08h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
- 0x3FBFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
- 0x3FFFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Write. (Offset 20h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
- 0x0CFFCC00, 0x33FFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /*
- * Refresh. (Offset 30h in UPMA RAM)
- */
- 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
- 0x3FFFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Exception. (Offset 3Ch in UPMA RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: RPXClassic\n");
- return (0);
-}
-
-/*-----------------------------------------------------------------------------
- * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
- *-----------------------------------------------------------------------------
- */
-static void board_get_enetaddr(uchar *enet)
-{
- int i;
- char buff[256], *cp;
-
- /* Initialize I2C */
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- /* Read 256 bytes in EEPROM */
- i2c_read (0x54, 0, 1, (uchar *)buff, 128);
- i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
-
- /* Retrieve MAC address in buffer (key EA) */
- for (cp = buff;;) {
- if (cp[0] == 'E' && cp[1] == 'A') {
- cp += 3;
- /* Read MAC address */
- for (i = 0; i < 6; i++, cp += 2) {
- enet[i] = aschex_to_byte ((unsigned char *)cp);
- }
- }
- /* Scan to the end of the record */
- while ((*cp != '\n') && (*cp != (char)0xff)) {
- cp++;
- }
- /* If the next character is a \n, 0 or ff, we are done. */
- cp++;
- if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
- break;
- }
-
-#ifdef CONFIG_FEC_ENET
- /* The MAC address is the same as normal ethernet except the 3rd byte */
- /* (See the E.P. Planet Core Overview manual */
- enet[3] |= 0x80;
-#endif
-
- printf("MAC address = %pM\n", enet);
-}
-
-int misc_init_r(void)
-{
- uchar enetaddr[6];
-
- if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
- board_get_enetaddr(enetaddr);
- eth_setenv_enetaddr("ethaddr", enetaddr);
- }
-
- return 0;
-}
-
-void rpxclassic_init (void)
-{
- /* Enable NVRAM */
- *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
-
-#ifdef CONFIG_FEC_ENET
-
- /* Validate the fast ethernet tranceiver */
- *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
- *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
- *((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
- *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
-#endif
-
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size10;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /* Refresh clock prescalar */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_mar = 0x00000000;
-
- /* Map controller banks 1 to the SDRAM bank */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /* Check Bank 0 Memory Size
- * try 10 column mode
- */
-
- size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- return (size10);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base, long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size(base, maxsize));
-}
-/*-----------------------------------------------------------------------------
- * aschex_to_byte --
- *-----------------------------------------------------------------------------
- */
-static unsigned char aschex_to_byte (unsigned char *cp)
-{
- u_char byte, c;
-
- c = *cp++;
-
- if ((c >= 'A') && (c <= 'F')) {
- c -= 'A';
- c += 10;
- } else if ((c >= 'a') && (c <= 'f')) {
- c -= 'a';
- c += 10;
- } else {
- c -= '0';
- }
-
- byte = c * 16;
-
- c = *cp;
-
- if ((c >= 'A') && (c <= 'F')) {
- c -= 'A';
- c += 10;
- } else if ((c >= 'a') && (c <= 'f')) {
- c -= 'a';
- c += 10;
- } else {
- c -= '0';
- }
-
- byte += c;
-
- return (byte);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/* Video support for the ECCX daughter board */
-
-
-#include <common.h>
-#include <config.h>
-
-#ifdef CONFIG_VIDEO_SED13806
-#include <sed13806.h>
-
-
-/* Screen configurations: the initialization of the SD13806 depends on
- screen and on display mode. We handle only 8bpp and 16 bpp modes */
-
-/* ECCX board is supplied with a NEC NL6448BC20 screen */
-#ifdef CONFIG_NEC_NL6448BC20
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
-
-#ifdef CONFIG_VIDEO_SED13806_8BPP
-static const S1D_REGS init_regs [] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0xe5}, /* General IO Pins Control Register 0 */
- {0x0009,0x1f}, /* General IO Pins Control Register 1 */
- {0x0010,0x02}, /* Memory Clock Configuration Register */
- {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x04}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x03}, /* LCD Display Mode Register */
- {0x0041,0x02}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x40}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x01}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x00}, /* TV Output Control Register */
- {0x0060,0x03}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x00}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01E4,0x00}, /* Look-Up Table Data Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
- {0, 0}
-};
-#endif /* CONFIG_VIDEO_SED13806_8BPP */
-
-#ifdef CONFIG_VIDEO_SED13806_16BPP
-
-static const S1D_REGS init_regs [] =
-{
- {0x0001,0x00}, /* Miscellaneous Register */
- {0x01FC,0x00}, /* Display Mode Register */
- {0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
- {0x0005,0x00}, /* General IO Pins Configuration Register 1 */
- {0x0008,0xe5}, /* General IO Pins Control Register 0 */
- {0x0009,0x1f}, /* General IO Pins Control Register 1 */
- {0x0010,0x02}, /* Memory Clock Configuration Register */
- {0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
- {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
- {0x001C,0x02}, /* MediaPlug Clock Configuration Register */
- {0x001E,0x01}, /* CPU To Memory Wait State Select Register */
- {0x0021,0x04}, /* DRAM Refresh Rate Register */
- {0x002A,0x00}, /* DRAM Timings Control Register 0 */
- {0x002B,0x01}, /* DRAM Timings Control Register 1 */
- {0x0020,0x80}, /* Memory Configuration Register */
- {0x0030,0x25}, /* Panel Type Register */
- {0x0031,0x00}, /* MOD Rate Register */
- {0x0032,0x4F}, /* LCD Horizontal Display Width Register */
- {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
- {0x0035,0x01}, /* TFT FPLINE Start Position Register */
- {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
- {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
- {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
- {0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
- {0x003B,0x00}, /* TFT FPFRAME Start Position Register */
- {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
- {0x0040,0x05}, /* LCD Display Mode Register */
- {0x0041,0x02}, /* LCD Miscellaneous Register */
- {0x0042,0x00}, /* LCD Display Start Address Register 0 */
- {0x0043,0x00}, /* LCD Display Start Address Register 1 */
- {0x0044,0x00}, /* LCD Display Start Address Register 2 */
- {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
- {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
- {0x0048,0x00}, /* LCD Pixel Panning Register */
- {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
- {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
- {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
- {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
- {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
- {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
- {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
- {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
- {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
- {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
- {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
- {0x005B,0x00}, /* TV Output Control Register */
- {0x0060,0x05}, /* CRT/TV Display Mode Register */
- {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
- {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
- {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
- {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
- {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
- {0x0068,0x00}, /* CRT/TV Pixel Panning Register */
- {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
- {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
- {0x0070,0x00}, /* LCD Ink/Cursor Control Register */
- {0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
- {0x0072,0x00}, /* LCD Cursor X Position Register 0 */
- {0x0073,0x00}, /* LCD Cursor X Position Register 1 */
- {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
- {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
- {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
- {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
- {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
- {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
- {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
- {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
- {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
- {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
- {0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
- {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
- {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
- {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
- {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
- {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
- {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
- {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
- {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
- {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
- {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
- {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
- {0x0100,0x00}, /* BitBlt Control Register 0 */
- {0x0101,0x00}, /* BitBlt Control Register 1 */
- {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
- {0x0103,0x00}, /* BitBlt Operation Register */
- {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
- {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
- {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
- {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
- {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
- {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
- {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
- {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
- {0x0110,0x00}, /* BitBlt Width Register 0 */
- {0x0111,0x00}, /* BitBlt Width Register 1 */
- {0x0112,0x00}, /* BitBlt Height Register 0 */
- {0x0113,0x00}, /* BitBlt Height Register 1 */
- {0x0114,0x00}, /* BitBlt Background Color Register 0 */
- {0x0115,0x00}, /* BitBlt Background Color Register 1 */
- {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
- {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
- {0x01E0,0x01}, /* Look-Up Table Mode Register */
- {0x01E2,0x00}, /* Look-Up Table Address Register */
- {0x01E4,0x00}, /* Look-Up Table Data Register */
- {0x01F0,0x10}, /* Power Save Configuration Register */
- {0x01F1,0x00}, /* Power Save Status Register */
- {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
- {0x01FC,0x01}, /* Display Mode Register */
- {0, 0}
-};
-
-#endif /* CONFIG_VIDEO_SED13806_16BPP */
-#endif /* CONFIG_NEC_NL6448BC20 */
-
-
-#ifdef CONFIG_CONSOLE_EXTRA_INFO
-
-/*-----------------------------------------------------------------------------
- * video_get_info_str -- setup a board string: type, speed, etc.
- * line_number= location to place info string beside logo
- * info= buffer for info string
- *-----------------------------------------------------------------------------
- */
-void video_get_info_str (int line_number, char *info)
-{
- if (line_number == 1) {
- strcpy (info, " RPXClassic board");
- }
- else {
- info [0] = '\0';
- }
-
-}
-#endif
-
-/*-----------------------------------------------------------------------------
- * board_video_init -- init de l'EPSON, config du CS
- *-----------------------------------------------------------------------------
- */
-unsigned int board_video_init (void)
-{
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- /* Program ECCX registers */
- *(ECCX_CSR12) |= ECCX_860;
- *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
- *(ECCX_CSR8) |= ECCX_ENEPSON;
-
- memctl->memc_or2 = SED13806_OR;
- memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
-
- return (SED13806_REG_ADDR);
-}
-
-/*-----------------------------------------------------------------------------
- * board_validate_screen --
- *-----------------------------------------------------------------------------
- */
-void board_validate_screen (unsigned int base)
-{
- /* Activate the panel bias power */
- *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
-}
-/*-----------------------------------------------------------------------------
- * board_get_regs --
- *-----------------------------------------------------------------------------
- */
-const S1D_REGS *board_get_regs (void)
-{
- return (init_regs);
-}
-/*-----------------------------------------------------------------------------
- * board_get_width --
- *-----------------------------------------------------------------------------
- */
-int board_get_width (void)
-{
- return (DISPLAY_WIDTH);
-}
-
-/*-----------------------------------------------------------------------------
- * board_get_height --
- *-----------------------------------------------------------------------------
- */
-int board_get_height (void)
-{
- return (DISPLAY_HEIGHT);
-}
-
-#endif /* CONFIG_VIDEO_SED13806 */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stäubli Faverges - <www.staubli.com>
- * Pierre AUBERT p.aubert@staubli.com
- * U-Boot port on RPXClassic LF (CLLF_BW31) board
- *
- * RPXClassic uses Am29DL323B flash memory with 2 banks
- *
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0 ;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x00010000;
- info->start[3] = base + 0x00018000;
- info->start[4] = base + 0x00020000;
- info->start[5] = base + 0x00028000;
- info->start[6] = base + 0x00030000;
- info->start[7] = base + 0x00038000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i-7) * 0x00040000) ;
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMDL323B:
- printf ("AMDL323DB (16 Mbytes, bottom boot sect)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Reset flash componeny */
- addr [0] = 0xf0f0f0f0;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0xAAA] = 0xAAAAAAAA ;
- addr[0x555] = 0x55555555 ;
- addr[0xAAA] = 0x90909090 ;
-
- value = addr[0] ;
-
- switch (value & 0x00FF00FF) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[2] ; /* device ID */
-
- switch (value & 0x00FF00FF) {
- case (AMD_ID_DL323B & 0x00FF00FF):
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x01000000; /* 16 Mb */
-
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
- /* set up sector start address table */
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x00010000;
- info->start[3] = base + 0x00018000;
- info->start[4] = base + 0x00020000;
- info->start[5] = base + 0x00028000;
- info->start[6] = base + 0x00030000;
- info->start[7] = base + 0x00038000;
- for (i = 8; i < info->sector_count; i++) {
- info->start[i] = base + ((i-7) * 0x00040000) ;
- }
-
- /* check for protected sectors */
- for (i = 0; i < 23; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[4] & 1 ;
- }
- /* Check for protected sectors in the 2nd bank */
- addr[0x100AAA] = 0xAAAAAAAA ;
- addr[0x100555] = 0x55555555 ;
- addr[0x100AAA] = 0x90909090 ;
-
- for (i = 23; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[4] & 1 ;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0xF0F0F0F0; /* reset bank 1 */
- addr = (volatile unsigned long *)info->start[23];
-
- *addr = 0xF0F0F0F0; /* reset bank 2 */
-
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
- addr[0xAAA] = 0x80808080;
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *)(info->start[sect]) ;
- addr[0] = 0x30303030 ;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long *)(info->start[l_sect]);
- while ((addr[0] & 0x80808080) != 0x80808080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_long *)info->start[0];
- addr[0] = 0xF0F0F0F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
- addr[0xAAA] = 0xA0A0A0A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = RPXlite.o flash.o
+++ /dev/null
-# Porting U-Boot onto RPXlite board
-# Written by Yoo. Jonghoon
-# E-Mail : yooth@ipone.co.kr
-# IP ONE Inc.
-
-# Since 2001. 1. 29
-
-# Shell : bash
-# Cross-compile tools : Montavista Hardhat
-# Debugging tools : Windriver VisionProbe (PowerPC BDM)
-# ppcboot ver. : ppcboot-0.8.1
-
-###############################################################
-# 1. Hardware setting
-###############################################################
-
-1.1. Board, BDM settings
- Install board, BDM, connect each other
-
-1.2. Save Register value
- Boot with board-on monitor program and save the
- register values with BDM.
-
-1.3. Configure flash programmer
- Check flash memory area in the memory map.
- 0xFFC00000 - 0xFFFFFFFF
-
- Boot monitor program is at
- 0xFFF00000
-
- You can program on-board flash memory with VisionClick
- flash programmer. Set the target flash device as:
-
- 29DL800B
-
- (?) The flash memory device in the board *is* 29LV800B,
- but I cannot program it with '29LV800B' option.
- (in VisionClick flash programming tools)
- I don't know why...
-
-1.4. Save boot monitor program *IMPORTANT*
- Upload boot monitor program from board to file.
- boot monitor program starts at 0xFFF00000
-
-1.5. Test flash memory programming
- Try to erase boot program in the flash memory,
- and re-write them.
- *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE
- BEFORE ERASING FLASH
-
-###############################################################
-# 2. U-Boot setting
-###############################################################
-
-2.1. Download U-Boot tarball at
- ftp://ftp.denx.de
- (The latest version is ppcboot-0.8.1.tar.bz2)
-
- To extract the archive use the following syntax :
- > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf -
-
-2.2. Add the following lines in '.profile'
- export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin
-
-2.3. Make board specific config, for example:
- > cd ppcboot-0.8.1
- > make TQM860L_config
-
- Now we can build ppcboot bin files.
- After make all, you must see these files in your
- ppcboot root directory.
-
- ppcboot
- ppcboot.bin
- ppcboot.srec
- ppcboot.map
-
-2.4. Make your own board directory into the
- ppcboot-0.8.1/board
- and make your board-specific files here.
-
- For exmanple, tqm8xx files are composed of
- .depend : Nothing
- Makefile : To make config file
- config.mk : Sets base address
- flash.c : Flash memory control files
- ppcboot.lds : linker(ld) script? (I don't know this yet)
- tqm8xx.c : DRAM control and board check routines
-
- And, add your board config lines in the
- ppcboot-0.8.1/Makefile
-
- Finally, add config_(your board).h file in the
- ppcboot-0.8.1/include/
-
- I've made board/rpxlite directory, and just copied
- tqm8xx settings for now.
-
- Rebuild ppcboot for rpxlite board:
- > make rpxlite_config
- > make
-
-###############################################################
-# 3. U-Boot porting
-###############################################################
-
-3.1. My RPXlite files are based on tqm8xx board files.
- > cd board
- > cp -r tqm8xx RPXLITE
- > cd RPXLITE
- > mv tqm8xx.c RPXLITE.c
- > cd ../../include
- > cp config_tqm8xx.h config_RPXLITE.h
-
-3.2. Modified files are:
- board/RPXLITE/RPXLITE.c /* DRAM-related routines */
- board/RPXLITE/flash.c /* flash-related routines */
- board/RPXLITE/config.mk /* set text base address */
- arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */
- include/config_RPXLITE.h /* board specific registers */
-
- See 'reg_config.txt' for register values in detail.
-
-###############################################################
-# 4. Running Linux
-###############################################################
-
-
-###############################################################
-# Misc Information
-###############################################################
-
-mem_config.txt:
-===============
-
-Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device
-manufacturer id : 01 (AMD)
-device id : 5B (AM29LV800B)
-size : 4Mbyte
-sector # : 19
-
-Sector information :
-
-number start addr. size
-00 FFC0_0000 64
-01 FFC1_0000 32
-02 FFC1_8000 32
-03 FFC2_0000 128
-04 FFC4_0000 256
-05 FFC8_0000 256
-06 FFCC_0000 256
-07 FFD0_0000 256
-08 FFD4_0000 256
-09 FFD8_0000 256
-10 FFDC_0000 256
-11 FFE0_0000 256
-12 FFE4_0000 256
-13 FFE8_0000 256
-14 FFEC_0000 256
-15 FFF0_0000 256
-16 FFF4_0000 256
-17 FFF8_0000 256
-18 FFFC_0000 256
-
-
-reg_config.txt:
-===============
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* SIU (System Interface Unit) */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-
-
-/*### IMMR */
-/*### Internal Memory Map Register */
-/*### Chap. 11.4.1 */
-
- ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */
- PARTNUM = 0x21
- MASKNUM = 0x00
-
- => 0xFA20 2100
-
----------------------------------------------------------------------
-
-/*### SIUMCR */
-/*### SIU Module Configuration Register */
-/*### Chap. 11.4.2 */
-/*### Offset : 0x0000 0000 */
-
- EARB = 0
- EARP = 0
- DSHW = 0
- DBGC = 0
- DBPC = 0
- FRC = 0
- DLK = 0
- OPAR = 0
- PNCS = 0
- DPC = 0
- MPRE = 0
- MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */
- AEME = 0
- SEME = 0
- BSC = 0
- GB5E = 0
- B2DD = 0
- B3DD = 0
-
- => 0x0000 0800
-
----------------------------------------------------------------------
-
-/*### SYPCR */
-/*### System Protection Control Register */
-/*### Chap. 11.4.3 */
-/*### Offset : 0x0000 0004 */
-
- SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */
- BMT = 0x06 /* BUS monitoring timing */
- BME = 1 /* BUS monitor enable */
- SWF = 1
- SWE = 0 /* SW watchdog disable */
- SWRI = 0
- SWP = 1
-
- => 0xFFFF 0689
-
----------------------------------------------------------------------
-
-/*### TESR */
-/*### Transfer Error Status Register */
-/*### Chap. 11.4.4 */
-/*### Offset : 0x0000 0020 */
-
- IEXT = 0
- ITMT = 0
- IPB = 0000
- DEXT = 0
- DTMT = 0
- DPB = 0000
-
- => 0x0000 0000
-
----------------------------------------------------------------------
-
-/*### SIPEND */
-/*### SIU Interrupt Pending Register */
-/*### Chap. 11.5.4.1 */
-/*### Offset : 0x0000 0010 */
-
- IRQ0~IRQ7 = 0
- LVL0~LVL7 = 0
-
- => 0x0000 0000
-
----------------------------------------------------------------------
-
-/*### SIMASK */
-/*### SIU Interrupt Mask Register */
-/*### Chap. 11.5.4.2 */
-/*### Offset : 0x0000 0014 */
-
- IRM0~IRM7 = 0 /* Mask all interrupts */
- LVL0~LVL7 = 0
-
- => 0x0000 0000
-
----------------------------------------------------------------------
-
-/*### SIEL */
-/*### SIU Interrupt Edge/Level Register */
-/*### Chap. 11.5.4.3 */
-/*### Offset : 0x0000 0018 */
-
- ED0~ED7 = 0 /* Low level triggered */
- WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */
-
- => 0x0000 0000
-
----------------------------------------------------------------------
-
-/*### SIVEC */
-/*### SIU Interrupt Vector Register */
-/*### Chap. 11.5.4.4 */
-/*### Offset : 0x0000 001C */
-
- INTC = 3C /* The lowest interrupt is pending..(?) */
-
- => 0x3C00 0000
-
----------------------------------------------------------------------
-
-/*### SWSR */
-/*### Software Service Register */
-/*### Chap. 11.7.1 */
-/*### Offset : 0x0000 001E */
-
- SEQ = 0
-
- => 0x0000
-
----------------------------------------------------------------------
-
-/*### SDCR */
-/*### SDMA Configuration Register */
-/*### Chap. 20.2.1 */
-/*### Offset : 0x0000 0032 */
-
- FRZ = 0
- RAID = 01 /* Priority level 5 (BR5) (normal operation) */
-
- => 0x0000 0001
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* UPMA (User Programmable Machine A) */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-
-/*### Chap. 16.6.4.1 */
-/*### Offset = 0x0000 017c */
-
- T0 = CFFF CC24 /* Single Read */
- T1 = 0FFF CC04
- T2 = 0CAF CC04
- T3 = 03AF CC08
- T4 = 3FBF CC27 /* last */
- T5 = FFFF CC25
- T6 = FFFF CC25
- T7 = FFFF CC25
- T8 = CFFF CC24 /* Burst Read */
- T9 = 0FFF CC04
- T10 = 0CAF CC84
- T11 = 03AF CC88
- T12 = 3FBF CC27 /* last */
- T13 = FFFF CC25
- T14 = FFFF CC25
- T15 = FFFF CC25
- T16 = FFFF CC25
- T17 = FFFF CC25
- T18 = FFFF CC25
- T19 = FFFF CC25
- T20 = FFFF CC25
- T21 = FFFF CC25
- T22 = FFFF CC25
- T23 = FFFF CC25
- T24 = CFFF CC24 /* Single Write */
- T25 = 0FFF CC04
- T26 = 0CFF CC04
- T27 = 03FF CC00
- T28 = 3FFF CC27 /* last */
- T29 = FFFF CC25
- T30 = FFFF CC25
- T31 = FFFF CC25
- T32 = CFFF CC24 /* Burst Write */
- T33 = 0FFF CC04
- T34 = 0CFF CC80
- T35 = 03FF CC8C
- T36 = 0CFF CC00
- T37 = 33FF CC27 /* last */
- T38 = FFFF CC25
- T39 = FFFF CC25
- T40 = FFFF CC25
- T41 = FFFF CC25
- T42 = FFFF CC25
- T43 = FFFF CC25
- T44 = FFFF CC25
- T45 = FFFF CC25
- T46 = FFFF CC25
- T47 = FFFF CC25
- T48 = C0FF CC24 /* Refresh */
- T49 = 03FF CC24
- T50 = 0FFF CC24
- T51 = 0FFF CC24
- T52 = 3FFF CC27 /* last */
- T53 = FFFF CC25
- T54 = FFFF CC25
- T55 = FFFF CC25
- T56 = FFFF CC25
- T57 = FFFF CC25
- T58 = FFFF CC25
- T59 = FFFF CC25
- T60 = FFFF CC25 /* Exception */
- T61 = FFFF CC25
- T62 = FFFF CC25
- T63 = FFFF CC25
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* UPMB */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
----------------------------------------------------------------------
-
-/*### Chap. 16.6.4.1 */
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* MEMC */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
----------------------------------------------------------------------
-
-/*### BR0 & OR0 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */
-/*### Flash memory */
-
- BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */
- AT = 000
- PS = 00
- PARE = 0
- WP = 0
- MS = 0 /* GPCM */
- V = 1 /* Valid */
-
- => 0xFE00 0001
-
- AM = 1111 1110 0000 0000 0 /* 32MBytes */
- ATM = 000
- CSNT/SAM = 0
- ACS/G5LA,G5LS = 00
- BIH = 1 /* Burst inhibited */
- SCY = 0100 /* cycle length = 4 */
- SETA = 0
- TRLX = 0
- EHTR = 0
-
- => 0xFE00 0140
-
-/*### BR1 & OR1 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
-/*### SDRAM */
-
- BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */
- AT = 000
- PS = 00
- PARE = 0
- WP = 0
- MS = 1 /* UPMA */
- V = 1 /* Valid */
-
- => 0x0000 0081
-
- AM = 1111 1110 0000 0000 /* 32MBytes */
- ATM = 000
- CSNT/SAM = 1
- ACS/G5LA,G5LS = 11
- BIH = 0
- SCY = 0000 /* cycle length = 0 */
- SETA = 0
- TRLX = 0
- EHTR = 0
-
- => 0xFE00 0E00
-
-/*### BR2 & OR2 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */
-
- BR2 & OR2 = 0x0000 0000 /* Not used */
-
-/*### BR3 & OR3 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
-/*### BCSR */
-
- BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */
- AT = 000
- PS = 00
- PARE = 0
- WP = 0
- MS = 0 /* GPCM */
- V = 1 /* Valid */
-
- => 0xFA40 0001
-
- AM = 1111 1111 0111 1111 1 /* (?) */
- ATM = 000
- CSNT/SAM = 1
- ACS/G5LA,G5LS = 00
- BIH = 1 /* Burst inhibited */
- SCY = 0001 /* cycle length = 1 */
- SETA = 0
- TRLX = 0
-
- => 0xFF7F 8910
-
-/*### BR4 & OR4 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
-/*### NVRAM & SRAM */
-
- BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */
- AT = 000
- PS = 01
- PARE = 0
- WP = 0
- MS = 0 /* GPCM */
- V = 1 /* Valid */
-
- => 0xFA00 0401
-
- AM = 1111 1111 1111 1000 0 /* 8MByte */
- ATM = 000
- CSNT/SAM = 1
- ACS/G5LA,G5LS = 00
- BIH = 1 /* Burst inhibited */
- SCY = 0111 /* cycle length = 7 */
- SETA = 0
- TRLX = 0
-
- => 0xFFF8 0970
-
-/*### BR5 & OR5 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */
-
- BR5 & OR5 = 0x0000 0000 /* Not used */
-
-/*### BR6 & OR6 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */
-
- BR6 & OR6 = 0x0000 0000 /* Not used */
-
-/*### BR7 & OR7 */
-/*### Base Registers & Option Registers */
-/*### Chap. 16.4.1 & 16.4.2 */
-/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */
-
- BR7 & OR7 = 0x0000 0000 /* Not used */
-
-/*### MAR */
-/*### Memory Address Register */
-/*### Chap. 16.4.7 */
-/*### Offset : 0x0000 0164 */
-
- MA = External memory address
-
-/*### MCR */
-/*### Memory Command Register */
-/*### Chap. 16.4.5 */
-/*### Offset : 0x0000 0168 */
-
- OP = xx /* Command op code */
- UM = 1 /* Select UPMA */
- MB = 001 /* Select CS1 */
- MCLF = xxxx /* Loop times */
- MAD = xx xxxx /* Memory array index */
-
-/*### MAMR */
-/*### Machine A Mode Register */
-/*### Chap. 16.4.4 */
-/*### Offset : 0x0000 0170 */
-
- PTA = 0101 1000
- PTAE = 1 /* Periodic timer A enabled */
- AMA = 010
- DSA = 00
- G0CLA = 000
- GPLA4DIS = 1
- RLFA = 0100
- WLFA = 0011
- TLFA = 0000
-
- => 0x58A0 1430
-
-/*### MBMR */
-/*### Machine B Mode Register */
-/*### Chap. 16.4.4 */
-/*### Offset : 0x0000 0174 */
-
- PTA = 0100 1110
- PTAE = 0 /* Periodic timer B disabled */
- AMA = 000
- DSA = 00
- G0CLA = 000
- GPLA4DIS = 1
- RLFA = 0000
- WLFA = 0000
- TLFA = 0000
-
- => 0x4E00 1000
-
-/*### MSTAT */
-/*### Memory Status Register */
-/*### Chap. 16.4.3 */
-/*### Offset : 0x0000 0178 */
-
- PER0~PER7 = Parity error
- WPER = Write protection error
-
- => 0x0000
-
-/*### MPTPR */
-/*### Memory Periodic Timer Prescaler Register */
-/*### Chap. 16.4.8 */
-/*### Offset : 0x0000 017A */
-
- PTP = 0000 1000 /* Divide by 8 */
-
- => 0x0800
-
-/*### MDR */
-/*### Memory Data Register */
-/*### Chap. 16.4.6 */
-/*### Offset : 0x0000 017C */
-
- MD = Memory data contains the RAM array word
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* TIMERS */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
----------------------------------------------------------------------
-
-/*### TBREFx */
-/*### Timebase Reference Registers */
-/*### Chap. 11.9.2 */
-/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
-/*### (Locked) */
-
- TBREFF0 = 0xFFFF FFFF
- TBREFF1 = 0xFFFF FFFF
-
----------------------------------------------------------------------
-
-/*### TBSCR */
-/*### Timebase Status and Control Registers */
-/*### Chap. 11.9.3 */
-/*### Offset : 0x0000 0200 */
-/*### (Locked) */
-
- TBIRQ = 00000000
- REF0 = 0
- REF1 = 0
- REFE0 = 0 /* Reference interrupt disable */
- REFE1 = 0
- TBF = 1
- TBE = 1 /* Timebase enable */
-
- => 0x0003
-
----------------------------------------------------------------------
-
-/*### RTCSC */
-/*### Real-Time Clock Status and Control Registers */
-/*### Chap. 11.10.1 */
-/*### Offset : 0x0000 0220 */
-/*### (Locked) */
-
- RTCIRQ = 00000000
- SEC = 1
- ALR = 0
- 38K = 0 /* PITRTCLK is driven by 32.768KHz */
- SIE = 0
- ALE = 0
- RTF = 0
- RTE = 1 /* Real-Time clock enabled */
-
- => 0x0081
-
----------------------------------------------------------------------
-
-/*### RTC */
-/*### Real-Time Clock Registers */
-/*### Chap. 11.10.2 */
-/*### Offset : 0x0000 0224 */
-/*### (Locked) */
-
- RTC = Real time clock measured in second
-
----------------------------------------------------------------------
-
-/*### RTCAL */
-/*### Real-Time Clock Alarm Registers */
-/*### Chap. 11.10.3 */
-/*### Offset : 0x0000 022C */
-/*### (Locked) */
-
- ALARM = 0xFFFF FFFF
-
----------------------------------------------------------------------
-
-/*### RTSEC */
-/*### Real-Time Clock Alarm Second Registers */
-/*### Chap. 11.10.4 */
-/*### Offset : 0x0000 0228 */
-/*### (Locked) */
-
- COUNTER = Counter bits(fraction of a second)
-
----------------------------------------------------------------------
-
-/*### PISCR */
-/*### Periodic Interrupt Status and Control Register */
-/*### Chap. 11.11.1 */
-/*### Offset : 0x0000 0240 */
-/*### (Locked) */
-
- PIRQ = 0
- PS = 0 /* Write 1 to clear */
- PIE = 0
- PITF = 1
- PTE = 0 /* PIT disabled */
-
----------------------------------------------------------------------
-
-/*### PITC */
-/*### PIT Count Register */
-/*### Chap. 11.11.2 */
-/*### Offset : 0x0000 0244 */
-/*### (Locked) */
-
- PITC = PIT count
-
----------------------------------------------------------------------
-
-/*### PITR */
-/*### PIT Register */
-/*### Chap. 11.11.3 */
-/*### Offset : 0x0000 0248 */
-/*### (Locked) */
-
- PIT = PIT count /* Read only */
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* CLOCKS */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
----------------------------------------------------------------------
-
-
----------------------------------------------------------------------
-
-/*### SCCR */
-/*### System Clock and Reset Control Register */
-/*### Chap. 15.6.1 */
-/*### Offset : 0x0000 0280 */
-/*### (Locked) */
-
- COM = 11 /* Clock output disabled */
- TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */
- RTDIV = 0 /* The clock is divided by 4 */
- RTSEL = 0 /* OSCM(Crystal oscillator) is selected */
- CRQEN = 0
- PRQEN = 0
- EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */
- DFSYNC = 00 /* Divided by 1 (normal operation) */
- DFBRG = 00 /* Divided by 1 (normal operation) */
- DFNL = 000
- DFNH = 000
-
- => 0x6200 0000
-
----------------------------------------------------------------------
-
-/*### PLPRCR */
-/*### PLL, Low-Power, and Reset Control Register */
-/*### Chap. 15.6.2 */
-/*### Offset : 0x0000 0284 */
-/*### (Locked) */
-
- MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */
- SPLSS = 0
- TEXPS = 0
- TMIST = 0
- CSRC = 0 /* The general system clock is generated by the DFNH field */
- LPM = 00 /* Normal high/normal low mode */
- CSR = 0
- LOLRE = 0
- FIOPD = 0
-
- => 0x0050 0000
-
----------------------------------------------------------------------
-
-/*### RSR */
-/*### Reset Status Register */
-/*### Chap. 12.2 */
-/*### Offset : 0x0000 0288 */
-/*### (Locked) */
-
- EHRS = External hard reset
- ESRS = External soft reset
- LLRS = Loss-of-lock reset
- SWRS = Software watchdog reset
- CSRS = Check stop reset
- DBHRS = Debug port hard reset
- DBSRS = Debug port soft reset
- JTRS = JTAG reset
-
-
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
-/* DMA */
-/* */
-/*------------------------------------------------------------------- */
-/*------------------------------------------------------------------- */
----------------------------------------------------------------------
-
-/*### SDSR */
-/*### SDMA Status Register */
-/*### Chap. 20.2.2 */
-/*### Offset : 0x0000 0908 */
-
- SBER = 0 /* SDMA channel bus error */
- DSP2 = 0 /* DSP chain2 (Tx) interrupt */
- DSP1 = 0 /* DSP chain1 (Rx) interrupt */
-
- => 0x00
-
-/*### SDMR */
-/*### SDMA Mask Register */
-/*### Chap. 20.2.3 */
-/*### Offset : 0x0000 090C */
-
- SBER = 0
- DSP2 = 0
- DSP1 = 0 /* All interrupts are masked */
-
- => 0x00
-
-/*### SDAR */
-/*### SDMA Address Register */
-/*### Chap. 20.2.4 */
-/*### Offset : 0x0000 0904 */
-
- AR = 0xxxxx xxxx /* current system address */
-
- => 0xFA20 23AC
-
-/*### IDSRx */
-/*### IDMA Status Register */
-/*### Chap. 20.3.3.2 */
-/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */
-
- AD = 0
- DONE = 0
- OB = 0
-
- => 0x00
-
-/*### IDMRx */
-/*### IDMA Mask Register */
-/*### Chap. 20.3.3.3 */
-/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */
-
- AD = 0
- DONE = 0
- OB = 0
+++ /dev/null
-After several heart-struck failure, I got one workable way to program
-each other in FLASH between PlanetCore and U-Boot.
-
-Hardware Platform : RPXlite DW(EP 823 H1 DW)
-
-1. From U-Boot to PlanetCore
-
-Utilities : PlanetCore Boot Loader - PCL200.mot
-
-[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot
-PCL200.mot pcl200.bin
-
-[Target Operation]
-u-boot>t 100000 pcl200.bin
-u-boot>go 0x100000
-## Starting application at 0x00100000 ...
-
-MPC8xx PlanetCore Flash Burner v2.00
-Copyright 2001 Embedded Planet. All rights reserved.
-
-Construct Flash Device.....done.
-
-
-Program MPC8xx PlanetCore Boot Loader v2.00
-Built Sep 19, 2001 at 14:34:42
-Image located from FC000000 to FC01B5D1.
-(Skipping an image, only loading low boot image)
-
-Low boot board detected, skipping high boot image.
-Erasing, programming and verifying will start in 20
-seconds
-Press P to start immediately or ESC to cancel
-Press Space or Enter for more options.
-..............
-
-Erasing
-Programming
-FLASH programmed successfully!
-Press R to induce a hard reset
-
-MPC8xx PlanetCore Boot Loader v2.00
-Copyright 2001 Embedded Planet. All rights reserved.
-DRAM available size = 64 MB
-wvCV
-DRAM OK
->
-
-2. From PlanetCore to U-Boot
-
-Utilities : PlanetCore FLASH Burner - PCB200.mot
-
-Use Flash Burner to finish the work:
-
-First, TFTP the U-Boot image file to RAM; For example,
-RPXlite_DW.bin to 0x400000
-Second, TFTP FLASH Burner to RAM; For example,
-0x100000
-Third, run the FLASH Burner and Program the U-Boot
-image into the correct location in FLASH.
-
-[Target Operation]
-MPC8xx PlanetCore Boot Loader v2.00
-Copyright 2001 Embedded Planet. All rights reserved.
-DRAM available size = 64 MB
-wvCV
-DRAM OK
->t
-Load using tftp via Ethernet
-Enter server IP address <172.16.115.6> :
-Enter server filename <PCL200.mot> : RPXlite_DW.bin
-Enter (B)inary or (S)record input mode <S> : B
-Enter address offset : <00400000 hex> :
-
-Total bytes = 120096 in 232184 uSecs
-Loaded addresses 00400000 through 0041D51F.
-Start address = 00400000
->t
-Load using tftp via Ethernet
-Enter server IP address <172.16.115.6> :
-Enter server filename <RPXlite_DW.bin> : PCB200.mot
-Enter (B)inary or (S)record input mode <B> : S
-Enter address offset : <00000000 hex> :
-.512.1024..2048....4096.....
-Total bytes = 326280 in 2570249 uSecs
-Loaded addresses 00100000 through 0011BB51.
-Start address = 00100000
->go
-[Go 00100000]
-
-MPC8xx PlanetCore Flash Burner v2.00
-Copyright 2001 Embedded Planet. All rights reserved.
-
-Construct Flash Device.....done.
-
-Bad start address
-Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length =
-0xFFFFFFFF
-Forcing Menu Interface
-
-h[elp] Show commands.
-c[ode] Show information on code to be loaded.
-di[splay] Display all flash sections.
-du[mp] Dump memory. d ? for more info.
-e[rase] Erase flash sections.
-f[ill] Fill flash sections.
-im[age] Toggle load high, low, or both flash
-images.
-in[fo] Show flash information.
-ma[p] Show memory map.
-mo[dify] Modify memory. m ? for more info.
-p[rogram] Erase, program, and verify now.
-reset Restart the loader.
-s[how] Show flash sections to erase and program.
-t[est] Test flash sections.
-q[uit] Quit without programming.
-#program 400000 ff000000 1D51F
-doProgram( 400000 ff000000 1D51F )
-
-Start = 0x00400000, target = 0xFF000000, length =
-0x0001D51F
-Erasing sector 0xFF000000, length 0x008000.
-Erasing sector 0xFF008000, length 0x008000.
-Erasing sector 0xFF010000, length 0x008000.
-Erasing sector 0xFF018000, length 0x008000.
-Programming FF000000 through FF01D51E
-FLASH programmed successfully!
-Press R to induce a hard reset
-
-Forcing Hard Reset by MachineCheck and
-ResetOnCheckstop...
-
-U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
-
-CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB
-D-Cache
-Board: RPXlite_DW
-DRAM: 64 MB
-FLASH: 16 MB
-*** Warning - bad CRC, using default environment
-
-In: serial
-Out: serial
-Err: serial
-Net: SCC ETHERNET
-u-boot>
-
--------------------------------------------------
-
-Well, sometimes network function of PlanetCore couldn't work when
-switching from U-Boot to PlanetCore. For example, you couldn't
-download a file from HOST PC via TFTP. Don't worry, just restart your
-HOST PC and everything would work as smooth as clockwork. I don't
-know the reason WHY:-)
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Merry Christmas and Happy New Year!
-
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-=====
-Best regards,
-
-Sam
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- *
- * DRAM related UPMA register values are modified.
- * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-
-/* ------------------------------------------------------------------------- */
-
-#define _NOT_USED_ 0xFFFFCC25
-
-const uint sdram_table[] = {
- /*
- * Single Read. (Offset 00h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
- 0x3FBFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Read. (Offset 08h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
- 0x3FBFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Single Write. (Offset 18h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
- 0x3FFFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Burst Write. (Offset 20h in UPMA RAM)
- */
- 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
- 0x0CFFCC00, 0x33FFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_,
-
- /*
- * Refresh. (Offset 30h in UPMA RAM)
- */
- 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
- 0x3FFFCC27, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
- /*
- * Exception. (Offset 3Ch in UPMA RAM)
- */
- _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
-};
-
-/* ------------------------------------------------------------------------- */
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- puts ("Board: RPXlite\n");
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
- long int size10;
-
- upmconfig (UPMA, (uint *) sdram_table,
- sizeof (sdram_table) / sizeof (uint));
-
- /* Refresh clock prescalar */
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- memctl->memc_mar = 0x00000000;
-
- /* Map controller banks 1 to the SDRAM bank */
- memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
-
- memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
-
- udelay (200);
-
- /* perform SDRAM initializsation sequence */
-
- memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
- udelay (1);
-
- memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
-
- udelay (1000);
-
- /* Check Bank 0 Memory Size
- * try 10 column mode
- */
-
- size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
- SDRAM_MAX_SIZE);
-
- return (size10);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
- long int maxsize)
-{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- memctl->memc_mamr = mamr_value;
-
- return (get_ram_size (base, maxsize));
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- *
- * Some of flash control words are modified. (from 2x16bit device
- * to 4x8bit device)
- * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
- * are not tested.
- *
- * (?) Does an RPXLite board which
- * does not use AM29LV800 flash memory exist ?
- * I don't know...
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */
-/* volatile memctl8xx_t *memctl = &immap->im_memctl; */
- unsigned long size_b0 ;
- int i;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-/*
- size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-*/
- /* Remap FLASH according to real size */
-/*%%%
- memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
- memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
-%%%*/
- /* Re-do sizing to get full correct info */
-
- size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00010000;
- info->start[2] = base + 0x00018000;
- info->start[3] = base + 0x00020000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + ((i-3) * 0x00040000) ;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00040000;
- }
- }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- addr[0xAAA] = 0x00AA00AA ;
- addr[0x555] = 0x00550055 ;
- addr[0xAAA] = 0x00900090 ;
-
- value = addr[0] ;
-
- switch (value & 0x00FF00FF) {
- case AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr[2] ; /* device ID */
-
- switch (value & 0x00FF00FF) {
- case (AMD_ID_LV400T & 0x00FF00FF):
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV400B & 0x00FF00FF):
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (AMD_ID_LV800T & 0x00FF00FF):
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (AMD_ID_LV800B & 0x00FF00FF):
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00400000; /*%%% Size doubled by yooth */
- break; /* => 4 MB */
-
- case (AMD_ID_LV160T & 0x00FF00FF):
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-
- case (AMD_ID_LV160B & 0x00FF00FF):
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- break; /* => 4 MB */
-#if 0 /* enable when device IDs are available */
- case AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-
- case AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 67;
- info->size = 0x00800000;
- break; /* => 8 MB */
-#endif
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
- /*%%% sector start address modified */
- /* set up sector start address table */
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00010000;
- info->start[2] = base + 0x00018000;
- info->start[3] = base + 0x00020000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + ((i-3) * 0x00040000) ;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00010000;
- info->start[i--] = base + info->size - 0x00018000;
- info->start[i--] = base + info->size - 0x00020000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00040000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr = (volatile unsigned long *)(info->start[i]);
- info->protect[i] = addr[4] & 1 ;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (volatile unsigned long *)info->start[0];
-
- *addr = 0xF0F0F0F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
- addr[0xAAA] = 0x80808080;
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long *)(info->start[sect]) ;
- addr[0] = 0x30303030 ;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long *)(info->start[l_sect]);
- while ((addr[0] & 0x80808080) != 0x80808080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (vu_long *)info->start[0];
- addr[0] = 0xF0F0F0F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)(info->start[0]);
- ulong start;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((vu_long *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0xAAA] = 0xAAAAAAAA;
- addr[0x555] = 0x55555555;
- addr[0xAAA] = 0xA0A0A0A0;
-
- *((vu_long *)dest) = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
-
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
-
- . = env_offset;
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
Orphan powerpc mpc824x - - mousse MOUSSE - -
Orphan powerpc mpc8260 - - - rsdproto - -
Orphan powerpc mpc8260 - - rpxsuper RPXsuper - -
-Orphan powerpc mpc8xx - - - RPXClassic - -
-Orphan powerpc mpc8xx - - - RPXlite - -
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+RPXClassic powerpc mpc8xx - 2014-04-04
+RPXlite powerpc mpc8xx - 2014-04-04
genietv powerpc mpc8xx - 2014-04-04
mbx8xx powerpc mpc8xx - 2014-04-04
nx823 powerpc mpc8xx - 2014-04-04
#if 0
-#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+#if defined(CONFIG_RPXLITE)
/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
* SYPCR is write once only, therefore must the slowest memory be faster
#endif
#if defined(CONFIG_PCMCIA) \
- && (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE))
+ && defined(CONFIG_RPXLITE)
#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
#endif
-#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */
+#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
-#ifdef CONFIG_RPXCLASSIC
-void rpxclassic_init (void);
-#endif
-
void rpxlite_init (void);
#ifdef CONFIG_HERMES
#endif /* CONFIG_QS860T */
-/*** RPXCLASSIC *****************************************************/
-
-#ifdef CONFIG_RPXCLASSIC
-
-#ifdef CONFIG_FEC_ENET
-
-# define FEC_ENET /* use FEC for EThernet */
-# undef SCC_ENET
-
-#else /* ! CONFIG_FEC_ENET */
-
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PROFF_ENET PROFF_SCC1
-#define CPM_CR_ENET CPM_CR_CH_SCC1
-#define SCC_ENET 0
-#define PA_ENET_RXD ((ushort)0x0001)
-#define PA_ENET_TXD ((ushort)0x0002)
-#define PA_ENET_TCLK ((ushort)0x0200)
-#define PA_ENET_RCLK ((ushort)0x0800)
-#define PB_ENET_TENA ((uint)0x00001000)
-#define PC_ENET_CLSN ((ushort)0x0010)
-#define PC_ENET_RENA ((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT ((uint)0x0000003d)
-
-#endif /* CONFIG_FEC_ENET */
-
-#endif /* CONFIG_RPXCLASSIC */
-
/*** RPXLITE ********************************************************/
#ifdef CONFIG_RPXLITE
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define RPXClassic_50MHz
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860 1
-#define CONFIG_RPXCLASSIC 1
-
-#define CONFIG_SYS_TEXT_BASE 0xff000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
-
-/* Define CONFIG_FEC_ENET to use Fast ethernet instead of ethernet on SCC1 */
-#define CONFIG_FEC_ENET
-#ifdef CONFIG_FEC_ENET
-#define CONFIG_SYS_DISCOVER_PHY 1
-#define CONFIG_MII 1
-#endif /* CONFIG_FEC_ENET */
-#define CONFIG_MISC_INIT_R
-
-/* Video console (graphic: Epson SED13806 on ECCX board, no keyboard */
-#if 1
-#define CONFIG_VIDEO_SED13806
-#define CONFIG_NEC_NL6448BC20
-#define CONFIG_VIDEO_SED13806_16BPP
-
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_VIDEO_SW_CURSOR
-#endif
-
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK 1
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_RESET_ADDRESS 0x80000000
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFA200000
-
-/*-----------------------------------------------------------------------------
- * I2C Configuration
- *-----------------------------------------------------------------------------
- */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0x34
-
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-
-#if defined(CONFIG_SYS_I2C_SOFT)
-#define CONFIG_SYS_I2C 1
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00000010)
-#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
-#define I2C_READ ((iop->pdat & 0x00000010) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
- else iop->pdat &= ~0x00000010
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
- else iop->pdat &= ~0x00000020
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x34
-#endif
-
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFF000000
-
-#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#else
-#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
-#endif
-#define CONFIG_SYS_MONITOR_BASE 0xFF000000
-/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#if 0
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x8000
-#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
-#else
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_ADDR 0xfa000100
-#define CONFIG_ENV_SIZE 0x1000
-#endif
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWP)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR ( (4 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS | PLPRCR_SPLSS | PLPRCR_TMIST)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/* #define CONFIG_SYS_DER 0x2002000F */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
-
-#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXLITE mem setting */
-#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
-#define CONFIG_SYS_OR3_PRELIM 0xff7f8970
-#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
-#define CONFIG_SYS_OR4_PRELIM 0xFFF80970
-
-/* ECCX CS settings */
-#define SED13806_OR 0xFFC00108 /* - 4 Mo
- - Burst inhibit
- - external TA */
-#define SED13806_REG_ADDR 0xa0000000
-#define SED13806_ACCES 0x801 /* 16 bit access */
-
-
-/* Global definitions for the ECCX board */
-#define ECCX_CSR_ADDR (0xfac00000)
-#define ECCX_CSR8_OFFSET (0x8)
-#define ECCX_CSR11_OFFSET (0xB)
-#define ECCX_CSR12_OFFSET (0xC)
-
-#define ECCX_CSR8 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR8_OFFSET)
-#define ECCX_CSR11 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR11_OFFSET)
-#define ECCX_CSR12 (volatile unsigned char *)(ECCX_CSR_ADDR + ECCX_CSR12_OFFSET)
-
-
-#define REG_GPIO_CTRL 0x008
-
-/* Definitions for CSR8 */
-#define ECCX_ENEPSON 0x80 /* Bit 0:
- 0= disable and reset SED1386
- 1= enable SED1386 */
-/* Bit 1: 0= SED1386 in Big Endian mode */
-/* 1= SED1386 in little endian mode */
-#define ECCX_LE 0x40
-#define ECCX_BE 0x00
-
-/* Bit 2,3: Selection */
-/* 00 = Disabled */
-/* 01 = CS2 is used for the SED1386 */
-/* 10 = CS5 is used for the SED1386 */
-/* 11 = reserved */
-#define ECCX_CS2 0x10
-#define ECCX_CS5 0x20
-
-/* Definitions for CSR12 */
-#define ECCX_ID 0x02
-#define ECCX_860 0x01
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 58
-
-/*
- * Refresh clock Prescalar
- */
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 10 column SDRAM */
-#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
- MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/* Configuration variable added by yooth. */
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
-#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
-#define BCSR0_COLTEST 0x20
-#define BCSR0_ETHLPBK 0x40
-#define BCSR0_ETHEN 0x80
-
-#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
-#define BCSR1_PCVCTL6 0x02
-#define BCSR1_PCVCTL5 0x04
-#define BCSR1_PCVCTL4 0x08
-#define BCSR1_IPB5SEL 0x10
-
-#define BCSR2_MIIRST 0x80
-#define BCSR2_MIIPWRDWN 0x40
-#define BCSR2_MIICTL 0x08
-
-#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
-#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
-#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
-#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
-#define BCSR3_D27 0x10 /* Dip Switch settings */
-#define BCSR3_D26 0x20
-#define BCSR3_D25 0x40
-#define BCSR3_D24 0x80
-
-
-/*
- * Environment setting
- */
-
-/* #define CONFIG_ETHADDR 00:10:EC:00:2C:A2 */
-/* #define CONFIG_IPADDR 10.10.106.1 */
-/* #define CONFIG_SERVERIP 10.10.104.11 */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
- * U-Boot port on RPXlite board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define RPXLite_50MHz
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#undef CONFIG_MPC860
-#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
-#define CONFIG_RPXLITE 1
-
-#define CONFIG_SYS_TEXT_BASE 0xfff00000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND \
- "bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
- "bootm"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-
-#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED 40000 /* 40 kHz is supposed to work */
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-/* Software (bit-bang) I2C driver configuration */
-#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
-
-#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
-#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
-#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit) if (bit) \
- immr->im_cpm.cp_pbdat |= PB_SDA; \
- else \
- immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit) if (bit) \
- immr->im_cpm.cp_pbdat |= PB_SCL; \
- else \
- immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-
-/* M41T11 Serial Access Timekeeper(R) SRAM */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-/* play along with the linux driver */
-#define CONFIG_SYS_M41T11_BASE_YEAR 1900
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x09900000
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xFA200000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
- SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register 11-27
- *-----------------------------------------------------------------------
- */
-/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
-#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
- */
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK SCCR_EBDF00
-/* up to 50 MHz we use a 1:1 clock */
-#define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
-#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define CONFIG_SYS_DER 0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0 and OR0 (FLASH)
- */
-
-#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
-#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
-
-/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
-#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
-
-#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
-#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
-
-#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
-#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/* RPXLITE mem setting */
-#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
-#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
-#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA 58
-
-/*
- * Refresh clock Prescalar
- */
-#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 10 column SDRAM */
-#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
- MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
- MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
-
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-/* Configuration variable added by yooth. */
-/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
-
-/*
- * BCSRx
- *
- * Board Status and Control Registers
- *
- */
-
-#define BCSR0 0xFA400000
-#define BCSR1 0xFA400001
-#define BCSR2 0xFA400002
-#define BCSR3 0xFA400003
-
-#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
-#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
-#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
-#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
-#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
-#define BCSR0_COLTEST 0x20
-#define BCSR0_ETHLPBK 0x40
-#define BCSR0_ETHEN 0x80
-
-#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
-#define BCSR1_PCVCTL6 0x02
-#define BCSR1_PCVCTL5 0x04
-#define BCSR1_PCVCTL4 0x08
-#define BCSR1_IPB5SEL 0x10
-
-#define BCSR2_ENPA5HDR 0x08 /* USB Control */
-#define BCSR2_ENUSBCLK 0x10
-#define BCSR2_USBPWREN 0x20
-#define BCSR2_USBSPD 0x40
-#define BCSR2_USBSUSP 0x80
-
-#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
-#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
-#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
-#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
-#define BCSR3_D27 0x10 /* Dip Switch settings */
-#define BCSR3_D26 0x20
-#define BCSR3_D25 0x40
-#define BCSR3_D24 0x80
-
-#endif /* __CONFIG_H */
#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
/* The RPX series use SLOT_B */
-#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
+#if defined(CONFIG_RPXLITE)
# define CONFIG_PCMCIA_SLOT_B
#elif defined(CONFIG_FADS) /* The FADS series are a mess */
# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 | SCC_PSMR_LPB;
-#ifdef CONFIG_RPXCLASSIC
- *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
- *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
-#endif
-
#ifdef CONFIG_RPXLITE
*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
-#elif defined(CONFIG_RPXCLASSIC)
- udelay (100000); /* wait 100 ms */
#endif
}
~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
#endif
-#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
+#if defined(CONFIG_RPXLITE)
/* Enable Monitor Port Transceiver */
*((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
#endif
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