]> git.sur5r.net Git - u-boot/commitdiff
imx: add i.MX8MQ SoC Revision and is_mx8m helper
authorPeng Fan <peng.fan@nxp.com>
Wed, 10 Jan 2018 05:20:27 +0000 (13:20 +0800)
committerStefano Babic <sbabic@denx.de>
Sun, 4 Feb 2018 11:00:58 +0000 (12:00 +0100)
Add i.MX8MQ SoC Revision
Add is_mx8m helper
The 7ULP is a dummy number, so use 0xEx.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
arch/arm/include/asm/arch-imx/cpu.h
arch/arm/include/asm/mach-imx/sys_proto.h

index ec5b419e47099343e0f235cb3e7ae449282c97e6..470961c6f7f5bc65516dfe06401a7026cf2b1688 100644 (file)
 #define MXC_CPU_MX6QP          0x69
 #define MXC_CPU_MX7S           0x71 /* dummy ID */
 #define MXC_CPU_MX7D           0x72
-#define MXC_CPU_MX7ULP         0x81 /* Temporally hard code */
+#define MXC_CPU_MX8MQ          0x82
+#define MXC_CPU_MX7ULP         0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610          0xF6 /* dummy ID */
 
 #define MXC_SOC_MX6            0x60
 #define MXC_SOC_MX7            0x70
-#define MXC_SOC_MX7ULP         0x80 /* dummy */
+#define MXC_SOC_MX8M           0x80
+#define MXC_SOC_MX7ULP         0xE0 /* dummy */
 
 #define CHIP_REV_1_0            0x10
 #define CHIP_REV_1_1            0x11
index c53e5400a1d3c0afc26442ee3d45ac84093d6fd0..96795e18148c7a0176ee5fd3901678d91c5b8315 100644 (file)
@@ -27,6 +27,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
+#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))