This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Larry Johnson <lrj@acm.org>
config TARGET_CSB472
bool "Support csb472"
-config TARGET_KORAT
- bool "Support korat"
-
config TARGET_LWMON5
bool "Support lwmon5"
select SUPPORT_SPL
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
-source "board/korat/Kconfig"
source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
+++ /dev/null
-if TARGET_KORAT
-
-config SYS_BOARD
- default "korat"
-
-config SYS_CONFIG_NAME
- default "korat"
-
-endif
+++ /dev/null
-KORAT BOARD
-M: Larry Johnson <lrj@acm.org>
-S: Maintained
-F: board/korat/
-F: include/configs/korat.h
-F: configs/korat_defconfig
-F: configs/korat_perm_defconfig
+++ /dev/null
-#
-# (C) Copyright 2002-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = korat.o
-extra-y += init.o
+++ /dev/null
-The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
-chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
-addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
-from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
-Bank #1 (with the starting address depending on the flash size detected at
-runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
-cannot be modified in the field. This also prevents FLASH0 from executing
-commands to return chip information, so its configuration is hard-coded in
-U-Boot.
-
-There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
-permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
-0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
-located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
-for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
-used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
-0xF7FDFFFF are used for the redundant copy of the parameters. These locations
-are used by both versions of U-Boot.
-
-On booting, the permanent U-Boot in FLASH0 begins executing. After performing
-minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
-the switch is sensed as open before a timeout period, then U-Boot branches to
-address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
-beginning. If the switch remains closed thoughout the timeout period, the
-permanent U-Boot activates the on-board buzzer until the switch is sensed as
-opened. It then continues to execute without branching to FLASH1. The effect
-of this is that normally the Korat board boots its upgradable U-Boot, but, if
-this has been corrupted, the user can boot the permanent U-Boot, which can then
-be used to erase and reload FLASH1 as needed.
-
-Note that it is not necessary for the permanent U-Boot to have all the latest
-features, but only that it have sufficient functionality (working "tftp",
-"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
-assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
-sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
-
-The build sequence:
-
- make korat_perm_config
- make all
-
-builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
-preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
-
- make korat_config
- make all
-
-creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
-leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
-
-2008-02-22, Larry Johnson <lrj@acm.org>
-
-
-The CompactFlash(R) controller on the Korat board provides a hi-speed USB
-interface. This may be connected to either a dedicated port on the on-board
-USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
-environment variable "korat_usbcf" can be used to specify which of these two
-USB host ports is used for CompactFlash. The valid setting for the variable are
-the strings "pci" and "ppc". If the variable defined and set to "ppc", then the
-PowerPC USB port is used. In all other cases the on-board USB controller is
-used, but if "korat_usbcf" is defined but is set to a string other than the two
-valid options, a warning is also issued.
-
-2009-01-28, Larry Johnson <lrj@acm.org>
+++ /dev/null
-#
-# (C) Copyright 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-#
-# Korat (PPC440EPx) board
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(emul),1)
-PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
-endif
-
-ifndef CONFIG_KORAT_PERMANENT
-LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
-endif
+++ /dev/null
-/*
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
-
-tlbtab:
- tlbtab_start
-
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
-
- /*
- * TLB entries for SDRAM are not needed on this platform. They are
- * generated dynamically in the SPD DDR2 detection routine.
- */
-
-#ifdef CONFIG_SYS_INIT_RAM_DCACHE
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
- AC_RWX | SA_G )
-#endif
-
- /* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
-
- tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
-
- /* TLB-entry for EBC */
- tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
-
- /* TLB-entry for Internal Registers & OCM */
- /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
- tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
-
- /*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
-
- /* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
-
- /* TLB-entry PCI IO Space - from sr@denx.de */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
-
- tlbtab_end
-
-#if defined(CONFIG_KORAT_PERMANENT)
- .globl korat_branch_absolute
-korat_branch_absolute:
- mtlr r3
- blr
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2010
- * Larry Johnson, lrj@acm.org
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdt_support.h>
-#include <i2c.h>
-#include <libfdt.h>
-#include <asm/ppc440.h>
-#include <asm/bitops.h>
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-uic.h>
-#include <asm/processor.h>
-#include <asm/4xx_pci.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-ulong flash_get_size(ulong base, int banknum);
-
-#if defined(CONFIG_KORAT_PERMANENT)
-void korat_buzzer(int const on)
-{
- if (on) {
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
- } else {
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
- }
-}
-#endif
-
-int board_early_init_f(void)
-{
- uint32_t sdr0_pfc1, sdr0_pfc2;
- uint32_t reg;
- int eth;
-
-#if defined(CONFIG_KORAT_PERMANENT)
- unsigned mscount;
-
- extern void korat_branch_absolute(uint32_t addr);
-
- for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
- udelay(1000);
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
- /* This call does not return. */
- korat_branch_absolute(
- CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
- }
- }
- korat_buzzer(1);
- while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
- udelay(1000);
-
- korat_buzzer(0);
-#endif
-
- mtdcr(EBC0_CFGADDR, EBC0_CFG);
- mtdcr(EBC0_CFGDATA, 0xb8400000);
-
- /*
- * Setup the interrupt controller polarities, triggers, etc.
- */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
- mtdcr(UIC0ER, 0x00000000); /* disable all */
- mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
- mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
- mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC0SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
- mtdcr(UIC1ER, 0x00000000); /* disable all */
- mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC1SR, 0xffffffff); /* clear all */
-
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
- mtdcr(UIC2ER, 0x00000000); /* disable all */
- mtdcr(UIC2CR, 0x00000000); /* all non-critical */
- mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
- mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
- mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
- mtdcr(UIC2SR, 0xffffffff); /* clear all */
-
- /*
- * Take sim card reader and CF controller out of reset. Also enable PHY
- * auto-detect until board-specific PHY resets are available.
- */
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
-
- /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
- * if the SFP module is present, and for copper if it is not present.
- */
- for (eth = 0; eth < 2; ++eth) {
- if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
- /* SFP module not present: configure PHY for copper. */
- /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
- 0x06 << (4 * eth));
- } else {
- /* SFP module present: configure PHY for fiber and
- enable output */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
- }
- }
- /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
- gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
- gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
-
- /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
- udelay(1000);
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
-
- /* select Ethernet (and optionally IIC1) pins */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
- SDR0_PFC1_SELECT_CONFIG_4;
-#ifdef CONFIG_I2C_MULTI_BUS
- sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
-#endif
- mfsdr(SDR0_PFC2, sdr0_pfc2);
- sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
- SDR0_PFC2_SELECT_CONFIG_4;
- mtsdr(SDR0_PFC2, sdr0_pfc2);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* PCI arbiter enabled */
- mfsdr(SDR0_PCI0, reg);
- mtsdr(SDR0_PCI0, 0x80000000 | reg);
-
- return 0;
-}
-
-/*
- * The boot flash on CS0 normally has its write-enable pin disabled, and so will
- * not respond to CFI commands. This routine therefore fills in the flash
- * information for the boot flash. (The flash at CS1 operates normally.)
- */
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
-{
- uint32_t addr;
- int i;
-
- if (1 != banknum)
- return 0;
-
- info->size = CONFIG_SYS_FLASH0_SIZE;
- info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
- info->flash_id = 0x01000000;
- info->portwidth = 2;
- info->chipwidth = 2;
- info->buffer_size = 32;
- info->erase_blk_tout = 16384;
- info->write_tout = 2;
- info->buffer_write_tout = 5;
- info->vendor = 2;
- info->cmd_reset = 0x00F0;
- info->interface = 2;
- info->legacy_unlock = 0;
- info->manufacturer_id = 1;
- info->device_id = 0x007E;
-
-#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
- info->device_id2 = 0x2101;
-#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
- info->device_id2 = 0x2301;
-#else
-#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
-#endif
-
- info->ext_addr = 0x0040;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x0055;
- info->addr_unlock1 = 0x00000555;
- info->addr_unlock2 = 0x000002AA;
- info->name = "CFI conformant";
- for (i = 0, addr = -info->size;
- i < info->sector_count;
- ++i, addr += 0x20000) {
- info->start[i] = addr;
- info->protect[i] = 0x00;
- }
- return 1;
-}
-
-static int man_data_read(unsigned int addr)
-{
- /*
- * Read an octet of data from address "addr" in the manufacturer's
- * information serial EEPROM, or -1 on error.
- */
- u8 data[2];
-
- if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
- 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
- debug("man_data_read(0x%02X) failed\n", addr);
- return -1;
- }
- debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
- return data[0];
-}
-
-static unsigned int man_data_field_addr(unsigned int const field)
-{
- /*
- * The manufacturer's information serial EEPROM contains a sequence of
- * zero-delimited fields. Return the starting address of field "field",
- * or 0 on error.
- */
- unsigned addr, i;
-
- if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
- /* Only format "A" is currently supported */
- return 0;
-
- for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
- if ('\0' == man_data_read(addr))
- ++i;
- }
- return (addr < 256) ? addr : 0;
-}
-
-static char *man_data_read_field(char s[], unsigned const field,
- unsigned const length)
-{
- /*
- * Place the null-terminated contents of field "field" of length
- * "length" from the manufacturer's information serial EEPROM into
- * string "s[length + 1]" and return a pointer to s, or return 0 on
- * error. In either case the original contents of s[] is not preserved.
- */
- unsigned addr, i;
-
- addr = man_data_field_addr(field);
- if (0 == addr || addr + length >= 255)
- return 0;
-
- for (i = 0; i < length; ++i) {
- int const c = man_data_read(addr++);
-
- if (c <= 0)
- return 0;
-
- s[i] = (char)c;
- }
- if (0 != man_data_read(addr))
- return 0;
-
- s[i] = '\0';
- return s;
-}
-
-static void set_serial_number(void)
-{
- /*
- * If the environmental variable "serial#" is not set, try to set it
- * from the manufacturer's information serial EEPROM.
- */
- char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
-
- if (getenv("serial#"))
- return;
-
- if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
- return;
-
- s[MAN_INFO_LENGTH] = '-';
- if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
- MAN_MAC_ADDR_LENGTH))
- return;
-
- setenv("serial#", s);
-}
-
-static void set_mac_addresses(void)
-{
- /*
- * If the environmental variables "ethaddr" and/or "eth1addr" are not
- * set, try to set them from the manufacturer's information serial
- * EEPROM.
- */
-
-#if MAN_MAC_ADDR_LENGTH % 2 != 0
-#error MAN_MAC_ADDR_LENGTH must be an even number
-#endif
-
- char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
- char *src;
- char *dst;
-
- if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
- return;
-
- if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
- MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
- return;
-
- for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
- *dst++ = *src++;
- *dst++ = *src++;
- *dst++ = ':';
- }
- if (0 == getenv("ethaddr"))
- setenv("ethaddr", s);
-
- if (0 == getenv("eth1addr")) {
- ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
- setenv("eth1addr", s);
- }
-}
-
-int misc_init_r(void)
-{
- uint32_t pbcr;
- int size_val;
- uint32_t reg;
- unsigned long usb2d0cr = 0;
- unsigned long usb2phy0cr, usb2h0cr = 0;
- unsigned long sdr0_pfc1;
- uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
- char const *const act = getenv("usbact");
- char const *const usbcf = getenv("korat_usbcf");
-
- /*
- * Re-do FLASH1 sizing and adjust flash start and offset.
- */
- gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
- gd->bd->bi_flashoffset = 0;
-
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(flash1_size) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, 0);
-
- /*
- * Re-do FLASH1 sizing and adjust flash offset to reserve space for
- * environment
- */
- gd->bd->bi_flashoffset =
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
-
- mtdcr(EBC0_CFGADDR, PB1CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
- pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtdcr(EBC0_CFGADDR, PB1CR);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
-#if defined(CONFIG_KORAT_PERMANENT)
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- flash_info + 1);
-#else
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
- flash_info);
-#endif
- /* Env protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- flash_info);
- (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- flash_info);
-
- /*
- * USB suff...
- */
- /*
- * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
- * ("pci") for the CompactFlash.
- */
- if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
- /*
- * If environment variable "usbcf" is defined and set to "ppc",
- * then connect the CompactFlash controller to the PowerPC USB
- * port.
- */
- printf("Attaching CompactFlash controller to PPC USB\n");
- out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
- in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
- } else {
- if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
- printf("Warning: \"korat_usbcf\" is not set to a legal "
- "value (\"ppc\" or \"pci\")\n");
-
- printf("Attaching CompactFlash controller to PCI USB\n");
- }
- if (act == NULL || strcmp(act, "hostdev") == 0) {
- /* SDR Setting */
- mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
-
- /*
- * An 8-bit/60MHz interface is the only possible alternative
- * when connecting the Device to the PHY
- */
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
-
- /*
- * To enable the USB 2.0 Device function
- * through the UTMI interface
- */
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
-
- mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
-
- /* clear resets */
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Host(int phy) Device(ext phy)\n");
-
- } else if (strcmp(act, "dev") == 0) {
- /*-------------------PATCH-------------------------------*/
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x672c6000);
-
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000080);
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x60206000);
-
- *(unsigned int *)(0xe0000350) = 0x00000001;
-
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x60306000);
- /*-------------------PATCH-------------------------------*/
-
- /* SDR Setting */
- mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB2D0CR, usb2d0cr);
- mfsdr(SDR0_PFC1, sdr0_pfc1);
-
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
- usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
- usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
-
- usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
- usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
-
- usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
- usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
-
- sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
- sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
-
- mtsdr(SDR0_USB2H0CR, usb2h0cr);
- mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB2D0CR, usb2d0cr);
- mtsdr(SDR0_PFC1, sdr0_pfc1);
-
- /* clear resets */
- udelay(1000);
- mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
- mtsdr(SDR0_SRST0, 0x00000000);
-
- printf("USB: Device(int phy)\n");
- }
-
- mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
- reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
- mtsdr(SDR0_SRST1, reg);
-
- /*
- * Clear PLB4A0_ACR[WRP]
- * This fix will make the MAL burst disabling patch for the Linux
- * EMAC driver obsolete.
- */
- reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
- mtdcr(PLB4A0_ACR, reg);
-
- set_serial_number();
- set_mac_addresses();
- gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
-
- return 0;
-}
-
-int checkboard(void)
-{
- char const *const s = getenv("serial#");
- u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
-
- printf("Board: Korat, Rev. %X", rev);
- if (s)
- printf(", serial# %s", s);
-
- printf(".\n Ethernet PHY 0: ");
- if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
- printf("fiber");
- else
- printf("copper");
-
- printf(", PHY 1: ");
- if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
- printf("fiber");
- else
- printf("copper");
-
- printf(".\n");
-#if defined(CONFIG_KORAT_PERMANENT)
- printf(" Executing permanent copy of U-Boot.\n");
-#endif
- return 0;
-}
-
-#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
-/*
- * Assign interrupts to PCI devices.
- */
-void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
-}
-#endif
-
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /* First do 440EP(x) common setup */
- __pci_target_init(hose);
-
- /*
- * Set up Configuration registers for on-board NEC uPD720101 USB
- * controller.
- */
- pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
- u32 val[4];
- int rc;
-
- ft_cpu_setup(blob, bd);
-
- /* Fixup NOR mapping */
- val[0] = 1; /* chip select number */
- val[1] = 0; /* always 0 */
- val[2] = gd->bd->bi_flashstart;
- val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
- rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
- val, sizeof(val), 1);
- if (rc)
- printf("Unable to update property NOR mapping, err=%s\n",
- fdt_strerror(rc));
-
- return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- .resetvec 0xF7FBFFFC :
- {
- *(.resetvec)
- } = 0xffff
-
- .bootpg 0xF7FBF000 :
- {
- arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
- } = 0xffff
-
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- }
-
- __bss_end = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KORAT=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="KORAT_PERMANENT"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_KORAT=y
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
+++ /dev/null
-/*
- * (C) Copyright 2007-2009
- * Larry Johnson, lrj@acm.org
- *
- * (C) Copyright 2006-2007
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * korat.h - configuration for Korat board
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_440EPX 1 /* Specific PPC440EPx */
-#define CONFIG_SYS_CLK_FREQ 33333333
-
-#ifdef CONFIG_KORAT_PERMANENT
-#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
-#else
-#define CONFIG_SYS_TEXT_BASE 0xF7F60000
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
-
-/*
- * Manufacturer's information serial EEPROM parameters
- */
-#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
-#define MAN_INFO_FIELD 2
-#define MAN_INFO_LENGTH 9
-#define MAN_MAC_ADDR_FIELD 3
-#define MAN_MAC_ADDR_LENGTH 12
-
-/*
- * Base addresses -- Note these are effective addresses where the actual
- * resources get mapped (not physical addresses).
- */
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH0_SIZE 0x01000000
-#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
-#define CONFIG_SYS_FLASH1_TOP 0xF8000000
-#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
-#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
-#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
-
-#define CONFIG_SYS_USB2D0_BASE 0xe0000100
-#define CONFIG_SYS_USB_DEVICE 0xe0000000
-#define CONFIG_SYS_USB_HOST 0xe0000400
-#define CONFIG_SYS_CPLD_BASE 0xc0000000
-
-/*
- * Initial RAM & stack pointer
- */
-/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
-#undef CONFIG_SYS_INIT_RAM_DCACHE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
-
-/*
- * FLASH related
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*
- * DDR SDRAM
- */
-#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
-#define CONFIG_DDR_ECC /* Use ECC when available */
-#define SPD_EEPROM_ADDRESS {0x50}
-#define CONFIG_PROG_SDRAM_TLB
-#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
- /* per 440EPx Errata CHIP_11 */
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_MULTI_EEPROMS
-#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-/* I2C RTC */
-#define CONFIG_RTC_M41T60 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/* I2C SYSMON (LM73) */
-#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
-#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_MIN_TEMP -30
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-/* Setup some board specific values for the default environment variables */
-#define CONFIG_HOSTNAME korat
-
-/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "u_boot=korat/u-boot.bin\0" \
- "load=tftp 200000 ${u_boot}\0" \
- "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
- "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
- "F7F60000 F7FBFFFF\0" \
- "upd=run load update\0" \
- "bootfile=korat/uImage\0" \
- "dtb=korat/korat.dtb\0" \
- "kernel_addr=F4000000\0" \
- "ramdisk_addr=F4400000\0" \
- "dtb_addr=F41E0000\0" \
- "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
- "cp.b ${fileaddr} F4000000 ${filesize}\0" \
- "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
- "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
- "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
- "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
- "${dtb}\0" \
- "rd_size=73728\0" \
- "ramargs=setenv bootargs root=/dev/ram rw " \
- "ramdisk_size=${rd_size}\0" \
- "usbdev=sda1\0" \
- "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
- "rootpath=/opt/eldk/ppc_4xxFP\0" \
- "netdev=eth0\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "pciclk=33\0" \
- "addide=setenv bootargs ${bootargs} ide=reverse " \
- "idebus=${pciclk}\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
- "flash_cf=run usbargs addide addip addtty; " \
- "bootm ${kernel_addr} - ${dtb_addr}\0" \
- "flash_nfs=run nfsargs addide addip addtty; " \
- "bootm ${kernel_addr} - ${dtb_addr}\0" \
- "flash_self=run ramargs addip addtty; " \
- "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_cf"
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_IBM_EMAC4_V4 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
-#define CONFIG_PHY_DYNAMIC_ANEG 1
-
-#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
- /* buffers & descriptors */
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_PHY1_ADDR 3
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/* Comment this out to enable USB 1.1 device */
-#define USB_2_0_DEVICE
-
-/* Partitions */
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_USB
-
-/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
- CONFIG_SYS_POST_CPU | \
- CONFIG_SYS_POST_ECC | \
- CONFIG_SYS_POST_ETHER | \
- CONFIG_SYS_POST_FPU | \
- CONFIG_SYS_POST_I2C | \
- CONFIG_SYS_POST_MEMORY | \
- CONFIG_SYS_POST_RTC | \
- CONFIG_SYS_POST_SPR | \
- CONFIG_SYS_POST_UART)
-
-#define CONFIG_LOGBUFFER
-#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*
- * Korat-specific options
- */
-#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
-
-/*
- * PCI stuff
- */
-/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
- /* CONFIG_SYS_PCI_MEMBASE */
-/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT
-#define CONFIG_SYS_PCI_MASTER_INIT
-#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
-#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
-
-/*
- * For booting Linux, the board info and command line data have to be in the
- * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
- * during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (NOR-FLASH) initialization */
-#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
-#define CONFIG_SYS_EBC_PB0AP 0x04017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
-#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
-#define CONFIG_SYS_EBC_PB0AP 0x04017300
-#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
-#else
-#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
-#endif
-
-/* Memory Bank 1 (NOR-FLASH) initialization */
-#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
-#define CONFIG_SYS_EBC_PB1AP 0x04017300
-#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
-#else
-#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
-#endif
-
-/* Memory Bank 2 (CPLD) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x04017300
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
-
-/*
- * GPIO Setup
- *
- * Korat GPIO usage:
- *
- * Init.
- * Pin Source I/O value Function
- * ------ ------ --- ----- ---------------------------------
- * GPIO00 Alt1 I/O x PerAddr07
- * GPIO01 Alt1 I/O x PerAddr06
- * GPIO02 Alt1 I/O x PerAddr05
- * GPIO03 GPIO x x GPIO03 to expansion bus connector
- * GPIO04 GPIO x x GPIO04 to expansion bus connector
- * GPIO05 GPIO x x GPIO05 to expansion bus connector
- * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
- * GPIO07 Alt1 O x PerCS2 (CPLD)
- * GPIO08 Alt1 O x PerCS3 to expansion bus connector
- * GPIO09 Alt1 O x PerCS4 to expansion bus connector
- * GPIO10 Alt1 O x PerCS5 to expansion bus connector
- * GPIO11 Alt1 I x PerErr
- * GPIO12 GPIO O 0 ATMega !Reset
- * GPIO13 GPIO x x Test Point 2 (TP2)
- * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
- * GPIO15 GPIO O 0 CPU Run LED !On
- * GPIO16 Alt1 O x GMC1TxD0
- * GPIO17 Alt1 O x GMC1TxD1
- * GPIO18 Alt1 O x GMC1TxD2
- * GPIO19 Alt1 O x GMC1TxD3
- * GPIO20 Alt1 I x RejectPkt0
- * GPIO21 Alt1 I x RejectPkt1
- * GPIO22 GPIO I x PGOOD_DDR
- * GPIO23 Alt1 O x SCPD0
- * GPIO24 Alt1 O x GMC0TxD2
- * GPIO25 Alt1 O x GMC0TxD3
- * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
- * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
- * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
- * GPIO29 GPIO I x Test jumper !Present
- * GPIO30 GPIO I x SFP module #0 !Present
- * GPIO31 GPIO I x SFP module #1 !Present
- *
- * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
- * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
- * GPIO34 Alt2 I x !UART1_CTS
- * GPIO35 Alt2 O x !UART1_RTS
- * GPIO36 Alt1 I x !UART0_CTS
- * GPIO37 Alt1 O x !UART0_RTS
- * GPIO38 Alt2 O x UART1_Tx
- * GPIO39 Alt2 I x UART1_Rx
- * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
- * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
- * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
- * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
- * GPIO44 xxxx x x (grounded through pulldown)
- * GPIO45 GPIO O 0 PHY #0 Enable
- * GPIO46 GPIO O 0 PHY #1 Enable
- * GPIO47 GPIO I x Reset switch !Pressed
- * GPIO48 GPIO I x Shutdown switch !Pressed
- * GPIO49 xxxx x x (reserved for trace port)
- * . . . . .
- * . . . . .
- * . . . . .
- * GPIO63 xxxx x x (reserved for trace port)
- */
-
-#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
-#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
-#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
-#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
-#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
-#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
-#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
-#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
-#define CONFIG_SYS_GPIO_PHY0_EN 45
-#define CONFIG_SYS_GPIO_PHY1_EN 46
-#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
-
-/*
- * PPC440 GPIO Configuration
- */
-#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
-{ \
-/* GPIO Core 0 */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
-{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
-{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
-{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
-}, \
-{ \
-/* GPIO Core 1 */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
-{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
-{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
-{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
-} \
-}
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/* Pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
projects / u-boot / commitdiff