]> git.sur5r.net Git - u-boot/commitdiff
T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
authorZhao Qiang <B45475@freescale.com>
Thu, 26 Mar 2015 08:13:09 +0000 (16:13 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 4 May 2015 16:24:16 +0000 (09:24 -0700)
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
drivers/pci/fsl_pci_init.c
include/configs/T208xQDS.h

index 231b07573f5b15a35c472bbf8c6cfcb124166412..152045ed93d26230581a8d641d94eea11420e2ae 100644 (file)
@@ -444,6 +444,21 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
                        ltssm = (in_be32(&pci->pex_csr0)
                                & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
                        enabled = (ltssm == 0x11) ? 1 : 0;
+#ifdef CONFIG_FSL_PCIE_RESET
+                       int i;
+                       /* assert PCIe reset */
+                       setbits_be32(&pci->pdb_stat, 0x08000000);
+                       (void) in_be32(&pci->pdb_stat);
+                       udelay(1000);
+                       /* clear PCIe reset */
+                       clrbits_be32(&pci->pdb_stat, 0x08000000);
+                       asm("sync;isync");
+                       for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
+                               pci_hose_read_config_word(hose, dev, PCI_LTSSM,
+                                                         &ltssm);
+                               udelay(1000);
+                       }
+#endif
                } else {
                /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
                /* enabled = ltssm >= PCI_LTSSM_L0; */
index 046aa48baa1c0330c5efb3e0d67444eb146d5a15..6adcb22521f503c4ca4dd8de1e999623d85987e6 100644 (file)
@@ -575,6 +575,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_PCIE2           /* PCIE controler 2 */
 #define CONFIG_PCIE3           /* PCIE controler 3 */
 #define CONFIG_PCIE4           /* PCIE controler 4 */
+#define CONFIG_FSL_PCIE_RESET
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */