powerpc/85xx: Add support for Book-E MMU Arch v2.0

A few of the config registers changed definition between MMU v1.0 and
MMUv2.0.  The new e6500 core from Freescale implements v2.0 of the
architecture.

Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 01a3561fa0e76091d18870f41e7b373245e03cf6..80ad04a735a13ddbba5b3131b4d6bb909dc2517a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -252,16 +252,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
        unsigned int tlb_size;
        unsigned int wimge = 0;
        unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-       unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+       unsigned int max_cam;
        u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
        wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 #endif
        size = min(memsize, CONFIG_MAX_MEM_MAPPED);
-
-       /* Convert (4^max) kB to (2^max) bytes */
-       max_cam = max_cam * 2 + 10;
+       if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+               /* Convert (4^max) kB to (2^max) bytes */
+               max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+       } else {
+               /* Convert (2^max) kB to (2^max) bytes */
+               max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+       }
 
        for (i = 0; size && i < 8; i++) {
                int ram_tlb_index = find_free_tlbcam();

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1b96b84dcb57337f0a664253c05de0ad142b2e14..4e326398216de082867abf39442c9c9d967173c4 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -513,7 +513,13 @@
 
 #define SPRN_TLB0CFG   0x2B0   /* TLB 0 Config Register */
 #define SPRN_TLB1CFG   0x2B1   /* TLB 1 Config Register */
+#define SPRN_TLB0PS    0x158   /* TLB 0 Page Size Register */
+#define SPRN_TLB1PS    0x159   /* TLB 1 Page Size Register */
 #define SPRN_MMUCSR0   0x3f4   /* MMU control and status register 0 */
+#define SPRN_MMUCFG    0x3F7   /* MMU Configuration Register */
+#define MMUCFG_MAVN    0x00000003      /* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1 0x00000000      /* v1.0 */
+#define MMUCFG_MAVN_V2 0x00000001      /* v2.0 */
 #define SPRN_MAS0      0x270   /* MMU Assist Register 0 */
 #define SPRN_MAS1      0x271   /* MMU Assist Register 1 */
 #define SPRN_MAS2      0x272   /* MMU Assist Register 2 */