Blackfin: unify cache handling code

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c
index 0c799325c63c2517aadde74435dae5399332825c..9efd88e7ec9c87df91333bd714126bafd3f4f67d 100644 (file)
--- a/cpu/blackfin/cpu.c
+++ b/cpu/blackfin/cpu.c
@@ -14,46 +14,11 @@
 #include <asm/blackfin.h>
 #include <asm/cplb.h>
 #include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
 #include <asm/mach-common/bits/trace.h>
 
 #include "cpu.h"
 #include "serial.h"
 
-void icache_enable(void)
-{
-       bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
-       SSYNC();
-}
-
-void icache_disable(void)
-{
-       bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
-       SSYNC();
-}
-
-int icache_status(void)
-{
-       return bfin_read_IMEM_CONTROL() & ENICPLB;
-}
-
-void dcache_enable(void)
-{
-       bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
-       SSYNC();
-}
-
-void dcache_disable(void)
-{
-       bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
-       SSYNC();
-}
-
-int dcache_status(void)
-{
-       return bfin_read_DMEM_CONTROL() & ENDCPLB;
-}
-
 __attribute__ ((__noreturn__))
 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 {

diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index c2f6e2848ef1db7750ba03edfb41de2ae55f9adf..41e2a62d12d3d587b9d42e5e0f9c761e0df341b9 100644 (file)
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
 
 void flush_cache(unsigned long addr, unsigned long size)
 {
@@ -24,3 +25,37 @@ void flush_cache(unsigned long addr, unsigned long size)
        if (dcache_status())
                blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
 }
+
+void icache_enable(void)
+{
+       bfin_write_IMEM_CONTROL(IMC | ENICPLB);
+       SSYNC();
+}
+
+void icache_disable(void)
+{
+       bfin_write_IMEM_CONTROL(0);
+       SSYNC();
+}
+
+int icache_status(void)
+{
+       return bfin_read_IMEM_CONTROL() & ENICPLB;
+}
+
+void dcache_enable(void)
+{
+       bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+       SSYNC();
+}
+
+void dcache_disable(void)
+{
+       bfin_write_DMEM_CONTROL(0);
+       SSYNC();
+}
+
+int dcache_status(void)
+{
+       return bfin_read_DMEM_CONTROL() & ENDCPLB;
+}