}
 
 int dram_init(void)
+{
+       /* dram_init must store complete ramsize in gd->ram_size */
+       gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM,
+                               PHYS_SDRAM_SIZE);
+       return 0;
+}
+
+void dram_init_banksize(void)
 {
        gd->bd->bi_dram[0].start = PHYS_SDRAM;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
-       return 0;
 }
 
 #ifdef CONFIG_RESET_PHY_R
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK     12000000 /* from 12 MHz crystal */
 #define CONFIG_SYS_HZ                  1000
+#define CONFIG_SYS_TEXT_BASE   0x73f00000
+#define CONFIG_AT91FAMILY
 
 #define CONFIG_ARCH_CPU_INIT
 
 #define CONFIG_SYS_MALLOC_LEN          ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
                                        0x1000)
 
+#define CONFIG_SYS_SDRAM_BASE  PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+                               GENERATED_GBL_DATA_SIZE)
+
 #define CONFIG_STACKSIZE               (32*1024)       /* regular stack */
 
 #ifdef CONFIG_USE_IRQ