stv0991: configure device tree for cadence qspi & flash

This patch add the device tree entry for qspi controller & spi flash
memory.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts
index b25c48bcecf9b00b84aa57fe547967e40bb5dee8..3b1efca3730ebdac6fd82c889e138a81978e3fd6 100644 (file)
--- a/arch/arm/dts/stv0991.dts
+++ b/arch/arm/dts/stv0991.dts
@@ -20,4 +20,38 @@
                reg = <0x80406000 0x1000>;
                clock = <2700000>;
        };
+
+       aliases {
+               spi0 = "/spi@80203000";         /* QSPI */
+       };
+
+       qspi: spi@80203000 {
+                       compatible = "cadence,qspi";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x80203000 0x100>,
+                               <0x40000000 0x1000000>;
+                       clocks = <3750000>;
+                       ext-decoder = <0>; /* external decoder */
+                       num-cs = <4>;
+                       fifo-depth = <256>;
+                       bus-num = <0>;
+                       status = "okay";
+
+                       flash0: n25q32@0 {
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               compatible = "spi-flash";
+                               reg = <0>;              /* chip select */
+                               spi-max-frequency = <50000000>;
+                               m25p,fast-read;
+                               page-size = <256>;
+                               block-size = <16>;      /* 2^16, 64KB */
+                               read-delay = <4>;       /* delay value in read data capture register */
+                               tshsl-ns = <50>;
+                               tsd2d-ns = <50>;
+                               tchsh-ns = <4>;
+                               tslch-ns = <4>;
+                       };
+       };
 };