writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
- if (count_value == 0) {
- /* reset initial value */
- /* count_value = 2085937.5(HZ) (per 1 sec)*/
- count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
- (MUX_DIV_2 + 1));
-
- /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
- count_value = count_value / 100;
- }
+ /* count_value = 2085937.5(HZ) (per 1 sec)*/
+ count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
+ (MUX_DIV_2 + 1));
+
+ /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
+ count_value = count_value / 100;
/* set count value */
writel(count_value, &timer->tcntb4);
/* delay x useconds */
void __udelay(unsigned long usec)
{
+ struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long tmo, tmp;
+ count_value = readl(&timer->tcntb4);
+
if (usec >= 1000) {
/*
* if "big" number, spread normalization
}
int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE +
+ PHYS_SDRAM_3_SIZE;
+
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
-
- return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
- PHYS_SDRAM_1_SIZE);
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{