]> git.sur5r.net Git - u-boot/commitdiff
ARM: tegra: Add CPU (armv7) files for Tegra124
authorTom Warren <twarren.nvidia@gmail.com>
Fri, 24 Jan 2014 19:46:15 +0000 (12:46 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 3 Feb 2014 16:46:46 +0000 (09:46 -0700)
These files are for code that runs on the CPU (A15) on Tegra124 boards.
At this time, there is no A15-specific code here. The warmboot/LP0 files
aren't included as that code hasn't been ported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
arch/arm/cpu/armv7/tegra124/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/tegra124/config.mk [new file with mode: 0644]
arch/arm/cpu/tegra124-common/Makefile [new file with mode: 0644]
arch/arm/cpu/tegra124-common/clock.c [new file with mode: 0644]
arch/arm/cpu/tegra124-common/funcmux.c [new file with mode: 0644]
arch/arm/cpu/tegra124-common/pinmux.c [new file with mode: 0644]

diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644 (file)
index 0000000..7f127b1
--- /dev/null
@@ -0,0 +1,6 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
diff --git a/arch/arm/cpu/armv7/tegra124/config.mk b/arch/arm/cpu/armv7/tegra124/config.mk
new file mode 100644 (file)
index 0000000..2f1c645
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+CONFIG_ARCH_DEVICE_TREE := tegra124
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
new file mode 100644 (file)
index 0000000..ff77992
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += clock.o
+obj-y  += funcmux.o
+obj-y  += pinmux.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
new file mode 100644 (file)
index 0000000..7394363
--- /dev/null
@@ -0,0 +1,826 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+       CLOCK_TYPE_AXPT,        /* PLL_A, PLL_X, PLL_P, CLK_M */
+       CLOCK_TYPE_MCPA,        /* and so on */
+       CLOCK_TYPE_MCPT,
+       CLOCK_TYPE_PCM,
+       CLOCK_TYPE_PCMT,
+       CLOCK_TYPE_PDCT,
+       CLOCK_TYPE_ACPT,
+       CLOCK_TYPE_ASPTE,
+       CLOCK_TYPE_PMDACD2T,
+       CLOCK_TYPE_PCST,
+
+       CLOCK_TYPE_PC2CC3M,
+       CLOCK_TYPE_PC2CC3S_T,
+       CLOCK_TYPE_PC2CC3M_T,
+       CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
+       CLOCK_TYPE_MC2CC3P_A,
+       CLOCK_TYPE_M,
+       CLOCK_TYPE_MCPTM2C2C3,
+       CLOCK_TYPE_PC2CC3T_S,
+       CLOCK_TYPE_AC2CC3P_TS2,
+
+       CLOCK_TYPE_COUNT,
+       CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+       CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+       { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(AUDIO),   CLK(SFROM32KHZ),        CLK(PERIPH),    CLK(OSC),
+               CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_29},
+       { CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
+               CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_28},
+
+       /* Additional clock types on Tegra114+ */
+       /* CLOCK_TYPE_PC2CC3M */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(MEMORY),    CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3S_T */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(SFROM32KHZ), CLK(NONE),     CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3M_T */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(MEMORY),    CLK(NONE),      CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(MEMORY),    CLK(NONE),      CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_MC2CC3P_A */
+       { CLK(MEMORY),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(PERIPH),    CLK(NONE),      CLK(AUDIO),     CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_M */
+       { CLK(MEMORY),          CLK(NONE),      CLK(NONE),      CLK(NONE),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       /* CLOCK_TYPE_MCPTM2C2C3 */
+       { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+               CLK(MEMORY2),   CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3T_S */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(OSC),       CLK(NONE),      CLK(SFROM32KHZ), CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_AC2CC3P_TS2 */
+       { CLK(AUDIO),   CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(PERIPH),    CLK(NONE),      CLK(OSC),       CLK(SRC2),
+               MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+       /* 0x00 */
+       TYPE(PERIPHC_I2S1,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PC2CC3M),
+       TYPE(PERIPHC_PWM,       CLOCK_TYPE_PC2CC3S_T),
+       TYPE(PERIPHC_05h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x08 */
+       TYPE(PERIPHC_08h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_I2C5,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_0bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_0ch,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
+       TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
+
+       /* 0x10 */
+       TYPE(PERIPHC_10h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_11h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_VI,        CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_13h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_SDMMC2,    CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_16h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_17h,       CLOCK_TYPE_NONE),
+
+       /* 0x18 */
+       TYPE(PERIPHC_18h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SDMMC4,    CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_1Bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_1Ch,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_HSI,       CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_UART1,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_UART2,     CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x20 */
+       TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_21h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_22h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
+       TYPE(PERIPHC_24h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_25h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_EMC,       CLOCK_TYPE_MCPTM2C2C3),
+
+       /* 0x28 */
+       TYPE(PERIPHC_UART3,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_29h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_2bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_2ch,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x30 */
+       TYPE(PERIPHC_UART4,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_UART5,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_VDE,       CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_OWR,       CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_NOR,       CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_DTV,       CLOCK_TYPE_NONE),
+
+       /* 0x38 */
+       TYPE(PERIPHC_38h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_39h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_3ah,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_3bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_MSENC,     CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_TSEC,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_3eh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_OSC,       CLOCK_TYPE_NONE),
+
+       /* 0x40 */
+       TYPE(PERIPHC_40h,       CLOCK_TYPE_NONE),       /* start with 0x3b0 */
+       TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PC2CC3T_S),
+       TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x48 */
+       TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_AC2CC3P_TS2),
+       TYPE(PERIPHC_49h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_DAM0,      CLOCK_TYPE_AC2CC3P_TS2),
+       TYPE(PERIPHC_DAM1,      CLOCK_TYPE_AC2CC3P_TS2),
+       TYPE(PERIPHC_DAM2,      CLOCK_TYPE_AC2CC3P_TS2),
+       TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PC2CC3S_T),
+       TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+       /* 0x50 */
+       TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+       TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+       TYPE(PERIPHC_52h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PC2CC3S_T),
+       TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_55h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_56h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_57h,       CLOCK_TYPE_NONE),
+
+       /* 0x58 */
+       TYPE(PERIPHC_58h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_59h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_5ah,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_5bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),
+       TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
+       TYPE(PERIPHC_HDA,       CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_5fh,       CLOCK_TYPE_NONE),
+
+       /* 0x60 */
+       TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_XUSB_FS,   CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_XUSB_SS,   CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_CILAB,     CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_CILCD,     CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_CILE,      CLOCK_TYPE_NONE),
+
+       /* 0x68 */
+       TYPE(PERIPHC_DSIA_LP,   CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_DSIB_LP,   CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_ENTROPY,   CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_DVFS_REF,  CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_DVFS_SOC,  CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_ADX0,      CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_AMX0,      CLOCK_TYPE_NONE),
+
+       /* 0x70 */
+       TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_72h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_73h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_74h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_75h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_I2C6,      CLOCK_TYPE_PC2CC3M_T16),
+
+       /* 0x78 */
+       TYPE(PERIPHC_78h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_EMC_DLL,   CLOCK_TYPE_MCPTM2C2C3),
+       TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_CLK72MHZ,  CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_ADX1,      CLOCK_TYPE_AC2CC3P_TS2),
+       TYPE(PERIPHC_AMX1,      CLOCK_TYPE_AC2CC3P_TS2),
+       TYPE(PERIPHC_VIC,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_7Fh,       CLOCK_TYPE_NONE),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ *     uint vi_sensor;  _VI_SENSOR_0,          0x1A8
+ *     SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+       /* Low word: 31:0 */
+       NONE(CPU),
+       NONE(COP),
+       NONE(TRIGSYS),
+       NONE(ISPB),
+       NONE(RESERVED4),
+       NONE(TMR),
+       PERIPHC_UART1,
+       PERIPHC_UART2,  /* and vfir 0x68 */
+
+       /* 8 */
+       NONE(GPIO),
+       PERIPHC_SDMMC2,
+       PERIPHC_SPDIF_IN,
+       PERIPHC_I2S1,
+       PERIPHC_I2C1,
+       NONE(RESERVED13),
+       PERIPHC_SDMMC1,
+       PERIPHC_SDMMC4,
+
+       /* 16 */
+       NONE(TCW),
+       PERIPHC_PWM,
+       PERIPHC_I2S2,
+       NONE(RESERVED19),
+       PERIPHC_VI,
+       NONE(RESERVED21),
+       NONE(USBD),
+       NONE(ISP),
+
+       /* 24 */
+       NONE(RESERVED24),
+       NONE(RESERVED25),
+       PERIPHC_DISP2,
+       PERIPHC_DISP1,
+       PERIPHC_HOST1X,
+       NONE(VCP),
+       PERIPHC_I2S0,
+       NONE(CACHE2),
+
+       /* Middle word: 63:32 */
+       NONE(MEM),
+       NONE(AHBDMA),
+       NONE(APBDMA),
+       NONE(RESERVED35),
+       NONE(RESERVED36),
+       NONE(STAT_MON),
+       NONE(RESERVED38),
+       NONE(FUSE),
+
+       /* 40 */
+       NONE(KFUSE),
+       PERIPHC_SBC1,           /* SBCx = SPIx */
+       PERIPHC_NOR,
+       NONE(RESERVED43),
+       PERIPHC_SBC2,
+       NONE(XIO),
+       PERIPHC_SBC3,
+       PERIPHC_I2C5,
+
+       /* 48 */
+       NONE(DSI),
+       NONE(RESERVED49),
+       PERIPHC_HSI,
+       PERIPHC_HDMI,
+       NONE(CSI),
+       NONE(RESERVED53),
+       PERIPHC_I2C2,
+       PERIPHC_UART3,
+
+       /* 56 */
+       NONE(MIPI_CAL),
+       PERIPHC_EMC,
+       NONE(USB2),
+       NONE(USB3),
+       NONE(RESERVED60),
+       PERIPHC_VDE,
+       NONE(BSEA),
+       NONE(BSEV),
+
+       /* Upper word 95:64 */
+       NONE(RESERVED64),
+       PERIPHC_UART4,
+       PERIPHC_UART5,
+       PERIPHC_I2C3,
+       PERIPHC_SBC4,
+       PERIPHC_SDMMC3,
+       NONE(PCIE),
+       PERIPHC_OWR,
+
+       /* 72 */
+       NONE(AFI),
+       PERIPHC_CSITE,
+       NONE(PCIEXCLK),
+       NONE(AVPUCQ),
+       NONE(LA),
+       NONE(TRACECLKIN),
+       NONE(SOC_THERM),
+       NONE(DTV),
+
+       /* 80 */
+       NONE(RESERVED80),
+       PERIPHC_I2CSLOW,
+       NONE(DSIB),
+       PERIPHC_TSEC,
+       NONE(RESERVED84),
+       NONE(RESERVED85),
+       NONE(RESERVED86),
+       NONE(EMUCIF),
+
+       /* 88 */
+       NONE(RESERVED88),
+       NONE(XUSB_HOST),
+       NONE(RESERVED90),
+       PERIPHC_MSENC,
+       NONE(RESERVED92),
+       NONE(RESERVED93),
+       NONE(RESERVED94),
+       NONE(XUSB_DEV),
+
+       /* V word: 31:0 */
+       NONE(CPUG),
+       NONE(CPULP),
+       NONE(V_RESERVED2),
+       PERIPHC_MSELECT,
+       NONE(V_RESERVED4),
+       PERIPHC_I2S3,
+       PERIPHC_I2S4,
+       PERIPHC_I2C4,
+
+       /* 104 */
+       PERIPHC_SBC5,
+       PERIPHC_SBC6,
+       PERIPHC_AUDIO,
+       NONE(APBIF),
+       PERIPHC_DAM0,
+       PERIPHC_DAM1,
+       PERIPHC_DAM2,
+       PERIPHC_HDA2CODEC2X,
+
+       /* 112 */
+       NONE(ATOMICS),
+       NONE(V_RESERVED17),
+       NONE(V_RESERVED18),
+       NONE(V_RESERVED19),
+       NONE(V_RESERVED20),
+       NONE(V_RESERVED21),
+       NONE(V_RESERVED22),
+       PERIPHC_ACTMON,
+
+       /* 120 */
+       NONE(EXTPERIPH1),
+       NONE(EXTPERIPH2),
+       NONE(EXTPERIPH3),
+       NONE(OOB),
+       PERIPHC_SATA,
+       PERIPHC_HDA,
+       NONE(TZRAM),
+       NONE(SE),
+
+       /* W word: 31:0 */
+       NONE(HDA2HDMICODEC),
+       NONE(SATACOLD),
+       NONE(W_RESERVED2),
+       NONE(W_RESERVED3),
+       NONE(W_RESERVED4),
+       NONE(W_RESERVED5),
+       NONE(W_RESERVED6),
+       NONE(W_RESERVED7),
+
+       /* 136 */
+       NONE(CEC),
+       NONE(W_RESERVED9),
+       NONE(W_RESERVED10),
+       NONE(W_RESERVED11),
+       NONE(W_RESERVED12),
+       NONE(W_RESERVED13),
+       NONE(XUSB_PADCTL),
+       NONE(W_RESERVED15),
+
+       /* 144 */
+       NONE(W_RESERVED16),
+       NONE(W_RESERVED17),
+       NONE(W_RESERVED18),
+       NONE(W_RESERVED19),
+       NONE(W_RESERVED20),
+       NONE(ENTROPY),
+       NONE(DDS),
+       NONE(W_RESERVED23),
+
+       /* 152 */
+       NONE(DP2),
+       NONE(AMX0),
+       NONE(ADX0),
+       NONE(DVFS),
+       NONE(XUSB_SS),
+       NONE(W_RESERVED29),
+       NONE(W_RESERVED30),
+       NONE(W_RESERVED31),
+
+       /* X word: 31:0 */
+       NONE(SPARE),
+       NONE(X_RESERVED1),
+       NONE(X_RESERVED2),
+       NONE(X_RESERVED3),
+       NONE(CAM_MCLK),
+       NONE(CAM_MCLK2),
+       PERIPHC_I2C6,
+       NONE(X_RESERVED7),
+
+       /* 168 */
+       NONE(X_RESERVED8),
+       NONE(X_RESERVED9),
+       NONE(X_RESERVED10),
+       NONE(VIM2_CLK),
+       NONE(X_RESERVED12),
+       NONE(X_RESERVED13),
+       NONE(EMC_DLL),
+       NONE(X_RESERVED15),
+
+       /* 176 */
+       NONE(HDMI_AUDIO),
+       NONE(CLK72MHZ),
+       NONE(VIC),
+       NONE(X_RESERVED19),
+       NONE(ADX1),
+       NONE(DPAUX),
+       NONE(SOR0),
+       NONE(X_RESERVED23),
+
+       /* 184 */
+       NONE(GPU),
+       NONE(AMX1),
+       NONE(X_RESERVED26),
+       NONE(X_RESERVED27),
+       NONE(X_RESERVED28),
+       NONE(X_RESERVED29),
+       NONE(X_RESERVED30),
+       NONE(X_RESERVED31),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that Tegra30+ support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+       struct clk_rst_ctlr *clkrst =
+                       (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 reg;
+
+       reg = readl(&clkrst->crc_osc_ctrl);
+       reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+       if (reg & 1)                            /* one of the newer freqs */
+               printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+       return reg >> 2;        /* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+       struct clk_rst_ctlr *clkrst =
+               (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       enum periphc_internal_id internal_id;
+
+       /* Coresight is a special case */
+       if (periph_id == PERIPH_ID_CSI)
+               return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+       assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+       internal_id = periph_id_to_internal_id[periph_id];
+       assert(internal_id != -1);
+       if (internal_id >= PERIPHC_VW_FIRST) {
+               internal_id -= PERIPHC_VW_FIRST;
+               return &clkrst->crc_clk_src_vw[internal_id];
+       } else {
+               return &clkrst->crc_clk_src[internal_id];
+       }
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id    peripheral to start
+ * @param source       PLL id of required parent clock
+ * @param mux_bits     Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+       enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+       enum clock_type_id type;
+       enum periphc_internal_id internal_id;
+       int mux;
+
+       assert(clock_periph_id_isvalid(periph_id));
+
+       internal_id = periph_id_to_internal_id[periph_id];
+       assert(periphc_internal_id_isvalid(internal_id));
+
+       type = clock_periph_type[internal_id];
+       assert(clock_type_id_isvalid(type));
+
+       *mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+       if (type == CLOCK_TYPE_PC2CC3M_T16)
+               *divider_bits = 16;
+       else
+               *divider_bits = 8;
+
+       for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+               if (clock_source[type][mux] == parent)
+                       return mux;
+
+       /* if we get here, either us or the caller has made a mistake */
+       printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+              parent);
+       return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+       struct clk_rst_ctlr *clkrst =
+               (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 *clk;
+       u32 reg;
+
+       /* Enable/disable the clock to this peripheral */
+       assert(clock_periph_id_isvalid(periph_id));
+       if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+               clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+       else
+               clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+       reg = readl(clk);
+       if (enable)
+               reg |= PERIPH_MASK(periph_id);
+       else
+               reg &= ~PERIPH_MASK(periph_id);
+       writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+       struct clk_rst_ctlr *clkrst =
+               (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 *reset;
+       u32 reg;
+
+       /* Enable/disable reset to the peripheral */
+       assert(clock_periph_id_isvalid(periph_id));
+       if (periph_id < PERIPH_ID_VW_FIRST)
+               reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+       else
+               reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+       reg = readl(reset);
+       if (enable)
+               reg |= PERIPH_MASK(periph_id);
+       else
+               reg &= ~PERIPH_MASK(periph_id);
+       writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id    Clock ID according to tegra124 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+       if (clk_id > PERIPH_ID_COUNT)
+               return PERIPH_ID_NONE;
+
+       switch (clk_id) {
+       case PERIPH_ID_RESERVED4:
+       case PERIPH_ID_RESERVED25:
+       case PERIPH_ID_RESERVED35:
+       case PERIPH_ID_RESERVED36:
+       case PERIPH_ID_RESERVED38:
+       case PERIPH_ID_RESERVED43:
+       case PERIPH_ID_RESERVED49:
+       case PERIPH_ID_RESERVED53:
+       case PERIPH_ID_RESERVED64:
+       case PERIPH_ID_RESERVED84:
+       case PERIPH_ID_RESERVED85:
+       case PERIPH_ID_RESERVED86:
+       case PERIPH_ID_RESERVED88:
+       case PERIPH_ID_RESERVED90:
+       case PERIPH_ID_RESERVED92:
+       case PERIPH_ID_RESERVED93:
+       case PERIPH_ID_RESERVED94:
+       case PERIPH_ID_V_RESERVED2:
+       case PERIPH_ID_V_RESERVED4:
+       case PERIPH_ID_V_RESERVED17:
+       case PERIPH_ID_V_RESERVED18:
+       case PERIPH_ID_V_RESERVED19:
+       case PERIPH_ID_V_RESERVED20:
+       case PERIPH_ID_V_RESERVED21:
+       case PERIPH_ID_V_RESERVED22:
+       case PERIPH_ID_W_RESERVED2:
+       case PERIPH_ID_W_RESERVED3:
+       case PERIPH_ID_W_RESERVED4:
+       case PERIPH_ID_W_RESERVED5:
+       case PERIPH_ID_W_RESERVED6:
+       case PERIPH_ID_W_RESERVED7:
+       case PERIPH_ID_W_RESERVED9:
+       case PERIPH_ID_W_RESERVED10:
+       case PERIPH_ID_W_RESERVED11:
+       case PERIPH_ID_W_RESERVED12:
+       case PERIPH_ID_W_RESERVED13:
+       case PERIPH_ID_W_RESERVED15:
+       case PERIPH_ID_W_RESERVED16:
+       case PERIPH_ID_W_RESERVED17:
+       case PERIPH_ID_W_RESERVED18:
+       case PERIPH_ID_W_RESERVED19:
+       case PERIPH_ID_W_RESERVED20:
+       case PERIPH_ID_W_RESERVED23:
+       case PERIPH_ID_W_RESERVED29:
+       case PERIPH_ID_W_RESERVED30:
+       case PERIPH_ID_W_RESERVED31:
+               return PERIPH_ID_NONE;
+       default:
+               return clk_id;
+       }
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+       struct clk_rst_ctlr *clkrst =
+               (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+       tegra30_set_up_pllp();
+
+       /*
+        * PLLC output frequency set to 600Mhz
+        * PLLD output frequency set to 925Mhz
+        */
+       switch (clock_get_osc_freq()) {
+       case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+               clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+               clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+               break;
+
+       case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+               clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+               clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+               break;
+
+       case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+               clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+               clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+               break;
+       case CLOCK_OSC_FREQ_19_2:
+       default:
+               /*
+                * These are not supported. It is too early to print a
+                * message and the UART likely won't work anyway due to the
+                * oscillator being wrong.
+                */
+               break;
+       }
+
+       /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+       writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+       /* PLLC_MISC: Set LOCK_ENABLE */
+       writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+       udelay(2);
+
+       /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+       writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+       udelay(2);
+}
+
+void arch_timer_init(void)
+{
+       struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
+       u32 freq, val;
+
+       freq = clock_get_rate(CLOCK_ID_OSC);
+       debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+
+       /* ARM CNTFRQ */
+       asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
+
+       /* Only Tegra114+ has the System Counter regs */
+       debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
+       writel(freq, &sysctr->cntfid0);
+
+       val = readl(&sysctr->cntcr);
+       val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
+       writel(val, &sysctr->cntcr);
+       debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
+}
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
new file mode 100644 (file)
index 0000000..d19fda0
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+       int bad_config = config != FUNCMUX_DEFAULT;
+
+       switch (id) {
+       case PERIPH_ID_UART4:
+               switch (config) {
+               case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
+                       pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+
+                       pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
+                       pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
+                       pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
+                       pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+
+                       pinmux_tristate_disable(PINGRP_GPIO_PJ7);
+                       pinmux_tristate_disable(PINGRP_GPIO_PB0);
+                       pinmux_tristate_disable(PINGRP_GPIO_PB1);
+                       pinmux_tristate_disable(PINGRP_GPIO_PK7);
+                       break;
+               }
+               break;
+
+       case PERIPH_ID_UART1:
+               switch (config) {
+               case FUNCMUX_UART1_KBC:
+                       pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
+                       pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+
+                       pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
+                       pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+
+                       pinmux_tristate_disable(PINGRP_KB_ROW9);
+                       pinmux_tristate_disable(PINGRP_KB_ROW10);
+                       break;
+               }
+               break;
+
+       /* Add other periph IDs here as needed */
+
+       default:
+               debug("%s: invalid periph_id %d", __func__, id);
+               return -1;
+       }
+
+       if (bad_config) {
+               debug("%s: invalid config %d for periph_id %d", __func__,
+                     config, id);
+               return -1;
+       }
+       return 0;
+}
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
new file mode 100644 (file)
index 0000000..a4ab4ea
--- /dev/null
@@ -0,0 +1,730 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+       const char *name;
+       enum pmux_func funcs[4];
+       enum pmux_func func_safe;
+       enum pmux_vddio vddio;
+       enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT      0
+#define PMUX_PULL_SHIFT                2
+#define PMUX_TRISTATE_SHIFT    4
+#define PMUX_TRISTATE_MASK     (1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT          5
+#define PMUX_OD_SHIFT          6
+#define PMUX_LOCK_SHIFT                7
+#define PMUX_IO_RESET_SHIFT    8
+#define PMUX_RCV_SEL_SHIFT     9
+
+#define PGRP_HSM_SHIFT         2
+#define PGRP_SCHMT_SHIFT       3
+#define PGRP_LPMD_SHIFT                4
+#define PGRP_LPMD_MASK         (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT       12
+#define PGRP_DRVDN_MASK                (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT       20
+#define PGRP_DRVUP_MASK                (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT                28
+#define PGRP_SLWR_MASK         (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT                30
+#define PGRP_SLWF_MASK         (3 << PGRP_SLWF_SHIFT)
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+       {                                               \
+               .vddio = PMUX_VDDIO_ ## vdd,            \
+               .funcs = {                              \
+                       PMUX_FUNC_ ## f0,               \
+                       PMUX_FUNC_ ## f1,               \
+                       PMUX_FUNC_ ## f2,               \
+                       PMUX_FUNC_ ## f3,               \
+               },                                      \
+               .func_safe = PMUX_FUNC_RSVD1,           \
+               .io = PMUX_PIN_ ## iod,                 \
+       }
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+       PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+       PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+       PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+       /*      NAME      VDD      f0           f1         f2       f3  */
+       PINI(ULPI_DATA0,  BB,      SPI3,       HSI,        UARTA,   ULPI),
+       PINI(ULPI_DATA1,  BB,      SPI3,       HSI,        UARTA,   ULPI),
+       PINI(ULPI_DATA2,  BB,      SPI3,       HSI,        UARTA,   ULPI),
+       PINI(ULPI_DATA3,  BB,      SPI3,        HSI,       UARTA,   ULPI),
+       PINI(ULPI_DATA4,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+       PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+       PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+       PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
+       PINI(ULPI_CLK,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+       PINI(ULPI_DIR,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+       PINI(ULPI_NXT,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+       PINI(ULPI_STP,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
+       PINI(DAP3_FS,     BB,      I2S2,       SPI5,       DISPA,   DISPB),
+       PINI(DAP3_DIN,    BB,      I2S2,       SPI5,       DISPA,   DISPB),
+       PINI(DAP3_DOUT,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+       PINI(DAP3_SCLK,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
+       PINI(GPIO_PV0,    BB,      USB,        RSVD2,      RSVD3,   RSVD4),
+       PINI(GPIO_PV1,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,     CLK12,      RSVD3,   RSVD4),
+       PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+       PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
+       PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
+       PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
+       PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
+       PIN_RESERVED,   /* Reserved: 0x3060 - 0x3064 */
+       PIN_RESERVED,
+       PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
+       PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved: 0x3070 - 0x310c */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+       PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved: 0x311c - 0x3160 */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+       PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
+       PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+       PINI(UART2_CTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
+       PINI(UART3_TXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+       PINI(UART3_RXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
+       PINI(UART3_CTS_N, UART,    UARTC,      SDMMC1,     DTV,     SPI4),
+       PINI(UART3_RTS_N, UART,    UARTC,      PWM0,       DTV,     DISPA),
+       PINI(GPIO_PU0,    UART,    OWR,        UARTA,      RSVD3,   RSVD4),
+       PINI(GPIO_PU1,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+       PINI(GPIO_PU2,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
+       PINI(GPIO_PU3,    UART,    PWM0,       UARTA,      DISPA,   DISPB),
+       PINI(GPIO_PU4,    UART,    PWM1,       UARTA,      DISPA,   DISPB),
+       PINI(GPIO_PU5,    UART,    PWM2,       UARTA,      DISPA,   DISPB),
+       PINI(GPIO_PU6,    UART,    PWM3,       UARTA,      USB,     DISPB),
+       PINI(GEN1_I2C_SDA, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+       PINI(GEN1_I2C_SCL, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
+       PINI(DAP4_FS,     UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+       PINI(DAP4_DIN,    UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+       PINI(DAP4_DOUT,   UART,    I2S3,       RSVD2,      DTV,     RSVD4),
+       PINI(DAP4_SCLK,   UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
+       PINI(CLK3_OUT,    UART,    EXTPERIPH3, RSVD2,      RSVD3,   RSVD4),
+       PINI(CLK3_REQ,    UART,    DEV3,       RSVD2,      RSVD3,   RSVD4),
+       PINI(GMI_WP_N,    GMI,     RSVD1,      NAND,       GMI,     GMI_ALT),
+       PINI(GMI_IORDY,   GMI,     SDMMC2,     RSVD2,      GMI,     TRACE),
+       PINI(GMI_WAIT,    GMI,     SPI4,       NAND,       GMI,     DTV),
+       PINI(GMI_ADV_N,   GMI,     RSVD1,      NAND,       GMI,     TRACE),
+       PINI(GMI_CLK,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+       PINI(GMI_CS0_N,   GMI,     RSVD1,      NAND,       GMI,     USB),
+       PINI(GMI_CS1_N,   GMI,     RSVD1,      NAND,       GMI,     SOC),
+       PINI(GMI_CS2_N,   GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+       PINI(GMI_CS3_N,   GMI,     SDMMC2,     NAND,       GMI,     GMI_ALT),
+       PINI(GMI_CS4_N,   GMI,     USB,        NAND,       GMI,     TRACE),
+       PINI(GMI_CS6_N,   GMI,     NAND,       NAND_ALT,   GMI,     SPI4),
+       PINI(GMI_CS7_N,   GMI,     NAND,       NAND_ALT,   GMI,     SDMMC2),
+       PINI(GMI_AD0,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+       PINI(GMI_AD1,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+       PINI(GMI_AD2,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+       PINI(GMI_AD3,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+       PINI(GMI_AD4,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
+       PINI(GMI_AD5,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+       PINI(GMI_AD6,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+       PINI(GMI_AD7,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
+       PINI(GMI_AD8,     GMI,     PWM0,       NAND,       GMI,     DTV),
+       PINI(GMI_AD9,     GMI,     PWM1,       NAND,       GMI,     CLDVFS),
+       PINI(GMI_AD10,    GMI,     PWM2,       NAND,       GMI,     CLDVFS),
+       PINI(GMI_AD11,    GMI,     PWM3,       NAND,       GMI,     USB),
+       PINI(GMI_AD12,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+       PINI(GMI_AD13,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
+       PINI(GMI_AD14,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+       PINI(GMI_AD15,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
+       PINI(GMI_A16,     GMI,     UARTD,      TRACE,      GMI,     GMI_ALT),
+       PINI(GMI_A17,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+       PINI(GMI_A18,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
+       PINI(GMI_A19,     GMI,     UARTD,      SPI4,       GMI,     TRACE),
+       PINI(GMI_WR_N,    GMI,     RSVD1,      NAND,       GMI,     SPI4),
+       PINI(GMI_OE_N,    GMI,     RSVD1,      NAND,       GMI,     SOC),
+       PINI(GMI_DQS,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
+       PINI(GMI_RST_N,   GMI,     NAND,       NAND_ALT,   GMI,     RSVD4),
+       PINI(GEN2_I2C_SCL, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+       PINI(GEN2_I2C_SDA, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
+       PINI(SDMMC4_CLK,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+       PINI(SDMMC4_CMD,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+       PINI(SDMMC4_DAT0, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT1, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT2, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT3, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT4, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
+       PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
+       PIN_RESERVED,   /* Reserved: 0x3280 */
+       PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT3, RSVD4),
+       PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+       PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
+       PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
+       PINI(CAM_I2C_SDA, CAM,     VGP2,       I2C3,       RSVD3,   RSVD4),
+       PINI(GPIO_PBB3,   CAM,     VGP3,       DISPA,      DISPB,   RSVD4),
+       PINI(GPIO_PBB4,   CAM,     VGP4,       DISPA,      DISPB,   RSVD4),
+       PINI(GPIO_PBB5,   CAM,     VGP5,       DISPA,      DISPB,   RSVD4),
+       PINI(GPIO_PBB6,   CAM,     VGP6,       DISPA,      DISPB,   RSVD4),
+       PINI(GPIO_PBB7,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+       PINI(GPIO_PCC2,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
+       PINI(JTAG_RTCK,   SYS,     RTCK,       RSVD2,      RSVD3,   RSVD4),
+       PINI(PWR_I2C_SCL, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+       PINI(PWR_I2C_SDA, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
+       PINI(KB_ROW0,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+       PINI(KB_ROW1,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
+       PINI(KB_ROW2,     SYS,     KBC,        RSVD2,      DTV,     SOC),
+       PINI(KB_ROW3,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+       PINI(KB_ROW4,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+       PINI(KB_ROW5,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
+       PINI(KB_ROW6,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
+       PINI(KB_ROW7,     SYS,     KBC,        RSVD2,      CLDVFS,  UARTA),
+       PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+       PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+       PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
+       PIN_RESERVED,   /* Reserved: 0x32e8 - 0x32f8 */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
+       PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
+       PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+       PINI(KB_COL3,     SYS,     KBC,        DISPA,      PWM2,    UARTA),
+       PINI(KB_COL4,     SYS,     KBC,        OWR,        SDMMC3,  UARTA),
+       PINI(KB_COL5,     SYS,     KBC,        RSVD2,      SDMMC1,  RSVD4),
+       PINI(KB_COL6,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+       PINI(KB_COL7,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
+       PINI(CLK_32K_OUT, SYS,     BLINK,      SOC,        RSVD3,   RSVD4),
+       PINI(SYS_CLK_REQ, SYS,     SYSCLK,     RSVD2,      RSVD3,   RSVD4),
+       PINI(CORE_PWR_REQ, SYS,    PWRON,      RSVD2,      RSVD3,   RSVD4),
+       PINI(CPU_PWR_REQ, SYS,     CPU,        RSVD2,      RSVD3,   RSVD4),
+       PINI(PWR_INT_N,   SYS,     PMI,        RSVD2,      RSVD3,   RSVD4),
+       PINI(CLK_32K_IN,  SYS,     CLK,        RSVD2,      RSVD3,   RSVD4),
+       PINI(OWR,         SYS,     OWR,        RSVD2,      RSVD3,   RSVD4),
+       PINI(DAP1_FS,     AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+       PINI(DAP1_DIN,    AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+       PINI(DAP1_DOUT,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+       PINI(DAP1_SCLK,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
+       PINI(CLK1_REQ,    AUDIO,   DAP,        DAP1,       RSVD3,   RSVD4),
+       PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1, DAP2,       RSVD3,   RSVD4),
+       PINI(SPDIF_IN,    AUDIO,   SPDIF,      USB,        RSVD3,   RSVD4),
+       PINI(SPDIF_OUT,   AUDIO,   SPDIF,      RSVD2,      RSVD3,   RSVD4),
+       PINI(DAP2_FS,     AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+       PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+       PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+       PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
+       PINI(DVFS_PWM,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+       PINI(GPIO_X1_AUD, AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
+       PINI(GPIO_X3_AUD, AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
+       PINI(DVFS_CLK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+       PINI(GPIO_X4_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
+       PINI(GPIO_X5_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+       PINI(GPIO_X6_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
+       PINI(GPIO_X7_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+       PIN_RESERVED,   /* Reserved: 0x3388 - 0x338c */
+       PIN_RESERVED,
+       PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+       PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
+       PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
+       PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
+       PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
+       PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
+       PIN_RESERVED,   /* Reserved: 0x33a8 - 0x33dc */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
+       PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
+       PINI(SDMMC3_CD_N, SYS,  SDMMC3,     OWR,        RSVD3,   RSVD4),
+       PINI(GPIO_W2_AUD, AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
+       PINI(GPIO_W3_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
+       PINI(USB_VBUS_EN0, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+       PINI(USB_VBUS_EN1, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+       PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+       PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved: 0x3404 */
+       PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *tri = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin */
+       assert(pmux_pingrp_isvalid(pin));
+
+       reg = readl(tri);
+       if (enable)
+               reg |= PMUX_TRISTATE_MASK;
+       else
+               reg &= ~PMUX_TRISTATE_MASK;
+       writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+       pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+       pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pull = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and pupd */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_pupd_isvalid(pupd));
+
+       reg = readl(pull);
+       reg &= ~(0x3 << PMUX_PULL_SHIFT);
+       reg |= (pupd << PMUX_PULL_SHIFT);
+       writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *muxctl = &pmt->pmt_ctl[pin];
+       int i, mux = -1;
+       u32 reg;
+
+       /* Error check on pin and func */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_func_isvalid(func));
+
+       /* Handle special values */
+       if (func == PMUX_FUNC_SAFE)
+               func = tegra_soc_pingroups[pin].func_safe;
+
+       if (func & PMUX_FUNC_RSVD1) {
+               mux = func & 0x3;
+       } else {
+               /* Search for the appropriate function */
+               for (i = 0; i < 4; i++) {
+                       if (tegra_soc_pingroups[pin].funcs[i] == func) {
+                               mux = i;
+                               break;
+                       }
+               }
+       }
+       assert(mux != -1);
+
+       reg = readl(muxctl);
+       reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+       reg |= (mux << PMUX_MUXCTL_SHIFT);
+       writel(reg, muxctl);
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pin_io = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and io */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_io_isvalid(io));
+
+       reg = readl(pin_io);
+       reg &= ~(0x1 << PMUX_IO_SHIFT);
+       reg |= (io & 0x1) << PMUX_IO_SHIFT;
+       writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pin_lock = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and lock */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_lock_isvalid(lock));
+
+       if (lock == PMUX_PIN_LOCK_DEFAULT)
+               return 0;
+
+       reg = readl(pin_lock);
+       reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+       if (lock == PMUX_PIN_LOCK_ENABLE) {
+               reg |= (0x1 << PMUX_LOCK_SHIFT);
+       } else {
+               /* lock == DISABLE, which isn't possible */
+               printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+                      __func__, lock);
+       }
+       writel(reg, pin_lock);
+
+       return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pin_od = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and od */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_od_isvalid(od));
+
+       if (od == PMUX_PIN_OD_DEFAULT)
+               return 0;
+
+       reg = readl(pin_od);
+       reg &= ~(0x1 << PMUX_OD_SHIFT);
+       if (od == PMUX_PIN_OD_ENABLE)
+               reg |= (0x1 << PMUX_OD_SHIFT);
+       writel(reg, pin_od);
+
+       return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+                               enum pmux_pin_ioreset ioreset)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and ioreset */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_ioreset_isvalid(ioreset));
+
+       if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+               return 0;
+
+       reg = readl(pin_ioreset);
+       reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+       if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+               reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+       writel(reg, pin_ioreset);
+
+       return 0;
+}
+
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+                               enum pmux_pin_rcv_sel rcv_sel)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and rcv_sel */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+       if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+               return 0;
+
+       reg = readl(pin_rcv_sel);
+       reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+       if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+               reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+       writel(reg, pin_rcv_sel);
+
+       return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+       enum pmux_pingrp pin = config->pingroup;
+
+       pinmux_set_func(pin, config->func);
+       pinmux_set_pullupdown(pin, config->pull);
+       pinmux_set_tristate(pin, config->tristate);
+       pinmux_set_io(pin, config->io);
+       pinmux_set_lock(pin, config->lock);
+       pinmux_set_od(pin, config->od);
+       pinmux_set_ioreset(pin, config->ioreset);
+       pinmux_set_rcv_sel(pin, config->rcv_sel);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+       int i;
+
+       for (i = 0; i < len; i++)
+               pinmux_config_pingroup(&config[i]);
+}
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_slwf = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and slwf */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_slw_isvalid(slwf));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwf == PGRP_SLWF_NONE)
+               return 0;
+
+       reg = readl(pad_slwf);
+       reg &= ~PGRP_SLWF_MASK;
+       reg |= (slwf << PGRP_SLWF_SHIFT);
+       writel(reg, pad_slwf);
+
+       return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_slwr = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and slwr */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_slw_isvalid(slwr));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwr == PGRP_SLWR_NONE)
+               return 0;
+
+       reg = readl(pad_slwr);
+       reg &= ~PGRP_SLWR_MASK;
+       reg |= (slwr << PGRP_SLWR_SHIFT);
+       writel(reg, pad_slwr);
+
+       return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_drvup = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and drvup */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_drv_isvalid(drvup));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvup == PGRP_DRVUP_NONE)
+               return 0;
+
+       reg = readl(pad_drvup);
+       reg &= ~PGRP_DRVUP_MASK;
+       reg |= (drvup << PGRP_DRVUP_SHIFT);
+       writel(reg, pad_drvup);
+
+       return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_drvdn = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and drvdn */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_drv_isvalid(drvdn));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvdn == PGRP_DRVDN_NONE)
+               return 0;
+
+       reg = readl(pad_drvdn);
+       reg &= ~PGRP_DRVDN_MASK;
+       reg |= (drvdn << PGRP_DRVDN_SHIFT);
+       writel(reg, pad_drvdn);
+
+       return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_lpmd = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad and lpmd value */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_lpmd_isvalid(lpmd));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (lpmd == PGRP_LPMD_NONE)
+               return 0;
+
+       reg = readl(pad_lpmd);
+       reg &= ~PGRP_LPMD_MASK;
+       reg |= (lpmd << PGRP_LPMD_SHIFT);
+       writel(reg, pad_lpmd);
+
+       return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_schmt = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad */
+       assert(pmux_padgrp_isvalid(pad));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (schmt == PGRP_SCHMT_NONE)
+               return 0;
+
+       reg = readl(pad_schmt);
+       reg &= ~(1 << PGRP_SCHMT_SHIFT);
+       if (schmt == PGRP_SCHMT_ENABLE)
+               reg |= (0x1 << PGRP_SCHMT_SHIFT);
+       writel(reg, pad_schmt);
+
+       return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_hsm = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad */
+       assert(pmux_padgrp_isvalid(pad));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (hsm == PGRP_HSM_NONE)
+               return 0;
+
+       reg = readl(pad_hsm);
+       reg &= ~(1 << PGRP_HSM_SHIFT);
+       if (hsm == PGRP_HSM_ENABLE)
+               reg |= (0x1 << PGRP_HSM_SHIFT);
+       writel(reg, pad_hsm);
+
+       return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+       enum pdrive_pingrp pad = config->padgrp;
+
+       padgrp_set_drvup_slwf(pad, config->slwf);
+       padgrp_set_drvdn_slwr(pad, config->slwr);
+       padgrp_set_drvup(pad, config->drvup);
+       padgrp_set_drvdn(pad, config->drvdn);
+       padgrp_set_lpmd(pad, config->lpmd);
+       padgrp_set_schmt(pad, config->schmt);
+       padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+       int i;
+
+       for (i = 0; i < len; i++)
+               padctrl_config_pingroup(&config[i]);
+}