MIPS: drop incaip board

This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>

diff --git a/MAKEALL b/MAKEALL
index 705a0bb5e1a2f2c20c325e7b67452f5e3ab282a5..c54240ced69325d18bc028a1aaca36cd9063aa4b 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -419,10 +419,6 @@ LIST_arm="$(targets_by_arch arm |          \
 #########################################################################
 
 LIST_mips4kc="         \
-       incaip          \
-       incaip_100MHz   \
-       incaip_133MHz   \
-       incaip_150MHz   \
        qemu_mips       \
        vct_platinum    \
        vct_platinum_small      \

diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile
deleted file mode 100644 (file)
index 7341a4a..0000000
--- a/arch/mips/cpu/mips32/incaip/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = incaip_wdt.o
-obj-y  += incaip_clock.o asc_serial.o

diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c
deleted file mode 100644 (file)
index 6f0e4f2..0000000
--- a/arch/mips/cpu/mips32/incaip/asc_serial.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * (INCA) ASC UART support
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/inca-ip.h>
-#include <serial.h>
-#include <linux/compiler.h>
-#include "asc_serial.h"
-
-
-#define SET_BIT(reg, mask)                  reg |= (mask)
-#define CLEAR_BIT(reg, mask)                reg &= (~mask)
-#define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
-
-extern uint incaip_get_fpiclk(void);
-
-static int serial_setopt (void);
-
-/* pointer to ASC register base address */
-static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
-
-/******************************************************************************
-*
-* serial_init - initialize a INCAASC channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-static int asc_serial_init(void)
-{
-    /* we have to set PMU.EN13 bit to enable an ASC device*/
-    INCAASC_PMU_ENABLE(13);
-
-    /* and we have to set CLC register*/
-    CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
-    SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
-    /* initialy we are in async mode */
-    pAsc->asc_con = ASCCON_M_8ASYNC;
-
-    /* select input port */
-    pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
-
-    /* TXFIFO's filling level */
-    SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
-                   ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
-    /* enable TXFIFO */
-    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
-
-    /* RXFIFO's filling level */
-    SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
-                   ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
-    /* enable RXFIFO */
-    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
-
-    /* enable error signals */
-    SET_BIT(pAsc->asc_con, ASCCON_FEN);
-    SET_BIT(pAsc->asc_con, ASCCON_OEN);
-
-    /* acknowledge ASC interrupts */
-    ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
-
-    /* disable ASC interrupts */
-    ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
-
-    /* set FIFOs into the transparent mode */
-    SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
-    SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
-
-    /* set baud rate */
-    serial_setbrg();
-
-    /* set the options */
-    serial_setopt();
-
-    return 0;
-}
-
-static void asc_serial_setbrg(void)
-{
-    ulong      uiReloadValue, fdv;
-    ulong      f_ASC;
-
-    f_ASC = incaip_get_fpiclk();
-
-#ifndef INCAASC_USE_FDV
-    fdv = 2;
-    uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
-    fdv = INCAASC_FDV_HIGH_BAUDRATE;
-    uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
-    if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
-    {
-#ifndef INCAASC_USE_FDV
-       fdv = 3;
-       uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
-       fdv = INCAASC_FDV_LOW_BAUDRATE;
-       uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
-       if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
-       {
-           return;    /* can't impossibly generate that baud rate */
-       }
-    }
-
-    /* Disable Baud Rate Generator; BG should only be written when R=0 */
-    CLEAR_BIT(pAsc->asc_con, ASCCON_R);
-
-#ifndef INCAASC_USE_FDV
-    /*
-     * Disable Fractional Divider (FDE)
-     * Divide clock by reload-value + constant (BRS)
-     */
-    /* FDE = 0 */
-    CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
-
-    if ( fdv == 2 )
-       CLEAR_BIT(pAsc->asc_con, ASCCON_BRS);   /* BRS = 0 */
-    else
-       SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
-
-#else /* INCAASC_USE_FDV */
-
-    /* Enable Fractional Divider */
-    SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
-
-    /* Set fractional divider value */
-    pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
-
-#endif /* INCAASC_USE_FDV */
-
-    /* Set reload value in BG */
-    pAsc->asc_bg = uiReloadValue;
-
-    /* Enable Baud Rate Generator */
-    SET_BIT(pAsc->asc_con, ASCCON_R);           /* R = 1 */
-}
-
-/*******************************************************************************
-*
-* serial_setopt - set the serial options
-*
-* Set the channel operating mode to that specified. Following options
-* are supported: CREAD, CSIZE, PARENB, and PARODD.
-*
-* Note, this routine disables the transmitter.  The calling routine
-* may have to re-enable it.
-*
-* RETURNS:
-* Returns 0 to indicate success, otherwise -1 is returned
-*/
-
-static int serial_setopt (void)
-{
-    ulong  con;
-
-    switch ( ASC_OPTIONS & ASCOPT_CSIZE )
-    {
-    /* 7-bit-data */
-    case ASCOPT_CS7:
-       con = ASCCON_M_7ASYNCPAR;   /* 7-bit-data and parity bit */
-       break;
-
-    /* 8-bit-data */
-    case ASCOPT_CS8:
-       if ( ASC_OPTIONS & ASCOPT_PARENB )
-           con = ASCCON_M_8ASYNCPAR;   /* 8-bit-data and parity bit */
-       else
-           con = ASCCON_M_8ASYNC;      /* 8-bit-data no parity */
-       break;
-
-    /*
-     *  only 7 and 8-bit frames are supported
-     *  if we don't use IOCTL extensions
-     */
-    default:
-       return -1;
-    }
-
-    if ( ASC_OPTIONS & ASCOPT_STOPB )
-       SET_BIT(con, ASCCON_STP);       /* 2 stop bits */
-    else
-       CLEAR_BIT(con, ASCCON_STP);     /* 1 stop bit */
-
-    if ( ASC_OPTIONS & ASCOPT_PARENB )
-       SET_BIT(con, ASCCON_PEN);           /* enable parity checking */
-    else
-       CLEAR_BIT(con, ASCCON_PEN);         /* disable parity checking */
-
-    if ( ASC_OPTIONS & ASCOPT_PARODD )
-       SET_BIT(con, ASCCON_ODD);       /* odd parity */
-    else
-       CLEAR_BIT(con, ASCCON_ODD);     /* even parity */
-
-    if ( ASC_OPTIONS & ASCOPT_CREAD )
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
-
-    pAsc->asc_con |= con;
-
-    return 0;
-}
-
-static void asc_serial_putc(const char c)
-{
-    uint txFl = 0;
-
-    if (c == '\n') serial_putc ('\r');
-
-    /* check do we have a free space in the TX FIFO */
-    /* get current filling level */
-    do
-    {
-       txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
-    }
-    while ( txFl == INCAASC_TXFIFO_FULL );
-
-    pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
-
-    /* check for errors */
-    if ( pAsc->asc_con & ASCCON_OE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-       return;
-    }
-}
-
-static int asc_serial_getc(void)
-{
-    ulong symbol_mask;
-    char c;
-
-    while (!serial_tstc());
-
-    symbol_mask =
-       ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-
-    c = (char)(pAsc->asc_rbuf & symbol_mask);
-
-    return c;
-}
-
-static int asc_serial_tstc(void)
-{
-    int res = 1;
-
-    if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
-    {
-       res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_FE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
-       res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_PE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
-       res = 0;
-    }
-    else if ( pAsc->asc_con & ASCCON_OE )
-    {
-       SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
-       res = 0;
-    }
-
-    return res;
-}
-
-static struct serial_device asc_serial_drv = {
-       .name   = "asc_serial",
-       .start  = asc_serial_init,
-       .stop   = NULL,
-       .setbrg = asc_serial_setbrg,
-       .putc   = asc_serial_putc,
-       .puts   = default_serial_puts,
-       .getc   = asc_serial_getc,
-       .tstc   = asc_serial_tstc,
-};
-
-void asc_serial_initialize(void)
-{
-       serial_register(&asc_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-       return &asc_serial_drv;
-}

diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h
deleted file mode 100644 (file)
index 7ffdcfa..0000000
--- a/arch/mips/cpu/mips32/incaip/asc_serial.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* incaAscSio.h - (INCA) ASC UART tty driver header */
-
-#ifndef __INCincaAscSioh
-#define __INCincaAscSioh
-
-#include <asm/inca-ip.h>
-
-/* channel operating modes */
-#define        ASCOPT_CSIZE    0x00000003
-#define        ASCOPT_CS7      0x00000001
-#define        ASCOPT_CS8      0x00000002
-#define        ASCOPT_PARENB   0x00000004
-#define        ASCOPT_STOPB    0x00000008
-#define        ASCOPT_PARODD   0x00000010
-#define        ASCOPT_CREAD    0x00000020
-
-#define ASC_OPTIONS            (ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY    0
-
-/* use fractional divider for baudrate settings */
-#define INCAASC_USE_FDV
-
-#ifdef INCAASC_USE_FDV
-   #define INCAASC_FDV_LOW_BAUDRATE        71
-   #define INCAASC_FDV_HIGH_BAUDRATE       453
-#endif /*INCAASC_USE_FDV*/
-
-
-#define INCAASC_TXFIFO_FL       1
-#define INCAASC_RXFIFO_FL       1
-#define INCAASC_TXFIFO_FULL     16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define INCAASC_IRQ_LINE_ALL        0x000F0000  /* all IRQs */
-
-#define INCAASC_IRQ_LINE_TIR            0x00010000      /* TIR - Tx */
-#define INCAASC_IRQ_LINE_RIR            0x00020000      /* RIR - Rx */
-#define INCAASC_IRQ_LINE_EIR            0x00040000      /* EIR - Err */
-#define INCAASC_IRQ_LINE_TBIR           0x00080000      /* TBIR - Tx Buf*/
-
-/* interrupt controller access macros */
-#define ASC_INTERRUPTS_ENABLE(X)  \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
-#define ASC_INTERRUPTS_DISABLE(X) \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
-#define ASC_INTERRUPTS_CLEAR(X)   \
-   *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR        0x00000001
-#define ASCCLC_DISS        0x00000002
-#define ASCCLC_RMCMASK     0x0000FF00
-#define ASCCLC_RMCOFFSET   8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK 0x0007
-    #define ASCCON_M_8SYNC          0x0
-    #define ASCCON_M_8ASYNC         0x1
-    #define ASCCON_M_8IRDAASYNC     0x2
-    #define ASCCON_M_7ASYNCPAR      0x3
-    #define ASCCON_M_9ASYNC         0x4
-    #define ASCCON_M_8WAKEUPASYNC   0x5
-    #define ASCCON_M_8ASYNCPAR      0x7
-#define ASCCON_STP      0x0008
-#define ASCCON_REN      0x0010
-#define ASCCON_PEN      0x0020
-#define ASCCON_FEN      0x0040
-#define ASCCON_OEN      0x0080
-#define ASCCON_PE       0x0100
-#define ASCCON_FE       0x0200
-#define ASCCON_OE       0x0400
-#define ASCCON_FDE      0x0800
-#define ASCCON_ODD      0x1000
-#define ASCCON_BRS      0x2000
-#define ASCCON_LB       0x4000
-#define ASCCON_R        0x8000
-
-/* WHBCON register's bits and bitfields */
-#define ASCWHBCON_CLRREN    0x0010
-#define ASCWHBCON_SETREN    0x0020
-#define ASCWHBCON_CLRPE     0x0100
-#define ASCWHBCON_CLRFE     0x0200
-#define ASCWHBCON_CLROE     0x0400
-#define ASCWHBCON_SETPE     0x0800
-#define ASCWHBCON_SETFE     0x1000
-#define ASCWHBCON_SETOE     0x2000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN       0x0001
-#define ASCABCON_AUREN      0x0002
-#define ASCABCON_ABSTEN     0x0004
-#define ASCABCON_ABDETEN    0x0008
-#define ASCABCON_FCDETEN    0x0010
-#define ASCABCON_EMMASK     0x0300
-    #define ASCABCON_EMOFF          8
-       #define ASCABCON_EM_DISAB       0x0
-       #define ASCABCON_EM_DURAB       0x1
-       #define ASCABCON_EM_ALWAYS      0x2
-#define ASCABCON_TXINV      0x0400
-#define ASCABCON_RXINV      0x0800
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK     0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_SETABEN     0x0001
-#define ASCWHBABCON_CLRABEN     0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET    0x0001
-#define ASCABSTAT_FCCDET    0x0002
-#define ASCABSTAT_SCSDET    0x0004
-#define ASCABSTAT_SCCDET    0x0008
-#define ASCABSTAT_DETWAIT   0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET  0x0001
-#define ASCWHBABSTAT_SETFCSDET  0x0002
-#define ASCWHBABSTAT_CLRFCCDET  0x0004
-#define ASCWHBABSTAT_SETFCCDET  0x0008
-#define ASCWHBABSTAT_CLRSCSDET  0x0010
-#define ASCWHBABSTAT_SETSCSDET  0x0020
-#define ASCWHBABSTAT_SETSCCDET  0x0040
-#define ASCWHBABSTAT_CLRSCCDET  0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFEN         0x0001
-#define ASCTXFCON_TXFFLU        0x0002
-#define ASCTXFCON_TXTMEN        0x0004
-#define ASCTXFCON_TXFITLMASK    0x3F00
-#define ASCTXFCON_TXFITLOFF     8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFEN         0x0001
-#define ASCRXFCON_RXFFLU        0x0002
-#define ASCRXFCON_RXTMEN        0x0004
-#define ASCRXFCON_RXFITLMASK    0x3F00
-#define ASCRXFCON_RXFITLOFF     8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK      0x003F
-#define ASCFSTAT_TXFFLMASK      0x3F00
-#define ASCFSTAT_TXFFLOFF       8
-
-#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
-
-typedef  struct         /* incaAsc_t */
-{
-    volatile unsigned long  asc_clc;                            /*0x0000*/
-    volatile unsigned long  asc_pisel;                          /*0x0004*/
-    volatile unsigned long  asc_rsvd1[2];   /* for mapping */   /*0x0008*/
-    volatile unsigned long  asc_con;                            /*0x0010*/
-    volatile unsigned long  asc_bg;                             /*0x0014*/
-    volatile unsigned long  asc_fdv;                            /*0x0018*/
-    volatile unsigned long  asc_pmw;        /* not used */      /*0x001C*/
-    volatile unsigned long  asc_tbuf;                           /*0x0020*/
-    volatile unsigned long  asc_rbuf;                           /*0x0024*/
-    volatile unsigned long  asc_rsvd2[2];   /* for mapping */   /*0x0028*/
-    volatile unsigned long  asc_abcon;                          /*0x0030*/
-    volatile unsigned long  asc_abstat;     /* not used */      /*0x0034*/
-    volatile unsigned long  asc_rsvd3[2];   /* for mapping */   /*0x0038*/
-    volatile unsigned long  asc_rxfcon;                         /*0x0040*/
-    volatile unsigned long  asc_txfcon;                         /*0x0044*/
-    volatile unsigned long  asc_fstat;                          /*0x0048*/
-    volatile unsigned long  asc_rsvd4;      /* for mapping */   /*0x004C*/
-    volatile unsigned long  asc_whbcon;                         /*0x0050*/
-    volatile unsigned long  asc_whbabcon;                       /*0x0054*/
-    volatile unsigned long  asc_whbabstat;  /* not used */      /*0x0058*/
-
-} incaAsc_t;
-
-#endif /* __INCincaAscSioh */

diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk
deleted file mode 100644 (file)
index 5c89129..0000000
--- a/arch/mips/cpu/mips32/incaip/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -mtune=4kc

diff --git a/arch/mips/cpu/mips32/incaip/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c
deleted file mode 100644 (file)
index efada9f..0000000
--- a/arch/mips/cpu/mips32/incaip/incaip_clock.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/inca-ip.h>
-
-
-/*******************************************************************************
-*
-* get_cpuclk - returns the frequency of the CPU.
-*
-* Gets the value directly from the INCA-IP hardware.
-*
-* RETURNS:
-*          150.000.000 for 150 MHz
-*          133.333.333 for 133 MHz (= 400MHz/3)
-*          100.000.000 for 100 MHz (= 400MHz/4)
-* NOTE:
-*   This functions should be used by the hardware driver to get the correct
-*   frequency of the CPU. Don't use the macros, which are set to init the CPU
-*   frequency in the ROM code.
-*/
-uint incaip_get_cpuclk (void)
-{
-       /*-------------------------------------------------------------------------*/
-       /* CPU Clock Input Multiplexer (MUX I)                                     */
-       /* Multiplexer MUX I selects the maximum input clock to the CPU.           */
-       /*-------------------------------------------------------------------------*/
-       if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) &
-           INCA_IP_CGU_CGU_MUXCR_MUXI) {
-               /* MUX I set to 150 MHz clock */
-               return 150000000;
-       } else {
-               /* MUX I set to 100/133 MHz clock */
-               if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) {
-                       /* Division value is 1/3, maximum CPU operating */
-                       /* frequency is 133.3 MHz                       */
-                       return 133333333;
-               } else {
-                       /* Division value is 1/4, maximum CPU operating */
-                       /* frequency is 100 MHz                         */
-                       return 100000000;
-               }
-       }
-}
-
-/*******************************************************************************
-*
-* get_fpiclk - returns the frequency of the FPI bus.
-*
-* Gets the value directly from the INCA-IP hardware.
-*
-* RETURNS: Frquency in Hz
-*
-* NOTE:
-*   This functions should be used by the hardware driver to get the correct
-*   frequency of the CPU. Don't use the macros, which are set to init the CPU
-*   frequency in the ROM code.
-*   The calculation for the
-*/
-uint incaip_get_fpiclk (void)
-{
-       uint clkCPU;
-
-       clkCPU = incaip_get_cpuclk ();
-
-       switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) {
-       case 0x4:
-               return clkCPU >> 1;     /* devided by 2 */
-               break;
-       case 0x8:
-               return clkCPU >> 2;     /* devided by 4 */
-               break;
-       default:
-               return clkCPU;
-               break;
-       }
-}
-
-int incaip_set_cpuclk (void)
-{
-       extern void ebu_init(long);
-       extern void cgu_init(long);
-       extern void sdram_init(long);
-       char tmp[64];
-       ulong cpuclk;
-
-       if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) {
-               cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
-               cgu_init (cpuclk);
-               ebu_init (cpuclk);
-               sdram_init (cpuclk);
-       }
-
-       return 0;
-}

diff --git a/arch/mips/cpu/mips32/incaip/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S
deleted file mode 100644 (file)
index b15320a..0000000
--- a/arch/mips/cpu/mips32/incaip/incaip_wdt.S
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *  INCA-IP Watchdog timer management code.
- *
- *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-
-#include <config.h>
-#include <asm/regdef.h>
-
-
-#define WD_BASE            0xb8000000
-#define WD_CON0(value)     0x0020(value)
-#define WD_CON1(value)     0x0024(value)
-#define WD_DISABLE         0x00000008
-#define WD_ENABLE          0x00000000
-#define WD_WRITE_PW        0xFFFC00F8
-#define WD_WRITE_ENDINIT   0xFFFC00F3
-#define WD_WRITE_INIT      0xFFFC00F2
-
-
-       .globl  disable_incaip_wdt
-disable_incaip_wdt:
-       li      t0, WD_BASE
-
-       /* Calculate password.
-        */
-       lw      t2, WD_CON1(t0)
-       and     t2, 0xC
-
-       lw      t3, WD_CON0(t0)
-       and     t3, 0xFFFFFF01
-
-       or      t3, t2
-       or      t3, 0xF0
-
-       sw      t3, WD_CON0(t0)         /* write password */
-
-       /* Clear ENDINIT.
-        */
-       li      t1, WD_WRITE_INIT
-       sw      t1, WD_CON0(t0)
-
-
-       li      t1, WD_DISABLE
-       sw      t1, WD_CON1(t0)         /* disable watchdog */
-       li      t1, WD_WRITE_PW
-       sw      t1, WD_CON0(t0)         /* write password */
-       li      t1, WD_WRITE_ENDINIT
-       sw      t1, WD_CON0(t0)         /* end command */
-
-       jr      ra
-       nop

diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h
deleted file mode 100644 (file)
index 5f03e2a..0000000
--- a/arch/mips/include/asm/inca-ip.h
+++ /dev/null
@@ -1,2430 +0,0 @@
-/******************************************************************************
-       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
-
-                              No Warranty
-   Because the program is licensed free of charge, there is no warranty for
-   the program, to the extent permitted by applicable law.  Except when
-   otherwise stated in writing the copyright holders and/or other parties
-   provide the program "as is" without warranty of any kind, either
-   expressed or implied, including, but not limited to, the implied
-   warranties of merchantability and fitness for a particular purpose. The
-   entire risk as to the quality and performance of the program is with
-   you.  should the program prove defective, you assume the cost of all
-   necessary servicing, repair or correction.
-
-   In no event unless required by applicable law or agreed to in writing
-   will any copyright holder, or any other party who may modify and/or
-   redistribute the program as permitted above, be liable to you for
-   damages, including any general, special, incidental or consequential
-   damages arising out of the use or inability to use the program
-   (including but not limited to loss of data or data being rendered
-   inaccurate or losses sustained by you or third parties or a failure of
-   the program to operate with any other programs), even if such holder or
-   other party has been advised of the possibility of such damages.
-******************************************************************************/
-
-
-/***********************************************************************/
-/*  Module      :  WDT register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_WDT                          (0xB8000000)
-/***********************************************************************/
-
-
-/***Reset Status Register Power On***/
-#define INCA_IP_WDT_RST_SR                       ((volatile u32*)(INCA_IP_WDT+ 0x0014))
-
-/***Reset Request Register***/
-#define INCA_IP_WDT_RST_REQ                      ((volatile u32*)(INCA_IP_WDT+ 0x0010))
-#define INCA_IP_WDT_RST_REQ_SWBOOT                        (1 << 24)
-#define INCA_IP_WDT_RST_REQ_SWCFG                          (1 << 16)
-#define INCA_IP_WDT_RST_REQ_RRPHY                          (1 << 5)
-#define INCA_IP_WDT_RST_REQ_RRHSP                          (1 << 4)
-#define INCA_IP_WDT_RST_REQ_RRFPI                          (1 << 3)
-#define INCA_IP_WDT_RST_REQ_RREXT                          (1 << 2)
-#define INCA_IP_WDT_RST_REQ_RRDSP                          (1 << 1)
-#define INCA_IP_WDT_RST_REQ_RRCPU                          (1 << 0)
-
-/***NMI Status Register***/
-#define INCA_IP_WDT_NMISR                        ((volatile u32*)(INCA_IP_WDT+ 0x002C))
-#define INCA_IP_WDT_NMISR_NMIWDT                        (1 << 2)
-#define INCA_IP_WDT_NMISR_NMIPLL                        (1 << 1)
-#define INCA_IP_WDT_NMISR_NMIEXT                        (1 << 0)
-
-/***Manufacturer Identification Register***/
-#define INCA_IP_WDT_MANID                        ((volatile u32*)(INCA_IP_WDT+ 0x0070))
-#define INCA_IP_WDT_MANID_MANUF (value)              (((( 1 << 11) - 1) & (value)) << 5)
-
-/***Chip Identification Register***/
-#define INCA_IP_WDT_CHIPID                       ((volatile u32*)(INCA_IP_WDT+ 0x0074))
-#define INCA_IP_WDT_CHIPID_VERSION (value)            (((( 1 << 4) - 1) & (value)) << 28)
-#define INCA_IP_WDT_CHIPID_PART_NUMBER (value)        (((( 1 << 16) - 1) & (value)) << 12)
-#define INCA_IP_WDT_CHIPID_MANID (value)              (((( 1 << 11) - 1) & (value)) << 1)
-
-/***Redesign Tracing Identification Register***/
-#define INCA_IP_WDT_RTID                         ((volatile u32*)(INCA_IP_WDT+ 0x0078))
-#define INCA_IP_WDT_RTID_LC                              (1 << 15)
-#define INCA_IP_WDT_RTID_RIX (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Watchdog Timer Control Register 0***/
-#define INCA_IP_WDT_WDT_CON0                    ((volatile u32*)(INCA_IP_WDT+ 0x0020))
-
-/***Watchdog Timer Control Register 1***/
-#define INCA_IP_WDT_WDT_CON1                    ((volatile u32*)(INCA_IP_WDT+ 0x0024))
-#define INCA_IP_WDT_WDT_CON1_WDTDR                          (1 << 3)
-#define INCA_IP_WDT_WDT_CON1_WDTIR                          (1 << 2)
-
-/***Watchdog Timer Status Register***/
-#define INCA_IP_WDT_WDT_SR                       ((volatile u32*)(INCA_IP_WDT+ 0x0028))
-#define INCA_IP_WDT_WDT_SR_WDTTIM (value)             (((( 1 << 16) - 1) & (value)) << 16)
-#define INCA_IP_WDT_WDT_SR_WDTPR                          (1 << 5)
-#define INCA_IP_WDT_WDT_SR_WDTTO                          (1 << 4)
-#define INCA_IP_WDT_WDT_SR_WDTDS                          (1 << 3)
-#define INCA_IP_WDT_WDT_SR_WDTIS                          (1 << 2)
-#define INCA_IP_WDT_WDT_SR_WDTOE                          (1 << 1)
-#define INCA_IP_WDT_WDT_SR_WDTAE                          (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  CGU register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_CGU                          (0xBF107000)
-/***********************************************************************/
-
-
-/***CGU PLL1 Control Register***/
-#define INCA_IP_CGU_CGU_PLL1CR                   ((volatile u32*)(INCA_IP_CGU+ 0x0008))
-#define INCA_IP_CGU_CGU_PLL1CR_SWRST                          (1 << 31)
-#define INCA_IP_CGU_CGU_PLL1CR_EN                              (1 << 30)
-#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value)               (((( 1 << 6) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value)               (((( 1 << 4) - 1) & (value)) << 0)
-
-/***CGU PLL0 Control Register***/
-#define INCA_IP_CGU_CGU_PLL0CR                   ((volatile u32*)(INCA_IP_CGU+ 0x0000))
-#define INCA_IP_CGU_CGU_PLL0CR_SWRST                          (1 << 31)
-#define INCA_IP_CGU_CGU_PLL0CR_EN                              (1 << 30)
-#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value)               (((( 1 << 6) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value)               (((( 1 << 4) - 1) & (value)) << 0)
-
-/***CGU PLL0 Status Register***/
-#define INCA_IP_CGU_CGU_PLL0SR                   ((volatile u32*)(INCA_IP_CGU+ 0x0004))
-#define INCA_IP_CGU_CGU_PLL0SR_LOCK                            (1 << 31)
-#define INCA_IP_CGU_CGU_PLL0SR_RCF                              (1 << 29)
-#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP                        (1 << 15)
-
-/***CGU PLL1 Status Register***/
-#define INCA_IP_CGU_CGU_PLL1SR                   ((volatile u32*)(INCA_IP_CGU+ 0x000C))
-#define INCA_IP_CGU_CGU_PLL1SR_LOCK                            (1 << 31)
-#define INCA_IP_CGU_CGU_PLL1SR_RCF                              (1 << 29)
-#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP                        (1 << 15)
-
-/***CGU Divider Control Register***/
-#define INCA_IP_CGU_CGU_DIVCR                    ((volatile u32*)(INCA_IP_CGU+ 0x0010))
-
-/***CGU Multiplexer Control Register***/
-#define INCA_IP_CGU_CGU_MUXCR                    ((volatile u32*)(INCA_IP_CGU+ 0x0014))
-#define INCA_IP_CGU_CGU_MUXCR_SWRST                          (1 << 31)
-#define INCA_IP_CGU_CGU_MUXCR_MUXII                          (1 << 1)
-#define INCA_IP_CGU_CGU_MUXCR_MUXI                            (1 << 0)
-
-/***CGU Fractional Divider Control Register***/
-#define INCA_IP_CGU_CGU_FDCR                    ((volatile u32*)(INCA_IP_CGU+ 0x0018))
-#define INCA_IP_CGU_CGU_FDCR_FDEN                            (1 << 31)
-#define INCA_IP_CGU_CGU_FDCR_INTEGER (value)            (((( 1 << 12) - 1) & (value)) << 16)
-#define INCA_IP_CGU_CGU_FDCR_FRACTION (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  PMU register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_PMU                          (0xBF102000)
-/***********************************************************************/
-
-
-/***PM Global Enable Register***/
-#define INCA_IP_PMU_PM_GEN                       ((volatile u32*)(INCA_IP_PMU+ 0x0000))
-#define INCA_IP_PMU_PM_GEN_EN16                            (1 << 16)
-#define INCA_IP_PMU_PM_GEN_EN15                            (1 << 15)
-#define INCA_IP_PMU_PM_GEN_EN14                            (1 << 14)
-#define INCA_IP_PMU_PM_GEN_EN13                            (1 << 13)
-#define INCA_IP_PMU_PM_GEN_EN12                            (1 << 12)
-#define INCA_IP_PMU_PM_GEN_EN11                            (1 << 11)
-#define INCA_IP_PMU_PM_GEN_EN10                            (1 << 10)
-#define INCA_IP_PMU_PM_GEN_EN9                              (1 << 9)
-#define INCA_IP_PMU_PM_GEN_EN8                              (1 << 8)
-#define INCA_IP_PMU_PM_GEN_EN7                              (1 << 7)
-#define INCA_IP_PMU_PM_GEN_EN6                              (1 << 6)
-#define INCA_IP_PMU_PM_GEN_EN5                              (1 << 5)
-#define INCA_IP_PMU_PM_GEN_EN4                              (1 << 4)
-#define INCA_IP_PMU_PM_GEN_EN3                              (1 << 3)
-#define INCA_IP_PMU_PM_GEN_EN2                              (1 << 2)
-#define INCA_IP_PMU_PM_GEN_EN0                              (1 << 0)
-
-/***PM Power Down Enable Register***/
-#define INCA_IP_PMU_PM_PDEN                      ((volatile u32*)(INCA_IP_PMU+ 0x0008))
-#define INCA_IP_PMU_PM_PDEN_EN16                            (1 << 16)
-#define INCA_IP_PMU_PM_PDEN_EN15                            (1 << 15)
-#define INCA_IP_PMU_PM_PDEN_EN14                            (1 << 14)
-#define INCA_IP_PMU_PM_PDEN_EN13                            (1 << 13)
-#define INCA_IP_PMU_PM_PDEN_EN12                            (1 << 12)
-#define INCA_IP_PMU_PM_PDEN_EN11                            (1 << 11)
-#define INCA_IP_PMU_PM_PDEN_EN10                            (1 << 10)
-#define INCA_IP_PMU_PM_PDEN_EN9                              (1 << 9)
-#define INCA_IP_PMU_PM_PDEN_EN8                              (1 << 8)
-#define INCA_IP_PMU_PM_PDEN_EN7                              (1 << 7)
-#define INCA_IP_PMU_PM_PDEN_EN5                              (1 << 5)
-#define INCA_IP_PMU_PM_PDEN_EN4                              (1 << 4)
-#define INCA_IP_PMU_PM_PDEN_EN3                              (1 << 3)
-#define INCA_IP_PMU_PM_PDEN_EN2                              (1 << 2)
-#define INCA_IP_PMU_PM_PDEN_EN0                              (1 << 0)
-
-/***PM Wake-Up from Power Down Register***/
-#define INCA_IP_PMU_PM_WUP                       ((volatile u32*)(INCA_IP_PMU+ 0x0010))
-#define INCA_IP_PMU_PM_WUP_WUP16                          (1 << 16)
-#define INCA_IP_PMU_PM_WUP_WUP15                          (1 << 15)
-#define INCA_IP_PMU_PM_WUP_WUP14                          (1 << 14)
-#define INCA_IP_PMU_PM_WUP_WUP13                          (1 << 13)
-#define INCA_IP_PMU_PM_WUP_WUP12                          (1 << 12)
-#define INCA_IP_PMU_PM_WUP_WUP11                          (1 << 11)
-#define INCA_IP_PMU_PM_WUP_WUP10                          (1 << 10)
-#define INCA_IP_PMU_PM_WUP_WUP9                            (1 << 9)
-#define INCA_IP_PMU_PM_WUP_WUP8                            (1 << 8)
-#define INCA_IP_PMU_PM_WUP_WUP7                            (1 << 7)
-#define INCA_IP_PMU_PM_WUP_WUP5                            (1 << 5)
-#define INCA_IP_PMU_PM_WUP_WUP4                            (1 << 4)
-#define INCA_IP_PMU_PM_WUP_WUP3                            (1 << 3)
-#define INCA_IP_PMU_PM_WUP_WUP2                            (1 << 2)
-#define INCA_IP_PMU_PM_WUP_WUP0                            (1 << 0)
-
-/***PM Control Register***/
-#define INCA_IP_PMU_PM_CR                        ((volatile u32*)(INCA_IP_PMU+ 0x0014))
-#define INCA_IP_PMU_PM_CR_AWEN                            (1 << 31)
-#define INCA_IP_PMU_PM_CR_SWRST                          (1 << 30)
-#define INCA_IP_PMU_PM_CR_SWCR                            (1 << 2)
-#define INCA_IP_PMU_PM_CR_CRD (value)                (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  BCU register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_BCU                          (0xB8000100)
-/***********************************************************************/
-
-
-/***BCU Control Register (0010H)***/
-#define INCA_IP_BCU_BCU_CON                      ((volatile u32*)(INCA_IP_BCU+ 0x0010))
-#define INCA_IP_BCU_BCU_CON_SPC (value)                (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_BCU_BCU_CON_SPE                              (1 << 19)
-#define INCA_IP_BCU_BCU_CON_PSE                              (1 << 18)
-#define INCA_IP_BCU_BCU_CON_DBG                              (1 << 16)
-#define INCA_IP_BCU_BCU_CON_TOUT (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***BCU Error Control Capture Register (0020H)***/
-#define INCA_IP_BCU_BCU_ECON                    ((volatile u32*)(INCA_IP_BCU+ 0x0020))
-#define INCA_IP_BCU_BCU_ECON_TAG (value)                (((( 1 << 4) - 1) & (value)) << 24)
-#define INCA_IP_BCU_BCU_ECON_RDN                              (1 << 23)
-#define INCA_IP_BCU_BCU_ECON_WRN                              (1 << 22)
-#define INCA_IP_BCU_BCU_ECON_SVM                              (1 << 21)
-#define INCA_IP_BCU_BCU_ECON_ACK (value)                (((( 1 << 2) - 1) & (value)) << 19)
-#define INCA_IP_BCU_BCU_ECON_ABT                              (1 << 18)
-#define INCA_IP_BCU_BCU_ECON_RDY                              (1 << 17)
-#define INCA_IP_BCU_BCU_ECON_TOUT                            (1 << 16)
-#define INCA_IP_BCU_BCU_ECON_ERRCNT (value)             (((( 1 << 16) - 1) & (value)) << 0)
-#define INCA_IP_BCU_BCU_ECON_OPC (value)                (((( 1 << 4) - 1) & (value)) << 28)
-
-/***BCU Error Address Capture Register (0024 H)***/
-#define INCA_IP_BCU_BCU_EADD                    ((volatile u32*)(INCA_IP_BCU+ 0x0024))
-#define INCA_IP_BCU_BCU_EADD_FPIADR
-
-/***BCU Error Data Capture Register (0028H)***/
-#define INCA_IP_BCU_BCU_EDAT                    ((volatile u32*)(INCA_IP_BCU+ 0x0028))
-#define INCA_IP_BCU_BCU_EDAT_FPIDAT
-
-/***********************************************************************/
-/*  Module      :  MBC register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_MBC                          (0xBF103000)
-/***********************************************************************/
-
-
-/***Mailbox CPU Configuration Register***/
-#define INCA_IP_MBC_MBC_CFG                      ((volatile u32*)(INCA_IP_MBC+ 0x0080))
-#define INCA_IP_MBC_MBC_CFG_SWAP (value)               (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_MBC_MBC_CFG_RES                              (1 << 5)
-#define INCA_IP_MBC_MBC_CFG_FWID (value)               (((( 1 << 4) - 1) & (value)) << 1)
-#define INCA_IP_MBC_MBC_CFG_SIZE                            (1 << 0)
-
-/***Mailbox CPU Interrupt Status Register***/
-#define INCA_IP_MBC_MBC_ISR                      ((volatile u32*)(INCA_IP_MBC+ 0x0084))
-#define INCA_IP_MBC_MBC_ISR_B3DA                            (1 << 31)
-#define INCA_IP_MBC_MBC_ISR_B2DA                            (1 << 30)
-#define INCA_IP_MBC_MBC_ISR_B1E                              (1 << 29)
-#define INCA_IP_MBC_MBC_ISR_B0E                              (1 << 28)
-#define INCA_IP_MBC_MBC_ISR_WDT                              (1 << 27)
-#define INCA_IP_MBC_MBC_ISR_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask Register***/
-#define INCA_IP_MBC_MBC_MSK                      ((volatile u32*)(INCA_IP_MBC+ 0x0088))
-#define INCA_IP_MBC_MBC_MSK_B3DA                            (1 << 31)
-#define INCA_IP_MBC_MBC_MSK_B2DA                            (1 << 30)
-#define INCA_IP_MBC_MBC_MSK_B1E                              (1 << 29)
-#define INCA_IP_MBC_MBC_MSK_B0E                              (1 << 28)
-#define INCA_IP_MBC_MBC_MSK_WDT                              (1 << 27)
-#define INCA_IP_MBC_MBC_MSK_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 01 Register***/
-#define INCA_IP_MBC_MBC_MSK01                    ((volatile u32*)(INCA_IP_MBC+ 0x008C))
-#define INCA_IP_MBC_MBC_MSK01_B3DA                            (1 << 31)
-#define INCA_IP_MBC_MBC_MSK01_B2DA                            (1 << 30)
-#define INCA_IP_MBC_MBC_MSK01_B1E                              (1 << 29)
-#define INCA_IP_MBC_MBC_MSK01_B0E                              (1 << 28)
-#define INCA_IP_MBC_MBC_MSK01_WDT                              (1 << 27)
-#define INCA_IP_MBC_MBC_MSK01_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Mask 10 Register***/
-#define INCA_IP_MBC_MBC_MSK10                    ((volatile u32*)(INCA_IP_MBC+ 0x0090))
-#define INCA_IP_MBC_MBC_MSK10_B3DA                            (1 << 31)
-#define INCA_IP_MBC_MBC_MSK10_B2DA                            (1 << 30)
-#define INCA_IP_MBC_MBC_MSK10_B1E                              (1 << 29)
-#define INCA_IP_MBC_MBC_MSK10_B0E                              (1 << 28)
-#define INCA_IP_MBC_MBC_MSK10_WDT                              (1 << 27)
-#define INCA_IP_MBC_MBC_MSK10_DS260 (value)             (((( 1 << 27) - 1) & (value)) << 0)
-
-/***Mailbox CPU Short Command Register***/
-#define INCA_IP_MBC_MBC_CMD                      ((volatile u32*)(INCA_IP_MBC+ 0x0094))
-#define INCA_IP_MBC_MBC_CMD_CS270 (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***Mailbox CPU Input Data of Buffer 0***/
-#define INCA_IP_MBC_MBC_ID0                      ((volatile u32*)(INCA_IP_MBC+ 0x0000))
-#define INCA_IP_MBC_MBC_ID0_INDATA
-
-/***Mailbox CPU Input Data of Buffer 1***/
-#define INCA_IP_MBC_MBC_ID1                      ((volatile u32*)(INCA_IP_MBC+ 0x0020))
-#define INCA_IP_MBC_MBC_ID1_INDATA
-
-/***Mailbox CPU Output Data of Buffer 2***/
-#define INCA_IP_MBC_MBC_OD2                      ((volatile u32*)(INCA_IP_MBC+ 0x0040))
-#define INCA_IP_MBC_MBC_OD2_OUTDATA
-
-/***Mailbox CPU Output Data of Buffer 3***/
-#define INCA_IP_MBC_MBC_OD3                      ((volatile u32*)(INCA_IP_MBC+ 0x0060))
-#define INCA_IP_MBC_MBC_OD3_OUTDATA
-
-/***Mailbox CPU Control Register of Buffer 0***/
-#define INCA_IP_MBC_MBC_CR0                      ((volatile u32*)(INCA_IP_MBC+ 0x0004))
-#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 1***/
-#define INCA_IP_MBC_MBC_CR1                      ((volatile u32*)(INCA_IP_MBC+ 0x0024))
-#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 2***/
-#define INCA_IP_MBC_MBC_CR2                      ((volatile u32*)(INCA_IP_MBC+ 0x0044))
-#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Control Register of Buffer 3***/
-#define INCA_IP_MBC_MBC_CR3                      ((volatile u32*)(INCA_IP_MBC+ 0x0064))
-#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value)          (((( 1 << 3) - 1) & (value)) << 0)
-
-/***Mailbox CPU Free Space of Buffer 0***/
-#define INCA_IP_MBC_MBC_FS0                      ((volatile u32*)(INCA_IP_MBC+ 0x0008))
-#define INCA_IP_MBC_MBC_FS0_FS
-
-/***Mailbox CPU Free Space of Buffer 1***/
-#define INCA_IP_MBC_MBC_FS1                      ((volatile u32*)(INCA_IP_MBC+ 0x0028))
-#define INCA_IP_MBC_MBC_FS1_FS
-
-/***Mailbox CPU Free Space of Buffer 2***/
-#define INCA_IP_MBC_MBC_FS2                      ((volatile u32*)(INCA_IP_MBC+ 0x0048))
-#define INCA_IP_MBC_MBC_FS2_FS
-
-/***Mailbox CPU Free Space of Buffer 3***/
-#define INCA_IP_MBC_MBC_FS3                      ((volatile u32*)(INCA_IP_MBC+ 0x0068))
-#define INCA_IP_MBC_MBC_FS3_FS
-
-/***Mailbox CPU Data Available in Buffer 0***/
-#define INCA_IP_MBC_MBC_DA0                      ((volatile u32*)(INCA_IP_MBC+ 0x000C))
-#define INCA_IP_MBC_MBC_DA0_DA
-
-/***Mailbox CPU Data Available in Buffer 1***/
-#define INCA_IP_MBC_MBC_DA1                      ((volatile u32*)(INCA_IP_MBC+ 0x002C))
-#define INCA_IP_MBC_MBC_DA1_DA
-
-/***Mailbox CPU Data Available in Buffer 2***/
-#define INCA_IP_MBC_MBC_DA2                      ((volatile u32*)(INCA_IP_MBC+ 0x004C))
-#define INCA_IP_MBC_MBC_DA2_DA
-
-/***Mailbox CPU Data Available in Buffer 3***/
-#define INCA_IP_MBC_MBC_DA3                      ((volatile u32*)(INCA_IP_MBC+ 0x006C))
-#define INCA_IP_MBC_MBC_DA3_DA
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_IABS0                    ((volatile u32*)(INCA_IP_MBC+ 0x0010))
-#define INCA_IP_MBC_MBC_IABS0_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_IABS1                    ((volatile u32*)(INCA_IP_MBC+ 0x0030))
-#define INCA_IP_MBC_MBC_IABS1_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_IABS2                    ((volatile u32*)(INCA_IP_MBC+ 0x0050))
-#define INCA_IP_MBC_MBC_IABS2_IABS
-
-/***Mailbox CPU Input Absolute Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_IABS3                    ((volatile u32*)(INCA_IP_MBC+ 0x0070))
-#define INCA_IP_MBC_MBC_IABS3_IABS
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_ITMP0                    ((volatile u32*)(INCA_IP_MBC+ 0x0014))
-#define INCA_IP_MBC_MBC_ITMP0_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_ITMP1                    ((volatile u32*)(INCA_IP_MBC+ 0x0034))
-#define INCA_IP_MBC_MBC_ITMP1_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_ITMP2                    ((volatile u32*)(INCA_IP_MBC+ 0x0054))
-#define INCA_IP_MBC_MBC_ITMP2_ITMP
-
-/***Mailbox CPU Input Temporary Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_ITMP3                    ((volatile u32*)(INCA_IP_MBC+ 0x0074))
-#define INCA_IP_MBC_MBC_ITMP3_ITMP
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_OABS0                    ((volatile u32*)(INCA_IP_MBC+ 0x0018))
-#define INCA_IP_MBC_MBC_OABS0_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_OABS1                    ((volatile u32*)(INCA_IP_MBC+ 0x0038))
-#define INCA_IP_MBC_MBC_OABS1_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_OABS2                    ((volatile u32*)(INCA_IP_MBC+ 0x0058))
-#define INCA_IP_MBC_MBC_OABS2_OABS
-
-/***Mailbox CPU Output Absolute Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_OABS3                    ((volatile u32*)(INCA_IP_MBC+ 0x0078))
-#define INCA_IP_MBC_MBC_OABS3_OABS
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 0***/
-#define INCA_IP_MBC_MBC_OTMP0                    ((volatile u32*)(INCA_IP_MBC+ 0x001C))
-#define INCA_IP_MBC_MBC_OTMP0_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 1***/
-#define INCA_IP_MBC_MBC_OTMP1                    ((volatile u32*)(INCA_IP_MBC+ 0x003C))
-#define INCA_IP_MBC_MBC_OTMP1_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 2***/
-#define INCA_IP_MBC_MBC_OTMP2                    ((volatile u32*)(INCA_IP_MBC+ 0x005C))
-#define INCA_IP_MBC_MBC_OTMP2_OTMP
-
-/***Mailbox CPU Output Temporary Pointer of Buffer 3***/
-#define INCA_IP_MBC_MBC_OTMP3                    ((volatile u32*)(INCA_IP_MBC+ 0x007C))
-#define INCA_IP_MBC_MBC_OTMP3_OTMP
-
-/***DSP Control Register***/
-#define INCA_IP_MBC_DCTRL                        ((volatile u32*)(INCA_IP_MBC+ 0x00A0))
-#define INCA_IP_MBC_DCTRL_BA                              (1 << 0)
-#define INCA_IP_MBC_DCTRL_BMOD (value)               (((( 1 << 3) - 1) & (value)) << 1)
-#define INCA_IP_MBC_DCTRL_IDL                              (1 << 4)
-#define INCA_IP_MBC_DCTRL_RES                              (1 << 15)
-
-/***DSP Status Register***/
-#define INCA_IP_MBC_DSTA                         ((volatile u32*)(INCA_IP_MBC+ 0x00A4))
-#define INCA_IP_MBC_DSTA_IDLE                            (1 << 0)
-#define INCA_IP_MBC_DSTA_PD                              (1 << 1)
-
-/***DSP Test 1 Register***/
-#define INCA_IP_MBC_DTST1                        ((volatile u32*)(INCA_IP_MBC+ 0x00A8))
-#define INCA_IP_MBC_DTST1_ABORT                          (1 << 0)
-#define INCA_IP_MBC_DTST1_HWF32                          (1 << 1)
-#define INCA_IP_MBC_DTST1_HWF4M                          (1 << 2)
-#define INCA_IP_MBC_DTST1_HWFOP                          (1 << 3)
-
-/***********************************************************************/
-/*  Module      :  Switch register address and bits                    */
-/***********************************************************************/
-
-#define INCA_IP_Switch                       (0xBF104000)
-/***********************************************************************/
-
-
-/***Unknown Destination Register***/
-#define INCA_IP_Switch_UN_DEST                      ((volatile u32*)(INCA_IP_Switch+ 0x0000))
-#define INCA_IP_Switch_UN_DEST_CB                              (1 << 8)
-#define INCA_IP_Switch_UN_DEST_LB                              (1 << 7)
-#define INCA_IP_Switch_UN_DEST_PB                              (1 << 6)
-#define INCA_IP_Switch_UN_DEST_CM                              (1 << 5)
-#define INCA_IP_Switch_UN_DEST_LM                              (1 << 4)
-#define INCA_IP_Switch_UN_DEST_PM                              (1 << 3)
-#define INCA_IP_Switch_UN_DEST_CU                              (1 << 2)
-#define INCA_IP_Switch_UN_DEST_LU                              (1 << 1)
-#define INCA_IP_Switch_UN_DEST_PU                              (1 << 0)
-
-/***VLAN Control Register***/
-#define INCA_IP_Switch_VLAN_CTRL                    ((volatile u32*)(INCA_IP_Switch+ 0x0004))
-#define INCA_IP_Switch_VLAN_CTRL_SC                              (1 << 6)
-#define INCA_IP_Switch_VLAN_CTRL_SL                              (1 << 5)
-#define INCA_IP_Switch_VLAN_CTRL_SP                              (1 << 4)
-#define INCA_IP_Switch_VLAN_CTRL_TC                              (1 << 3)
-#define INCA_IP_Switch_VLAN_CTRL_TL                              (1 << 2)
-#define INCA_IP_Switch_VLAN_CTRL_TP                              (1 << 1)
-#define INCA_IP_Switch_VLAN_CTRL_VA                              (1 << 0)
-
-/***PC VLAN Configuration Register***/
-#define INCA_IP_Switch_PC_VLAN                      ((volatile u32*)(INCA_IP_Switch+ 0x0008))
-#define INCA_IP_Switch_PC_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
-
-/***LAN VLAN Configuration Register***/
-#define INCA_IP_Switch_LAN_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x000C))
-#define INCA_IP_Switch_LAN_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
-
-/***CPU VLAN Configuration Register***/
-#define INCA_IP_Switch_CPU_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x0010))
-#define INCA_IP_Switch_CPU_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
-
-/***Priority CoS Mapping Register***/
-#define INCA_IP_Switch_PRI_CoS                      ((volatile u32*)(INCA_IP_Switch+ 0x0014))
-#define INCA_IP_Switch_PRI_CoS_P7                              (1 << 7)
-#define INCA_IP_Switch_PRI_CoS_P6                              (1 << 6)
-#define INCA_IP_Switch_PRI_CoS_P5                              (1 << 5)
-#define INCA_IP_Switch_PRI_CoS_P4                              (1 << 4)
-#define INCA_IP_Switch_PRI_CoS_P3                              (1 << 3)
-#define INCA_IP_Switch_PRI_CoS_P2                              (1 << 2)
-#define INCA_IP_Switch_PRI_CoS_P1                              (1 << 1)
-#define INCA_IP_Switch_PRI_CoS_P0                              (1 << 0)
-
-/***Spanning Tree Port Status Register***/
-#define INCA_IP_Switch_ST_PT                        ((volatile u32*)(INCA_IP_Switch+ 0x0018))
-#define INCA_IP_Switch_ST_PT_CPS (value)                (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_Switch_ST_PT_LPS (value)                (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_Switch_ST_PT_PPS (value)                (((( 1 << 2) - 1) & (value)) << 0)
-
-/***ARL Control Register***/
-#define INCA_IP_Switch_ARL_CTL                      ((volatile u32*)(INCA_IP_Switch+ 0x001C))
-#define INCA_IP_Switch_ARL_CTL_CHCC                            (1 << 15)
-#define INCA_IP_Switch_ARL_CTL_CHCL                            (1 << 14)
-#define INCA_IP_Switch_ARL_CTL_CHCP                            (1 << 13)
-#define INCA_IP_Switch_ARL_CTL_CC                              (1 << 12)
-#define INCA_IP_Switch_ARL_CTL_CL                              (1 << 11)
-#define INCA_IP_Switch_ARL_CTL_CP                              (1 << 10)
-#define INCA_IP_Switch_ARL_CTL_CG                              (1 << 9)
-#define INCA_IP_Switch_ARL_CTL_PS                              (1 << 8)
-#define INCA_IP_Switch_ARL_CTL_MRO                              (1 << 7)
-#define INCA_IP_Switch_ARL_CTL_SRC                              (1 << 6)
-#define INCA_IP_Switch_ARL_CTL_ATS                              (1 << 5)
-#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value)       (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_ARL_CTL_MAF                              (1 << 1)
-#define INCA_IP_Switch_ARL_CTL_ENL                              (1 << 0)
-#define INCA_IP_Switch_ARL_CTL_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
-
-/***CPU Access Control Register***/
-#define INCA_IP_Switch_CPU_ACTL                    ((volatile u32*)(INCA_IP_Switch+ 0x0020))
-#define INCA_IP_Switch_CPU_ACTL_RA                              (1 << 31)
-#define INCA_IP_Switch_CPU_ACTL_RW                              (1 << 30)
-#define INCA_IP_Switch_CPU_ACTL_Res (value)                (((( 1 << 21) - 1) & (value)) << 9)
-#define INCA_IP_Switch_CPU_ACTL_AVA                              (1 << 8)
-#define INCA_IP_Switch_CPU_ACTL_IDX (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***CPU Access Data Register 1***/
-#define INCA_IP_Switch_DATA1                        ((volatile u32*)(INCA_IP_Switch+ 0x0024))
-#define INCA_IP_Switch_DATA1_Data (value)               (((( 1 << 24) - 1) & (value)) << 0)
-
-/***CPU Access Data Register 2***/
-#define INCA_IP_Switch_DATA2                        ((volatile u32*)(INCA_IP_Switch+ 0x0028))
-#define INCA_IP_Switch_DATA2_Data
-
-/***CPU Port Control Register***/
-#define INCA_IP_Switch_CPU_PCTL                    ((volatile u32*)(INCA_IP_Switch+ 0x002C))
-#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value)          (((( 1 << 3) - 1) & (value)) << 11)
-#define INCA_IP_Switch_CPU_PCTL_DAC                              (1 << 10)
-#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value)          (((( 1 << 3) - 1) & (value)) << 7)
-#define INCA_IP_Switch_CPU_PCTL_MAM                              (1 << 6)
-#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value)          (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_Switch_CPU_PCTL_MAC                              (1 << 2)
-#define INCA_IP_Switch_CPU_PCTL_EML                              (1 << 1)
-#define INCA_IP_Switch_CPU_PCTL_EDL                              (1 << 0)
-#define INCA_IP_Switch_CPU_PCTL_Res (value)                (((( 1 << 18) - 1) & (value)) << 14)
-
-/***DSCP CoS Mapping Register 1***/
-#define INCA_IP_Switch_DSCP_COS1                    ((volatile u32*)(INCA_IP_Switch+ 0x0030))
-#define INCA_IP_Switch_DSCP_COS1_DSCP
-
-/***DSCP CoS Mapping Register 1***/
-#define INCA_IP_Switch_DSCP_COS2                    ((volatile u32*)(INCA_IP_Switch+ 0x0034))
-#define INCA_IP_Switch_DSCP_COS2_DSCP
-
-/***PC WFQ Control Register***/
-#define INCA_IP_Switch_PC_WFQ_CTL                   ((volatile u32*)(INCA_IP_Switch+ 0x0080))
-#define INCA_IP_Switch_PC_WFQ_CTL_P1                              (1 << 9)
-#define INCA_IP_Switch_PC_WFQ_CTL_P0                              (1 << 8)
-#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
-
-/***PC TX Control Register***/
-#define INCA_IP_Switch_PC_TX_CTL                    ((volatile u32*)(INCA_IP_Switch+ 0x0084))
-#define INCA_IP_Switch_PC_TX_CTL_ELR                              (1 << 1)
-#define INCA_IP_Switch_PC_TX_CTL_EER                              (1 << 0)
-
-/***LAN WFQ Control Register***/
-#define INCA_IP_Switch_LAN_WFQ_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0100))
-#define INCA_IP_Switch_LAN_WFQ_CTL_P1                              (1 << 9)
-#define INCA_IP_Switch_LAN_WFQ_CTL_P0                              (1 << 8)
-#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
-
-/***LAN TX Control Register***/
-#define INCA_IP_Switch_LAN_TX_CTL                   ((volatile u32*)(INCA_IP_Switch+ 0x0104))
-#define INCA_IP_Switch_LAN_TX_CTL_ELR                              (1 << 1)
-#define INCA_IP_Switch_LAN_TX_CTL_EER                              (1 << 0)
-
-/***CPU WFQ Control Register***/
-#define INCA_IP_Switch_CPU_WFQ_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0180))
-#define INCA_IP_Switch_CPU_WFQ_CTL_P1                              (1 << 9)
-#define INCA_IP_Switch_CPU_WFQ_CTL_P0                              (1 << 8)
-#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
-#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
-#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
-
-/***PM PC RX Watermark Register***/
-#define INCA_IP_Switch_PC_WM                        ((volatile u32*)(INCA_IP_Switch+ 0x0200))
-#define INCA_IP_Switch_PC_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_PC_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_PC_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_PC_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM LAN RX Watermark Register***/
-#define INCA_IP_Switch_LAN_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x0204))
-#define INCA_IP_Switch_LAN_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_LAN_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_LAN_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_LAN_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM CPU RX Watermark Register***/
-#define INCA_IP_Switch_CPU_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x0208))
-#define INCA_IP_Switch_CPU_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_CPU_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_CPU_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_CPU_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM CPU RX Watermark Register***/
-#define INCA_IP_Switch_GBL_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x020C))
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value)         (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value)         (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value)         (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value)         (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM Control Register***/
-#define INCA_IP_Switch_PM_CTL                       ((volatile u32*)(INCA_IP_Switch+ 0x0210))
-#define INCA_IP_Switch_PM_CTL_GDN                              (1 << 3)
-#define INCA_IP_Switch_PM_CTL_CDN                              (1 << 2)
-#define INCA_IP_Switch_PM_CTL_LDN                              (1 << 1)
-#define INCA_IP_Switch_PM_CTL_PDN                              (1 << 0)
-
-/***PM Header Control Register***/
-#define INCA_IP_Switch_PMAC_HD_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0280))
-#define INCA_IP_Switch_PMAC_HD_CTL_RL2                              (1 << 21)
-#define INCA_IP_Switch_PMAC_HD_CTL_RC                              (1 << 20)
-#define INCA_IP_Switch_PMAC_HD_CTL_CM                              (1 << 19)
-#define INCA_IP_Switch_PMAC_HD_CTL_CV                              (1 << 18)
-#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value)          (((( 1 << 16) - 1) & (value)) << 2)
-#define INCA_IP_Switch_PMAC_HD_CTL_TAG                              (1 << 1)
-#define INCA_IP_Switch_PMAC_HD_CTL_ADD                              (1 << 0)
-
-/***PM Source Address Register 1***/
-#define INCA_IP_Switch_PMAC_SA1                    ((volatile u32*)(INCA_IP_Switch+ 0x0284))
-#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***PM Source Address Register 2***/
-#define INCA_IP_Switch_PMAC_SA2                    ((volatile u32*)(INCA_IP_Switch+ 0x0288))
-#define INCA_IP_Switch_PMAC_SA2_SA_31_0
-
-/***PM Dest Address Register 1***/
-#define INCA_IP_Switch_PMAC_DA1                    ((volatile u32*)(INCA_IP_Switch+ 0x028C))
-#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***PM Dest Address Register 2***/
-#define INCA_IP_Switch_PMAC_DA2                    ((volatile u32*)(INCA_IP_Switch+ 0x0290))
-#define INCA_IP_Switch_PMAC_DA2_DA_31_0
-
-/***PM VLAN Register***/
-#define INCA_IP_Switch_PMAC_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x0294))
-#define INCA_IP_Switch_PMAC_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 13)
-#define INCA_IP_Switch_PMAC_VLAN_CFI                              (1 << 12)
-#define INCA_IP_Switch_PMAC_VLAN_VLANID (value)             (((( 1 << 12) - 1) & (value)) << 0)
-
-/***PM TX IPG Counter Register***/
-#define INCA_IP_Switch_PMAC_TX_IPG                  ((volatile u32*)(INCA_IP_Switch+ 0x0298))
-#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value)             (((( 1 << 8) - 1) & (value)) << 0)
-
-/***PM RX IPG Counter Register***/
-#define INCA_IP_Switch_PMAC_RX_IPG                  ((volatile u32*)(INCA_IP_Switch+ 0x029C))
-#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value)             (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Mirror Register***/
-#define INCA_IP_Switch_MRR                          ((volatile u32*)(INCA_IP_Switch+ 0x0300))
-#define INCA_IP_Switch_MRR_MRR (value)                (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_Switch_MRR_EC                              (1 << 5)
-#define INCA_IP_Switch_MRR_EL                              (1 << 4)
-#define INCA_IP_Switch_MRR_EP                              (1 << 3)
-#define INCA_IP_Switch_MRR_IC                              (1 << 2)
-#define INCA_IP_Switch_MRR_IL                              (1 << 1)
-#define INCA_IP_Switch_MRR_IP                              (1 << 0)
-
-/***Packet Length Register***/
-#define INCA_IP_Switch_PKT_LEN                      ((volatile u32*)(INCA_IP_Switch+ 0x0304))
-#define INCA_IP_Switch_PKT_LEN_ADD                              (1 << 11)
-#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value)        (((( 1 << 11) - 1) & (value)) << 0)
-
-/***MDIO Access Register***/
-#define INCA_IP_Switch_MDIO_ACC                    ((volatile u32*)(INCA_IP_Switch+ 0x0480))
-#define INCA_IP_Switch_MDIO_ACC_RA                              (1 << 31)
-#define INCA_IP_Switch_MDIO_ACC_RW                              (1 << 30)
-#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value)          (((( 1 << 5) - 1) & (value)) << 21)
-#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value)          (((( 1 << 5) - 1) & (value)) << 16)
-#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Ethernet PHY Register***/
-#define INCA_IP_Switch_EPHY                         ((volatile u32*)(INCA_IP_Switch+ 0x0484))
-#define INCA_IP_Switch_EPHY_SL                              (1 << 7)
-#define INCA_IP_Switch_EPHY_SP                              (1 << 6)
-#define INCA_IP_Switch_EPHY_LL                              (1 << 5)
-#define INCA_IP_Switch_EPHY_LP                              (1 << 4)
-#define INCA_IP_Switch_EPHY_DL                              (1 << 3)
-#define INCA_IP_Switch_EPHY_DP                              (1 << 2)
-#define INCA_IP_Switch_EPHY_PL                              (1 << 1)
-#define INCA_IP_Switch_EPHY_PP                              (1 << 0)
-
-/***Pause Write Enable Register***/
-#define INCA_IP_Switch_PWR_EN                       ((volatile u32*)(INCA_IP_Switch+ 0x0488))
-#define INCA_IP_Switch_PWR_EN_PL                              (1 << 1)
-#define INCA_IP_Switch_PWR_EN_PP                              (1 << 0)
-
-/***MDIO Configuration Register***/
-#define INCA_IP_Switch_MDIO_CFG                    ((volatile u32*)(INCA_IP_Switch+ 0x048C))
-#define INCA_IP_Switch_MDIO_CFG_MDS (value)                (((( 1 << 2) - 1) & (value)) << 14)
-#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value)       (((( 1 << 5) - 1) & (value)) << 9)
-#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value)        (((( 1 << 5) - 1) & (value)) << 4)
-#define INCA_IP_Switch_MDIO_CFG_UEP                              (1 << 3)
-#define INCA_IP_Switch_MDIO_CFG_PS                              (1 << 2)
-#define INCA_IP_Switch_MDIO_CFG_PT                              (1 << 1)
-#define INCA_IP_Switch_MDIO_CFG_UMM                              (1 << 0)
-
-/***Clock Configuration Register***/
-#define INCA_IP_Switch_CLK_CFG                      ((volatile u32*)(INCA_IP_Switch+ 0x0500))
-#define INCA_IP_Switch_CLK_CFG_ARL_ID                        (1 << 9)
-#define INCA_IP_Switch_CLK_CFG_CPU_ID                        (1 << 8)
-#define INCA_IP_Switch_CLK_CFG_LAN_ID                        (1 << 7)
-#define INCA_IP_Switch_CLK_CFG_PC_ID                          (1 << 6)
-#define INCA_IP_Switch_CLK_CFG_SE_ID                          (1 << 5)
-
-/***********************************************************************/
-/*  Module      :  SSC1 register address and bits                      */
-/***********************************************************************/
-
-#define INCA_IP_SSC1                         (0xB8000500)
-/***********************************************************************/
-
-
-/***Control Register (Programming Mode)***/
-#define INCA_IP_SSC1_SCC_CON_PRG                  ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
-#define INCA_IP_SSC1_SCC_CON_PRG_EN                              (1 << 15)
-#define INCA_IP_SSC1_SCC_CON_PRG_MS                              (1 << 14)
-#define INCA_IP_SSC1_SCC_CON_PRG_AREN                            (1 << 12)
-#define INCA_IP_SSC1_SCC_CON_PRG_BEN                              (1 << 11)
-#define INCA_IP_SSC1_SCC_CON_PRG_PEN                              (1 << 10)
-#define INCA_IP_SSC1_SCC_CON_PRG_REN                              (1 << 9)
-#define INCA_IP_SSC1_SCC_CON_PRG_TEN                              (1 << 8)
-#define INCA_IP_SSC1_SCC_CON_PRG_LB                              (1 << 7)
-#define INCA_IP_SSC1_SCC_CON_PRG_PO                              (1 << 6)
-#define INCA_IP_SSC1_SCC_CON_PRG_PH                              (1 << 5)
-#define INCA_IP_SSC1_SCC_CON_PRG_HB                              (1 << 4)
-#define INCA_IP_SSC1_SCC_CON_PRG_BM (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SCC Control Register (Operating Mode)***/
-#define INCA_IP_SSC1_SCC_CON_OPR                  ((volatile u32*)(INCA_IP_SSC1+ 0x0010))
-#define INCA_IP_SSC1_SCC_CON_OPR_EN                              (1 << 15)
-#define INCA_IP_SSC1_SCC_CON_OPR_MS                              (1 << 14)
-#define INCA_IP_SSC1_SCC_CON_OPR_BSY                              (1 << 12)
-#define INCA_IP_SSC1_SCC_CON_OPR_BE                              (1 << 11)
-#define INCA_IP_SSC1_SCC_CON_OPR_PE                              (1 << 10)
-#define INCA_IP_SSC1_SCC_CON_OPR_RE                              (1 << 9)
-#define INCA_IP_SSC1_SCC_CON_OPR_TE                              (1 << 8)
-#define INCA_IP_SSC1_SCC_CON_OPR_BC (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SSC Write Hardware Modified Control Register***/
-#define INCA_IP_SSC1_SSC_WHBCON                   ((volatile u32*)(INCA_IP_SSC1+ 0x0040))
-#define INCA_IP_SSC1_SSC_WHBCON_SETBE                          (1 << 15)
-#define INCA_IP_SSC1_SSC_WHBCON_SETPE                          (1 << 14)
-#define INCA_IP_SSC1_SSC_WHBCON_SETRE                          (1 << 13)
-#define INCA_IP_SSC1_SSC_WHBCON_SETTE                          (1 << 12)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRBE                          (1 << 11)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRPE                          (1 << 10)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRRE                          (1 << 9)
-#define INCA_IP_SSC1_SSC_WHBCON_CLRTE                          (1 << 8)
-
-/***SSC Baudrate Timer Reload Register***/
-#define INCA_IP_SSC1_SSC_BR                       ((volatile u32*)(INCA_IP_SSC1+ 0x0014))
-#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Transmitter Buffer Register***/
-#define INCA_IP_SSC1_SSC_TB                       ((volatile u32*)(INCA_IP_SSC1+ 0x0020))
-#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receiver Buffer Register***/
-#define INCA_IP_SSC1_SSC_RB                       ((volatile u32*)(INCA_IP_SSC1+ 0x0024))
-#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receive FIFO Control Register***/
-#define INCA_IP_SSC1_SSC_RXFCON                   ((volatile u32*)(INCA_IP_SSC1+ 0x0030))
-#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN                        (1 << 2)
-#define INCA_IP_SSC1_SSC_RXFCON_RXFLU                          (1 << 1)
-#define INCA_IP_SSC1_SSC_RXFCON_RXFEN                          (1 << 0)
-
-/***SSC Transmit FIFO Control Register***/
-#define INCA_IP_SSC1_SSC_TXFCON                   ((volatile u32*)(INCA_IP_SSC1+ 0x0034))
-#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN                        (1 << 2)
-#define INCA_IP_SSC1_SSC_TXFCON_TXFLU                          (1 << 1)
-#define INCA_IP_SSC1_SSC_TXFCON_TXFEN                          (1 << 0)
-
-/***SSC FIFO Status Register***/
-#define INCA_IP_SSC1_SSC_FSTAT                    ((volatile u32*)(INCA_IP_SSC1+ 0x0038))
-#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value)              (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value)              (((( 1 << 6) - 1) & (value)) << 0)
-
-/***SSC Clock Control Register***/
-#define INCA_IP_SSC1_SSC_CLC                      ((volatile u32*)(INCA_IP_SSC1+ 0x0000))
-#define INCA_IP_SSC1_SSC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_SSC1_SSC_CLC_DISS                            (1 << 1)
-#define INCA_IP_SSC1_SSC_CLC_DISR                            (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  SSC2 register address and bits                      */
-/***********************************************************************/
-
-#define INCA_IP_SSC2                         (0xB8000600)
-/***********************************************************************/
-
-
-/***Control Register (Programming Mode)***/
-#define INCA_IP_SSC2_SCC_CON_PRG                  ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
-#define INCA_IP_SSC2_SCC_CON_PRG_EN                              (1 << 15)
-#define INCA_IP_SSC2_SCC_CON_PRG_MS                              (1 << 14)
-#define INCA_IP_SSC2_SCC_CON_PRG_AREN                            (1 << 12)
-#define INCA_IP_SSC2_SCC_CON_PRG_BEN                              (1 << 11)
-#define INCA_IP_SSC2_SCC_CON_PRG_PEN                              (1 << 10)
-#define INCA_IP_SSC2_SCC_CON_PRG_REN                              (1 << 9)
-#define INCA_IP_SSC2_SCC_CON_PRG_TEN                              (1 << 8)
-#define INCA_IP_SSC2_SCC_CON_PRG_LB                              (1 << 7)
-#define INCA_IP_SSC2_SCC_CON_PRG_PO                              (1 << 6)
-#define INCA_IP_SSC2_SCC_CON_PRG_PH                              (1 << 5)
-#define INCA_IP_SSC2_SCC_CON_PRG_HB                              (1 << 4)
-#define INCA_IP_SSC2_SCC_CON_PRG_BM (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SCC Control Register (Operating Mode)***/
-#define INCA_IP_SSC2_SCC_CON_OPR                  ((volatile u32*)(INCA_IP_SSC2+ 0x0010))
-#define INCA_IP_SSC2_SCC_CON_OPR_EN                              (1 << 15)
-#define INCA_IP_SSC2_SCC_CON_OPR_MS                              (1 << 14)
-#define INCA_IP_SSC2_SCC_CON_OPR_BSY                              (1 << 12)
-#define INCA_IP_SSC2_SCC_CON_OPR_BE                              (1 << 11)
-#define INCA_IP_SSC2_SCC_CON_OPR_PE                              (1 << 10)
-#define INCA_IP_SSC2_SCC_CON_OPR_RE                              (1 << 9)
-#define INCA_IP_SSC2_SCC_CON_OPR_TE                              (1 << 8)
-#define INCA_IP_SSC2_SCC_CON_OPR_BC (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***SSC Write Hardware Modified Control Register***/
-#define INCA_IP_SSC2_SSC_WHBCON                   ((volatile u32*)(INCA_IP_SSC2+ 0x0040))
-#define INCA_IP_SSC2_SSC_WHBCON_SETBE                          (1 << 15)
-#define INCA_IP_SSC2_SSC_WHBCON_SETPE                          (1 << 14)
-#define INCA_IP_SSC2_SSC_WHBCON_SETRE                          (1 << 13)
-#define INCA_IP_SSC2_SSC_WHBCON_SETTE                          (1 << 12)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRBE                          (1 << 11)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRPE                          (1 << 10)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRRE                          (1 << 9)
-#define INCA_IP_SSC2_SSC_WHBCON_CLRTE                          (1 << 8)
-
-/***SSC Baudrate Timer Reload Register***/
-#define INCA_IP_SSC2_SSC_BR                       ((volatile u32*)(INCA_IP_SSC2+ 0x0014))
-#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Transmitter Buffer Register***/
-#define INCA_IP_SSC2_SSC_TB                       ((volatile u32*)(INCA_IP_SSC2+ 0x0020))
-#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receiver Buffer Register***/
-#define INCA_IP_SSC2_SSC_RB                       ((volatile u32*)(INCA_IP_SSC2+ 0x0024))
-#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***SSC Receive FIFO Control Register***/
-#define INCA_IP_SSC2_SSC_RXFCON                   ((volatile u32*)(INCA_IP_SSC2+ 0x0030))
-#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN                        (1 << 2)
-#define INCA_IP_SSC2_SSC_RXFCON_RXFLU                          (1 << 1)
-#define INCA_IP_SSC2_SSC_RXFCON_RXFEN                          (1 << 0)
-
-/***SSC Transmit FIFO Control Register***/
-#define INCA_IP_SSC2_SSC_TXFCON                   ((volatile u32*)(INCA_IP_SSC2+ 0x0034))
-#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN                        (1 << 2)
-#define INCA_IP_SSC2_SSC_TXFCON_TXFLU                          (1 << 1)
-#define INCA_IP_SSC2_SSC_TXFCON_TXFEN                          (1 << 0)
-
-/***SSC FIFO Status Register***/
-#define INCA_IP_SSC2_SSC_FSTAT                    ((volatile u32*)(INCA_IP_SSC2+ 0x0038))
-#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value)              (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value)              (((( 1 << 6) - 1) & (value)) << 0)
-
-/***SSC Clock Control Register***/
-#define INCA_IP_SSC2_SSC_CLC                      ((volatile u32*)(INCA_IP_SSC2+ 0x0000))
-#define INCA_IP_SSC2_SSC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_SSC2_SSC_CLC_DISS                            (1 << 1)
-#define INCA_IP_SSC2_SSC_CLC_DISR                            (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  EBU register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_EBU                          (0xB8000200)
-/***********************************************************************/
-
-
-/***EBU Clock Control Register***/
-#define INCA_IP_EBU_EBU_CLC                      ((volatile u32*)(INCA_IP_EBU+ 0x0000))
-#define INCA_IP_EBU_EBU_CLC_DISS                            (1 << 1)
-#define INCA_IP_EBU_EBU_CLC_DISR                            (1 << 0)
-
-/***EBU Global Control Register***/
-#define INCA_IP_EBU_EBU_CON                      ((volatile u32*)(INCA_IP_EBU+ 0x0010))
-#define INCA_IP_EBU_EBU_CON_DTACS (value)              (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_CON_DTARW (value)              (((( 1 << 3) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_CON_TOUTC (value)              (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_EBU_EBU_CON_ARBMODE (value)            (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_CON_ARBSYNC                      (1 << 5)
-#define INCA_IP_EBU_EBU_CON_1                              (1 << 3)
-
-/***EBU Address Select Register 0***/
-#define INCA_IP_EBU_EBU_ADDSEL0                  ((volatile u32*)(INCA_IP_EBU+ 0x0020))
-#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE                      (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL0_REGEN                          (1 << 0)
-
-/***EBU Address Select Register 1***/
-#define INCA_IP_EBU_EBU_ADDSEL1                  ((volatile u32*)(INCA_IP_EBU+ 0x0024))
-#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE                      (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL1_REGEN                          (1 << 0)
-
-/***EBU Address Select Register 2***/
-#define INCA_IP_EBU_EBU_ADDSEL2                  ((volatile u32*)(INCA_IP_EBU+ 0x0028))
-#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value)               (((( 1 << 20) - 1) & (value)) << 12)
-#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE                      (1 << 1)
-#define INCA_IP_EBU_EBU_ADDSEL2_REGEN                          (1 << 0)
-
-/***EBU Bus Configuration Register 0***/
-#define INCA_IP_EBU_EBU_BUSCON0                  ((volatile u32*)(INCA_IP_EBU+ 0x0060))
-#define INCA_IP_EBU_EBU_BUSCON0_WRDIS                          (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITINV                      (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON0_SETUP                          (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 1***/
-#define INCA_IP_EBU_EBU_BUSCON1                  ((volatile u32*)(INCA_IP_EBU+ 0x0064))
-#define INCA_IP_EBU_EBU_BUSCON1_WRDIS                          (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITINV                      (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON1_SETUP                          (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***EBU Bus Configuration Register 2***/
-#define INCA_IP_EBU_EBU_BUSCON2                  ((volatile u32*)(INCA_IP_EBU+ 0x0068))
-#define INCA_IP_EBU_EBU_BUSCON2_WRDIS                          (1 << 31)
-#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value)               (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value)              (((( 1 << 2) - 1) & (value)) << 27)
-#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value)               (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value)             (((( 1 << 2) - 1) & (value)) << 22)
-#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value)               (((( 1 << 2) - 1) & (value)) << 20)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITINV                      (1 << 19)
-#define INCA_IP_EBU_EBU_BUSCON2_SETUP                          (1 << 18)
-#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value)              (((( 1 << 2) - 1) & (value)) << 16)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value)            (((( 1 << 7) - 1) & (value)) << 9)
-#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value)            (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  SDRAM register address and bits                     */
-/***********************************************************************/
-
-#define INCA_IP_SDRAM                        (0xBF800000)
-/***********************************************************************/
-
-
-/***MC Access Error Cause Register***/
-#define INCA_IP_SDRAM_MC_ERRCAUSE                  ((volatile u32*)(INCA_IP_SDRAM+ 0x0100))
-#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR                              (1 << 31)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value)                (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***MC Access Error Address Register***/
-#define INCA_IP_SDRAM_MC_ERRADDR                   ((volatile u32*)(INCA_IP_SDRAM+ 0x0108))
-#define INCA_IP_SDRAM_MC_ERRADDR_ADDR
-
-/***MC I/O General Purpose Register***/
-#define INCA_IP_SDRAM_MC_IOGP                      ((volatile u32*)(INCA_IP_SDRAM+ 0x0800))
-#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value)               (((( 1 << 4) - 1) & (value)) << 28)
-#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value)               (((( 1 << 4) - 1) & (value)) << 24)
-#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value)               (((( 1 << 4) - 1) & (value)) << 20)
-#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value)               (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_IOGP_CPS                              (1 << 11)
-#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value)          (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value)             (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value)              (((( 1 << 4) - 1) & (value)) << 0)
-
-/***MC Self Refresh Register***/
-#define INCA_IP_SDRAM_MC_SELFRFSH                  ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00))
-#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS                            (1 << 1)
-#define INCA_IP_SDRAM_MC_SELFRFSH_PWD                              (1 << 0)
-#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value)                (((( 1 << 30) - 1) & (value)) << 2)
-
-/***MC Enable Register***/
-#define INCA_IP_SDRAM_MC_CTRLENA                   ((volatile u32*)(INCA_IP_SDRAM+ 0x1000))
-#define INCA_IP_SDRAM_MC_CTRLENA_ENA                              (1 << 0)
-#define INCA_IP_SDRAM_MC_CTRLENA_Res (value)                (((( 1 << 31) - 1) & (value)) << 1)
-
-/***MC Mode Register Setup Code***/
-#define INCA_IP_SDRAM_MC_MRSCODE                   ((volatile u32*)(INCA_IP_SDRAM+ 0x1008))
-#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value)                (((( 1 << 5) - 1) & (value)) << 7)
-#define INCA_IP_SDRAM_MC_MRSCODE_CL (value)                (((( 1 << 3) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_MRSCODE_WT                              (1 << 3)
-#define INCA_IP_SDRAM_MC_MRSCODE_BL (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***MC Configuration Data-word Width Register***/
-#define INCA_IP_SDRAM_MC_CFGDW                    ((volatile u32*)(INCA_IP_SDRAM+ 0x1010))
-#define INCA_IP_SDRAM_MC_CFGDW_DW (value)                (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_CFGDW_Res (value)                (((( 1 << 28) - 1) & (value)) << 4)
-
-/***MC Configuration Physical Bank 0 Register***/
-#define INCA_IP_SDRAM_MC_CFGPB0                    ((volatile u32*)(INCA_IP_SDRAM+ 0x1018))
-#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value)             (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value)             (((( 1 << 4) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value)              (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_CFGPB0_Res (value)                (((( 1 << 16) - 1) & (value)) << 16)
-
-/***MC Latency Register***/
-#define INCA_IP_SDRAM_MC_LATENCY                   ((volatile u32*)(INCA_IP_SDRAM+ 0x1038))
-#define INCA_IP_SDRAM_MC_LATENCY_TRP (value)                (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value)               (((( 1 << 4) - 1) & (value)) << 12)
-#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value)               (((( 1 << 4) - 1) & (value)) << 8)
-#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value)               (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value)               (((( 1 << 4) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_LATENCY_Res (value)                (((( 1 << 12) - 1) & (value)) << 20)
-
-/***MC Refresh Cycle Time Register***/
-#define INCA_IP_SDRAM_MC_TREFRESH                  ((volatile u32*)(INCA_IP_SDRAM+ 0x1040))
-#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value)               (((( 1 << 13) - 1) & (value)) << 0)
-#define INCA_IP_SDRAM_MC_TREFRESH_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
-
-/***********************************************************************/
-/*  Module      :  GPTU register address and bits                      */
-/***********************************************************************/
-
-#define INCA_IP_GPTU                         (0xB8000300)
-/***********************************************************************/
-
-
-/***GPT Clock Control Register***/
-#define INCA_IP_GPTU_GPT_CLC                      ((volatile u32*)(INCA_IP_GPTU+ 0x0000))
-#define INCA_IP_GPTU_GPT_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_GPTU_GPT_CLC_DISS                            (1 << 1)
-#define INCA_IP_GPTU_GPT_CLC_DISR                            (1 << 0)
-
-/***GPT Timer 3 Control Register***/
-#define INCA_IP_GPTU_GPT_T3CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0014))
-#define INCA_IP_GPTU_GPT_T3CON_T3RDIR                        (1 << 15)
-#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR                      (1 << 14)
-#define INCA_IP_GPTU_GPT_T3CON_T3EDGE                        (1 << 13)
-#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value)               (((( 1 << 2) - 1) & (value)) << 11)
-#define INCA_IP_GPTU_GPT_T3CON_T3OTL                          (1 << 10)
-#define INCA_IP_GPTU_GPT_T3CON_T3UD                            (1 << 7)
-#define INCA_IP_GPTU_GPT_T3CON_T3R                              (1 << 6)
-#define INCA_IP_GPTU_GPT_T3CON_T3M (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T3CON_T3I (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write Hardware Modified Timer 3 Control Register
-If set and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT3CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x004C))
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR                (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR                (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE                  (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE                  (1 << 12)
-#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL                  (1 << 11)
-#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL                  (1 << 10)
-
-/***GPT Timer 2 Control Register***/
-#define INCA_IP_GPTU_GPT_T2CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0010))
-#define INCA_IP_GPTU_GPT_T2CON_TxRDIR                        (1 << 15)
-#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR                      (1 << 14)
-#define INCA_IP_GPTU_GPT_T2CON_TxEDGE                        (1 << 13)
-#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS                      (1 << 12)
-#define INCA_IP_GPTU_GPT_T2CON_TxRC                            (1 << 9)
-#define INCA_IP_GPTU_GPT_T2CON_TxUD                            (1 << 7)
-#define INCA_IP_GPTU_GPT_T2CON_TxR                              (1 << 6)
-#define INCA_IP_GPTU_GPT_T2CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T2CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Control Register***/
-#define INCA_IP_GPTU_GPT_T4CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0018))
-#define INCA_IP_GPTU_GPT_T4CON_TxRDIR                        (1 << 15)
-#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR                      (1 << 14)
-#define INCA_IP_GPTU_GPT_T4CON_TxEDGE                        (1 << 13)
-#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS                      (1 << 12)
-#define INCA_IP_GPTU_GPT_T4CON_TxRC                            (1 << 9)
-#define INCA_IP_GPTU_GPT_T4CON_TxUD                            (1 << 7)
-#define INCA_IP_GPTU_GPT_T4CON_TxR                              (1 << 6)
-#define INCA_IP_GPTU_GPT_T4CON_TxM (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T4CON_TxI (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 2 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT2CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x0048))
-#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR                (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR                (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE                  (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE                  (1 << 12)
-
-/***GPT Write HW Modified Timer 4 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT4CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x0050))
-#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR                (1 << 15)
-#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR                (1 << 14)
-#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE                  (1 << 13)
-#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE                  (1 << 12)
-
-/***GPT Capture Reload Register***/
-#define INCA_IP_GPTU_GPT_CAPREL                   ((volatile u32*)(INCA_IP_GPTU+ 0x0030))
-#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value)             (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 2 Register***/
-#define INCA_IP_GPTU_GPT_T2                       ((volatile u32*)(INCA_IP_GPTU+ 0x0034))
-#define INCA_IP_GPTU_GPT_T2_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 3 Register***/
-#define INCA_IP_GPTU_GPT_T3                       ((volatile u32*)(INCA_IP_GPTU+ 0x0038))
-#define INCA_IP_GPTU_GPT_T3_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 4 Register***/
-#define INCA_IP_GPTU_GPT_T4                       ((volatile u32*)(INCA_IP_GPTU+ 0x003C))
-#define INCA_IP_GPTU_GPT_T4_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 5 Register***/
-#define INCA_IP_GPTU_GPT_T5                       ((volatile u32*)(INCA_IP_GPTU+ 0x0040))
-#define INCA_IP_GPTU_GPT_T5_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Register***/
-#define INCA_IP_GPTU_GPT_T6                       ((volatile u32*)(INCA_IP_GPTU+ 0x0044))
-#define INCA_IP_GPTU_GPT_T6_TVAL (value)               (((( 1 << 16) - 1) & (value)) << 0)
-
-/***GPT Timer 6 Control Register***/
-#define INCA_IP_GPTU_GPT_T6CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x0020))
-#define INCA_IP_GPTU_GPT_T6CON_T6SR                            (1 << 15)
-#define INCA_IP_GPTU_GPT_T6CON_T6CLR                          (1 << 14)
-#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value)               (((( 1 << 2) - 1) & (value)) << 11)
-#define INCA_IP_GPTU_GPT_T6CON_T6OTL                          (1 << 10)
-#define INCA_IP_GPTU_GPT_T6CON_T6UD                            (1 << 7)
-#define INCA_IP_GPTU_GPT_T6CON_T6R                              (1 << 6)
-#define INCA_IP_GPTU_GPT_T6CON_T6M (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T6CON_T6I (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***GPT Write HW Modified Timer 6 Control Register If set
- and clear bit are written concurrently with 1, the associated bit is not changed.***/
-#define INCA_IP_GPTU_GPT_WHBT6CON                 ((volatile u32*)(INCA_IP_GPTU+ 0x0054))
-#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL                  (1 << 11)
-#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL                  (1 << 10)
-
-/***GPT Timer 5 Control Register***/
-#define INCA_IP_GPTU_GPT_T5CON                    ((volatile u32*)(INCA_IP_GPTU+ 0x001C))
-#define INCA_IP_GPTU_GPT_T5CON_T5SC                            (1 << 15)
-#define INCA_IP_GPTU_GPT_T5CON_T5CLR                          (1 << 14)
-#define INCA_IP_GPTU_GPT_T5CON_CI (value)                (((( 1 << 2) - 1) & (value)) << 12)
-#define INCA_IP_GPTU_GPT_T5CON_T5CC                            (1 << 11)
-#define INCA_IP_GPTU_GPT_T5CON_CT3                              (1 << 10)
-#define INCA_IP_GPTU_GPT_T5CON_T5RC                            (1 << 9)
-#define INCA_IP_GPTU_GPT_T5CON_T5UDE                          (1 << 8)
-#define INCA_IP_GPTU_GPT_T5CON_T5UD                            (1 << 7)
-#define INCA_IP_GPTU_GPT_T5CON_T5R                              (1 << 6)
-#define INCA_IP_GPTU_GPT_T5CON_T5M (value)                (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_GPTU_GPT_T5CON_T5I (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  IOM register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_IOM                          (0xBF105000)
-/***********************************************************************/
-
-
-/***Receive FIFO***/
-#define INCA_IP_IOM_RFIFO                        ((volatile u32*)(INCA_IP_IOM+ 0x0000))
-#define INCA_IP_IOM_RFIFO_RXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Transmit FIFO***/
-#define INCA_IP_IOM_XFIFO                        ((volatile u32*)(INCA_IP_IOM+ 0x0000))
-#define INCA_IP_IOM_XFIFO_TXD (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Interrupt Status Register HDLC***/
-#define INCA_IP_IOM_ISTAH                        ((volatile u32*)(INCA_IP_IOM+ 0x0080))
-#define INCA_IP_IOM_ISTAH_RME                              (1 << 7)
-#define INCA_IP_IOM_ISTAH_RPF                              (1 << 6)
-#define INCA_IP_IOM_ISTAH_RFO                              (1 << 5)
-#define INCA_IP_IOM_ISTAH_XPR                              (1 << 4)
-#define INCA_IP_IOM_ISTAH_XMR                              (1 << 3)
-#define INCA_IP_IOM_ISTAH_XDU                              (1 << 2)
-
-/***Interrupt Mask Register HDLC***/
-#define INCA_IP_IOM_MASKH                        ((volatile u32*)(INCA_IP_IOM+ 0x0080))
-#define INCA_IP_IOM_MASKH_RME                              (1 << 7)
-#define INCA_IP_IOM_MASKH_RPF                              (1 << 6)
-#define INCA_IP_IOM_MASKH_RFO                              (1 << 5)
-#define INCA_IP_IOM_MASKH_XPR                              (1 << 4)
-#define INCA_IP_IOM_MASKH_XMR                              (1 << 3)
-#define INCA_IP_IOM_MASKH_XDU                              (1 << 2)
-
-/***Status Register***/
-#define INCA_IP_IOM_STAR                         ((volatile u32*)(INCA_IP_IOM+ 0x0084))
-#define INCA_IP_IOM_STAR_XDOV                            (1 << 7)
-#define INCA_IP_IOM_STAR_XFW                              (1 << 6)
-#define INCA_IP_IOM_STAR_RACI                            (1 << 3)
-#define INCA_IP_IOM_STAR_XACI                            (1 << 1)
-
-/***Command Register***/
-#define INCA_IP_IOM_CMDR                         ((volatile u32*)(INCA_IP_IOM+ 0x0084))
-#define INCA_IP_IOM_CMDR_RMC                              (1 << 7)
-#define INCA_IP_IOM_CMDR_RRES                            (1 << 6)
-#define INCA_IP_IOM_CMDR_XTF                              (1 << 3)
-#define INCA_IP_IOM_CMDR_XME                              (1 << 1)
-#define INCA_IP_IOM_CMDR_XRES                            (1 << 0)
-
-/***Mode Register***/
-#define INCA_IP_IOM_MODEH                        ((volatile u32*)(INCA_IP_IOM+ 0x0088))
-#define INCA_IP_IOM_MODEH_MDS2                            (1 << 7)
-#define INCA_IP_IOM_MODEH_MDS1                            (1 << 6)
-#define INCA_IP_IOM_MODEH_MDS0                            (1 << 5)
-#define INCA_IP_IOM_MODEH_RAC                              (1 << 3)
-#define INCA_IP_IOM_MODEH_DIM2                            (1 << 2)
-#define INCA_IP_IOM_MODEH_DIM1                            (1 << 1)
-#define INCA_IP_IOM_MODEH_DIM0                            (1 << 0)
-
-/***Extended Mode Register***/
-#define INCA_IP_IOM_EXMR                         ((volatile u32*)(INCA_IP_IOM+ 0x008C))
-#define INCA_IP_IOM_EXMR_XFBS                            (1 << 7)
-#define INCA_IP_IOM_EXMR_RFBS (value)               (((( 1 << 2) - 1) & (value)) << 5)
-#define INCA_IP_IOM_EXMR_SRA                              (1 << 4)
-#define INCA_IP_IOM_EXMR_XCRC                            (1 << 3)
-#define INCA_IP_IOM_EXMR_RCRC                            (1 << 2)
-#define INCA_IP_IOM_EXMR_ITF                              (1 << 0)
-
-/***SAPI1 Register***/
-#define INCA_IP_IOM_SAP1                         ((volatile u32*)(INCA_IP_IOM+ 0x0094))
-#define INCA_IP_IOM_SAP1_SAPI1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_SAP1_MHA                              (1 << 0)
-
-/***Receive Frame Byte Count Low***/
-#define INCA_IP_IOM_RBCL                         ((volatile u32*)(INCA_IP_IOM+ 0x0098))
-#define INCA_IP_IOM_RBCL_RBC(value)              (1 << value)
-
-
-/***SAPI2 Register***/
-#define INCA_IP_IOM_SAP2                         ((volatile u32*)(INCA_IP_IOM+ 0x0098))
-#define INCA_IP_IOM_SAP2_SAPI2 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_SAP2_MLA                              (1 << 0)
-
-/***Receive Frame Byte Count High***/
-#define INCA_IP_IOM_RBCH                         ((volatile u32*)(INCA_IP_IOM+ 0x009C))
-#define INCA_IP_IOM_RBCH_OV                              (1 << 4)
-#define INCA_IP_IOM_RBCH_RBC11                          (1 << 3)
-#define INCA_IP_IOM_RBCH_RBC10                          (1 << 2)
-#define INCA_IP_IOM_RBCH_RBC9                            (1 << 1)
-#define INCA_IP_IOM_RBCH_RBC8                            (1 << 0)
-
-/***TEI1 Register 1***/
-#define INCA_IP_IOM_TEI1                         ((volatile u32*)(INCA_IP_IOM+ 0x009C))
-#define INCA_IP_IOM_TEI1_TEI1 (value)               (((( 1 << 7) - 1) & (value)) << 1)
-#define INCA_IP_IOM_TEI1_EA                              (1 << 0)
-
-/***Receive Status Register***/
-#define INCA_IP_IOM_RSTA                         ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
-#define INCA_IP_IOM_RSTA_VFR                              (1 << 7)
-#define INCA_IP_IOM_RSTA_RDO                              (1 << 6)
-#define INCA_IP_IOM_RSTA_CRC                              (1 << 5)
-#define INCA_IP_IOM_RSTA_RAB                              (1 << 4)
-#define INCA_IP_IOM_RSTA_SA1                              (1 << 3)
-#define INCA_IP_IOM_RSTA_SA0                              (1 << 2)
-#define INCA_IP_IOM_RSTA_TA                              (1 << 0)
-#define INCA_IP_IOM_RSTA_CR                              (1 << 1)
-
-/***TEI2 Register***/
-#define INCA_IP_IOM_TEI2                         ((volatile u32*)(INCA_IP_IOM+ 0x00A0))
-#define INCA_IP_IOM_TEI2_TEI2 (value)               (((( 1 << 7) - 1) & (value)) << 1)
-#define INCA_IP_IOM_TEI2_EA                              (1 << 0)
-
-/***Test Mode Register HDLC***/
-#define INCA_IP_IOM_TMH                          ((volatile u32*)(INCA_IP_IOM+ 0x00A4))
-#define INCA_IP_IOM_TMH_TLP                              (1 << 0)
-
-/***Command/Indication Receive 0***/
-#define INCA_IP_IOM_CIR0                         ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
-#define INCA_IP_IOM_CIR0_CODR0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_IOM_CIR0_CIC0                            (1 << 3)
-#define INCA_IP_IOM_CIR0_CIC1                            (1 << 2)
-#define INCA_IP_IOM_CIR0_SG                              (1 << 1)
-#define INCA_IP_IOM_CIR0_BAS                              (1 << 0)
-
-/***Command/Indication Transmit 0***/
-#define INCA_IP_IOM_CIX0                         ((volatile u32*)(INCA_IP_IOM+ 0x00B8))
-#define INCA_IP_IOM_CIX0_CODX0 (value)              (((( 1 << 4) - 1) & (value)) << 4)
-#define INCA_IP_IOM_CIX0_TBA2                            (1 << 3)
-#define INCA_IP_IOM_CIX0_TBA1                            (1 << 2)
-#define INCA_IP_IOM_CIX0_TBA0                            (1 << 1)
-#define INCA_IP_IOM_CIX0_BAC                              (1 << 0)
-
-/***Command/Indication Receive 1***/
-#define INCA_IP_IOM_CIR1                         ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
-#define INCA_IP_IOM_CIR1_CODR1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-
-/***Command/Indication Transmit 1***/
-#define INCA_IP_IOM_CIX1                         ((volatile u32*)(INCA_IP_IOM+ 0x00BC))
-#define INCA_IP_IOM_CIX1_CODX1 (value)              (((( 1 << 6) - 1) & (value)) << 2)
-#define INCA_IP_IOM_CIX1_CICW                            (1 << 1)
-#define INCA_IP_IOM_CIX1_CI1E                            (1 << 0)
-
-/***Controller Data Access Reg. (CH10)***/
-#define INCA_IP_IOM_CDA10                        ((volatile u32*)(INCA_IP_IOM+ 0x0100))
-#define INCA_IP_IOM_CDA10_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH11)***/
-#define INCA_IP_IOM_CDA11                        ((volatile u32*)(INCA_IP_IOM+ 0x0104))
-#define INCA_IP_IOM_CDA11_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH20)***/
-#define INCA_IP_IOM_CDA20                        ((volatile u32*)(INCA_IP_IOM+ 0x0108))
-#define INCA_IP_IOM_CDA20_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Controller Data Access Reg. (CH21)***/
-#define INCA_IP_IOM_CDA21                        ((volatile u32*)(INCA_IP_IOM+ 0x010C))
-#define INCA_IP_IOM_CDA21_CDA (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define INCA_IP_IOM_CDA_TSDP10                   ((volatile u32*)(INCA_IP_IOM+ 0x0110))
-#define INCA_IP_IOM_CDA_TSDP10_DPS                              (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define INCA_IP_IOM_CDA_TSDP11                   ((volatile u32*)(INCA_IP_IOM+ 0x0114))
-#define INCA_IP_IOM_CDA_TSDP11_DPS                              (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define INCA_IP_IOM_CDA_TSDP20                   ((volatile u32*)(INCA_IP_IOM+ 0x0118))
-#define INCA_IP_IOM_CDA_TSDP20_DPS                              (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define INCA_IP_IOM_CDA_TSDP21                   ((volatile u32*)(INCA_IP_IOM+ 0x011C))
-#define INCA_IP_IOM_CDA_TSDP21_DPS                              (1 << 7)
-#define INCA_IP_IOM_CDA_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH10)***/
-#define INCA_IP_IOM_CO_TSDP10                    ((volatile u32*)(INCA_IP_IOM+ 0x0120))
-#define INCA_IP_IOM_CO_TSDP10_DPS                              (1 << 7)
-#define INCA_IP_IOM_CO_TSDP10_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH11)***/
-#define INCA_IP_IOM_CO_TSDP11                    ((volatile u32*)(INCA_IP_IOM+ 0x0124))
-#define INCA_IP_IOM_CO_TSDP11_DPS                              (1 << 7)
-#define INCA_IP_IOM_CO_TSDP11_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH20)***/
-#define INCA_IP_IOM_CO_TSDP20                    ((volatile u32*)(INCA_IP_IOM+ 0x0128))
-#define INCA_IP_IOM_CO_TSDP20_DPS                              (1 << 7)
-#define INCA_IP_IOM_CO_TSDP20_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Time Slot and Data Port Sel. (CH21)***/
-#define INCA_IP_IOM_CO_TSDP21                    ((volatile u32*)(INCA_IP_IOM+ 0x012C))
-#define INCA_IP_IOM_CO_TSDP21_DPS                              (1 << 7)
-#define INCA_IP_IOM_CO_TSDP21_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define INCA_IP_IOM_CDA1_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x0138))
-#define INCA_IP_IOM_CDA1_CR_EN_TBM                        (1 << 5)
-#define INCA_IP_IOM_CDA1_CR_EN_I1                          (1 << 4)
-#define INCA_IP_IOM_CDA1_CR_EN_I0                          (1 << 3)
-#define INCA_IP_IOM_CDA1_CR_EN_O1                          (1 << 2)
-#define INCA_IP_IOM_CDA1_CR_EN_O0                          (1 << 1)
-#define INCA_IP_IOM_CDA1_CR_SWAP                            (1 << 0)
-
-/***Ctrl. Reg. Contr. Data Access CH1x***/
-#define INCA_IP_IOM_CDA2_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x013C))
-#define INCA_IP_IOM_CDA2_CR_EN_TBM                        (1 << 5)
-#define INCA_IP_IOM_CDA2_CR_EN_I1                          (1 << 4)
-#define INCA_IP_IOM_CDA2_CR_EN_I0                          (1 << 3)
-#define INCA_IP_IOM_CDA2_CR_EN_O1                          (1 << 2)
-#define INCA_IP_IOM_CDA2_CR_EN_O0                          (1 << 1)
-#define INCA_IP_IOM_CDA2_CR_SWAP                            (1 << 0)
-
-/***Control Register B-Channel Data***/
-#define INCA_IP_IOM_BCHA_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x0144))
-#define INCA_IP_IOM_BCHA_CR_EN_BC2                        (1 << 4)
-#define INCA_IP_IOM_BCHA_CR_EN_BC1                        (1 << 3)
-
-/***Control Register B-Channel Data***/
-#define INCA_IP_IOM_BCHB_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x0148))
-#define INCA_IP_IOM_BCHB_CR_EN_BC2                        (1 << 4)
-#define INCA_IP_IOM_BCHB_CR_EN_BC1                        (1 << 3)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define INCA_IP_IOM_DCI_CR                       ((volatile u32*)(INCA_IP_IOM+ 0x014C))
-#define INCA_IP_IOM_DCI_CR_DPS_CI1                      (1 << 7)
-#define INCA_IP_IOM_DCI_CR_EN_CI1                        (1 << 6)
-#define INCA_IP_IOM_DCI_CR_EN_D                            (1 << 5)
-
-/***Control Reg. for HDLC and CI1 Data***/
-#define INCA_IP_IOM_DCIC_CR                      ((volatile u32*)(INCA_IP_IOM+ 0x014C))
-#define INCA_IP_IOM_DCIC_CR_DPS_CI0                      (1 << 7)
-#define INCA_IP_IOM_DCIC_CR_EN_CI0                        (1 << 6)
-#define INCA_IP_IOM_DCIC_CR_DPS_D                          (1 << 5)
-
-/***Control Reg. Serial Data Strobe x***/
-#define INCA_IP_IOM_SDS_CR                       ((volatile u32*)(INCA_IP_IOM+ 0x0154))
-#define INCA_IP_IOM_SDS_CR_ENS_TSS                      (1 << 7)
-#define INCA_IP_IOM_SDS_CR_ENS_TSS_1                  (1 << 6)
-#define INCA_IP_IOM_SDS_CR_ENS_TSS_3                  (1 << 5)
-#define INCA_IP_IOM_SDS_CR_TSS (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Control Register IOM Data***/
-#define INCA_IP_IOM_IOM_CR                       ((volatile u32*)(INCA_IP_IOM+ 0x015C))
-#define INCA_IP_IOM_IOM_CR_SPU                              (1 << 7)
-#define INCA_IP_IOM_IOM_CR_CI_CS                          (1 << 5)
-#define INCA_IP_IOM_IOM_CR_TIC_DIS                      (1 << 4)
-#define INCA_IP_IOM_IOM_CR_EN_BCL                        (1 << 3)
-#define INCA_IP_IOM_IOM_CR_CLKM                            (1 << 2)
-#define INCA_IP_IOM_IOM_CR_Res                              (1 << 1)
-#define INCA_IP_IOM_IOM_CR_DIS_IOM                      (1 << 0)
-
-/***Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_STI                          ((volatile u32*)(INCA_IP_IOM+ 0x0160))
-#define INCA_IP_IOM_STI_STOV21                        (1 << 7)
-#define INCA_IP_IOM_STI_STOV20                        (1 << 6)
-#define INCA_IP_IOM_STI_STOV11                        (1 << 5)
-#define INCA_IP_IOM_STI_STOV10                        (1 << 4)
-#define INCA_IP_IOM_STI_STI21                          (1 << 3)
-#define INCA_IP_IOM_STI_STI20                          (1 << 2)
-#define INCA_IP_IOM_STI_STI11                          (1 << 1)
-#define INCA_IP_IOM_STI_STI10                          (1 << 0)
-
-/***Acknowledge Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_ASTI                         ((volatile u32*)(INCA_IP_IOM+ 0x0160))
-#define INCA_IP_IOM_ASTI_ACK21                          (1 << 3)
-#define INCA_IP_IOM_ASTI_ACK20                          (1 << 2)
-#define INCA_IP_IOM_ASTI_ACK11                          (1 << 1)
-#define INCA_IP_IOM_ASTI_ACK10                          (1 << 0)
-
-/***Mask Synchronous Transfer Interrupt***/
-#define INCA_IP_IOM_MSTI                         ((volatile u32*)(INCA_IP_IOM+ 0x0164))
-#define INCA_IP_IOM_MSTI_STOV21                        (1 << 7)
-#define INCA_IP_IOM_MSTI_STOV20                        (1 << 6)
-#define INCA_IP_IOM_MSTI_STOV11                        (1 << 5)
-#define INCA_IP_IOM_MSTI_STOV10                        (1 << 4)
-#define INCA_IP_IOM_MSTI_STI21                          (1 << 3)
-#define INCA_IP_IOM_MSTI_STI20                          (1 << 2)
-#define INCA_IP_IOM_MSTI_STI11                          (1 << 1)
-#define INCA_IP_IOM_MSTI_STI10                          (1 << 0)
-
-/***Configuration Register for Serial Data Strobes***/
-#define INCA_IP_IOM_SDS_CONF                    ((volatile u32*)(INCA_IP_IOM+ 0x0168))
-#define INCA_IP_IOM_SDS_CONF_SDS_BCL                      (1 << 0)
-
-/***Monitoring CDA Bits***/
-#define INCA_IP_IOM_MCDA                         ((volatile u32*)(INCA_IP_IOM+ 0x016C))
-#define INCA_IP_IOM_MCDA_MCDA21 (value)             (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_IOM_MCDA_MCDA20 (value)             (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_IOM_MCDA_MCDA11 (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_IOM_MCDA_MCDA10 (value)             (((( 1 << 2) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  ASC register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_ASC                          (0xB8000400)
-/***********************************************************************/
-
-
-/***ASC Port Input Select Register***/
-#define INCA_IP_ASC_ASC_PISEL                    ((volatile u32*)(INCA_IP_ASC+ 0x0004))
-#define INCA_IP_ASC_ASC_PISEL_RIS                              (1 << 0)
-
-/***ASC Control Register***/
-#define INCA_IP_ASC_ASC_CON                      ((volatile u32*)(INCA_IP_ASC+ 0x0010))
-#define INCA_IP_ASC_ASC_CON_R                              (1 << 15)
-#define INCA_IP_ASC_ASC_CON_LB                              (1 << 14)
-#define INCA_IP_ASC_ASC_CON_BRS                              (1 << 13)
-#define INCA_IP_ASC_ASC_CON_ODD                              (1 << 12)
-#define INCA_IP_ASC_ASC_CON_FDE                              (1 << 11)
-#define INCA_IP_ASC_ASC_CON_OE                              (1 << 10)
-#define INCA_IP_ASC_ASC_CON_FE                              (1 << 9)
-#define INCA_IP_ASC_ASC_CON_PE                              (1 << 8)
-#define INCA_IP_ASC_ASC_CON_OEN                              (1 << 7)
-#define INCA_IP_ASC_ASC_CON_FEN                              (1 << 6)
-#define INCA_IP_ASC_ASC_CON_PENRXDI                  (1 << 5)
-#define INCA_IP_ASC_ASC_CON_REN                              (1 << 4)
-#define INCA_IP_ASC_ASC_CON_STP                              (1 << 3)
-#define INCA_IP_ASC_ASC_CON_M (value)                (((( 1 << 3) - 1) & (value)) << 0)
-
-/***ASC Write Hardware Modified Control Register***/
-#define INCA_IP_ASC_ASC_WHBCON                   ((volatile u32*)(INCA_IP_ASC+ 0x0050))
-#define INCA_IP_ASC_ASC_WHBCON_SETOE                          (1 << 13)
-#define INCA_IP_ASC_ASC_WHBCON_SETFE                          (1 << 12)
-#define INCA_IP_ASC_ASC_WHBCON_SETPE                          (1 << 11)
-#define INCA_IP_ASC_ASC_WHBCON_CLROE                          (1 << 10)
-#define INCA_IP_ASC_ASC_WHBCON_CLRFE                          (1 << 9)
-#define INCA_IP_ASC_ASC_WHBCON_CLRPE                          (1 << 8)
-#define INCA_IP_ASC_ASC_WHBCON_SETREN                        (1 << 5)
-#define INCA_IP_ASC_ASC_WHBCON_CLRREN                        (1 << 4)
-
-/***ASC Baudrate Timer/Reload Register***/
-#define INCA_IP_ASC_ASC_BTR                      ((volatile u32*)(INCA_IP_ASC+ 0x0014))
-#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value)          (((( 1 << 13) - 1) & (value)) << 0)
-
-/***ASC Fractional Divider Register***/
-#define INCA_IP_ASC_ASC_FDV                      ((volatile u32*)(INCA_IP_ASC+ 0x0018))
-#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value)          (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC IrDA Pulse Mode/Width Register***/
-#define INCA_IP_ASC_ASC_PMW                      ((volatile u32*)(INCA_IP_ASC+ 0x001C))
-#define INCA_IP_ASC_ASC_PMW_IRPW                            (1 << 8)
-#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value)          (((( 1 << 8) - 1) & (value)) << 0)
-
-/***ASC Transmit Buffer Register***/
-#define INCA_IP_ASC_ASC_TBUF                    ((volatile u32*)(INCA_IP_ASC+ 0x0020))
-#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value)          (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Receive Buffer Register***/
-#define INCA_IP_ASC_ASC_RBUF                    ((volatile u32*)(INCA_IP_ASC+ 0x0024))
-#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value)          (((( 1 << 9) - 1) & (value)) << 0)
-
-/***ASC Autobaud Control Register***/
-#define INCA_IP_ASC_ASC_ABCON                    ((volatile u32*)(INCA_IP_ASC+ 0x0030))
-#define INCA_IP_ASC_ASC_ABCON_RXINV                          (1 << 11)
-#define INCA_IP_ASC_ASC_ABCON_TXINV                          (1 << 10)
-#define INCA_IP_ASC_ASC_ABCON_ABEM (value)               (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_ASC_ASC_ABCON_FCDETEN                      (1 << 4)
-#define INCA_IP_ASC_ASC_ABCON_ABDETEN                      (1 << 3)
-#define INCA_IP_ASC_ASC_ABCON_ABSTEN                        (1 << 2)
-#define INCA_IP_ASC_ASC_ABCON_AUREN                          (1 << 1)
-#define INCA_IP_ASC_ASC_ABCON_ABEN                            (1 << 0)
-
-/***Receive FIFO Control Register***/
-#define INCA_IP_ASC_RXFCON                       ((volatile u32*)(INCA_IP_ASC+ 0x0040))
-#define INCA_IP_ASC_RXFCON_RXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_RXFCON_RXTMEN                        (1 << 2)
-#define INCA_IP_ASC_RXFCON_RXFFLU                        (1 << 1)
-#define INCA_IP_ASC_RXFCON_RXFEN                          (1 << 0)
-
-/***Transmit FIFO Control Register***/
-#define INCA_IP_ASC_TXFCON                       ((volatile u32*)(INCA_IP_ASC+ 0x0044))
-#define INCA_IP_ASC_TXFCON_TXFITL (value)             (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_TXFCON_TXTMEN                        (1 << 2)
-#define INCA_IP_ASC_TXFCON_TXFFLU                        (1 << 1)
-#define INCA_IP_ASC_TXFCON_TXFEN                          (1 << 0)
-
-/***FIFO Status Register***/
-#define INCA_IP_ASC_FSTAT                        ((volatile u32*)(INCA_IP_ASC+ 0x0048))
-#define INCA_IP_ASC_FSTAT_TXFFL (value)              (((( 1 << 6) - 1) & (value)) << 8)
-#define INCA_IP_ASC_FSTAT_RXFFL (value)              (((( 1 << 6) - 1) & (value)) << 0)
-
-/***ASC Write HW Modified Autobaud Control Register***/
-#define INCA_IP_ASC_ASC_WHBABCON                 ((volatile u32*)(INCA_IP_ASC+ 0x0054))
-#define INCA_IP_ASC_ASC_WHBABCON_SETABEN                      (1 << 1)
-#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN                      (1 << 0)
-
-/***ASC Autobaud Status Register***/
-#define INCA_IP_ASC_ASC_ABSTAT                   ((volatile u32*)(INCA_IP_ASC+ 0x0034))
-#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT                      (1 << 4)
-#define INCA_IP_ASC_ASC_ABSTAT_SCCDET                        (1 << 3)
-#define INCA_IP_ASC_ASC_ABSTAT_SCSDET                        (1 << 2)
-#define INCA_IP_ASC_ASC_ABSTAT_FCCDET                        (1 << 1)
-#define INCA_IP_ASC_ASC_ABSTAT_FCSDET                        (1 << 0)
-
-/***ASC Write HW Modified Autobaud Status Register***/
-#define INCA_IP_ASC_ASC_WHBABSTAT                 ((volatile u32*)(INCA_IP_ASC+ 0x0058))
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT                (1 << 9)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT                (1 << 8)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET                  (1 << 7)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET                  (1 << 6)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET                  (1 << 5)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET                  (1 << 4)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET                  (1 << 3)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET                  (1 << 2)
-#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET                  (1 << 1)
-#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET                  (1 << 0)
-
-/***ASC Clock Control Register***/
-#define INCA_IP_ASC_ASC_CLC                      ((volatile u32*)(INCA_IP_ASC+ 0x0000))
-#define INCA_IP_ASC_ASC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_ASC_ASC_CLC_DISS                            (1 << 1)
-#define INCA_IP_ASC_ASC_CLC_DISR                            (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  DMA register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_DMA                          (0xBF108000)
-/***********************************************************************/
-
-
-/***DMA RX Channel 0 Command Register***/
-#define INCA_IP_DMA_DMA_RXCCR0                   ((volatile u32*)(INCA_IP_DMA+ 0x0800))
-#define INCA_IP_DMA_DMA_RXCCR0_LBE                              (1 << 31)
-#define INCA_IP_DMA_DMA_RXCCR0_HPEN                            (1 << 30)
-#define INCA_IP_DMA_DMA_RXCCR0_INIT                            (1 << 2)
-#define INCA_IP_DMA_DMA_RXCCR0_OFF                              (1 << 1)
-#define INCA_IP_DMA_DMA_RXCCR0_HR                              (1 << 0)
-
-/***DMA RX Channel 1 Command Register***/
-#define INCA_IP_DMA_DMA_RXCCR1                   ((volatile u32*)(INCA_IP_DMA+ 0x0804))
-#define INCA_IP_DMA_DMA_RXCCR1_LBE                              (1 << 31)
-#define INCA_IP_DMA_DMA_RXCCR1_HPEN                            (1 << 30)
-#define INCA_IP_DMA_DMA_RXCCR1_INIT                            (1 << 2)
-#define INCA_IP_DMA_DMA_RXCCR1_OFF                              (1 << 1)
-#define INCA_IP_DMA_DMA_RXCCR1_HR                              (1 << 0)
-
-/***DMA Receive Interrupt Status Register***/
-#define INCA_IP_DMA_DMA_RXISR                    ((volatile u32*)(INCA_IP_DMA+ 0x0808))
-#define INCA_IP_DMA_DMA_RXISR_RDERRx (value)             (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value)            (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_RXISR_EOPx (value)               (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_RXISR_CPTx (value)               (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_RXISR_HLDx (value)               (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA Receive Interrupt Mask Register***/
-#define INCA_IP_DMA_DMA_RXIMR                    ((volatile u32*)(INCA_IP_DMA+ 0x080C))
-#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value)             (((( 1 << 2) - 1) & (value)) << 8)
-#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value)            (((( 1 << 2) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_RXIMR_EOPx (value)               (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_RXIMR_CPTx (value)               (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_RXIMR_HLDx (value)               (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Rx Channel 0
-***/
-#define INCA_IP_DMA_DMA_RXFRDA0                  ((volatile u32*)(INCA_IP_DMA+ 0x0810))
-#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Rx Channel 1
-***/
-#define INCA_IP_DMA_DMA_RXFRDA1                  ((volatile u32*)(INCA_IP_DMA+ 0x0814))
-#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA Receive Channel Polling Time***/
-#define INCA_IP_DMA_DMA_RXPOLL                   ((volatile u32*)(INCA_IP_DMA+ 0x0818))
-#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value)               (((( 1 << 2) - 1) & (value)) << 30)
-#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value)               (((( 1 << 2) - 1) & (value)) << 28)
-#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value)         (((( 1 << 8) - 1) & (value)) << 0)
-
-/***DMA TX Channel 0 Command Register (Voice Port)***/
-#define INCA_IP_DMA_DMA_TXCCR0                   ((volatile u32*)(INCA_IP_DMA+ 0x0880))
-#define INCA_IP_DMA_DMA_TXCCR0_LBE                              (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR0_HPEN                            (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR0_HR                              (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR0_OFF                              (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR0_INIT                            (1 << 0)
-
-/***DMA TX Channel 1 Command Register (Mangmt Port)***/
-#define INCA_IP_DMA_DMA_TXCCR1                   ((volatile u32*)(INCA_IP_DMA+ 0x0884))
-#define INCA_IP_DMA_DMA_TXCCR1_LBE                              (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR1_HPEN                            (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR1_HR                              (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR1_OFF                              (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR1_INIT                            (1 << 0)
-
-/***DMA TX Channel 2 Command Register (SSC Port)***/
-#define INCA_IP_DMA_DMA_TXCCR2                   ((volatile u32*)(INCA_IP_DMA+ 0x0888))
-#define INCA_IP_DMA_DMA_TXCCR2_LBE                              (1 << 31)
-#define INCA_IP_DMA_DMA_TXCCR2_HPEN                            (1 << 30)
-#define INCA_IP_DMA_DMA_TXCCR2_HBF                              (1 << 29)
-#define INCA_IP_DMA_DMA_TXCCR2_HR                              (1 << 2)
-#define INCA_IP_DMA_DMA_TXCCR2_OFF                              (1 << 1)
-#define INCA_IP_DMA_DMA_TXCCR2_INIT                            (1 << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 0
-***/
-#define INCA_IP_DMA_DMA_TXFRDA0                  ((volatile u32*)(INCA_IP_DMA+ 0x08A0))
-#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 1
-***/
-#define INCA_IP_DMA_DMA_TXFRDA1                  ((volatile u32*)(INCA_IP_DMA+ 0x08A4))
-#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA First Receive Descriptor Addr. for Tx Channel 2
-***/
-#define INCA_IP_DMA_DMA_TXFRDA2                  ((volatile u32*)(INCA_IP_DMA+ 0x08A8))
-#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value)             (((( 1 << 28) - 1) & (value)) << 0)
-
-/***DMA Transmit Channel Arbitration Register***/
-#define INCA_IP_DMA_DMA_TXWGT                    ((volatile u32*)(INCA_IP_DMA+ 0x08C0))
-#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value)              (((( 1 << 2) - 1) & (value)) << 4)
-#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value)             (((( 1 << 2) - 1) & (value)) << 2)
-#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value)             (((( 1 << 2) - 1) & (value)) << 0)
-
-/***DMA Transmit Channel Polling Time***/
-#define INCA_IP_DMA_DMA_TXPOLL                   ((volatile u32*)(INCA_IP_DMA+ 0x08C4))
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value)               (((( 1 << 2) - 1) & (value)) << 30)
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value)               (((( 1 << 2) - 1) & (value)) << 28)
-#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value)               (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value)         (((( 1 << 8) - 1) & (value)) << 0)
-
-/***DMA Transmit Interrupt Status Register***/
-#define INCA_IP_DMA_DMA_TXISR                    ((volatile u32*)(INCA_IP_DMA+ 0x08C8))
-#define INCA_IP_DMA_DMA_TXISR_RDERRx (value)             (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_DMA_DMA_TXISR_HLDx (value)               (((( 1 << 3) - 1) & (value)) << 9)
-#define INCA_IP_DMA_DMA_TXISR_CPTx (value)               (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_TXISR_EOPx (value)               (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value)            (((( 1 << 3) - 1) & (value)) << 0)
-
-/***DMA Transmit Interrupt Mask Register***/
-#define INCA_IP_DMA_DMA_TXIMR                    ((volatile u32*)(INCA_IP_DMA+ 0x08CC))
-#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value)             (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_DMA_DMA_TXIMR_HLDx (value)               (((( 1 << 3) - 1) & (value)) << 9)
-#define INCA_IP_DMA_DMA_TXIMR_CPTx (value)               (((( 1 << 3) - 1) & (value)) << 6)
-#define INCA_IP_DMA_DMA_TXIMR_EOPx (value)               (((( 1 << 3) - 1) & (value)) << 3)
-#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value)            (((( 1 << 3) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  Debug register address and bits                     */
-/***********************************************************************/
-
-#define INCA_IP_Debug                        (0xBF106000)
-/***********************************************************************/
-
-
-/***MCD Break Bus Switch Register***/
-#define INCA_IP_Debug_MCD_BBS                      ((volatile u32*)(INCA_IP_Debug+ 0x0000))
-#define INCA_IP_Debug_MCD_BBS_BTP1                            (1 << 19)
-#define INCA_IP_Debug_MCD_BBS_BTP0                            (1 << 18)
-#define INCA_IP_Debug_MCD_BBS_BSP1                            (1 << 17)
-#define INCA_IP_Debug_MCD_BBS_BSP0                            (1 << 16)
-#define INCA_IP_Debug_MCD_BBS_BT5EN                          (1 << 15)
-#define INCA_IP_Debug_MCD_BBS_BT4EN                          (1 << 14)
-#define INCA_IP_Debug_MCD_BBS_BT5                              (1 << 13)
-#define INCA_IP_Debug_MCD_BBS_BT4                              (1 << 12)
-#define INCA_IP_Debug_MCD_BBS_BS5EN                          (1 << 7)
-#define INCA_IP_Debug_MCD_BBS_BS4EN                          (1 << 6)
-#define INCA_IP_Debug_MCD_BBS_BS5                              (1 << 5)
-#define INCA_IP_Debug_MCD_BBS_BS4                              (1 << 4)
-
-/***MCD Multiplexer Control Register***/
-#define INCA_IP_Debug_MCD_MCR                      ((volatile u32*)(INCA_IP_Debug+ 0x0008))
-#define INCA_IP_Debug_MCD_MCR_MUX5                            (1 << 4)
-#define INCA_IP_Debug_MCD_MCR_MUX4                            (1 << 3)
-#define INCA_IP_Debug_MCD_MCR_MUX1                            (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  TSF register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_TSF                          (0xB8000900)
-/***********************************************************************/
-
-
-/***TSF Configuration Register (0000H)***/
-#define INCA_IP_TSF_TSF_CONF                    ((volatile u32*)(INCA_IP_TSF+ 0x0000))
-#define INCA_IP_TSF_TSF_CONF_PWMEN                          (1 << 2)
-#define INCA_IP_TSF_TSF_CONF_LEDEN                          (1 << 1)
-#define INCA_IP_TSF_TSF_CONF_KEYEN                          (1 << 0)
-
-/***Key scan Configuration Register (0004H)***/
-#define INCA_IP_TSF_KEY_CONF                    ((volatile u32*)(INCA_IP_TSF+ 0x0004))
-#define INCA_IP_TSF_KEY_CONF_SL (value)                (((( 1 << 4) - 1) & (value)) << 0)
-
-/***Scan Register Line 0 and 1 (0008H)***/
-#define INCA_IP_TSF_SREG01                       ((volatile u32*)(INCA_IP_TSF+ 0x0008))
-#define INCA_IP_TSF_SREG01_RES1x (value)              (((( 1 << 12) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG01_RES0x (value)              (((( 1 << 13) - 1) & (value)) << 0)
-
-/***Scan Register Line 2 and 3 (000CH)***/
-#define INCA_IP_TSF_SREG23                       ((volatile u32*)(INCA_IP_TSF+ 0x000C))
-#define INCA_IP_TSF_SREG23_RES3x (value)              (((( 1 << 10) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG23_RES2x (value)              (((( 1 << 11) - 1) & (value)) << 0)
-
-/***Scan Register Line 4, 5 and 6 (0010H)***/
-#define INCA_IP_TSF_SREG456                      ((volatile u32*)(INCA_IP_TSF+ 0x0010))
-#define INCA_IP_TSF_SREG456_RES6x (value)              (((( 1 << 7) - 1) & (value)) << 24)
-#define INCA_IP_TSF_SREG456_RES5x (value)              (((( 1 << 8) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG456_RES4x (value)              (((( 1 << 9) - 1) & (value)) << 0)
-
-/***Scan Register Line 7 to 12 (0014H)***/
-#define INCA_IP_TSF_SREG7to12                    ((volatile u32*)(INCA_IP_TSF+ 0x0014))
-#define INCA_IP_TSF_SREG7to12_RES12x                        (1 << 28)
-#define INCA_IP_TSF_SREG7to12_RES11x (value)             (((( 1 << 2) - 1) & (value)) << 24)
-#define INCA_IP_TSF_SREG7to12_RES10x (value)             (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_TSF_SREG7to12_RES9x (value)              (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_TSF_SREG7to12_RES8x (value)              (((( 1 << 5) - 1) & (value)) << 8)
-#define INCA_IP_TSF_SREG7to12_RES7x (value)              (((( 1 << 6) - 1) & (value)) << 0)
-
-/***LEDMUX Configuration Register (0018H)***/
-#define INCA_IP_TSF_LEDMUX_CONF                  ((volatile u32*)(INCA_IP_TSF+ 0x0018))
-#define INCA_IP_TSF_LEDMUX_CONF_ETL1                            (1 << 25)
-#define INCA_IP_TSF_LEDMUX_CONF_ESTA1                          (1 << 24)
-#define INCA_IP_TSF_LEDMUX_CONF_EDPX1                          (1 << 23)
-#define INCA_IP_TSF_LEDMUX_CONF_EACT1                          (1 << 22)
-#define INCA_IP_TSF_LEDMUX_CONF_ESPD1                          (1 << 21)
-#define INCA_IP_TSF_LEDMUX_CONF_ETL0                            (1 << 20)
-#define INCA_IP_TSF_LEDMUX_CONF_ESTA0                          (1 << 19)
-#define INCA_IP_TSF_LEDMUX_CONF_EDPX0                          (1 << 18)
-#define INCA_IP_TSF_LEDMUX_CONF_EACT0                          (1 << 17)
-#define INCA_IP_TSF_LEDMUX_CONF_ESPD0                          (1 << 16)
-#define INCA_IP_TSF_LEDMUX_CONF_INV                              (1 << 1)
-#define INCA_IP_TSF_LEDMUX_CONF_NCOL                            (1 << 0)
-
-/***LED Register (001CH)***/
-#define INCA_IP_TSF_LED_REG                      ((volatile u32*)(INCA_IP_TSF+ 0x001C))
-#define INCA_IP_TSF_LED_REG_Lxy (value)                (((( 1 << 24) - 1) & (value)) << 0)
-
-/***Pulse Width Modulator 1 and 2 Register (0020H)***/
-#define INCA_IP_TSF_PWM12                        ((volatile u32*)(INCA_IP_TSF+ 0x0020))
-#define INCA_IP_TSF_PWM12_PW2PW1 (value)             (((( 1 << NaN) - 1) & (value)) << NaN)
-
-/***********************************************************************/
-/*  Module      :  Ports register address and bits                     */
-/***********************************************************************/
-
-#define INCA_IP_Ports                        (0xB8000A00)
-/***********************************************************************/
-
-
-/***Port 1 Data Output Register (0020H)***/
-#define INCA_IP_Ports_P1_OUT                       ((volatile u32*)(INCA_IP_Ports+ 0x0020))
-#define INCA_IP_Ports_P1_OUT_P(value)               (1 << value)
-
-
-/***Port 2 Data Output Register (0040H)***/
-#define INCA_IP_Ports_P2_OUT                       ((volatile u32*)(INCA_IP_Ports+ 0x0040))
-#define INCA_IP_Ports_P2_OUT_P(value)               (1 << value)
-
-
-/***Port 1 Data Input Register (0024H)***/
-#define INCA_IP_Ports_P1_IN                        ((volatile u32*)(INCA_IP_Ports+ 0x0024))
-#define INCA_IP_Ports_P1_IN_P(value)               (1 << value)
-
-
-/***Port 2 Data Input Register (0044H)***/
-#define INCA_IP_Ports_P2_IN                        ((volatile u32*)(INCA_IP_Ports+ 0x0044))
-#define INCA_IP_Ports_P2_IN_P(value)               (1 << value)
-
-
-/***Port 1 Direction Register (0028H)***/
-#define INCA_IP_Ports_P1_DIR                       ((volatile u32*)(INCA_IP_Ports+ 0x0028))
-#define INCA_IP_Ports_P1_DIR_Port1P(value)         (1 << value)
-
-#define INCA_IP_Ports_P1_DIR_Port2Pn (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Port 2 Direction Register (0048H)***/
-#define INCA_IP_Ports_P2_DIR                       ((volatile u32*)(INCA_IP_Ports+ 0x0048))
-#define INCA_IP_Ports_P2_DIR_Port1P(value)         (1 << value)
-
-#define INCA_IP_Ports_P2_DIR_Port2Pn (value)          (((( 1 << 16) - 1) & (value)) << 0)
-
-/***Port 0 Alternate Function Select Register 0 (000C H)
-***/
-#define INCA_IP_Ports_P0_ALTSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x000C))
-#define INCA_IP_Ports_P0_ALTSEL_Port0P(value)         (1 << value)
-
-
-/***Port 1 Alternate Function Select Register 0 (002C H)
-***/
-#define INCA_IP_Ports_P1_ALTSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x002C))
-#define INCA_IP_Ports_P1_ALTSEL_Port1P(value)         (1 << value)
-
-#define INCA_IP_Ports_P1_ALTSEL_Port2P(value)         (1 << value)
-
-
-/***Port 2 Alternate Function Select Register 0 (004C H)
-***/
-#define INCA_IP_Ports_P2_ALTSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x004C))
-#define INCA_IP_Ports_P2_ALTSEL_Port1P(value)         (1 << value)
-
-#define INCA_IP_Ports_P2_ALTSEL_Port2P(value)         (1 << value)
-
-
-/***Port 0 Input Schmitt-Trigger Off Register (0010 H)
-***/
-#define INCA_IP_Ports_P0_STOFF                    ((volatile u32*)(INCA_IP_Ports+ 0x0010))
-#define INCA_IP_Ports_P0_STOFF_Port0P(value)         (1 << value)
-
-
-/***Port 1 Input Schmitt-Trigger Off Register (0030 H)
-***/
-#define INCA_IP_Ports_P1_STOFF                    ((volatile u32*)(INCA_IP_Ports+ 0x0030))
-#define INCA_IP_Ports_P1_STOFF_Port1P(value)         (1 << value)
-
-#define INCA_IP_Ports_P1_STOFF_Port2P(value)         (1 << value)
-
-
-/***Port 2 Input Schmitt-Trigger Off Register (0050 H)
-***/
-#define INCA_IP_Ports_P2_STOFF                    ((volatile u32*)(INCA_IP_Ports+ 0x0050))
-#define INCA_IP_Ports_P2_STOFF_Port1P(value)         (1 << value)
-
-#define INCA_IP_Ports_P2_STOFF_Port2P(value)         (1 << value)
-
-
-/***Port 2 Open Drain Control Register (0054H)***/
-#define INCA_IP_Ports_P2_OD                        ((volatile u32*)(INCA_IP_Ports+ 0x0054))
-#define INCA_IP_Ports_P2_OD_Port2P(value)         (1 << value)
-
-
-/***Port 0 Pull Up Device Enable Register (0018 H)***/
-#define INCA_IP_Ports_P0_PUDEN                    ((volatile u32*)(INCA_IP_Ports+ 0x0018))
-#define INCA_IP_Ports_P0_PUDEN_Port0P(value)         (1 << value)
-
-
-/***Port 2 Pull Up Device Enable Register (0058 H)***/
-#define INCA_IP_Ports_P2_PUDEN                    ((volatile u32*)(INCA_IP_Ports+ 0x0058))
-#define INCA_IP_Ports_P2_PUDEN_Port2P(value)         (1 << value)
-
-#define INCA_IP_Ports_P2_PUDEN_Port2P(value)         (1 << value)
-
-
-/***Port 0 Pull Up/Pull Down Select Register (001C H)***/
-#define INCA_IP_Ports_P0_PUDSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x001C))
-#define INCA_IP_Ports_P0_PUDSEL_Port0P(value)         (1 << value)
-
-
-/***Port 2 Pull Up/Pull Down Select Register (005C H)***/
-#define INCA_IP_Ports_P2_PUDSEL                    ((volatile u32*)(INCA_IP_Ports+ 0x005C))
-#define INCA_IP_Ports_P2_PUDSEL_Port2P(value)         (1 << value)
-
-#define INCA_IP_Ports_P2_PUDSEL_Port2P(value)         (1 << value)
-
-
-/***********************************************************************/
-/*  Module      :  DES/3DES register address and bits                 */
-/***********************************************************************/
-
-#define INCA_IP_DES_3DES                    (0xB8000800)
-/***********************************************************************/
-
-
-/***DES Input Data High Register***/
-#define INCA_IP_DES_3DES_DES_IHR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000))
-#define INCA_IP_DES_3DES_DES_IHR_IH(value)               (1 << value)
-
-
-/***DES Input Data Low Register***/
-#define INCA_IP_DES_3DES_DES_ILR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004))
-#define INCA_IP_DES_3DES_DES_ILR_IL(value)               (1 << value)
-
-
-/***DES Key #1 High Register***/
-#define INCA_IP_DES_3DES_DES_K1HR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008))
-#define INCA_IP_DES_3DES_DES_K1HR_K1H(value)              (1 << value)
-
-
-/***DES Key #1 Low Register***/
-#define INCA_IP_DES_3DES_DES_K1LR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C))
-#define INCA_IP_DES_3DES_DES_K1LR_K1L(value)              (1 << value)
-
-
-/***DES Key #2 High Register***/
-#define INCA_IP_DES_3DES_DES_K2HR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010))
-#define INCA_IP_DES_3DES_DES_K2HR_K2H(value)              (1 << value)
-
-
-/***DES Key #2 Low Register***/
-#define INCA_IP_DES_3DES_DES_K2LR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014))
-#define INCA_IP_DES_3DES_DES_K2LR_K2L(value)              (1 << value)
-
-
-/***DES Key #3 High Register***/
-#define INCA_IP_DES_3DES_DES_K3HR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018))
-#define INCA_IP_DES_3DES_DES_K3HR_K3H(value)              (1 << value)
-
-
-/***DES Key #3 Low Register***/
-#define INCA_IP_DES_3DES_DES_K3LR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C))
-#define INCA_IP_DES_3DES_DES_K3LR_K3L(value)              (1 << value)
-
-
-/***DES Initialization Vector High Register***/
-#define INCA_IP_DES_3DES_DES_IVHR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020))
-#define INCA_IP_DES_3DES_DES_IVHR_IVH(value)              (1 << value)
-
-
-/***DES Initialization Vector Low Register***/
-#define INCA_IP_DES_3DES_DES_IVLR                    ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024))
-#define INCA_IP_DES_3DES_DES_IVLR_IVL(value)              (1 << value)
-
-
-/***DES Control Register***/
-#define INCA_IP_DES_3DES_DES_CONTROLR                 ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028))
-#define INCA_IP_DES_3DES_DES_CONTROLR_KRE                              (1 << 31)
-#define INCA_IP_DES_3DES_DES_CONTROLR_DAU                              (1 << 16)
-#define INCA_IP_DES_3DES_DES_CONTROLR_F(value)               (1 << value)
-
-#define INCA_IP_DES_3DES_DES_CONTROLR_O(value)               (1 << value)
-
-#define INCA_IP_DES_3DES_DES_CONTROLR_GO                              (1 << 8)
-#define INCA_IP_DES_3DES_DES_CONTROLR_STP                              (1 << 7)
-#define INCA_IP_DES_3DES_DES_CONTROLR_IEN                              (1 << 6)
-#define INCA_IP_DES_3DES_DES_CONTROLR_BUS                              (1 << 5)
-#define INCA_IP_DES_3DES_DES_CONTROLR_SM                              (1 << 4)
-#define INCA_IP_DES_3DES_DES_CONTROLR_E_D                              (1 << 3)
-#define INCA_IP_DES_3DES_DES_CONTROLR_M(value)               (1 << value)
-
-
-/***DES Output Data High Register***/
-#define INCA_IP_DES_3DES_DES_OHR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C))
-#define INCA_IP_DES_3DES_DES_OHR_OH(value)               (1 << value)
-
-
-/***DES Output Data Low Register***/
-#define INCA_IP_DES_3DES_DES_OLR                      ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030))
-#define INCA_IP_DES_3DES_DES_OLR_OL(value)               (1 << value)
-
-
-/***********************************************************************/
-/*  Module      :  AES register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_AES                          (0xB8000880)
-/***********************************************************************/
-
-
-/***AES Input Data 3 Register***/
-#define INCA_IP_AES_AES_ID3R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID3R_I(value)               (1 << value)
-
-
-/***AES Input Data 2 Register***/
-#define INCA_IP_AES_AES_ID2R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID2R_I(value)               (1 << value)
-
-
-/***AES Input Data 1 Register***/
-#define INCA_IP_AES_AES_ID1R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID1R_I(value)               (1 << value)
-
-
-/***AES Input Data 0 Register***/
-#define INCA_IP_AES_AES_ID0R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_ID0R_I(value)               (1 << value)
-
-
-/***AES Output Data 3 Register***/
-#define INCA_IP_AES_AES_OD3R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD3R_O(value)               (1 << value)
-
-
-/***AES Output Data 2 Register***/
-#define INCA_IP_AES_AES_OD2R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD2R_O(value)               (1 << value)
-
-
-/***AES Output Data 1 Register***/
-#define INCA_IP_AES_AES_OD1R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD1R_O(value)               (1 << value)
-
-
-/***AES Output Data 0 Register***/
-#define INCA_IP_AES_AES_OD0R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_OD0R_O(value)               (1 << value)
-
-
-/***AES Key 7 Register***/
-#define INCA_IP_AES_AES_K7R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K7R_K(value)               (1 << value)
-
-
-/***AES Key 6 Register***/
-#define INCA_IP_AES_AES_K6R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K6R_K(value)               (1 << value)
-
-
-/***AES Key 5 Register***/
-#define INCA_IP_AES_AES_K5R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K5R_K(value)               (1 << value)
-
-
-/***AES Key 4 Register***/
-#define INCA_IP_AES_AES_K4R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K4R_K(value)               (1 << value)
-
-
-/***AES Key 3 Register***/
-#define INCA_IP_AES_AES_K3R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K3R_K(value)               (1 << value)
-
-
-/***AES Key 2 Register***/
-#define INCA_IP_AES_AES_K2R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K2R_K(value)               (1 << value)
-
-
-/***AES Key 1 Register***/
-#define INCA_IP_AES_AES_K1R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K1R_K(value)               (1 << value)
-
-
-/***AES Key 0 Register***/
-#define INCA_IP_AES_AES_K0R                      ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_K0R_K(value)               (1 << value)
-
-
-/***AES Initialization Vector 3 Register***/
-#define INCA_IP_AES_AES_IV3R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV3R_IV(value)               (1 << value)
-
-
-/***AES Initialization Vector 2 Register***/
-#define INCA_IP_AES_AES_IV2R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV2R_IV(value)               (1 << value)
-
-
-/***AES Initialization Vector 1 Register***/
-#define INCA_IP_AES_AES_IV1R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV1R_IV(value)               (1 << value)
-
-
-/***AES Initialization Vector 0 Register***/
-#define INCA_IP_AES_AES_IV0R                    ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_IV0R_IV (value)                (((( 1 << 32) - 1) &(value)) << 0)
-
-/***AES Control Register***/
-#define INCA_IP_AES_AES_CONTROLR                 ((volatile u32*)(INCA_IP_AES+ 0x0000))
-#define INCA_IP_AES_AES_CONTROLR_KRE                              (1 << 31)
-#define INCA_IP_AES_AES_CONTROLR_DAU                              (1 << 16)
-#define INCA_IP_AES_AES_CONTROLR_PNK                              (1 << 15)
-#define INCA_IP_AES_AES_CONTROLR_F(value)               (1 << value)
-
-#define INCA_IP_AES_AES_CONTROLR_O(value)               (1 << value)
-
-#define INCA_IP_AES_AES_CONTROLR_GO                              (1 << 8)
-#define INCA_IP_AES_AES_CONTROLR_STP                              (1 << 7)
-#define INCA_IP_AES_AES_CONTROLR_IEN                              (1 << 6)
-#define INCA_IP_AES_AES_CONTROLR_BUS                              (1 << 5)
-#define INCA_IP_AES_AES_CONTROLR_SM                              (1 << 4)
-#define INCA_IP_AES_AES_CONTROLR_E_D                              (1 << 3)
-#define INCA_IP_AES_AES_CONTROLR_KV                              (1 << 2)
-#define INCA_IP_AES_AES_CONTROLR_K(value)               (1 << value)
-
-
-/***********************************************************************/
-/*  Module      :  I²C register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_IIC                          (0xB8000700)
-/***********************************************************************/
-
-
-/***I²C Port Input Select Register***/
-#define INCA_IP_IIC_IIC_PISEL                    ((volatile u32*)(INCA_IP_IIC+ 0x0004))
-#define INCA_IP_IIC_IIC_PISEL_SDAIS(value)            (1 << value)
-
-#define INCA_IP_IIC_IIC_PISEL_SCLIS(value)            (1 << value)
-
-
-/***I²C Clock Control Register***/
-#define INCA_IP_IIC_IIC_CLC                      ((volatile u32*)(INCA_IP_IIC+ 0x0000))
-#define INCA_IP_IIC_IIC_CLC_RMC (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_CLC_DISS                            (1 << 1)
-#define INCA_IP_IIC_IIC_CLC_DISR                            (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_0                 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_0_WMEN                            (1 << 31)
-#define INCA_IP_IIC_IIC_SYSCON_0_CI (value)                (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_IIC_IIC_SYSCON_0_STP                              (1 << 25)
-#define INCA_IP_IIC_IIC_SYSCON_0_IGE                              (1 << 24)
-#define INCA_IP_IIC_IIC_SYSCON_0_TRX                              (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_0_INT                              (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS                        (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_0_BUM                              (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value)                (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_0_RSC                              (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_0_M10                              (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_0_RMEN                            (1 << 15)
-#define INCA_IP_IIC_IIC_SYSCON_0_CO (value)                (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQE                            (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQP                            (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_0_IRQD                            (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_0_BB                              (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_0_LRB                              (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_0_SLA                              (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_0_AL                              (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_0_ADR                              (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_1                 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_1_RM (value)                (((( 1 << 8) - 1) & (value)) << 24)
-#define INCA_IP_IIC_IIC_SYSCON_1_TRX                              (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_1_INT                              (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS                        (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_1_BUM                              (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value)                (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_1_RSC                              (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_1_M10                              (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_1_RMEN                            (1 << 15)
-#define INCA_IP_IIC_IIC_SYSCON_1_CO (value)                (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQE                            (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQP                            (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_1_IRQD                            (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_1_BB                              (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_1_LRB                              (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_1_SLA                              (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_1_AL                              (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_1_ADR                              (1 << 0)
-
-/***I²C System Control Register***/
-#define INCA_IP_IIC_IIC_SYSCON_2                 ((volatile u32*)(INCA_IP_IIC+ 0x0010))
-#define INCA_IP_IIC_IIC_SYSCON_2_WMEN                            (1 << 31)
-#define INCA_IP_IIC_IIC_SYSCON_2_CI (value)                (((( 1 << 2) - 1) & (value)) << 26)
-#define INCA_IP_IIC_IIC_SYSCON_2_STP                              (1 << 25)
-#define INCA_IP_IIC_IIC_SYSCON_2_IGE                              (1 << 24)
-#define INCA_IP_IIC_IIC_SYSCON_2_TRX                              (1 << 23)
-#define INCA_IP_IIC_IIC_SYSCON_2_INT                              (1 << 22)
-#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS                        (1 << 21)
-#define INCA_IP_IIC_IIC_SYSCON_2_BUM                              (1 << 20)
-#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value)                (((( 1 << 2) - 1) & (value)) << 18)
-#define INCA_IP_IIC_IIC_SYSCON_2_RSC                              (1 << 17)
-#define INCA_IP_IIC_IIC_SYSCON_2_M10                              (1 << 16)
-#define INCA_IP_IIC_IIC_SYSCON_2_WM (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQE                            (1 << 7)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQP                            (1 << 6)
-#define INCA_IP_IIC_IIC_SYSCON_2_IRQD                            (1 << 5)
-#define INCA_IP_IIC_IIC_SYSCON_2_BB                              (1 << 4)
-#define INCA_IP_IIC_IIC_SYSCON_2_LRB                              (1 << 3)
-#define INCA_IP_IIC_IIC_SYSCON_2_SLA                              (1 << 2)
-#define INCA_IP_IIC_IIC_SYSCON_2_AL                              (1 << 1)
-#define INCA_IP_IIC_IIC_SYSCON_2_ADR                              (1 << 0)
-
-/***I²C Write Hardware Modified System Control Register
-***/
-#define INCA_IP_IIC_IIC_WHBSYSCON                 ((volatile u32*)(INCA_IP_IIC+ 0x0020))
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN                      (1 << 31)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN                      (1 << 30)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP                        (1 << 26)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP                        (1 << 25)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX                        (1 << 24)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX                        (1 << 23)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS                  (1 << 22)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS                  (1 << 21)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM                        (1 << 20)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM                        (1 << 19)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC                        (1 << 17)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC                        (1 << 16)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN                      (1 << 15)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN                      (1 << 14)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE                      (1 << 10)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP                      (1 << 9)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD                      (1 << 8)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE                      (1 << 7)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP                      (1 << 6)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD                      (1 << 5)
-#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL                          (1 << 2)
-#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL                          (1 << 1)
-
-/***I²C Bus Control Register***/
-#define INCA_IP_IIC_IIC_BUSCON_0                 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
-#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD                        (1 << 31)
-#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value)             (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value)             (((( 1 << 10) - 1) & (value)) << 16)
-#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value)            (1 << value)
-
-#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value)            (1 << value)
-
-
-/***I²C Bus Control Register***/
-#define INCA_IP_IIC_IIC_BUSCON_1                 ((volatile u32*)(INCA_IP_IIC+ 0x0014))
-#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD                        (1 << 31)
-#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value)             (((( 1 << 2) - 1) & (value)) << 29)
-#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value)             (((( 1 << 7) - 1) & (value)) << 17)
-#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value)            (1 << value)
-
-#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value)            (1 << value)
-
-
-/***I²C Receive Transmit Buffer***/
-#define INCA_IP_IIC_IIC_RTB                      ((volatile u32*)(INCA_IP_IIC+ 0x0018))
-#define INCA_IP_IIC_IIC_RTB_RTB(value)              (1 << value)
-
-
-/***********************************************************************/
-/*  Module      :  FB register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_FB                          (0xBF880000)
-/***********************************************************************/
-
-
-/***FB Access Error Cause Register***/
-#define INCA_IP_FB_FB_ERRCAUSE                  ((volatile u32*)(INCA_IP_FB+ 0x0100))
-#define INCA_IP_FB_FB_ERRCAUSE_ERR                              (1 << 31)
-#define INCA_IP_FB_FB_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***FB Access Error Address Register***/
-#define INCA_IP_FB_FB_ERRADDR                   ((volatile u32*)(INCA_IP_FB+ 0x0108))
-#define INCA_IP_FB_FB_ERRADDR_ADDR
-
-/***FB Configuration Register***/
-#define INCA_IP_FB_FB_CFG                       ((volatile u32*)(INCA_IP_FB+ 0x0800))
-#define INCA_IP_FB_FB_CFG_SVM                              (1 << 0)
-
-/***********************************************************************/
-/*  Module      :  SRAM register address and bits                      */
-/***********************************************************************/
-
-#define INCA_IP_SRAM                         (0xBF980000)
-/***********************************************************************/
-
-
-/***SRAM Size Register***/
-#define INCA_IP_SRAM_SRAM_SIZE                    ((volatile u32*)(INCA_IP_SRAM+ 0x0800))
-#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value)               (((( 1 << 23) - 1) & (value)) << 0)
-
-/***********************************************************************/
-/*  Module      :  BIU register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_BIU                          (0xBFA80000)
-/***********************************************************************/
-
-
-/***BIU Identification Register***/
-#define INCA_IP_BIU_BIU_ID                       ((volatile u32*)(INCA_IP_BIU+ 0x0000))
-#define INCA_IP_BIU_BIU_ID_ARCH                            (1 << 16)
-#define INCA_IP_BIU_BIU_ID_ID (value)                (((( 1 << 8) - 1) & (value)) << 8)
-#define INCA_IP_BIU_BIU_ID_REV (value)                (((( 1 << 8) - 1) & (value)) << 0)
-
-/***BIU Access Error Cause Register***/
-#define INCA_IP_BIU_BIU_ERRCAUSE                 ((volatile u32*)(INCA_IP_BIU+ 0x0100))
-#define INCA_IP_BIU_BIU_ERRCAUSE_ERR                              (1 << 31)
-#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value)               (((( 1 << 4) - 1) & (value)) << 16)
-#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value)              (((( 1 << 2) - 1) & (value)) << 0)
-
-/***BIU Access Error Address Register***/
-#define INCA_IP_BIU_BIU_ERRADDR                  ((volatile u32*)(INCA_IP_BIU+ 0x0108))
-#define INCA_IP_BIU_BIU_ERRADDR_ADDR
-
-/***********************************************************************/
-/*  Module      :  ICU register address and bits                       */
-/***********************************************************************/
-
-#define INCA_IP_ICU                          (0xBF101000)
-/***********************************************************************/
-
-
-/***IM0 Interrupt Status Register***/
-#define INCA_IP_ICU_IM0_ISR                      ((volatile u32*)(INCA_IP_ICU+ 0x0000))
-#define INCA_IP_ICU_IM0_ISR_IR(value)               (1 << value)
-
-
-/***IM1 Interrupt Status Register***/
-#define INCA_IP_ICU_IM1_ISR                      ((volatile u32*)(INCA_IP_ICU+ 0x0200))
-#define INCA_IP_ICU_IM1_ISR_IR(value)               (1 << value)
-
-
-/***IM2 Interrupt Status Register***/
-#define INCA_IP_ICU_IM2_ISR                      ((volatile u32*)(INCA_IP_ICU+ 0x0400))
-#define INCA_IP_ICU_IM2_ISR_IR(value)               (1 << value)
-
-
-/***IM0 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM0_IER                      ((volatile u32*)(INCA_IP_ICU+ 0x0008))
-#define INCA_IP_ICU_IM0_IER_IR(value)               (1 << value)
-
-
-/***IM1 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM1_IER                      ((volatile u32*)(INCA_IP_ICU+ 0x0208))
-#define INCA_IP_ICU_IM1_IER_IR(value)               (1 << value)
-
-
-/***IM2 Interrupt Enable Register***/
-#define INCA_IP_ICU_IM2_IER                      ((volatile u32*)(INCA_IP_ICU+ 0x0408))
-#define INCA_IP_ICU_IM2_IER_IR(value)               (1 << value)
-
-
-/***IM0 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM0_IOSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0010))
-#define INCA_IP_ICU_IM0_IOSR_IR(value)               (1 << value)
-
-
-/***IM1 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM1_IOSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0210))
-#define INCA_IP_ICU_IM1_IOSR_IR(value)               (1 << value)
-
-
-/***IM2 Interrupt Output Status Register***/
-#define INCA_IP_ICU_IM2_IOSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0410))
-#define INCA_IP_ICU_IM2_IOSR_IR(value)               (1 << value)
-
-
-/***IM0 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM0_IRSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0018))
-#define INCA_IP_ICU_IM0_IRSR_IR(value)               (1 << value)
-
-
-/***IM1 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM1_IRSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0218))
-#define INCA_IP_ICU_IM1_IRSR_IR(value)               (1 << value)
-
-
-/***IM2 Interrupt Request Set Register***/
-#define INCA_IP_ICU_IM2_IRSR                    ((volatile u32*)(INCA_IP_ICU+ 0x0418))
-#define INCA_IP_ICU_IM2_IRSR_IR(value)               (1 << value)
-
-
-/***External Interrupt Control Register***/
-#define INCA_IP_ICU_ICU_EICR                    ((volatile u32*)(INCA_IP_ICU+ 0x0B00))
-#define INCA_IP_ICU_ICU_EICR_EII5 (value)               (((( 1 << 3) - 1) & (value)) << 20)
-#define INCA_IP_ICU_ICU_EICR_EII4 (value)               (((( 1 << 3) - 1) & (value)) << 16)
-#define INCA_IP_ICU_ICU_EICR_EII3 (value)               (((( 1 << 3) - 1) & (value)) << 12)
-#define INCA_IP_ICU_ICU_EICR_EII2 (value)               (((( 1 << 3) - 1) & (value)) << 8)
-#define INCA_IP_ICU_ICU_EICR_EII1 (value)               (((( 1 << 3) - 1) & (value)) << 4)
-#define INCA_IP_ICU_ICU_EICR_EII0 (value)               (((( 1 << 3) - 1) & (value)) << 0)

diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index 9f3cce9a628b3bf8906b5b47504d9d7af5567217..a5b2fc08f87926fe8a27a95a054dac9b22e8764e 100644 (file)
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void)
        extern char __image_copy_end[];
        return (unsigned long) &__image_copy_end;
 }
-
-extern int incaip_set_cpuclk(void);

diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index 317c8258de9998ca459fccd9b80feae5d629208e..3200d87e30ae623267541949336118081885ab52 100644 (file)
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -103,9 +103,6 @@ init_fnc_t *init_sequence[] = {
        board_early_init_f,
        timer_init,
        env_init,               /* initialize environment */
-#ifdef CONFIG_INCA_IP
-       incaip_set_cpuclk,      /* set cpu clock according to env. variable */
-#endif
        init_baudrate,          /* initialize baudrate settings */
        serial_init,            /* serial communications setup */
        console_init_f,

diff --git a/board/incaip/Makefile b/board/incaip/Makefile
deleted file mode 100644 (file)
index 602d30e..0000000
--- a/board/incaip/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = incaip.o flash.o
-obj-y  += lowlevel_init.o

diff --git a/board/incaip/README b/board/incaip/README
deleted file mode 100644 (file)
index 1329152..0000000
--- a/board/incaip/README
+++ /dev/null
@@ -1,57 +0,0 @@
-
-Flash programming on the INCA-IP board is complicated because of the
-EBU swapping unit. A BDI2000 can be used for flash programming only
-if the EBU swapping unit is enabled; otherwise it will not detect the
-flash memory. But the EBU swapping unit is disadbled after reset, so
-if you program some code to flash with the swapping unit on, it will
-not be runnable with the swapping unit off.
-
-The consequence is that you have to write a pre-swapped image to
-flash using the BDI2000. A simple host-side tool "inca-swap-bytes" is
-provided in the "tools/" directory. Use it as follows:
-
-       bash$ ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp
-
-Note that the current BDI config file _disables_ the EBU swapping
-unit for the flash bank 0. To enable it, (this is required for the
-BDI flash commands to work) uncomment the following line in the
-config file:
-
-       ;WM32   0xb8000260      0x404161ff ; Swapping unit enabled
-
-and comment out
-
-       WM32    0xb8000260      0x004161ff ; Swapping unit disabled
-
-Alternatively, you can use "mm 0xb8000260 <value>" commands to
-enable/disable the swapping unit manually.
-
-Just for reference, here is the complete sequence of actions we took
-to install a U-Boot image into flash.
-
-    1. ./inca-swap-bytes <u-boot.bin >u-boot.bin.swp
-
-    2. From BDI:
-
-       mm 0xb8000260  0x404161ff
-       erase 0xb0000000
-       erase 0xb0010000
-       prog 0xb0000000 /tftpboot/INCA/u-boot.bin.swp bin
-       mm 0xb8000260 0x004161ff
-       go 0xb0000000
-
-
-Ethernet autonegotiation needs some time to complete. Instead of
-delaying the boot process in all cases, we just start the
-autonegotiation process when U-Boot comes up and that is all. Most
-likely, it will complete by the time the network transfer is
-attempted for the first time. In the worst case, if a transfer is
-attempted before the autonegotiation is complete, just a single
-packet would be lost resulting in a single timeout error, and then
-the transfer would proceed normally. So the time that we would have
-lost unconditionally waiting for the autonegotiation to complete, we
-have to wait only if the file transfer is started immediately after
-reset. We've verified that this works for all the clock
-configurations.
-
-(C) 2003 Wolfgang Denk

diff --git a/board/incaip/config.mk b/board/incaip/config.mk
deleted file mode 100644 (file)
index e854f8e..0000000
--- a/board/incaip/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-#
-# INCA-IP board with MIPS 4Kc CPU core
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xB0000000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80100000

diff --git a/board/incaip/flash.c b/board/incaip/flash.c
deleted file mode 100644 (file)
index a786ac9..0000000
--- a/board/incaip/flash.c
+++ /dev/null
@@ -1,655 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/inca-ip.h>
-
-flash_info_t   flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
- *        has nothing to do with the flash chip being 8-bit or 16-bit.
- */
-#ifdef CONFIG_FLASH_16BIT
-typedef unsigned short FLASH_PORT_WIDTH;
-typedef volatile unsigned short FLASH_PORT_WIDTHV;
-#define        FLASH_ID_MASK   0xFFFF
-#else
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-#define        FLASH_ID_MASK   0xFFFFFFFF
-#endif
-
-#define FPW    FLASH_PORT_WIDTH
-#define FPWV   FLASH_PORT_WIDTHV
-
-#define ORMASK(size) ((-size) & OR_AM_MSK)
-
-#if 0
-#define FLASH_CYCLE1   0x0555
-#define FLASH_CYCLE2   0x02aa
-#else
-#define FLASH_CYCLE1   0x0554
-#define FLASH_CYCLE2   0x02ab
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static void flash_get_offsets(ulong base, flash_info_t *info);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
-       unsigned long size = 0;
-       int i;
-
-       /* Init: no FLASHes known */
-       for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-               ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
-               ulong * buscon = (ulong *)
-                       ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
-
-               /* Disable write protection */
-               *buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
-
-#if 1
-               memset(&flash_info[i], 0, sizeof(flash_info_t));
-#endif
-
-               flash_info[i].size =
-                       flash_get_size((FPW *)flashbase, &flash_info[i]);
-
-               if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-                       printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
-                       i, flash_info[i].size);
-               }
-
-               size += flash_info[i].size;
-       }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_SYS_MONITOR_BASE,
-                     CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-                     flash_get_info(CONFIG_SYS_MONITOR_BASE));
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-       /* ENV protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_ENV_ADDR,
-                     CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-                     flash_get_info(CONFIG_ENV_ADDR));
-#endif
-
-
-       return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
-       FPWV *base = (FPWV *)(info->start[0]);
-
-       /* Put FLASH back in read mode */
-       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
-               *base = (FPW)0x00FF00FF;        /* Intel Read Mode */
-       else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
-               *base = (FPW)0x00F000F0;        /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-       int i;
-
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
-           && (info->flash_id & FLASH_BTYPE)) {
-               int bootsect_size;      /* number of bytes/boot sector  */
-               int sect_size;          /* number of bytes/regular sector */
-
-               bootsect_size = 0x00002000 * (sizeof(FPW)/2);
-               sect_size =     0x00010000 * (sizeof(FPW)/2);
-
-               /* set sector offsets for bottom boot block type        */
-               for (i = 0; i < 8; ++i) {
-                       info->start[i] = base + (i * bootsect_size);
-               }
-               for (i = 8; i < info->sector_count; i++) {
-                       info->start[i] = base + ((i - 7) * sect_size);
-               }
-       }
-       else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
-                && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
-
-               int sect_size;          /* number of bytes/sector */
-
-               sect_size = 0x00010000 * (sizeof(FPW)/2);
-
-               /* set up sector start address table (uniform sector type) */
-               for( i = 0; i < info->sector_count; i++ )
-                       info->start[i] = base + (i * sect_size);
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
-       int i;
-       flash_info_t * info;
-
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
-               info = & flash_info[i];
-               if (info->start[0] <= base && base < info->start[0] + info->size)
-                       break;
-       }
-
-       return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
-       int i;
-       uchar *boottype;
-       uchar *bootletter;
-       char *fmt;
-       uchar botbootletter[] = "B";
-       uchar topbootletter[] = "T";
-       uchar botboottype[] = "bottom boot sector";
-       uchar topboottype[] = "top boot sector";
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_AMD:     printf ("AMD ");                break;
-       case FLASH_MAN_BM:      printf ("BRIGHT MICRO ");       break;
-       case FLASH_MAN_FUJ:     printf ("FUJITSU ");            break;
-       case FLASH_MAN_SST:     printf ("SST ");                break;
-       case FLASH_MAN_STM:     printf ("STM ");                break;
-       case FLASH_MAN_INTEL:   printf ("INTEL ");              break;
-       default:                printf ("Unknown Vendor ");     break;
-       }
-
-       /* check for top or bottom boot, if it applies */
-       if (info->flash_id & FLASH_BTYPE) {
-               boottype = botboottype;
-               bootletter = botbootletter;
-       }
-       else {
-               boottype = topboottype;
-               bootletter = topbootletter;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM640U:
-               fmt = "29LV641D (64 Mbit, uniform sectors)\n";
-               break;
-       case FLASH_28F800C3B:
-       case FLASH_28F800C3T:
-               fmt = "28F800C3%s (8 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL800B:
-       case FLASH_INTEL800T:
-               fmt = "28F800B3%s (8 Mbit, %s)\n";
-               break;
-       case FLASH_28F160C3B:
-       case FLASH_28F160C3T:
-               fmt = "28F160C3%s (16 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL160B:
-       case FLASH_INTEL160T:
-               fmt = "28F160B3%s (16 Mbit, %s)\n";
-               break;
-       case FLASH_28F320C3B:
-       case FLASH_28F320C3T:
-               fmt = "28F320C3%s (32 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL320B:
-       case FLASH_INTEL320T:
-               fmt = "28F320B3%s (32 Mbit, %s)\n";
-               break;
-       case FLASH_28F640C3B:
-       case FLASH_28F640C3T:
-               fmt = "28F640C3%s (64 Mbit, %s)\n";
-               break;
-       case FLASH_INTEL640B:
-       case FLASH_INTEL640T:
-               fmt = "28F640B3%s (64 Mbit, %s)\n";
-               break;
-       default:
-               fmt = "Unknown Chip Type\n";
-               break;
-       }
-
-       printf (fmt, bootletter, boottype);
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20,
-               info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-
-       for (i=0; i<info->sector_count; ++i) {
-               if ((i % 5) == 0) {
-                       printf ("\n   ");
-               }
-
-               printf (" %08lX%s", info->start[i],
-                       info->protect[i] ? " (RO)" : "     ");
-       }
-
-       printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
-       /* Write auto select command: read Manufacturer ID */
-
-       /* Write auto select command sequence and test FLASH answer */
-       addr[FLASH_CYCLE1] = (FPW)0x00AA00AA;   /* for AMD, Intel ignores this */
-       addr[FLASH_CYCLE2] = (FPW)0x00550055;   /* for AMD, Intel ignores this */
-       addr[FLASH_CYCLE1] = (FPW)0x00900090;   /* selects Intel or AMD */
-
-       /* The manufacturer codes are only 1 byte, so just use 1 byte.
-        * This works for any bus width and any FLASH device width.
-        */
-       switch (addr[1] & 0xff) {
-
-       case (uchar)AMD_MANUFACT:
-               info->flash_id = FLASH_MAN_AMD;
-               break;
-
-       case (uchar)INTEL_MANUFACT:
-               info->flash_id = FLASH_MAN_INTEL;
-               break;
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               break;
-       }
-
-       /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
-       if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) {
-
-       case (FPW)AMD_ID_LV640U:        /* 29LV640 and 29LV641 have same ID */
-               info->flash_id += FLASH_AM640U;
-               info->sector_count = 128;
-               info->size = 0x00800000 * (sizeof(FPW)/2);
-               break;                          /* => 8 or 16 MB        */
-
-       case (FPW)INTEL_ID_28F800C3B:
-               info->flash_id += FLASH_28F800C3B;
-               info->sector_count = 23;
-               info->size = 0x00100000 * (sizeof(FPW)/2);
-               break;                          /* => 1 or 2 MB         */
-
-       case (FPW)INTEL_ID_28F800B3B:
-               info->flash_id += FLASH_INTEL800B;
-               info->sector_count = 23;
-               info->size = 0x00100000 * (sizeof(FPW)/2);
-               break;                          /* => 1 or 2 MB         */
-
-       case (FPW)INTEL_ID_28F160C3B:
-               info->flash_id += FLASH_28F160C3B;
-               info->sector_count = 39;
-               info->size = 0x00200000 * (sizeof(FPW)/2);
-               break;                          /* => 2 or 4 MB         */
-
-       case (FPW)INTEL_ID_28F160B3B:
-               info->flash_id += FLASH_INTEL160B;
-               info->sector_count = 39;
-               info->size = 0x00200000 * (sizeof(FPW)/2);
-               break;                          /* => 2 or 4 MB         */
-
-       case (FPW)INTEL_ID_28F320C3B:
-               info->flash_id += FLASH_28F320C3B;
-               info->sector_count = 71;
-               info->size = 0x00400000 * (sizeof(FPW)/2);
-               break;                          /* => 4 or 8 MB         */
-
-       case (FPW)INTEL_ID_28F320B3B:
-               info->flash_id += FLASH_INTEL320B;
-               info->sector_count = 71;
-               info->size = 0x00400000 * (sizeof(FPW)/2);
-               break;                          /* => 4 or 8 MB         */
-
-       case (FPW)INTEL_ID_28F640C3B:
-               info->flash_id += FLASH_28F640C3B;
-               info->sector_count = 135;
-               info->size = 0x00800000 * (sizeof(FPW)/2);
-               break;                          /* => 8 or 16 MB        */
-
-       case (FPW)INTEL_ID_28F640B3B:
-               info->flash_id += FLASH_INTEL640B;
-               info->sector_count = 135;
-               info->size = 0x00800000 * (sizeof(FPW)/2);
-               break;                          /* => 8 or 16 MB        */
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               return (0);                     /* => no or unknown flash */
-       }
-
-       flash_get_offsets((ulong)addr, info);
-
-       /* Put FLASH back in read mode */
-       flash_reset(info);
-
-       return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int    flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-       FPWV *addr;
-       int flag, prot, sect;
-       int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
-       ulong start, now, last;
-       int rcode = 0;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_INTEL800B:
-       case FLASH_INTEL160B:
-       case FLASH_INTEL320B:
-       case FLASH_INTEL640B:
-       case FLASH_28F800C3B:
-       case FLASH_28F160C3B:
-       case FLASH_28F320C3B:
-       case FLASH_28F640C3B:
-       case FLASH_AM640U:
-               break;
-       case FLASH_UNKNOWN:
-       default:
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect=s_first; sect<=s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf ("- Warning: %d protected sectors will not be erased!\n",
-                       prot);
-       } else {
-               printf ("\n");
-       }
-
-       last  = get_timer(0);
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
-
-               if (info->protect[sect] != 0)   /* protected, skip it */
-                       continue;
-
-               /* Disable interrupts which might cause a timeout here */
-               flag = disable_interrupts();
-
-               addr = (FPWV *)(info->start[sect]);
-               if (intel) {
-                       *addr = (FPW)0x00500050; /* clear status register */
-                       *addr = (FPW)0x00200020; /* erase setup */
-                       *addr = (FPW)0x00D000D0; /* erase confirm */
-               }
-               else {
-                       /* must be AMD style if not Intel */
-                       FPWV *base;             /* first address in bank */
-
-                       base = (FPWV *)(info->start[0]);
-                       base[FLASH_CYCLE1] = (FPW)0x00AA00AA;   /* unlock */
-                       base[FLASH_CYCLE2] = (FPW)0x00550055;   /* unlock */
-                       base[FLASH_CYCLE1] = (FPW)0x00800080;   /* erase mode */
-                       base[FLASH_CYCLE1] = (FPW)0x00AA00AA;   /* unlock */
-                       base[FLASH_CYCLE2] = (FPW)0x00550055;   /* unlock */
-                       *addr = (FPW)0x00300030;        /* erase sector */
-               }
-
-               /* re-enable interrupts if necessary */
-               if (flag)
-                       enable_interrupts();
-
-               start = get_timer(0);
-
-               /* wait at least 50us for AMD, 80us for Intel.
-                * Let's wait 1 ms.
-                */
-               udelay (1000);
-
-               while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-                       if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                               printf ("Timeout\n");
-
-                               if (intel) {
-                                       /* suspend erase        */
-                                       *addr = (FPW)0x00B000B0;
-                               }
-
-                               flash_reset(info);      /* reset to read mode */
-                               rcode = 1;              /* failed */
-                               break;
-                       }
-
-                       /* show that we're waiting */
-                       if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
-                               putc ('.');
-                               last = get_timer(0);
-                       }
-               }
-
-               /* show that we're waiting */
-               if ((get_timer(last)) > CONFIG_SYS_HZ) {        /* every second */
-                       putc ('.');
-                       last = get_timer(0);
-               }
-
-               flash_reset(info);      /* reset to read mode   */
-       }
-
-       printf (" done\n");
-       return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-    FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
-    int bytes;   /* number of bytes to program in current word         */
-    int left;    /* number of bytes left to program                    */
-    int i, res;
-
-    for (left = cnt, res = 0;
-        left > 0 && res == 0;
-        addr += sizeof(data), left -= sizeof(data) - bytes) {
-
-       bytes = addr & (sizeof(data) - 1);
-       addr &= ~(sizeof(data) - 1);
-
-       /* combine source and destination data so can program
-        * an entire word of 16 or 32 bits
-        */
-       for (i = 0; i < sizeof(data); i++) {
-           data <<= 8;
-           if (i < bytes || i - bytes >= left )
-               data += *((uchar *)addr + i);
-           else
-               data += *src++;
-       }
-
-       /* write one word to the flash */
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_AMD:
-               res = write_word_amd(info, (FPWV *)addr, data);
-               break;
-       case FLASH_MAN_INTEL:
-               res = write_word_intel(info, (FPWV *)addr, data);
-               break;
-       default:
-               /* unknown flash type, error! */
-               printf ("missing or unknown FLASH type\n");
-               res = 1;        /* not really a timeout, but gives error */
-               break;
-       }
-    }
-
-    return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
-    ulong start;
-    int flag;
-    int res = 0;       /* result, assume success       */
-    FPWV *base;                /* first address in flash bank  */
-
-    /* Check if Flash is (sufficiently) erased */
-    if ((*dest & data) != data) {
-       return (2);
-    }
-
-
-    base = (FPWV *)(info->start[0]);
-
-    /* Disable interrupts which might cause a timeout here */
-    flag = disable_interrupts();
-
-    base[FLASH_CYCLE1] = (FPW)0x00AA00AA;      /* unlock */
-    base[FLASH_CYCLE2] = (FPW)0x00550055;      /* unlock */
-    base[FLASH_CYCLE1] = (FPW)0x00A000A0;      /* selects program mode */
-
-    *dest = data;              /* start programming the data   */
-
-    /* re-enable interrupts if necessary */
-    if (flag)
-       enable_interrupts();
-
-    start = get_timer (0);
-
-    /* data polling for D7 */
-    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-       if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-           *dest = (FPW)0x00F000F0;    /* reset bank */
-           res = 1;
-       }
-    }
-
-    return (res);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for Intel FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
-{
-    ulong start;
-    int flag;
-    int res = 0;       /* result, assume success       */
-
-    /* Check if Flash is (sufficiently) erased */
-    if ((*dest & data) != data) {
-       return (2);
-    }
-
-    /* Disable interrupts which might cause a timeout here */
-    flag = disable_interrupts();
-
-    *dest = (FPW)0x00500050;   /* clear status register        */
-    *dest = (FPW)0x00FF00FF;   /* make sure in read mode       */
-    *dest = (FPW)0x00400040;   /* program setup                */
-
-    *dest = data;              /* start programming the data   */
-
-    /* re-enable interrupts if necessary */
-    if (flag)
-       enable_interrupts();
-
-    start = get_timer (0);
-
-    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
-       if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-           *dest = (FPW)0x00B000B0;    /* Suspend program      */
-           res = 1;
-       }
-    }
-
-    if (res == 0 && (*dest & (FPW)0x00100010))
-       res = 1;        /* write failed, time out error is close enough */
-
-    *dest = (FPW)0x00500050;   /* clear status register        */
-    *dest = (FPW)0x00FF00FF;   /* make sure in read mode       */
-
-    return (res);
-}

diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
deleted file mode 100644 (file)
index 217b8af..0000000
--- a/board/incaip/incaip.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/addrspace.h>
-#include <asm/inca-ip.h>
-#include <asm/io.h>
-#include <asm/reboot.h>
-
-extern uint incaip_get_cpuclk(void);
-
-void _machine_restart(void)
-{
-       *INCA_IP_WDT_RST_REQ = 0x3f;
-}
-
-static ulong max_sdram_size(void)
-{
-       /* The only supported SDRAM data width is 16bit.
-        */
-#define CONFIG_SYS_DW  2
-
-       /* The only supported number of SDRAM banks is 4.
-        */
-#define CONFIG_SYS_NB  4
-
-       ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
-       int   cols   = cfgpb0 & 0xF;
-       int   rows   = (cfgpb0 & 0xF0) >> 4;
-       ulong size   = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
-
-       return size;
-}
-
-phys_size_t initdram(int board_type)
-{
-       int   rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
-       ulong size, max_size       = 0;
-       ulong our_address;
-
-       asm volatile ("move %0, $25" : "=r" (our_address) :);
-
-               /* Can't probe for RAM size unless we are running from Flash.
-                */
-       if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
-       {
-               return max_sdram_size();
-       }
-
-       for (cols = 0x8; cols <= 0xC; cols++)
-       {
-               for (rows = 0xB; rows <= 0xD; rows++)
-               {
-                       *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
-                                                  (rows << 4) | cols;
-                       size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
-                                                            max_sdram_size());
-
-                       if (size > max_size)
-                       {
-                               best_val = *INCA_IP_SDRAM_MC_CFGPB0;
-                               max_size = size;
-                       }
-               }
-       }
-
-       *INCA_IP_SDRAM_MC_CFGPB0 = best_val;
-       return max_size;
-}
-
-int checkboard (void)
-{
-       unsigned long chipid = *INCA_IP_WDT_CHIPID;
-       int part_num;
-
-       puts ("Board: INCA-IP ");
-       part_num = (chipid >> 12) & 0xffff;
-       switch (part_num) {
-       case 0xc0:
-               printf ("Standard Version, ");
-               break;
-       case 0xc1:
-               printf ("Basic Version, ");
-               break;
-       default:
-               printf ("Unknown Part Number 0x%x ", part_num);
-               break;
-       }
-
-       printf ("Chip V1.%ld, ", (chipid >> 28));
-
-       printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
-
-       set_io_port_base(0);
-
-       return 0;
-}
-
-#if defined(CONFIG_INCA_IP_SWITCH)
-int board_eth_init(bd_t *bis)
-{
-       return inca_switch_initialize(bis);
-}
-#endif

diff --git a/board/incaip/lowlevel_init.S b/board/incaip/lowlevel_init.S
deleted file mode 100644 (file)
index b6cf6a9..0000000
--- a/board/incaip/lowlevel_init.S
+++ /dev/null
@@ -1,287 +0,0 @@
-/*
- *  Memory sub-system initialization code for INCA-IP development board.
- *
- *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-
-
-#define EBU_MODUL_BASE         0xB8000200
-#define EBU_CLC(value)         0x0000(value)
-#define EBU_CON(value)         0x0010(value)
-#define EBU_ADDSEL0(value)     0x0020(value)
-#define EBU_ADDSEL1(value)     0x0024(value)
-#define EBU_ADDSEL2(value)     0x0028(value)
-#define EBU_BUSCON0(value)     0x0060(value)
-#define EBU_BUSCON1(value)     0x0064(value)
-#define EBU_BUSCON2(value)     0x0068(value)
-
-#define MC_MODUL_BASE          0xBF800000
-#define MC_ERRCAUSE(value)     0x0100(value)
-#define MC_ERRADDR(value)      0x0108(value)
-#define MC_IOGP(value)         0x0800(value)
-#define MC_SELFRFSH(value)     0x0A00(value)
-#define MC_CTRLENA(value)      0x1000(value)
-#define MC_MRSCODE(value)      0x1008(value)
-#define MC_CFGDW(value)                0x1010(value)
-#define MC_CFGPB0(value)       0x1018(value)
-#define MC_LATENCY(value)      0x1038(value)
-#define MC_TREFRESH(value)     0x1040(value)
-
-#define CGU_MODUL_BASE         0xBF107000
-#define CGU_PLL1CR(value)      0x0008(value)
-#define CGU_DIVCR(value)       0x0010(value)
-#define CGU_MUXCR(value)       0x0014(value)
-#define CGU_PLL1SR(value)      0x000C(value)
-
-       .set    noreorder
-
-
-/*
- * void ebu_init(long)
- *
- * a0 has the clock value we are going to run at
- */
-       .globl  ebu_init
-       .ent    ebu_init
-ebu_init:
-__ebu_init:
-
-       li      t1, EBU_MODUL_BASE
-       li      t2, 0xA0000041
-       sw      t2, EBU_ADDSEL0(t1)
-       li      t2, 0xA0800041
-       sw      t2, EBU_ADDSEL2(t1)
-       li      t2, 0xBE0000F1
-       sw      t2, EBU_ADDSEL1(t1)
-
-       li      t3, 100000000
-       beq     a0, t3, 1f
-       nop
-       li      t3, 133000000
-       beq     a0, t3, 2f
-       nop
-       li      t3, 150000000
-       beq     a0, t3, 2f
-       nop
-       b       3f
-       nop
-
-       /* 100 MHz */
-1:
-       li      t2, 0x8841417D
-       sw      t2, EBU_BUSCON0(t1)
-       sw      t2, EBU_BUSCON2(t1)
-       li      t2, 0x684142BD
-       b       3f
-       sw      t2, EBU_BUSCON1(t1)     /* delay slot */
-
-       /* 133 or 150 MHz */
-2:
-       li      t2, 0x8841417E
-       sw      t2, EBU_BUSCON0(t1)
-       sw      t2, EBU_BUSCON2(t1)
-       li      t2, 0x684143FD
-       sw      t2, EBU_BUSCON1(t1)
-3:
-       jr      ra
-       nop
-
-       .end    ebu_init
-
-
-/*
- * void cgu_init(long)
- *
- * a0 has the clock value
- */
-       .globl  cgu_init
-       .ent    cgu_init
-cgu_init:
-__cgu_init:
-
-       li      t1, CGU_MODUL_BASE
-
-       li      t3, 100000000
-       beq     a0, t3, 1f
-       nop
-       li      t3, 133000000
-       beq     a0, t3, 2f
-       nop
-       li      t3, 150000000
-       beq     a0, t3, 3f
-       nop
-       b       5f
-       nop
-
-       /* 100 MHz clock */
-1:
-       li      t2, 0x80000014
-       sw      t2, CGU_DIVCR(t1)
-       li      t2, 0x80000000
-       sw      t2, CGU_MUXCR(t1)
-       li      t2, 0x800B0001
-       b       5f
-       sw      t2, CGU_PLL1CR(t1)      /* delay slot */
-
-       /* 133 MHz clock */
-2:
-       li      t2, 0x80000054
-       sw      t2, CGU_DIVCR(t1)
-       li      t2, 0x80000000
-       sw      t2, CGU_MUXCR(t1)
-       li      t2, 0x800B0001
-       b       5f
-       sw      t2, CGU_PLL1CR(t1)      /* delay slot */
-
-       /* 150 MHz clock */
-3:
-       li      t2, 0x80000017
-       sw      t2, CGU_DIVCR(t1)
-       li      t2, 0xC00B0001
-       sw      t2, CGU_PLL1CR(t1)
-       li      t3, 0x80000000
-4:
-       lw      t2, CGU_PLL1SR(t1)
-       and     t2, t2, t3
-       beq     t2, zero, 4b
-       nop
-       li      t2, 0x80000001
-       sw      t2, CGU_MUXCR(t1)
-5:
-       jr      ra
-       nop
-
-       .end    cgu_init
-
-
-/*
- * void sdram_init(long)
- *
- * a0 has the clock value
- */
-       .globl  sdram_init
-       .ent    sdram_init
-sdram_init:
-__sdram_init:
-
-       li      t1, MC_MODUL_BASE
-
-#if 0
-       /* Disable memory controller before changing any of its registers */
-       sw      zero, MC_CTRLENA(t1)
-#endif
-
-       li      t2, 100000000
-       beq     a0, t2, 1f
-       nop
-       li      t2, 133000000
-       beq     a0, t2, 2f
-       nop
-       li      t2, 150000000
-       beq     a0, t2, 3f
-       nop
-       b       5f
-       nop
-
-       /* 100 MHz clock */
-1:
-       /* Set clock ratio (clkrat=1:1, rddel=3) */
-       li      t2, 0x00000003
-       sw      t2, MC_IOGP(t1)
-
-       /* Set sdram refresh rate (4K/64ms @ 100MHz) */
-       li      t2, 0x0000061A
-       b       4f
-       sw      t2, MC_TREFRESH(t1)
-
-       /* 133 MHz clock */
-2:
-       /* Set clock ratio (clkrat=1:1, rddel=3) */
-       li      t2, 0x00000003
-       sw      t2, MC_IOGP(t1)
-
-       /* Set sdram refresh rate (4K/64ms @ 133MHz) */
-       li      t2, 0x00000822
-       b       4f
-       sw      t2, MC_TREFRESH(t1)
-
-       /* 150 MHz clock */
-3:
-       /* Set clock ratio (clkrat=3:2, rddel=4) */
-       li      t2, 0x00000014
-       sw      t2, MC_IOGP(t1)
-
-       /* Set sdram refresh rate (4K/64ms @ 150MHz) */
-       li      t2, 0x00000927
-       sw      t2, MC_TREFRESH(t1)
-
-4:
-       /* Clear Error log registers */
-       sw      zero, MC_ERRCAUSE(t1)
-       sw      zero, MC_ERRADDR(t1)
-
-       /* Clear Power-down registers */
-       sw      zero, MC_SELFRFSH(t1)
-
-       /* Set CAS Latency */
-       li      t2, 0x00000020          /* CL = 2 */
-       sw      t2, MC_MRSCODE(t1)
-
-       /* Set word width to 16 bit */
-       li      t2, 0x2
-       sw      t2, MC_CFGDW(t1)
-
-       /* Set CS0 to SDRAM parameters */
-       li      t2, 0x000014C9
-       sw      t2, MC_CFGPB0(t1)
-
-       /* Set SDRAM latency parameters */
-       li      t2, 0x00026325          /* BC PC100 */
-       sw      t2, MC_LATENCY(t1)
-
-5:
-       /* Finally enable the controller */
-       li      t2, 0x00000001
-       sw      t2, MC_CTRLENA(t1)
-
-       jr      ra
-       nop
-
-       .end    sdram_init
-
-
-       .globl  lowlevel_init
-       .ent    lowlevel_init
-lowlevel_init:
-
-       /* Disable Watchdog.
-        */
-       la      t9, disable_incaip_wdt
-       jalr    t9
-       nop
-
-       /* EBU, CGU and SDRAM Initialization.
-        */
-       li      a0, CONFIG_CPU_CLOCK_RATE
-       move    t0, ra
-
-       /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
-        * modify t0 and a0.
-        */
-       bal     __cgu_init
-       nop
-       bal     __ebu_init
-       nop
-       bal     __sdram_init
-       nop
-       move    ra, t0
-
-       jr      ra
-       nop
-
-       .end    lowlevel_init

diff --git a/boards.cfg b/boards.cfg
index c83aff3b141938a2c5f5e744af742414f03c0c1b..f1f699458b7d099a2c41aa691c62f0c4edaf97d2 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -519,10 +519,6 @@ Active  mips        mips32         au1x00      -               dbau1x00
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1550                             dbau1x00:DBAU1550                                                                                                                 Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               dbau1x00            dbau1550_el                          dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN                                                                                               Thomas Lange <thomas@corelatus.se>
 Active  mips        mips32         au1x00      -               pb1x00              pb1000                               pb1x00:PB1000                                                                                                                     -
-Active  mips        mips32         incaip      -               incaip              incaip                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
-Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <wd@denx.de>
-Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <wd@denx.de>
-Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  mips        mips64         -           -               qemu-mips           qemu_mips64                          qemu-mips64:SYS_BIG_ENDIAN                                                                                                        -
 Active  mips        mips64         -           -               qemu-mips           qemu_mips64el                        qemu-mips64:SYS_LITTLE_ENDIAN                                                                                                     -
 Active  nds32       n1213          ag101       AndesTech       adp-ag101           adp-ag101                            -                                                                                                                                 Andes <uboot@andestech.com>

diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 15c39e767582de2d0372420b58ed898ae4a1c4c2..f9742e7d49454f7ec6bf0983109684e12769e237 100644 (file)
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -125,3 +125,4 @@ MVS1             powerpc     MPC823         306620b     2008-08-26  Andre Schwar
 adsvix           ARM         PXA27x         7610db1     2008-07-30  Adrian Filipi <adrian.filipi@eurotech.com>
 R5200            ColdFire    -              48ead7a     2008-03-31  Zachary P. Landau <zachary.landau@labxtechnologies.com>
 CPCI440          powerpc     440GP          b568fd2     2007-12-27  Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+incaip           mips        mips32         -           2014-04-17  Wolfgang Denk <wd@denx.de>

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 7f9ce90a6d554eb2585f70bf42def4b2a15de071..c25b3c93ce510bad7366e5ec17b112d38dbf8d96 100644 (file)
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
 obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
 obj-$(CONFIG_GRETH) += greth.o
-obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
 obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
 obj-$(CONFIG_LAN91C96) += lan91c96.o

diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c
deleted file mode 100644 (file)
index cdfbfa6..0000000
--- a/drivers/net/inca-ip_sw.c
+++ /dev/null
@@ -1,793 +0,0 @@
-/*
- * INCA-IP internal switch ethernet driver.
- *
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-
-#include <common.h>
-
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/inca-ip.h>
-#include <asm/addrspace.h>
-
-
-#define NUM_RX_DESC    PKTBUFSRX
-#define NUM_TX_DESC    3
-#define TOUT_LOOP      1000000
-
-
-#define DELAY  udelay(10000)
-  /* Sometimes the store word instruction hangs while writing to one
-   * of the Switch registers. Moving the instruction into a separate
-   * function somehow makes the problem go away.
-   */
-static void SWORD(volatile u32 * reg, u32 value)
-{
-       *reg = value;
-}
-
-#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
-#define DMA_READ_REG(reg, value)    value = (u32)*((volatile u32*)reg)
-#define SW_WRITE_REG(reg, value)   \
-       SWORD(reg, value);\
-       DELAY;\
-       SWORD(reg, value);
-
-#define SW_READ_REG(reg, value)           \
-       value = (u32)*((volatile u32*)reg);\
-       DELAY;\
-       value = (u32)*((volatile u32*)reg);
-
-#define INCA_DMA_TX_POLLING_TIME       0x07
-#define INCA_DMA_RX_POLLING_TIME       0x07
-
-#define INCA_DMA_TX_HOLD               0x80000000
-#define INCA_DMA_TX_EOP                        0x40000000
-#define INCA_DMA_TX_SOP                        0x20000000
-#define INCA_DMA_TX_ICPT               0x10000000
-#define INCA_DMA_TX_IEOP               0x08000000
-
-#define INCA_DMA_RX_C                  0x80000000
-#define INCA_DMA_RX_SOP                        0x40000000
-#define INCA_DMA_RX_EOP                        0x20000000
-
-#define INCA_SWITCH_PHY_SPEED_10H      0x1
-#define INCA_SWITCH_PHY_SPEED_10F      0x5
-#define INCA_SWITCH_PHY_SPEED_100H     0x2
-#define INCA_SWITCH_PHY_SPEED_100F     0x6
-
-/************************ Auto MDIX settings ************************/
-#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR                INCA_IP_Ports_P1_DIR
-#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL     INCA_IP_Ports_P1_ALTSEL
-#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT                INCA_IP_Ports_P1_OUT
-#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX    16
-
-#define WAIT_SIGNAL_RETRIES                    100
-#define WAIT_LINK_RETRIES                      100
-#define LINK_RETRY_DELAY                       2000  /* ms */
-/********************************************************************/
-
-typedef struct
-{
-       union {
-               struct {
-                       volatile u32 HOLD               :1;
-                       volatile u32 ICpt               :1;
-                       volatile u32 IEop               :1;
-                       volatile u32 offset             :3;
-                       volatile u32 reserved0          :4;
-                       volatile u32 NFB                :22;
-               }field;
-
-               volatile u32 word;
-       }params;
-
-       volatile u32 nextRxDescPtr;
-
-       volatile u32 RxDataPtr;
-
-       union {
-               struct {
-                       volatile u32 C                  :1;
-                       volatile u32 Sop                :1;
-                       volatile u32 Eop                :1;
-                       volatile u32 reserved3          :12;
-                       volatile u32 NBT                :17;
-               }field;
-
-               volatile u32 word;
-       }status;
-
-} inca_rx_descriptor_t;
-
-
-typedef struct
-{
-       union {
-               struct {
-                       volatile u32 HOLD               :1;
-                       volatile u32 Eop                :1;
-                       volatile u32 Sop                :1;
-                       volatile u32 ICpt               :1;
-                       volatile u32 IEop               :1;
-                       volatile u32 reserved0          :5;
-                       volatile u32 NBA                :22;
-               }field;
-
-               volatile u32 word;
-       }params;
-
-       volatile u32 nextTxDescPtr;
-
-       volatile u32 TxDataPtr;
-
-       volatile u32 C                  :1;
-       volatile u32 reserved3          :31;
-
-} inca_tx_descriptor_t;
-
-
-static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
-static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
-
-static int tx_new, rx_new, tx_hold, rx_hold;
-static int tx_old_hold = -1;
-static int initialized = 0;
-
-
-static int inca_switch_init(struct eth_device *dev, bd_t * bis);
-static int inca_switch_send(struct eth_device *dev, void *packet, int length);
-static int inca_switch_recv(struct eth_device *dev);
-static void inca_switch_halt(struct eth_device *dev);
-static void inca_init_switch_chip(void);
-static void inca_dma_init(void);
-static int inca_amdix(void);
-
-
-int inca_switch_initialize(bd_t * bis)
-{
-       struct eth_device *dev;
-
-#if 0
-       printf("Entered inca_switch_initialize()\n");
-#endif
-
-       if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
-               printf("Failed to allocate memory\n");
-               return 0;
-       }
-       memset(dev, 0, sizeof(*dev));
-
-       inca_dma_init();
-
-       inca_init_switch_chip();
-
-#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
-       inca_amdix();
-#endif
-
-       sprintf(dev->name, "INCA-IP Switch");
-       dev->init = inca_switch_init;
-       dev->halt = inca_switch_halt;
-       dev->send = inca_switch_send;
-       dev->recv = inca_switch_recv;
-
-       eth_register(dev);
-
-#if 0
-       printf("Leaving inca_switch_initialize()\n");
-#endif
-
-       return 0;
-}
-
-
-static int inca_switch_init(struct eth_device *dev, bd_t * bis)
-{
-       int i;
-       u32 v, regValue;
-       u16 wTmp;
-
-#if 0
-       printf("Entering inca_switch_init()\n");
-#endif
-
-       /* Set MAC address.
-        */
-       wTmp = (u16)dev->enetaddr[0];
-       regValue = (wTmp << 8) | dev->enetaddr[1];
-
-       SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
-
-       wTmp = (u16)dev->enetaddr[2];
-       regValue = (wTmp << 8) | dev->enetaddr[3];
-       regValue = regValue << 16;
-       wTmp = (u16)dev->enetaddr[4];
-       regValue |= (wTmp<<8) | dev->enetaddr[5];
-
-       SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
-
-       /* Initialize the descriptor rings.
-        */
-       for (i = 0; i < NUM_RX_DESC; i++) {
-               inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
-               memset(rx_desc, 0, sizeof(rx_ring[i]));
-
-               /* Set maximum size of receive buffer.
-                */
-               rx_desc->params.field.NFB = PKTSIZE_ALIGN;
-
-               /* Set the offset of the receive buffer. Zero means
-                * that the offset mechanism is not used.
-                */
-               rx_desc->params.field.offset = 0;
-
-               /* Check if it is the last descriptor.
-                */
-               if (i == (NUM_RX_DESC - 1)) {
-                       /* Let the last descriptor point to the first
-                        * one.
-                        */
-                       rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
-               } else {
-                       /* Set the address of the next descriptor.
-                        */
-                       rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
-               }
-
-               rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
-       }
-
-#if 0
-       printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
-       printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
-#endif
-
-       for (i = 0; i < NUM_TX_DESC; i++) {
-               inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
-
-               memset(tx_desc, 0, sizeof(tx_ring[i]));
-
-               tx_desc->params.word       = 0;
-               tx_desc->params.field.HOLD = 1;
-               tx_desc->C                 = 1;
-
-                       /* Check if it is the last descriptor.
-                        */
-               if (i == (NUM_TX_DESC - 1)) {
-                               /* Let the last descriptor point to the
-                                * first one.
-                                */
-                       tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
-               } else {
-                               /* Set the address of the next descriptor.
-                                */
-                       tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
-               }
-       }
-
-       /* Initialize RxDMA.
-        */
-       DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
-       debug("RX status = 0x%08X\n", v);
-
-       /* Writing to the FRDA of CHANNEL.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
-
-       /* Writing to the COMMAND REG.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
-
-       /* Initialize TxDMA.
-        */
-       DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
-       debug("TX status = 0x%08X\n", v);
-
-       /* Writing to the FRDA of CHANNEL.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
-
-       tx_new = rx_new = 0;
-
-       tx_hold = NUM_TX_DESC - 1;
-       rx_hold = NUM_RX_DESC - 1;
-
-#if 0
-       rx_ring[rx_hold].params.field.HOLD = 1;
-#endif
-       /* enable spanning tree forwarding, enable the CPU port */
-       /* ST_PT:
-        *      CPS (CPU port status)   0x3 (forwarding)
-        *      LPS (LAN port status)   0x3 (forwarding)
-        *      PPS (PC port status)    0x3 (forwarding)
-        */
-       SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
-
-#if 0
-       printf("Leaving inca_switch_init()\n");
-#endif
-
-       return 0;
-}
-
-
-static int inca_switch_send(struct eth_device *dev, void *packet, int length)
-{
-       int                    i;
-       int                    res      = -1;
-       u32                    command;
-       u32                    regValue;
-       inca_tx_descriptor_t * tx_desc  = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
-
-#if 0
-       printf("Entered inca_switch_send()\n");
-#endif
-
-       if (length <= 0) {
-               printf ("%s: bad packet size: %d\n", dev->name, length);
-               goto Done;
-       }
-
-       for(i = 0; tx_desc->C == 0; i++) {
-               if (i >= TOUT_LOOP) {
-                       printf("%s: tx error buffer not ready\n", dev->name);
-                       goto Done;
-               }
-       }
-
-       if (tx_old_hold >= 0) {
-               ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
-       }
-       tx_old_hold = tx_hold;
-
-       tx_desc->params.word =
-                       (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
-
-       tx_desc->C = 0;
-       tx_desc->TxDataPtr = (u32)packet;
-       tx_desc->params.field.NBA = length;
-
-       ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
-
-       tx_hold = tx_new;
-       tx_new  = (tx_new + 1) % NUM_TX_DESC;
-
-
-       if (! initialized) {
-               command = INCA_IP_DMA_DMA_TXCCR0_INIT;
-               initialized = 1;
-       } else {
-               command = INCA_IP_DMA_DMA_TXCCR0_HR;
-       }
-
-       DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
-       regValue |= command;
-#if 0
-       printf("regValue = 0x%x\n", regValue);
-#endif
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
-
-#if 1
-       for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
-               if (i >= TOUT_LOOP) {
-                       printf("%s: tx buffer not ready\n", dev->name);
-                       goto Done;
-               }
-       }
-#endif
-       res = length;
-Done:
-#if 0
-       printf("Leaving inca_switch_send()\n");
-#endif
-       return res;
-}
-
-
-static int inca_switch_recv(struct eth_device *dev)
-{
-       int                    length  = 0;
-       inca_rx_descriptor_t * rx_desc;
-
-#if 0
-       printf("Entered inca_switch_recv()\n");
-#endif
-
-       for (;;) {
-               rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
-
-               if (rx_desc->status.field.C == 0) {
-                       break;
-               }
-
-#if 0
-               rx_ring[rx_new].params.field.HOLD = 1;
-#endif
-
-               if (! rx_desc->status.field.Eop) {
-                       printf("Partly received packet!!!\n");
-                       break;
-               }
-
-               length = rx_desc->status.field.NBT;
-               rx_desc->status.word &=
-                        ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
-#if 0
-{
-  int i;
-  for (i=0;i<length - 4;i++) {
-    if (i % 16 == 0) printf("\n%04x: ", i);
-    printf("%02X ", NetRxPackets[rx_new][i]);
-  }
-  printf("\n");
-}
-#endif
-
-               if (length) {
-#if 0
-                       printf("Received %d bytes\n", length);
-#endif
-                       NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
-               } else {
-#if 1
-                       printf("Zero length!!!\n");
-#endif
-               }
-
-
-               ((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
-
-               rx_hold = rx_new;
-
-               rx_new = (rx_new + 1) % NUM_RX_DESC;
-       }
-
-#if 0
-       printf("Leaving inca_switch_recv()\n");
-#endif
-
-       return length;
-}
-
-
-static void inca_switch_halt(struct eth_device *dev)
-{
-#if 0
-       printf("Entered inca_switch_halt()\n");
-#endif
-
-#if 1
-       initialized = 0;
-#endif
-#if 1
-       /* Disable forwarding to the CPU port.
-        */
-       SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
-
-       /* Close RxDMA channel.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
-
-       /* Close TxDMA channel.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
-
-
-#endif
-#if 0
-       printf("Leaving inca_switch_halt()\n");
-#endif
-}
-
-
-static void inca_init_switch_chip(void)
-{
-       u32 regValue;
-
-       /* To workaround a problem with collision counter
-        * (see Errata sheet).
-        */
-       SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
-       SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
-
-#if 1
-       /* init MDIO configuration:
-        *      MDS (Poll speed):       0x01 (4ms)
-        *      PHY_LAN_ADDR:           0x06
-        *      PHY_PC_ADDR:            0x05
-        *      UEP (Use External PHY): 0x00 (Internal PHY is used)
-        *      PS (Port Select):       0x00 (PT/UMM for LAN)
-        *      PT (PHY Test):          0x00 (no test mode)
-        *      UMM (Use MDIO Mode):    0x00 (state machine is disabled)
-        */
-       SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
-
-       /* init PHY:
-        *      SL (Auto Neg. Speed for LAN)
-        *      SP (Auto Neg. Speed for PC)
-        *      LL (Link Status for LAN)
-        *      LP (Link Status for PC)
-        *      DL (Duplex Status for LAN)
-        *      DP (Duplex Status for PC)
-        *      PL (Auto Neg. Pause Status for LAN)
-        *      PP (Auto Neg. Pause Status for PC)
-        */
-       SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
-
-       /* MDIO_ACC:
-        *      RA (Request/Ack)  0x01 (Request)
-        *      RW (Read/Write)   0x01 (Write)
-        *      PHY_ADDR          0x05 (PC)
-        *      REG_ADDR          0x00 (PHY_BCR: basic control register)
-        *      PHY_DATA          0x8000
-        *                    Reset                   - software reset
-        *                    LB (loop back)          - normal
-        *                    SS (speed select)       - 10 Mbit/s
-        *                    ANE (auto neg. enable)  - enable
-        *                    PD (power down)         - normal
-        *                    ISO (isolate)           - normal
-        *                    RAN (restart auto neg.) - normal
-        *                    DM (duplex mode)        - half duplex
-        *                    CT (collision test)     - enable
-        */
-       SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
-
-       /* MDIO_ACC:
-        *      RA (Request/Ack)  0x01 (Request)
-        *      RW (Read/Write)   0x01 (Write)
-        *      PHY_ADDR          0x06 (LAN)
-        *      REG_ADDR          0x00 (PHY_BCR: basic control register)
-        *      PHY_DATA          0x8000
-        *                    Reset                   - software reset
-        *                    LB (loop back)          - normal
-        *                    SS (speed select)       - 10 Mbit/s
-        *                    ANE (auto neg. enable)  - enable
-        *                    PD (power down)         - normal
-        *                    ISO (isolate)           - normal
-        *                    RAN (restart auto neg.) - normal
-        *                    DM (duplex mode)        - half duplex
-        *                    CT (collision test)     - enable
-        */
-       SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
-
-#endif
-
-       /* Make sure the CPU port is disabled for now. We
-        * don't want packets to get stacked for us until
-        * we enable DMA and are prepared to receive them.
-        */
-       SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
-
-       SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
-
-       /* CRC GEN is enabled.
-        */
-       regValue |= 0x00000200;
-       SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
-
-       /* ADD TAG is disabled.
-        */
-       SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
-       regValue &= ~0x00000002;
-       SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
-}
-
-
-static void inca_dma_init(void)
-{
-       /* Switch off all DMA channels.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
-
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
-
-       /* Setup TX channel polling time.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
-
-       /* Setup RX channel polling time.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
-
-       /* ERRATA: write reset value into the DMA RX IMR register.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
-
-       /* Just in case: disable all transmit interrupts also.
-        */
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
-
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
-       DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
-}
-
-#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
-static int inca_amdix(void)
-{
-       u32 phyReg1 = 0;
-       u32 phyReg4 = 0;
-       u32 phyReg5 = 0;
-       u32 phyReg6 = 0;
-       u32 phyReg31 = 0;
-       u32 regEphy = 0;
-       int mdi_flag;
-       int retries;
-
-       /* Setup GPIO pins.
-        */
-       *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR    |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
-       *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
-
-#if 0
-       /* Wait for signal.
-        */
-       retries = WAIT_SIGNAL_RETRIES;
-       while (--retries) {
-               SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                               (0x1 << 31) |   /* RA           */
-                               (0x0 << 30) |   /* Read         */
-                               (0x6 << 21) |   /* LAN          */
-                               (17  << 16));   /* PHY_MCSR     */
-               do {
-                       SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
-               } while (phyReg1 & (1 << 31));
-
-               if (phyReg1 & (1 << 1)) {
-                       /* Signal detected */
-                       break;
-               }
-       }
-
-       if (!retries)
-               goto Fail;
-#endif
-
-       /* Set MDI mode.
-        */
-       *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
-       mdi_flag = 1;
-
-       /* Wait for link.
-        */
-       retries = WAIT_LINK_RETRIES;
-       while (--retries) {
-               udelay(LINK_RETRY_DELAY * 1000);
-               SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                               (0x1 << 31) |   /* RA           */
-                               (0x0 << 30) |   /* Read         */
-                               (0x6 << 21) |   /* LAN          */
-                               (1   << 16));   /* PHY_BSR      */
-               do {
-                       SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
-               } while (phyReg1 & (1 << 31));
-
-               if (phyReg1 & (1 << 2)) {
-                       /* Link is up */
-                       break;
-               } else if (mdi_flag) {
-                       /* Set MDIX mode */
-                       *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
-                       mdi_flag = 0;
-               } else {
-                       /* Set MDI mode */
-                       *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
-                       mdi_flag = 1;
-               }
-       }
-
-       if (!retries) {
-               goto Fail;
-       } else {
-               SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                               (0x1 << 31) |   /* RA           */
-                               (0x0 << 30) |   /* Read         */
-                               (0x6 << 21) |   /* LAN          */
-                               (1   << 16));   /* PHY_BSR      */
-               do {
-                       SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
-               } while (phyReg1 & (1 << 31));
-
-               /* Auto-negotiation / Parallel detection complete
-                */
-               if (phyReg1 & (1 << 5)) {
-                       SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                               (0x1 << 31) |   /* RA           */
-                               (0x0 << 30) |   /* Read         */
-                               (0x6 << 21) |   /* LAN          */
-                               (31  << 16));   /* PHY_SCSR     */
-                       do {
-                               SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
-                       } while (phyReg31 & (1 << 31));
-
-                       switch ((phyReg31 >> 2) & 0x7) {
-                       case INCA_SWITCH_PHY_SPEED_10H:
-                               /* 10Base-T Half-duplex */
-                               regEphy = 0;
-                               break;
-                       case INCA_SWITCH_PHY_SPEED_10F:
-                               /* 10Base-T Full-duplex */
-                               regEphy = INCA_IP_Switch_EPHY_DL;
-                               break;
-                       case INCA_SWITCH_PHY_SPEED_100H:
-                               /* 100Base-TX Half-duplex */
-                               regEphy = INCA_IP_Switch_EPHY_SL;
-                               break;
-                       case INCA_SWITCH_PHY_SPEED_100F:
-                               /* 100Base-TX Full-duplex */
-                               regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
-                               break;
-                       }
-
-                       /* In case of Auto-negotiation,
-                        * update the negotiated PAUSE support status
-                        */
-                       if (phyReg1 & (1 << 3)) {
-                               SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                                       (0x1 << 31) |   /* RA           */
-                                       (0x0 << 30) |   /* Read         */
-                                       (0x6 << 21) |   /* LAN          */
-                                       (6   << 16));   /* MII_EXPANSION        */
-                               do {
-                                       SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
-                               } while (phyReg6 & (1 << 31));
-
-                               /* We are Autoneg-able.
-                                * Is Link partner also able to autoneg?
-                                */
-                               if (phyReg6 & (1 << 0)) {
-                                       SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                                               (0x1 << 31) |   /* RA           */
-                                               (0x0 << 30) |   /* Read         */
-                                               (0x6 << 21) |   /* LAN          */
-                                               (4   << 16));   /* MII_ADVERTISE        */
-                                       do {
-                                               SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
-                                       } while (phyReg4 & (1 << 31));
-
-                                       /* We advertise PAUSE capab.
-                                        * Does link partner also advertise it?
-                                        */
-                                       if (phyReg4 & (1 << 10)) {
-                                               SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
-                                                       (0x1 << 31) |   /* RA           */
-                                                       (0x0 << 30) |   /* Read         */
-                                                       (0x6 << 21) |   /* LAN          */
-                                                       (5   << 16));   /* MII_LPA      */
-                                               do {
-                                                       SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
-                                               } while (phyReg5 & (1 << 31));
-
-                                               /* Link partner is PAUSE capab.
-                                                */
-                                               if (phyReg5 & (1 << 10)) {
-                                                       regEphy |= INCA_IP_Switch_EPHY_PL;
-                                               }
-                                       }
-                               }
-
-                       }
-
-                       /* Link is up */
-                       regEphy |= INCA_IP_Switch_EPHY_LL;
-
-                       SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
-               }
-       }
-
-       return 0;
-
-Fail:
-       printf("No Link on LAN port\n");
-       return -1;
-}
-#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */

diff --git a/include/common.h b/include/common.h
index baf361b3e556e1c112a04ae2ce3ea92a177b827c..5fb0bb2d3d4db5c462f0c7e961b789417ed1ca24 100644 (file)
--- a/include/common.h
+++ b/include/common.h
@@ -681,9 +681,6 @@ ulong       get_UCLK (void);
 #if defined(CONFIG_LH7A40X)
 ulong  get_PLLCLK (void);
 #endif
-#if defined CONFIG_INCA_IP
-uint   incaip_get_cpuclk (void);
-#endif
 #if defined(CONFIG_IMX)
 ulong get_systemPLLCLK(void);
 ulong get_FCLK(void);

diff --git a/include/configs/incaip.h b/include/configs/incaip.h
deleted file mode 100644 (file)
index e11d184..0000000
--- a/include/configs/incaip.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * This file contains the configuration parameters for the INCA-IP board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_INCA_IP         1       /* on a INCA-IP Board   */
-
-#define CONFIG_XWAY_SWAP_BYTES
-
-/*
- * Clock for the MIPS core (MHz)
- * allowed values: 100000000, 133000000, and 150000000 (default)
- */
-#ifndef CONFIG_CPU_CLOCK_RATE
-#define CONFIG_CPU_CLOCK_RATE  150000000
-#endif
-
-#define CONFIG_SYS_XWAY_EBU_BOOTCFG    0x40C4  /* CMULT = 8 */
-
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-
-#define CONFIG_BAUDRATE                115200
-
-#define        CONFIG_TIMESTAMP                /* Print image info with timestamp */
-
-#define CONFIG_PREBOOT "echo;" \
-       "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-       "echo"
-
-#undef CONFIG_BOOTARGS
-
-#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
-       "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
-               "nfsroot=${serverip}:${rootpath}\0"                     \
-       "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
-       "addip=setenv bootargs ${bootargs} "                            \
-               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
-               ":${hostname}:${netdev}:off\0"                          \
-       "addmisc=setenv bootargs ${bootargs} "                          \
-               "console=ttyS0,${baudrate} "                            \
-               "ethaddr=${ethaddr} "                                   \
-               "panic=1\0"                                             \
-       "flash_nfs=run nfsargs addip addmisc;"                          \
-               "bootm ${kernel_addr}\0"                                \
-       "flash_self=run ramargs addip addmisc;"                         \
-               "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
-       "net_nfs=tftp 80500000 ${bootfile};"                            \
-               "run nfsargs addip addmisc;bootm\0"                     \
-       "rootpath=/opt/eldk/mips_4KC\0"                                 \
-       "bootfile=/tftpboot/INCA/uImage\0"                              \
-       "kernel_addr=B0040000\0"                                        \
-       "ramdisk_addr=B0100000\0"                                       \
-       "u-boot=/tftpboot/INCA/u-boot.bin\0"                            \
-       "load=tftp 80500000 ${u-boot}\0"                                \
-       "update=protect off 1:0-2;era 1:0-2;"                           \
-               "cp.b 80500000 B0000000 ${filesize}\0"                  \
-       ""
-#define CONFIG_BOOTCOMMAND     "run flash_self"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SNTP
-
-
-/*
- * Miscellaneous configurable options
- */
-#define        CONFIG_SYS_LONGHELP                             /* undef to save memory      */
-#define        CONFIG_SYS_PROMPT               "INCA-IP # "    /* Monitor Command Prompt    */
-#define        CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size   */
-#define        CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
-#define        CONFIG_SYS_MAXARGS              16              /* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN          128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN      128*1024
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ     (incaip_get_cpuclk() / 2)
-
-#define CONFIG_SYS_SDRAM_BASE          0x80000000
-
-#define        CONFIG_SYS_LOAD_ADDR            0x80100000      /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START       0x80100000
-#define CONFIG_SYS_MEMTEST_END         0x80800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      (128)   /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1           0xb0000000 /* Flash Bank #1 */
-#define PHYS_FLASH_2           0xb0800000 /* Flash Bank #2 */
-
-/* The following #defines are needed to get flash environment right */
-#define        CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define        CONFIG_SYS_MONITOR_LEN          (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET      0x400000
-
-#define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define        CONFIG_ENV_IS_IN_FLASH  1
-
-/* Address and size of Primary Environment Sector      */
-#define CONFIG_ENV_ADDR                0xB0030000
-#define CONFIG_ENV_SIZE                0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS   1
-
-#define CONFIG_INCA_IP_SWITCH
-#define CONFIG_INCA_IP_SWITCH_AMDIX
-
-/*
- * JFFS2 partitions
- */
-/* No command line, one static partition, use all space on the device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV               "nor1"
-#define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET       0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT         "nor0=INCA-IP Bank 0"
-#define MTDPARTS_DEFAULT       "mtdparts=INCA-IP Bank 0:192k(uboot)," \
-                                                       "64k(env)," \
-                                                       "768k(linux)," \
-                                                       "1m@3m(rootfs)," \
-                                                       "768k(linux2)," \
-                                                       "3m@5m(rootfs2)"
-*/
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         4096
-#define CONFIG_SYS_ICACHE_SIZE         4096
-#define CONFIG_SYS_CACHELINE_SIZE      16
-
-#endif /* __CONFIG_H */

diff --git a/include/netdev.h b/include/netdev.h
index 32b5073ef025bb3e8d5e8b2bac0c3558236d0a25..e211f1841f60d7dac07d43d4dd9297a720854ac2 100644 (file)
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -54,7 +54,6 @@ int ftmac100_initialize(bd_t *bits);
 int ftmac110_initialize(bd_t *bits);
 int greth_initialize(bd_t *bis);
 void gt6426x_eth_initialize(bd_t *bis);
-int inca_switch_initialize(bd_t *bis);
 int ks8695_eth_initialize(void);
 int ks8851_mll_initialize(u8 dev_num, int base_addr);
 int lan91c96_initialize(u8 dev_num, int base_addr);