ARM: UniPhier: switch to xHCI for PH1-Pro4

PH1-Pro4 includes both EHCI and xHCI IP cores.
Unfortunately, U-Boot cannot enable EHCI and xHCI support
simultaneously.  Some users may wish Super-Speed connection.
Disable CONFIG_USB_EHCI_HCD and enable CONFIG_USB_XHCI_HCD.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
index f1fb7b761673ddf9426f36dec0712a5e0f2f4491..ace5fc50147a1a67ba0ebaafc79f1bbe24c5e397 100644 (file)
--- a/configs/ph1_pro4_defconfig
+++ b/configs/ph1_pro4_defconfig
@@ -38,5 +38,5 @@ CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
 CONFIG_SPL_NAND_DENALI=y
 CONFIG_UNIPHIER_SERIAL=y
 CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 3f738fb6420bdd14d7999d3def3619eff1da5a02..df89d14cc3a0a9f58d5e90b5f74dd39bb34bd827 100644 (file)
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -88,6 +88,8 @@
 /* #define CONFIG_SYS_ICACHE_OFF */
 /* #define CONFIG_SYS_DCACHE_OFF */
 
+#define CONFIG_SYS_CACHELINE_SIZE      32
+
 /* Comment out the following to enable L2 cache */
 #define CONFIG_UNIPHIER_L2CACHE_ON
 
@@ -186,6 +188,7 @@
 
 /* USB */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                2
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     4
 #define CONFIG_CMD_FAT
 #define CONFIG_FAT_WRITE
 #define CONFIG_DOS_PARTITION