85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled

The new is_serdes_configured covers a broader range of devices than the
PCI specific code.  Use it instead as we convert away from the
is_fsl_pci_cfg() code.

Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
index 85995cac95edc39a22c1cd5eecbcb9eb3feb29d0..186936f23e830b189e6c350433b1f02496f67847 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
+++ b/arch/powerpc/cpu/mpc8xxx/pci_cfg.c
@@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] =
 #elif defined(CONFIG_MPC8536)
 static struct pci_info pci_config_info[] =
 {
-       [LAW_TRGT_IF_PCI] = {
-               .cfg =   0,
-       },
-       [LAW_TRGT_IF_PCIE_1] = {
-               .cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
-       },
-       [LAW_TRGT_IF_PCIE_2] = {
-               .cfg =   (1 << 5) | (1 << 7),
-       },
-       [LAW_TRGT_IF_PCIE_3] = {
-               .cfg =   (1 << 7),
-       },
 };
 #elif defined(CONFIG_MPC8544)
 static struct pci_info pci_config_info[] =

diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index 1f11563f5a0a3d88a92f52049054880f0c066508..61b7454d9a8cf57fdeb8a0071807b0978c9a76bf 100644 (file)
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -28,15 +28,7 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-       SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-       SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
        SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
-       SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-       SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
-       SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-       SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-       SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
        SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
        SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };

diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 253ed181fcfbe0fe7f612f754f4d47e056dac732..8daa0c359a637a708a2e8b9f994fb4a8b4b4295c 100644 (file)
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -30,6 +30,7 @@
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
+#include <asm/fsl_serdes.h>
 #include <spd.h>
 #include <miiphy.h>
 #include <libfdt.h>
@@ -219,9 +220,13 @@ void pci_init_board(void)
 
        puts("\n");
 #ifdef CONFIG_PCIE3
-       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+       pcie_configured = is_serdes_configured(PCIE3);
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+               set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
+                               LAW_TRGT_IF_PCIE_3);
+               set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCIE_3);
                SET_STD_PCIE_INFO(pci_info[num], 3);
                pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
                printf ("    PCIE3 connected to Slot3 as %s (base address %lx)\n",
@@ -239,9 +244,13 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE1
-       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+       pcie_configured = is_serdes_configured(PCIE1);
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+               set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
+                               LAW_TRGT_IF_PCIE_1);
+               set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCIE_1);
                SET_STD_PCIE_INFO(pci_info[num], 1);
                pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
                printf ("    PCIE1 connected to Slot1 as %s (base address %lx)\n",
@@ -259,9 +268,13 @@ void pci_init_board(void)
 #endif
 
 #ifdef CONFIG_PCIE2
-       pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+       pcie_configured = is_serdes_configured(PCIE2);
 
        if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+               set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
+                               LAW_TRGT_IF_PCIE_2);
+               set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCIE_2);
                SET_STD_PCIE_INFO(pci_info[num], 2);
                pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
                printf ("    PCIE2 connected to Slot 2 as %s (base address %lx)\n",
@@ -285,6 +298,10 @@ void pci_init_board(void)
        pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+               set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
+                               LAW_TRGT_IF_PCI);
+               set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
+                               LAW_TRGT_IF_PCI);
                SET_STD_PCI_INFO(pci_info[num], 1);
                pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
                printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
@@ -540,15 +557,23 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_PCI1
        ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#else
+       ft_fsl_pci_setup(blob, "pci0", NULL);
 #endif
 #ifdef CONFIG_PCIE2
        ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#else
+       ft_fsl_pci_setup(blob, "pci1", NULL);
 #endif
 #ifdef CONFIG_PCIE2
        ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#else
+       ft_fsl_pci_setup(blob, "pci2", NULL);
 #endif
 #ifdef CONFIG_PCIE1
        ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
+#else
+       ft_fsl_pci_setup(blob, "pci3", NULL);
 #endif
 #ifdef CONFIG_FSL_SGMII_RISER
        fsl_sgmii_riser_fdt_fixup(blob);