drivers/ddr/fsl: Fix timing_cfg_2 register

Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but
with wrong bit position. It is bit 13 in big-endian, or left shift
18 from LSB. This error hasn't had any impact because we don't have
fast enough DDR4 using the extra bit so far.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index b26269c14d59d1bd4f5744d05c411c572fbcba6e..1d5cec662ce1c94f4af5ca9282aa457e3ace1473 100644 (file)
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
                | ((add_lat_mclk & 0xf) << 28)
                | ((cpo & 0x1f) << 23)
                | ((wr_lat & 0xf) << 19)
-               | ((wr_lat & 0x10) << 14)
+               | ((wr_lat & 0x10) << 18)
                | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
                | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
                | ((cke_pls & 0x7) << 6)