writel(0x00000307, &mctl_com->mbagcr[5]);
}
-static bool mctl_mem_matches(u32 offset)
-{
- const int match_count = 64;
- int i, matches = 0;
-
- for (i = 0; i < match_count; i++) {
- if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
- readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
- matches++;
- }
-
- return matches == match_count;
-}
-
unsigned long sunxi_dram_init(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
/* Detect and set page size */
+ mctl_mem_fill();
for (columns = 7; columns < 20; columns++) {
if (mctl_mem_matches(1 << columns))
break;
#include <asm/arch/dram_sun4i.h>
#endif
+#define MCTL_MEM_FILL_MATCH_COUNT 64
+
unsigned long sunxi_dram_init(void);
/*
}
}
+/*
+ * Fill beginning of DRAM with "random" data for mctl_mem_matches()
+ */
+static inline void mctl_mem_fill(void)
+{
+ int i;
+
+ for (i = 0; i < MCTL_MEM_FILL_MATCH_COUNT; i++)
+ writel(0xaa55aa55 + i, CONFIG_SYS_SDRAM_BASE + i * 4);
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+static inline bool mctl_mem_matches(u32 offset)
+{
+ int i, matches = 0;
+
+ for (i = 0; i < MCTL_MEM_FILL_MATCH_COUNT; i++) {
+ if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
+ readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
+ matches++;
+ }
+
+ return matches == MCTL_MEM_FILL_MATCH_COUNT;
+}
+
#endif /* _SUNXI_DRAM_H */