# define LSR_ORER 1
# define FIFOLEVEL_MASK 0xFF
#elif defined(CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7722)
# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
#define CACHE_OC_NUM_ENTRIES 512
#define CACHE_OC_ENTRY_SHIFT 5
-#if defined (CONFIG_CPU_SH7750)
-#include <asm/cpu_sh7750.h>
+#if defined (CONFIG_CPU_SH7750) || \
+ defined(CONFIG_CPU_SH7751)
+# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
-#include <asm/cpu_sh7722.h>
+# include <asm/cpu_sh7722.h>
#elif defined (CONFIG_CPU_SH7780)
-#include <asm/cpu_sh7780.h>
+# include <asm/cpu_sh7780.h>
#else
-#error "Unknown SH4 variant"
+# error "Unknown SH4 variant"
#endif
#endif /* _ASM_CPU_SH4_H_ */
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
-#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
+#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
-#define CCR_CACHE_INIT 0x0000090b
+#define CCR_CACHE_INIT 0x0000090B
#endif
/* OCN */