MIPS: Malta: Enable CM & L2 support

Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 76714379a4cec17302adfec8ad82cfbd092c1bc0..f113b91de70857163bba8f5e8887f523162c28f7 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -26,6 +26,8 @@ config TARGET_MALTA
        select DM
        select DM_SERIAL
        select DYNAMIC_IO_PORT_BASE
+       select MIPS_CM
+       select MIPS_L2_CACHE
        select OF_CONTROL
        select OF_ISA_BUS
        select SUPPORTS_BIG_ENDIAN

diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 3d48cdc1f4714ec05805c49a857197b51bc3a214..6df4d9f719bbfb6b6ef2dd7c34f0be43602af97b 100644 (file)
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -28,12 +28,6 @@
 
        .globl  lowlevel_init
 lowlevel_init:
-       /* disable any L2 cache for now */
-       sync
-       mfc0    t0, CP0_CONFIG, 2
-       ori     t0, t0, 0x1 << 12
-       mtc0    t0, CP0_CONFIG, 2
-
        /* detect the core card */
        PTR_LI  t0, CKSEG1ADDR(MALTA_REVISION)
        lw      t0, 0(t0)