]> git.sur5r.net Git - u-boot/commitdiff
Fix ULI RTC support on MPC8544 DS
authorKumar Gala <galak@kernel.crashing.org>
Thu, 30 Aug 2007 21:18:18 +0000 (16:18 -0500)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 4 Sep 2007 21:00:48 +0000 (16:00 -0500)
The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC.  We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.

The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/freescale/mpc8544ds/init.S
board/freescale/mpc8544ds/mpc8544ds.c
include/configs/MPC8544DS.h

index 900c3680c71dbb55bdda8a73acf66274123f17ee..68ccba746ba9a08c7c9ec2b6e3dbe341289698dd 100644 (file)
@@ -237,6 +237,6 @@ law_entry:
 
        /* contains both PCIE3 MEM & IO space */
        .long   (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_2M)
+       .long   LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
        entry_end
index 4c3b27f23898fe0cd8fd98e63854c7ad9e1eba34..76d909191f9605a088beabbdae79a49862b79507 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <asm/immap_fsl_pci.h>
+#include <asm/io.h>
 #include <spd.h>
 #include <miiphy.h>
 
@@ -222,6 +223,11 @@ pci_init_board(void)
                printf ("    PCIE3 on bus %02x - %02x\n",
                        hose->first_busno,hose->last_busno);
 
+               /*
+                * Activate ULI1575 legacy chip by performing a fake
+                * memory access.  Needed to make ULI RTC work.
+                */
+               in_be32(CFG_PCIE3_MEM_BASE);
        } else {
                printf ("    PCIE3: disabled\n");
        }
index 9743f031e0b495648dc8ea58c31d9164bae147f0..f580ccadee5ea515ff5b911c348da1529834eca6 100644 (file)
@@ -310,6 +310,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CFG_PCIE3_IO_BASE      0x00000000
 #define CFG_PCIE3_IO_PHYS      0xb0100000      /* reuse mem LAW */
 #define CFG_PCIE3_IO_SIZE      0x00100000      /* 1M */
+#define CFG_PCIE3_MEM_BASE2    0xb0200000
+#define CFG_PCIE3_MEM_PHYS2    CFG_PCIE3_MEM_BASE2
+#define CFG_PCIE3_MEM_SIZE2    0x00200000      /* 1M */
 
 #if defined(CONFIG_PCI)