]> git.sur5r.net Git - u-boot/commitdiff
powerpc/85xx: Add P1023RDB board support
authorChunhe Lan <Chunhe.Lan@freescale.com>
Fri, 14 Jun 2013 08:21:48 +0000 (16:21 +0800)
committerAndy Fleming <afleming@freescale.com>
Thu, 20 Jun 2013 22:08:53 +0000 (17:08 -0500)
P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/Makefile
board/freescale/p1023rdb/Makefile [new file with mode: 0644]
board/freescale/p1023rdb/ddr.c [new file with mode: 0644]
board/freescale/p1023rdb/law.c [new file with mode: 0644]
board/freescale/p1023rdb/p1023rdb.c [new file with mode: 0644]
board/freescale/p1023rdb/tlb.c [new file with mode: 0644]
boards.cfg
include/configs/P1023RDB.h [new file with mode: 0644]

index 2318064a4786fbb31a408dba45c2ebd651f554ce..4669883a3caf54bd89cd5b089e3b055e39e3265c 100644 (file)
@@ -73,6 +73,7 @@ COBJS-$(CONFIG_P1014) += ddr-gen3.o
 COBJS-$(CONFIG_P1020)  += ddr-gen3.o
 COBJS-$(CONFIG_P1021)  += ddr-gen3.o
 COBJS-$(CONFIG_P1022)  += ddr-gen3.o
+COBJS-$(CONFIG_P1023)  += ddr-gen3.o
 COBJS-$(CONFIG_P1024)  += ddr-gen3.o
 COBJS-$(CONFIG_P1025)  += ddr-gen3.o
 COBJS-$(CONFIG_P2010)  += ddr-gen3.o
diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile
new file mode 100644 (file)
index 0000000..45c4f8b
--- /dev/null
@@ -0,0 +1,33 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS-y        += $(BOARD).o
+COBJS-y        += ddr.o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
new file mode 100644 (file)
index 0000000..7ed275a
--- /dev/null
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* CONFIG_SYS_DDR_RAW_TIMING */
+/*
+ * Hynix H5TQ1G83TFR-H9C
+ */
+dimm_params_t ddr_raw_timing = {
+       .n_ranks = 1,
+       .rank_density = 536870912u,
+       .capacity = 536870912u,
+       .primary_sdram_width = 32,
+       .ec_sdram_width = 0,
+       .registered_dimm = 0,
+       .mirrored_dimm = 0,
+       .n_row_addr = 14,
+       .n_col_addr = 10,
+       .n_banks_per_sdram_device = 8,
+       .edc_config = 0,
+       .burst_lengths_bitmask = 0x0c,
+
+       .tCKmin_X_ps = 1875,
+       .caslat_X = 0x1e << 4,  /* 5,6,7,8 */
+       .tAA_ps = 13125,
+       .tWR_ps = 18000,
+       .tRCD_ps = 13125,
+       .tRRD_ps = 7500,
+       .tRP_ps = 13125,
+       .tRAS_ps = 37500,
+       .tRC_ps = 50625,
+       .tRFC_ps = 160000,
+       .tWTR_ps = 7500,
+       .tRTP_ps = 7500,
+       .refresh_rate_ps = 7800000,
+       .tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+               unsigned int controller_number,
+               unsigned int dimm_number)
+{
+       const char dimm_model[] = "Fixed DDR on board";
+
+       if ((controller_number == 0) && (dimm_number == 0)) {
+               memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+               memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+               memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+       }
+
+       return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       int i;
+       popts->clk_adjust = 6;
+       popts->cpo_override = 0x1f;
+       popts->write_data_delay = 2;
+       popts->half_strength_driver_enable = 1;
+       /* Write leveling override */
+       popts->wrlvl_en = 1;
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0xf;
+       popts->wrlvl_start = 0x8;
+       popts->trwt_override = 1;
+       popts->trwt = 0;
+
+       for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+               popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+               popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+       }
+}
+
diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c
new file mode 100644 (file)
index 0000000..331662c
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+       SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+       SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
+               LAW_TRGT_IF_DPAA_SWP_SRAM),
+       SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
new file mode 100644 (file)
index 0000000..918398b
--- /dev/null
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *           Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cache.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_portals.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+       fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+       /* Set ABSWP to implement conversion of addresses in the LBC */
+       setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       printf("Board: P1023 RDB\n");
+
+       return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+       fsl_pcie_init_board(0);
+}
+#endif
+
+int board_early_init_r(void)
+{
+       const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+       const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+       /*
+        * Remap Boot flash + PROMJET region to caching-inhibited
+        * so that flash can be erased properly.
+        */
+
+       /* Flush d-cache and invalidate i-cache of any FLASH data */
+       flush_dcache();
+       invalidate_icache();
+
+       /* invalidate existing TLB entry for flash + promjet */
+       disable_tlb(flash_esel);
+
+       set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+               MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+               0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+       setup_portals();
+
+       return 0;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+       return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+       return gd->mem_clk;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+       struct fsl_pq_mdio_info dtsec_mdio_info;
+
+       /*
+        * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
+        * is not correct.
+        */
+       setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
+
+       dtsec_mdio_info.regs =
+               (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+       dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+       /* Register the 1G MDIO bus */
+       fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+       fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
+       fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
+
+       fm_info_set_mdio(FM1_DTSEC1,
+                        miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+       fm_info_set_mdio(FM1_DTSEC2,
+                        miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+#ifdef CONFIG_FMAN_ENET
+       cpu_eth_init(bis);
+#endif
+
+       return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+       fdt_fixup_dr_usb(blob, bd);
+#endif
+
+       fdt_fixup_fman_ethernet(blob);
+}
+#endif
diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c
new file mode 100644 (file)
index 0000000..3417c0f
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+       /* TLB 0 - for temp stack in cache */
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 0, BOOKE_PAGESZ_4K, 0),
+
+       /* TLB 1 */
+       /* *I*** - Covers boot page */
+       SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                     0, 0, BOOKE_PAGESZ_4K, 1),
+
+       /* *I*G* - CCSRBAR */
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 1, BOOKE_PAGESZ_4M, 1),
+
+       /* W**G* - Flash, localbus */
+       /* This will be changed to *I*G* after relocation to RAM. */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+                     0, 2, BOOKE_PAGESZ_256M, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 3, BOOKE_PAGESZ_1G, 1),
+
+       /* *I*G* - PCI */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+                     CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 4, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+                     CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 5, BOOKE_PAGESZ_256M, 1),
+
+       /* *I*G* - PCI I/O */
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 6, BOOKE_PAGESZ_256K, 1),
+
+       /* Bman/Qman */
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+                     MAS3_SW|MAS3_SR, 0,
+                     0, 7, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
+                     CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 8, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_M,
+                     0, 9, BOOKE_PAGESZ_1M, 1),
+       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
+                     CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_1M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                     MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 11, BOOKE_PAGESZ_16K, 1),
+
+#ifdef CONFIG_SYS_RAMBOOT
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
+                     CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 12, BOOKE_PAGESZ_256M, 1),
+
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+                     CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                     0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 4993220b5705516f917ffab1438e1eb983f0880d..c0c428262b2f1d8f57f46cf63724d041f6a4958d 100644 (file)
@@ -831,6 +831,7 @@ P1022DS_36BIT_SPIFLASH       powerpc     mpc85xx     p1022ds             freesca
 P1022DS_SDCARD               powerpc     mpc85xx     p1022ds             freescale     -           P1022DS:SDCARD
 P1022DS_36BIT_SDCARD         powerpc     mpc85xx     p1022ds             freescale     -           P1022DS:36BIT,SDCARD
 P1022DS_36BIT                powerpc     mpc85xx     p1022ds             freescale      -           P1022DS:36BIT
+P1023RDB                     powerpc     mpc85xx     p1023rdb            freescale      -           P1023RDB
 P1023RDS                     powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS
 P1023RDS_NAND                powerpc     mpc85xx     p1023rds            freescale      -           P1023RDS:NAND
 P1024RDB                     powerpc     mpc85xx     p1_p2_rdb_pc        freescale      -           p1_p2_rdb_pc:P1024RDB
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
new file mode 100644 (file)
index 0000000..fee8040
--- /dev/null
@@ -0,0 +1,401 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *          Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE   0xeff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE           /* BOOKE */
+#define CONFIG_E500            /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_P1023
+#define CONFIG_MP              /* support multiple processors */
+
+#define CONFIG_FSL_ELBC                /* Has Enhanced localbus controller */
+#define CONFIG_PCI             /* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
+#define CONFIG_PCIE1           /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2           /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3           /* PCIE controler 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET  /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ    66666666
+#define CONFIG_DDR_CLK_FREQ    CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                        /* toggle L2 cache */
+#define CONFIG_BTB                     /* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START       0x01000000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END         0x02000000
+
+#define CONFIG_PANIC_HANG      /* do not reset board on panic */
+
+/* Implement conversion of addresses in the LBC */
+#define CONFIG_SYS_LBC_LBCR            0x00000000
+#define CONFIG_SYS_LBC_LCRR            LCRR_CLKDIV_8
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define CONFIG_CHIP_SELECTS_PER_CTRL   1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SDRAM_SIZE          512u    /* DDR is 512M */
+#define CONFIG_SYS_SPD_BUS_NUM          0
+#define SPD_EEPROM_ADDRESS              0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff     DDR                     512M cacheable
+ * 0x8000_0000 0xbfff_ffff     PCI Express Mem         1G non-cacheable
+ * 0xc000_0000 0xdfff_ffff     PCI                     512M non-cacheable
+ * 0xe100_0000 0xe3ff_ffff     PCI IO range            4M non-cacheable
+ * 0xff00_0000 0xff3f_ffff     DPAA_QBMAN              4M cacheable
+ * 0xff60_0000 0xff7f_ffff     CCSR                    2M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff     L1 for stack            16K cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000 0xefff_ffff     NOR flash               64M non-cacheable
+ * 0xffa0_0000 0xffaf_ffff     NAND                    1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE          0xec000000 /* start of FLASH 64M */
+#define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+                               | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      512     /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
+
+#define CONFIG_BOARD_EARLY_INIT_F      /* call board_early_init_f function */
+#define CONFIG_BOARD_EARLY_INIT_R      /* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR       0xffd00000      /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
+                                       GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)      /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN  (6 * 1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE           0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS      CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_PS_8               /* Port Size = 8bit */ \
+                               | BR_MS_FCM             /* MSEL = FCM */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB                /* length 256K */ \
+                               | OR_FCM_PGS \
+                               | OR_FCM_CSCT \
+                               | OR_FCM_CST \
+                               | OR_FCM_CHT \
+                               | OR_FCM_SCY_1 \
+                               | OR_FCM_TRLX \
+                               | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX              1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED   400000  /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_OFFSET          0x3000
+#define CONFIG_SYS_I2C2_OFFSET         0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
+#define CONFIG_SYS_EEPROM_BUS_NUM              0
+
+#define CONFIG_CMD_I2C
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME          "Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT      0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT       0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME          "Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME          "Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000           /* Defind e1000 pci Ethernet card */
+#define CONFIG_PCI_PNP         /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR                0xfff80000
+#else
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO              /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE   /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING         /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ  1000            /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ   (64 << 20)   /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)   /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE                "uImage"
+#define CONFIG_UBOOTPATH       (u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR                1000000
+
+#define CONFIG_BOOTDELAY -1    /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE        115200
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN          /* support Q/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE       0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE       0x00200000
+#define CONFIG_SYS_BMAN_MEM_BASE       0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE       0x00200000
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR     0xeff40000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
+#define CONFIG_SYS_FDT_PAD             (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2
+
+#define CONFIG_SYS_TBIPA_VALUE 8
+#define CONFIG_MII             /* MII PHY management */
+#define CONFIG_ETHPRIME                "FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS      \
+       "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#endif /* __CONFIG_H */