]> git.sur5r.net Git - u-boot/commitdiff
stm32f7: stm32f746-disco: read memory info from device tree
authorVikas Manocha <vikas.manocha@st.com>
Mon, 10 Apr 2017 22:03:01 +0000 (15:03 -0700)
committerTom Rini <trini@konsulko.com>
Mon, 8 May 2017 15:57:21 +0000 (11:57 -0400)
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>

board/st/stm32f746-disco/stm32f746-disco.c
drivers/ram/stm32_sdram.c
include/configs/stm32f746-disco.h

index 52c1900ee3402da09ee99ac45b86231ecc90567e..dc3a9dcade000c21bc7e35be3d80f393d2756820 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size)
+{
+       int mr_node;
+
+       mr_node = fdt_path_offset(gd->fdt_blob, "/memory");
+       if (mr_node < 0)
+               return mr_node;
+       *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node,
+                                                     "reg", 0, mr_size, false);
+       debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size);
+
+       return 0;
+}
 int dram_init(void)
 {
        struct udevice *dev;
-       struct ram_info ram;
        int rv;
+       fdt_addr_t mr_base, mr_size;
 
        rv = uclass_get_device(UCLASS_RAM, 0, &dev);
        if (rv) {
                debug("DRAM init failed: %d\n", rv);
                return rv;
        }
-       rv = ram_get_info(dev, &ram);
-       if (rv) {
-               debug("Cannot get DRAM size: %d\n", rv);
+
+       rv = get_memory_base_size(&mr_base, &mr_size);
+       if (rv)
                return rv;
-       }
-       debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size);
-       gd->ram_size = ram.size;
+       gd->ram_size = mr_size;
+       gd->ram_top = mr_base;
 
+       return rv;
+}
+
+int dram_init_banksize(void)
+{
+       fdt_addr_t mr_base, mr_size;
+       get_memory_base_size(&mr_base, &mr_size);
        /*
         * Fill in global info with description of SRAM configuration
         */
-       gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
-       gd->bd->bi_dram[0].size  = ram.size;
+       gd->bd->bi_dram[0].start = mr_base;
+       gd->bd->bi_dram[0].size  = mr_size;
 
-       return rv;
+       return 0;
 }
 
 #ifdef CONFIG_ETH_DESIGNWARE
@@ -111,7 +130,6 @@ int board_late_init(void)
 
 int board_init(void)
 {
-       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
+       gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
        return 0;
 }
index eb1ab945b509cbcf9f0e6bfc897b9cdc62fadfbb..5e09f35b9199b7e4ae700682a6ef6cdc4238fa9d 100644 (file)
@@ -179,7 +179,6 @@ static int stm32_fmc_probe(struct udevice *dev)
 
 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 {
-       info->size = CONFIG_SYS_RAM_SIZE;
        return 0;
 }
 
index 48ac4413e026c2a8bff90818c37dea54ee22cfb0..349ee3af89ee10f78f574576cc7471fd2090a142 100644 (file)
  * Configuration of the external SDRAM memory
  */
 #define CONFIG_NR_DRAM_BANKS           1
-#define CONFIG_SYS_RAM_SIZE            (8 * 1024 * 1024)
-#define CONFIG_SYS_RAM_CS              1
-#define CONFIG_SYS_RAM_FREQ_DIV                2
-#define CONFIG_SYS_RAM_BASE            0xC0000000
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_RAM_BASE
+#define CONFIG_SYS_RAM_FREQ_DIV         2
 #define CONFIG_SYS_LOAD_ADDR           0xC0400000
 #define CONFIG_LOADADDR                        0xC0400000