#define FSL_CORENET_RCWSR13_EC2                        0x0c000000
 #define FSL_CORENET_RCWSR13_EC2_RGMII          0x08000000
 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET    0x28
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET    0xd00
 #define PXCKEN_MASK                            0x80000000
 #define PXCK_MASK                              0x00FF0000
 #define PXCK_BITS_START                                16
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR        \
        (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
+       (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \
 
 #endif
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        board_mux_lane_to_slot();
+
+       /* Increase IO drive strength to address FCS error on RGMII */
+       out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
+
        return 0;
 }