#
# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
+# see the file Documentation/kbuild/kconfig-language.txt in the
+# Linux kernel source tree.
#
mainmenu "U-Boot $UBOOTVERSION Configuration"
string "Local version - append to U-Boot release"
help
Append an extra string to the end of your U-Boot version.
- This will show up on your boot log, for example.
+ This will show up in your boot log, for example.
The string you set here will be appended after the contents of
any files with a filename matching localversion* in your
object and source tree, in that order. Your total string can
default y
help
This will try to automatically determine if the current tree is a
- release tree by looking for git tags that belong to the current
+ release tree by looking for Git tags that belong to the current
top of tree revision.
A string of the format -gxxxxxxxx will be added to the localversion
- if a git-based tree is found. The string generated by this will be
+ if a Git-based tree is found. The string generated by this will be
appended after any matching localversion* files, and after the value
set in CONFIG_LOCALVERSION.
bool "Enable malloc() pool before relocation"
default y if DM
help
- Before relocation memory is very limited on many platforms. Still,
+ Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
depends on SYS_MALLOC_F
default 0x400
help
- Before relocation memory is very limited on many platforms. Still,
+ Before relocation, memory is very limited on many platforms. Still,
we can provide a small malloc() pool if needed. Driver model in
particular needs this to operate, so that it can allocate the
initial serial device and any others that are needed.
This option allows certain base U-Boot options and settings
to be disabled or tweaked. This is for specialized
environments which can tolerate a "non-standard" U-Boot.
- Only use this if you really know what you are doing.
+ Use this only if you really know what you are doing.
if EXPERT
config SYS_MALLOC_CLEAR_ON_INIT
Then the boot time can be significantly reduced.
Warning:
When disabling this, please check if malloc calls, maybe
- should be replaced by calloc - if expects zeroed memory.
+ should be replaced by calloc - if one expects zeroed memory.
endif
endmenu # General setup
config SPL_SYS_MALLOC_SIMPLE
bool
depends on SPL
- prompt "Only use malloc_simple functions in the spl"
+ prompt "Only use malloc_simple functions in the SPL"
help
Say Y here to only use the *_simple malloc functions from
- malloc_simple.c, rather then using the versions from dlmalloc.c
+ malloc_simple.c, rather then using the versions from dlmalloc.c;
this will make the SPL binary smaller at the cost of more heap
usage as the *_simple malloc functions do not re-use free-ed mem.
VERSION = 2016
PATCHLEVEL = 05
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
void flush_dcache_all(void)
{
-#ifdef CONFIG_ISA_ARCV2
- if (!ioc_exists)
-#endif
- __dc_entire_op(OP_FLUSH);
+ __dc_entire_op(OP_FLUSH);
#ifdef CONFIG_ISA_ARCV2
- if (slc_exists && !ioc_exists)
+ if (slc_exists)
__slc_entire_op(OP_FLUSH);
#endif
}
WEAK(lowlevel_init)
mov x29, lr /* Save LR */
-#ifndef CONFIG_ARMV8_MULTIENTRY
-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
- /*
- * For single-entry systems the lowlevel init is very simple.
- */
- ldr x0, =GICD_BASE
- bl gic_init_secure
-#endif
-#else /* CONFIG_ARMV8_MULTIENTRY is set */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
ldr x0, =GICD_BASE
ldr x1, =GICC_BASE
bl gic_init_secure_percpu
-#endif
#endif
branch_if_master x0, x1, 2f
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mmc3 {
vmmc-supply = <&dcdc4>;
bus-width = <4>;
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&usb2_phy1 {
vmmc_aux-supply = <&vdd_3v3>;
pbias-supply = <&pbias_mmc_reg>;
bus-width = <4>;
- cd-gpios = <&gpio6 27 0>; /* gpio 219 */
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&mmc2 {
status = "okay";
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is always hardwired.
+ */
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
};
&mmc2 {
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
- cd-gpios = <&gpio6 27 0>;
+ cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
};
&mmc2 {
};
aliases {
- /* this allow the ethaddr uboot environmnet variable contents
+ /* this allow the ethaddr uboot environment variable contents
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
};
aliases {
- /* this allow the ethaddr uboot environmnet variable contents
+ /* this allow the ethaddr uboot environment variable contents
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
};
aliases {
+ /*
+ * This allows the ethaddr uboot environment variable
+ * contents to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
udc0 = &usb1;
};
aliases {
/*
- * This allows the ethaddr uboot environmnet variable
+ * This allows the ethaddr uboot environment variable
* contents to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
#define BOOT_DEVICE_MMC1 0x07
#define BOOT_DEVICE_MMC2 0x08
#define BOOT_DEVICE_SPI 0x0A
+#define BOOT_DEVICE_USB 0x0D
#define BOOT_DEVICE_UART 0x41
-#define BOOT_DEVICE_USB 0x45
+#define BOOT_DEVICE_USBETH 0x45
#define BOOT_DEVICE_CPGMAC 0x47
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ /* run low-level CPU init code (from flash) */
+ move.l #cpu_init_f, %a1
+ jsr (%a1)
+ /* run low-level board init code (from flash) */
+ move.l #board_init_f, %a1
+ jsr (%a1)
/* board_init_f() does not return */
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ /* run low-level CPU init code (from flash) */
+ move.l #cpu_init_f, %a1
+ jsr (%a1)
+ /* run low-level board init code (from flash) */
+ move.l #board_init_f, %a1
+ jsr (%a1)
/* board_init_f() does not return */
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ /* run low-level CPU init code (from flash) */
+ move.l #cpu_init_f, %a1
+ jsr (%a1)
+ /* run low-level board init code (from flash) */
+ move.l #board_init_f, %a1
+ jsr (%a1)
/* board_init_f() does not return */
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ /* run low-level CPU init code (from flash) */
+ move.l #cpu_init_f, %a1
+ jsr (%a1)
+ /* run low-level board init code (from flash) */
+ move.l #board_init_f, %a1
+ jsr (%a1)
/* board_init_f() does not return */
#include <image.h>
#include <fdt_support.h>
#include <asm/addrspace.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
}
-int arch_fixup_memory_node(void *blob)
+int arch_fixup_fdt(void *blob)
{
#if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT)
- u64 mem_start = 0;
+ u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart);
u64 mem_size = gd->ram_size;
return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1);
config SYS_BOARD
default "sandbox"
+config SYS_CPU
+ default "sandbox"
+
config SYS_CONFIG_NAME
default "sandbox"
obj-y += car.o dram.o
endif
obj-y += cpu.o fw_cfg.o qemu.o
-ifndef CONFIG_QEMU_ACPI_TABLE
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
-endif
+++ /dev/null
-/*
- * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/acpi_table.h>
-#include <asm/ioapic.h>
-#include <asm/tables.h>
-
-void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
- void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
- u16 pmbase;
-
- pci_dev_t bdf = PCI_BDF(0, 0x1f, 0);
- pci_read_config_word(bdf, 0x40, &pmbase);
-
- /*
- * TODO(saket.sinha89@gmail.com): wrong value
- * of pmbase by above function. Hard-coding it to
- * correct value. Since no PCI register is
- * programmed Power Management Interface is
- * not working
- */
- pmbase = 0x0600;
-
- memset((void *)fadt, 0, sizeof(struct acpi_fadt));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(struct acpi_fadt);
- header->revision = 3;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 0;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 0x00;
- fadt->preferred_pm_profile = PM_MOBILE;
- fadt->sci_int = 0x9;
- fadt->smi_cmd = 0;
- fadt->acpi_enable = 0;
- fadt->acpi_disable = 0;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0;
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = pmbase + 0x50;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x20;
- fadt->gpe1_blk = 0;
- fadt->pm1_evt_len = 4;
- /*
- * Upper word is reserved and
- * Linux complains about 32 bit
- */
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 1;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 16;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0;
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 0x39;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x32;
- fadt->iapc_boot_arch = 0x00;
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
- ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER |
- ACPI_FADT_PLATFORM_CLOCK;
- fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0;
- fadt->reset_value = 0x06;
- /*
- * Set X_FIRMWARE_CTRL only if FACS is
- * above 4GB. If X_FIRMWARE_CTRL is set,
- * then FIRMWARE_CTRL must be zero
- */
- fadt->x_firmware_ctl_l = 0;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
- fadt->x_pm1b_evt_blk.space_id = 0;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
- fadt->x_pm1a_cnt_blk.space_id = 1;
- /*
- * Upper word is reserved and
- * Linux complains about 32 bit
- */
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
- fadt->x_pm1b_cnt_blk.space_id = 0;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 128;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pmbase + 0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
- fadt->x_gpe1_blk.space_id = 0;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = table_compute_checksum((void *)fadt, header->length);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /*
- * TODO(saket.sinha89@gmail.com): get these
- * IRQ values from device tree
- */
- current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
- 2, IO_APIC_ADDR, 0);
- current += acpi_create_madt_irqoverride(
- (struct acpi_madt_irqoverride *)current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride(
- (struct acpi_madt_irqoverride *)current, 0, 9, 9, 0xd);
- current += acpi_create_madt_irqoverride(
- (struct acpi_madt_irqoverride *)current, 0, 0xd, 0xd, 0xd);
- acpi_create_madt_lapic_nmi(
- (struct acpi_madt_lapic_nmi *)current, 0, 0, 0);
-
- return current;
-}
+++ /dev/null
-/* CPU hotplug */
-
-Scope(\_SB) {
- /* Objects filled in by run-time generated SSDT */
- External(NTFY, MethodObj)
- External(CPON, PkgObj)
-
- /* Methods called by run-time generated SSDT Processor objects */
- Method(CPMA, 1, NotSerialized) {
- /*
- * _MAT method - create an madt apic buffer
- * Arg0 = Processor ID = Local APIC ID
- * Local0 = CPON flag for this cpu
- */
- Store(DerefOf(Index(CPON, Arg0)), Local0)
- /* Local1 = Buffer (in madt apic form) to return */
- Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
- /* Update the processor id, lapic id, and enable/disable status */
- Store(Arg0, Index(Local1, 2))
- Store(Arg0, Index(Local1, 3))
- Store(Local0, Index(Local1, 4))
- Return (Local1)
- }
- Method(CPST, 1, NotSerialized) {
- /*
- * _STA method - return ON status of cpu
- * Arg0 = Processor ID = Local APIC ID
- * Local0 = CPON flag for this cpu
- */
- Store(DerefOf(Index(CPON, Arg0)), Local0)
- If (Local0) {
- Return (0xf)
- } Else {
- Return (0x0)
- }
- }
- Method(CPEJ, 2, NotSerialized) {
- /* _EJ0 method - eject callback */
- Sleep(200)
- }
-
- /* CPU hotplug notify method */
- OperationRegion(PRST, SystemIO, 0xaf00, 32)
- Field(PRST, ByteAcc, NoLock, Preserve) {
- PRS, 256
- }
- Method(PRSC, 0) {
- /* Local5 = active cpu bitmap */
- Store(PRS, Local5)
- /* Local2 = last read byte from bitmap */
- Store(Zero, Local2)
- /* Local0 = Processor ID / APIC ID iterator */
- Store(Zero, Local0)
- While (LLess(Local0, SizeOf(CPON))) {
- /* Local1 = CPON flag for this cpu */
- Store(DerefOf(Index(CPON, Local0)), Local1)
- If (And(Local0, 0x07)) {
- /* Shift down previously read bitmap byte */
- ShiftRight(Local2, 1, Local2)
- } Else {
- /* Read next byte from cpu bitmap */
- Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
- }
- /* Local3 = active state for this cpu */
- Store(And(Local2, 1), Local3)
-
- If (LNotEqual(Local1, Local3)) {
- /* State change - update CPON with new state */
- Store(Local3, Index(CPON, Local0))
- /* Do CPU notify */
- If (LEqual(Local3, 1)) {
- NTFY(Local0, 1)
- } Else {
- NTFY(Local0, 3)
- }
- }
- Increment(Local0)
- }
- }
-}
+++ /dev/null
-/* Debugging */
-
-Scope(\) {
- /* Debug Output */
- OperationRegion(DBG, SystemIO, 0x0402, 0x01)
- Field(DBG, ByteAcc, NoLock, Preserve) {
- DBGB, 8,
- }
- /*
- * Debug method - use this method to send output to the QEMU
- * BIOS debug port. This method handles strings, integers,
- * and buffers. For example: DBUG("abc") DBUG(0x123)
- */
- Method(DBUG, 1) {
- ToHexString(Arg0, Local0)
- ToBuffer(Local0, Local0)
- Subtract(SizeOf(Local0), 1, Local1)
- Store(Zero, Local2)
- While (LLess(Local2, Local1)) {
- Store(DerefOf(Index(Local0, Local2)), DBGB)
- Increment(Local2)
- }
- Store(0x0a, dbgb)
- }
-}
+++ /dev/null
-/* HPET */
-
-Scope(\_SB) {
- Device(HPET) {
- Name(_HID, EISAID("PNP0103"))
- Name(_UID, 0)
- OperationRegion(HPTM, SystemMemory, 0xfed00000, 0x400)
- Field(HPTM, DWordAcc, Lock, Preserve) {
- VEND, 32,
- PRD, 32,
- }
- Method(_STA, 0, NotSerialized) {
- Store(VEND, Local0)
- Store(PRD, Local1)
- ShiftRight(Local0, 16, Local0)
- If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
- Return (0x0)
- }
- If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) {
- Return (0x0)
- }
- Return (0x0f)
- }
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadOnly,
- 0xfed00000, /* Address Base */
- 0x00000400, /* Address Length */
- )
- })
- }
-}
+++ /dev/null
-/* Common legacy ISA style devices. */
-Scope(\_SB.PCI0.ISA) {
-
- Device(RTC) {
- Name(_HID, EisaId("PNP0B00"))
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
- IRQNoFlags() { 8 }
- IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
- })
- }
-
- Device(KBD) {
- Name(_HID, EisaId("PNP0303"))
- Method(_STA, 0, NotSerialized) {
- Return (0x0f)
- }
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags() { 1 }
- })
- }
-
- Device(MOU) {
- Name(_HID, EisaId("PNP0F13"))
- Method(_STA, 0, NotSerialized) {
- Return (0x0f)
- }
- Name(_CRS, ResourceTemplate() {
- IRQNoFlags() { 12 }
- })
- }
-
- Device(FDC0) {
- Name(_HID, EisaId("PNP0700"))
- Method(_STA, 0, NotSerialized) {
- Store(FDEN, Local0)
- If (LEqual(Local0, 0)) {
- Return (0x00)
- } Else {
- Return (0x0f)
- }
- }
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x03f2, 0x03f2, 0x00, 0x04)
- IO(Decode16, 0x03f7, 0x03f7, 0x00, 0x01)
- IRQNoFlags() { 6 }
- DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
- })
- }
-
- Device(LPT) {
- Name(_HID, EisaId("PNP0400"))
- Method(_STA, 0, NotSerialized) {
- Store(LPEN, Local0)
- If (LEqual(Local0, 0)) {
- Return (0x00)
- } Else {
- Return (0x0f)
- }
- }
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
- IRQNoFlags() { 7 }
- })
- }
-
- Device(COM1) {
- Name(_HID, EisaId("PNP0501"))
- Name(_UID, 0x01)
- Method(_STA, 0, NotSerialized) {
- Store(CAEN, Local0)
- If (LEqual(Local0, 0)) {
- Return (0x00)
- } Else {
- Return (0x0f)
- }
- }
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x03f8, 0x03f8, 0x00, 0x08)
- IRQNoFlags() { 4 }
- })
- }
-
- Device(COM2) {
- Name(_HID, EisaId("PNP0501"))
- Name(_UID, 0x02)
- Method(_STA, 0, NotSerialized) {
- Store(CBEN, Local0)
- If (LEqual(Local0, 0)) {
- Return (0x00)
- } Else {
- Return (0x0f)
- }
- }
- Name(_CRS, ResourceTemplate() {
- IO(Decode16, 0x02f8, 0x02f8, 0x00, 0x08)
- IRQNoFlags() { 3 }
- })
- }
-}
+++ /dev/null
-/* PCI CRS (current resources) definition. */
-Scope(\_SB.PCI0) {
-
- Name(CRES, ResourceTemplate() {
- WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, /* Address Space Granularity */
- 0x0000, /* Address Range Minimum */
- 0x00ff, /* Address Range Maximum */
- 0x0000, /* Address Translation Offset */
- 0x0100, /* Address Length */
- ,, )
- IO(Decode16,
- 0x0cf8, /* Address Range Minimum */
- 0x0cf8, /* Address Range Maximum */
- 0x01, /* Address Alignment */
- 0x08, /* Address Length */
- )
- WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* Address Space Granularity */
- 0x0000, /* Address Range Minimum */
- 0x0cf7, /* Address Range Maximum */
- 0x0000, /* Address Translation Offset */
- 0x0cf8, /* Address Length */
- ,, , TypeStatic)
- WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* Address Space Granularity */
- 0x0d00, /* Address Range Minimum */
- 0xffff, /* Address Range Maximum */
- 0x0000, /* Address Translation Offset */
- 0xf300, /* Address Length */
- ,, , TypeStatic)
- DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Address Space Granularity */
- 0x000a0000, /* Address Range Minimum */
- 0x000bffff, /* Address Range Maximum */
- 0x00000000, /* Address Translation Offset */
- 0x00020000, /* Address Length */
- ,, , AddressRangeMemory, TypeStatic)
- DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, /* Address Space Granularity */
- 0xe0000000, /* Address Range Minimum */
- 0xfebfffff, /* Address Range Maximum */
- 0x00000000, /* Address Translation Offset */
- 0x1ec00000, /* Address Length */
- ,, PW32, AddressRangeMemory, TypeStatic)
- })
-
- Name(CR64, ResourceTemplate() {
- QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, /* Address Space Granularity */
- 0x80000000, /* Address Range Minimum */
- 0xffffffff, /* Address Range Maximum */
- 0x00000000, /* Address Translation Offset */
- 0x80000000, /* Address Length */
- ,, PW64, AddressRangeMemory, TypeStatic)
- })
-
- Method(_CRS, 0) {
- Return (CRES)
- }
-}
+++ /dev/null
-/*
- * QEMU ACPI DSDT ASL definition
- *
- * Copyright (c) 2006 Fabrice Bellard
- *
- * Copyright (c) 2010 Isaku Yamahata
- * yamahata at valinux co jp
- * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
- */
-
-DefinitionBlock (
- "dsdt.aml", /* Output Filename */
- "DSDT", /* Signature */
- 0x01, /* DSDT Compliance Revision */
- "UBOO", /* OEMID */
- "UBOOT ", /* TABLE ID */
- 0x2 /* OEM Revision */
- )
-{
-
-#include "acpi/dbug.asl"
-
- Scope(\_SB) {
- OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
- OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
- Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
- PCIB, 8,
- }
- }
-
-
-/* PCI Bus definition */
-
- Scope(\_SB) {
- Device(PCI0) {
- Name(_HID, EisaId("PNP0A08"))
- Name(_CID, EisaId("PNP0A03"))
- Name(_ADR, 0x00)
- Name(_UID, 1)
-
- /* _OSC: based on sample of ACPI3.0b spec */
- Name(SUPP, 0) /* PCI _OSC Support Field value */
- Name(CTRL, 0) /* PCI _OSC Control Field value */
- Method(_OSC, 4) {
- /* Create DWORD-addressable fields from Capabilities Buffer */
- CreateDWordField(Arg3, 0, CDW1)
-
- /* Check for proper UUID */
- If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
- {
- /* Create DWORD-addressable fields from Capabilities Buffer */
- CreateDWordField(Arg3, 4, CDW2)
- CreateDWordField(Arg3, 8, CDW3)
-
- /* Save Capabilities DWORD2 & 3 */
- Store(CDW2, SUPP)
- Store(CDW3, CTRL)
-
- /*
- * Always allow native PME, AER (no dependencies)
- * Never allow SHPC (no SHPC controller in this system)
- */
- And(CTRL, 0x1d, CTRL)
-
- If (LNotEqual(Arg1, One)) {
- /* Unknown revision */
- Or(CDW1, 0x08, CDW1)
- }
- If (LNotEqual(CDW3, CTRL)) {
- /* Capabilities bits were masked */
- Or(CDW1, 0x10, CDW1)
- }
- /* Update DWORD3 in the buffer */
- Store(CTRL, CDW3)
- } Else {
- Or(CDW1, 4, CDW1) /* Unrecognized UUID */
- }
- Return (Arg3)
- }
- }
- }
-
-#include "acpi/pci-crs.asl"
-#include "acpi/hpet.asl"
-
-
-/* VGA */
-
- Scope(\_SB.PCI0) {
- Device(VGA) {
- Name(_ADR, 0x00010000)
- Method(_S1D, 0, NotSerialized) {
- Return (0x00)
- }
- Method(_S2D, 0, NotSerialized) {
- Return (0x00)
- }
- Method(_S3D, 0, NotSerialized) {
- Return (0x00)
- }
- }
- }
-
-
-/* LPC ISA bridge */
-
- Scope(\_SB.PCI0) {
- /* PCI D31:f0 LPC ISA bridge */
- Device(ISA) {
- /* PCI D31:f0 */
- Name(_ADR, 0x001f0000)
-
- /* ICH9 PCI to ISA irq remapping */
- OperationRegion(PIRQ, PCI_Config, 0x60, 0x0c)
-
- OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
- Field(LPCD, AnyAcc, NoLock, Preserve) {
- COMA, 3,
- , 1,
- COMB, 3,
-
- Offset(0x01),
- LPTD, 2,
- , 2,
- FDCD, 2
- }
- OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
- Field(LPCE, AnyAcc, NoLock, Preserve) {
- CAEN, 1,
- CBEN, 1,
- LPEN, 1,
- FDEN, 1
- }
- }
- }
-
-#include "acpi/isa.asl"
-
-
-/* PCI IRQs */
-
- /* Zero => PIC mode, One => APIC Mode */
- Name(\PICF, Zero)
- Method(\_PIC, 1, NotSerialized) {
- Store(Arg0, \PICF)
- }
-
- Scope(\_SB) {
- Scope(PCI0) {
-#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
- Package() { nr##ffff, 0, lnk0, 0 }, \
- Package() { nr##ffff, 1, lnk1, 0 }, \
- Package() { nr##ffff, 2, lnk2, 0 }, \
- Package() { nr##ffff, 3, lnk3, 0 }
-
-#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
-#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
-
-#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
-#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
-#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
-#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
-
- Name(PRTP, Package() {
- prt_slot_lnkE(0x0000),
- prt_slot_lnkF(0x0001),
- prt_slot_lnkG(0x0002),
- prt_slot_lnkH(0x0003),
- prt_slot_lnkE(0x0004),
- prt_slot_lnkF(0x0005),
- prt_slot_lnkG(0x0006),
- prt_slot_lnkH(0x0007),
- prt_slot_lnkE(0x0008),
- prt_slot_lnkF(0x0009),
- prt_slot_lnkG(0x000a),
- prt_slot_lnkH(0x000b),
- prt_slot_lnkE(0x000c),
- prt_slot_lnkF(0x000d),
- prt_slot_lnkG(0x000e),
- prt_slot_lnkH(0x000f),
- prt_slot_lnkE(0x0010),
- prt_slot_lnkF(0x0011),
- prt_slot_lnkG(0x0012),
- prt_slot_lnkH(0x0013),
- prt_slot_lnkE(0x0014),
- prt_slot_lnkF(0x0015),
- prt_slot_lnkG(0x0016),
- prt_slot_lnkH(0x0017),
- prt_slot_lnkE(0x0018),
-
- /* INTA -> PIRQA for slot 25 - 31
- see the default value of D<N>IR */
- prt_slot_lnkA(0x0019),
- prt_slot_lnkA(0x001a),
- prt_slot_lnkA(0x001b),
- prt_slot_lnkA(0x001c),
- prt_slot_lnkA(0x001d),
-
- /* PCIe->PCI bridge. use PIRQ[E-H] */
- prt_slot_lnkE(0x001e),
-
- prt_slot_lnkA(0x001f)
- })
-
-#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
- Package() { nr##ffff, 0, gsi0, 0 }, \
- Package() { nr##ffff, 1, gsi1, 0 }, \
- Package() { nr##ffff, 2, gsi2, 0 }, \
- Package() { nr##ffff, 3, gsi3, 0 }
-
-#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
-#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
-#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
-#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
-
-#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
-#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
-#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
-#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
-
- Name(PRTA, Package() {
- prt_slot_gsiE(0x0000),
- prt_slot_gsiF(0x0001),
- prt_slot_gsiG(0x0002),
- prt_slot_gsiH(0x0003),
- prt_slot_gsiE(0x0004),
- prt_slot_gsiF(0x0005),
- prt_slot_gsiG(0x0006),
- prt_slot_gsiH(0x0007),
- prt_slot_gsiE(0x0008),
- prt_slot_gsiF(0x0009),
- prt_slot_gsiG(0x000a),
- prt_slot_gsiH(0x000b),
- prt_slot_gsiE(0x000c),
- prt_slot_gsiF(0x000d),
- prt_slot_gsiG(0x000e),
- prt_slot_gsiH(0x000f),
- prt_slot_gsiE(0x0010),
- prt_slot_gsiF(0x0011),
- prt_slot_gsiG(0x0012),
- prt_slot_gsiH(0x0013),
- prt_slot_gsiE(0x0014),
- prt_slot_gsiF(0x0015),
- prt_slot_gsiG(0x0016),
- prt_slot_gsiH(0x0017),
- prt_slot_gsiE(0x0018),
-
- /*
- * INTA -> PIRQA for slot 25 - 31, but 30
- * see the default value of D<N>IR
- */
- prt_slot_gsiA(0x0019),
- prt_slot_gsiA(0x001a),
- prt_slot_gsiA(0x001b),
- prt_slot_gsiA(0x001c),
- prt_slot_gsiA(0x001d),
-
- /* PCIe->PCI bridge. use PIRQ[E-H] */
- prt_slot_gsiE(0x001e),
-
- prt_slot_gsiA(0x001f)
- })
-
- Method(_PRT, 0, NotSerialized) {
- /*
- * PCI IRQ routing table,
- * example from ACPI 2.0a
- * specification, section 6.2.8.1
- * Note: we provide the same info
- * as the PCI routing table
- * of the Bochs BIOS
- */
- If (LEqual(\PICF, Zero)) {
- Return (PRTP)
- } Else {
- Return (PRTA)
- }
- }
- }
-
- Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
- PRQA, 8,
- PRQB, 8,
- PRQC, 8,
- PRQD, 8,
-
- Offset(0x08),
- PRQE, 8,
- PRQF, 8,
- PRQG, 8,
- PRQH, 8
- }
-
- Method(IQST, 1, NotSerialized) {
- /* _STA method - get status */
- If (And(0x80, Arg0)) {
- Return (0x09)
- }
- Return (0x0b)
- }
- Method(IQCR, 1, NotSerialized) {
- /* _CRS method - get current settings */
- Name(PRR0, ResourceTemplate() {
- Interrupt(, Level, ActiveHigh, Shared) { 0 }
- })
- CreateDWordField(PRR0, 0x05, PRRI)
- Store(And(Arg0, 0x0f), PRRI)
- Return (PRR0)
- }
-
-#define define_link(link, uid, reg) \
- Device(link) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- Name(_PRS, ResourceTemplate() { \
- Interrupt(, Level, ActiveHigh, Shared) { \
- 5, 10, 11 \
- } \
- }) \
- Method(_STA, 0, NotSerialized) { \
- Return (IQST(reg)) \
- } \
- Method(_DIS, 0, NotSerialized) { \
- Or(reg, 0x80, reg) \
- } \
- Method(_CRS, 0, NotSerialized) { \
- Return (IQCR(reg)) \
- } \
- Method(_SRS, 1, NotSerialized) { \
- CreateDWordField(Arg0, 0x05, PRRI) \
- Store(PRRI, reg) \
- } \
- }
-
- define_link(LNKA, 0, PRQA)
- define_link(LNKB, 1, PRQB)
- define_link(LNKC, 2, PRQC)
- define_link(LNKD, 3, PRQD)
- define_link(LNKE, 4, PRQE)
- define_link(LNKF, 5, PRQF)
- define_link(LNKG, 6, PRQG)
- define_link(LNKH, 7, PRQH)
-
-#define define_gsi_link(link, uid, gsi) \
- Device(link) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- Name(_PRS, ResourceTemplate() { \
- Interrupt(, Level, ActiveHigh, Shared) { \
- gsi \
- } \
- }) \
- Name(_CRS, ResourceTemplate() { \
- Interrupt(, Level, ActiveHigh, Shared) { \
- gsi \
- } \
- }) \
- Method(_SRS, 1, NotSerialized) { \
- } \
- }
-
- define_gsi_link(GSIA, 0, 0x10)
- define_gsi_link(GSIB, 0, 0x11)
- define_gsi_link(GSIC, 0, 0x12)
- define_gsi_link(GSID, 0, 0x13)
- define_gsi_link(GSIE, 0, 0x14)
- define_gsi_link(GSIF, 0, 0x15)
- define_gsi_link(GSIG, 0, 0x16)
- define_gsi_link(GSIH, 0, 0x17)
- }
-
-/* General purpose events */
-
- Scope(\_GPE) {
- Name(_HID, "ACPI0006")
-
- Method(_L00) {
- }
- Method(_L01) {
- }
- Method(_L02) {
- }
- Method(_L03) {
- }
- Method(_L04) {
- }
- Method(_L05) {
- }
- Method(_L06) {
- }
- Method(_L07) {
- }
- Method(_L08) {
- }
- Method(_L09) {
- }
- Method(_L0A) {
- }
- Method(_L0B) {
- }
- Method(_L0C) {
- }
- Method(_L0D) {
- }
- Method(_L0E) {
- }
- Method(_L0F) {
- }
- }
-}
/*
- * (C) Copyright 2015 Miao Yan <yanmiaoebst@gmail.com>
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
- int i;
- short n;
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (i < info->sector_count) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("ST "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
- break;
- case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
- break;
- case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
- break;
- case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
- break;
- case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
- break;
- case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
- break;
- case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
- break;
- case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
- break;
- case FLASH_AM640U: printf ("AM29LV640D (64 M, uniform sector)\n");
- break;
- case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
- break;
- case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
- break;
- case FLASH_STMW320DT: printf ("M29W320DT (32 M, top sector)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
-#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
- /* print empty and read-only info */
- printf (" %08lX%s%s",
- info->start[i],
- erased ? " E" : " ",
- info->protect[i] ? "RO " : " ");
-#else
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
-#endif
-
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- short n;
- CONFIG_SYS_FLASH_WORD_SIZE value;
- ulong base = (ulong)addr;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
-
- debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
-
- /* Write auto select command: read Manufacturer ID */
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
-
- value = addr2[CONFIG_SYS_FLASH_READ0];
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
- info->flash_id = FLASH_MAN_STM;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
-
- switch (value) {
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
- info->flash_id += FLASH_STMW320DT;
- info->sector_count = 67;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
- info->sector_count = 71;
- info->size = 0x00400000; break; /* => 4 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
- info->sector_count = 128;
- info->size = 0x00800000; break; /* => 8 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- /* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
- /* set sector offsets for bottom boot block type */
- for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
- info->start[i] = base;
- base += 8 << 10;
- }
- while (i < info->sector_count) { /* 64k regular sectors */
- info->start[i] = base;
- base += 64 << 10;
- ++i;
- }
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
- ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
- /* set sector offsets for top boot block type */
- base += info->size;
- i = info->sector_count;
- /* 1 x 16k boot sector */
- base -= 16 << 10;
- --i;
- info->start[i] = base;
- /* 2 x 8k boot sectors */
- for (n=0; n<2; ++n) {
- base -= 8 << 10;
- --i;
- info->start[i] = base;
- }
- /* 1 x 32k boot sector */
- base -= 32 << 10;
- --i;
- info->start[i] = base;
-
- while (i > 0) { /* 64k regular sectors */
- base -= 64 << 10;
- --i;
- info->start[i] = base;
- }
- } else {
- if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- int i;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- if (sect == s_first) {
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
- addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- }
- addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
- while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
-#ifdef CONFIG_B2
- data = data | ((*(uchar *)cp)<<(8*i));
-#else
- data = (data << 8) | (*(uchar *)cp);
-#endif
- }
- for (; i<4 && cnt>0; ++i) {
-#ifdef CONFIG_B2
- data = data | ((*src++)<<(8*i));
-#else
- data = (data << 8) | *src++;
-#endif
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
-#ifdef CONFIG_B2
- data = data | ((*(uchar *)cp)<<(8*i));
-#else
- data = (data << 8) | (*(uchar *)cp);
-#endif
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
-#ifdef CONFIG_B2
- data = (*(ulong*)src);
- src += 4;
-#else
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
-#endif
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-#ifdef CONFIG_B2
- data = data | ((*src++)<<(8*i));
-#else
- data = (data << 8) | *src++;
-#endif
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
-#ifdef CONFIG_B2
- data = data | ((*(uchar *)cp)<<(8*i));
-#else
- data = (data << 8) | (*(uchar *)cp);
-#endif
- }
-
- return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- ulong *data_ptr = &data;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
- volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)data_ptr;
- ulong start;
- int flag;
- int i;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*((volatile ulong *)dest) & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
- {
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
- addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
config SYS_CONFIG_NAME
default "am57xx_evm"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 6
+ default 3
+ help
+ The AM57x (and DRA7xx) SoC has a total of 6 UARTs available to it.
+ Depending on your specific board you may want something other than UART3
+ here.
+
source "board/ti/common/Kconfig"
endif
#define board_is_x15() board_ti_is("BBRDX15_")
#define board_is_am572x_evm() board_ti_is("AM572PM_")
+#define board_is_am572x_idk() board_ti_is("AM572IDK")
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
- .sdram_tim1 = 0xcccf36ab,
+ .sdram_tim1 = 0xcccf36b3,
.sdram_tim2 = 0x308f7fda,
- .sdram_tim3 = 0x409f88a8,
+ .sdram_tim3 = 0x407f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
bname = "BeagleBoard X15";
else if (board_is_am572x_evm())
bname = "AM572x EVM";
+ else if (board_is_am572x_idk())
+ bname = "AM572x IDK";
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
if (board_is_am572x_evm())
name = "am57xx_evm";
+ else if (board_is_am572x_idk())
+ name = "am572x_idk";
else
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
- __recalibrate_iodelay(core_padconf_array_essential,
- ARRAY_SIZE(core_padconf_array_essential),
- iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
+ const struct pad_conf_entry *pconf;
+ const struct iodelay_cfg_entry *iod;
+ int pconf_sz, iod_sz;
+
+ if (board_is_am572x_idk()) {
+ pconf = core_padconf_array_essential_am572x_idk;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
+ iod = iodelay_cfg_array_am572x_idk;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
+ } else {
+ /* Common for X15/GPEVM */
+ pconf = core_padconf_array_essential_x15;
+ pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
+ iod = iodelay_cfg_array_x15;
+ iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
+ }
+
+ __recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
}
#endif
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
+ /* The phy address for the AM572x IDK are different than x15 */
+ if (board_is_am572x_idk()) {
+ cpsw_data.slave_data[0].phy_addr = 0;
+ cpsw_data.slave_data[1].phy_addr = 1;
+ }
+
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
#include <asm/arch/mux_dra7xx.h>
-const struct pad_conf_entry core_padconf_array_essential[] = {
+const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
{RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */
};
+const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
+ {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
+ {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
+ {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
+ {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
+ {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
+ {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
+ {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
+ {VIN1A_D13, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d13.gpio3_17 */
+ {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
+ {VIN1A_D15, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d15.gpio3_19 */
+ {VIN1A_D17, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d17.gpio3_21 */
+ {VIN1A_D18, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
+ {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
+ {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
+ {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
+ {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
+ {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
+ {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
+ {VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */
+ {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.ecap1 */
+ {VIN2A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.gpio4_4 */
+ {VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.gpio4_5 */
+ {VIN2A_D5, (M13 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.pr1_pru1_gpo2 */
+ {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
+ {VIN2A_D7, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.pr1_mii_mii1_txen */
+ {VIN2A_D8, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.pr1_mii_mii1_txd3 */
+ {VIN2A_D9, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.pr1_mii_mii1_txd2 */
+ {VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
+ {VIN2A_D11, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
+ {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
+ {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
+ {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */
+ {RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
+ {UART3_RXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.pr1_mii0_rxdv */
+ {UART3_TXD, (M11 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.rp1_mii_mr0_clk */
+ {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M14 | PIN_OUTPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M0 | PIN_OUTPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6)_16 */
+ {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.i6_19 */
+ {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+ {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
+ {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */
+ {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
+ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
+ {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */
+ {MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */
+ {MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */
+ {MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */
+ {MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */
+ {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
+ {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)},/* mcasp5_fsx.pr2_pru1_gpi2 */
+ {MCASP5_AXR0, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.pr2_pru1_gpo3 */
+ {MCASP5_AXR1, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.pr2_pru1_gpo4 */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
+ {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */
+ {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
+ {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
+ {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
+ {UART1_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rxd.gpio7_22 */
+ {UART1_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio7_23 */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
+ {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
+ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
+ {TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */
+ {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
+ {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_INPUT)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
+ {RESETN, (M0 | PIN_OUTPUT_PULLUP)}, /* resetn.resetn */
+ {RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */
+};
+
const struct pad_conf_entry early_padconf[] = {
{UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
{UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
};
#ifdef CONFIG_IODELAY_RECALIBRATION
-const struct iodelay_cfg_entry iodelay_cfg_array[] = {
+const struct iodelay_cfg_entry iodelay_cfg_array_x15[] = {
{0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
{0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
{0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
{0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
{0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
};
+
+const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
+ {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
+ {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
+ {0x0138, 2605, 45}, /* CFG_GPMC_A12_IN */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 1976, 1389}, /* CFG_GPMC_A14_IN */
+ {0x015C, 1872, 1408}, /* CFG_GPMC_A15_IN */
+ {0x0168, 1914, 1506}, /* CFG_GPMC_A16_IN */
+ {0x0170, 57, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
+ {0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
+ {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
+ {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
+ {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
+ {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
+ {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
+ {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
+ {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
+ {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
+};
#endif
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TI_AEMIF)
static struct aemif_config aemif_configs[] = {
{ /* CS0 */
.mode = AEMIF_MODE_NAND,
.width = AEMIF_WIDTH_8,
},
};
+#endif
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
if (ddr3_size)
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
return 0;
help
Boot an ELF/vxWorks image from the memory.
+config CMD_FDT
+ bool "Flattened Device Tree utility commands"
+ default y
+ depends on OF_LIBFDT
+ help
+ Do FDT related setup before booting into the Operating System.
+
config CMD_GO
bool "go"
default y
obj-$(CONFIG_CMD_EXT2) += ext2.o
obj-$(CONFIG_CMD_FAT) += fat.o
obj-$(CONFIG_CMD_FDC) += fdc.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_CMD_FDT) += fdt.o
obj-$(CONFIG_CMD_FITUPD) += fitupd.o
obj-$(CONFIG_CMD_FLASH) += flash.o
ifdef CONFIG_FPGA
#include <errno.h>
#include <libfdt.h>
#include <libfdt_env.h>
+#include <memalign.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
/*
* When booting using the "bootefi" command, we don't know which
}
};
+static struct efi_device_path_file_path bootefi_device_path[] = {
+ {
+ .dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ .dp.length = sizeof(bootefi_image_path[0]),
+ .str = { 'b','o','o','t','e','f','i' },
+ }, {
+ .dp.type = DEVICE_PATH_TYPE_END,
+ .dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+ .dp.length = sizeof(bootefi_image_path[0]),
+ }
+};
+
static efi_status_t bootefi_open_dp(void *handle, efi_guid_t *protocol,
void **protocol_interface, void *agent_handle,
void *controller_handle, uint32_t attributes)
{
- *protocol_interface = bootefi_image_path;
+ *protocol_interface = bootefi_device_path;
return EFI_SUCCESS;
}
/* The EFI loaded_image interface for the image executed via "bootefi" */
static struct efi_loaded_image loaded_image_info = {
- .device_handle = bootefi_image_path,
+ .device_handle = bootefi_device_path,
.file_path = bootefi_image_path,
};
{
/*
* When asking for the device path interface, return
- * bootefi_image_path
+ * bootefi_device_path
*/
.guid = &efi_guid_device_path,
.open = &bootefi_open_dp,
/* The EFI object struct for the device the "bootefi" image was loaded from */
static struct efi_object bootefi_device_obj = {
- .handle = bootefi_image_path,
+ .handle = bootefi_device_path,
.protocols = {
{
/* When asking for the device path interface, return
- * bootefi_image_path */
+ * bootefi_device_path */
.guid = &efi_guid_device_path,
.open = &bootefi_open_dp,
}
},
};
+static void *copy_fdt(void *fdt)
+{
+ u64 fdt_size = fdt_totalsize(fdt);
+ unsigned long fdt_ram_start = -1L, fdt_pages;
+ u64 new_fdt_addr;
+ void *new_fdt;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ u64 ram_start = gd->bd->bi_dram[i].start;
+ u64 ram_size = gd->bd->bi_dram[i].size;
+
+ if (!ram_size)
+ continue;
+
+ if (ram_start < fdt_ram_start)
+ fdt_ram_start = ram_start;
+ }
+
+ /* Give us at least 4kb breathing room */
+ fdt_size = ALIGN(fdt_size + 4096, 4096);
+ fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
+
+ /* Safe fdt location is at 128MB */
+ new_fdt_addr = fdt_ram_start + (128 * 1024 * 1024) + fdt_size;
+ if (efi_allocate_pages(1, EFI_BOOT_SERVICES_DATA, fdt_pages,
+ &new_fdt_addr) != EFI_SUCCESS) {
+ /* If we can't put it there, put it somewhere */
+ new_fdt_addr = (ulong)memalign(4096, fdt_size);
+ }
+ new_fdt = (void*)(ulong)new_fdt_addr;
+ memcpy(new_fdt, fdt, fdt_totalsize(fdt));
+ fdt_set_totalsize(new_fdt, fdt_size);
+
+ return new_fdt;
+}
+
/*
* Load an EFI payload into a newly allocated piece of memory, register all
* EFI objects it would want to access and jump to it.
*/
-static unsigned long do_bootefi_exec(void *efi)
+static unsigned long do_bootefi_exec(void *efi, void *fdt)
{
ulong (*entry)(void *image_handle, struct efi_system_table *st);
ulong fdt_pages, fdt_size, fdt_start, fdt_end;
*/
efi_save_gd();
- /* Update system table to point to our currently loaded FDT */
-
- if (working_fdt) {
+ if (fdt && !fdt_check_header(fdt)) {
/* Prepare fdt for payload */
- if (image_setup_libfdt(&img, working_fdt, 0, NULL)) {
+ fdt = copy_fdt(fdt);
+
+ if (image_setup_libfdt(&img, fdt, 0, NULL)) {
printf("ERROR: Failed to process device tree\n");
return -EINVAL;
}
/* Link to it in the efi tables */
systab.tables[0].guid = EFI_FDT_GUID;
- systab.tables[0].table = working_fdt;
+ systab.tables[0].table = fdt;
systab.nr_tables = 1;
/* And reserve the space in the memory map */
- fdt_start = ((ulong)working_fdt) & ~EFI_PAGE_MASK;
- fdt_end = ((ulong)working_fdt) + fdt_totalsize(working_fdt);
+ fdt_start = ((ulong)fdt) & ~EFI_PAGE_MASK;
+ fdt_end = ((ulong)fdt) + fdt_totalsize(fdt);
fdt_size = (fdt_end - fdt_start) + EFI_PAGE_MASK;
fdt_pages = fdt_size >> EFI_PAGE_SHIFT;
/* Give a bootloader the chance to modify the device tree */
fdt_pages += 2;
efi_add_memory_map(fdt_start, fdt_pages,
EFI_BOOT_SERVICES_DATA, true);
-
} else {
- printf("WARNING: No device tree loaded, expect boot to fail\n");
+ printf("WARNING: Invalid device tree, expect boot to fail\n");
systab.nr_tables = 0;
}
/* Interpreter command to boot an arbitrary EFI image from memory */
static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- char *saddr;
- unsigned long addr;
+ char *saddr, *sfdt;
+ unsigned long addr, fdt_addr = 0;
int r = 0;
if (argc < 2)
addr = simple_strtoul(saddr, NULL, 16);
+ if (argc > 2) {
+ sfdt = argv[2];
+ fdt_addr = simple_strtoul(sfdt, NULL, 16);
+ }
+
printf("## Starting EFI application at 0x%08lx ...\n", addr);
- r = do_bootefi_exec((void *)addr);
+ r = do_bootefi_exec((void *)addr, (void*)fdt_addr);
printf("## Application terminated, r = %d\n", r);
if (r != 0)
#ifdef CONFIG_SYS_LONGHELP
static char bootefi_help_text[] =
- "<image address>\n"
- " - boot EFI payload stored at address <image address>\n"
- "\n"
- "Since most EFI payloads want to have a device tree provided, please\n"
- "make sure you load a device tree using the fdt addr command before\n"
- "executing bootefi.\n";
+ "<image address> [fdt address]\n"
+ " - boot EFI payload stored at address <image address>.\n"
+ " If specified, the device tree located at <fdt address> gets\n"
+ " exposed as EFI configuration table.\n";
#endif
U_BOOT_CMD(
- bootefi, 2, 0, do_bootefi,
+ bootefi, 3, 0, do_bootefi,
"Boots an EFI payload from memory\n",
bootefi_help_text
);
-void efi_set_bootdev(const char *dev, const char *devnr)
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path)
{
- char devname[16] = { 0 }; /* dp->str is u16[16] long */
+ __maybe_unused struct blk_desc *desc;
+ char devname[32] = { 0 }; /* dp->str is u16[32] long */
char *colon;
/* Assemble the condensed device name we use in efi_disk.c */
snprintf(devname, sizeof(devname), "%s%s", dev, devnr);
colon = strchr(devname, ':');
+
+#ifdef CONFIG_ISO_PARTITION
+ /* For ISOs we create partition block devices */
+ desc = blk_get_dev(dev, simple_strtol(devnr, NULL, 10));
+ if (desc && (desc->type != DEV_TYPE_UNKNOWN) &&
+ (desc->part_type == PART_TYPE_ISO)) {
+ if (!colon)
+ snprintf(devname, sizeof(devname), "%s%s:1", dev,
+ devnr);
+ colon = NULL;
+ }
+#endif
+
if (colon)
*colon = '\0';
- /* Patch the bootefi_image_path to the target device */
+ /* Patch bootefi_device_path to the target device */
+ memset(bootefi_device_path[0].str, 0, sizeof(bootefi_device_path[0].str));
+ ascii2unicode(bootefi_device_path[0].str, devname);
+
+ /* Patch bootefi_image_path to the target file path */
memset(bootefi_image_path[0].str, 0, sizeof(bootefi_image_path[0].str));
+ snprintf(devname, sizeof(devname), "%s", path);
ascii2unicode(bootefi_image_path[0].str, devname);
}
static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "");
+ efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
+ (argc > 4) ? argv[4] : "");
return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
}
!defined(CONFIG_ENV_IS_IN_NAND) && \
!defined(CONFIG_ENV_IS_IN_NVRAM) && \
!defined(CONFIG_ENV_IS_IN_ONENAND) && \
+ !defined(CONFIG_ENV_IS_IN_SATA) && \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
!defined(CONFIG_ENV_IS_IN_REMOTE) && \
!defined(CONFIG_ENV_IS_IN_UBI) && \
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
#endif
/*
#define UMS_NAME_LEN 16
-static int ums_init(const char *devtype, const char *devnums)
+static int ums_init(const char *devtype, const char *devnums_part_str)
{
- char *s, *t, *devnum, *name;
+ char *s, *t, *devnum_part_str, *name;
struct blk_desc *block_dev;
- int ret;
+ disk_partition_t info;
+ int partnum;
+ int ret = -1;
struct ums *ums_new;
- s = strdup(devnums);
+ s = strdup(devnums_part_str);
if (!s)
return -1;
ums_count = 0;
for (;;) {
- devnum = strsep(&t, ",");
- if (!devnum)
+ devnum_part_str = strsep(&t, ",");
+ if (!devnum_part_str)
break;
- ret = blk_get_device_by_str(devtype, devnum, &block_dev);
- if (ret < 0)
+ partnum = blk_get_device_part_str(devtype, devnum_part_str,
+ &block_dev, &info, 1);
+
+ if (partnum < 0)
goto cleanup;
+ /* Check if the argument is in legacy format. If yes,
+ * expose all partitions by setting the partnum = 0
+ * e.g. ums 0 mmc 0
+ */
+ if (!strchr(devnum_part_str, ':'))
+ partnum = 0;
+
/* f_mass_storage.c assumes SECTOR_SIZE sectors */
- if (block_dev->blksz != SECTOR_SIZE) {
- ret = -1;
+ if (block_dev->blksz != SECTOR_SIZE)
goto cleanup;
- }
ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
- if (!ums_new) {
- ret = -1;
+ if (!ums_new)
goto cleanup;
- }
ums = ums_new;
+ /* if partnum = 0, expose all partitions */
+ if (partnum == 0) {
+ ums[ums_count].start_sector = 0;
+ ums[ums_count].num_sectors = block_dev->lba;
+ } else {
+ ums[ums_count].start_sector = info.start;
+ ums[ums_count].num_sectors = info.size;
+ }
+
ums[ums_count].read_sector = ums_read_sector;
ums[ums_count].write_sector = ums_write_sector;
- ums[ums_count].start_sector = 0;
- ums[ums_count].num_sectors = block_dev->lba;
+
name = malloc(UMS_NAME_LEN);
- if (!name) {
- ret = -1;
+ if (!name)
goto cleanup;
- }
snprintf(name, UMS_NAME_LEN, "UMS disk %d", ums_count);
ums[ums_count].name = name;
ums[ums_count].block_dev = *block_dev;
ums_count++;
}
- if (!ums_count)
- ret = -1;
- else
+ if (ums_count)
ret = 0;
cleanup:
U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage,
"Use the UMS [USB Mass Storage]",
- "<USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n"
+ "<USB_controller> [<devtype>] <dev[:part]> e.g. ums 0 mmc 0\n"
" devtype defaults to mmc"
);
obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
obj-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
+obj-$(CONFIG_ENV_IS_IN_SATA) += env_sata.o
obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
--- /dev/null
+/*
+ * (C) Copyright 2010-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <errno.h>
+#include <memalign.h>
+#include <sata.h>
+#include <search.h>
+
+#if defined(CONFIG_ENV_SIZE_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+#error ENV REDUND not supported
+#endif
+
+#if !defined(CONFIG_ENV_OFFSET) || !defined(CONFIG_ENV_SIZE)
+#error CONFIG_ENV_OFFSET or CONFIG_ENV_SIZE not defined
+#endif
+
+char *env_name_spec = "SATA";
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int sata_get_env_dev(void)
+{
+ return CONFIG_SYS_SATA_ENV_DEV;
+}
+
+int env_init(void)
+{
+ /* use default */
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+
+ return 0;
+}
+
+#ifdef CONFIG_CMD_SAVEENV
+static inline int write_env(struct blk_desc *sata, unsigned long size,
+ unsigned long offset, void *buffer)
+{
+ uint blk_start, blk_cnt, n;
+
+ blk_start = ALIGN(offset, sata->blksz) / sata->blksz;
+ blk_cnt = ALIGN(size, sata->blksz) / sata->blksz;
+
+ n = blk_dwrite(sata, blk_start, blk_cnt, buffer);
+
+ return (n == blk_cnt) ? 0 : -1;
+}
+
+int saveenv(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
+ struct blk_desc *sata = NULL;
+ int env_sata, ret;
+
+ if (sata_initialize())
+ return 1;
+
+ env_sata = sata_get_env_dev();
+
+ sata = sata_get_dev(env_sata);
+ if (sata == NULL) {
+ printf("Unknown SATA(%d) device for environment!\n",
+ env_sata);
+ return 1;
+ }
+
+ ret = env_export(env_new);
+ if (ret)
+ return 1;
+
+ printf("Writing to SATA(%d)...", env_sata);
+ if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, &env_new)) {
+ puts("failed\n");
+ return 1;
+ }
+
+ puts("done\n");
+ return 0;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+static inline int read_env(struct blk_desc *sata, unsigned long size,
+ unsigned long offset, void *buffer)
+{
+ uint blk_start, blk_cnt, n;
+
+ blk_start = ALIGN(offset, sata->blksz) / sata->blksz;
+ blk_cnt = ALIGN(size, sata->blksz) / sata->blksz;
+
+ n = blk_dread(sata, blk_start, blk_cnt, buffer);
+
+ return (n == blk_cnt) ? 0 : -1;
+}
+
+void env_relocate_spec(void)
+{
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+ struct blk_desc *sata = NULL;
+ int env_sata;
+
+ if (sata_initialize())
+ return;
+
+ env_sata = sata_get_env_dev();
+
+ sata = sata_get_dev(env_sata);
+ if (sata == NULL) {
+ printf("Unknown SATA(%d) device for environment!\n",
+ env_sata);
+ return;
+ }
+
+ if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf))
+ return set_default_env(NULL);
+
+ env_import(buf, 1);
+}
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
CONFIG_AXP_ALDO4_VOLT=3300
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
+CONFIG_G_DNL_VENDOR_NUM=0x1f3a
+CONFIG_G_DNL_PRODUCT_NUM=0x1010
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_RSA=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_OMAP54XX=y
CONFIG_TARGET_BEAGLE_X15=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Congatec"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_TEGRA20=y
-CONFIG_USB_ULPI=y
-CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_FSL_DSPI=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Toradex"
+CONFIG_G_DNL_VENDOR_NUM=0x1b67
+CONFIG_G_DNL_PRODUCT_NUM=0x0016
# CONFIG_CMD_SETEXPR is not set
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USE_PRIVATE_LIBGCC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_DM=y
+CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_OF_LIBFDT=y
CONFIG_E1000=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Gateworks"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_TI_AEMIF=y
+CONFIG_CMD_NAND=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_TI_AEMIF=y
+CONFIG_CMD_NAND=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
+CONFIG_TI_AEMIF=y
+CONFIG_CMD_NAND=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_CMD_PING=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_SST=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Boundary"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_TEGRA124=y
CONFIG_DM_REGULATOR=y
CONFIG_USB=y
CONFIG_DM_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_PHY_SAMSUNG=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_VIDEO_BRIDGE=y
CONFIG_ERRNO_STR=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_ERRNO_STR=y
CONFIG_CMD_GPIO=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="TI"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_CMD_GPIO=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="TI"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0403
+CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_MISC is not set
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="altera"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="terasic"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="denx"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="terasic"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="ebv"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_USE_TINY_PRINTF=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="TBS"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
+CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Siemens AG"
+CONFIG_G_DNL_VENDOR_NUM=0x0908
+CONFIG_G_DNL_PRODUCT_NUM=0x02d2
CONFIG_OF_LIBFDT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Samsung"
+CONFIG_G_DNL_VENDOR_NUM=0x04e8
+CONFIG_G_DNL_PRODUCT_NUM=0x6601
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="NVIDIA"
+CONFIG_G_DNL_VENDOR_NUM=0x0955
+CONFIG_G_DNL_PRODUCT_NUM=0x701a
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
# CONFIG_CMD_NFS is not set
CONFIG_USB=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="FSL"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
CONFIG_OF_LIBFDT=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
CONFIG_OF_LIBFDT=y
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
# CONFIG_REGEX is not set
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_DM_ETH=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
+CONFIG_OF_LIBFDT=y
CONFIG_ARM=y
CONFIG_TARGET_ZIPITZ2=y
+CONFIG_SYS_PROMPT="$ "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
-CONFIG_SYS_PROMPT="$ "
+CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03FD
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_ZYNQ_SDHCI=y
CONFIG_ZYNQ_GEM=y
CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
CONFIG_DEBUG_UART_CLOCK=50000000
CONFIG_ZYNQ_QSPI=y
CONFIG_USB=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ULPI=y
CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Xilinx"
+CONFIG_G_DNL_VENDOR_NUM=0x03fd
+CONFIG_G_DNL_PRODUCT_NUM=0x0300
static unsigned char tmpbuf[CD_SECTSIZE];
+unsigned long iso_dread(struct blk_desc *block_dev, lbaint_t start,
+ lbaint_t blkcnt, void *buffer)
+{
+ unsigned long ret;
+
+ if (block_dev->blksz == 512) {
+ /* Convert from 2048 to 512 sector size */
+ start *= 4;
+ blkcnt *= 4;
+ }
+
+ ret = blk_dread(block_dev, start, blkcnt, buffer);
+
+ if (block_dev->blksz == 512)
+ ret /= 4;
+
+ return ret;
+}
+
/* only boot records will be listed as valid partitions */
int part_get_info_iso_verb(struct blk_desc *dev_desc, int part_num,
disk_partition_t *info, int verb)
iso_val_entry_t *pve = (iso_val_entry_t *)tmpbuf;
iso_init_def_entry_t *pide;
- if (dev_desc->blksz != CD_SECTSIZE)
+ if ((dev_desc->blksz != CD_SECTSIZE) && (dev_desc->blksz != 512))
return -1;
/* the first sector (sector 0x10) must be a primary volume desc */
blkaddr=PVD_OFFSET;
- if (blk_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
+ if (iso_dread(dev_desc, PVD_OFFSET, 1, (ulong *)tmpbuf) != 1)
return -1;
if(ppr->desctype!=0x01) {
if(verb)
ppr->stand_ident, dev_desc->devnum, part_num);
return (-1);
}
- lastsect= ((ppr->firstsek_LEpathtab1_LE & 0x000000ff)<<24) +
- ((ppr->firstsek_LEpathtab1_LE & 0x0000ff00)<< 8) +
- ((ppr->firstsek_LEpathtab1_LE & 0x00ff0000)>> 8) +
- ((ppr->firstsek_LEpathtab1_LE & 0xff000000)>>24) ;
- info->blksz=ppr->secsize_BE; /* assuming same block size for all entries */
+ lastsect = le32_to_cpu(ppr->firstsek_LEpathtab1_LE);
+ /* assuming same block size for all entries */
+ info->blksz = be16_to_cpu(ppr->secsize_BE);
PRINTF(" Lastsect:%08lx\n",lastsect);
for(i=blkaddr;i<lastsect;i++) {
PRINTF("Reading block %d\n", i);
- if (blk_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
+ if (iso_dread(dev_desc, i, 1, (ulong *)tmpbuf) != 1)
return -1;
if(ppr->desctype==0x00)
break; /* boot entry found */
}
bootaddr = get_unaligned_le32(pbr->pointer);
PRINTF(" Boot Entry at: %08lX\n",bootaddr);
- if (blk_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
+ if (iso_dread(dev_desc, bootaddr, 1, (ulong *)tmpbuf) != 1) {
if(verb)
printf ("** Can't read Boot Entry at %lX on %d:%d **\n",
bootaddr, dev_desc->devnum, part_num);
chksum=0;
chksumbuf = (unsigned short *)tmpbuf;
for(i=0;i<0x10;i++)
- chksum+=((chksumbuf[i] &0xff)<<8)+((chksumbuf[i] &0xff00)>>8);
+ chksum += le16_to_cpu(chksumbuf[i]);
if(chksum!=0) {
if(verb)
printf("** Checksum Error in booting catalog validation entry on %d:%d **\n",
}
#endif
/* the validation entry seems to be ok, now search the "partition" */
- entry_num=0;
+ entry_num=1;
offset=0x20;
strcpy((char *)info->type, "U-Boot");
switch(dev_desc->if_type) {
}
newblkaddr = get_unaligned_le32(pide->rel_block_addr);
info->start=newblkaddr;
- PRINTF(" part %d found @ %lx size %lx\n",part_num,newblkaddr,info->size);
+
+ if (dev_desc->blksz == 512) {
+ info->size *= 4;
+ info->start *= 4;
+ info->blksz = 512;
+ }
+
+ PRINTF(" part %d found @ %lx size %lx\n",part_num,info->start,info->size);
return 0;
}
{
disk_partition_t info;
- return part_get_info_iso_verb(dev_desc, 0, &info, 0);
+ return part_get_info_iso_verb(dev_desc, 1, &info, 1);
}
U_BOOT_PART_TYPE(iso) = {
char sysid[32]; /* system Identifier */
char volid[32]; /* volume Identifier */
unsigned char zeros1[8]; /* unused */
- unsigned long volsiz_LE; /* volume size Little Endian */
- unsigned long volsiz_BE; /* volume size Big Endian */
+ unsigned int volsiz_LE; /* volume size Little Endian */
+ unsigned int volsiz_BE; /* volume size Big Endian */
unsigned char zeros2[32]; /* unused */
unsigned short setsize_LE; /* volume set size LE */
unsigned short setsize_BE; /* volume set size BE */
unsigned short seqnum_BE; /* volume sequence number BE */
unsigned short secsize_LE; /* sector size LE */
unsigned short secsize_BE; /* sector size BE */
- unsigned long pathtablen_LE;/* Path Table size LE */
- unsigned long pathtablen_BE;/* Path Table size BE */
- unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
- unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
- unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
- unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
+ unsigned int pathtablen_LE;/* Path Table size LE */
+ unsigned int pathtablen_BE;/* Path Table size BE */
+ unsigned int firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
+ unsigned int firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
+ unsigned int firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
+ unsigned int firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
unsigned char rootdir[34]; /* directory record for root dir */
char volsetid[128];/* Volume set identifier */
char pubid[128]; /* Publisher identifier */
char sysid[32]; /* system Identifier */
char volid[32]; /* volume Identifier */
unsigned char zeros1[8]; /* unused */
- unsigned long volsiz_LE; /* volume size Little Endian */
- unsigned long volsiz_BE; /* volume size Big Endian */
+ unsigned int volsiz_LE; /* volume size Little Endian */
+ unsigned int volsiz_BE; /* volume size Big Endian */
unsigned char escapeseq[32];/* Escape sequences */
unsigned short setsize_LE; /* volume set size LE */
unsigned short setsize_BE; /* volume set size BE */
unsigned short seqnum_BE; /* volume sequence number BE */
unsigned short secsize_LE; /* sector size LE */
unsigned short secsize_BE; /* sector size BE */
- unsigned long pathtablen_LE;/* Path Table size LE */
- unsigned long pathtablen_BE;/* Path Table size BE */
- unsigned long firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
- unsigned long firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
- unsigned long firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
- unsigned long firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
+ unsigned int pathtablen_LE;/* Path Table size LE */
+ unsigned int pathtablen_BE;/* Path Table size BE */
+ unsigned int firstsek_LEpathtab1_LE; /* location of first occurrence of little endian type path table */
+ unsigned int firstsek_LEpathtab2_LE; /* location of optional occurrence of little endian type path table */
+ unsigned int firstsek_BEpathtab1_BE; /* location of first occurrence of big endian type path table */
+ unsigned int firstsek_BEpathtab2_BE; /* location of optional occurrence of big endian type path table */
unsigned char rootdir[34]; /* directory record for root dir */
char volsetid[128];/* Volume set identifier */
char pubid[128]; /* Publisher identifier */
unsigned char unused;
char sysid[32]; /* system Identifier */
char volid[32]; /* volume partition Identifier */
- unsigned long partloc_LE; /* volume partition location LE */
- unsigned long partloc_BE; /* volume partition location BE */
- unsigned long partsiz_LE; /* volume partition size LE */
- unsigned long partsiz_BE; /* volume partition size BE */
+ unsigned int partloc_LE; /* volume partition location LE */
+ unsigned int partloc_BE; /* volume partition location BE */
+ unsigned int partsiz_LE; /* volume partition size LE */
+ unsigned int partsiz_BE; /* volume partition size BE */
}iso_part_rec_t;
-This patch series adds support for ext4 ls,load and write features in uboot
-Journaling is supported for write feature.
+U-Boot supports access of both ext2 and ext4 filesystems, either in read-only
+mode or in read-write mode.
-To enable support for the ext4 (and ext2) filesystem implementation,
-#define CONFIG_FS_EXT4
+First, to enable support for both ext4 (and, automatically, ext2 as well),
+but without selecting the corresponding commands, use one of:
-If you want write support,
-#define CONFIG_EXT4_WRITE
+ #define CONFIG_FS_EXT4 (for read-only)
+ #define CONFIG_EXT4_WRITE (for read-write)
-To Enable ext2 ls and load commands, modify the board specific config file with
-#define CONFIG_CMD_EXT2
-This automatically defines CONFIG_FS_EXT4 for you.
+Next, to select the ext2-related commands:
-To Enable ext4 ls and load commands, modify the board specific config file with
-#define CONFIG_CMD_EXT4
-This automatically defines CONFIG_FS_EXT4 for you.
+ * ext2ls
+ * ext2load
-To enable ext4 write command, modify the board specific config file with
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-These automatically define CONFIG_FS_EXT4 and CONFIG_EXT4_WRITE for you.
+or ext4-related commands:
-Also relevant are the generic filesystem commands,
-#define CONFIG_CMD_FS_GENERIC
-This does not automatically enable EXT4 support for you.
+ * ext4size
+ * ext4ls
+ * ext4load
-Steps to test:
+use one or both of:
-1. After applying the patch, ext4 specific commands can be seen
- in the boot loader prompt using
- UBOOT #help
+ #define CONFIG_CMD_EXT2
+ #define CONFIG_CMD_EXT4
+
+Selecting either of the above automatically defines CONFIG_FS_EXT4 if it
+wasn't defined already.
+
+In addition, to get the write access command "ext4write", use:
+
+ #define CONFIG_CMD_EXT4_WRITE
+
+which automatically defines CONFIG_EXT4_WRITE if it wasn't defined
+already.
+
+Also relevant are the generic filesystem commands, selected by:
+
+ #define CONFIG_CMD_FS_GENERIC
+
+This does not automatically enable EXT4 support for you, you still need
+to do that yourself.
+
+Some sample commands to test ext4 support:
+1. Check that the commands can be seen in the output of U-Boot help:
+
+ UBOOT #help
+ ...
ext4load- load binary file from a Ext4 file system
ext4ls - list files in a directory (default /)
+ ext4size - determine a file's size
ext4write- create a file in ext4 formatted partition
+ ...
+
+2. To list the files in an ext4-formatted partition, run:
-2. To list the files in ext4 formatted partition, execute
ext4ls <interface> <dev[:part]> [directory]
+
For example:
UBOOT #ext4ls mmc 0:5 /usr/lib
-3. To read and load a file from an ext4 formatted partition to RAM, execute
+3. To read and load a file from an ext4-formatted partition to RAM, run:
+
ext4load <interface> <dev[:part]> [addr] [filename] [bytes]
+
For example:
UBOOT #ext4load mmc 2:2 0x30007fc0 uImage
-4. To write a file to a ext4 formatted partition.
+4. To write a file to an ext4-formatted partition.
+
a) First load a file to RAM at a particular address for example 0x30007fc0.
- Now execute ext4write command
+ Now execute ext4write command:
ext4write <interface> <dev[:part]> [filename] [Address] [sizebytes]
+
For example:
UBOOT #ext4write mmc 2:2 /boot/uImage 0x30007fc0 6183120
(here 6183120 is the size of the file to be written)
source "drivers/led/Kconfig"
+source "drivers/memory/Kconfig"
+
source "drivers/misc/Kconfig"
source "drivers/mmc/Kconfig"
memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
ahci_fill_cmd_slot(pp, cmd_fis_len);
+ ahci_dcache_flush_sata_cmd(pp);
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
return dev_get_addr_index(dev, 0);
}
+void *dev_get_addr_ptr(struct udevice *dev)
+{
+ return (void *)(uintptr_t)dev_get_addr_index(dev, 0);
+}
+
bool device_has_children(struct udevice *dev)
{
return !list_empty(&dev->child_head);
/* Obtain the address bits */
lo_addr_bits = prule->sdram_start >> 20ULL;
- hi_addr_bits = prule->sdram_end >> 20ULL;
+ hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
debug("sdram set rule start %x, %d\n", lo_addr_bits,
prule->sdram_start);
STATIC_SKIP_DELAY_LOOPS)
/* calibration steps requested by the rtl */
-u16 dyn_calib_steps;
+static u16 dyn_calib_steps;
/*
* To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
* zero when skipping
*/
-u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
+static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
((non_skip_value) & skip_delay_mask)
-struct gbl_type *gbl;
-struct param_type *param;
+static struct gbl_type *gbl;
+static struct param_type *param;
static void set_failing_group_stage(u32 group, u32 stage,
u32 substage)
int i;
for (i = 0; i < 16; i++) {
- debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
+ debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
+ scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
}
}
scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
+static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+{
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+}
+
static void scc_mgr_set_dqs_io_in_delay(u32 delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
delay);
}
-static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
+static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
{
- scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
+ rwcfg->mem_dq_per_write_dqs + 1 + dm,
+ delay);
}
static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
*/
scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
read_group, delay, 1);
- writel(0, &sdr_scc_mgr->update);
}
/**
SCC_MGR_HHP_GLOBALS_OFFSET |
SCC_MGR_HHP_EXTRAS_OFFSET;
- debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
+ debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
__func__, __LINE__);
writel(value, addr);
- debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+ debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
__func__, __LINE__);
}
writel(0xff, &sdr_scc_mgr->dq_ena);
/* Zero all DM config settings. */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+ if (!out_only)
+ scc_mgr_set_dm_in_delay(i, 0);
scc_mgr_set_dm_out1_delay(i, 0);
+ }
/* Multicast to all DM enables. */
writel(0xff, &sdr_scc_mgr->dm_ena);
/* DQS shift */
new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
if (new_delay > iocfg->io_out2_delay_max) {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay, new_delay,
iocfg->io_out2_delay_max,
/* OCT shift */
new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
if (new_delay > iocfg->io_out2_delay_max) {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
__func__, __LINE__, write_group, delay,
new_delay, iocfg->io_out2_delay_max,
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
if (all_correct) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"write_test(%u,%u,ALL) : %u == %u => %i\n",
write_group, use_dm, *bit_chk,
param->write_correct_mask,
*bit_chk == param->write_correct_mask);
return *bit_chk == param->write_correct_mask;
} else {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"write_test(%u,%u,ONE) : %u != %i => %i\n",
write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
return *bit_chk != 0x00;
if (bit_chk != param->read_correct_mask)
ret = -EIO;
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
__func__, __LINE__, group, bit_chk,
param->read_correct_mask, ret);
if (all_correct) {
ret = (*bit_chk == param->read_correct_mask);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
__func__, __LINE__, group, all_groups, *bit_chk,
param->read_correct_mask, ret);
} else {
ret = (*bit_chk != 0x00);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
__func__, __LINE__, group, all_groups, *bit_chk,
0, ret);
u32 v, ret, fail_cnt = 0;
for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
- debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
+ debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT, 0);
}
/* No failing read found! Something must have gone wrong. */
- debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
+ debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
return 0;
}
}
/* Cannot find working solution */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
+ debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
__func__, __LINE__);
return -EINVAL;
}
ret = sdr_find_phase(0, grp, work_end, i, p);
if (ret) {
/* Cannot see edge of failing read. */
- debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
+ debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
__func__, __LINE__);
}
work_mid = (work_bgn + work_end) / 2;
- debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
+ debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
- debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
+ debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
work_mid %= tmp_delay;
- debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
+ debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
p = tmp_delay / iocfg->delay_per_opa_tap;
- debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
+ debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
d = DIV_ROUND_UP(work_mid - tmp_delay,
iocfg->delay_per_dqs_en_dchain_tap);
d = iocfg->dqs_en_delay_max;
tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
- debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
+ debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
* because the largest possible margin in 1 VFIFO cycle.
*/
for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
- debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
+ debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
0)) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d center: found: ptap=%u dtap=%u\n",
__func__, __LINE__, p, d);
return 0;
rw_mgr_incr_vfifo(grp);
}
- debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+ debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
__func__, __LINE__);
return -EINVAL;
}
d = 0;
- debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
+ debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
__func__, __LINE__, p);
}
if (d != 0)
work_end -= iocfg->delay_per_dqs_en_dchain_tap;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d p/d: ptap=%u dtap=%u end=%u\n",
__func__, __LINE__, p, d - 1, work_end);
if (work_end < work_bgn) {
/* nil range */
- debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
+ debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
__func__, __LINE__);
return -EINVAL;
}
- debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
+ debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
__func__, __LINE__, work_bgn, work_end);
/*
* To do that we'll back up a ptap and re-find the edge of the
* window using dtaps
*/
- debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
+ debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
__func__, __LINE__);
/* Special case code for backing up a phase */
if (p == 0) {
p = iocfg->dqs_en_phase_max;
rw_mgr_decr_vfifo(grp);
- debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
+ debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
__func__, __LINE__, p);
} else {
p = p - 1;
- debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
+ debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
__func__, __LINE__, p);
}
*/
/* Find a passing read. */
- debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
+ debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
__func__, __LINE__);
initial_failing_dtap = d;
found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
if (found_passing_read) {
/* Find a failing read. */
- debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
+ debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
__func__, __LINE__);
d++;
found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
&d);
} else {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
__func__, __LINE__);
}
dtaps_per_ptap = d - initial_failing_dtap;
writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
- debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
+ debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
__func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
/* Step 6: Find the centre of the window. */
}
*sticky_bit_chk = *sticky_bit_chk | *bit_chk;
ret = ret && (*sticky_bit_chk == correct_mask);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d center(left): dtap=%u => %u == %u && %u",
__func__, __LINE__, d,
*sticky_bit_chk, correct_mask, ret);
*sticky_bit_chk = 0;
for (i = per_dqs - 1; i >= 0; i--) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
__func__, __LINE__, i, left_edge[i],
i, right_edge[i]);
if ((left_edge[i] == delay_max + 1) &&
(right_edge[i] != delay_max + 1)) {
right_edge[i] = delay_max + 1;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d vfifo_center: reset right_edge[%u]: %d\n",
__func__, __LINE__, i, right_edge[i]);
}
}
}
- debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
+ debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
__func__, __LINE__, d);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"bit_chk_test=%i left_edge[%u]: %d ",
bit_chk & 1, i, left_edge[i]);
- debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+ debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
right_edge[i]);
bit_chk >>= 1;
}
/* Check that all bits have a window */
for (i = 0; i < per_dqs; i++) {
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
__func__, __LINE__, i, left_edge[i],
i, right_edge[i]);
(*mid_min)++;
*mid_min = *mid_min / 2;
- debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
+ debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
__func__, __LINE__, *mid_min, min_index);
return min_index;
}
const int min_index, const int test_bgn,
int *dq_margin, int *dqs_margin)
{
- const u32 delay_max = write ? iocfg->io_out1_delay_max :
+ const s32 delay_max = write ? iocfg->io_out1_delay_max :
iocfg->io_in_delay_max;
- const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
+ const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
rwcfg->mem_dq_per_read_dqs;
- const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
+ const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
SCC_MGR_IO_IN_DELAY_OFFSET;
- const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
+ const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
- u32 temp_dq_io_delay1, temp_dq_io_delay2;
+ s32 temp_dq_io_delay1;
int shift_dq, i, p;
/* Initialize data for export structures */
(left_edge[min_index] - right_edge[min_index]))/2 +
(orig_mid_min - mid_min);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"vfifo_center: before: shift_dq[%u]=%d\n",
i, shift_dq);
- temp_dq_io_delay1 = readl(addr + (p << 2));
- temp_dq_io_delay2 = readl(addr + (i << 2));
+ temp_dq_io_delay1 = readl(addr + (i << 2));
if (shift_dq + temp_dq_io_delay1 > delay_max)
- shift_dq = delay_max - temp_dq_io_delay2;
+ shift_dq = delay_max - temp_dq_io_delay1;
else if (shift_dq + temp_dq_io_delay1 < 0)
shift_dq = -temp_dq_io_delay1;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"vfifo_center: after: shift_dq[%u]=%d\n",
i, shift_dq);
scc_mgr_load_dq(p);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"vfifo_center: margin[%u]=[%d,%d]\n", i,
left_edge[i] - shift_dq + (-mid_min),
right_edge[i] + shift_dq - (-mid_min));
scc_mgr_load_dqs(rw_group);
writel(0, &sdr_scc_mgr->update);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d vfifo_center: failed to find edge [%u]: %d %d",
__func__, __LINE__, i, left_edge[i], right_edge[i]);
if (use_read_test) {
new_dqs = 0;
mid_min = start_dqs - new_dqs;
- debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
+ debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
mid_min, new_dqs);
if (iocfg->shift_dqs_en_when_shift_dqs) {
}
new_dqs = start_dqs - mid_min;
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
start_dqs,
iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
/* Move DQS */
scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
scc_mgr_load_dqs(rw_group);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
__func__, __LINE__, dq_margin, dqs_margin);
/* Set a particular DQ/DQS phase. */
scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
- debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
+ debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
/*
*/
ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
if (ret)
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d Guaranteed read test failed: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
return ret;
for (i = 0, p = test_bgn, d = 0;
i < rwcfg->mem_dq_per_read_dqs;
i++, p++, d += delay_step) {
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
__func__, __LINE__, rw_group, r, i, p, d);
*/
ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
__func__, __LINE__, rw_group, !ret);
do {
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
+ debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
/* Add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d lfifo: success: using read_lat=%u\n",
__func__, __LINE__, gbl->curr_read_lat);
} else {
set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
CAL_SUBSTAGE_READ_LATENCY);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d lfifo: failed at initial read_lat=%u\n",
__func__, __LINE__, gbl->curr_read_lat);
}
orig_mid_min = mid_min;
new_dqs = start_dqs;
mid_min = 0;
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
__func__, __LINE__, start_dqs, new_dqs, mid_min);
writel(0, &sdr_scc_mgr->update);
/* Centre DM */
- debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
+ debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
/*
* Set the left and right edge of each bit to an illegal value.
left_edge[0] = -1 * bgn_best;
right_edge[0] = end_best;
- debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
+ debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
__func__, __LINE__, left_edge[0], right_edge[0]);
/* Move DQS (back to orig). */
scc_mgr_apply_group_dm_out1_delay(mid);
writel(0, &sdr_scc_mgr->update);
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
__func__, __LINE__, left_edge[0], right_edge[0],
mid, dm_margin);
/* Export values. */
gbl->fom_out += dq_margin + dqs_margin;
- debug_cond(DLEVEL == 2,
+ debug_cond(DLEVEL >= 2,
"%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
__func__, __LINE__, dq_margin, dqs_margin, dm_margin);
static int run_mem_calibrate(void)
{
int pass;
+ u32 ctrl_cfg;
debug("%s:%d\n", __func__, __LINE__);
writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
/* Stop tracking manager. */
- clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+ ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
+ writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
+ &sdr_ctrl->ctrl_cfg);
phy_mgr_initialize();
rw_mgr_mem_initialize();
writel(0x2, &phy_mgr_cfg->mux_sel);
/* Start tracking manager. */
- setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
return pass;
}
printf("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
rwcfg->mem_virtual_groups_per_read_dqs,
rwcfg->mem_virtual_groups_per_write_dqs);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
- debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
+ debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
- debug_cond(DLEVEL == 1,
+ debug_cond(DLEVEL >= 1,
"max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
- debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
+ debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
iocfg->io_out2_delay_max);
- debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
+ debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
hc_initialize_rom_data();
#define REG_EN_CTL_ENABLE (1 << 7)
struct pm8916_gpio_bank {
- uint16_t pid; /* Peripheral ID on SPMI bus */
+ uint32_t pid; /* Peripheral ID on SPMI bus */
};
static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
*/
#include <common.h>
+#include <dm.h>
#include <i2c.h>
+#include <pci.h>
#include <asm/io.h>
#include "designware_i2c.h"
-static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
-{
- switch (adap->hwadapnr) {
-#if CONFIG_SYS_I2C_BUS_MAX >= 4
- case 3:
- return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
+struct dw_scl_sda_cfg {
+ u32 ss_hcnt;
+ u32 fs_hcnt;
+ u32 ss_lcnt;
+ u32 fs_lcnt;
+ u32 sda_hold;
+};
+
+#ifdef CONFIG_X86
+/* BayTrail HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg byt_config = {
+ .ss_hcnt = 0x200,
+ .fs_hcnt = 0x55,
+ .ss_lcnt = 0x200,
+ .fs_lcnt = 0x99,
+ .sda_hold = 0x6,
+};
#endif
-#if CONFIG_SYS_I2C_BUS_MAX >= 3
- case 2:
- return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
-#endif
-#if CONFIG_SYS_I2C_BUS_MAX >= 2
- case 1:
- return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
-#endif
- case 0:
- return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
- default:
- printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
- }
- return NULL;
+struct dw_i2c {
+ struct i2c_regs *regs;
+ struct dw_scl_sda_cfg *scl_sda_cfg;
+};
+
+static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+{
+ u32 ena = enable ? IC_ENABLE_0B : 0;
+ int timeout = 100;
+
+ do {
+ writel(ena, &i2c_base->ic_enable);
+ if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
+ return;
+
+ /*
+ * Wait 10 times the signaling period of the highest I2C
+ * transfer supported by the driver (for 400KHz this is
+ * 25us) as described in the DesignWare I2C databook.
+ */
+ udelay(25);
+ } while (timeout--);
+
+ printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
}
/*
- * set_speed - Set the i2c speed mode (standard, high, fast)
- * @i2c_spd: required i2c speed mode
+ * i2c_set_bus_speed - Set the i2c speed
+ * @speed: required i2c speed
*
- * Set the i2c speed mode (standard, high, fast)
+ * Set the i2c speed.
*/
-static void set_speed(struct i2c_adapter *adap, int i2c_spd)
+static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
+ struct dw_scl_sda_cfg *scl_sda_cfg,
+ unsigned int speed)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned int cntl;
unsigned int hcnt, lcnt;
- unsigned int enbl;
+ int i2c_spd;
+
+ if (speed >= I2C_MAX_SPEED)
+ i2c_spd = IC_SPEED_MODE_MAX;
+ else if (speed >= I2C_FAST_SPEED)
+ i2c_spd = IC_SPEED_MODE_FAST;
+ else
+ i2c_spd = IC_SPEED_MODE_STANDARD;
/* to set speed cltr must be disabled */
- enbl = readl(&i2c_base->ic_enable);
- enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_base->ic_enable);
+ dw_i2c_enable(i2c_base, false);
cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
switch (i2c_spd) {
+#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
case IC_SPEED_MODE_MAX:
- cntl |= IC_CON_SPD_HS;
- hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ cntl |= IC_CON_SPD_SS;
+ if (scl_sda_cfg) {
+ hcnt = scl_sda_cfg->fs_hcnt;
+ lcnt = scl_sda_cfg->fs_lcnt;
+ } else {
+ hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
+ }
writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
- lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
break;
+#endif
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
- hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ if (scl_sda_cfg) {
+ hcnt = scl_sda_cfg->ss_hcnt;
+ lcnt = scl_sda_cfg->ss_lcnt;
+ } else {
+ hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
+ }
writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
- lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
break;
case IC_SPEED_MODE_FAST:
default:
cntl |= IC_CON_SPD_FS;
- hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ if (scl_sda_cfg) {
+ hcnt = scl_sda_cfg->fs_hcnt;
+ lcnt = scl_sda_cfg->fs_lcnt;
+ } else {
+ hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
+ lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
+ }
writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
- lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
break;
}
writel(cntl, &i2c_base->ic_con);
- /* Enable back i2c now speed set */
- enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_base->ic_enable);
-}
-
-/*
- * i2c_set_bus_speed - Set the i2c speed
- * @speed: required i2c speed
- *
- * Set the i2c speed.
- */
-static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
-{
- int i2c_spd;
-
- if (speed >= I2C_MAX_SPEED)
- i2c_spd = IC_SPEED_MODE_MAX;
- else if (speed >= I2C_FAST_SPEED)
- i2c_spd = IC_SPEED_MODE_FAST;
- else
- i2c_spd = IC_SPEED_MODE_STANDARD;
+ /* Configure SDA Hold Time if required */
+ if (scl_sda_cfg)
+ writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
- set_speed(adap, i2c_spd);
- adap->speed = speed;
+ /* Enable back i2c now speed set */
+ dw_i2c_enable(i2c_base, true);
return 0;
}
-/*
- * i2c_init - Init function
- * @speed: required i2c speed
- * @slaveaddr: slave address for the device
- *
- * Initialization function.
- */
-static void dw_i2c_init(struct i2c_adapter *adap, int speed,
- int slaveaddr)
-{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
- unsigned int enbl;
-
- /* Disable i2c */
- enbl = readl(&i2c_base->ic_enable);
- enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_base->ic_enable);
-
- writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
- writel(IC_RX_TL, &i2c_base->ic_rx_tl);
- writel(IC_TX_TL, &i2c_base->ic_tx_tl);
- dw_i2c_set_bus_speed(adap, speed);
- writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
- writel(slaveaddr, &i2c_base->ic_sar);
-
- /* Enable i2c */
- enbl = readl(&i2c_base->ic_enable);
- enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_base->ic_enable);
-}
-
/*
* i2c_setaddress - Sets the target slave address
* @i2c_addr: target i2c address
*
* Sets the target slave address.
*/
-static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
+static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
- unsigned int enbl;
-
/* Disable i2c */
- enbl = readl(&i2c_base->ic_enable);
- enbl &= ~IC_ENABLE_0B;
- writel(enbl, &i2c_base->ic_enable);
+ dw_i2c_enable(i2c_base, false);
writel(i2c_addr, &i2c_base->ic_tar);
/* Enable i2c */
- enbl = readl(&i2c_base->ic_enable);
- enbl |= IC_ENABLE_0B;
- writel(enbl, &i2c_base->ic_enable);
+ dw_i2c_enable(i2c_base, true);
}
/*
*
* Flushes the i2c RX FIFO
*/
-static void i2c_flush_rxfifo(struct i2c_adapter *adap)
+static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
-
while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
readl(&i2c_base->ic_cmd_data);
}
*
* Waits for bus busy
*/
-static int i2c_wait_for_bb(struct i2c_adapter *adap)
+static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned long start_time_bb = get_timer(0);
while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
return 0;
}
-static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
+static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
int alen)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
-
- if (i2c_wait_for_bb(adap))
+ if (i2c_wait_for_bb(i2c_base))
return 1;
- i2c_setaddress(adap, chip);
+ i2c_setaddress(i2c_base, chip);
while (alen) {
alen--;
/* high byte address going out first */
return 0;
}
-static int i2c_xfer_finish(struct i2c_adapter *adap)
+static int i2c_xfer_finish(struct i2c_regs *i2c_base)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
ulong start_stop_det = get_timer(0);
while (1) {
}
}
- if (i2c_wait_for_bb(adap)) {
+ if (i2c_wait_for_bb(i2c_base)) {
printf("Timed out waiting for bus\n");
return 1;
}
- i2c_flush_rxfifo(adap);
+ i2c_flush_rxfifo(i2c_base);
return 0;
}
*
* Read from i2c memory.
*/
-static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
- int alen, u8 *buffer, int len)
+static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
unsigned long start_time_rx;
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
addr);
#endif
- if (i2c_xfer_init(adap, dev, addr, alen))
+ if (i2c_xfer_init(i2c_base, dev, addr, alen))
return 1;
start_time_rx = get_timer(0);
}
}
- return i2c_xfer_finish(adap);
+ return i2c_xfer_finish(i2c_base);
}
/*
*
* Write to i2c memory.
*/
-static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
- int alen, u8 *buffer, int len)
+static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
{
- struct i2c_regs *i2c_base = i2c_get_base(adap);
int nb = len;
unsigned long start_time_tx;
addr);
#endif
- if (i2c_xfer_init(adap, dev, addr, alen))
+ if (i2c_xfer_init(i2c_base, dev, addr, alen))
return 1;
start_time_tx = get_timer(0);
}
}
- return i2c_xfer_finish(adap);
+ return i2c_xfer_finish(i2c_base);
+}
+
+/*
+ * __dw_i2c_init - Init function
+ * @speed: required i2c speed
+ * @slaveaddr: slave address for the device
+ *
+ * Initialization function.
+ */
+static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
+{
+ /* Disable i2c */
+ dw_i2c_enable(i2c_base, false);
+
+ writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
+ writel(IC_RX_TL, &i2c_base->ic_rx_tl);
+ writel(IC_TX_TL, &i2c_base->ic_tx_tl);
+ writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
+#ifndef CONFIG_DM_I2C
+ __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
+ writel(slaveaddr, &i2c_base->ic_sar);
+#endif
+
+ /* Enable i2c */
+ dw_i2c_enable(i2c_base, true);
}
+#ifndef CONFIG_DM_I2C
/*
- * i2c_probe - Probe the i2c chip
+ * The legacy I2C functions. These need to get removed once
+ * all users of this driver are converted to DM.
*/
+static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
+{
+ switch (adap->hwadapnr) {
+#if CONFIG_SYS_I2C_BUS_MAX >= 4
+ case 3:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 3
+ case 2:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
+#endif
+#if CONFIG_SYS_I2C_BUS_MAX >= 2
+ case 1:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
+#endif
+ case 0:
+ return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+ default:
+ printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
+ }
+
+ return NULL;
+}
+
+static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
+ unsigned int speed)
+{
+ adap->speed = speed;
+ return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
+}
+
+static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
+{
+ __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
+}
+
+static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
+{
+ return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
+}
+
+static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
+ int alen, u8 *buffer, int len)
+{
+ return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
+}
+
+/* dw_i2c_probe - Probe the i2c chip */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
+ struct i2c_regs *i2c_base = i2c_get_base(adap);
u32 tmp;
int ret;
/*
* Try to read the first location of the chip.
*/
- ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
+ ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
if (ret)
dw_i2c_init(adap, adap->speed, adap->slaveaddr);
dw_i2c_write, dw_i2c_set_bus_speed,
CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif
+
+#else /* CONFIG_DM_I2C */
+/* The DM I2C functions */
+
+static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
+ int nmsgs)
+{
+ struct dw_i2c *i2c = dev_get_priv(bus);
+ int ret;
+
+ debug("i2c_xfer: %d messages\n", nmsgs);
+ for (; nmsgs > 0; nmsgs--, msg++) {
+ debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
+ if (msg->flags & I2C_M_RD) {
+ ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
+ msg->buf, msg->len);
+ } else {
+ ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
+ msg->buf, msg->len);
+ }
+ if (ret) {
+ debug("i2c_write: error sending\n");
+ return -EREMOTEIO;
+ }
+ }
+
+ return 0;
+}
+
+static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+ struct dw_i2c *i2c = dev_get_priv(bus);
+
+ return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
+}
+
+static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+ uint chip_flags)
+{
+ struct dw_i2c *i2c = dev_get_priv(bus);
+ struct i2c_regs *i2c_base = i2c->regs;
+ u32 tmp;
+ int ret;
+
+ /* Try to read the first location of the chip */
+ ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
+ if (ret)
+ __dw_i2c_init(i2c_base, 0, 0);
+
+ return ret;
+}
+
+static int designware_i2c_probe(struct udevice *bus)
+{
+ struct dw_i2c *priv = dev_get_priv(bus);
+
+ if (device_is_on_pci_bus(bus)) {
+#ifdef CONFIG_DM_PCI
+ /* Save base address from PCI BAR */
+ priv->regs = (struct i2c_regs *)
+ dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+#ifdef CONFIG_X86
+ /* Use BayTrail specific timing values */
+ priv->scl_sda_cfg = &byt_config;
+#endif
+#endif
+ } else {
+ priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
+ }
+
+ __dw_i2c_init(priv->regs, 0, 0);
+
+ return 0;
+}
+
+static int designware_i2c_bind(struct udevice *dev)
+{
+ static int num_cards;
+ char name[20];
+
+ /* Create a unique device name for PCI type devices */
+ if (device_is_on_pci_bus(dev)) {
+ /*
+ * ToDo:
+ * Setting req_seq in the driver is probably not recommended.
+ * But without a DT alias the number is not configured. And
+ * using this driver is impossible for PCIe I2C devices.
+ * This can be removed, once a better (correct) way for this
+ * is found and implemented.
+ */
+ dev->req_seq = num_cards;
+ sprintf(name, "i2c_designware#%u", num_cards++);
+ device_set_name(dev, name);
+ }
+
+ return 0;
+}
+
+static const struct dm_i2c_ops designware_i2c_ops = {
+ .xfer = designware_i2c_xfer,
+ .probe_chip = designware_i2c_probe_chip,
+ .set_bus_speed = designware_i2c_set_bus_speed,
+};
+
+static const struct udevice_id designware_i2c_ids[] = {
+ { .compatible = "snps,designware-i2c" },
+ { }
+};
+
+U_BOOT_DRIVER(i2c_designware) = {
+ .name = "i2c_designware",
+ .id = UCLASS_I2C,
+ .of_match = designware_i2c_ids,
+ .bind = designware_i2c_bind,
+ .probe = designware_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct dw_i2c),
+ .ops = &designware_i2c_ops,
+};
+
+#ifdef CONFIG_X86
+static struct pci_device_id designware_pci_supported[] = {
+ /* Intel BayTrail has 7 I2C controller located on the PCI bus */
+ { PCI_VDEVICE(INTEL, 0x0f41) },
+ { PCI_VDEVICE(INTEL, 0x0f42) },
+ { PCI_VDEVICE(INTEL, 0x0f43) },
+ { PCI_VDEVICE(INTEL, 0x0f44) },
+ { PCI_VDEVICE(INTEL, 0x0f45) },
+ { PCI_VDEVICE(INTEL, 0x0f46) },
+ { PCI_VDEVICE(INTEL, 0x0f47) },
+ {},
+};
+
+U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
+#endif
+
+#endif /* CONFIG_DM_I2C */
#define __DW_I2C_H_
struct i2c_regs {
- u32 ic_con;
- u32 ic_tar;
- u32 ic_sar;
- u32 ic_hs_maddr;
- u32 ic_cmd_data;
- u32 ic_ss_scl_hcnt;
- u32 ic_ss_scl_lcnt;
- u32 ic_fs_scl_hcnt;
- u32 ic_fs_scl_lcnt;
- u32 ic_hs_scl_hcnt;
- u32 ic_hs_scl_lcnt;
- u32 ic_intr_stat;
- u32 ic_intr_mask;
- u32 ic_raw_intr_stat;
- u32 ic_rx_tl;
- u32 ic_tx_tl;
- u32 ic_clr_intr;
- u32 ic_clr_rx_under;
- u32 ic_clr_rx_over;
- u32 ic_clr_tx_over;
- u32 ic_clr_rd_req;
- u32 ic_clr_tx_abrt;
- u32 ic_clr_rx_done;
- u32 ic_clr_activity;
- u32 ic_clr_stop_det;
- u32 ic_clr_start_det;
- u32 ic_clr_gen_call;
- u32 ic_enable;
- u32 ic_status;
- u32 ic_txflr;
- u32 ix_rxflr;
- u32 reserved_1;
- u32 ic_tx_abrt_source;
+ u32 ic_con; /* 0x00 */
+ u32 ic_tar; /* 0x04 */
+ u32 ic_sar; /* 0x08 */
+ u32 ic_hs_maddr; /* 0x0c */
+ u32 ic_cmd_data; /* 0x10 */
+ u32 ic_ss_scl_hcnt; /* 0x14 */
+ u32 ic_ss_scl_lcnt; /* 0x18 */
+ u32 ic_fs_scl_hcnt; /* 0x1c */
+ u32 ic_fs_scl_lcnt; /* 0x20 */
+ u32 ic_hs_scl_hcnt; /* 0x24 */
+ u32 ic_hs_scl_lcnt; /* 0x28 */
+ u32 ic_intr_stat; /* 0x2c */
+ u32 ic_intr_mask; /* 0x30 */
+ u32 ic_raw_intr_stat; /* 0x34 */
+ u32 ic_rx_tl; /* 0x38 */
+ u32 ic_tx_tl; /* 0x3c */
+ u32 ic_clr_intr; /* 0x40 */
+ u32 ic_clr_rx_under; /* 0x44 */
+ u32 ic_clr_rx_over; /* 0x48 */
+ u32 ic_clr_tx_over; /* 0x4c */
+ u32 ic_clr_rd_req; /* 0x50 */
+ u32 ic_clr_tx_abrt; /* 0x54 */
+ u32 ic_clr_rx_done; /* 0x58 */
+ u32 ic_clr_activity; /* 0x5c */
+ u32 ic_clr_stop_det; /* 0x60 */
+ u32 ic_clr_start_det; /* 0x64 */
+ u32 ic_clr_gen_call; /* 0x68 */
+ u32 ic_enable; /* 0x6c */
+ u32 ic_status; /* 0x70 */
+ u32 ic_txflr; /* 0x74 */
+ u32 ic_rxflr; /* 0x78 */
+ u32 ic_sda_hold; /* 0x7c */
+ u32 ic_tx_abrt_source; /* 0x80 */
+ u8 res1[0x18]; /* 0x84 */
+ u32 ic_enable_status; /* 0x9c */
};
#if !defined(IC_CLK)
--- /dev/null
+#
+# Memory devices
+#
+
+menu "Memory Controller drivers"
+
+config TI_AEMIF
+ tristate "Texas Instruments AEMIF driver"
+ depends on ARCH_KEYSTONE
+ help
+ This driver is for the AEMIF module available in Texas Instruments
+ SoCs. AEMIF stands for Asynchronous External Memory Interface and
+ is intended to provide a glue-less interface to a variety of
+ asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
+ of 256M bytes of any of these memories can be accessed at a given
+ time via four chip selects with 64M byte access per chip select.
+
+endmenu
struct mmc_config *cfg;
int val;
- priv->base_addr = (struct hsmmc *)dev_get_addr(dev);
+ priv->base_addr = map_physmem(dev_get_addr(dev), sizeof(struct hsmmc *),
+ MAP_NOCACHE);
cfg = &priv->cfg;
cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
if (mmc == NULL)
return -1;
+#ifdef OMAP_HSMMC_USE_GPIO
+ gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
+ gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
+#endif
+
upriv->mmc = mmc;
return 0;
INIT_LIST_HEAD(&ubi->pq[i]);
ubi->pq_head = 0;
+ ubi->free_count = 0;
list_for_each_entry_safe(aeb, tmp, &ai->erase, u.list) {
cond_resched();
found_pebs++;
}
- ubi->free_count = 0;
list_for_each_entry(aeb, &ai->free, u.list) {
cond_resched();
#define REG_MASK 0xFF
struct pm8916_priv {
- uint16_t usid; /* Slave ID on SPMI bus */
+ uint32_t usid; /* Slave ID on SPMI bus */
};
static int pm8916_reg_count(struct udevice *dev)
if (input) {
WATCHDOG_RESET();
- return lsr & BCM283X_MU_LSR_RX_READY;
+ return (lsr & BCM283X_MU_LSR_RX_READY) ? 1 : 0;
} else {
- return !(lsr & BCM283X_MU_LSR_TX_IDLE);
+ return (lsr & BCM283X_MU_LSR_TX_IDLE) ? 0 : 1;
}
}
source "drivers/usb/host/Kconfig"
+source "drivers/usb/dwc3/Kconfig"
+
source "drivers/usb/musb-new/Kconfig"
source "drivers/usb/emul/Kconfig"
--- /dev/null
+config USB_DWC3
+ bool "DesignWare USB3 DRD Core Support"
+ depends on (USB && USB_GADGET)
+ select USB_GADGET_DUALSPEED
+ help
+ Say Y here if your system has a Dual Role SuperSpeed
+ USB controller based on the DesignWare USB3 IP Core.
+
+if USB_DWC3
+
+choice
+ bool "DWC3 Mode Selection"
+
+config USB_DWC3_HOST
+ bool "Host only mode"
+ depends on USB
+ help
+ Select this when you want to use DWC3 in host mode only,
+ thereby the gadget feature will be regressed.
+
+config USB_DWC3_GADGET
+ bool "Gadget only mode"
+ depends on USB_GADGET
+ help
+ Select this when you want to use DWC3 in gadget mode only,
+ thereby the host feature will be regressed.
+
+endchoice
+
+comment "Platform Glue Driver Support"
+
+config USB_DWC3_OMAP
+ bool "Texas Instruments OMAP5 and similar Platforms"
+ help
+ Some platforms from Texas Instruments like OMAP5, DRA7xxx and
+ AM437x use this IP for USB2/3 functionality.
+
+ Say 'Y' here if you have one such device
+
+menu "PHY Subsystem"
+
+config USB_DWC3_PHY_OMAP
+ bool "TI OMAP SoC series USB DRD PHY driver"
+ help
+ Enable single driver for both USB2 PHY programming and USB3 PHY
+ programming for TI SoCs.
+
+config USB_DWC3_PHY_SAMSUNG
+ bool "Exynos5 SoC series USB DRD PHY driver"
+ help
+ Enable USB DRD PHY support for Exynos 5 SoC series.
+ This driver provides PHY interface for USB 3.0 DRD controller
+ present on Exynos5 SoC series.
+
+endmenu
+
+endif
a USB peripheral device. Configure one hardware driver for your
peripheral/device side bus controller, and a "gadget driver" for
your peripheral protocol.
+
+if USB_GADGET
+
+config USB_GADGET_ATMEL_USBA
+ bool "Atmel USBA"
+ select USB_GADGET_DUALSPEED
+ help
+ USBA is the integrated high-speed USB Device controller on
+ the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel.
+
+config USB_GADGET_DWC2_OTG
+ bool "DesignWare USB2.0 HS OTG controller (gadget mode)"
+ select USB_GADGET_DUALSPEED
+ help
+ The Designware USB2.0 high-speed gadget controller
+ integrated into many SoCs. Select this option if you want the
+ driver to operate in Peripheral mode. This option requires
+ USB_GADGET to be enabled.
+
+config CI_UDC
+ bool "ChipIdea device controller"
+ select USB_GADGET_DUALSPEED
+ help
+ Say Y here to enable device controller functionality of the
+ ChipIdea driver.
+
+config USB_GADGET_VBUS_DRAW
+ int "Maximum VBUS Power usage (2-500 mA)"
+ range 2 500
+ default 2
+ help
+ Some devices need to draw power from USB when they are
+ configured, perhaps to operate circuitry or to recharge
+ batteries. This is in addition to any local power supply,
+ such as an AC adapter or batteries.
+
+ Enter the maximum power your device draws through USB, in
+ milliAmperes. The permitted range of values is 2 - 500 mA;
+ 0 mA would be legal, but can make some hosts misbehave.
+
+ This value will be used except for system-specific gadget
+ drivers that have more specific information.
+
+# Selected by UDC drivers that support high-speed operation.
+config USB_GADGET_DUALSPEED
+ bool
+
+config USB_GADGET_DOWNLOAD
+ bool "Enable USB download gadget"
+ help
+ Composite USB download gadget support (g_dnl) for download functions.
+ This code works on top of composite gadget.
+
+if USB_GADGET_DOWNLOAD
+
+config G_DNL_MANUFACTURER
+ string "Vendor name of USB device"
+
+config G_DNL_VENDOR_NUM
+ hex "Vendor ID of USB device"
+
+config G_DNL_PRODUCT_NUM
+ hex "Product ID of USB device"
+
+endif # USB_GADGET_DOWNLOAD
+
+endif # USB_GADGET
* CONFIG_G_DNL_VENDOR_NUM
* CONFIG_G_DNL_PRODUCT_NUM
* CONFIG_G_DNL_MANUFACTURER
- * at e.g. ./include/configs/<board>.h
+ * at e.g. ./configs/<board>_defconfig
*/
#define STRING_MANUFACTURER 25
.bDescriptorType = USB_DT_DEVICE,
.bcdUSB = __constant_cpu_to_le16(0x0200),
- .bDeviceClass = USB_CLASS_COMM,
- .bDeviceSubClass = 0x02, /*0x02:CDC-modem , 0x00:CDC-serial*/
+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
+ .bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/
.idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM),
.idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM),
config USB_MUSB_GADGET
bool "MUSB gadget mode support"
+ select USB_GADGET_DUALSPEED
help
Enables the MUSB USB dual-role controller in gadget mode.
#define INODE_LOCKED_MAX 64
struct super_block *ubifs_sb;
-LIST_HEAD(super_blocks);
static struct inode *inodes_locked_down[INODE_LOCKED_MAX];
s->s_type = type;
#ifndef __UBOOT__
strlcpy(s->s_id, type->name, sizeof(s->s_id));
+ list_add_tail(&s->s_list, &super_blocks);
#else
strncpy(s->s_id, type->name, sizeof(s->s_id));
#endif
- list_add_tail(&s->s_list, &super_blocks);
hlist_add_head(&s->s_instances, &type->fs_supers);
#ifndef __UBOOT__
spin_unlock(&sb_lock);
#endif
#ifdef BOOTEFI_NAME
+#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64)
+/*
+ * On 32bit ARM systems there is a reasonable number of systems that follow
+ * the $soc-$board$boardver.dtb name scheme for their device trees. Use that
+ * scheme if we don't have an explicit fdtfile variable.
+ */
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \
+ "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \
+ "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \
+ "fi; "
+#else
+#define BOOTENV_EFI_SET_FDTFILE_FALLBACK
+#endif
+
+
#define BOOTENV_SHARED_EFI \
"boot_efi_binary=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${kernel_addr_r} efi/boot/"BOOTEFI_NAME"; " \
- "bootefi ${kernel_addr_r}\0" \
+ "if fdt addr ${fdt_addr_r}; then " \
+ "bootefi ${kernel_addr_r} ${fdt_addr_r};" \
+ "else" \
+ "bootefi ${kernel_addr_r} ${fdtcontroladdr};" \
+ "fi\0" \
\
"load_efi_dtb=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
- "${fdt_addr_r} ${prefix}${fdtfile}; " \
- "fdt addr ${fdt_addr_r}\0" \
+ "${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \
\
"efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \
"scan_dev_for_efi=" \
+ "setenv efi_fdtfile ${fdtfile}; " \
+ BOOTENV_EFI_SET_FDTFILE_FALLBACK \
"for prefix in ${efi_dtb_prefixes}; do " \
"if test -e ${devtype} " \
"${devnum}:${distro_bootpart} " \
- "${prefix}${fdtfile}; then " \
+ "${prefix}${efi_fdtfile}; then " \
"run load_efi_dtb; " \
"fi;" \
"done;" \
"efi/boot/"BOOTEFI_NAME"; " \
"run boot_efi_binary; " \
"echo EFI LOAD FAILED: continuing...; " \
- "fi; \0"
+ "fi; " \
+ "setenv efi_fdtfile\0"
#define SCAN_DEV_FOR_EFI "run scan_dev_for_efi;"
#else
#define BOOTENV_SHARED_EFI
#define CONFIG_MENU
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
+#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
#endif /* CONFIG_DM_ETH */
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#endif /* CONFIG_USB_MUSB_GADGET */
/*
#endif /* CONFIG_USB_MUSB_HOST */
#ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#endif /* CONFIG_USB_MUSB_GADGET */
#define CONFIG_AM437X_USB2PHY2_HOST
#endif
-/* USB GADGET */
-#if !defined(CONFIG_SPL_BUILD) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT))
-#define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
-#define CONFIG_USB_DWC3_GADGET
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_USB_GADGET_DUALSPEED
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USBETH_SUPPORT)
+#undef CONFIG_USB_DWC3_PHY_OMAP
+#undef CONFIG_USB_DWC3_OMAP
+#undef CONFIG_USB_DWC3
+#undef CONFIG_USB_DWC3_GADGET
+
+#undef CONFIG_USB_GADGET_DOWNLOAD
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#undef CONFIG_G_DNL_MANUFACTURER
+#undef CONFIG_G_DNL_VENDOR_NUM
+#undef CONFIG_G_DNL_PRODUCT_NUM
+#undef CONFIG_USB_GADGET_DUALSPEED
#endif
/*
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#endif /* CONFIG_USB_MUSB_GADGET */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#ifdef CONFIG_USB_MUSB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-
-/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#endif /* CONFIG_USB_MUSB_GADGET */
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
#define CONFIG_BAUDRATE 115200
-#define CONFIG_ENV_SIZE 0x10000
-#define CONFIG_ENV_IS_NOWHERE
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (0x00011a00 * 512)
+#define CONFIG_ENV_SIZE (8 * 512)
#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - SZ_1M)
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
-#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USBID_ADDR 0x34052c46
-#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 /* google */
-#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 /* nexus one */
-#define CONFIG_G_DNL_MANUFACTURER "Broadcom Corporation"
#endif /* __BCM28155_AP_H */
#define CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "Congatec"
/* USB Device Firmware Update support */
#define CONFIG_CMD_DFU
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT3
#define CONFIG_CMD_EXT4
#define CONFIG_DOS_PARTITION
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* USB Client Support */
-#define CONFIG_CI_UDC
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_TRDX_VID 0x1B67
#define CONFIG_TRDX_PID_COLIBRI_VF50 0x0016
#define CONFIG_TRDX_PID_COLIBRI_VF61 0x0017
#define CONFIG_TRDX_PID_COLIBRI_VF61IT 0x0018
#define CONFIG_TRDX_PID_COLIBRI_VF50IT 0x0019
-#define CONFIG_G_DNL_MANUFACTURER "Toradex"
-#define CONFIG_G_DNL_VENDOR_NUM CONFIG_TRDX_VID
-#define CONFIG_G_DNL_PRODUCT_NUM CONFIG_TRDX_PID_COLIBRI_VF50
/* USB DFU */
-#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_CMD_DFU
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_NAND
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
-
/* DFU class support */
#define CONFIG_CMD_DFU
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_NAND
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-/* USB DFU IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
-
#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
-/* USB GADGET */
-#define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
-#define CONFIG_USB_DWC3_GADGET
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_USB_GADGET_DUALSPEED
-
/* USB Device Firmware Update support */
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_RAM
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
/* UART */
#define CONFIG_BAUDRATE 115200
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"linux_image=Image\0" \
- "linux_addr=0x81000000\0"\
- "fdt_image=apq8016-sbc.dtb\0" \
- "fdt_addr=0x83000000\0"\
- "ramdisk_addr=0x84000000\0"\
+ "kernel_addr_r=0x81000000\0"\
+ "fdtfile=apq8016-sbc.dtb\0" \
+ "fdt_addr_r=0x83000000\0"\
+ "ramdisk_addr_r=0x84000000\0"\
BOOTENV
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_CMD_DFU
#define CONFIG_CMD_GPT
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET_DOWNLOAD
-
/* TIZEN THOR downloader support */
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_USB_FUNCTION_THOR
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
"else echo U-Boot not downloaded..exiting;fi\0" \
"bootcmd=run net_nfs\0"
-/* Enable FIT images support */
-#define CONFIG_CMD_FDT
-
#endif /* __CONFIG_H */
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_OF_LIBFDT
-
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_KEYBOARD
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_NETCONSOLE
/* USB Mass Storage Gadget */
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-/* Netchip IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "Gateworks"
/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_VERSION_VARIABLE
#define CONFIG_IMAGE_FORMAT_LEGACY
-#define CONFIG_CMD_FDT
#define CONFIG_CMD_HASH
#define CONFIG_SHA1
#define CONFIG_SHA256
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_OMAP2PLUS
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-
-/*
- * Download
- */
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-
/*
* Fastboot
*/
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-/* attention! not only for gadget, enables also highspeed in hostmode */
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#define CONFIG_AM335X_USB1
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
-#define CONFIG_OF_LIBFDT
/*
* Linux Information
*/
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_EXT3
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#define CONFIG_USB_STORAGE
/* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "DENX"
#define CONFIG_LOADADDR 0x20800000
#define CONFIG_BOOTCOMMAND "run mmc_mmc"
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_OF_LIBFDT
/*
* Extra Environments
#define CONFIG_IMX_VIDEO_SKIP
#ifndef CONFIG_SPL
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "FSL"
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_IMX_THERMAL
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "FSL"
/* USB Device Firmware Update support */
#define CONFIG_CMD_DFU
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_NETCONSOLE
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-/* Netchip IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "Boundary"
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* Gadget part */
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_NETCONSOLE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_EXYNOS
-/* DWC3 */
-#define CONFIG_USB_DWC3
-#define CONFIG_USB_DWC3_GADGET
-#define CONFIG_USB_DWC3_PHY_SAMSUNG
-
-/* USB gadget */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-/* Downloader */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
-#define CONFIG_USB_GADGET_DOWNLOAD
-
/* DFU */
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_I2C_NOPROBES {{0x0, 0x0}}
/* USB */
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_TWL4030_USB 1
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_G_DNL_MANUFACTURER "TI"
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
/* USB */
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETHER_RNDIS
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_G_DNL_MANUFACTURER "TI"
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
-/* USB GADGET */
-#define CONFIG_USB_DWC3_PHY_OMAP
-#define CONFIG_USB_DWC3_OMAP
-#define CONFIG_USB_DWC3
-#define CONFIG_USB_DWC3_GADGET
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
-#define CONFIG_USB_GADGET_DUALSPEED
-
/* USB Device Firmware Update support */
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_RAM
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-/*
- * Handover flattened device tree (dtb file) to Linux kernel
- */
-#define CONFIG_OF_LIBFDT 1
-
/*-----------------------------------------------------------------------
* SDHC Configuration
*/
#define CONFIG_CMD_GPT
/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define CONFIG_USB_FUNCTION_THOR
/* USB Samsung's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
-#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
-#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+
+#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_G_DNL_MANUFACTURER "Samsung"
/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
#define MTDIDS_DEFAULT "onenand0=samsung-onenand"
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_MAX_I2C_BUS 7
-#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8998
-#define CONFIG_USB_GADGET_DWC2_OTG
#define CONFIG_USB_GADGET_DWC2_OTG_PHY
-#define CONFIG_USB_GADGET_DUALSPEED
/*
* SPI Settings
#endif
/* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D2 XPlained"
#endif
/* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
#endif
/* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
#endif
/* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D4EK"
#define CONFIG_SANDBOX_BITS_PER_LONG 64
#define CONFIG_LMB
-#define CONFIG_CMD_FDT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_CMD_PCI
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
-#define CONFIG_USB_GADGET_DUALSPEED
-
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_NETCONSOLE
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_USB_MUSB_GADGET
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
#undef CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USB_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
#endif /* CONFIG_USB_MUSB_GADGET */
-#define CONFIG_USB_GADGET_DOWNLOAD
-
/* USB DRACO ID as default */
#define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
/* USB Device Firmware Update support */
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_ENV
-/* Enable Device-Tree (FDT) support */
-#define CONFIG_CMD_FDT
-
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
#define CONFIG_CMD_DFU
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_NAND
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-/* USB DFU IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
-
#define CONFIG_SYS_CACHELINE_SIZE 0x2000
#endif
# undef CONFIG_CMD_NFS
#endif /* CONFIG_MACB */
-#define CONFIG_CMD_FDT
-
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x301000
#define CONFIG_SPL_STACK_R
#define CONFIG_USB_MUSB_OMAP2PLUS
#define CONFIG_TWL4030_USB
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-
-/*
- * Download
- */
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-
-#define CONFIG_G_DNL_VENDOR_NUM 0x0451
-#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
-
/*
* Fastboot
*/
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_USB_GADGET_DWC2_OTG
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-/* USB Composite download gadget - g_dnl */
-#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_FUNCTION_DFU
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
-#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
-#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
-#ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR
-#endif
+#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
#endif
/*
#define CONFIG_SYS_THUMB_BUILD
/*#define CONFIG_SYS_NO_FLASH*/
-#define CONFIG_OF_LIBFDT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_FLASH_BASE 0x08000000
#endif
#ifdef CONFIG_USB_MUSB_GADGET
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-
-#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#endif
-#ifdef CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_G_DNL_VENDOR_NUM 0x1f3a
-#define CONFIG_G_DNL_PRODUCT_NUM 0x1010
-#define CONFIG_G_DNL_MANUFACTURER "Allwinner Technology"
-#endif
-
#ifdef CONFIG_USB_FUNCTION_DFU
#define CONFIG_CMD_DFU
#define CONFIG_DFU_RAM
#define CONFIG_CMD_DFU
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_NAND
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-/* USB DFU IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0908
-#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
-#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
-
#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#endif
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
#ifdef CONFIG_CMD_USB_MASS_STORAGE
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 0
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "TBS"
#endif /* CONFIG_CMD_USB_MASS_STORAGE */
#define CONFIG_USB_KEYBOARD
#ifdef CONFIG_USB_KEYBOARD
#ifndef CONFIG_SPL_BUILD
/* USB gadget mode support*/
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_CI_UDC
#define CONFIG_CI_UDC_HAS_HOSTPC
-#define CONFIG_USB_GADGET_DUALSPEED
-#ifndef CONFIG_G_DNL_VENDOR_NUM
-#define CONFIG_G_DNL_VENDOR_NUM 0x0955
-#endif
-#ifndef CONFIG_G_DNL_PRODUCT_NUM
-#define CONFIG_G_DNL_PRODUCT_NUM 0x701A
-#endif
-#ifndef CONFIG_G_DNL_MANUFACTURER
-#define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
-#endif
-#define CONFIG_USB_GADGET_DOWNLOAD
/* USB mass storage protocol */
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES
-/* AEMIF */
-#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
/* I2C Configuration */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_SF
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_USB_MUSB_PIO_ONLY
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-/* attention! not only for gadget, enables also highspeed in hostmode */
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#define CONFIG_AM335X_USB1
#endif
/* USB device */
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_ATMEL_USBA
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_MANUFACTURER "L+G VInCo"
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */
#endif
-#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
-#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "FSL"
#define CONFIG_CMD_DFU
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
-#define CONFIG_USB_GADGET_DUALSPEED
-
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_CDC
#define CONFIG_NETCONSOLE
#define CONFIG_SYS_NO_FLASH
#endif
-#define CONFIG_OF_LIBFDT 1
#define CONFIG_BAUDRATE 115200
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_USB_STORAGE
#define CONFIG_USB_XHCI_ZYNQMP
-#define CONFIG_USB_DWC3
-#define CONFIG_USB_DWC3_GADGET
-
-#define CONFIG_USB_GADGET_DOWNLOAD
-#define CONFIG_USB_GADGET_DUALSPEED
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
-#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_RAM
-#define CONFIG_G_DNL_VENDOR_NUM 0x03FD
-#define CONFIG_G_DNL_PRODUCT_NUM 0x0300
-#define CONFIG_G_DNL_MANUFACTURER "Xilinx"
#define CONFIG_USB_CABLE_CHECK
#define CONFIG_CMD_DFU
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_SYS_MMC_ENV_PART 1 /* boot parition */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */
-#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_CACHE
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_LZMA /* LZMA compression support */
-#define CONFIG_OF_LIBFDT
/*
* Serial Console Configuration
# define CONFIG_EHCI_IS_TDI
# define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
-# define CONFIG_USB_GADGET_DUALSPEED
-# define CONFIG_USB_GADGET_DOWNLOAD
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_USB_FUNCTION_DFU
# define CONFIG_DFU_RAM
-# define CONFIG_USB_GADGET_VBUS_DRAW 2
-# define CONFIG_G_DNL_VENDOR_NUM 0x03FD
-# define CONFIG_G_DNL_PRODUCT_NUM 0x0300
-# define CONFIG_G_DNL_MANUFACTURER "Xilinx"
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_DFU
# define CONFIG_CMD_THOR_DOWNLOAD
*/
fdt_addr_t dev_get_addr(struct udevice *dev);
+/**
+ * dev_get_addr_ptr() - Return pointer to the address of the reg property
+ * of a device
+ *
+ * @dev: Pointer to a device
+ *
+ * @return Pointer to addr, or NULL if there is no such property
+ */
+void *dev_get_addr_ptr(struct udevice *dev);
+
/**
* dev_get_addr_index() - Get the indexed reg property of a device
*
struct efi_device_path_file_path {
struct efi_device_path dp;
- u16 str[16];
+ u16 str[32];
};
#define BLOCK_IO_GUID \
/* Call this to relocate the runtime section to an address space */
void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
/* Call this to set the current device name */
-void efi_set_bootdev(const char *dev, const char *devnr);
+void efi_set_bootdev(const char *dev, const char *devnr, const char *path);
/* Generic EFI memory allocator, call this to get memory */
void *efi_alloc(uint64_t len, int memory_type);
/* No loader configured, stub out EFI_ENTRY */
static inline void efi_restore_gd(void) { }
-static inline void efi_set_bootdev(const char *dev, const char *devnr) { }
+static inline void efi_set_bootdev(const char *dev, const char *devnr,
+ const char *path) { }
#endif
struct efi_block_io_media media;
/* EFI device path to this block device */
struct efi_device_path_file_path *dp;
+ /* Offset into disk for simple partitions */
+ lbaint_t offset;
};
static efi_status_t efi_disk_open_block(void *handle, efi_guid_t *protocol,
return EFI_EXIT(EFI_DEVICE_ERROR);
blksz = desc->blksz;
blocks = buffer_size / blksz;
+ lba += diskobj->offset;
#ifdef DEBUG_EFI
printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
.flush_blocks = &efi_disk_flush_blocks,
};
+static void efi_disk_add_dev(char *name,
+ const struct block_drvr *cur_drvr,
+ const struct blk_desc *desc,
+ int dev_index,
+ lbaint_t offset)
+{
+ struct efi_disk_obj *diskobj;
+ struct efi_device_path_file_path *dp;
+ int objlen = sizeof(*diskobj) + (sizeof(*dp) * 2);
+
+ diskobj = calloc(1, objlen);
+
+ /* Fill in object data */
+ diskobj->parent.protocols[0].guid = &efi_block_io_guid;
+ diskobj->parent.protocols[0].open = efi_disk_open_block;
+ diskobj->parent.protocols[1].guid = &efi_guid_device_path;
+ diskobj->parent.protocols[1].open = efi_disk_open_dp;
+ diskobj->parent.handle = diskobj;
+ diskobj->ops = block_io_disk_template;
+ diskobj->ifname = cur_drvr->name;
+ diskobj->dev_index = dev_index;
+ diskobj->offset = offset;
+
+ /* Fill in EFI IO Media info (for read/write callbacks) */
+ diskobj->media.removable_media = desc->removable;
+ diskobj->media.media_present = 1;
+ diskobj->media.block_size = desc->blksz;
+ diskobj->media.io_align = desc->blksz;
+ diskobj->media.last_block = desc->lba;
+ diskobj->ops.media = &diskobj->media;
+
+ /* Fill in device path */
+ dp = (void*)&diskobj[1];
+ diskobj->dp = dp;
+ dp[0].dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
+ dp[0].dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH;
+ dp[0].dp.length = sizeof(*dp);
+ ascii2unicode(dp[0].str, name);
+
+ dp[1].dp.type = DEVICE_PATH_TYPE_END;
+ dp[1].dp.sub_type = DEVICE_PATH_SUB_TYPE_END;
+ dp[1].dp.length = sizeof(*dp);
+
+ /* Hook up to the device list */
+ list_add_tail(&diskobj->parent.link, &efi_obj_list);
+}
+
+static int efi_disk_create_eltorito(struct blk_desc *desc,
+ const struct block_drvr *cur_drvr,
+ int diskid)
+{
+ int disks = 0;
+#ifdef CONFIG_ISO_PARTITION
+ char devname[32] = { 0 }; /* dp->str is u16[32] long */
+ disk_partition_t info;
+ int part = 1;
+
+ if (desc->part_type != PART_TYPE_ISO)
+ return 0;
+
+ while (!part_get_info(desc, part, &info)) {
+ snprintf(devname, sizeof(devname), "%s%d:%d", cur_drvr->name,
+ diskid, part);
+ efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
+ part++;
+ disks++;
+ }
+#endif
+
+ return disks;
+}
+
/*
* U-Boot doesn't have a list of all online disk devices. So when running our
* EFI payload, we scan through all of the potentially available ones and
printf("Scanning disks on %s...\n", cur_drvr->name);
for (i = 0; i < 4; i++) {
struct blk_desc *desc;
- struct efi_disk_obj *diskobj;
- struct efi_device_path_file_path *dp;
- int objlen = sizeof(*diskobj) + (sizeof(*dp) * 2);
- char devname[16] = { 0 }; /* dp->str is u16[16] long */
+ char devname[32] = { 0 }; /* dp->str is u16[32] long */
desc = blk_get_dev(cur_drvr->name, i);
if (!desc)
if (desc->type == DEV_TYPE_UNKNOWN)
continue;
- diskobj = calloc(1, objlen);
-
- /* Fill in object data */
- diskobj->parent.protocols[0].guid = &efi_block_io_guid;
- diskobj->parent.protocols[0].open = efi_disk_open_block;
- diskobj->parent.protocols[1].guid = &efi_guid_device_path;
- diskobj->parent.protocols[1].open = efi_disk_open_dp;
- diskobj->parent.handle = diskobj;
- diskobj->ops = block_io_disk_template;
- diskobj->ifname = cur_drvr->name;
- diskobj->dev_index = i;
-
- /* Fill in EFI IO Media info (for read/write callbacks) */
- diskobj->media.removable_media = desc->removable;
- diskobj->media.media_present = 1;
- diskobj->media.block_size = desc->blksz;
- diskobj->media.io_align = desc->blksz;
- diskobj->media.last_block = desc->lba;
- diskobj->ops.media = &diskobj->media;
-
- /* Fill in device path */
- dp = (void*)&diskobj[1];
- diskobj->dp = dp;
- dp[0].dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE;
- dp[0].dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH;
- dp[0].dp.length = sizeof(*dp);
snprintf(devname, sizeof(devname), "%s%d",
cur_drvr->name, i);
- ascii2unicode(dp[0].str, devname);
-
- dp[1].dp.type = DEVICE_PATH_TYPE_END;
- dp[1].dp.sub_type = DEVICE_PATH_SUB_TYPE_END;
- dp[1].dp.length = sizeof(*dp);
-
- /* Hook up to the device list */
- list_add_tail(&diskobj->parent.link, &efi_obj_list);
+ efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
disks++;
+
+ /*
+ * El Torito images show up as block devices
+ * in an EFI world, so let's create them here
+ */
+ disks += efi_disk_create_eltorito(desc, cur_drvr, i);
}
}
printf("Found %d disks\n", disks);
switch (type) {
case 0:
/* Any page */
- addr = efi_find_free_memory(len, gd->ram_top);
+ addr = efi_find_free_memory(len, gd->start_addr_sp);
if (!addr) {
r = EFI_NOT_FOUND;
break;
uint32_t *descriptor_version)
{
ulong map_size = 0;
+ int map_entries = 0;
struct list_head *lhandle;
list_for_each(lhandle, &efi_mem)
- map_size += sizeof(struct efi_mem_desc);
+ map_entries++;
+
+ map_size = map_entries * sizeof(struct efi_mem_desc);
*memory_map_size = map_size;
/* Copy list into array */
if (memory_map) {
+ /* Return the list in ascending order */
+ memory_map = &memory_map[map_entries - 1];
list_for_each(lhandle, &efi_mem) {
struct efi_mem_list *lmem;
lmem = list_entry(lhandle, struct efi_mem_list, link);
*memory_map = lmem->desc;
- memory_map++;
+ memory_map--;
}
}
int efi_memory_init(void)
{
- uint64_t runtime_start, runtime_end, runtime_pages;
- uint64_t uboot_start, uboot_pages;
- uint64_t uboot_stack_size = 16 * 1024 * 1024;
+ unsigned long runtime_start, runtime_end, runtime_pages;
+ unsigned long uboot_start, uboot_pages;
+ unsigned long uboot_stack_size = 16 * 1024 * 1024;
int i;
/* Add RAM */
static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_device_error(void);
static efi_status_t EFI_RUNTIME_TEXT EFIAPI efi_invalid_parameter(void);
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define EFI_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+#else
+/* Just use the greatest cache flush alignment requirement I'm aware of */
+#define EFI_CACHELINE_SIZE 128
+#endif
+
#if defined(CONFIG_ARM64)
#define R_RELATIVE 1027
#define R_MASK 0xffffffffULL
#endif
*p = newaddr;
- flush_dcache_range((ulong)p, (ulong)&p[1]);
+ flush_dcache_range((ulong)p & ~(EFI_CACHELINE_SIZE - 1),
+ ALIGN((ulong)&p[1], EFI_CACHELINE_SIZE));
}
#ifndef IS_RELA
gzwrite_progress(iteration++,
totalfilled,
szexpected);
- blocks_written = dev->block_write(dev, outblock,
- writeblocks,
- writebuf);
+ blocks_written = blk_dwrite(dev, outblock,
+ writeblocks, writebuf);
outblock += blocks_written;
if (ctrlc()) {
puts("abort\n");
projects / u-boot / commitdiff