]> git.sur5r.net Git - u-boot/commitdiff
armv8/ls1043aqds: Add support for >2GB memory
authorShaohui Xie <Shaohui.Xie@freescale.com>
Mon, 4 Jan 2016 03:03:44 +0000 (11:03 +0800)
committerYork Sun <york.sun@nxp.com>
Mon, 25 Jan 2016 16:24:14 +0000 (08:24 -0800)
This patch also exposes the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
board/freescale/ls1043aqds/ddr.c
board/freescale/ls1043aqds/ls1043aqds.c
include/configs/ls1043aqds.h

index 42d906824ae5423196eca8ca6e3e309446c99284..3d3c53385a12c838b0229de1e03ca71e3e58a3c8 100644 (file)
@@ -132,9 +132,22 @@ void dram_init_banksize(void)
         * The address needs to add the offset of its bank.
         */
        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-       gd->bd->bi_dram[0].size = gd->ram_size;
+       if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                                         CONFIG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-       gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
-       gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+               gd->secure_ram = gd->bd->bi_dram[1].start +
+                                gd->secure_ram -
+                                CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 #endif
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
+               gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       }
 }
index d6696ca8120abd80051a78391e8c35f47f5f071d..576fa46226268992c57e6cfd3d6e5312e15101cf 100644 (file)
@@ -303,6 +303,16 @@ int board_init(void)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+       u64 base[CONFIG_NR_DRAM_BANKS];
+       u64 size[CONFIG_NR_DRAM_BANKS];
+
+       /* fixup DT for the two DDR banks */
+       base[0] = gd->bd->bi_dram[0].start;
+       size[0] = gd->bd->bi_dram[0].size;
+       base[1] = gd->bd->bi_dram[1].start;
+       size[1] = gd->bd->bi_dram[1].size;
+
+       fdt_fixup_memory_banks(blob, base, size, 2);
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
index 398f1c3f7723bec6f2758515a5bd2fe5faff3622..02247b3342bc84796db033128795314cebfca634 100644 (file)
@@ -33,7 +33,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL   4
-#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_NR_DRAM_BANKS           2
 
 #define CONFIG_DDR_SPD
 #define SPD_EEPROM_ADDRESS             0x51