ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite

The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.

This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index f823117687e70fc27bb083894a6515ee1ba2e7df..4e47ab395b4ff22de9ec1589fac93b574ed669c8 100644 (file)
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * (C) Copyright 2006
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <ppc440.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -362,8 +363,8 @@ int checkboard(void)
        printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-       rev = in8(CFG_BCSR_BASE + 0);
-       val = in8(CFG_BCSR_BASE + 5) & 0x01;
+       rev = in_8((void *)(CFG_BCSR_BASE + 0));
+       val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
        printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
        if (s != NULL) {

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 912f09ee4395b62c52f25fa12ecda59d6ecd8e00..6ec922ab0074a74c796ea05ab052fca64d09ded7 100644 (file)
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,6 +24,7 @@
 #include <common.h>
 #include <ppc4xx.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <spd_sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -181,8 +184,8 @@ int checkboard(void)
        printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 #endif
 
-       rev = *(u8 *)(CFG_CPLD + 0);
-       val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+       rev = in_8((void *)(CFG_BCSR_BASE + 0));
+       val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
        printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
        if (s != NULL) {

diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index c2e1386217f9dcda7f28ea8162ba0da016316062..600f98cf0d40525fa758057d8a273664f3dec8a1 100644 (file)
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -450,6 +450,8 @@
 #define CFG_EBC_PB2AP          0x24814580
 #define CFG_EBC_PB2CR          (CFG_BCSR_BASE | 0x38000)
 
+#define CFG_BCSR5_PCI66EN      0x80
+
 /*-----------------------------------------------------------------------
  * NAND FLASH
  *----------------------------------------------------------------------*/

diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h
index 6a5b7f1eaacd4b38e07d22f56757e22a784c57e3..35bce4af904905075a9e7c37e2650756eb5b6162 100644 (file)
--- a/include/configs/yosemite.h
+++ b/include/configs/yosemite.h
@@ -359,6 +359,8 @@
 #define CFG_EBC_PB2AP          0x04814500
 #define CFG_EBC_PB2CR          (CFG_CPLD | 0x18000)
 
+#define CFG_BCSR5_PCI66EN      0x80
+
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */