s5pc1xx: support the GPIO interface

This patch adds support the GPIO interface and update the README file.

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 4f922e686afeec24ef1e20da9f6516408c200046..7290c2f522378f78f829b5b5be22c1e079c3cb35 100644 (file)
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -33,6 +33,7 @@ SOBJS += reset.o
 
 COBJS  += clock.o
 COBJS  += cpu_info.o
+COBJS  += gpio.o
 COBJS  += timer.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)

diff --git a/cpu/arm_cortexa8/s5pc1xx/gpio.c b/cpu/arm_cortexa8/s5pc1xx/gpio.c
new file mode 100644 (file)
index 0000000..a97244b
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/gpio.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+#define CON_MASK(x)            (0xf << ((x) << 2))
+#define CON_SFR(x, v)          ((v) << ((x) << 2))
+
+#define DAT_MASK(x)            (0x1 << (x))
+#define DAT_SET(x)             (0x1 << (x))
+
+#define PULL_MASK(x)           (0x3 << ((x) << 1))
+#define PULL_MODE(x, v)                ((v) << ((x) << 1))
+
+#define DRV_MASK(x)            (0x3 << ((x) << 1))
+#define DRV_SET(x, m)          ((m) << ((x) << 1))
+#define RATE_MASK(x)           (0x1 << (x + 16))
+#define RATE_SET(x)            (0x1 << (x + 16))
+
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
+{
+       unsigned int value;
+
+       value = readl(&bank->con);
+       value &= ~CON_MASK(gpio);
+       value |= CON_SFR(gpio, cfg);
+       writel(value, &bank->con);
+}
+
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+       unsigned int value;
+
+       gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+
+       value = readl(&bank->dat);
+       value &= ~DAT_MASK(gpio);
+       if (en)
+               value |= DAT_SET(gpio);
+       writel(value, &bank->dat);
+}
+
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+       gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+}
+
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+       unsigned int value;
+
+       value = readl(&bank->dat);
+       value &= ~DAT_MASK(gpio);
+       if (en)
+               value |= DAT_SET(gpio);
+       writel(value, &bank->dat);
+}
+
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+       unsigned int value;
+
+       value = readl(&bank->dat);
+       return !!(value & DAT_MASK(gpio));
+}
+
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->pull);
+       value &= ~PULL_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_PULL_DOWN:
+       case GPIO_PULL_UP:
+               value |= PULL_MODE(gpio, mode);
+               break;
+       default:
+               return;
+       }
+
+       writel(value, &bank->pull);
+}
+
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->drv);
+       value &= ~DRV_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_DRV_1X:
+       case GPIO_DRV_2X:
+       case GPIO_DRV_3X:
+       case GPIO_DRV_4X:
+               value |= DRV_SET(gpio, mode);
+               break;
+       default:
+               return;
+       }
+
+       writel(value, &bank->drv);
+}
+
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+       unsigned int value;
+
+       value = readl(&bank->drv);
+       value &= ~RATE_MASK(gpio);
+
+       switch (mode) {
+       case GPIO_DRV_FAST:
+       case GPIO_DRV_SLOW:
+               value |= RATE_SET(gpio);
+               break;
+       default:
+               return;
+       }
+
+       writel(value, &bank->drv);
+}

diff --git a/doc/README.s5pc1xx b/doc/README.s5pc1xx
index 5a0fe33db1bd8649f9d169d4cb87575ee2bf663e..ab1f02469c5d5ca46e9b76c86d3b89318202da97 100644 (file)
--- a/doc/README.s5pc1xx
+++ b/doc/README.s5pc1xx
@@ -41,7 +41,23 @@ To check SoC:
                printf("cpu is s5pc110\n");
 
 gpio
-       not supported yet.
+
+       struct s5pc100_gpio *gpio = (struct s5pc100_gpio*)S5PC100_GPIO_BASE;
+
+       /* GPA[0] pin set to irq */
+       gpio_cfg_pin(&gpio->gpio_a, 0, GPIO_IRQ);
+
+       /* GPA[0] pin set to input */
+       gpio_direction_input(&gpio->gpio_a, 0);
+
+       /* GPA[0] pin set to output/high */
+       gpio_direction_output(&gpio->gpio_a, 0, 1);
+
+       /* GPA[0] value set to low */
+       gpio_set_value(&gpio->gpio_a, 0, 0);
+
+       /* get GPA[0] value */
+       value = gpio_get_value(&gpio->gpio_a, 0);
 
 Links
 =====

diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h
index afbc7ea5ae5a8d3d572621b56a1014cb93460953..8e4bb863f9cab9fc6b7b398953e17ccbbbf68bbc 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/gpio.h
+++ b/include/asm-arm/arch-s5pc1xx/gpio.h
@@ -124,6 +124,35 @@ struct s5pc110_gpio {
        struct s5pc1xx_gpio_bank gpio_h2;
        struct s5pc1xx_gpio_bank gpio_h3;
 };
+
+/* functions */
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg);
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio);
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio);
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
 #endif
 
+/* Pin configurations */
+#define GPIO_INPUT     0x0
+#define GPIO_OUTPUT    0x1
+#define GPIO_IRQ       0xf
+#define GPIO_FUNC(x)   (x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE 0x0
+#define GPIO_PULL_DOWN 0x1
+#define GPIO_PULL_UP   0x2
+
+/* Drive Strength level */
+#define GPIO_DRV_1X    0x0
+#define GPIO_DRV_2X    0x1
+#define GPIO_DRV_3X    0x2
+#define GPIO_DRV_4X    0x3
+#define GPIO_DRV_FAST  0x0
+#define GPIO_DRV_SLOW  0x1
+
 #endif