Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
case MIDR_CORTEX_A9_R1P3:
*omap4_revision = OMAP4430_ES2_3;
break;
+ case MIDR_CORTEX_A9_R2P10:
+ *omap4_revision = OMAP4460_ES1_0;
+ break;
default:
*omap4_revision = OMAP4430_SILICON_ID_INVALID;
break;
#define OMAP4430_ES2_1 0x44300210
#define OMAP4430_ES2_2 0x44300220
#define OMAP4430_ES2_3 0x44300230
+#define OMAP4460_ES1_0 0x44600100
/* ROM code defines */
/* Boot device */
#define MIDR_CORTEX_A9_R0P1 0x410FC091
#define MIDR_CORTEX_A9_R1P2 0x411FC092
#define MIDR_CORTEX_A9_R1P3 0x411FC093
+#define MIDR_CORTEX_A9_R2P10 0x412FC09A
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0