#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
+/* USB CTRL Base Address */
+#define USB1_CTRL 0x44e10628
+#define USB1_CTRL_CM_PWRDN BIT(0)
+#define USB1_CTRL_OTG_PWRDN BIT(1)
+
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
#define DDR_PHY_DATA_ADDR 0x44E120C8
void usb_phy_power(int on)
{
- return;
+ u32 val;
+
+ /* USB1_CTRL */
+ val = readl(USB1_CTRL);
+ if (on) {
+ /*
+ * these bits are re-used on AM437x to power up/down the USB
+ * CM and OTG PHYs, if we don't toggle them, USB will not be
+ * functional on newer silicon revisions
+ */
+ val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN);
+ } else {
+ val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN;
+ }
+
+ writel(val, USB1_CTRL);
}
#endif /* CONFIG_AM437X_USB2PHY2_HOST */