]> git.sur5r.net Git - u-boot/commitdiff
hrcon: Add fan controllers
authorDirk Eibach <dirk.eibach@gdsys.cc>
Wed, 28 Oct 2015 10:46:36 +0000 (11:46 +0100)
committerTom Rini <trini@konsulko.com>
Thu, 12 Nov 2015 23:04:10 +0000 (18:04 -0500)
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
board/gdsys/common/Makefile
board/gdsys/common/fanctrl.c [new file with mode: 0644]
board/gdsys/common/fanctrl.h [new file with mode: 0644]
board/gdsys/mpc8308/hrcon.c
board/gdsys/mpc8308/strider.c
drivers/i2c/soft_i2c.c
include/configs/hrcon.h

index 0aa1849758612ea3f2edbeef8ce318a6cda9fc85..ce230455c84c8b919bc8c2d8ec584d9649ecb376 100644 (file)
@@ -12,6 +12,7 @@ obj-$(CONFIG_IO64) += miiphybb.o
 obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
 obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
 obj-$(CONFIG_CONTROLCENTERD) += dp501.o
-obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o
+obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
 obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
+obj-$(CONFIG_STRIDER) += fanctrl.o
 obj-$(CONFIG_STRIDER_CON) += osd.o
diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c
new file mode 100644 (file)
index 0000000..44569bb
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+enum {
+       FAN_CONFIG = 0x03,
+       FAN_TACHLIM_LSB = 0x48,
+       FAN_TACHLIM_MSB = 0x49,
+       FAN_PWM_FREQ = 0x4D,
+};
+
+void init_fan_controller(u8 addr)
+{
+       int val;
+
+       /* set PWM Frequency to 2.5% resolution */
+       i2c_reg_write(addr, FAN_PWM_FREQ, 20);
+
+       /* set Tachometer Limit */
+       i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
+       i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
+
+       /* enable Tach input */
+       val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
+       i2c_reg_write(addr, FAN_CONFIG, val);
+}
diff --git a/board/gdsys/common/fanctrl.h b/board/gdsys/common/fanctrl.h
new file mode 100644 (file)
index 0000000..12bc850
--- /dev/null
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2015
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _FANCTRL_H_
+#define _FANCTRL_H_
+
+void init_fan_controller(u8 addr);
+
+#endif
index 3cc03cbdade987bf9249cc0088d02367b28d4f16..880b6387de29c9139d1792fc93754dd578678179 100644 (file)
@@ -26,6 +26,7 @@
 #include "../common/osd.h"
 #include "../common/mclink.h"
 #include "../common/phy.h"
+#include "../common/fanctrl.h"
 
 #include <pca953x.h>
 #include <pca9698.h>
@@ -52,6 +53,11 @@ enum {
 unsigned int mclink_fpgacount;
 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
 
+struct {
+       u8 bus;
+       u8 addr;
+} hrcon_fans[] = CONFIG_HRCON_FANS;
+
 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
 {
        int res;
@@ -199,6 +205,11 @@ int last_stage_init(void)
                }
        }
 
+       for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
+               i2c_set_bus_num(hrcon_fans[k].bus);
+               init_fan_controller(hrcon_fans[k].addr);
+       }
+
        return 0;
 }
 
index 8e5d5de8f788e23233d2d77b7372aeb972c2eed7..ef5b6c03f8ccc21075552087aec9ee27fa383eae 100644 (file)
@@ -28,6 +28,7 @@
 #include "../common/mclink.h"
 #include "../common/osd.h"
 #include "../common/phy.h"
+#include "../common/fanctrl.h"
 
 #include <pca953x.h>
 #include <pca9698.h>
@@ -51,13 +52,6 @@ enum {
        GPIO_MDIO = 1 << 15,
 };
 
-enum {
-       FAN_CONFIG = 0x03,
-       FAN_TACHLIM_LSB = 0x48,
-       FAN_TACHLIM_MSB = 0x49,
-       FAN_PWM_FREQ = 0x4D,
-};
-
 unsigned int mclink_fpgacount;
 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
 
@@ -128,22 +122,6 @@ int checkboard(void)
        return 0;
 }
 
-static void init_fan_controller(u8 addr)
-{
-       int val;
-
-       /* set PWM Frequency to 2.5% resolution */
-       i2c_reg_write(addr, FAN_PWM_FREQ, 20);
-
-       /* set Tachometer Limit */
-       i2c_reg_write(addr, FAN_TACHLIM_LSB, 0x10);
-       i2c_reg_write(addr, FAN_TACHLIM_MSB, 0x0a);
-
-       /* enable Tach input */
-       val = i2c_reg_read(addr, FAN_CONFIG) | 0x04;
-       i2c_reg_write(addr, FAN_CONFIG, val);
-}
-
 int last_stage_init(void)
 {
        int slaves;
index b000a0ec029bc9a47a5990b41971a456a0872950..5ffc974479db2f4747ef12748632c2e9d2926249 100644 (file)
@@ -501,3 +501,31 @@ U_BOOT_I2C_ADAP_COMPLETE(soft7, soft_i2c_init, soft_i2c_probe,
                         CONFIG_SYS_I2C_SOFT_SLAVE_8,
                         7)
 #endif
+#if defined(I2C_SOFT_DECLARATIONS9)
+U_BOOT_I2C_ADAP_COMPLETE(soft8, soft_i2c_init, soft_i2c_probe,
+                        soft_i2c_read, soft_i2c_write, NULL,
+                        CONFIG_SYS_I2C_SOFT_SPEED_9,
+                        CONFIG_SYS_I2C_SOFT_SLAVE_9,
+                        8)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS10)
+U_BOOT_I2C_ADAP_COMPLETE(soft9, soft_i2c_init, soft_i2c_probe,
+                        soft_i2c_read, soft_i2c_write, NULL,
+                        CONFIG_SYS_I2C_SOFT_SPEED_10,
+                        CONFIG_SYS_I2C_SOFT_SLAVE_10,
+                        9)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS11)
+U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe,
+                        soft_i2c_read, soft_i2c_write, NULL,
+                        CONFIG_SYS_I2C_SOFT_SPEED_11,
+                        CONFIG_SYS_I2C_SOFT_SLAVE_11,
+                        10)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS12)
+U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe,
+                        soft_i2c_read, soft_i2c_write, NULL,
+                        CONFIG_SYS_I2C_SOFT_SPEED_12,
+                        CONFIG_SYS_I2C_SOFT_SLAVE_12,
+                        11)
+#endif
index 16d5885e3797a7c894ec1cf390b512c38a96bea4..84d0928a6787b8c3eca0767b5beb1eef0a886b66 100644 (file)
 #define I2C_SOFT_DECLARATIONS4
 #define CONFIG_SYS_I2C_SOFT_SPEED_4            50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4            0x7F
-
-#ifdef CONFIG_HRCON_DH
 #define I2C_SOFT_DECLARATIONS5
 #define CONFIG_SYS_I2C_SOFT_SPEED_5            50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_5            0x7F
 #define I2C_SOFT_DECLARATIONS8
 #define CONFIG_SYS_I2C_SOFT_SPEED_8            50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_8            0x7F
+
+#ifdef CONFIG_HRCON_DH
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9            50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9            0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10           50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10           0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11           50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11           0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12           50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12           0x7F
 #endif
 
 #ifdef CONFIG_HRCON_DH
-#define CONFIG_SYS_ICS8N3QV01_I2C              {9, 10, 11, 12, 13, 14, 15, 16}
+#define CONFIG_SYS_ICS8N3QV01_I2C              {13, 14, 15, 16, 17, 18, 19, 20}
 #define CONFIG_SYS_DP501_I2C                   {1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_HRCON_FANS                      { {10, 0x4c}, {11, 0x4c}, \
+                                                 {12, 0x4c} }
 #else
-#define CONFIG_SYS_ICS8N3QV01_I2C              {5, 6, 7, 8}
+#define CONFIG_SYS_ICS8N3QV01_I2C              {9, 10, 11, 12}
 #define CONFIG_SYS_DP501_I2C                   {1, 2, 3, 4}
+#define CONFIG_HRCON_FANS                      { {6, 0x4c}, {7, 0x4c}, \
+                                                 {8, 0x4c} }
 #endif
 
 #ifndef __ASSEMBLY__
@@ -410,33 +426,37 @@ void fpga_control_set(unsigned int bus, int pin);
 void fpga_control_clear(unsigned int bus, int pin);
 #endif
 
+#define I2C_SDA_GPIO   ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO   ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX   (I2C_ADAP_HWNR % 4)
+
 #ifdef CONFIG_HRCON_DH
 #define I2C_ACTIVE \
        do { \
-               if (I2C_ADAP_HWNR > 3) \
-                       fpga_control_set(I2C_ADAP_HWNR, 0x0004); \
+               if (I2C_ADAP_HWNR > 7) \
+                       fpga_control_set(I2C_FPGA_IDX, 0x0004); \
                else \
-                       fpga_control_clear(I2C_ADAP_HWNR, 0x0004); \
+                       fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
        } while (0)
 #else
 #define I2C_ACTIVE     { }
 #endif
 #define I2C_TRISTATE   { }
 #define I2C_READ \
-       (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
+       (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 #define I2C_SDA(bit) \
        do { \
                if (bit) \
-                       fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
+                       fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
                else \
-                       fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
+                       fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
        } while (0)
 #define I2C_SCL(bit) \
        do { \
                if (bit) \
-                       fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
+                       fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
                else \
-                       fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+                       fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
        } while (0)
 #define I2C_DELAY      udelay(25)      /* 1/4 I2C clock duration */