* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
                 * and do not drop the Preamble.
                 */
-               fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
+               fec->eth->mii_speed = (((gd->ips_clk / 1000000) / 5) + 1) << 1;
 
                /*
                 * Reset PHY, then delay 300ns
 
        if (fdr == -1) {
                ulong best_speed = 0;
                ulong divider;
-               ulong ipb, scl;
+               ulong ips, scl;
                ulong bestmatch = 0xffffffffUL;
                int best_i = 0, best_j = 0, i, j;
                int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
                        {126, 128}
                };
 
-               ipb = gd->ipb_clk;
+               ips = gd->ips_clk;
                for (i = 7; i >= 0; i--) {
                        for (j = 7; j >= 0; j--) {
                                scl = 2 * (scltap[j].scl2tap +
                                           (SCL_Tap[i] - 1) * scltap[j].tap2tap
                                           + 2);
-                               if (ipb <= speed*scl) {
-                                       if ((speed*scl - ipb) < bestmatch) {
-                                               bestmatch = speed*scl - ipb;
+                               if (ips <= speed*scl) {
+                                       if ((speed*scl - ips) < bestmatch) {
+                                               bestmatch = speed*scl - ips;
                                                best_i = i;
                                                best_j = j;
-                                               best_speed = ipb/scl;
+                                               best_speed = ips/scl;
                                        }
                                }
                        }
 
        psc->mode = PSC_MODE_1_STOPBIT;
 
        /* calculate dividor for setting PSC CTUR and CTLR registers */
-       baseclk = (gd->ipb_clk + 8) / 16;
+       baseclk = (gd->ips_clk + 8) / 16;
        div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
 
        psc->ctur = (div >> 8) & 0xff;
 
                ips_clk = 0;
        }
 
-       gd->ipb_clk = ips_clk;
+       gd->ips_clk = ips_clk;
        gd->csb_clk = csb_clk;
        gd->cpu_clk = core_clk;
        gd->bus_clk = csb_clk;
        printf ("Clock configuration:\n");
        printf ("  CPU:                 %4d MHz\n", gd->cpu_clk / 1000000);
        printf ("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
-       printf ("  IPS Bus:             %4d MHz\n", gd->ipb_clk / 1000000);
+       printf ("  IPS Bus:             %4d MHz\n", gd->ips_clk / 1000000);
        printf ("  DDR:                 %4d MHz\n", 2 * gd->csb_clk / 1000000);
        return 0;
 }
 
        unsigned long   pci_clk;
 #endif
 #if defined(CONFIG_MPC512X)
-       u32 ipb_clk;
+       u32 ips_clk;
        u32 csb_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 
        bd->bi_vco     = gd->vco_out;
 #endif /* CONFIG_CPM2 */
 #if defined(CONFIG_MPC512X)
-       bd->bi_ipsfreq = gd->ipb_clk;
+       bd->bi_ipsfreq = gd->ips_clk;
 #endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC5xxx)
        bd->bi_ipbfreq = gd->ipb_clk;