#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for armada100 */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
/*
* defines to be used in other places
*/
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 */
/*
#ifndef __AT91SAM9X5_H__
#define __AT91SAM9X5_H__
-#define CONFIG_ARM926EJS /* ARM926EJS Core */
#define CONFIG_AT91FAMILY /* it's a member of AT91 family */
/*
#endif /* CONFIG_KW88F6281 */
#include <asm/arch/soc.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_SYS_CACHELINE_SIZE 32
/* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define _LPC32XX_CONFIG_H
/* Basic CPU architecture */
-#define CONFIG_ARM926EJS
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_NR_DRAM_BANKS_MAX 2
#include <asm/arch/pantheon.h>
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for pantheon */
#define CONFIG_SYS_CACHELINE_SIZE 32
#endif /* CONFIG_ARM1136 */
-#ifdef CONFIG_ARM926EJS
+#ifdef CONFIG_CPU_ARM926EJS
/* test and clean, page 2-23 of arm926ejs manual */
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif /* CONFIG_ARM926EJS */
+#endif /* CONFIG_CPU_ARM926EJS */
return;
}
/*
* SoC configurations
*/
-#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
-#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
+#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
#define CONFIG_MACH_TYPE 1698 /* APF27 */
#define CONFIG_SYS_GENERIC_BOARD
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_CALIMAIN
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA830_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA830 /* TI DA830 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM355 /* DM355 based board */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SOC_DM365
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Clock rates detection */
#ifndef __ASSEMBLY__
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
/* SoC Configuration */
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/*===================*/
/* SoC Configuration */
/*===================*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SOC_DM644X
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
*/
#define CONFIG_MARVELL 1
-#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
#define CONFIG_88F5182 1 /* SOC Name */
#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_HAWK
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
/*
* SoC Configuration
*/
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_MB86R0x_IOCLK get_bus_freq(0)
#define CONFIG_SYS_TEXT_BASE 0x10000000
-#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
#include <nomadik.h>
-#define CONFIG_ARM926EJS
#define CONFIG_NOMADIK_8815 /* cpu variant */
#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
+#define CONFIG_VERSATILE 1 /* This is Versatile Platform Board */
#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
#define CONFIG_SYS_MEMTEST_START 0x100000
#include <asm/arch/imx-regs.h>
-#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX25
#define CONFIG_SYS_TEXT_BASE 0xA0000000
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