Changes for U-Boot 1.0.0:
======================================================================
+* Patch by Steven Scholz, 10 Oct 2003
+ - Add support for Altera FPGA ACEX1K
+
* Patches by Thomas Lange, 09 Oct 2003:
- fix cmd_ide.c for non ppc boards (read/write functions did not
add ATA base address)
- fix for shannon board
- #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
+ - Endian swap ATA identity for all big endian CPUs, not just PPC
+ - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
+ args to linux
+ - add support for dbau1x00 board (MIPS32)
* Patch by Sangmoon Kim, 07 Oct 2003:
add support for debris board
D: ESTEEM192E support
N: Magnus Damm
-E: eramdam@kieray1.p.y.ki.era.ericsson.se
+E: damm@opensource.se
D: 8xxrom
N: Arun Dharankar
D: Port to Motorola Sandpoint 3 (MPC8240)
N: Thomas Lange
-E: thomas@corelatus.com
-D: Support for GTH board; lots of PCMCIA fixes
+E: thomas@corelatus.se
+D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
N: The LEOX team
E: team@leox.org
ZUMA MPC7xx_74xx
-Thomas Lange <thomas@corelatus.com>
+Thomas Lange <thomas@corelatus.se>
GTH MPC860
incaip MIPS32 4Kc
purple MIPS64 5Kc
+Thomas Lange <thomas@corelatus.se>
+ dbau1x00 MIPS32 Au1000
+
#########################################################################
# Nios-32 Systems: #
# #
LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
#########################################################################
-## MIPS 4Kc Systems
+## MIPS Systems
#########################################################################
LIST_mips4kc="incaip"
LIST_mips5kc="purple"
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
+LIST_au1x00="dbau1x00"
+
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
#########################################################################
## i386 Systems
@./mkconfig $(@:_config=) nios nios dk1c20
+#########################################################################
+## MIPS32 AU1000
+#########################################################################
+dbau1x00_config : unconfig
+ @./mkconfig $(@:_config=) mips mips dbau1x00
+
#########################################################################
#########################################################################
- MPC824X Family Member (if CONFIG_MPC824X is defined)
- Define exactly one of
- CONFIG_MPC8240, CONFIG_MPC8245
+ Define exactly one of
+ CONFIG_MPC8240, CONFIG_MPC8245
- 8xx CPU Options: (if using an 8xx cpu)
Define one or more of
- CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() can not work e.g.
- no 32KHz reference PIT/RTC clock
+ CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() cannot work
+ e.g. if there is no 32KHz
+ reference PIT/RTC clock
-- Clock Interface:
+- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
U-Boot stores all clock information in Hz
"clocks_in_mhz" can be defined so that U-Boot
converts clock data to MHZ before passing it to the
Linux kernel.
-
When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
"clocks_in_mhz=1" is automatically included in the
default environment.
+ CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
+
+ When transfering memsize parameter to linux, some versions
+ expect it to be in bytes, others in MB.
+ Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
+
- Console Interface:
Depending on board, define exactly one serial port
(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+SOBJS = memsetup.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+By Thomas.Lange@corelatus.se 2003-10-06
+----------------------------------------
+DbAu1000 is a development board from AMD containing
+an Alchemy AU1000 with mips32 core.
+
+Limitations & comments
+----------------------
+I assume that you set board to BIG endian!
+Little endian not tested, most probably broken.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+some day ( dbau1000, dbau1100 and dbau1500 ).
+
+I only have a dbau1000, so all testing is limited
+to this board!
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader deliviered with board.
+
+Ethernet only supported for mac0.
+
+Pcmcia only supported for slot 0, only 3.3V.
+
+Pcmcia IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+######## NOTE!!!!!! #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
+#
+
+# ROM version
+TEXT_BASE = 0xbfc00000
+
+# RAM version
+#TEXT_BASE = 0x80100000
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+long int initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+ return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN 0x0010
+#define BCSR_PCMCIA_PC0RST 0x0080
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+ u16 status;
+ volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
+ volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
+ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+ u32 proc_id;
+
+ *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+ proc_id = read_32bit_cp0_register(CP0_PRID);
+
+ switch(proc_id>>24){
+ case 0:
+ puts("Board: Merlot (DbAu1000)\n");
+ printf("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id>>8)&0xFF,proc_id&0xFF);
+ break;
+ default:
+ printf("Unsupported cpu %d, proc_id=0x%x\n",proc_id>>24,proc_id);
+ }
+#ifdef CONFIG_IDE_PCMCIA
+ /* Enable 3.3 V on slot 0 ( VCC )
+ No 5V */
+ status = 4;
+ *pcmcia_bcsr = status;
+
+ status |= BCSR_PCMCIA_PC0DRVEN;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(300*1000);
+
+ status |= BCSR_PCMCIA_PC0RST;
+ *pcmcia_bcsr = status;
+ au_sync();
+
+ udelay(100*1000);
+
+ /* PCMCIA is on a 36 bit physical address.
+ We need to map it into a 32 bit addresses */
+
+#if 0
+ /* We dont need theese unless we run whole pcmcia package */
+ write_one_tlb(20, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_IO_BASE, /* Hi */
+ 0x3C000017, /* Lo0 */
+ 0x3C200017); /* Lo1 */
+
+ write_one_tlb(21, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_ATTR_BASE, /* Hi */
+ 0x3D000017, /* Lo0 */
+ 0x3D200017); /* Lo1 */
+#endif
+ write_one_tlb(22, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_MEM_ADDR, /* Hi */
+ 0x3E000017, /* Lo0 */
+ 0x3E200017); /* Lo1 */
+
+ /* Release reset of ethernet PHY chips */
+ /* Always do this, because linux does not know about it */
+ *phy = 3;
+
+ return 0;
+#endif
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ printf ("Skipping flash_init\n");
+ return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ printf ("write_buff not implemented\n");
+ return (-1);
+}
--- /dev/null
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+
+ .globl memsetup
+memsetup:
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
+
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 8 /* 96 MHz */
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+/* SDCS 0,1 SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x005522AA
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR0
+ li t1, 0x001003F8
+ sw t1, 0(t0)
+
+
+ li t0, MEM_SDADDR1
+ li t1, 0x001023F8
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x64000C24 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x66000C24 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD1
+ li t1, 0x00000033
+ sw t1, 0(t0)
+ sync
+
+ /* Static memory controller */
+
+ /* RCE0 AMD 29LV640M MirrorBit Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00000003
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME0
+ li t1, 0x22080b20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11E03F80
+ sw t1, 0(t0)
+
+ /* RCE1 CPLD Board Logic */
+ li t0, MEM_STCFG1
+ li t1, 0x00000080
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x22080a20
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10c03f00
+ sw t1, 0(t0)
+
+ /* RCE3 PCMCIA 250ns */
+ li t0, MEM_STCFG3
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+
+ li t0, MEM_STTIME3
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ sync
+
+ j ra
+ nop
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+ .sdata : { *(.sdata) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h> /* core U-Boot definitions */
+#include <ACEX1K.h> /* ACEX device family */
+
+#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
+
+/* Define FPGA_DEBUG to get debug printf's */
+/* #define FPGA_DEBUG */
+
+#ifdef FPGA_DEBUG
+#define PRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#undef CFG_FPGA_CHECK_BUSY
+#define CFG_FPGA_PROG_FEEDBACK
+
+/* Note: The assumption is that we cannot possibly run fast enough to
+ * overrun the device (the Slave Parallel mode can free run at 50MHz).
+ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * the board config file to slow things down.
+ */
+#ifndef CONFIG_FPGA_DELAY
+#define CONFIG_FPGA_DELAY()
+#endif
+
+#ifndef CFG_FPGA_WAIT
+#define CFG_FPGA_WAIT 100
+#endif
+
+static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
+static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
+/* static int ACEX1K_ps_info( Altera_desc *desc ); */
+static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset );
+
+/* ------------------------------------------------------------------------- */
+/* ACEX1K Generic Implementation */
+int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL;
+
+ switch (desc->iface) {
+ case passive_serial:
+ PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
+ ret_val = ACEX1K_ps_load (desc, buf, bsize);
+ break;
+
+ /* Add new interface types here */
+
+ default:
+ printf ("%s: Unsupported interface type, %d\n",
+ __FUNCTION__, desc->iface);
+ }
+
+ return ret_val;
+}
+
+int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL;
+
+ switch (desc->iface) {
+ case passive_serial:
+ PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
+ ret_val = ACEX1K_ps_dump (desc, buf, bsize);
+ break;
+
+ /* Add new interface types here */
+
+ default:
+ printf ("%s: Unsupported interface type, %d\n",
+ __FUNCTION__, desc->iface);
+ }
+
+ return ret_val;
+}
+
+int ACEX1K_info( Altera_desc *desc )
+{
+ return FPGA_SUCCESS;
+}
+
+
+int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+ int ret_val = FPGA_FAIL; /* assume a failure */
+
+ if (desc->family != Altera_ACEX1K) {
+ printf ("%s: Unsupported family type, %d\n",
+ __FUNCTION__, desc->family);
+ return FPGA_FAIL;
+ } else
+ switch (desc->iface) {
+ case passive_serial:
+ ret_val = ACEX1K_ps_reloc (desc, reloc_offset);
+ break;
+
+ /* Add new interface types here */
+
+ default:
+ printf ("%s: Unsupported interface type, %d\n",
+ __FUNCTION__, desc->iface);
+ }
+
+ return ret_val;
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ACEX1K Passive Serial Generic Implementation */
+
+static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
+ int i;
+
+ PRINTF ("%s: start with interface functions @ 0x%p\n",
+ __FUNCTION__, fn);
+
+ if (fn) {
+ size_t bytecount = 0;
+ unsigned char *data = (unsigned char *) buf;
+ int cookie = desc->cookie; /* make a local copy */
+ unsigned long ts; /* timestamp */
+
+ PRINTF ("%s: Function Table:\n"
+ "ptr:\t0x%p\n"
+ "struct: 0x%p\n"
+ "config:\t0x%p\n"
+ "status:\t0x%p\n"
+ "clk:\t0x%p\n"
+ "data:\t0x%p\n"
+ "done:\t0x%p\n\n",
+ __FUNCTION__, &fn, fn, fn->config, fn->status,
+ fn->clk, fn->data, fn->done);
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);
+#endif
+
+ /*
+ * Run the pre configuration function if there is one.
+ */
+ if (*fn->pre) {
+ (*fn->pre) (cookie);
+ }
+
+ /* Establish the initial state */
+ (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
+
+ udelay(2); /* T_cfg > 2us */
+
+ /* nSTATUS should be asserted now */
+ (*fn->done) (cookie);
+ if ( !(*fn->status) (cookie) ) {
+ puts ("** nSTATUS is not asserted.\n");
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
+
+ (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */
+ udelay(2); /* T_cf2st1 < 4us */
+
+ /* Wait for nSTATUS to be released (i.e. deasserted) */
+ ts = get_timer (0); /* get current time */
+ do {
+ CONFIG_FPGA_DELAY ();
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ puts ("** Timeout waiting for STATUS to go high.\n");
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
+ (*fn->done) (cookie);
+ } while ((*fn->status) (cookie));
+
+ /* Get ready for the burn */
+ CONFIG_FPGA_DELAY ();
+
+ /* Load the data */
+ while (bytecount < bsize) {
+ unsigned char val=0;
+#ifdef CFG_FPGA_CHECK_CTRLC
+ if (ctrlc ()) {
+ (*fn->abort) (cookie);
+ return FPGA_FAIL;
+ }
+#endif
+ /* Altera detects an error if INIT goes low (active)
+ while DONE is low (inactive) */
+#if 0 /* not yet implemented */
+ if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+ puts ("** CRC error during FPGA load.\n");
+ (*fn->abort) (cookie);
+ return (FPGA_FAIL);
+ }
+#endif
+ val = data [bytecount ++ ];
+ i = 8;
+ do {
+ /* Deassert the clock */
+ (*fn->clk) (FALSE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Write data */
+ (*fn->data) ( (val & 0x01), TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ /* Assert the clock */
+ (*fn->clk) (TRUE, TRUE, cookie);
+ CONFIG_FPGA_DELAY ();
+ val >>= 1;
+ i --;
+ } while (i > 0);
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ if (bytecount % (bsize / 40) == 0)
+ putc ('.'); /* let them know we are alive */
+#endif
+ }
+
+ CONFIG_FPGA_DELAY ();
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ putc ('\n'); /* terminate the dotted line */
+#endif
+
+ /*
+ * Checking FPGA's CONF_DONE signal - correctly booted ?
+ */
+
+ if ( ! (*fn->done) (cookie) ) {
+ puts ("** Booting failed! CONF_DONE is still deasserted.\n");
+ (*fn->abort) (cookie);
+ return (FPGA_FAIL);
+ }
+
+ /*
+ * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
+ */
+
+ for (i = 0; i < 12; i++) {
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
+ }
+
+ ret_val = FPGA_SUCCESS;
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+ if (ret_val == FPGA_SUCCESS) {
+ puts ("Done.\n");
+ }
+ else {
+ puts ("Fail.\n");
+ }
+#endif
+ (*fn->post) (cookie);
+
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+}
+
+static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+ /* Readback is only available through the Slave Parallel and */
+ /* boundary-scan interfaces. */
+ printf ("%s: Passive Serial Dumping is unavailable\n",
+ __FUNCTION__);
+ return FPGA_FAIL;
+}
+
+static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+ int ret_val = FPGA_FAIL; /* assume the worst */
+ Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn =
+ (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns);
+
+ if (fn) {
+ ulong addr;
+
+ /* Get the relocated table address */
+ addr = (ulong) fn + reloc_offset;
+ fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr;
+
+ if (!fn_r->relocated) {
+
+ if (memcmp (fn_r, fn,
+ sizeof (Altera_ACEX1K_Passive_Serial_fns))
+ == 0) {
+ /* good copy of the table, fix the descriptor pointer */
+ desc->iface_fns = fn_r;
+ } else {
+ PRINTF ("%s: Invalid function table at 0x%p\n",
+ __FUNCTION__, fn_r);
+ return FPGA_FAIL;
+ }
+
+ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+ desc);
+
+ addr = (ulong) (fn->pre) + reloc_offset;
+ fn_r->pre = (Altera_pre_fn) addr;
+
+ addr = (ulong) (fn->config) + reloc_offset;
+ fn_r->config = (Altera_config_fn) addr;
+
+ addr = (ulong) (fn->status) + reloc_offset;
+ fn_r->status = (Altera_status_fn) addr;
+
+ addr = (ulong) (fn->done) + reloc_offset;
+ fn_r->done = (Altera_done_fn) addr;
+
+ addr = (ulong) (fn->clk) + reloc_offset;
+ fn_r->clk = (Altera_clk_fn) addr;
+
+ addr = (ulong) (fn->data) + reloc_offset;
+ fn_r->data = (Altera_data_fn) addr;
+
+ addr = (ulong) (fn->abort) + reloc_offset;
+ fn_r->abort = (Altera_abort_fn) addr;
+
+ addr = (ulong) (fn->post) + reloc_offset;
+ fn_r->post = (Altera_post_fn) addr;
+
+ fn_r->relocated = TRUE;
+
+ } else {
+ /* this table has already been moved */
+ /* XXX - should check to see if the descriptor is correct */
+ desc->iface_fns = fn_r;
+ }
+
+ ret_val = FPGA_SUCCESS;
+ } else {
+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+ }
+
+ return ret_val;
+
+}
+
+#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
AOBJS =
-COBJS = main.o altera.o bedbug.o \
+COBJS = main.o ACEX1K.o altera.o bedbug.o \
cmd_autoscript.o \
cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
cmd_cache.o cmd_console.o \
/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
*
*/
-/*
- * Note that this is just boilerplate - there is no Altera support yet.
- */
-
-
/*
* Altera FPGA support
*/
#include <common.h>
-#include <fpga.h> /* Generic FPGA support */
-#include <altera.h> /* Altera specific stuff */
+#include <ACEX1K.h>
-#if 0
-#define FPGA_DEBUG
-#endif
+/* Define FPGA_DEBUG to get debug printf's */
+/* #define FPGA_DEBUG */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
+/* Local Static Functions */
+static int altera_validate (Altera_desc * desc, char *fn);
+
/* ------------------------------------------------------------------------- */
int altera_load( Altera_desc *desc, void *buf, size_t bsize )
{
- printf( "No support for Altera devices yet.\n" );
- return FPGA_FAIL;
+ int ret_val = FPGA_FAIL; /* assume a failure */
+
+ if (!altera_validate (desc, __FUNCTION__)) {
+ printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+ } else {
+ switch (desc->family) {
+ case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX1K)
+ PRINTF ("%s: Launching the ACEX1K Loader...\n",
+ __FUNCTION__);
+ ret_val = ACEX1K_load (desc, buf, bsize);
+#else
+ printf ("%s: No support for ACEX1K devices.\n",
+ __FUNCTION__);
+#endif
+ break;
+
+ default:
+ printf ("%s: Unsupported family type, %d\n",
+ __FUNCTION__, desc->family);
+ }
+ }
+
+ return ret_val;
}
int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
{
- printf( "No support for Altera devices yet.\n" );
- return FPGA_FAIL;
+ int ret_val = FPGA_FAIL; /* assume a failure */
+
+ if (!altera_validate (desc, __FUNCTION__)) {
+ printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+ } else {
+ switch (desc->family) {
+ case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX)
+ PRINTF ("%s: Launching the ACEX1K Reader...\n",
+ __FUNCTION__);
+ ret_val = ACEX1K_dump (desc, buf, bsize);
+#else
+ printf ("%s: No support for ACEX1K devices.\n",
+ __FUNCTION__);
+#endif
+ break;
+
+ default:
+ printf ("%s: Unsupported family type, %d\n",
+ __FUNCTION__, desc->family);
+ }
+ }
+
+ return ret_val;
}
int altera_info( Altera_desc *desc )
{
- printf( "No support for Altera devices yet.\n" );
- return FPGA_FAIL;
+ int ret_val = FPGA_FAIL;
+
+ if (altera_validate (desc, __FUNCTION__)) {
+ printf ("Family: \t");
+ switch (desc->family) {
+ case Altera_ACEX1K:
+ printf ("ACEX1K\n");
+ break;
+ /* Add new family types here */
+ default:
+ printf ("Unknown family type, %d\n", desc->family);
+ }
+
+ printf ("Interface type:\t");
+ switch (desc->iface) {
+ case passive_serial:
+ printf ("Passive Serial (PS)\n");
+ break;
+ case passive_parallel_synchronous:
+ printf ("Passive Parallel Synchronous (PPS)\n");
+ break;
+ case passive_parallel_asynchronous:
+ printf ("Passive Parallel Asynchronous (PPA)\n");
+ break;
+ case passive_serial_asynchronous:
+ printf ("Passive Serial Asynchronous (PSA)\n");
+ break;
+ case altera_jtag_mode: /* Not used */
+ printf ("JTAG Mode\n");
+ break;
+ /* Add new interface types here */
+ default:
+ printf ("Unsupported interface type, %d\n", desc->iface);
+ }
+
+ printf ("Device Size: \t%d bytes\n"
+ "Cookie: \t0x%x (%d)\n",
+ desc->size, desc->cookie, desc->cookie);
+
+ if (desc->iface_fns) {
+ printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
+ switch (desc->family) {
+ case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX1K)
+ ACEX1K_info (desc);
+#else
+ /* just in case */
+ printf ("%s: No support for ACEX1K devices.\n",
+ __FUNCTION__);
+#endif
+ break;
+ /* Add new family types here */
+ default:
+ /* we don't need a message here - we give one up above */
+ }
+ } else {
+ printf ("No Device Function Table.\n");
+ }
+
+ ret_val = FPGA_SUCCESS;
+ } else {
+ printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+ }
+
+ return ret_val;
+}
+
+int altera_reloc( Altera_desc *desc, ulong reloc_offset)
+{
+ int ret_val = FPGA_FAIL; /* assume a failure */
+
+ if (!altera_validate (desc, __FUNCTION__)) {
+ printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+ } else {
+ switch (desc->family) {
+ case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX1K)
+ ret_val = ACEX1K_reloc (desc, reloc_offset);
+#else
+ printf ("%s: No support for ACEX devices.\n",
+ __FUNCTION__);
+#endif
+ break;
+ /* Add new family types here */
+ default:
+ printf ("%s: Unsupported family type, %d\n",
+ __FUNCTION__, desc->family);
+ }
+ }
+
+ return ret_val;
}
/* ------------------------------------------------------------------------- */
+static int altera_validate (Altera_desc * desc, char *fn)
+{
+ int ret_val = FALSE;
+
+ if (desc) {
+ if ((desc->family > min_altera_type) &&
+ (desc->family < max_altera_type)) {
+ if ((desc->iface > min_altera_iface_type) &&
+ (desc->iface < max_altera_iface_type)) {
+ if (desc->size) {
+ ret_val = TRUE;
+ } else {
+ printf ("%s: NULL part size\n", fn);
+ }
+ } else {
+ printf ("%s: Invalid Interface type, %d\n",
+ fn, desc->iface);
+ }
+ } else {
+ printf ("%s: Invalid family type, %d\n", fn, desc->family);
+ }
+ } else {
+ printf ("%s: NULL descriptor!\n", fn);
+ }
+
+ return ret_val;
+}
/* ------------------------------------------------------------------------- */
-#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
+#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
static void __inline__ ide_outb(int dev, int port, unsigned char val);
static unsigned char __inline__ ide_inb(int dev, int port);
-#ifdef __PPC__
-static void input_swap_data(int dev, ulong *sect_buf, int words);
-#endif
static void input_data(int dev, ulong *sect_buf, int words);
static void output_data(int dev, ulong *sect_buf, int words);
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
*pbuf = 0;
}
# endif /* CONFIG_AMIGAONEG3SE */
+#endif /* __PPC_ */
+/* We only need to swap data if we are running on a big endian cpu. */
+/* But Au1x00 cpu:s already swaps data in big endian mode! */
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_AU1X00)
+#define input_swap_data(x,y,z) input_data(x,y,z)
+#else
static void
input_swap_data(int dev, ulong *sect_buf, int words)
{
*dbuf++ = ld_le16(pbuf);
}
}
-#else /* ! __PPC__ */
-#define input_swap_data(x,y,z) input_data(x,y,z)
-#endif /* __PPC__ */
+#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
#ifdef __PPC__
LIB = lib$(CPU).a
START = start.o
-OBJS = interrupts.o cpu.o incaip_clock.o serial.o
+OBJS = asc_serial.o au1x00_serial.o au1x00_eth.o \
+ cpu.o interrupts.o incaip_clock.o
SOBJS = incaip_wdt.o cache.o
all: .depend $(START) $(LIB)
--- /dev/null
+/*
+ * (INCA) ASC UART support
+ */
+
+#include <config.h>
+
+#if defined(CONFIG_PURPLE) || defined(CONFIG_INCA_IP)
+
+#ifdef CONFIG_PURPLE
+#define serial_init asc_serial_init
+#define serial_putc asc_serial_putc
+#define serial_puts asc_serial_puts
+#define serial_getc asc_serial_getc
+#define serial_tstc asc_serial_tstc
+#define serial_setbrg asc_serial_setbrg
+#endif
+
+#include <common.h>
+#include <asm/inca-ip.h>
+#include "asc_serial.h"
+
+#ifdef CONFIG_PURPLE
+
+#undef ASC_FIFO_PRESENT
+#define TOUT_LOOP 100000
+
+/* Set base address for second FPI interrupt control register bank */
+#define SFPI_INTCON_BASEADDR 0xBF0F0000
+
+/* Register offset from base address */
+#define FBS_ISR 0x00000000 /* Interrupt status register */
+#define FBS_IMR 0x00000008 /* Interrupt mask register */
+#define FBS_IDIS 0x00000010 /* Interrupt disable register */
+
+/* Interrupt status register bits */
+#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */
+#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */
+#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */
+#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */
+#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */
+#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */
+
+#else
+
+#define ASC_FIFO_PRESENT
+
+#endif
+
+
+#define SET_BIT(reg, mask) reg |= (mask)
+#define CLEAR_BIT(reg, mask) reg &= (~mask)
+#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
+#define SET_BITS(reg, mask) SET_BIT(reg, mask)
+#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
+
+extern uint incaip_get_fpiclk(void);
+
+static int serial_setopt (void);
+
+/* pointer to ASC register base address */
+static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
+
+/******************************************************************************
+*
+* serial_init - initialize a INCAASC channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+#ifdef CONFIG_INCA_IP
+ /* we have to set PMU.EN13 bit to enable an ASC device*/
+ INCAASC_PMU_ENABLE(13);
+#endif
+
+ /* and we have to set CLC register*/
+ CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
+ SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
+
+ /* initialy we are in async mode */
+ pAsc->asc_con = ASCCON_M_8ASYNC;
+
+ /* select input port */
+ pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
+
+#ifdef ASC_FIFO_PRESENT
+ /* TXFIFO's filling level */
+ SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
+ ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
+ /* enable TXFIFO */
+ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
+
+ /* RXFIFO's filling level */
+ SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
+ ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
+ /* enable RXFIFO */
+ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
+#endif
+
+ /* enable error signals */
+ SET_BIT(pAsc->asc_con, ASCCON_FEN);
+ SET_BIT(pAsc->asc_con, ASCCON_OEN);
+
+#ifdef CONFIG_INCA_IP
+ /* acknowledge ASC interrupts */
+ ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
+
+ /* disable ASC interrupts */
+ ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
+#endif
+
+#ifdef ASC_FIFO_PRESENT
+ /* set FIFOs into the transparent mode */
+ SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
+ SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
+#endif
+
+ /* set baud rate */
+ serial_setbrg();
+
+ /* set the options */
+ serial_setopt();
+
+ return 0;
+}
+
+void serial_setbrg (void)
+{
+ ulong uiReloadValue, fdv;
+ ulong f_ASC;
+
+#ifdef CONFIG_INCA_IP
+ f_ASC = incaip_get_fpiclk();
+#else
+ f_ASC = ASC_CLOCK_RATE;
+#endif
+
+#ifndef INCAASC_USE_FDV
+ fdv = 2;
+ uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+ fdv = INCAASC_FDV_HIGH_BAUDRATE;
+ uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+#endif /* INCAASC_USE_FDV */
+
+ if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+ {
+#ifndef INCAASC_USE_FDV
+ fdv = 3;
+ uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+ fdv = INCAASC_FDV_LOW_BAUDRATE;
+ uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+#endif /* INCAASC_USE_FDV */
+
+ if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+ {
+ return; /* can't impossibly generate that baud rate */
+ }
+ }
+
+ /* Disable Baud Rate Generator; BG should only be written when R=0 */
+ CLEAR_BIT(pAsc->asc_con, ASCCON_R);
+
+#ifndef INCAASC_USE_FDV
+ /*
+ * Disable Fractional Divider (FDE)
+ * Divide clock by reload-value + constant (BRS)
+ */
+ /* FDE = 0 */
+ CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
+
+ if ( fdv == 2 )
+ CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
+ else
+ SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
+
+#else /* INCAASC_USE_FDV */
+
+ /* Enable Fractional Divider */
+ SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
+
+ /* Set fractional divider value */
+ pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
+
+#endif /* INCAASC_USE_FDV */
+
+ /* Set reload value in BG */
+ pAsc->asc_bg = uiReloadValue;
+
+ /* Enable Baud Rate Generator */
+ SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
+}
+
+/*******************************************************************************
+*
+* serial_setopt - set the serial options
+*
+* Set the channel operating mode to that specified. Following options
+* are supported: CREAD, CSIZE, PARENB, and PARODD.
+*
+* Note, this routine disables the transmitter. The calling routine
+* may have to re-enable it.
+*
+* RETURNS:
+* Returns 0 to indicate success, otherwise -1 is returned
+*/
+
+static int serial_setopt (void)
+{
+ ulong con;
+
+ switch ( ASC_OPTIONS & ASCOPT_CSIZE )
+ {
+ /* 7-bit-data */
+ case ASCOPT_CS7:
+ con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
+ break;
+
+ /* 8-bit-data */
+ case ASCOPT_CS8:
+ if ( ASC_OPTIONS & ASCOPT_PARENB )
+ con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
+ else
+ con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
+ break;
+
+ /*
+ * only 7 and 8-bit frames are supported
+ * if we don't use IOCTL extensions
+ */
+ default:
+ return -1;
+ }
+
+ if ( ASC_OPTIONS & ASCOPT_STOPB )
+ SET_BIT(con, ASCCON_STP); /* 2 stop bits */
+ else
+ CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
+
+ if ( ASC_OPTIONS & ASCOPT_PARENB )
+ SET_BIT(con, ASCCON_PEN); /* enable parity checking */
+ else
+ CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
+
+ if ( ASC_OPTIONS & ASCOPT_PARODD )
+ SET_BIT(con, ASCCON_ODD); /* odd parity */
+ else
+ CLEAR_BIT(con, ASCCON_ODD); /* even parity */
+
+ if ( ASC_OPTIONS & ASCOPT_CREAD )
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
+
+ pAsc->asc_con |= con;
+
+ return 0;
+}
+
+void serial_putc (const char c)
+{
+#ifdef ASC_FIFO_PRESENT
+ uint txFl = 0;
+#else
+ uint timeout = 0;
+#endif
+
+ if (c == '\n') serial_putc ('\r');
+
+#ifdef ASC_FIFO_PRESENT
+ /* check do we have a free space in the TX FIFO */
+ /* get current filling level */
+ do
+ {
+ txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
+ }
+ while ( txFl == INCAASC_TXFIFO_FULL );
+#else
+
+ while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
+ FBS_ISR_AB))
+ {
+ if (timeout++ > TOUT_LOOP)
+ {
+ break;
+ }
+ }
+#endif
+
+ pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
+
+#ifndef ASC_FIFO_PRESENT
+ *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
+ FBS_ISR_AT;
+#endif
+
+ /* check for errors */
+ if ( pAsc->asc_con & ASCCON_OE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ return;
+ }
+}
+
+void serial_puts (const char *s)
+{
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ ulong symbol_mask;
+ char c;
+
+ while (!serial_tstc());
+
+ symbol_mask =
+ ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
+
+ c = (char)(pAsc->asc_rbuf & symbol_mask);
+
+#ifndef ASC_FIFO_PRESENT
+ *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
+#endif
+
+ return c;
+}
+
+int serial_tstc (void)
+{
+ int res = 1;
+
+#ifdef ASC_FIFO_PRESENT
+ if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
+ {
+ res = 0;
+ }
+#else
+ if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
+ FBS_ISR_AR))
+
+ {
+ res = 0;
+ }
+#endif
+ else if ( pAsc->asc_con & ASCCON_FE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
+ res = 0;
+ }
+ else if ( pAsc->asc_con & ASCCON_PE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
+ res = 0;
+ }
+ else if ( pAsc->asc_con & ASCCON_OE )
+ {
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ res = 0;
+ }
+
+ return res;
+}
+#endif /* CONFIG_PURPLE || CONFIG_INCA_IP */
--- /dev/null
+/* incaAscSio.h - (INCA) ASC UART tty driver header */
+
+#ifndef __INCincaAscSioh
+#define __INCincaAscSioh
+
+#include <asm/inca-ip.h>
+
+/* channel operating modes */
+#define ASCOPT_CSIZE 0x00000003
+#define ASCOPT_CS7 0x00000001
+#define ASCOPT_CS8 0x00000002
+#define ASCOPT_PARENB 0x00000004
+#define ASCOPT_STOPB 0x00000008
+#define ASCOPT_PARODD 0x00000010
+#define ASCOPT_CREAD 0x00000020
+
+#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
+
+/* ASC input select (0 or 1) */
+#define CONSOLE_TTY 0
+
+/* use fractional divider for baudrate settings */
+#define INCAASC_USE_FDV
+
+#ifdef INCAASC_USE_FDV
+ #define INCAASC_FDV_LOW_BAUDRATE 71
+ #define INCAASC_FDV_HIGH_BAUDRATE 453
+#endif /*INCAASC_USE_FDV*/
+
+
+#define INCAASC_TXFIFO_FL 1
+#define INCAASC_RXFIFO_FL 1
+#define INCAASC_TXFIFO_FULL 16
+
+/* interrupt lines masks for the ASC device interrupts*/
+/* change these macroses if it's necessary */
+#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
+
+#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
+#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
+#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
+#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
+
+/* interrupt controller access macros */
+#define ASC_INTERRUPTS_ENABLE(X) \
+ *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
+#define ASC_INTERRUPTS_DISABLE(X) \
+ *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
+#define ASC_INTERRUPTS_CLEAR(X) \
+ *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
+
+/* CLC register's bits and bitfields */
+#define ASCCLC_DISR 0x00000001
+#define ASCCLC_DISS 0x00000002
+#define ASCCLC_RMCMASK 0x0000FF00
+#define ASCCLC_RMCOFFSET 8
+
+/* CON register's bits and bitfields */
+#define ASCCON_MODEMASK 0x0007
+ #define ASCCON_M_8SYNC 0x0
+ #define ASCCON_M_8ASYNC 0x1
+ #define ASCCON_M_8IRDAASYNC 0x2
+ #define ASCCON_M_7ASYNCPAR 0x3
+ #define ASCCON_M_9ASYNC 0x4
+ #define ASCCON_M_8WAKEUPASYNC 0x5
+ #define ASCCON_M_8ASYNCPAR 0x7
+#define ASCCON_STP 0x0008
+#define ASCCON_REN 0x0010
+#define ASCCON_PEN 0x0020
+#define ASCCON_FEN 0x0040
+#define ASCCON_OEN 0x0080
+#define ASCCON_PE 0x0100
+#define ASCCON_FE 0x0200
+#define ASCCON_OE 0x0400
+#define ASCCON_FDE 0x0800
+#define ASCCON_ODD 0x1000
+#define ASCCON_BRS 0x2000
+#define ASCCON_LB 0x4000
+#define ASCCON_R 0x8000
+
+/* WHBCON register's bits and bitfields */
+#define ASCWHBCON_CLRREN 0x0010
+#define ASCWHBCON_SETREN 0x0020
+#define ASCWHBCON_CLRPE 0x0100
+#define ASCWHBCON_CLRFE 0x0200
+#define ASCWHBCON_CLROE 0x0400
+#define ASCWHBCON_SETPE 0x0800
+#define ASCWHBCON_SETFE 0x1000
+#define ASCWHBCON_SETOE 0x2000
+
+/* ABCON register's bits and bitfields */
+#define ASCABCON_ABEN 0x0001
+#define ASCABCON_AUREN 0x0002
+#define ASCABCON_ABSTEN 0x0004
+#define ASCABCON_ABDETEN 0x0008
+#define ASCABCON_FCDETEN 0x0010
+#define ASCABCON_EMMASK 0x0300
+ #define ASCABCON_EMOFF 8
+ #define ASCABCON_EM_DISAB 0x0
+ #define ASCABCON_EM_DURAB 0x1
+ #define ASCABCON_EM_ALWAYS 0x2
+#define ASCABCON_TXINV 0x0400
+#define ASCABCON_RXINV 0x0800
+
+/* FDV register mask, offset and bitfields*/
+#define ASCFDV_VALUE_MASK 0x000001FF
+
+/* WHBABCON register's bits and bitfields */
+#define ASCWHBABCON_SETABEN 0x0001
+#define ASCWHBABCON_CLRABEN 0x0002
+
+/* ABSTAT register's bits and bitfields */
+#define ASCABSTAT_FCSDET 0x0001
+#define ASCABSTAT_FCCDET 0x0002
+#define ASCABSTAT_SCSDET 0x0004
+#define ASCABSTAT_SCCDET 0x0008
+#define ASCABSTAT_DETWAIT 0x0010
+
+/* WHBABSTAT register's bits and bitfields */
+#define ASCWHBABSTAT_CLRFCSDET 0x0001
+#define ASCWHBABSTAT_SETFCSDET 0x0002
+#define ASCWHBABSTAT_CLRFCCDET 0x0004
+#define ASCWHBABSTAT_SETFCCDET 0x0008
+#define ASCWHBABSTAT_CLRSCSDET 0x0010
+#define ASCWHBABSTAT_SETSCSDET 0x0020
+#define ASCWHBABSTAT_SETSCCDET 0x0040
+#define ASCWHBABSTAT_CLRSCCDET 0x0080
+#define ASCWHBABSTAT_CLRDETWAIT 0x0100
+#define ASCWHBABSTAT_SETDETWAIT 0x0200
+
+/* TXFCON register's bits and bitfields */
+#define ASCTXFCON_TXFEN 0x0001
+#define ASCTXFCON_TXFFLU 0x0002
+#define ASCTXFCON_TXTMEN 0x0004
+#define ASCTXFCON_TXFITLMASK 0x3F00
+#define ASCTXFCON_TXFITLOFF 8
+
+/* RXFCON register's bits and bitfields */
+#define ASCRXFCON_RXFEN 0x0001
+#define ASCRXFCON_RXFFLU 0x0002
+#define ASCRXFCON_RXTMEN 0x0004
+#define ASCRXFCON_RXFITLMASK 0x3F00
+#define ASCRXFCON_RXFITLOFF 8
+
+/* FSTAT register's bits and bitfields */
+#define ASCFSTAT_RXFFLMASK 0x003F
+#define ASCFSTAT_TXFFLMASK 0x3F00
+#define ASCFSTAT_TXFFLOFF 8
+
+#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
+
+typedef struct /* incaAsc_t */
+{
+ volatile unsigned long asc_clc; /*0x0000*/
+ volatile unsigned long asc_pisel; /*0x0004*/
+ volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
+ volatile unsigned long asc_con; /*0x0010*/
+ volatile unsigned long asc_bg; /*0x0014*/
+ volatile unsigned long asc_fdv; /*0x0018*/
+ volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
+ volatile unsigned long asc_tbuf; /*0x0020*/
+ volatile unsigned long asc_rbuf; /*0x0024*/
+ volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
+ volatile unsigned long asc_abcon; /*0x0030*/
+ volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
+ volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
+ volatile unsigned long asc_rxfcon; /*0x0040*/
+ volatile unsigned long asc_txfcon; /*0x0044*/
+ volatile unsigned long asc_fstat; /*0x0048*/
+ volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
+ volatile unsigned long asc_whbcon; /*0x0050*/
+ volatile unsigned long asc_whbabcon; /*0x0054*/
+ volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
+
+} incaAsc_t;
+
+#endif /* __INCincaAscSioh */
--- /dev/null
+/* Only eth0 supported for now
+ *
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <config.h>
+
+#ifdef CONFIG_AU1X00
+
+#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#error "PHY and MII not supported yet"
+/* We just assume that we are running 100FD for now */
+/* We all use switches, right? ;-) */
+#endif
+
+#ifdef CONFIG_AU1000
+/* Base address differ between cpu:s */
+#define ETH0_BASE AU1000_ETH0_BASE
+#define MAC0_ENABLE AU1000_MAC0_ENABLE
+#else
+#error "Au1100 and Au1500 not supported"
+#endif
+
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/au1x00.h>
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH 1520
+#define PKT_MAXBUF_SIZE 1518
+
+static char txbuf[DBUF_LENGTH];
+
+static int next_tx;
+static int next_rx;
+
+/* 4 rx and 4 tx fifos */
+#define NO_OF_FIFOS 4
+
+typedef struct{
+ u32 status;
+ u32 addr;
+ u32 len; /* Only used for tx */
+ u32 not_used;
+} mac_fifo_t;
+
+mac_fifo_t mac_fifo[NO_OF_FIFOS];
+
+#define MAX_WAIT 1000
+
+static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
+ volatile mac_fifo_t *fifo_tx =
+ (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+ int i;
+ int res;
+
+ /* tx fifo should always be idle */
+ fifo_tx[next_tx].len = length;
+ fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
+ au_sync();
+
+ udelay(1);
+ i=0;
+ while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
+ if(i>MAX_WAIT){
+ printf("TX timeout\n");
+ break;
+ }
+ udelay(1);
+ i++;
+ }
+
+ /* Clear done bit */
+ fifo_tx[next_tx].addr = 0;
+ fifo_tx[next_tx].len = 0;
+ au_sync();
+
+ res = fifo_tx[next_tx].status;
+
+ next_tx++;
+ if(next_tx>=NO_OF_FIFOS){
+ next_tx=0;
+ }
+ return(res);
+}
+
+static int au1x00_recv(struct eth_device* dev){
+ volatile mac_fifo_t *fifo_rx =
+ (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+
+ int length;
+ u32 status;
+
+ for(;;){
+ if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
+ /* Nothing has been received */
+ return(-1);
+ }
+
+ status = fifo_rx[next_rx].status;
+
+ length = status&0x3FFF;
+
+ if(status&RX_ERROR){
+ printf("Rx error 0x%x\n", status);
+ }
+ else{
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[next_rx], length - 4);
+ }
+
+ fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
+
+ next_rx++;
+ if(next_rx>=NO_OF_FIFOS){
+ next_rx=0;
+ }
+ } /* for */
+
+ return(0); /* Does anyone use this? */
+}
+
+static int au1x00_init(struct eth_device* dev, bd_t * bd){
+
+ volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
+ volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
+ volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
+ volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
+ volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
+ volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
+ volatile mac_fifo_t *fifo_tx =
+ (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
+ volatile mac_fifo_t *fifo_rx =
+ (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
+ int i;
+
+ next_tx = 0;
+ next_rx = 0;
+
+ /* We have to enable clocks before releasing reset */
+ *macen = MAC_EN_CLOCK_ENABLE;
+ udelay(10);
+
+ /* Enable MAC0 */
+ /* We have to release reset before accessing registers */
+ *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
+ MAC_EN_RESET1|MAC_EN_RESET2;
+ udelay(10);
+
+ for(i=0;i<NO_OF_FIFOS;i++){
+ fifo_tx[i].len = 0;
+ fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
+ fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
+ }
+
+ /* Put mac addr in little endian */
+#define ea eth_get_dev()->enetaddr
+ *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
+ *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
+ (ea[1] << 8) | (ea[0] ) ;
+#undef ea
+
+ *mac_mcast_low = 0;
+ *mac_mcast_high = 0;
+
+ *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
+ udelay(1);
+ *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
+
+ return(1);
+}
+
+static void au1x00_halt(struct eth_device* dev){
+}
+
+int au1x00_enet_initialize(bd_t *bis){
+ struct eth_device* dev;
+
+ dev = (struct eth_device*) malloc(sizeof *dev);
+ memset(dev, 0, sizeof *dev);
+
+ sprintf(dev->name, "Au1X00 ETHERNET");
+ dev->iobase = 0;
+ dev->priv = 0;
+ dev->init = au1x00_init;
+ dev->halt = au1x00_halt;
+ dev->send = au1x00_send;
+ dev->recv = au1x00_recv;
+
+ eth_register(dev);
+
+ return 1;
+}
+
+#endif /* CONFIG_AU1X00 */
--- /dev/null
+/*
+ * AU1X00 UART support
+ *
+ * Hardcoded to UART 0 for now
+ * Speed and options also hardcoded to 115200 8N1
+ *
+ * Copyright (c) 2003 Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_AU1X00
+
+#include <common.h>
+#include <asm/au1x00.h>
+
+/******************************************************************************
+*
+* serial_init - initialize a channel
+*
+* This routine initializes the number of data bits, parity
+* and set the selected baud rate. Interrupts are disabled.
+* Set the modem control signals if the option is selected.
+*
+* RETURNS: N/A
+*/
+
+int serial_init (void)
+{
+ volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
+ volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
+
+ /* Enable clocks first */
+ *uart_enable = UART_EN_CE;
+
+ /* Then release reset */
+ /* Must release reset before setting other regs */
+ *uart_enable = UART_EN_CE|UART_EN_E;
+
+ /* Activate fifos, reset tx and rx */
+ /* Set tx trigger level to 12 */
+ *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
+ UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
+
+ serial_setbrg();
+
+ return 0;
+}
+
+
+void serial_setbrg (void)
+{
+ volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
+ volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
+
+ /* Set baudrate to 115200 */
+ *uart_clk = 0x36;
+
+ /* Set parity, stop bits and word length to 8N1 */
+ *uart_lcr = UART_LCR_WLEN8;
+}
+
+void serial_putc (const char c)
+{
+ volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+ volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
+
+ if (c == '\n') serial_putc ('\r');
+
+ /* Wait for fifo to shift out some bytes */
+ while((*uart_lsr&UART_LSR_THRE)==0);
+
+ *uart_tx = (u32)c;
+}
+
+void serial_puts (const char *s)
+{
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+}
+
+int serial_getc (void)
+{
+ volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
+ char c;
+
+ while (!serial_tstc());
+
+ c = (*uart_rx&0xFF);
+ return c;
+}
+
+int serial_tstc (void)
+{
+ volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
+
+ if(*uart_lsr&UART_LSR_DR){
+ /* Data in rfifo */
+ return(1);
+ }
+ return 0;
+}
+#endif /* CONFIG_SERIAL_AU1X00 */
* RETURNS: N/A
*
*/
-#if defined(CONFIG_INCA_IP)
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
-#elif defined(CONFIG_PURPLE)
+#if defined(CONFIG_PURPLE)
# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+#else
+# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
#include <common.h>
#include <command.h>
#include <asm/inca-ip.h>
+#include <asm/mipsregs.h>
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
{
}
+
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){
+ write_32bit_cp0_register(CP0_ENTRYLO0, low0);
+ write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
+ write_32bit_cp0_register(CP0_ENTRYLO1, low1);
+ write_32bit_cp0_register(CP0_ENTRYHI, hi);
+ write_32bit_cp0_register(CP0_INDEX, index);
+ tlb_write_indexed();
+}
+++ /dev/null
-/*
- * (INCA) ASC UART support
- */
-
-#include <config.h>
-
-#ifdef CONFIG_PURPLE
-#define serial_init asc_serial_init
-#define serial_putc asc_serial_putc
-#define serial_puts asc_serial_puts
-#define serial_getc asc_serial_getc
-#define serial_tstc asc_serial_tstc
-#define serial_setbrg asc_serial_setbrg
-#endif
-
-#include <common.h>
-#include <asm/inca-ip.h>
-#include "serial.h"
-
-#ifdef CONFIG_PURPLE
-
-#undef ASC_FIFO_PRESENT
-#define TOUT_LOOP 100000
-
-/* Set base address for second FPI interrupt control register bank */
-#define SFPI_INTCON_BASEADDR 0xBF0F0000
-
-/* Register offset from base address */
-#define FBS_ISR 0x00000000 /* Interrupt status register */
-#define FBS_IMR 0x00000008 /* Interrupt mask register */
-#define FBS_IDIS 0x00000010 /* Interrupt disable register */
-
-/* Interrupt status register bits */
-#define FBS_ISR_AT 0x00000040 /* ASC transmit interrupt */
-#define FBS_ISR_AR 0x00000020 /* ASC receive interrupt */
-#define FBS_ISR_AE 0x00000010 /* ASC error interrupt */
-#define FBS_ISR_AB 0x00000008 /* ASC transmit buffer interrupt */
-#define FBS_ISR_AS 0x00000004 /* ASC start of autobaud detection interrupt */
-#define FBS_ISR_AF 0x00000002 /* ASC end of autobaud detection interrupt */
-
-#else
-
-#define ASC_FIFO_PRESENT
-
-#endif
-
-
-#define SET_BIT(reg, mask) reg |= (mask)
-#define CLEAR_BIT(reg, mask) reg &= (~mask)
-#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
-#define SET_BITS(reg, mask) SET_BIT(reg, mask)
-#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
-
-extern uint incaip_get_fpiclk(void);
-
-static int serial_setopt (void);
-
-/* pointer to ASC register base address */
-static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC;
-
-/******************************************************************************
-*
-* serial_init - initialize a INCAASC channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-int serial_init (void)
-{
-#ifdef CONFIG_INCA_IP
- /* we have to set PMU.EN13 bit to enable an ASC device*/
- INCAASC_PMU_ENABLE(13);
-#endif
-
- /* and we have to set CLC register*/
- CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
- SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
- /* initialy we are in async mode */
- pAsc->asc_con = ASCCON_M_8ASYNC;
-
- /* select input port */
- pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
-
-#ifdef ASC_FIFO_PRESENT
- /* TXFIFO's filling level */
- SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
- ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
- /* enable TXFIFO */
- SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
-
- /* RXFIFO's filling level */
- SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
- ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
- /* enable RXFIFO */
- SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
-#endif
-
- /* enable error signals */
- SET_BIT(pAsc->asc_con, ASCCON_FEN);
- SET_BIT(pAsc->asc_con, ASCCON_OEN);
-
-#ifdef CONFIG_INCA_IP
- /* acknowledge ASC interrupts */
- ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL);
-
- /* disable ASC interrupts */
- ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL);
-#endif
-
-#ifdef ASC_FIFO_PRESENT
- /* set FIFOs into the transparent mode */
- SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN);
- SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN);
-#endif
-
- /* set baud rate */
- serial_setbrg();
-
- /* set the options */
- serial_setopt();
-
- return 0;
-}
-
-void serial_setbrg (void)
-{
- ulong uiReloadValue, fdv;
- ulong f_ASC;
-
-#ifdef CONFIG_INCA_IP
- f_ASC = incaip_get_fpiclk();
-#else
- f_ASC = ASC_CLOCK_RATE;
-#endif
-
-#ifndef INCAASC_USE_FDV
- fdv = 2;
- uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
- fdv = INCAASC_FDV_HIGH_BAUDRATE;
- uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
- if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
- {
-#ifndef INCAASC_USE_FDV
- fdv = 3;
- uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
- fdv = INCAASC_FDV_LOW_BAUDRATE;
- uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
-#endif /* INCAASC_USE_FDV */
-
- if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
- {
- return; /* can't impossibly generate that baud rate */
- }
- }
-
- /* Disable Baud Rate Generator; BG should only be written when R=0 */
- CLEAR_BIT(pAsc->asc_con, ASCCON_R);
-
-#ifndef INCAASC_USE_FDV
- /*
- * Disable Fractional Divider (FDE)
- * Divide clock by reload-value + constant (BRS)
- */
- /* FDE = 0 */
- CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
-
- if ( fdv == 2 )
- CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
- else
- SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
-
-#else /* INCAASC_USE_FDV */
-
- /* Enable Fractional Divider */
- SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
-
- /* Set fractional divider value */
- pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
-
-#endif /* INCAASC_USE_FDV */
-
- /* Set reload value in BG */
- pAsc->asc_bg = uiReloadValue;
-
- /* Enable Baud Rate Generator */
- SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */
-}
-
-/*******************************************************************************
-*
-* serial_setopt - set the serial options
-*
-* Set the channel operating mode to that specified. Following options
-* are supported: CREAD, CSIZE, PARENB, and PARODD.
-*
-* Note, this routine disables the transmitter. The calling routine
-* may have to re-enable it.
-*
-* RETURNS:
-* Returns 0 to indicate success, otherwise -1 is returned
-*/
-
-static int serial_setopt (void)
-{
- ulong con;
-
- switch ( ASC_OPTIONS & ASCOPT_CSIZE )
- {
- /* 7-bit-data */
- case ASCOPT_CS7:
- con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
- break;
-
- /* 8-bit-data */
- case ASCOPT_CS8:
- if ( ASC_OPTIONS & ASCOPT_PARENB )
- con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
- else
- con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
- break;
-
- /*
- * only 7 and 8-bit frames are supported
- * if we don't use IOCTL extensions
- */
- default:
- return -1;
- }
-
- if ( ASC_OPTIONS & ASCOPT_STOPB )
- SET_BIT(con, ASCCON_STP); /* 2 stop bits */
- else
- CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
-
- if ( ASC_OPTIONS & ASCOPT_PARENB )
- SET_BIT(con, ASCCON_PEN); /* enable parity checking */
- else
- CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
-
- if ( ASC_OPTIONS & ASCOPT_PARODD )
- SET_BIT(con, ASCCON_ODD); /* odd parity */
- else
- CLEAR_BIT(con, ASCCON_ODD); /* even parity */
-
- if ( ASC_OPTIONS & ASCOPT_CREAD )
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
-
- pAsc->asc_con |= con;
-
- return 0;
-}
-
-void serial_putc (const char c)
-{
-#ifdef ASC_FIFO_PRESENT
- uint txFl = 0;
-#else
- uint timeout = 0;
-#endif
-
- if (c == '\n') serial_putc ('\r');
-
-#ifdef ASC_FIFO_PRESENT
- /* check do we have a free space in the TX FIFO */
- /* get current filling level */
- do
- {
- txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
- }
- while ( txFl == INCAASC_TXFIFO_FULL );
-#else
-
- while(!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
- FBS_ISR_AB))
- {
- if (timeout++ > TOUT_LOOP)
- {
- break;
- }
- }
-#endif
-
- pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
-
-#ifndef ASC_FIFO_PRESENT
- *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
- FBS_ISR_AT;
-#endif
-
- /* check for errors */
- if ( pAsc->asc_con & ASCCON_OE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
- return;
- }
-}
-
-void serial_puts (const char *s)
-{
- while (*s)
- {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
-{
- ulong symbol_mask;
- char c;
-
- while (!serial_tstc());
-
- symbol_mask =
- ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-
- c = (char)(pAsc->asc_rbuf & symbol_mask);
-
-#ifndef ASC_FIFO_PRESENT
- *(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AR;
-#endif
-
- return c;
-}
-
-int serial_tstc (void)
-{
- int res = 1;
-
-#ifdef ASC_FIFO_PRESENT
- if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
- {
- res = 0;
- }
-#else
- if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
- FBS_ISR_AR))
-
- {
- res = 0;
- }
-#endif
- else if ( pAsc->asc_con & ASCCON_FE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
- res = 0;
- }
- else if ( pAsc->asc_con & ASCCON_PE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
- res = 0;
- }
- else if ( pAsc->asc_con & ASCCON_OE )
- {
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
- res = 0;
- }
-
- return res;
-}
+++ /dev/null
-/* incaAscSio.h - (INCA) ASC UART tty driver header */
-
-#ifndef __INCincaAscSioh
-#define __INCincaAscSioh
-
-#include <asm/inca-ip.h>
-
-/* channel operating modes */
-#define ASCOPT_CSIZE 0x00000003
-#define ASCOPT_CS7 0x00000001
-#define ASCOPT_CS8 0x00000002
-#define ASCOPT_PARENB 0x00000004
-#define ASCOPT_STOPB 0x00000008
-#define ASCOPT_PARODD 0x00000010
-#define ASCOPT_CREAD 0x00000020
-
-#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
-
-/* ASC input select (0 or 1) */
-#define CONSOLE_TTY 0
-
-/* use fractional divider for baudrate settings */
-#define INCAASC_USE_FDV
-
-#ifdef INCAASC_USE_FDV
- #define INCAASC_FDV_LOW_BAUDRATE 71
- #define INCAASC_FDV_HIGH_BAUDRATE 453
-#endif /*INCAASC_USE_FDV*/
-
-
-#define INCAASC_TXFIFO_FL 1
-#define INCAASC_RXFIFO_FL 1
-#define INCAASC_TXFIFO_FULL 16
-
-/* interrupt lines masks for the ASC device interrupts*/
-/* change these macroses if it's necessary */
-#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
-
-#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
-#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
-#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
-#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
-
-/* interrupt controller access macros */
-#define ASC_INTERRUPTS_ENABLE(X) \
- *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
-#define ASC_INTERRUPTS_DISABLE(X) \
- *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
-#define ASC_INTERRUPTS_CLEAR(X) \
- *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
-
-/* CLC register's bits and bitfields */
-#define ASCCLC_DISR 0x00000001
-#define ASCCLC_DISS 0x00000002
-#define ASCCLC_RMCMASK 0x0000FF00
-#define ASCCLC_RMCOFFSET 8
-
-/* CON register's bits and bitfields */
-#define ASCCON_MODEMASK 0x0007
- #define ASCCON_M_8SYNC 0x0
- #define ASCCON_M_8ASYNC 0x1
- #define ASCCON_M_8IRDAASYNC 0x2
- #define ASCCON_M_7ASYNCPAR 0x3
- #define ASCCON_M_9ASYNC 0x4
- #define ASCCON_M_8WAKEUPASYNC 0x5
- #define ASCCON_M_8ASYNCPAR 0x7
-#define ASCCON_STP 0x0008
-#define ASCCON_REN 0x0010
-#define ASCCON_PEN 0x0020
-#define ASCCON_FEN 0x0040
-#define ASCCON_OEN 0x0080
-#define ASCCON_PE 0x0100
-#define ASCCON_FE 0x0200
-#define ASCCON_OE 0x0400
-#define ASCCON_FDE 0x0800
-#define ASCCON_ODD 0x1000
-#define ASCCON_BRS 0x2000
-#define ASCCON_LB 0x4000
-#define ASCCON_R 0x8000
-
-/* WHBCON register's bits and bitfields */
-#define ASCWHBCON_CLRREN 0x0010
-#define ASCWHBCON_SETREN 0x0020
-#define ASCWHBCON_CLRPE 0x0100
-#define ASCWHBCON_CLRFE 0x0200
-#define ASCWHBCON_CLROE 0x0400
-#define ASCWHBCON_SETPE 0x0800
-#define ASCWHBCON_SETFE 0x1000
-#define ASCWHBCON_SETOE 0x2000
-
-/* ABCON register's bits and bitfields */
-#define ASCABCON_ABEN 0x0001
-#define ASCABCON_AUREN 0x0002
-#define ASCABCON_ABSTEN 0x0004
-#define ASCABCON_ABDETEN 0x0008
-#define ASCABCON_FCDETEN 0x0010
-#define ASCABCON_EMMASK 0x0300
- #define ASCABCON_EMOFF 8
- #define ASCABCON_EM_DISAB 0x0
- #define ASCABCON_EM_DURAB 0x1
- #define ASCABCON_EM_ALWAYS 0x2
-#define ASCABCON_TXINV 0x0400
-#define ASCABCON_RXINV 0x0800
-
-/* FDV register mask, offset and bitfields*/
-#define ASCFDV_VALUE_MASK 0x000001FF
-
-/* WHBABCON register's bits and bitfields */
-#define ASCWHBABCON_SETABEN 0x0001
-#define ASCWHBABCON_CLRABEN 0x0002
-
-/* ABSTAT register's bits and bitfields */
-#define ASCABSTAT_FCSDET 0x0001
-#define ASCABSTAT_FCCDET 0x0002
-#define ASCABSTAT_SCSDET 0x0004
-#define ASCABSTAT_SCCDET 0x0008
-#define ASCABSTAT_DETWAIT 0x0010
-
-/* WHBABSTAT register's bits and bitfields */
-#define ASCWHBABSTAT_CLRFCSDET 0x0001
-#define ASCWHBABSTAT_SETFCSDET 0x0002
-#define ASCWHBABSTAT_CLRFCCDET 0x0004
-#define ASCWHBABSTAT_SETFCCDET 0x0008
-#define ASCWHBABSTAT_CLRSCSDET 0x0010
-#define ASCWHBABSTAT_SETSCSDET 0x0020
-#define ASCWHBABSTAT_SETSCCDET 0x0040
-#define ASCWHBABSTAT_CLRSCCDET 0x0080
-#define ASCWHBABSTAT_CLRDETWAIT 0x0100
-#define ASCWHBABSTAT_SETDETWAIT 0x0200
-
-/* TXFCON register's bits and bitfields */
-#define ASCTXFCON_TXFEN 0x0001
-#define ASCTXFCON_TXFFLU 0x0002
-#define ASCTXFCON_TXTMEN 0x0004
-#define ASCTXFCON_TXFITLMASK 0x3F00
-#define ASCTXFCON_TXFITLOFF 8
-
-/* RXFCON register's bits and bitfields */
-#define ASCRXFCON_RXFEN 0x0001
-#define ASCRXFCON_RXFFLU 0x0002
-#define ASCRXFCON_RXTMEN 0x0004
-#define ASCRXFCON_RXFITLMASK 0x3F00
-#define ASCRXFCON_RXFITLOFF 8
-
-/* FSTAT register's bits and bitfields */
-#define ASCFSTAT_RXFFLMASK 0x003F
-#define ASCFSTAT_TXFFLMASK 0x3F00
-#define ASCFSTAT_TXFFLOFF 8
-
-#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
-
-typedef struct /* incaAsc_t */
-{
- volatile unsigned long asc_clc; /*0x0000*/
- volatile unsigned long asc_pisel; /*0x0004*/
- volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
- volatile unsigned long asc_con; /*0x0010*/
- volatile unsigned long asc_bg; /*0x0014*/
- volatile unsigned long asc_fdv; /*0x0018*/
- volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
- volatile unsigned long asc_tbuf; /*0x0020*/
- volatile unsigned long asc_rbuf; /*0x0024*/
- volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
- volatile unsigned long asc_abcon; /*0x0030*/
- volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
- volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
- volatile unsigned long asc_rxfcon; /*0x0040*/
- volatile unsigned long asc_txfcon; /*0x0044*/
- volatile unsigned long asc_fstat; /*0x0048*/
- volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
- volatile unsigned long asc_whbcon; /*0x0050*/
- volatile unsigned long asc_whbabcon; /*0x0054*/
- volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
-
-} incaAsc_t;
-
-#endif /* __INCincaAscSioh */
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ACEX1K_H_
+#define _ACEX1K_H_
+
+#include <altera.h>
+
+extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size );
+extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize );
+extern int ACEX1K_info( Altera_desc *desc );
+extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off );
+
+/* Slave Serial Implementation function table */
+typedef struct {
+ Altera_pre_fn pre;
+ Altera_config_fn config;
+ Altera_clk_fn clk;
+ Altera_status_fn status;
+ Altera_done_fn done;
+ Altera_data_fn data;
+ Altera_abort_fn abort;
+ Altera_post_fn post;
+ int relocated;
+} Altera_ACEX1K_Passive_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* ACEX1K */
+/* FIXME: Which size do we mean?
+ * Datasheet says 1337000/8=167125Bytes,
+ * Filesize of an *.rbf file is 166965 Bytes
+ */
+#if 0
+#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */
+#endif
+#define Altera_EP1K100_SIZE (166965*8)
+
+/* Descriptor Macros
+ *********************************************************************/
+/* ACEX1K devices */
+#define Altera_EP1K100_DESC(iface, fn_table, cookie) \
+{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie }
+
+#endif /* _ACEX1K_H_ */
#define _ALTERA_H_
/*
- * Note that this is just Altera FPGA interface boilerplate.
- * There is no support for Altera devices yet.
- *
- * See include/xilinx.h for a working example.
+ * See include/xilinx.h for another working example.
*/
-/* In your board's config.h file you should define CONFIG_FPGA as such:
- * #define CONFIG_FPGA (CFG_ALTERA_xxx | CFG_ALTERA_IF_xxx )
- */
+/* Altera Model definitions
+ *********************************************************************/
+#define CFG_ACEX1K CFG_FPGA_DEV( 0x1 )
-/* Altera Model definitions */
-#define CFG_ALTERA_xxxx ( CFG_FPGA_ALTERA | CFG_FPGA_DEV( 0x1 ))
+#define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K)
/* Add new models here */
-/* Altera Interface definitions */
-#define CFG_ALTERA_IF_xxx CFG_FPGA_IF( 0x1 )
+/* Altera Interface definitions
+ *********************************************************************/
+#define CFG_ALTERA_IF_PS CFG_FPGA_IF( 0x1 ) /* passive serial */
/* Add new interfaces here */
-typedef enum { /* typedef Altera_iface */
- min_altera_iface_type, /* insert all new types after this */
-/* Add new interfaces here */
- max_altera_iface_type /* insert all new types before this */
-} Altera_iface; /* end, typedef Altera_iface */
+typedef enum { /* typedef Altera_iface */
+ min_altera_iface_type, /* insert all new types after this */
+ passive_serial, /* serial data and external clock */
+ passive_parallel_synchronous, /* parallel data */
+ passive_parallel_asynchronous, /* parallel data */
+ passive_serial_asynchronous, /* serial data w/ internal clock (not used) */
+ altera_jtag_mode, /* jtag/tap serial (not used ) */
+ max_altera_iface_type /* insert all new types before this */
+} Altera_iface; /* end, typedef Altera_iface */
-typedef enum { /* typedef Altera_Family */
- min_altera_type, /* insert all new types after this */
+typedef enum { /* typedef Altera_Family */
+ min_altera_type, /* insert all new types after this */
+ Altera_ACEX1K, /* ACEX1K Family */
/* Add new models here */
- max_altera_type /* insert all new types before this */
-} Altera_Family; /* end, typedef Altera_Family */
+ max_altera_type /* insert all new types before this */
+} Altera_Family; /* end, typedef Altera_Family */
-typedef struct { /* typedef Altera_desc */
- Altera_Family family; /* part type */
- Altera_iface iface; /* interface type */
- size_t size; /* bytes of data part can accept */
- void * base; /* base interface address */
-} Altera_desc; /* end, typedef Altera_desc */
+typedef struct { /* typedef Altera_desc */
+ Altera_Family family; /* part type */
+ Altera_iface iface; /* interface type */
+ size_t size; /* bytes of data part can accept */
+ void * iface_fns;/* interface function table */
+ void * base; /* base interface address */
+ int cookie; /* implementation specific cookie */
+} Altera_desc; /* end, typedef Altera_desc */
+/* Generic Altera Functions
+ *********************************************************************/
extern int altera_load( Altera_desc *desc, void *image, size_t size );
extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize );
extern int altera_info( Altera_desc *desc );
-extern int altera_reloc( Altera_desc *desc, ulong reloc_off );
+extern int altera_reloc( Altera_desc *desc, ulong reloc_offset );
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*Altera_pre_fn)( int cookie );
+typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
+typedef int (*Altera_status_fn)( int cookie );
+typedef int (*Altera_done_fn)( int cookie );
+typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
+typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int (*Altera_abort_fn)( int cookie );
+typedef int (*Altera_post_fn)( int cookie );
-#endif /* _ALTERA_H_ */
+#endif /* _ALTERA_H_ */
--- /dev/null
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Include file for Alchemy Semiconductor's Au1k CPU.
+ *
+ * Copyright 2000,2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+ /*
+ * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
+ */
+
+#ifndef _AU1X00_H_
+#define _AU1X00_H_
+
+#ifndef __ASSEMBLY__
+/* cpu pipeline flush */
+void static inline au_sync(void)
+{
+ __asm__ volatile ("sync");
+}
+
+void static inline au_sync_udelay(int us)
+{
+ __asm__ volatile ("sync");
+ udelay(us);
+}
+
+void static inline au_writeb(u8 val, int reg)
+{
+ *(volatile u8 *)(reg) = val;
+}
+
+void static inline au_writew(u16 val, int reg)
+{
+ *(volatile u16 *)(reg) = val;
+}
+
+void static inline au_writel(u32 val, int reg)
+{
+ *(volatile u32 *)(reg) = val;
+}
+
+static inline u8 au_readb(unsigned long port)
+{
+ return (*(volatile u8 *)port);
+}
+
+static inline u16 au_readw(unsigned long port)
+{
+ return (*(volatile u16 *)port);
+}
+
+static inline u32 au_readl(unsigned long port)
+{
+ return (*(volatile u32 *)port);
+}
+
+/* These next three functions should be a generic part of the MIPS
+ * kernel (with the 'au_' removed from the name) and selected for
+ * processors that support the instructions.
+ * Taken from PPC tree. -- Dan
+ */
+/* Return the bit position of the most significant 1 bit in a word */
+static __inline__ int __ilog2(unsigned int x)
+{
+ int lz;
+
+ asm volatile (
+ ".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ ".set\tmips32\n\t"
+ "clz\t%0,%1\n\t"
+ ".set\tmips0\n\t"
+ ".set\tat\n\t"
+ ".set\treorder"
+ : "=r" (lz)
+ : "r" (x));
+
+ return 31 - lz;
+}
+
+static __inline__ int au_ffz(unsigned int x)
+{
+ if ((x = ~x) == 0)
+ return 32;
+ return __ilog2(x & -x);
+}
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+static __inline__ int au_ffs(int x)
+{
+ return __ilog2(x & -x) + 1;
+}
+
+#endif /* !ASSEMBLY */
+
+#ifdef CONFIG_PM
+/* no CP0 timer irq */
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
+#else
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+#endif
+
+/* SDRAM Controller */
+#define MEM_SDMODE0 0xB4000000
+#define MEM_SDMODE1 0xB4000004
+#define MEM_SDMODE2 0xB4000008
+
+#define MEM_SDADDR0 0xB400000C
+#define MEM_SDADDR1 0xB4000010
+#define MEM_SDADDR2 0xB4000014
+
+#define MEM_SDREFCFG 0xB4000018
+#define MEM_SDPRECMD 0xB400001C
+#define MEM_SDAUTOREF 0xB4000020
+
+#define MEM_SDWRMD0 0xB4000024
+#define MEM_SDWRMD1 0xB4000028
+#define MEM_SDWRMD2 0xB400002C
+
+#define MEM_SDSLEEP 0xB4000030
+#define MEM_SDSMCKE 0xB4000034
+
+/* Static Bus Controller */
+#define MEM_STCFG0 0xB4001000
+#define MEM_STTIME0 0xB4001004
+#define MEM_STADDR0 0xB4001008
+
+#define MEM_STCFG1 0xB4001010
+#define MEM_STTIME1 0xB4001014
+#define MEM_STADDR1 0xB4001018
+
+#define MEM_STCFG2 0xB4001020
+#define MEM_STTIME2 0xB4001024
+#define MEM_STADDR2 0xB4001028
+
+#define MEM_STCFG3 0xB4001030
+#define MEM_STTIME3 0xB4001034
+#define MEM_STADDR3 0xB4001038
+
+/* Interrupt Controller 0 */
+#define IC0_CFG0RD 0xB0400040
+#define IC0_CFG0SET 0xB0400040
+#define IC0_CFG0CLR 0xB0400044
+
+#define IC0_CFG1RD 0xB0400048
+#define IC0_CFG1SET 0xB0400048
+#define IC0_CFG1CLR 0xB040004C
+
+#define IC0_CFG2RD 0xB0400050
+#define IC0_CFG2SET 0xB0400050
+#define IC0_CFG2CLR 0xB0400054
+
+#define IC0_REQ0INT 0xB0400054
+#define IC0_SRCRD 0xB0400058
+#define IC0_SRCSET 0xB0400058
+#define IC0_SRCCLR 0xB040005C
+#define IC0_REQ1INT 0xB040005C
+
+#define IC0_ASSIGNRD 0xB0400060
+#define IC0_ASSIGNSET 0xB0400060
+#define IC0_ASSIGNCLR 0xB0400064
+
+#define IC0_WAKERD 0xB0400068
+#define IC0_WAKESET 0xB0400068
+#define IC0_WAKECLR 0xB040006C
+
+#define IC0_MASKRD 0xB0400070
+#define IC0_MASKSET 0xB0400070
+#define IC0_MASKCLR 0xB0400074
+
+#define IC0_RISINGRD 0xB0400078
+#define IC0_RISINGCLR 0xB0400078
+#define IC0_FALLINGRD 0xB040007C
+#define IC0_FALLINGCLR 0xB040007C
+
+#define IC0_TESTBIT 0xB0400080
+
+/* Interrupt Controller 1 */
+#define IC1_CFG0RD 0xB1800040
+#define IC1_CFG0SET 0xB1800040
+#define IC1_CFG0CLR 0xB1800044
+
+#define IC1_CFG1RD 0xB1800048
+#define IC1_CFG1SET 0xB1800048
+#define IC1_CFG1CLR 0xB180004C
+
+#define IC1_CFG2RD 0xB1800050
+#define IC1_CFG2SET 0xB1800050
+#define IC1_CFG2CLR 0xB1800054
+
+#define IC1_REQ0INT 0xB1800054
+#define IC1_SRCRD 0xB1800058
+#define IC1_SRCSET 0xB1800058
+#define IC1_SRCCLR 0xB180005C
+#define IC1_REQ1INT 0xB180005C
+
+#define IC1_ASSIGNRD 0xB1800060
+#define IC1_ASSIGNSET 0xB1800060
+#define IC1_ASSIGNCLR 0xB1800064
+
+#define IC1_WAKERD 0xB1800068
+#define IC1_WAKESET 0xB1800068
+#define IC1_WAKECLR 0xB180006C
+
+#define IC1_MASKRD 0xB1800070
+#define IC1_MASKSET 0xB1800070
+#define IC1_MASKCLR 0xB1800074
+
+#define IC1_RISINGRD 0xB1800078
+#define IC1_RISINGCLR 0xB1800078
+#define IC1_FALLINGRD 0xB180007C
+#define IC1_FALLINGCLR 0xB180007C
+
+#define IC1_TESTBIT 0xB1800080
+
+/* Interrupt Configuration Modes */
+#define INTC_INT_DISABLED 0
+#define INTC_INT_RISE_EDGE 0x1
+#define INTC_INT_FALL_EDGE 0x2
+#define INTC_INT_RISE_AND_FALL_EDGE 0x3
+#define INTC_INT_HIGH_LEVEL 0x5
+#define INTC_INT_LOW_LEVEL 0x6
+#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
+
+/* Interrupt Numbers */
+#define AU1X00_UART0_INT 0
+#define AU1000_UART1_INT 1 /* au1000 */
+#define AU1000_UART2_INT 2 /* au1000 */
+
+#define AU1500_PCI_INTA 1 /* au1500 */
+#define AU1500_PCI_INTB 2 /* au1500 */
+
+#define AU1X00_UART3_INT 3
+
+#define AU1000_SSI0_INT 4 /* au1000 */
+#define AU1000_SSI1_INT 5 /* au1000 */
+
+#define AU1500_PCI_INTC 4 /* au1500 */
+#define AU1500_PCI_INTD 5 /* au1500 */
+
+#define AU1X00_DMA_INT_BASE 6
+#define AU1X00_TOY_INT 14
+#define AU1X00_TOY_MATCH0_INT 15
+#define AU1X00_TOY_MATCH1_INT 16
+#define AU1X00_TOY_MATCH2_INT 17
+#define AU1X00_RTC_INT 18
+#define AU1X00_RTC_MATCH0_INT 19
+#define AU1X00_RTC_MATCH1_INT 20
+#define AU1X00_RTC_MATCH2_INT 21
+#define AU1000_IRDA_TX_INT 22 /* au1000 */
+#define AU1000_IRDA_RX_INT 23 /* au1000 */
+#define AU1X00_USB_DEV_REQ_INT 24
+#define AU1X00_USB_DEV_SUS_INT 25
+#define AU1X00_USB_HOST_INT 26
+#define AU1X00_ACSYNC_INT 27
+#define AU1X00_MAC0_DMA_INT 28
+#define AU1X00_MAC1_DMA_INT 29
+#define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT
+#define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT
+#define AU1000_I2S_UO_INT 30 /* au1000 */
+#define AU1X00_AC97C_INT 31
+#define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT
+#define AU1X00_GPIO_0 32
+#define AU1X00_GPIO_1 33
+#define AU1X00_GPIO_2 34
+#define AU1X00_GPIO_3 35
+#define AU1X00_GPIO_4 36
+#define AU1X00_GPIO_5 37
+#define AU1X00_GPIO_6 38
+#define AU1X00_GPIO_7 39
+#define AU1X00_GPIO_8 40
+#define AU1X00_GPIO_9 41
+#define AU1X00_GPIO_10 42
+#define AU1X00_GPIO_11 43
+#define AU1X00_GPIO_12 44
+#define AU1X00_GPIO_13 45
+#define AU1X00_GPIO_14 46
+#define AU1X00_GPIO_15 47
+
+/* Au1000 only */
+#define AU1000_GPIO_16 48
+#define AU1000_GPIO_17 49
+#define AU1000_GPIO_18 50
+#define AU1000_GPIO_19 51
+#define AU1000_GPIO_20 52
+#define AU1000_GPIO_21 53
+#define AU1000_GPIO_22 54
+#define AU1000_GPIO_23 55
+#define AU1000_GPIO_24 56
+#define AU1000_GPIO_25 57
+#define AU1000_GPIO_26 58
+#define AU1000_GPIO_27 59
+#define AU1000_GPIO_28 60
+#define AU1000_GPIO_29 61
+#define AU1000_GPIO_30 62
+#define AU1000_GPIO_31 63
+
+/* Au1500 only */
+#define AU1500_GPIO_200 48
+#define AU1500_GPIO_201 49
+#define AU1500_GPIO_202 50
+#define AU1500_GPIO_203 51
+#define AU1500_GPIO_20 52
+#define AU1500_GPIO_204 53
+#define AU1500_GPIO_205 54
+#define AU1500_GPIO_23 55
+#define AU1500_GPIO_24 56
+#define AU1500_GPIO_25 57
+#define AU1500_GPIO_26 58
+#define AU1500_GPIO_27 59
+#define AU1500_GPIO_28 60
+#define AU1500_GPIO_206 61
+#define AU1500_GPIO_207 62
+#define AU1500_GPIO_208_215 63
+
+#define AU1X00_MAX_INTR 63
+
+#define AU1100_SD 2
+#define AU1100_GPIO_208_215 29
+/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
+
+/* Programmable Counters 0 and 1 */
+#define SYS_BASE 0xB1900000
+#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
+#define SYS_CNTRL_E1S (1<<23)
+#define SYS_CNTRL_T1S (1<<20)
+#define SYS_CNTRL_M21 (1<<19)
+#define SYS_CNTRL_M11 (1<<18)
+#define SYS_CNTRL_M01 (1<<17)
+#define SYS_CNTRL_C1S (1<<16)
+#define SYS_CNTRL_BP (1<<14)
+#define SYS_CNTRL_EN1 (1<<13)
+#define SYS_CNTRL_BT1 (1<<12)
+#define SYS_CNTRL_EN0 (1<<11)
+#define SYS_CNTRL_BT0 (1<<10)
+#define SYS_CNTRL_E0 (1<<8)
+#define SYS_CNTRL_E0S (1<<7)
+#define SYS_CNTRL_32S (1<<5)
+#define SYS_CNTRL_T0S (1<<4)
+#define SYS_CNTRL_M20 (1<<3)
+#define SYS_CNTRL_M10 (1<<2)
+#define SYS_CNTRL_M00 (1<<1)
+#define SYS_CNTRL_C0S (1<<0)
+
+/* Programmable Counter 0 Registers */
+#define SYS_TOYTRIM (SYS_BASE + 0)
+#define SYS_TOYWRITE (SYS_BASE + 4)
+#define SYS_TOYMATCH0 (SYS_BASE + 8)
+#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
+#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
+#define SYS_TOYREAD (SYS_BASE + 0x40)
+
+/* Programmable Counter 1 Registers */
+#define SYS_RTCTRIM (SYS_BASE + 0x44)
+#define SYS_RTCWRITE (SYS_BASE + 0x48)
+#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
+#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
+#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
+#define SYS_RTCREAD (SYS_BASE + 0x58)
+
+/* I2S Controller */
+#define I2S_DATA 0xB1000000
+#define I2S_DATA_MASK (0xffffff)
+#define I2S_CONFIG 0xB1000004
+#define I2S_CONFIG_XU (1<<25)
+#define I2S_CONFIG_XO (1<<24)
+#define I2S_CONFIG_RU (1<<23)
+#define I2S_CONFIG_RO (1<<22)
+#define I2S_CONFIG_TR (1<<21)
+#define I2S_CONFIG_TE (1<<20)
+#define I2S_CONFIG_TF (1<<19)
+#define I2S_CONFIG_RR (1<<18)
+#define I2S_CONFIG_RE (1<<17)
+#define I2S_CONFIG_RF (1<<16)
+#define I2S_CONFIG_PD (1<<11)
+#define I2S_CONFIG_LB (1<<10)
+#define I2S_CONFIG_IC (1<<9)
+#define I2S_CONFIG_FM_BIT 7
+#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
+#define I2S_CONFIG_TN (1<<6)
+#define I2S_CONFIG_RN (1<<5)
+#define I2S_CONFIG_SZ_BIT 0
+#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
+
+#define I2S_CONTROL 0xB1000008
+#define I2S_CONTROL_D (1<<1)
+#define I2S_CONTROL_CE (1<<0)
+
+/* USB Host Controller */
+/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
+#define USB_OHCI_BASE 0x10100000
+#define USB_OHCI_LEN 0x00100000
+#define USB_HOST_CONFIG 0xB017fffc
+
+/* USB Device Controller */
+#define USBD_EP0RD 0xB0200000
+#define USBD_EP0WR 0xB0200004
+#define USBD_EP2WR 0xB0200008
+#define USBD_EP3WR 0xB020000C
+#define USBD_EP4RD 0xB0200010
+#define USBD_EP5RD 0xB0200014
+#define USBD_INTEN 0xB0200018
+#define USBD_INTSTAT 0xB020001C
+#define USBDEV_INT_SOF (1<<12)
+#define USBDEV_INT_HF_BIT 6
+#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
+#define USBDEV_INT_CMPLT_BIT 0
+#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
+#define USBD_CONFIG 0xB0200020
+#define USBD_EP0CS 0xB0200024
+#define USBD_EP2CS 0xB0200028
+#define USBD_EP3CS 0xB020002C
+#define USBD_EP4CS 0xB0200030
+#define USBD_EP5CS 0xB0200034
+#define USBDEV_CS_SU (1<<14)
+#define USBDEV_CS_NAK (1<<13)
+#define USBDEV_CS_ACK (1<<12)
+#define USBDEV_CS_BUSY (1<<11)
+#define USBDEV_CS_TSIZE_BIT 1
+#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
+#define USBDEV_CS_STALL (1<<0)
+#define USBD_EP0RDSTAT 0xB0200040
+#define USBD_EP0WRSTAT 0xB0200044
+#define USBD_EP2WRSTAT 0xB0200048
+#define USBD_EP3WRSTAT 0xB020004C
+#define USBD_EP4RDSTAT 0xB0200050
+#define USBD_EP5RDSTAT 0xB0200054
+#define USBDEV_FSTAT_FLUSH (1<<6)
+#define USBDEV_FSTAT_UF (1<<5)
+#define USBDEV_FSTAT_OF (1<<4)
+#define USBDEV_FSTAT_FCNT_BIT 0
+#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
+#define USBD_ENABLE 0xB0200058
+#define USBDEV_ENABLE (1<<1)
+#define USBDEV_CE (1<<0)
+
+/* Ethernet Controllers */
+#define AU1000_ETH0_BASE 0xB0500000
+#define AU1000_ETH1_BASE 0xB0510000
+#define AU1500_ETH0_BASE 0xB1500000
+#define AU1500_ETH1_BASE 0xB1510000
+#define AU1100_ETH0_BASE 0xB0500000
+
+/* 4 byte offsets from AU1000_ETH_BASE */
+#define MAC_CONTROL 0x0
+#define MAC_RX_ENABLE (1<<2)
+#define MAC_TX_ENABLE (1<<3)
+#define MAC_DEF_CHECK (1<<5)
+#define MAC_SET_BL(X) (((X)&0x3)<<6)
+#define MAC_AUTO_PAD (1<<8)
+#define MAC_DISABLE_RETRY (1<<10)
+#define MAC_DISABLE_BCAST (1<<11)
+#define MAC_LATE_COL (1<<12)
+#define MAC_HASH_MODE (1<<13)
+#define MAC_HASH_ONLY (1<<15)
+#define MAC_PASS_ALL (1<<16)
+#define MAC_INVERSE_FILTER (1<<17)
+#define MAC_PROMISCUOUS (1<<18)
+#define MAC_PASS_ALL_MULTI (1<<19)
+#define MAC_FULL_DUPLEX (1<<20)
+#define MAC_NORMAL_MODE 0
+#define MAC_INT_LOOPBACK (1<<21)
+#define MAC_EXT_LOOPBACK (1<<22)
+#define MAC_DISABLE_RX_OWN (1<<23)
+#define MAC_BIG_ENDIAN (1<<30)
+#define MAC_RX_ALL (1<<31)
+#define MAC_ADDRESS_HIGH 0x4
+#define MAC_ADDRESS_LOW 0x8
+#define MAC_MCAST_HIGH 0xC
+#define MAC_MCAST_LOW 0x10
+#define MAC_MII_CNTRL 0x14
+#define MAC_MII_BUSY (1<<0)
+#define MAC_MII_READ 0
+#define MAC_MII_WRITE (1<<1)
+#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
+#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
+#define MAC_MII_DATA 0x18
+#define MAC_FLOW_CNTRL 0x1C
+#define MAC_FLOW_CNTRL_BUSY (1<<0)
+#define MAC_FLOW_CNTRL_ENABLE (1<<1)
+#define MAC_PASS_CONTROL (1<<2)
+#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
+#define MAC_VLAN1_TAG 0x20
+#define MAC_VLAN2_TAG 0x24
+
+/* Ethernet Controller Enable */
+#define AU1000_MAC0_ENABLE 0xB0520000
+#define AU1000_MAC1_ENABLE 0xB0520004
+#define AU1500_MAC0_ENABLE 0xB1520000
+#define AU1500_MAC1_ENABLE 0xB1520004
+#define AU1100_MAC0_ENABLE 0xB0520000
+
+#define MAC_EN_CLOCK_ENABLE (1<<0)
+#define MAC_EN_RESET0 (1<<1)
+#define MAC_EN_TOSS (0<<2)
+#define MAC_EN_CACHEABLE (1<<3)
+#define MAC_EN_RESET1 (1<<4)
+#define MAC_EN_RESET2 (1<<5)
+#define MAC_DMA_RESET (1<<6)
+
+/* Ethernet Controller DMA Channels */
+
+#define MAC0_TX_DMA_ADDR 0xB4004000
+#define MAC1_TX_DMA_ADDR 0xB4004200
+/* offsets from MAC_TX_RING_ADDR address */
+#define MAC_TX_BUFF0_STATUS 0x0
+#define TX_FRAME_ABORTED (1<<0)
+#define TX_JAB_TIMEOUT (1<<1)
+#define TX_NO_CARRIER (1<<2)
+#define TX_LOSS_CARRIER (1<<3)
+#define TX_EXC_DEF (1<<4)
+#define TX_LATE_COLL_ABORT (1<<5)
+#define TX_EXC_COLL (1<<6)
+#define TX_UNDERRUN (1<<7)
+#define TX_DEFERRED (1<<8)
+#define TX_LATE_COLL (1<<9)
+#define TX_COLL_CNT_MASK (0xF<<10)
+#define TX_PKT_RETRY (1<<31)
+#define MAC_TX_BUFF0_ADDR 0x4
+#define TX_DMA_ENABLE (1<<0)
+#define TX_T_DONE (1<<1)
+#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
+#define MAC_TX_BUFF0_LEN 0x8
+#define MAC_TX_BUFF1_STATUS 0x10
+#define MAC_TX_BUFF1_ADDR 0x14
+#define MAC_TX_BUFF1_LEN 0x18
+#define MAC_TX_BUFF2_STATUS 0x20
+#define MAC_TX_BUFF2_ADDR 0x24
+#define MAC_TX_BUFF2_LEN 0x28
+#define MAC_TX_BUFF3_STATUS 0x30
+#define MAC_TX_BUFF3_ADDR 0x34
+#define MAC_TX_BUFF3_LEN 0x38
+
+#define MAC0_RX_DMA_ADDR 0xB4004100
+#define MAC1_RX_DMA_ADDR 0xB4004300
+/* offsets from MAC_RX_RING_ADDR */
+#define MAC_RX_BUFF0_STATUS 0x0
+#define RX_FRAME_LEN_MASK 0x3fff
+#define RX_WDOG_TIMER (1<<14)
+#define RX_RUNT (1<<15)
+#define RX_OVERLEN (1<<16)
+#define RX_COLL (1<<17)
+#define RX_ETHER (1<<18)
+#define RX_MII_ERROR (1<<19)
+#define RX_DRIBBLING (1<<20)
+#define RX_CRC_ERROR (1<<21)
+#define RX_VLAN1 (1<<22)
+#define RX_VLAN2 (1<<23)
+#define RX_LEN_ERROR (1<<24)
+#define RX_CNTRL_FRAME (1<<25)
+#define RX_U_CNTRL_FRAME (1<<26)
+#define RX_MCAST_FRAME (1<<27)
+#define RX_BCAST_FRAME (1<<28)
+#define RX_FILTER_FAIL (1<<29)
+#define RX_PACKET_FILTER (1<<30)
+#define RX_MISSED_FRAME (1<<31)
+
+#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
+ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+#define MAC_RX_BUFF0_ADDR 0x4
+#define RX_DMA_ENABLE (1<<0)
+#define RX_T_DONE (1<<1)
+#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
+#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
+#define MAC_RX_BUFF1_STATUS 0x10
+#define MAC_RX_BUFF1_ADDR 0x14
+#define MAC_RX_BUFF2_STATUS 0x20
+#define MAC_RX_BUFF2_ADDR 0x24
+#define MAC_RX_BUFF3_STATUS 0x30
+#define MAC_RX_BUFF3_ADDR 0x34
+
+
+/* UARTS 0-3 */
+#define UART0_ADDR 0xB1100000
+#define UART1_ADDR 0xB1200000
+#define UART2_ADDR 0xB1300000
+#define UART3_ADDR 0xB1400000
+#define UART_BASE UART0_ADDR
+#define UART_DEBUG_BASE UART2_ADDR
+
+#define UART_RX 0 /* Receive buffer */
+#define UART_TX 4 /* Transmit buffer */
+#define UART_IER 8 /* Interrupt Enable Register */
+#define UART_IIR 0xC /* Interrupt ID Register */
+#define UART_FCR 0x10 /* FIFO Control Register */
+#define UART_LCR 0x14 /* Line Control Register */
+#define UART_MCR 0x18 /* Modem Control Register */
+#define UART_LSR 0x1C /* Line Status Register */
+#define UART_MSR 0x20 /* Modem Status Register */
+#define UART_CLK 0x28 /* Baud Rate Clock Divider */
+#define UART_ENABLE 0x100 /* Uart enable */
+
+#define UART_EN_CE 1 /* Clock enable */
+#define UART_EN_E 2 /* Enable */
+
+#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
+#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
+#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
+#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
+#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
+#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_SBC 0x40 /* Set break control */
+#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
+#define UART_LCR_EPAR 0x10 /* Even parity select */
+#define UART_LCR_PARITY 0x08 /* Parity Enable */
+#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT 0x40 /* Transmitter empty */
+#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
+#define UART_LSR_BI 0x10 /* Break interrupt indicator */
+#define UART_LSR_FE 0x08 /* Frame error indicator */
+#define UART_LSR_PE 0x04 /* Parity error indicator */
+#define UART_LSR_OE 0x02 /* Overrun error indicator */
+#define UART_LSR_DR 0x01 /* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2 0x08 /* Out2 complement */
+#define UART_MCR_OUT1 0x04 /* Out1 complement */
+#define UART_MCR_RTS 0x02 /* RTS complement */
+#define UART_MCR_DTR 0x01 /* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
+
+
+
+/* SSIO */
+#define SSI0_STATUS 0xB1600000
+#define SSI_STATUS_BF (1<<4)
+#define SSI_STATUS_OF (1<<3)
+#define SSI_STATUS_UF (1<<2)
+#define SSI_STATUS_D (1<<1)
+#define SSI_STATUS_B (1<<0)
+#define SSI0_INT 0xB1600004
+#define SSI_INT_OI (1<<3)
+#define SSI_INT_UI (1<<2)
+#define SSI_INT_DI (1<<1)
+#define SSI0_INT_ENABLE 0xB1600008
+#define SSI_INTE_OIE (1<<3)
+#define SSI_INTE_UIE (1<<2)
+#define SSI_INTE_DIE (1<<1)
+#define SSI0_CONFIG 0xB1600020
+#define SSI_CONFIG_AO (1<<24)
+#define SSI_CONFIG_DO (1<<23)
+#define SSI_CONFIG_ALEN_BIT 20
+#define SSI_CONFIG_ALEN_MASK (0x7<<20)
+#define SSI_CONFIG_DLEN_BIT 16
+#define SSI_CONFIG_DLEN_MASK (0x7<<16)
+#define SSI_CONFIG_DD (1<<11)
+#define SSI_CONFIG_AD (1<<10)
+#define SSI_CONFIG_BM_BIT 8
+#define SSI_CONFIG_BM_MASK (0x3<<8)
+#define SSI_CONFIG_CE (1<<7)
+#define SSI_CONFIG_DP (1<<6)
+#define SSI_CONFIG_DL (1<<5)
+#define SSI_CONFIG_EP (1<<4)
+#define SSI0_ADATA 0xB1600024
+#define SSI_AD_D (1<<24)
+#define SSI_AD_ADDR_BIT 16
+#define SSI_AD_ADDR_MASK (0xff<<16)
+#define SSI_AD_DATA_BIT 0
+#define SSI_AD_DATA_MASK (0xfff<<0)
+#define SSI0_CLKDIV 0xB1600028
+#define SSI0_CONTROL 0xB1600100
+#define SSI_CONTROL_CD (1<<1)
+#define SSI_CONTROL_E (1<<0)
+
+/* SSI1 */
+#define SSI1_STATUS 0xB1680000
+#define SSI1_INT 0xB1680004
+#define SSI1_INT_ENABLE 0xB1680008
+#define SSI1_CONFIG 0xB1680020
+#define SSI1_ADATA 0xB1680024
+#define SSI1_CLKDIV 0xB1680028
+#define SSI1_ENABLE 0xB1680100
+
+/*
+ * Register content definitions
+ */
+#define SSI_STATUS_BF (1<<4)
+#define SSI_STATUS_OF (1<<3)
+#define SSI_STATUS_UF (1<<2)
+#define SSI_STATUS_D (1<<1)
+#define SSI_STATUS_B (1<<0)
+
+/* SSI_INT */
+#define SSI_INT_OI (1<<3)
+#define SSI_INT_UI (1<<2)
+#define SSI_INT_DI (1<<1)
+
+/* SSI_INTEN */
+#define SSI_INTEN_OIE (1<<3)
+#define SSI_INTEN_UIE (1<<2)
+#define SSI_INTEN_DIE (1<<1)
+
+#define SSI_CONFIG_AO (1<<24)
+#define SSI_CONFIG_DO (1<<23)
+#define SSI_CONFIG_ALEN (7<<20)
+#define SSI_CONFIG_DLEN (15<<16)
+#define SSI_CONFIG_DD (1<<11)
+#define SSI_CONFIG_AD (1<<10)
+#define SSI_CONFIG_BM (3<<8)
+#define SSI_CONFIG_CE (1<<7)
+#define SSI_CONFIG_DP (1<<6)
+#define SSI_CONFIG_DL (1<<5)
+#define SSI_CONFIG_EP (1<<4)
+#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
+#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
+#define SSI_CONFIG_BM_HI (0<<8)
+#define SSI_CONFIG_BM_LO (1<<8)
+#define SSI_CONFIG_BM_CY (2<<8)
+
+#define SSI_ADATA_D (1<<24)
+#define SSI_ADATA_ADDR (0xFF<<16)
+#define SSI_ADATA_DATA (0x0FFF)
+#define SSI_ADATA_ADDR_N(N) (N<<16)
+
+#define SSI_ENABLE_CD (1<<1)
+#define SSI_ENABLE_E (1<<0)
+
+
+/* IrDA Controller */
+#define IRDA_BASE 0xB0300000
+#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
+#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
+#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
+#define IR_RING_SIZE (IRDA_BASE+0x0C)
+#define IR_RING_PROMPT (IRDA_BASE+0x10)
+#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
+#define IR_INT_CLEAR (IRDA_BASE+0x18)
+#define IR_CONFIG_1 (IRDA_BASE+0x20)
+#define IR_RX_INVERT_LED (1<<0)
+#define IR_TX_INVERT_LED (1<<1)
+#define IR_ST (1<<2)
+#define IR_SF (1<<3)
+#define IR_SIR (1<<4)
+#define IR_MIR (1<<5)
+#define IR_FIR (1<<6)
+#define IR_16CRC (1<<7)
+#define IR_TD (1<<8)
+#define IR_RX_ALL (1<<9)
+#define IR_DMA_ENABLE (1<<10)
+#define IR_RX_ENABLE (1<<11)
+#define IR_TX_ENABLE (1<<12)
+#define IR_LOOPBACK (1<<14)
+#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
+ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS (IRDA_BASE+0x24)
+#define IR_ENABLE (IRDA_BASE+0x28)
+#define IR_RX_STATUS (1<<9)
+#define IR_TX_STATUS (1<<10)
+#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
+#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
+#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
+#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
+#define IR_CONFIG_2 (IRDA_BASE+0x3C)
+#define IR_MODE_INV (1<<0)
+#define IR_ONE_PIN (1<<1)
+#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
+
+/* GPIO */
+#define SYS_PINFUNC 0xB190002C
+#define SYS_PF_USB (1<<15) /* 2nd USB device/host */
+#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
+#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
+#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
+#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
+#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
+#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
+#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
+#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
+#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
+#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
+#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
+#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
+#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
+#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
+#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
+#define SYS_TRIOUTRD 0xB1900100
+#define SYS_TRIOUTCLR 0xB1900100
+#define SYS_OUTPUTRD 0xB1900108
+#define SYS_OUTPUTSET 0xB1900108
+#define SYS_OUTPUTCLR 0xB190010C
+#define SYS_PINSTATERD 0xB1900110
+#define SYS_PININPUTEN 0xB1900110
+
+/* GPIO2, Au1500 only */
+#define GPIO2_BASE 0xB1700000
+#define GPIO2_DIR (GPIO2_BASE + 0)
+#define GPIO2_DATA_EN (GPIO2_BASE + 8)
+#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
+#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
+#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
+
+/* Power Management */
+#define SYS_SCRATCH0 0xB1900018
+#define SYS_SCRATCH1 0xB190001C
+#define SYS_WAKEMSK 0xB1900034
+#define SYS_ENDIAN 0xB1900038
+#define SYS_POWERCTRL 0xB190003C
+#define SYS_WAKESRC 0xB190005C
+#define SYS_SLPPWR 0xB1900078
+#define SYS_SLEEP 0xB190007C
+
+/* Clock Controller */
+#define SYS_FREQCTRL0 0xB1900020
+#define SYS_FC_FRDIV2_BIT 22
+#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
+#define SYS_FC_FE2 (1<<21)
+#define SYS_FC_FS2 (1<<20)
+#define SYS_FC_FRDIV1_BIT 12
+#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
+#define SYS_FC_FE1 (1<<11)
+#define SYS_FC_FS1 (1<<10)
+#define SYS_FC_FRDIV0_BIT 2
+#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
+#define SYS_FC_FE0 (1<<1)
+#define SYS_FC_FS0 (1<<0)
+#define SYS_FREQCTRL1 0xB1900024
+#define SYS_FC_FRDIV5_BIT 22
+#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
+#define SYS_FC_FE5 (1<<21)
+#define SYS_FC_FS5 (1<<20)
+#define SYS_FC_FRDIV4_BIT 12
+#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
+#define SYS_FC_FE4 (1<<11)
+#define SYS_FC_FS4 (1<<10)
+#define SYS_FC_FRDIV3_BIT 2
+#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
+#define SYS_FC_FE3 (1<<1)
+#define SYS_FC_FS3 (1<<0)
+#define SYS_CLKSRC 0xB1900028
+#define SYS_CS_ME1_BIT 27
+#define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
+#define SYS_CS_DE1 (1<<26)
+#define SYS_CS_CE1 (1<<25)
+#define SYS_CS_ME0_BIT 22
+#define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
+#define SYS_CS_DE0 (1<<21)
+#define SYS_CS_CE0 (1<<20)
+#define SYS_CS_MI2_BIT 17
+#define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
+#define SYS_CS_DI2 (1<<16)
+#define SYS_CS_CI2 (1<<15)
+#define SYS_CS_MUH_BIT 12
+#define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
+#define SYS_CS_DUH (1<<11)
+#define SYS_CS_CUH (1<<10)
+#define SYS_CS_MUD_BIT 7
+#define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
+#define SYS_CS_DUD (1<<6)
+#define SYS_CS_CUD (1<<5)
+#define SYS_CS_MIR_BIT 2
+#define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
+#define SYS_CS_DIR (1<<1)
+#define SYS_CS_CIR (1<<0)
+
+#define SYS_CS_MUX_AUX 0x1
+#define SYS_CS_MUX_FQ0 0x2
+#define SYS_CS_MUX_FQ1 0x3
+#define SYS_CS_MUX_FQ2 0x4
+#define SYS_CS_MUX_FQ3 0x5
+#define SYS_CS_MUX_FQ4 0x6
+#define SYS_CS_MUX_FQ5 0x7
+#define SYS_CPUPLL 0xB1900060
+#define SYS_AUXPLL 0xB1900064
+
+/* AC97 Controller */
+#define AC97C_CONFIG 0xB0000000
+#define AC97C_RECV_SLOTS_BIT 13
+#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
+#define AC97C_XMIT_SLOTS_BIT 3
+#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
+#define AC97C_SG (1<<2)
+#define AC97C_SYNC (1<<1)
+#define AC97C_RESET (1<<0)
+#define AC97C_STATUS 0xB0000004
+#define AC97C_XU (1<<11)
+#define AC97C_XO (1<<10)
+#define AC97C_RU (1<<9)
+#define AC97C_RO (1<<8)
+#define AC97C_READY (1<<7)
+#define AC97C_CP (1<<6)
+#define AC97C_TR (1<<5)
+#define AC97C_TE (1<<4)
+#define AC97C_TF (1<<3)
+#define AC97C_RR (1<<2)
+#define AC97C_RE (1<<1)
+#define AC97C_RF (1<<0)
+#define AC97C_DATA 0xB0000008
+#define AC97C_CMD 0xB000000C
+#define AC97C_WD_BIT 16
+#define AC97C_READ (1<<7)
+#define AC97C_INDEX_MASK 0x7f
+#define AC97C_CNTRL 0xB0000010
+#define AC97C_RS (1<<1)
+#define AC97C_CE (1<<0)
+
+#ifdef CONFIG_SOC_AU1500
+/* Au1500 PCI Controller */
+#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
+#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
+#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
+#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
+#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
+#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
+#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
+#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
+#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
+#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
+#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
+#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
+#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
+#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
+#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
+#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
+
+#define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */
+
+/* All of our structures, like pci resource, have 32 bit members.
+ * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
+ * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
+ * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
+ * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
+ * addresses. For PCI IO, it's simpler because we get to do the ioremap
+ * ourselves and then adjust the device's resources.
+ */
+#define Au1500_EXT_CFG 0x600000000
+#define Au1500_EXT_CFG_TYPE1 0x680000000
+#define Au1500_PCI_IO_START 0x500000000
+#define Au1500_PCI_IO_END 0x5000FFFFF
+#define Au1500_PCI_MEM_START 0x440000000
+#define Au1500_PCI_MEM_END 0x443FFFFFF
+
+#define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
+#define PCI_IO_END (Au1500_PCI_IO_END)
+#define PCI_MEM_START (Au1500_PCI_MEM_START)
+#define PCI_MEM_END (Au1500_PCI_MEM_END)
+#define PCI_FIRST_DEVFN (0<<3)
+#define PCI_LAST_DEVFN (19<<3)
+
+#endif
+
+#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
+/* no PCI bus controller */
+#define PCI_IO_START 0
+#define PCI_IO_END 0
+#define PCI_MEM_START 0
+#define PCI_MEM_END 0
+#define PCI_FIRST_DEVFN 0
+#define PCI_LAST_DEVFN 0
+#endif
+#define AU1X_SOCK0_IO 0xF00000000
+#define AU1X_SOCK0_PHYS_ATTR 0xF40000000
+#define AU1X_SOCK0_PHYS_MEM 0xF80000000
+
+/* pcmcia socket 1 needs external glue logic so the memory map
+ * differs from board to board.
+ */
+
+/* Only for db board, not older pb */
+#define AU1X_SOCK1_IO 0xF04000000
+#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
+#define AU1X_SOCK1_PHYS_MEM 0xF84000000
+
+#endif
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2003 Maciej W. Rozycki
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
:"=r" (__res)); \
__res;})
+#define tlb_write_indexed() \
+ __asm__ __volatile__( \
+ ".set noreorder\n\t" \
+ "tlbwi\n\t" \
+".set reorder")
+
/*
* R4x00 interrupt enable / cause bits
*/
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
+#define CONFIG_DBAU1X00 1
+#define CONFIG_AU1X00 1 /* alchemy series cpu */
+
+/* Also known as Merlot */
+#define CONFIG_DBAU1000 1 /* board, Hardcoded for now */
+#define CONFIG_AU1000 1 /* cpu, Hardcoded for now */
+
+#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
+
+#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs $(bootargs) " \
+ "console=ttyS0,$(baudrate) " \
+ "panic=1\0" \
+ "bootfile=/tftpboot/vmlinux.srec\0" \
+ "load=tftp 80500000 $(u-boot)\0" \
+ ""
+/* Boot from Compact flash partition 2 as default */
+#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm"
+
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
+ CFG_CMD_IDE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ELF ) & \
+ ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
+ CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
+ CFG_CMD_BDI | CFG_CMD_BEDBUG))
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "DbAu1x00 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args*/
+
+#define CFG_MALLOC_LEN 128*1024
+
+#define CFG_BOOTPARAMS_LEN 128*1024
+
+#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */
+
+#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
+
+#define CFG_LOAD_ADDR 0x81000000 /* default load address */
+
+#define CFG_MEMTEST_START 0x80100000
+#define CFG_MEMTEST_END 0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
+
+#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
+
+/* The following #defines are needed to get flash environment right */
+#define CFG_MONITOR_BASE TEXT_BASE
+#define CFG_MONITOR_LEN (192 << 10)
+
+#define CFG_INIT_SP_OFFSET 0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CFG_FLASH_BASE PHYS_FLASH_2
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
+
+#define CFG_ENV_IS_NOWHERE 1
+
+/* Address and size of Primary Environment Sector */
+#define CFG_ENV_ADDR 0xB0030000
+#define CFG_ENV_SIZE 0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+/*---ATA PCMCIA ------------------------------------*/
+#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CFG_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CONFIG_ATAPI 1
+#define CONFIG_MAC_PARTITION 1
+
+/* We run CF in "true ide" mode or a harddrive via pcmcia */
+#define CONFIG_IDE_PCMCIA 1
+
+/* We only support one slot for now */
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+#undef CONFIG_IDE_RESET /* reset for ide not supported */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET 8
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET 0
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET 0x0100
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 16384
+#define CFG_ICACHE_SIZE 16384
+#define CFG_CACHELINE_SIZE 32
+
+#define DB1000_BCSR_ADDR 0xAE000000
+
+#endif /* __CONFIG_H */
static void linux_env_set (char * env_name, char * env_val);
-void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
- ulong addr, ulong *len_ptr, int verify)
+void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
+ ulong addr, ulong * len_ptr, int verify)
{
- DECLARE_GLOBAL_DATA_PTR;
+ DECLARE_GLOBAL_DATA_PTR;
- ulong len = 0, checksum;
- ulong initrd_start, initrd_end;
- ulong data;
- void (*theKernel)(int, char **, char **, int *);
- image_header_t *hdr = &header;
- char *commandline = getenv("bootargs");
- char env_buf[12];
+ ulong len = 0, checksum;
+ ulong initrd_start, initrd_end;
+ ulong data;
+ void (*theKernel) (int, char **, char **, int *);
+ image_header_t *hdr = &header;
+ char *commandline = getenv ("bootargs");
+ char env_buf[12];
- theKernel = (void (*)(int, char **, char **, int *))ntohl(hdr->ih_ep);
-
- /*
- * Check if there is an initrd image
- */
- if (argc >= 3) {
- SHOW_BOOT_PROGRESS (9);
-
- addr = simple_strtoul(argv[2], NULL, 16);
-
- printf ("## Loading Ramdisk Image at %08lx ...\n", addr);
-
- /* Copy header so we can blank CRC field for re-calculation */
- memcpy (&header, (char *)addr, sizeof(image_header_t));
-
- if (ntohl(hdr->ih_magic) != IH_MAGIC) {
- printf ("Bad Magic Number\n");
- SHOW_BOOT_PROGRESS (-10);
- do_reset (cmdtp, flag, argc, argv);
- }
-
- data = (ulong)&header;
- len = sizeof(image_header_t);
-
- checksum = ntohl(hdr->ih_hcrc);
- hdr->ih_hcrc = 0;
-
- if (crc32 (0, (char *)data, len) != checksum) {
- printf ("Bad Header Checksum\n");
- SHOW_BOOT_PROGRESS (-11);
- do_reset (cmdtp, flag, argc, argv);
- }
-
- SHOW_BOOT_PROGRESS (10);
-
- print_image_hdr (hdr);
-
- data = addr + sizeof(image_header_t);
- len = ntohl(hdr->ih_size);
-
- if (verify) {
- ulong csum = 0;
-
- printf (" Verifying Checksum ... ");
- csum = crc32 (0, (char *)data, len);
- if (csum != ntohl(hdr->ih_dcrc)) {
- printf ("Bad Data CRC\n");
- SHOW_BOOT_PROGRESS (-12);
- do_reset (cmdtp, flag, argc, argv);
- }
- printf ("OK\n");
- }
-
- SHOW_BOOT_PROGRESS (11);
-
- if ((hdr->ih_os != IH_OS_LINUX) ||
- (hdr->ih_arch != IH_CPU_MIPS) ||
- (hdr->ih_type != IH_TYPE_RAMDISK) ) {
- printf ("No Linux MIPS Ramdisk Image\n");
- SHOW_BOOT_PROGRESS (-13);
- do_reset (cmdtp, flag, argc, argv);
- }
+ theKernel =
+ (void (*)(int, char **, char **, int *)) ntohl (hdr->ih_ep);
/*
- * Now check if we have a multifile image
+ * Check if there is an initrd image
*/
- } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) {
- ulong tail = ntohl(len_ptr[0]) % 4;
- int i;
-
- SHOW_BOOT_PROGRESS (13);
-
- /* skip kernel length and terminator */
- data = (ulong)(&len_ptr[2]);
- /* skip any additional image length fields */
- for (i=1; len_ptr[i]; ++i)
- data += 4;
- /* add kernel length, and align */
- data += ntohl(len_ptr[0]);
- if (tail) {
- data += 4 - tail;
+ if (argc >= 3) {
+ SHOW_BOOT_PROGRESS (9);
+
+ addr = simple_strtoul (argv[2], NULL, 16);
+
+ printf ("## Loading Ramdisk Image at %08lx ...\n", addr);
+
+ /* Copy header so we can blank CRC field for re-calculation */
+ memcpy (&header, (char *) addr, sizeof (image_header_t));
+
+ if (ntohl (hdr->ih_magic) != IH_MAGIC) {
+ printf ("Bad Magic Number\n");
+ SHOW_BOOT_PROGRESS (-10);
+ do_reset (cmdtp, flag, argc, argv);
+ }
+
+ data = (ulong) & header;
+ len = sizeof (image_header_t);
+
+ checksum = ntohl (hdr->ih_hcrc);
+ hdr->ih_hcrc = 0;
+
+ if (crc32 (0, (char *) data, len) != checksum) {
+ printf ("Bad Header Checksum\n");
+ SHOW_BOOT_PROGRESS (-11);
+ do_reset (cmdtp, flag, argc, argv);
+ }
+
+ SHOW_BOOT_PROGRESS (10);
+
+ print_image_hdr (hdr);
+
+ data = addr + sizeof (image_header_t);
+ len = ntohl (hdr->ih_size);
+
+ if (verify) {
+ ulong csum = 0;
+
+ printf (" Verifying Checksum ... ");
+ csum = crc32 (0, (char *) data, len);
+ if (csum != ntohl (hdr->ih_dcrc)) {
+ printf ("Bad Data CRC\n");
+ SHOW_BOOT_PROGRESS (-12);
+ do_reset (cmdtp, flag, argc, argv);
+ }
+ printf ("OK\n");
+ }
+
+ SHOW_BOOT_PROGRESS (11);
+
+ if ((hdr->ih_os != IH_OS_LINUX) ||
+ (hdr->ih_arch != IH_CPU_MIPS) ||
+ (hdr->ih_type != IH_TYPE_RAMDISK)) {
+ printf ("No Linux MIPS Ramdisk Image\n");
+ SHOW_BOOT_PROGRESS (-13);
+ do_reset (cmdtp, flag, argc, argv);
+ }
+
+ /*
+ * Now check if we have a multifile image
+ */
+ } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
+ ulong tail = ntohl (len_ptr[0]) % 4;
+ int i;
+
+ SHOW_BOOT_PROGRESS (13);
+
+ /* skip kernel length and terminator */
+ data = (ulong) (&len_ptr[2]);
+ /* skip any additional image length fields */
+ for (i = 1; len_ptr[i]; ++i)
+ data += 4;
+ /* add kernel length, and align */
+ data += ntohl (len_ptr[0]);
+ if (tail) {
+ data += 4 - tail;
+ }
+
+ len = ntohl (len_ptr[1]);
+
+ } else {
+ /*
+ * no initrd image
+ */
+ SHOW_BOOT_PROGRESS (14);
+
+ data = 0;
}
- len = ntohl(len_ptr[1]);
-
- } else {
- /*
- * no initrd image
- */
- SHOW_BOOT_PROGRESS (14);
-
- data = 0;
- }
-
#ifdef DEBUG
- if (!data) {
- printf ("No initrd\n");
- }
+ if (!data) {
+ printf ("No initrd\n");
+ }
#endif
- if (data) {
- initrd_start = data;
- initrd_end = initrd_start + len;
- } else {
- initrd_start = 0;
- initrd_end = 0;
- }
+ if (data) {
+ initrd_start = data;
+ initrd_end = initrd_start + len;
+ } else {
+ initrd_start = 0;
+ initrd_end = 0;
+ }
- SHOW_BOOT_PROGRESS (15);
+ SHOW_BOOT_PROGRESS (15);
#ifdef DEBUG
- printf ("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong)theKernel);
+ printf ("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) theKernel);
#endif
- linux_params_init (PHYSADDR(gd->bd->bi_boot_params), commandline);
+ linux_params_init (PHYSADDR (gd->bd->bi_boot_params), commandline);
+
+#ifdef CONFIG_MEMSIZE_IN_BYTES
+ sprintf (env_buf, "%lu", gd->ram_size);
+#ifdef DEBUG
+ printf ("## Giving linux memsize in bytes, %lu\n", gd->ram_size);
+#endif
+#else
+ sprintf (env_buf, "%lu", gd->ram_size >> 20);
+#ifdef DEBUG
+ printf ("## Giving linux memsize in MB, %lu\n", gd->ram_size >> 20);
+#endif
+#endif /* CONFIG_MEMSIZE_IN_BYTES */
- sprintf (env_buf, "%lu", gd->ram_size >> 20);
- linux_env_set ("memsize", env_buf);
+ linux_env_set ("memsize", env_buf);
- sprintf (env_buf, "0x%08X", (uint)PHYSADDR(initrd_start));
- linux_env_set ("initrd_start", env_buf);
+ sprintf (env_buf, "0x%08X", (uint) PHYSADDR (initrd_start));
+ linux_env_set ("initrd_start", env_buf);
- sprintf (env_buf, "0x%X", (uint)(initrd_end - initrd_start));
- linux_env_set ("initrd_size", env_buf);
+ sprintf (env_buf, "0x%X", (uint) (initrd_end - initrd_start));
+ linux_env_set ("initrd_size", env_buf);
- sprintf (env_buf, "0x%08X", (uint)(gd->bd->bi_flashstart));
- linux_env_set ("flash_start", env_buf);
+ sprintf (env_buf, "0x%08X", (uint) (gd->bd->bi_flashstart));
+ linux_env_set ("flash_start", env_buf);
- sprintf (env_buf, "0x%X", (uint)(gd->bd->bi_flashsize));
- linux_env_set ("flash_size", env_buf);
+ sprintf (env_buf, "0x%X", (uint) (gd->bd->bi_flashsize));
+ linux_env_set ("flash_size", env_buf);
- /* we assume that the kernel is in place */
- printf("\nStarting kernel ...\n\n");
+ /* we assume that the kernel is in place */
+ printf ("\nStarting kernel ...\n\n");
- theKernel(linux_argc, linux_argv, linux_env, 0);
+ theKernel (linux_argc, linux_argv, linux_env, 0);
}
-static void linux_params_init (ulong start, char * line)
+static void linux_params_init (ulong start, char *line)
{
- char * next, * quote, * argp;
-
- linux_argc = 1;
- linux_argv = (char **) start;
- linux_argv[0] = 0;
- argp = (char *)(linux_argv + LINUX_MAX_ARGS);
-
- next = line;
-
- while (line && *line && linux_argc < LINUX_MAX_ARGS)
- {
- quote = strchr (line, '"');
- next = strchr (line, ' ');
-
- while (next != NULL && quote != NULL && quote < next)
- {
- /* we found a left quote before the next blank
- * now we have to find the matching right quote
- */
- next = strchr (quote + 1, '"');
- if (next != NULL)
- {
- quote = strchr (next + 1, '"');
- next = strchr (next + 1, ' ');
- }
- }
+ char *next, *quote, *argp;
- if (next == NULL)
- {
- next = line + strlen (line);
- }
+ linux_argc = 1;
+ linux_argv = (char **) start;
+ linux_argv[0] = 0;
+ argp = (char *) (linux_argv + LINUX_MAX_ARGS);
+
+ next = line;
- linux_argv [linux_argc] = argp;
- memcpy (argp, line, next - line);
- argp [next - line] = 0;
+ while (line && *line && linux_argc < LINUX_MAX_ARGS) {
+ quote = strchr (line, '"');
+ next = strchr (line, ' ');
- argp += next - line + 1;
- linux_argc ++;
+ while (next != NULL && quote != NULL && quote < next) {
+ /* we found a left quote before the next blank
+ * now we have to find the matching right quote
+ */
+ next = strchr (quote + 1, '"');
+ if (next != NULL) {
+ quote = strchr (next + 1, '"');
+ next = strchr (next + 1, ' ');
+ }
+ }
- if (*next) next ++;
+ if (next == NULL) {
+ next = line + strlen (line);
+ }
- line = next;
- }
+ linux_argv[linux_argc] = argp;
+ memcpy (argp, line, next - line);
+ argp[next - line] = 0;
- linux_env = (char **)(((ulong)argp + 15) & ~15);
- linux_env [0] = 0;
- linux_env_p = (char *)(linux_env + LINUX_MAX_ENVS);
- linux_env_idx = 0;
+ argp += next - line + 1;
+ linux_argc++;
+
+ if (*next)
+ next++;
+
+ line = next;
+ }
+
+ linux_env = (char **) (((ulong) argp + 15) & ~15);
+ linux_env[0] = 0;
+ linux_env_p = (char *) (linux_env + LINUX_MAX_ENVS);
+ linux_env_idx = 0;
}
-static void linux_env_set (char * env_name, char * env_val)
+static void linux_env_set (char *env_name, char *env_val)
{
- if (linux_env_idx < LINUX_MAX_ENVS - 1)
- {
- linux_env [linux_env_idx] = linux_env_p;
+ if (linux_env_idx < LINUX_MAX_ENVS - 1) {
+ linux_env[linux_env_idx] = linux_env_p;
- strcpy (linux_env_p, env_name);
- linux_env_p += strlen (env_name);
+ strcpy (linux_env_p, env_name);
+ linux_env_p += strlen (env_name);
- strcpy (linux_env_p, "=");
- linux_env_p += 1;
+ strcpy (linux_env_p, "=");
+ linux_env_p += 1;
- strcpy (linux_env_p, env_val);
- linux_env_p += strlen (env_val);
+ strcpy (linux_env_p, env_val);
+ linux_env_p += strlen (env_val);
- linux_env_p ++;
- linux_env [++ linux_env_idx] = 0;
- }
+ linux_env_p++;
+ linux_env[++linux_env_idx] = 0;
+ }
}
extern int plb2800_eth_initialize(bd_t*);
extern int mpc5xxx_fec_initialize(bd_t*);
extern int skge_initialize(bd_t*);
+extern int au1x00_enet_initialize(bd_t*);
static struct eth_device *eth_devices, *eth_current;
#if defined(CONFIG_SK98)
skge_initialize(bis);
#endif
+#if defined(CONFIG_AU1X00)
+ au1x00_enet_initialize(bis);
+#endif
if (!eth_devices) {
puts ("No ethernet found.\n");
projects / u-boot / commitdiff