ppc4xx: Rework 440GX UIC handling

This patch reworks the 440GX interrupt handling so that the common 4xx
code can be used. The 440GX is an exception to all other 4xx variants
by having the cascading interrupt vectors not on UIC0 but on a special
UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references
the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt
handling is simpler without any 440GX special cases.

Also some additional cleanup to cpu/ppc4xx/interrupt.c is done.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index eea1e1e177c350bffdba3707220984c1b4f15ac8..4d1d093219eb1972f1712ba733bdd8a06fae0c28 100644 (file)
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -147,36 +147,48 @@ int board_early_init_f (void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
-       mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
-       mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-
+       /*
+        * Because of the interrupt handling rework to handle 440GX interrupts
+        * with the common code, we needed to change names of the UIC registers.
+        * Here the new relationship:
+        *
+        * U-Boot name  440GX name
+        * -----------------------
+        * UIC0         UICB0
+        * UIC1         UIC0
+        * UIC2         UIC1
+        * UIC3         UIC2
+        */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
        mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
-       mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
+       mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
+       mtdcr (uic1pr, 0xfffffe13);     /* per ref-board manual */
+       mtdcr (uic1tr, 0x01c00008);     /* per ref-board manual */
        mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
 
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
        mtdcr (uic2er, 0x00000000);     /* disable all */
        mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
+       mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
        mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
 
-       mtdcr (uicb0sr, 0xfc000000); /* clear all */
-       mtdcr (uicb0er, 0x00000000); /* disable all */
-       mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-       mtdcr (uicb0pr, 0xfc000000); /* */
-       mtdcr (uicb0tr, 0x00000000); /* */
-       mtdcr (uicb0vr, 0x00000001); /* */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+       mtdcr (uic3er, 0x00000000);     /* disable all */
+       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
+       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+
+       mtdcr (uic0sr, 0xfc000000); /* clear all */
+       mtdcr (uic0er, 0x00000000); /* disable all */
+       mtdcr (uic0cr, 0x00000000); /* all non-critical */
+       mtdcr (uic0pr, 0xfc000000); /* */
+       mtdcr (uic0tr, 0x00000000); /* */
+       mtdcr (uic0vr, 0x00000001); /* */
        mfsdr (sdr_mfr, mfr);
        mfr &= ~SDR0_MFR_ECS_MASK;
 /*     mtsdr(sdr_mfr, mfr); */

diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index b6c306539e40752f6f2984102d08e528f768129f..fdd82e7ccad1b7db89bc3921216c7a8afe2fbbab 100644 (file)
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -119,36 +119,48 @@ int board_early_init_f (void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
-       mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
-       mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-
+       /*
+        * Because of the interrupt handling rework to handle 440GX interrupts
+        * with the common code, we needed to change names of the UIC registers.
+        * Here the new relationship:
+        *
+        * U-Boot name  440GX name
+        * -----------------------
+        * UIC0         UICB0
+        * UIC1         UIC0
+        * UIC2         UIC1
+        * UIC3         UIC2
+        */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
        mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
-       mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
+       mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
+       mtdcr (uic1pr, 0xfffffe13);     /* per ref-board manual */
+       mtdcr (uic1tr, 0x01c00008);     /* per ref-board manual */
        mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
 
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
        mtdcr (uic2er, 0x00000000);     /* disable all */
        mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
+       mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
        mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
 
-       mtdcr (uicb0sr, 0xfc000000);    /* clear all */
-       mtdcr (uicb0er, 0x00000000);    /* disable all */
-       mtdcr (uicb0cr, 0x00000000);    /* all non-critical */
-       mtdcr (uicb0pr, 0xfc000000);    /* */
-       mtdcr (uicb0tr, 0x00000000);    /* */
-       mtdcr (uicb0vr, 0x00000001);    /* */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+       mtdcr (uic3er, 0x00000000);     /* disable all */
+       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
+       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+
+       mtdcr (uic0sr, 0xfc000000);     /* clear all */
+       mtdcr (uic0er, 0x00000000);     /* disable all */
+       mtdcr (uic0cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic0pr, 0xfc000000);     /* */
+       mtdcr (uic0tr, 0x00000000);     /* */
+       mtdcr (uic0vr, 0x00000001);     /* */
 
        /* Enable two GPIO 10~11 and TraceA signal */
        mfsdr(sdr_pfc0,reg);

diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index 131a62dd649b7903fe8a39d0c2cc89d0dd7f40c5..cc491d05b14bc18278f158d9bce27c291ff046fb 100644 (file)
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -48,36 +48,48 @@ int board_early_init_f (void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic0pr, 0xfffffe03);     /* per manual */
-       mtdcr (uic0tr, 0x01c00000);     /* per manual */
-       mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-
+       /*
+        * Because of the interrupt handling rework to handle 440GX interrupts
+        * with the common code, we needed to change names of the UIC registers.
+        * Here the new relationship:
+        *
+        * U-Boot name  440GX name
+        * -----------------------
+        * UIC0         UICB0
+        * UIC1         UIC0
+        * UIC2         UIC1
+        * UIC3         UIC2
+        */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
        mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
-       mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
+       mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
+       mtdcr (uic1pr, 0xfffffe03);     /* per manual */
+       mtdcr (uic1tr, 0x01c00000);     /* per manual */
        mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
 
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
        mtdcr (uic2er, 0x00000000);     /* disable all */
        mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
+       mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
        mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
 
-       mtdcr (uicb0sr, 0xfc000000); /* clear all */
-       mtdcr (uicb0er, 0x00000000); /* disable all */
-       mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-       mtdcr (uicb0pr, 0xfc000000); /* */
-       mtdcr (uicb0tr, 0x00000000); /* */
-       mtdcr (uicb0vr, 0x00000001); /* */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+       mtdcr (uic3er, 0x00000000);     /* disable all */
+       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
+       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+
+       mtdcr (uic0sr, 0xfc000000); /* clear all */
+       mtdcr (uic0er, 0x00000000); /* disable all */
+       mtdcr (uic0cr, 0x00000000); /* all non-critical */
+       mtdcr (uic0pr, 0xfc000000); /* */
+       mtdcr (uic0tr, 0x00000000); /* */
+       mtdcr (uic0vr, 0x00000001); /* */
 
        /* Setup shutdown/SSD empty interrupt as inputs */
        out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));

diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index 2d71d3b2cc7280bb93ca25047b3726a0ce6c8e2d..72ce976350e47b23e8fe0b2b9f236a762a608e53 100644 (file)
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -195,36 +195,48 @@ int board_early_init_f (void)
        /*--------------------------------------------------------------------+
         * Setup the interrupt controller polarities, triggers, etc.
         +-------------------------------------------------------------------*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000000);     /* all non- critical */
-       mtdcr (uic0pr, 0xfffffe03);     /* polarity */
-       mtdcr (uic0tr, 0x01c00000);     /* trigger edge vs level */
-       mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-
+       /*
+        * Because of the interrupt handling rework to handle 440GX interrupts
+        * with the common code, we needed to change names of the UIC registers.
+        * Here the new relationship:
+        *
+        * U-Boot name  440GX name
+        * -----------------------
+        * UIC0         UICB0
+        * UIC1         UIC0
+        * UIC2         UIC1
+        * UIC3         UIC2
+        */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
        mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic1pr, 0xffffc8ff);     /* polarity */
-       mtdcr (uic1tr, 0x00ff0000);     /* trigger edge vs level */
+       mtdcr (uic1cr, 0x00000000);     /* all non- critical */
+       mtdcr (uic1pr, 0xfffffe03);     /* polarity */
+       mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
        mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
 
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
        mtdcr (uic2er, 0x00000000);     /* disable all */
        mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffff83ff);     /* polarity */
-       mtdcr (uic2tr, 0x00ff8c0f);     /* trigger edge vs level */
+       mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
+       mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
        mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
 
-       mtdcr (uicb0sr, 0xfc000000);    /* clear all */
-       mtdcr (uicb0er, 0x00000000);    /* disable all */
-       mtdcr (uicb0cr, 0x00000000);    /* all non-critical */
-       mtdcr (uicb0pr, 0xfc000000);
-       mtdcr (uicb0tr, 0x00000000);
-       mtdcr (uicb0vr, 0x00000001);
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+       mtdcr (uic3er, 0x00000000);     /* disable all */
+       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic3pr, 0xffff83ff);     /* polarity */
+       mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
+       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+
+       mtdcr (uic0sr, 0xfc000000);     /* clear all */
+       mtdcr (uic0er, 0x00000000);     /* disable all */
+       mtdcr (uic0cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic0pr, 0xfc000000);
+       mtdcr (uic0tr, 0x00000000);
+       mtdcr (uic0vr, 0x00000001);
 
        fpga_init();
 

diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 97049013e1cea80f27867a9e7e564a1f79a6c437..63c91dc59c68e13bc950883503c24dca2c0593d9 100644 (file)
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -185,36 +185,48 @@ int board_early_init_f (void)
        /*--------------------------------------------------------------------+
         * Setup the interrupt controller polarities, triggers, etc.
         +-------------------------------------------------------------------*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000000);     /* all non- critical */
-       mtdcr (uic0pr, 0xfffffe03);     /* polarity */
-       mtdcr (uic0tr, 0x01c00000);     /* trigger edge vs level */
-       mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-
+       /*
+        * Because of the interrupt handling rework to handle 440GX interrupts
+        * with the common code, we needed to change names of the UIC registers.
+        * Here the new relationship:
+        *
+        * U-Boot name  440GX name
+        * -----------------------
+        * UIC0         UICB0
+        * UIC1         UIC0
+        * UIC2         UIC1
+        * UIC3         UIC2
+        */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
        mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic1pr, 0xffffc8ff);     /* polarity */
-       mtdcr (uic1tr, 0x00ff0000);     /* trigger edge vs level */
+       mtdcr (uic1cr, 0x00000000);     /* all non- critical */
+       mtdcr (uic1pr, 0xfffffe03);     /* polarity */
+       mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
        mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
 
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
        mtdcr (uic2er, 0x00000000);     /* disable all */
        mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffff83ff);     /* polarity */
-       mtdcr (uic2tr, 0x00ff8c0f);     /* trigger edge vs level */
+       mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
+       mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
        mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
 
-       mtdcr (uicb0sr, 0xfc000000);    /* clear all */
-       mtdcr (uicb0er, 0x00000000);    /* disable all */
-       mtdcr (uicb0cr, 0x00000000);    /* all non-critical */
-       mtdcr (uicb0pr, 0xfc000000);
-       mtdcr (uicb0tr, 0x00000000);
-       mtdcr (uicb0vr, 0x00000001);
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+       mtdcr (uic3er, 0x00000000);     /* disable all */
+       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic3pr, 0xffff83ff);     /* polarity */
+       mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
+       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+
+       mtdcr (uic0sr, 0xfc000000);     /* clear all */
+       mtdcr (uic0er, 0x00000000);     /* disable all */
+       mtdcr (uic0cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic0pr, 0xfc000000);
+       mtdcr (uic0tr, 0x00000000);
+       mtdcr (uic0vr, 0x00000001);
 
        fpga_init();
 

diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index bc7e3bd17cbedd9c27a73a2d6dbcde802d7fc216..c94a345d90d7e4333c860d31d88e9c4a670d60fc 100644 (file)
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -59,36 +59,48 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000003);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic0pr, 0xfffffe00);     /* per ref-board manual */
-       mtdcr (uic0tr, 0x01c00000);     /* per ref-board manual */
-       mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all */
-
+       /*
+        * Because of the interrupt handling rework to handle 440GX interrupts
+        * with the common code, we needed to change names of the UIC registers.
+        * Here the new relationship:
+        *
+        * U-Boot name  440GX name
+        * -----------------------
+        * UIC0         UICB0
+        * UIC1         UIC0
+        * UIC2         UIC1
+        * UIC3         UIC2
+        */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
        mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic1pr, 0xffffc0ff);     /* per ref-board manual */
-       mtdcr (uic1tr, 0x00ff8000);     /* per ref-board manual */
+       mtdcr (uic1cr, 0x00000003);     /* SMI & UIC1 crit are critical */
+       mtdcr (uic1pr, 0xfffffe00);     /* per ref-board manual */
+       mtdcr (uic1tr, 0x01c00000);     /* per ref-board manual */
        mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic1sr, 0xffffffff);     /* clear all */
 
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
        mtdcr (uic2er, 0x00000000);     /* disable all */
        mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic2pr, 0xffffc0ff);     /* per ref-board manual */
+       mtdcr (uic2tr, 0x00ff8000);     /* per ref-board manual */
        mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
        mtdcr (uic2sr, 0xffffffff);     /* clear all */
 
-       mtdcr (uicb0sr, 0xfc000000); /* clear all */
-       mtdcr (uicb0er, 0x00000000); /* disable all */
-       mtdcr (uicb0cr, 0x00000000); /* all non-critical */
-       mtdcr (uicb0pr, 0xfc000000); /* */
-       mtdcr (uicb0tr, 0x00000000); /* */
-       mtdcr (uicb0vr, 0x00000001); /* */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+       mtdcr (uic3er, 0x00000000);     /* disable all */
+       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
+       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
+       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (uic3sr, 0xffffffff);     /* clear all */
+
+       mtdcr (uic0sr, 0xfc000000); /* clear all */
+       mtdcr (uic0er, 0x00000000); /* disable all */
+       mtdcr (uic0cr, 0x00000000); /* all non-critical */
+       mtdcr (uic0pr, 0xfc000000); /* */
+       mtdcr (uic0tr, 0x00000000); /* */
+       mtdcr (uic0vr, 0x00000001); /* */
 
        LED0_ON();
 

diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 01712b056e0e599607299f0456de0efab55719d7..8a3833513e2b21512814a8f872190da66840cb1c 100644 (file)
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -169,12 +169,15 @@
  * UIC. Only exception is 440GX where the EMAC interrupts are
  * spread over two UIC's!
  */
+#if defined(CONFIG_440GX)
+#define UIC_BASE_MAL   UIC1_DCR_BASE
+#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
+#define UIC_BASE_EMAC  UIC2_DCR_BASE
+#define UIC_BASE_EMAC_B        UIC3_DCR_BASE
+#else
 #define UIC_BASE_MAL   (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
 #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
 #define UIC_BASE_EMAC  (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
-#if defined(CONFIG_440GX)
-#define UIC_BASE_EMAC_B        (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(2)) * 0x10))
-#else
 #define UIC_BASE_EMAC_B        (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
 #endif
 

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index ac6427905161809ca8b733cbfc13cccc0c3d5695..e2d04027815a8e44b430ce2f17764ad78bb8ddd7 100644 (file)
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -138,9 +138,10 @@ void reconfigure_pll(u32 new_cpu_freq)
 void
 cpu_init_f (void)
 {
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_460EX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
        u32 val;
 #endif
+
        reconfigure_pll(CFG_PLL_RECONFIG);
 
 #if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE)
@@ -273,6 +274,18 @@ cpu_init_f (void)
        reset_4xx_watchdog();
 #endif /* CONFIG_WATCHDOG */
 
+#if defined(CONFIG_440GX)
+       /* Take the GX out of compatibility mode
+        * Travis Sawyer, 9 Mar 2004
+        * NOTE: 440gx user manual inconsistency here
+        *       Compatibility mode and Ethernet Clock select are not
+        *       correct in the manual
+        */
+       mfsdr(sdr_mfr, val);
+       val &= ~0x10000000;
+       mtsdr(sdr_mfr,val);
+#endif /* CONFIG_440GX */
+
 #if defined(CONFIG_460EX)
        /*
         * Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and

diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 6dbd6d281907fa4fcd91483a53bedb276cec905c..8215dc652edb1d0fe5fb947ac547d558173bb53c 100644 (file)
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -40,14 +40,8 @@
                         UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
                         UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
 #elif (UIC_MAX > 2)
-#if defined(CONFIG_440GX)
-#define UICB0_ALL      (UIC_MASK(VECNUM_UIC0CI) | UIC_MASK(VECNUM_UIC0NCI) | \
-                        UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
-                        UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
-#else
 #define UICB0_ALL      (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
                         UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
-#endif
 #elif (UIC_MAX > 1)
 #define UICB0_ALL      (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
 #else
@@ -70,10 +64,6 @@ static struct irq_action irq_vecs[UIC_MAX * 32];
 u32 get_dcr(u16);
 void set_dcr(u16, u32);
 
-#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
-static void uic_cascade_interrupt(void *para);
-#endif
-
 #if defined(CONFIG_440)
 
 /* SPRN changed in 440 */
@@ -157,42 +147,19 @@ int interrupt_init_cpu (unsigned *decrementer_count)
         */
        set_evpr(0x00000000);
 
-#if !defined(CONFIG_440GX)
 #if (UIC_MAX > 1)
        /* Install the UIC1 handlers */
-       irq_install_handler(VECNUM_UIC1NCI, uic_cascade_interrupt, 0);
-       irq_install_handler(VECNUM_UIC1CI, uic_cascade_interrupt, 0);
+       irq_install_handler(VECNUM_UIC1NCI, (void *)(void *)external_interrupt, 0);
+       irq_install_handler(VECNUM_UIC1CI, (void *)(void *)external_interrupt, 0);
 #endif
 #if (UIC_MAX > 2)
-       irq_install_handler(VECNUM_UIC2NCI, uic_cascade_interrupt, 0);
-       irq_install_handler(VECNUM_UIC2CI, uic_cascade_interrupt, 0);
+       irq_install_handler(VECNUM_UIC2NCI, (void *)(void *)external_interrupt, 0);
+       irq_install_handler(VECNUM_UIC2CI, (void *)(void *)external_interrupt, 0);
 #endif
 #if (UIC_MAX > 3)
-       irq_install_handler(VECNUM_UIC3NCI, uic_cascade_interrupt, 0);
-       irq_install_handler(VECNUM_UIC3CI, uic_cascade_interrupt, 0);
+       irq_install_handler(VECNUM_UIC3NCI, (void *)(void *)external_interrupt, 0);
+       irq_install_handler(VECNUM_UIC3CI, (void *)(void *)external_interrupt, 0);
 #endif
-#else /* !defined(CONFIG_440GX) */
-       /*
-        * ToDo: Remove this 440GX special handling:
-        * Move SDR0_MFR setup to cpu.c and use common code with UICB0
-        * on 440GX. 2008-06-26, sr
-        */
-       /* Take the GX out of compatibility mode
-        * Travis Sawyer, 9 Mar 2004
-        * NOTE: 440gx user manual inconsistency here
-        *       Compatibility mode and Ethernet Clock select are not
-        *       correct in the manual
-        */
-       mfsdr(sdr_mfr, val);
-       val &= ~0x10000000;
-       mtsdr(sdr_mfr,val);
-
-       /* Enable UIC interrupts via UIC Base Enable Register */
-       mtdcr(uicb0sr, UICB0_ALL);
-       mtdcr(uicb0er, UICB0_ALL);
-       /* None are critical */
-       mtdcr(uicb0cr, 0);
-#endif /* !defined(CONFIG_440GX) */
 
        return (0);
 }
@@ -243,22 +210,6 @@ static void uic_interrupt(u32 uic_base, int vec_base)
        }
 }
 
-#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
-static void uic_cascade_interrupt(void *para)
-{
-       external_interrupt(para);
-}
-#endif
-
-#if defined(CONFIG_440GX)
-/* 440GX uses base uic register */
-#define UIC_BMSR       uicb0msr
-#define UIC_BSR                uicb0sr
-#else
-#define UIC_BMSR       uic0msr
-#define UIC_BSR                uic0sr
-#endif
-
 /*
  * Handle external interrupts
  */
@@ -269,7 +220,7 @@ void external_interrupt(struct pt_regs *regs)
        /*
         * Read masked interrupt status register to determine interrupt source
         */
-       uic_msr = mfdcr(UIC_BMSR);
+       uic_msr = mfdcr(uic0msr);
 
 #if (UIC_MAX > 1)
        if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
@@ -289,20 +240,10 @@ void external_interrupt(struct pt_regs *regs)
                uic_interrupt(UIC3_DCR_BASE, 96);
 #endif
 
-#if defined(CONFIG_440)
-#if !defined(CONFIG_440GX)
        if (uic_msr & ~(UICB0_ALL))
                uic_interrupt(UIC0_DCR_BASE, 0);
-#else
-       if ((UIC_MASK(VECNUM_UIC0CI) & uic_msr) ||
-           (UIC_MASK(VECNUM_UIC0NCI) & uic_msr))
-               uic_interrupt(UIC0_DCR_BASE, 0);
-#endif
-#else /* CONFIG_440 */
-       uic_interrupt(UIC0_DCR_BASE, 0);
-#endif /* CONFIG_440 */
 
-       mtdcr(UIC_BSR, uic_msr);
+       mtdcr(uic0sr, uic_msr);
 
        return;
 }
@@ -312,8 +253,6 @@ void external_interrupt(struct pt_regs *regs)
  */
 void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
 {
-       int i;
-
        /*
         * Print warning when replacing with a different irq vector
         */
@@ -324,20 +263,19 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
        irq_vecs[vec].handler = handler;
        irq_vecs[vec].arg = arg;
 
-       i = vec & 0x1f;
        if ((vec >= 0) && (vec < 32))
-               mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
+               mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
 #if (UIC_MAX > 1)
        else if ((vec >= 32) && (vec < 64))
-               mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
+               mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
 #endif
 #if (UIC_MAX > 2)
        else if ((vec >= 64) && (vec < 96))
-               mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i));
+               mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
 #endif
 #if (UIC_MAX > 3)
        else if (vec >= 96)
-               mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i));
+               mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
 #endif
 
        debug("Install interrupt for vector %d ==> %p\n", vec, handler);
@@ -345,25 +283,22 @@ void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
 
 void irq_free_handler (int vec)
 {
-       int i;
-
        debug("Free interrupt for vector %d ==> %p\n",
              vec, irq_vecs[vec].handler);
 
-       i = vec & 0x1f;
        if ((vec >= 0) && (vec < 32))
-               mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
+               mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
 #if (UIC_MAX > 1)
        else if ((vec >= 32) && (vec < 64))
-               mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
+               mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
 #endif
 #if (UIC_MAX > 2)
        else if ((vec >= 64) && (vec < 96))
-               mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i));
+               mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
 #endif
 #if (UIC_MAX > 3)
        else if (vec >= 96)
-               mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i));
+               mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
 #endif
 
        irq_vecs[vec].handler = NULL;

diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h
index b596f0edfb842da06c89b9ab192eab1b7e9df825..eeaaa493efe4aa4830515cf7d3bd81f1b87f6321 100644 (file)
--- a/include/asm-ppc/ppc4xx-uic.h
+++ b/include/asm-ppc/ppc4xx-uic.h
@@ -29,11 +29,10 @@
 /*
  * Define the number of UIC's
  */
-#if defined(CONFIG_440SPE) || \
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #define UIC_MAX                4
-#elif defined(CONFIG_440GX) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_405EX)
 #define UIC_MAX                3
 #elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
@@ -55,7 +54,23 @@
 #define UIC_VR 0x7                     /* UIC vector                   */
 #define UIC_VCR 0x8                    /* UIC vector configuration     */
 
+/*
+ * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
+ * are cascaded on. With this trick we can use the common UIC code for 440GX
+ * too.
+ */
+#if defined(CONFIG_440GX)
+#define UIC0_DCR_BASE 0x200
+#define UIC1_DCR_BASE 0xc0
+#define UIC2_DCR_BASE 0xd0
+#define UIC3_DCR_BASE 0x210
+#else
 #define UIC0_DCR_BASE 0xc0
+#define UIC1_DCR_BASE 0xd0
+#define UIC2_DCR_BASE 0xe0
+#define UIC3_DCR_BASE 0xf0
+#endif
+
 #define uic0sr (UIC0_DCR_BASE+0x0)     /* UIC0 status                  */
 #define uic0er (UIC0_DCR_BASE+0x2)     /* UIC0 enable                  */
 #define uic0cr (UIC0_DCR_BASE+0x3)     /* UIC0 critical                */
@@ -65,7 +80,6 @@
 #define uic0vr (UIC0_DCR_BASE+0x7)     /* UIC0 vector                  */
 #define uic0vcr (UIC0_DCR_BASE+0x8)    /* UIC0 vector configuration    */
 
-#define UIC1_DCR_BASE 0xd0
 #define uic1sr (UIC1_DCR_BASE+0x0)     /* UIC1 status                  */
 #define uic1er (UIC1_DCR_BASE+0x2)     /* UIC1 enable                  */
 #define uic1cr (UIC1_DCR_BASE+0x3)     /* UIC1 critical                */
@@ -75,11 +89,6 @@
 #define uic1vr (UIC1_DCR_BASE+0x7)     /* UIC1 vector                  */
 #define uic1vcr (UIC1_DCR_BASE+0x8)    /* UIC1 vector configuration    */
 
-#if defined(CONFIG_440GX)
-#define UIC2_DCR_BASE 0x210
-#else
-#define UIC2_DCR_BASE 0xe0
-#endif
 #define uic2sr (UIC2_DCR_BASE+0x0)     /* UIC2 status-Read Clear       */
 #define uic2srs        (UIC2_DCR_BASE+0x1)     /* UIC2 status-Read Set         */
 #define uic2er (UIC2_DCR_BASE+0x2)     /* UIC2 enable                  */
@@ -90,7 +99,6 @@
 #define uic2vr (UIC2_DCR_BASE+0x7)     /* UIC2 vector                  */
 #define uic2vcr (UIC2_DCR_BASE+0x8)    /* UIC2 vector configuration    */
 
-#define UIC3_DCR_BASE 0xf0
 #define uic3sr (UIC3_DCR_BASE+0x0)     /* UIC3 status-Read Clear       */
 #define uic3srs        (UIC3_DCR_BASE+0x1)     /* UIC3 status-Read Set         */
 #define uic3er (UIC3_DCR_BASE+0x2)     /* UIC3 enable                  */
@@ -101,27 +109,15 @@
 #define uic3vr (UIC3_DCR_BASE+0x7)     /* UIC3 vector                  */
 #define uic3vcr (UIC3_DCR_BASE+0x8)    /* UIC3 vector configuration    */
 
-#if defined(CONFIG_440GX)
-#define UIC_DCR_BASE 0x200
-#define uicb0sr         (UIC_DCR_BASE+0x0)     /* UIC Base Status Register     */
-#define uicb0er         (UIC_DCR_BASE+0x2)     /* UIC Base enable              */
-#define uicb0cr         (UIC_DCR_BASE+0x3)     /* UIC Base critical            */
-#define uicb0pr         (UIC_DCR_BASE+0x4)     /* UIC Base polarity            */
-#define uicb0tr         (UIC_DCR_BASE+0x5)     /* UIC Base triggering          */
-#define uicb0msr (UIC_DCR_BASE+0x6)    /* UIC Base masked status       */
-#define uicb0vr         (UIC_DCR_BASE+0x7)     /* UIC Base vector              */
-#define uicb0vcr (UIC_DCR_BASE+0x8)    /* UIC Base vector configuration*/
-#endif /* CONFIG_440GX */
-
 /* The following is for compatibility with 405 code */
-#define uicsr  uic0sr
-#define uicer  uic0er
-#define uiccr  uic0cr
-#define uicpr  uic0pr
-#define uictr  uic0tr
-#define uicmsr uic0msr
-#define uicvr  uic0vr
-#define uicvcr uic0vcr
+#define uicsr  uic0sr
+#define uicer  uic0er
+#define uiccr  uic0cr
+#define uicpr  uic0pr
+#define uictr  uic0tr
+#define uicmsr uic0msr
+#define uicvr  uic0vr
+#define uicvcr uic0vcr
 
 /*
  * Now the interrupt vector definitions. They are different for most of
@@ -188,24 +184,28 @@
 #endif /* CONFIG_440GP */
 
 #if defined(CONFIG_440GX)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB       10
-#define VECNUM_MAL_RXEOB       11
+/* UICB 0 (440GX only) */
+/*
+ * All those defines below are off-by-one, so that the common UIC code
+ * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
+ */
+#define VECNUM_UIC1CI          0
+#define VECNUM_UIC1NCI         1
+#define VECNUM_UIC2CI          2
+#define VECNUM_UIC2NCI         3
+#define VECNUM_UIC3CI          4
+#define VECNUM_UIC3NCI         5
 
-/* UIC 1 */
-#define VECNUM_MAL_SERR                (32 + 0)
-#define VECNUM_MAL_TXDE                (32 + 1)
-#define VECNUM_MAL_RXDE                (32 + 2)
-#define VECNUM_ETH0            (32 + 28)
-#define VECNUM_ETH1_OFFS       2
+/* UIC 0, used as UIC1 on 440GX because of UICB0 */
+#define VECNUM_MAL_TXEOB       (32 + 10)
+#define VECNUM_MAL_RXEOB       (32 + 11)
 
-/* UICB 0 (440GX only) */
-#define VECNUM_UIC0CI          0
-#define VECNUM_UIC0NCI         1
-#define VECNUM_UIC1CI          2
-#define VECNUM_UIC1NCI         3
-#define VECNUM_UIC2CI          4
-#define VECNUM_UIC2NCI         5
+/* UIC 1, used as UIC2 on 440GX because of UICB0 */
+#define VECNUM_MAL_SERR                (64 + 0)
+#define VECNUM_MAL_TXDE                (64 + 1)
+#define VECNUM_MAL_RXDE                (64 + 2)
+#define VECNUM_ETH0            (64 + 28)
+#define VECNUM_ETH1_OFFS       2
 #endif /* CONFIG_440GX */
 
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -288,6 +288,7 @@
  * Mask definitions (used for example in 4xx_enet.c)
  */
 #define UIC_MASK(vec)          (0x80000000 >> ((vec) & 0x1f))
+/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
 #define UIC_NR(vec)            ((vec) >> 5)
 
 #endif /* _PPC4xx_UIC_H_ */