* tAXPD=1, need design to confirm.
         */
        int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
-       unsigned int data_rate = fsl_ddr_get_mem_data_rate();
+       unsigned int data_rate = get_ddr_freq(0);
        tmrd_mclk = 4;
        /* set the turnaround time */
        trwt_mclk = 1;
 
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
-extern unsigned int fsl_ddr_get_mem_data_rate(void);
 #endif
 
 
 #include "ddr.h"
 
-unsigned int fsl_ddr_get_mem_data_rate(void);
-
 /*
  * Round mclk_ps to nearest 10 ps in memory controller code.
  *
 {
        unsigned int mclk_ps;
 
-       mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
+       mclk_ps = 2000000000000ULL / get_ddr_freq(0);
        /* round to nearest 10 ps */
        return 10 * ((mclk_ps + 5) / 10);
 }
        if (!picos)
                return 0;
 
-       clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
+       clks = get_ddr_freq(0) * (unsigned long long) picos;
        clks_temp = clks;
        clks = clks / ULL_2e12;
        if (clks_temp % ULL_2e12) {
 
        }
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
-
 void
 fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                        unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
-
 void
 fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
 }
 
-
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_bus_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_bus_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
        /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
         * freqency and n_banks specified in board_specific_parameters table.
         */
-       ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000;
+       ddr_freq = get_ddr_freq(0) / 1000000;
        for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
                if (pdimm[j].n_ranks > 0) {
                        for (i = 0; i < num_params; i++) {
 
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
 {
        int ret;
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                        unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
-
 void
 fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_bus_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
-
 void
 fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 
        i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
 }
 
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
-
 void
 fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 
                sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_bus_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                        unsigned int ctrl_num)
 {
        unsigned int datarate;
 
        get_sys_info(&sysinfo);
-       datarate = fsl_ddr_get_mem_data_rate() / 1000000;
+       datarate = get_ddr_freq(0) / 1000000;
 
        for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) {
                if ((bopts[i].datarate_mhz_low <= datarate) &&
 
        }
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                        unsigned int ctrl_num)
 {
 
                 sizeof(ddr2_spd_eeprom_t));
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
                      unsigned int ctrl_num)
 {
 
        }
 }
 
-unsigned int fsl_ddr_get_mem_data_rate(void)
-{
-       return get_ddr_freq(0);
-}
-
 /*
  *     There are traditionally three board-specific SDRAM timing parameters
  *     which must be calculated based on the particular PCB artwork.  These are:
 
 #if defined(CONFIG_MPC86xx)
 typedef MPC86xx_SYS_INFO sys_info_t;
 void   get_sys_info  ( sys_info_t * );
+static inline ulong get_ddr_freq(ulong dummy)
+{
+       return get_bus_freq(dummy);
+}
 #endif
 
 #if defined(CONFIG_4xx) || defined(CONFIG_IOP480)