]> git.sur5r.net Git - u-boot/commitdiff
Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro
authorChander Kashyap <chander.kashyap@linaro.org>
Sun, 5 Feb 2012 23:01:45 +0000 (23:01 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 12 Feb 2012 09:11:30 +0000 (10:11 +0100)
CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4)
architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ
to make it generic for exynos architecture.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
arch/arm/cpu/armv7/exynos/clock.c
include/configs/s5pc210_universal.h
include/configs/trats.h

index 0c199cdab3d7771ac20f7b3467fc286dde4fb489..4d92c53b95466b00ba8ca5de8aedc630bcae1ca9 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210       24000000
-#endif
-
 /* exynos4: return pll clock frequency */
 static unsigned long exynos4_get_pll_clk(int pllreg)
 {
@@ -76,7 +72,7 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
        /* SDIV [2:0] */
        s = r & 0x7;
 
-       freq = CONFIG_SYS_CLK_FREQ_C210;
+       freq = CONFIG_SYS_CLK_FREQ;
 
        if (pllreg == EPLL) {
                k = k & 0xffff;
index be000cbafe5c7e36f29d2525478fdcb648429e7d..8286680f26c14446bc42d7ab84bad78cf9931457 100644 (file)
@@ -49,6 +49,7 @@
 
 /* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
 #define CONFIG_SYS_CLK_FREQ_C210       24000000
+#define CONFIG_SYS_CLK_FREQ            CONFIG_SYS_CLK_FREQ_C210
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
index acb3241530c8707397fd75a6337e820fd538bcc2..10f11d95792edb04389b2a3f90d55cd4eaac09d2 100644 (file)
@@ -49,6 +49,7 @@
 
 /* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
 #define CONFIG_SYS_CLK_FREQ_C210       24000000
+#define CONFIG_SYS_CLK_FREQ            CONFIG_SYS_CLK_FREQ_C210
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG