]> git.sur5r.net Git - u-boot/commitdiff
PXA270: Added support for TrizepsIV board.
authorstefano babic <sbabic@denx.de>
Thu, 30 Aug 2007 21:01:49 +0000 (23:01 +0200)
committerWolfgang Denk <wd@denx.de>
Thu, 6 Sep 2007 23:06:19 +0000 (01:06 +0200)
This patch add support for the Trizeps IV module (520Mhz).

Signed-off-by: Stefano Babic <sbabic@denx.de>
Makefile
board/trizepsiv/Makefile [new file with mode: 0644]
board/trizepsiv/config.mk [new file with mode: 0644]
board/trizepsiv/conxs.c [new file with mode: 0644]
board/trizepsiv/eeprom.c [new file with mode: 0644]
board/trizepsiv/lowlevel_init.S [new file with mode: 0644]
board/trizepsiv/pxavoltage.S [new file with mode: 0644]
board/trizepsiv/u-boot.lds [new file with mode: 0644]
drivers/dm9000x.c
include/configs/trizepsiv.h [new file with mode: 0644]

index 0477cd3dc2ec551378747236ebee3b868a158301..0371d4619d407f634b3b0bbfe6b64e39a009673e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -2334,6 +2334,9 @@ scpu_config:    unconfig
 pxa255_idp_config:     unconfig
        @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp
 
+trizepsiv_config       :       unconfig
+       @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv
+
 wepep250_config        :       unconfig
        @$(MKCONFIG) $(@:_config=) arm pxa wepep250
 
diff --git a/board/trizepsiv/Makefile b/board/trizepsiv/Makefile
new file mode 100644 (file)
index 0000000..115e17d
--- /dev/null
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := conxs.o eeprom.o
+SOBJS  := lowlevel_init.o pxavoltage.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/trizepsiv/config.mk b/board/trizepsiv/config.mk
new file mode 100644 (file)
index 0000000..4486f6b
--- /dev/null
@@ -0,0 +1,3 @@
+TEXT_BASE =0xa1f00000
+# 0xa1700000
+#TEXT_BASE = 0
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
new file mode 100644 (file)
index 0000000..7c6c855
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define                RH_A_PSM        (1 << 8)        /* power switching mode */
+#define                RH_A_NPS        (1 << 9)        /* no power switching */
+
+extern struct serial_device serial_ffuart_device;
+extern struct serial_device serial_btuart_device;
+extern struct serial_device serial_stuart_device;
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+void usb_board_init(void)
+{
+       UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+               ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+
+       UHCHR |= UHCHR_FSBIR;
+
+       while (UHCHR & UHCHR_FSBIR);
+
+       UHCHR &= ~UHCHR_SSE;
+       UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+
+       /* Clear any OTG Pin Hold */
+       if (PSSR & PSSR_OTGPH)
+               PSSR |= PSSR_OTGPH;
+
+       UHCRHDA &= ~(RH_A_NPS);
+       UHCRHDA |= RH_A_PSM;
+
+       /* Set port power control mask bits, only 3 ports. */
+       UHCRHDB |= (0x7<<17);
+}
+
+void usb_board_init_fail(void)
+{
+       return;
+}
+
+void usb_board_stop(void)
+{
+       UHCHR |= UHCHR_FHR;
+       udelay(11);
+       UHCHR &= ~UHCHR_FHR;
+
+       UHCCOMS |= 1;
+       udelay(10);
+
+       CKEN &= ~CKEN10_USBHOST;
+
+       puts("Called USB STOP\n");
+       return;
+}
+
+int board_init (void)
+{
+       /* memory and cpu-speed are setup before relocation */
+       /* so we do _nothing_ here */
+
+       /* arch number of ConXS Board */
+       gd->bd->bi_arch_number = 776;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = 0xa000003c;
+
+       return 0;
+}
+
+int board_late_init(void)
+{
+#if defined(CONFIG_SERIAL_MULTI)
+       char *console=getenv("boot_console");
+
+       if ((strcmp(console,"serial_btuart") == 0) ||
+               (strcmp(console,"serial_stuart") == 0) ||
+               (strcmp(console,"serial_ffuart") == 0)) {
+                       setenv("stdout",console);
+                       setenv("stdin", console);
+                       setenv("stderr",console);
+       } else {
+               setenv("stdout", "serial");
+               setenv("stdin", "serial");
+               setenv("stderr", "serial");
+       }
+#endif
+       return 0;
+}
+
+struct serial_device *default_serial_console (void)
+{
+       return &serial_ffuart_device;
+}
+
+int dram_init (void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+       return 0;
+}
diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c
new file mode 100644 (file)
index 0000000..3d3bc00
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+static unsigned char srom[128];
+extern u16 read_srom_word(int);
+extern void write_srom_word(int offset, u16 val);
+
+static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+       int i;
+
+       for (i=0; i < 0x40; i++) {
+               if (!(i % 0x10))
+                       printf("\n%08lx:", i);
+               printf(" %04x", read_srom_word(i));
+       }
+       printf ("\n");
+       return (0);
+}
+
+static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+       int offset,value;
+
+       if (argc < 4) {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+
+       offset=simple_strtoul(argv[2],NULL,16);
+       value=simple_strtoul(argv[3],NULL,16);
+       if (offset > 0x40) {
+               printf("Wrong offset : 0x%x\n",offset);
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+       write_srom_word(offset, value);
+       return (0);
+}
+
+int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) {
+       if (argc < 2) {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+
+       if (strcmp (argv[1],"read") == 0) {
+               return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
+       } else if (strcmp (argv[1],"write") == 0) {
+               return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
+       } else {
+               printf ("Usage:\n%s\n", cmdtp->usage);
+               return 1;
+       }
+}
+
+U_BOOT_CMD(
+       dm9000ee,4,1,do_dm9000_eeprom,
+       "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n",
+       "\ndm9000ee write <word offset> <value> \n"
+       "\tdm9000ee read \n"
+       "\tword:\t\t00-02 : MAC Address\n"
+       "\t\t\t03-07 : DM9000 Configuration\n"
+       "\t\t\t08-63 : User data\n");
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S
new file mode 100644 (file)
index 0000000..d886938
--- /dev/null
@@ -0,0 +1,503 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc p15,0,\reg,c2,c0,0
+   mov \reg,\reg
+   sub pc,pc,#4
+   .endm
+
+
+/*
+ *     Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+       /* Set up GPIO pins first ----------------------------------------- */
+
+       ldr             r0,     =GPSR0
+       ldr             r1,     =CFG_GPSR0_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPSR1
+       ldr             r1,     =CFG_GPSR1_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPSR2
+       ldr             r1,     =CFG_GPSR2_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPSR3
+       ldr             r1,     =CFG_GPSR3_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPCR0
+       ldr             r1,     =CFG_GPCR0_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPCR1
+       ldr             r1,     =CFG_GPCR1_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPCR2
+       ldr             r1,     =CFG_GPCR2_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPCR3
+       ldr             r1,     =CFG_GPCR3_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GRER0
+       ldr             r1,     =CFG_GRER0_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GRER1
+       ldr             r1,     =CFG_GRER1_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GRER2
+       ldr             r1,     =CFG_GRER2_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GRER3
+       ldr             r1,     =CFG_GRER3_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GFER0
+       ldr             r1,     =CFG_GFER0_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GFER1
+       ldr             r1,     =CFG_GFER1_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GFER2
+       ldr             r1,     =CFG_GFER2_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GFER3
+       ldr             r1,     =CFG_GFER3_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPDR0
+       ldr             r1,     =CFG_GPDR0_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPDR1
+       ldr             r1,     =CFG_GPDR1_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPDR2
+       ldr             r1,     =CFG_GPDR2_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GPDR3
+       ldr             r1,     =CFG_GPDR3_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR0_L
+       ldr             r1,     =CFG_GAFR0_L_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR0_U
+       ldr             r1,     =CFG_GAFR0_U_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR1_L
+       ldr             r1,     =CFG_GAFR1_L_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR1_U
+       ldr             r1,     =CFG_GAFR1_U_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR2_L
+       ldr             r1,     =CFG_GAFR2_L_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR2_U
+       ldr             r1,     =CFG_GAFR2_U_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR3_L
+       ldr             r1,     =CFG_GAFR3_L_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =GAFR3_U
+       ldr             r1,     =CFG_GAFR3_U_VAL
+       str             r1,   [r0]
+
+       ldr             r0,     =PSSR           /* enable GPIO pins */
+       ldr             r1,     =CFG_PSSR_VAL
+       str             r1,   [r0]
+
+       /* ---------------------------------------------------------------- */
+       /* Enable memory interface                                          */
+       /*                                                                  */
+       /* The sequence below is based on the recommended init steps        */
+       /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+       /* Chapter 10.                                                      */
+       /* ---------------------------------------------------------------- */
+
+       /* ---------------------------------------------------------------- */
+       /* Step 1: Wait for at least 200 microsedonds to allow internal     */
+       /*         clocks to settle. Only necessary after hard reset...     */
+       /*         FIXME: can be optimized later                            */
+       /* ---------------------------------------------------------------- */
+
+       ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
+       mov r2, #0
+       str r2, [r3]
+       ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
+                                       /* so 0x300 should be plenty        */
+1:
+       ldr r2, [r3]
+       cmp r4, r2
+       bgt 1b
+
+mem_init:
+
+       ldr     r1,  =MEMC_BASE         /* get memory controller base addr. */
+
+       /* ---------------------------------------------------------------- */
+       /* Step 2a: Initialize Asynchronous static memory controller        */
+       /* ---------------------------------------------------------------- */
+
+       /* MSC registers: timing, bus width, mem type                       */
+
+       /* MSC0: nCS(0,1)                                                   */
+       ldr     r2,   =CFG_MSC0_VAL
+       str     r2,   [r1, #MSC0_OFFSET]
+       ldr     r2,   [r1, #MSC0_OFFSET]        /* read back to ensure      */
+                                               /* that data latches        */
+       /* MSC1: nCS(2,3)                                                   */
+       ldr     r2,  =CFG_MSC1_VAL
+       str     r2,  [r1, #MSC1_OFFSET]
+       ldr     r2,  [r1, #MSC1_OFFSET]
+
+       /* MSC2: nCS(4,5)                                                   */
+       ldr     r2,  =CFG_MSC2_VAL
+       str     r2,  [r1, #MSC2_OFFSET]
+       ldr     r2,  [r1, #MSC2_OFFSET]
+
+       /* ---------------------------------------------------------------- */
+       /* Step 2b: Initialize Card Interface                               */
+       /* ---------------------------------------------------------------- */
+
+       /* MECR: Memory Expansion Card Register                             */
+       ldr     r2,  =CFG_MECR_VAL
+       str     r2,  [r1, #MECR_OFFSET]
+       ldr     r2,     [r1, #MECR_OFFSET]
+
+       /* MCMEM0: Card Interface slot 0 timing                             */
+       ldr     r2,  =CFG_MCMEM0_VAL
+       str     r2,  [r1, #MCMEM0_OFFSET]
+       ldr     r2,     [r1, #MCMEM0_OFFSET]
+
+       /* MCMEM1: Card Interface slot 1 timing                             */
+       ldr     r2,  =CFG_MCMEM1_VAL
+       str     r2,  [r1, #MCMEM1_OFFSET]
+       ldr     r2,     [r1, #MCMEM1_OFFSET]
+
+       /* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+       ldr     r2,  =CFG_MCATT0_VAL
+       str     r2,  [r1, #MCATT0_OFFSET]
+       ldr     r2,     [r1, #MCATT0_OFFSET]
+
+       /* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+       ldr     r2,  =CFG_MCATT1_VAL
+       str     r2,  [r1, #MCATT1_OFFSET]
+       ldr     r2,     [r1, #MCATT1_OFFSET]
+
+       /* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+       ldr     r2,  =CFG_MCIO0_VAL
+       str     r2,  [r1, #MCIO0_OFFSET]
+       ldr     r2,     [r1, #MCIO0_OFFSET]
+
+       /* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+       ldr     r2,  =CFG_MCIO1_VAL
+       str     r2,  [r1, #MCIO1_OFFSET]
+       ldr     r2,     [r1, #MCIO1_OFFSET]
+
+       /* ---------------------------------------------------------------- */
+       /* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+       /* ---------------------------------------------------------------- */
+       ldr     r2,  =CFG_FLYCNFG_VAL
+       str     r2,  [r1, #FLYCNFG_OFFSET]
+       str     r2,     [r1, #FLYCNFG_OFFSET]
+
+       /* ---------------------------------------------------------------- */
+       /* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+       /* ---------------------------------------------------------------- */
+
+       /* Before accessing MDREFR we need a valid DRI field, so we set     */
+       /* this to power on defaults + DRI field.                           */
+
+       ldr     r4,     [r1, #MDREFR_OFFSET]
+       ldr     r2,     =0xFFF
+       bic     r4,     r4, r2
+
+       ldr     r3,     =CFG_MDREFR_VAL
+       and     r3,     r3,  r2
+
+       orr     r4,     r4, r3
+       str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+
+       orr     r4,  r4, #MDREFR_K0RUN
+       orr     r4,  r4, #MDREFR_K0DB4
+       orr     r4,  r4, #MDREFR_K0FREE
+       orr     r4,  r4, #MDREFR_K0DB2
+       orr     r4,  r4, #MDREFR_K1DB2
+       bic     r4,  r4, #MDREFR_K1FREE
+       bic     r4,  r4, #MDREFR_K2FREE
+
+       str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+       ldr     r4,  [r1, #MDREFR_OFFSET]
+
+       /* Note: preserve the mdrefr value in r4                            */
+
+
+       /* ---------------------------------------------------------------- */
+       /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+       /* ---------------------------------------------------------------- */
+
+       /* Initialize SXCNFG register. Assert the enable bits               */
+
+       /* Write SXMRS to cause an MRS command to all enabled banks of      */
+       /* synchronous static memory. Note that SXLCR need not be written   */
+       /* at this time.                                                    */
+
+       ldr     r2,  =CFG_SXCNFG_VAL
+       str     r2,  [r1, #SXCNFG_OFFSET]
+
+       /* ---------------------------------------------------------------- */
+       /* Step 4: Initialize SDRAM                                         */
+       /* ---------------------------------------------------------------- */
+
+       bic     r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+       orr     r4, r4, #MDREFR_K1RUN
+       bic     r4, r4, #MDREFR_K2DB2
+       str     r4, [r1, #MDREFR_OFFSET]
+       ldr     r4, [r1, #MDREFR_OFFSET]
+
+       bic     r4, r4, #MDREFR_SLFRSH
+       str     r4, [r1, #MDREFR_OFFSET]
+       ldr     r4, [r1, #MDREFR_OFFSET]
+
+       orr     r4, r4, #MDREFR_E1PIN
+       str     r4, [r1, #MDREFR_OFFSET]
+       ldr     r4, [r1, #MDREFR_OFFSET]
+
+       nop
+       nop
+
+
+       /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+       /*          configure but not enable each SDRAM partition pair.     */
+
+       ldr     r4,     =CFG_MDCNFG_VAL
+       bic     r4,     r4,     #(MDCNFG_DE0|MDCNFG_DE1)
+       bic     r4,     r4,     #(MDCNFG_DE2|MDCNFG_DE3)
+
+       str     r4,     [r1, #MDCNFG_OFFSET]    /* write back MDCNFG        */
+       ldr     r4,     [r1, #MDCNFG_OFFSET]
+
+
+       /* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+       /*          100..200 Âµsec.                                          */
+
+       ldr r3, =OSCR                   /* reset the OS Timer Count to zero */
+       mov r2, #0
+       str r2, [r3]
+       ldr r4, =0x300                  /* really 0x2E1 is about 200usec,   */
+                                       /* so 0x300 should be plenty        */
+1:
+           ldr r2, [r3]
+           cmp r4, r2
+           bgt 1b
+
+
+       /* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+       /*          attempting non-burst read or write accesses to disabled */
+       /*          SDRAM, as commonly specified in the power up sequence   */
+       /*          documented in SDRAM data sheets. The address(es) used   */
+       /*          for this purpose must not be cacheable.                 */
+
+       ldr     r3,     =CFG_DRAM_BASE
+       str     r2,     [r3]
+       str     r2,     [r3]
+       str     r2,     [r3]
+       str     r2,     [r3]
+       str     r2,     [r3]
+       str     r2,     [r3]
+       str     r2,     [r3]
+       str     r2,     [r3]
+
+
+       /* Step 4g: Write MDCNFG with enable bits asserted                  */
+       /*          (MDCNFG:DEx set to 1).                                  */
+
+       ldr     r3,     [r1, #MDCNFG_OFFSET]
+       mov     r4, r3
+       orr     r3,     r3,     #MDCNFG_DE0
+       str     r3,     [r1, #MDCNFG_OFFSET]
+       mov     r0, r3
+
+       /* Step 4h: Write MDMRS.                                            */
+
+       ldr     r2,  =CFG_MDMRS_VAL
+       str     r2,  [r1, #MDMRS_OFFSET]
+
+       /* enable APD */
+       ldr     r3,  [r1, #MDREFR_OFFSET]
+       orr     r3,  r3,  #MDREFR_APD
+       str     r3,  [r1, #MDREFR_OFFSET]
+
+       /* We are finished with Intel's memory controller initialisation    */
+
+
+setvoltage:
+
+       mov     r10,    lr
+       bl      initPXAvoltage  /* In case the board is rebooting with a    */
+       mov     lr,     r10     /* low voltage raise it up to a good one.   */
+
+#if 1
+       b initirqs
+#endif
+
+wakeup:
+       /* Are we waking from sleep? */
+       ldr     r0,     =RCSR
+       ldr     r1,     [r0]
+       and     r1,     r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+       str     r1,     [r0]
+       teq     r1,     #RCSR_SMR
+
+       bne     initirqs
+
+       ldr     r0,     =PSSR
+       mov     r1,     #PSSR_PH
+       str     r1,     [r0]
+
+       /* if so, resume at PSPR */
+       ldr     r0,     =PSPR
+       ldr     r1,     [r0]
+       mov     pc,     r1
+
+       /* ---------------------------------------------------------------- */
+       /* Disable (mask) all interrupts at interrupt controller            */
+       /* ---------------------------------------------------------------- */
+
+initirqs:
+
+       mov     r1,  #0         /* clear int. level register (IRQ, not FIQ) */
+       ldr     r2,  =ICLR
+       str     r1,  [r2]
+
+       ldr     r2,  =ICMR      /* mask all interrupts at the controller    */
+       str     r1,  [r2]
+
+       /* ---------------------------------------------------------------- */
+       /* Clock initialisation                                             */
+       /* ---------------------------------------------------------------- */
+
+initclks:
+
+       /* Disable the peripheral clocks, and set the core clock frequency  */
+
+       /* Turn Off on-chip peripheral clocks (except for memory)           */
+       /* for re-configuration.                                            */
+       ldr     r1,  =CKEN
+       ldr     r2,  =CFG_CKEN
+       str     r2,  [r1]
+
+       /* ... and write the core clock config register                     */
+       ldr     r2,  =CFG_CCCR
+       ldr     r1,  =CCCR
+       str     r2,  [r1]
+
+       /* Turn on turbo mode */
+       mrc     p14, 0, r2, c6, c0, 0
+       orr     r2, r2, #0xB            /* Turbo, Fast-Bus, Freq change**/
+       mcr     p14, 0, r2, c6, c0, 0
+
+       /* Re-write MDREFR */
+       ldr     r1, =MEMC_BASE
+       ldr     r2, [r1, #MDREFR_OFFSET]
+       str     r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+       /* enable the 32Khz oscillator for RTC and PowerManager             */
+       ldr     r1,  =OSCC
+       mov     r2,  #OSCC_OON
+       str     r2,  [r1]
+
+       /* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+       /* has settled.                                                     */
+60:
+       ldr     r2, [r1]
+       ands    r2, r2, #1
+       beq     60b
+#else
+#error "RTC not defined"
+#endif
+
+       /* Interrupt init: Mask all interrupts                              */
+    ldr r0, =ICMR /* enable no sources */
+       mov r1, #0
+    str r1, [r0]
+       /* FIXME */
+
+#ifdef NODEBUG
+       /*Disable software and data breakpoints */
+       mov     r0,#0
+       mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
+       mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
+       mcr     p15,0,r0,c14,c4,0  /* dbcon */
+
+       /*Enable all debug functionality */
+       mov     r0,#0x80000000
+       mcr     p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+       /* ---------------------------------------------------------------- */
+       /* End lowlevel_init                                                        */
+       /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+       mov     pc, lr
diff --git a/board/trizepsiv/pxavoltage.S b/board/trizepsiv/pxavoltage.S
new file mode 100644 (file)
index 0000000..5e41132
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+
+               .global initPXAvoltage
+
+initPXAvoltage:
+               mov     pc, lr
+
diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds
new file mode 100644 (file)
index 0000000..f010239
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text      :
+       {
+         cpu/pxa/start.o       (.text)
+         *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}
index e0d531bd917c9a772577a07d719a7a848adf3322..6131b5c35708c107219310e52dfeae7df20f782a 100644 (file)
@@ -99,7 +99,7 @@ void eth_halt(void);
 static int dm9000_probe(void);
 static u16 phy_read(int);
 static void phy_write(int, u16);
-static u16 read_srom_word(int);
+u16 read_srom_word(int);
 static u8 DM9000_ior(int);
 static void DM9000_iow(int reg, u8 value);
 
@@ -537,7 +537,7 @@ eth_rx(void)
 /*
   Read a word data from SROM
 */
-static u16
+u16
 read_srom_word(int offset)
 {
        DM9000_iow(DM9000_EPAR, offset);
@@ -547,6 +547,18 @@ read_srom_word(int offset)
        return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
 }
 
+void
+write_srom_word(int offset, u16 val)
+{
+       DM9000_iow(DM9000_EPAR, offset);
+       DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
+       DM9000_iow(DM9000_EPDRL, (val & 0xff));
+       DM9000_iow(DM9000_EPCR, 0x12);
+       udelay(8000);
+       DM9000_iow(DM9000_EPCR, 0);
+}
+
+
 /*
    Read a byte from I/O port
 */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
new file mode 100644 (file)
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+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_PXA27X          1       /* This is an PXA27x CPU    */
+
+#define LITTLEENDIAN           1       /* used by usb_ohci.c           */
+
+#define CONFIG_MMC             1
+#define BOARD_LATE_INIT                1
+
+#undef CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN     (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_FFUART         1       /* we use FFUART on Conxs */
+#define CONFIG_BTUART         1       /* we use BTUART on Conxs */
+#define CONFIG_STUART         1       /* we use STUART on Conxs */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE               38400
+
+#define CONFIG_DOS_PARTITION   1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY       3
+#define CONFIG_SERVERIP                192.168.1.99
+#define CONFIG_BOOTCOMMAND     "run boot_flash"
+#define CONFIG_BOOTARGS                "console=ttyS0,38400 ramdisk_size=12288"\
+                               " rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                      \
+       "program_boot_mmc="                                             \
+                       "mw.b 0xa0010000 0xff 0x20000; "                \
+                       "if      mmcinit && "                           \
+                               "fatload mmc 0 0xa0010000 u-boot.bin; " \
+                       "then "                                         \
+                               "protect off 0x0 0x1ffff; "             \
+                               "erase 0x0 0x1ffff; "                   \
+                               "cp.b 0xa0010000 0x0 0x20000; "         \
+                       "fi\0"                                          \
+       "program_uzImage_mmc="                                          \
+                       "mw.b 0xa0010000 0xff 0x180000; "               \
+                       "if      mmcinit && "                           \
+                               "fatload mmc 0 0xa0010000 uzImage; "    \
+                       "then "                                         \
+                               "protect off 0x40000 0x1bffff; "        \
+                               "erase 0x40000 0x1bffff; "              \
+                               "cp.b 0xa0010000 0x40000 0x180000; "    \
+                       "fi\0"                                          \
+       "program_ramdisk_mmc="                                          \
+                       "mw.b 0xa0010000 0xff 0x500000; "               \
+                       "if      mmcinit && "                           \
+                               "fatload mmc 0 0xa0010000 ramdisk.gz; " \
+                       "then "                                         \
+                               "protect off 0x1c0000 0x6bffff; "       \
+                               "erase 0x1c0000 0x6bffff; "             \
+                               "cp.b 0xa0010000 0x1c0000 0x500000; "   \
+                       "fi\0"                                          \
+       "boot_mmc="                                                     \
+                       "if      mmcinit && "                           \
+                               "fatload mmc 0 0xa0030000 uzImage && "  \
+                               "fatload mmc 0 0xa0800000 ramdisk.gz; " \
+                       "then "                                         \
+                               "bootm 0xa0030000; "                    \
+                       "fi\0"                                          \
+       "boot_flash="                                                   \
+                       "cp.b 0x1c0000 0xa0800000 0x500000; "           \
+                       "bootm 0x40000\0"                               \
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG      1      /* enable passing of ATAGs      */
+/* #define CONFIG_INITRD_TAG    1 */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE   230400          /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX  2               /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_HUSH_PARSER                1
+#define CFG_PROMPT_HUSH_PS2    "> "
+
+#define CFG_LONGHELP                           /* undef to save memory         */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT             "$ "            /* Monitor Command Prompt */
+#else
+#define CFG_PROMPT             "=> "           /* Monitor Command Prompt */
+#endif
+#define CFG_CBSIZE             256             /* Console I/O Buffer Size      */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16              /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CFG_DEVICE_NULLDEV     1
+
+#define CFG_MEMTEST_START      0xa0400000      /* memtest works on     */
+#define CFG_MEMTEST_END                0xa0800000      /* 4 ... 8 MB in DRAM   */
+
+#undef CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR          0xa1000000      /* default load address */
+
+#define CFG_HZ                 3686400         /* incrementer freq: 3.6864 MHz */
+#define CFG_CPUSPEED           0x207           /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+                                               /* valid baudrates */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+#define CFG_MMC_BASE           0xF0000000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ   (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ   (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS   4          /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1           0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE      0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2           0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE      0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3           0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE      0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4           0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE      0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1           0x00000000 /* Flash Bank #1 */
+
+#define CFG_DRAM_BASE          0xa0000000
+#define CFG_DRAM_SIZE          0x04000000
+
+#define CFG_FLASH_BASE         PHYS_FLASH_1
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPSR0_VAL          0x00018000
+#define CFG_GPSR1_VAL          0x00000000
+#define CFG_GPSR2_VAL          0x400dc000
+#define CFG_GPSR3_VAL          0x00000000
+#define CFG_GPCR0_VAL          0x00000000
+#define CFG_GPCR1_VAL          0x00000000
+#define CFG_GPCR2_VAL          0x00000000
+#define CFG_GPCR3_VAL          0x00000000
+#define CFG_GPDR0_VAL          0x00018000
+#define CFG_GPDR1_VAL          0x00028801
+#define CFG_GPDR2_VAL          0x520dc000
+#define CFG_GPDR3_VAL          0x0001E000
+#define CFG_GAFR0_L_VAL                0x801c0000
+#define CFG_GAFR0_U_VAL                0x00000013
+#define CFG_GAFR1_L_VAL                0x6990100A
+#define CFG_GAFR1_U_VAL                0x00000008
+#define CFG_GAFR2_L_VAL                0xA0000000
+#define CFG_GAFR2_U_VAL                0x010900F2
+#define CFG_GAFR3_L_VAL                0x54000003
+#define CFG_GAFR3_U_VAL                0x00002401
+#define CFG_GRER0_VAL          0x00000000
+#define CFG_GRER1_VAL          0x00000000
+#define CFG_GRER2_VAL          0x00000000
+#define CFG_GRER3_VAL          0x00000000
+#define CFG_GFER0_VAL          0x00000000
+#define CFG_GFER1_VAL          0x00000000
+#define CFG_GFER2_VAL          0x00000000
+#define CFG_GFER3_VAL          0x00000020
+
+
+#define CFG_PSSR_VAL           0x20    /* CHECK */
+
+/*
+ * Clock settings
+ */
+#define CFG_CKEN               0x01FFFFFF      /* CHECK */
+#define CFG_CCCR               0x02000290 /*   520Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CFG_MSC0_VAL           0x4df84df0
+#define CFG_MSC1_VAL           0x7ff87ff4
+#define CFG_MSC2_VAL           0xa26936d4
+#define CFG_MDCNFG_VAL         0x880009C9
+#define CFG_MDREFR_VAL         0x20ca201e
+#define CFG_MDMRS_VAL          0x00220022
+
+#define CFG_FLYCNFG_VAL                0x00000000
+#define CFG_SXCNFG_VAL         0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CFG_MECR_VAL           0x00000001
+#define CFG_MCMEM0_VAL         0x00004204
+#define CFG_MCMEM1_VAL         0x00010204
+#define CFG_MCATT0_VAL         0x00010504
+#define CFG_MCATT1_VAL         0x00010504
+#define CFG_MCIO0_VAL          0x00008407
+#define CFG_MCIO1_VAL          0x0000c108
+
+#define CONFIG_DRIVER_DM9000           1
+#define CONFIG_DRIVER_DM9000           1
+#define CONFIG_DM9000_BASE     0x08000000
+#define DM9000_IO                      CONFIG_DM9000_BASE
+#define DM9000_DATA                    (CONFIG_DM9000_BASE+0x8004)
+/* #define CONFIG_DM9000_USE_8BIT */
+/* #define CONFIG_DM9000_USE_16BIT */
+#define CONFIG_DM9000_USE_32BIT
+
+#define CONFIG_USB_OHCI_NEW    1
+#define CFG_USB_OHCI_BOARD_INIT        1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS    3
+#define CFG_USB_OHCI_REGS_BASE 0x4C000000
+#define CFG_USB_OHCI_SLOT_NAME "trizepsiv"
+#define CONFIG_USB_STORAGE     1
+#define CFG_USB_OHCI_CPU_INIT  1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER   1
+
+#define CFG_MONITOR_BASE       0
+#define CFG_MONITOR_LEN                0x40000
+
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     4 + 255  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT   (25*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT   (25*CFG_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CFG_FLASH_USE_BUFFER_WRITE 1
+
+/* Flash environment locations */
+#define CFG_ENV_IS_IN_FLASH    1
+#define CFG_ENV_ADDR           (PHYS_FLASH_1 + CFG_MONITOR_LEN)        /* Addr of Environment Sector   */
+#define CFG_ENV_SIZE           0x40000 /* Total Size of Environment            */
+#define CFG_ENV_SECT_SIZE      0x40000 /* Total Size of Environment Sector     */
+
+/* Address and size of Redundant Environment Sector    */
+#define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
+
+#endif /* __CONFIG_H */