]> git.sur5r.net Git - u-boot/commitdiff
mpc8xx: remove IP860 board support
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Mon, 15 Dec 2014 14:26:16 +0000 (23:26 +0900)
committerTom Rini <trini@ti.com>
Mon, 5 Jan 2015 17:08:53 +0000 (12:08 -0500)
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
13 files changed:
arch/powerpc/cpu/mpc8xx/Kconfig
arch/powerpc/cpu/mpc8xx/cpu_init.c
arch/powerpc/cpu/mpc8xx/serial.c
board/ip860/Kconfig [deleted file]
board/ip860/MAINTAINERS [deleted file]
board/ip860/Makefile [deleted file]
board/ip860/flash.c [deleted file]
board/ip860/ip860.c [deleted file]
board/ip860/u-boot.lds.debug [deleted file]
configs/IP860_defconfig [deleted file]
doc/README.scrapyard
include/commproc.h
include/configs/IP860.h [deleted file]

index ef5c511374ef4663d61a5b5b0ddfb485d6c4499b..45e7d7e2916376f7563815623cf7e67800b4d72b 100644 (file)
@@ -13,9 +13,6 @@ config TARGET_COGENT_MPC8XX
 config TARGET_ESTEEM192E
        bool "Support ESTEEM192E"
 
-config TARGET_IP860
-       bool "Support IP860"
-
 config TARGET_TQM823L
        bool "Support TQM823L"
 
@@ -56,7 +53,6 @@ endchoice
 
 source "board/cogent/Kconfig"
 source "board/esteem192e/Kconfig"
-source "board/ip860/Kconfig"
 source "board/tqc/tqm8xx/Kconfig"
 
 endmenu
index 753d25da6bb58d1bd3d6056d894c2e3631d0afd4..f621d6285ceb730b0380c1ee8e2988aa0a1214fe 100644 (file)
@@ -125,12 +125,6 @@ void cpu_init_f (volatile immap_t * immr)
         *  I owe him a free beer. - wd]
         */
 
-#if defined(CONFIG_IP860)      || \
-    defined(CONFIG_RMU)
-
-       memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
-#endif
-
 #if defined(CONFIG_SYS_OR0_REMAP)
        memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
 #endif
@@ -150,10 +144,6 @@ void cpu_init_f (volatile immap_t * immr)
        memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 #endif
 
-#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
-       memctl->memc_br0 = 0;
-#endif
-
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
        memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
        memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
index bb16b17937cf3e9503c5517d88097ff98fe21146..af65c969c2f51c3d9a72629d139bc1e2fbfeeb54 100644 (file)
@@ -416,18 +416,13 @@ static int scc_init (void)
        cp->cp_pbdir &= ~0x06;
        cp->cp_pbodr &= ~0x06;
 
-#elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
+#elif (SCC_INDEX < 2)
        /*
         * Standard configuration for SCC's is on Part A
         */
        ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
        ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
        ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
-#else
-       /*
-        * The IP860 has SCC3 and SCC4 on Port D
-        */
-       ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
 #endif
 
        /* Allocate space for two buffer descriptors in the DP ram. */
diff --git a/board/ip860/Kconfig b/board/ip860/Kconfig
deleted file mode 100644 (file)
index 955c9db..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_IP860
-
-config SYS_BOARD
-       default "ip860"
-
-config SYS_CONFIG_NAME
-       default "IP860"
-
-endif
diff --git a/board/ip860/MAINTAINERS b/board/ip860/MAINTAINERS
deleted file mode 100644 (file)
index 36d5690..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-IP860 BOARD
-M:     Wolfgang Denk <wd@denx.de>
-S:     Maintained
-F:     board/ip860/
-F:     include/configs/IP860.h
-F:     configs/IP860_defconfig
diff --git a/board/ip860/Makefile b/board/ip860/Makefile
deleted file mode 100644 (file)
index 3c60006..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = ip860.o flash.o
diff --git a/board/ip860/flash.c b/board/ip860/flash.c
deleted file mode 100644 (file)
index 542b0c8..0000000
+++ /dev/null
@@ -1,440 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t   flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR      (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE      CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-       volatile immap_t        *immap  = (immap_t *)CONFIG_SYS_IMMR;
-       volatile memctl8xx_t    *memctl = &immap->im_memctl;
-       volatile ip860_bcsr_t   *bcsr   = (ip860_bcsr_t *)BCSR_BASE;
-       unsigned long size;
-       int i;
-
-       /* Init: enable write,
-        * or we cannot even write flash commands
-        */
-       bcsr->bd_ctrl |= BD_CTRL_FLWE;
-
-       for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-       }
-
-       /* Static FLASH Bank configuration here - FIXME XXX */
-
-       size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
-
-       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-                       size, size<<20);
-       }
-
-       /* Remap FLASH according to real size */
-       memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-       memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
-                               (memctl->memc_br1 & ~(BR_BA_MSK));
-
-       /* Re-do sizing to get full correct info */
-       size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       flash_info[0].size = size;
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_SYS_MONITOR_BASE,
-                     CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-                     &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-       /* ENV protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                     CONFIG_ENV_ADDR,
-                     CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-                     &flash_info[0]);
-#endif
-       return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-       int i;
-
-       /* all possible flash types
-        * (28F016SV, 28F160S3, 28F320S3)
-        * have the same erase block size: 64 kB per chip,
-        * of 128 kB per bank
-        */
-
-       /* set up sector start address table */
-       for (i = 0; i < info->sector_count; i++) {
-               info->start[i] = base;
-               base += 0x00020000;
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf ("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_INTEL:   printf ("Intel ");              break;
-       default:                printf ("Unknown Vendor ");     break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_28F016SV:    printf ("28F016SV (16 Mbit, 32 x 64k)\n");
-                               break;
-       case FLASH_28F160S3:    printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
-                               break;
-       case FLASH_28F320S3:    printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
-                               break;
-       default:                printf ("Unknown Chip Type\n");
-                               break;
-       }
-
-       printf ("  Size: %ld MB in %d Sectors\n",
-               info->size >> 20, info->sector_count);
-
-       printf ("  Sector Start Addresses:");
-       for (i=0; i<info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf ("\n   ");
-               printf (" %08lX%s",
-                       info->start[i],
-                       info->protect[i] ? " (RO)" : "     "
-               );
-       }
-       printf ("\n");
-       return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
-       short i;
-       ulong value;
-       ulong base = (ulong)addr;
-
-       /* Write "Intelligent Identifier" command: read Manufacturer ID */
-       *addr = 0x90909090;
-
-       value = addr[0];
-       switch (value) {
-       case (MT_MANUFACT & 0x00FF00FF):        /* MT or => Intel */
-       case (INTEL_ALT_MANU & 0x00FF00FF):
-               info->flash_id = FLASH_MAN_INTEL;
-               break;
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               return (0);                     /* no or unknown flash  */
-       }
-
-       value = addr[1];                        /* device ID            */
-
-       switch (value) {
-       case (INTEL_ID_28F016S):
-               info->flash_id += FLASH_28F016SV;
-               info->sector_count = 32;
-               info->size = 0x00400000;
-               break;                          /* => 2x2 MB            */
-
-       case (INTEL_ID_28F160S3):
-               info->flash_id += FLASH_28F160S3;
-               info->sector_count = 32;
-               info->size = 0x00400000;
-               break;                          /* => 2x2 MB            */
-
-       case (INTEL_ID_28F320S3):
-               info->flash_id += FLASH_28F320S3;
-               info->sector_count = 64;
-               info->size = 0x00800000;
-               break;                          /* => 2x4 MB            */
-
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               return (0);                     /* => no or unknown flash */
-
-       }
-
-       /* set up sector start address table */
-       for (i = 0; i < info->sector_count; i++) {
-               info->start[i] = base + (i * 0x00020000);
-               /* don't know how to check sector protection */
-               info->protect[i] = 0;
-       }
-
-       /*
-        * Prevent writes to uninitialized FLASH.
-        */
-       if (info->flash_id != FLASH_UNKNOWN) {
-               addr = (vu_long *)info->start[0];
-
-               *addr = 0xFFFFFF;       /* reset bank to read array mode */
-       }
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int    flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-       int flag, prot, sect;
-       ulong start, now, last;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf ("- missing\n");
-               } else {
-                       printf ("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
-               printf ("Can't erase unknown flash type %08lx - aborted\n",
-                       info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect=s_first; sect<=s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf ("- Warning: %d protected sectors will not be erased!\n",
-                       prot);
-       } else {
-               printf ("\n");
-       }
-
-       start = get_timer (0);
-       last  = start;
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect<=s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       vu_long *addr = (vu_long *)(info->start[sect]);
-
-                       /* Disable interrupts which might cause a timeout here */
-                       flag = disable_interrupts();
-
-                       /* Single Block Erase Command */
-                       *addr = 0x20202020;
-                       /* Confirm */
-                       *addr = 0xD0D0D0D0;
-                       /* Resume Command, as per errata update */
-                       *addr = 0xD0D0D0D0;
-
-                       /* re-enable interrupts if necessary */
-                       if (flag)
-                               enable_interrupts();
-
-                       /* wait at least 80us - let's wait 1 ms */
-                       udelay (1000);
-
-                       while ((*addr & 0x00800080) != 0x00800080) {
-                               if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                                       printf ("Timeout\n");
-                                       *addr = 0xFFFFFFFF;     /* reset bank */
-                                       return 1;
-                               }
-                               /* show that we're waiting */
-                               if ((now - last) > 1000) {      /* every second */
-                                       putc ('.');
-                                       last = now;
-                               }
-                       }
-
-                       /* reset to read mode */
-                       *addr = 0xFFFFFFFF;
-               }
-       }
-
-       printf (" done\n");
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-       ulong cp, wp, data;
-       int i, l, rc;
-
-       wp = (addr & ~3);       /* get lower word aligned address */
-
-       /*
-        * handle unaligned start bytes
-        */
-       if ((l = addr - wp) != 0) {
-               data = 0;
-               for (i=0, cp=wp; i<l; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-               for (; i<4 && cnt>0; ++i) {
-                       data = (data << 8) | *src++;
-                       --cnt;
-                       ++cp;
-               }
-               for (; cnt==0 && i<4; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-
-               if ((rc = write_word(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += 4;
-       }
-
-       /*
-        * handle word aligned part
-        */
-       while (cnt >= 4) {
-               data = 0;
-               for (i=0; i<4; ++i) {
-                       data = (data << 8) | *src++;
-               }
-               if ((rc = write_word(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp  += 4;
-               cnt -= 4;
-       }
-
-       if (cnt == 0) {
-               return (0);
-       }
-
-       /*
-        * handle unaligned tail bytes
-        */
-       data = 0;
-       for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-               data = (data << 8) | *src++;
-               --cnt;
-       }
-       for (; i<4; ++i, ++cp) {
-               data = (data << 8) | (*(uchar *)cp);
-       }
-
-       return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-       vu_long *addr = (vu_long *)dest;
-       ulong start, csr;
-       int flag;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*addr & data) != data) {
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       /* Write Command */
-       *addr = 0x10101010;
-
-       /* Write Data */
-       *addr = data;
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* data polling for D7 */
-       start = get_timer (0);
-       flag  = 0;
-       while (((csr = *addr) & 0x00800080) != 0x00800080) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       flag = 1;
-                       break;
-               }
-       }
-       if (csr & 0x00400040) {
-printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
-               flag = 1;
-       }
-
-       /* Clear Status Registers Command */
-       *addr = 0x50505050;
-       /* Reset to read array mode */
-       *addr = 0xFFFFFFFF;
-
-       return (flag);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c
deleted file mode 100644 (file)
index 4e3b1b5..0000000
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <mpc8xx.h>
-
-/* ------------------------------------------------------------------------- */
-
-static long int dram_size (long int, long int *, long int);
-unsigned long ip860_get_dram_size(void);
-unsigned long ip860_get_clk_freq (void);
-/* ------------------------------------------------------------------------- */
-
-#define        _NOT_USED_      0xFFFFFFFF
-
-const uint sdram_table[] = {
-       /*
-        * Single Read. (Offset 0 in UPMA RAM)
-        */
-       0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
-       0x1ff77c47,                                     /* last */
-       /*
-        * SDRAM Initialization (offset 5 in UPMA RAM)
-        *
-        * This is no UPM entry point. The following definition uses
-        * the remaining space to establish an initialization
-        * sequence, which is executed by a RUN command.
-        *
-        */
-       0x1ff77c34, 0xefeabc34, 0x1fb57c35,     /* last */
-       /*
-        * Burst Read. (Offset 8 in UPMA RAM)
-        */
-       0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
-       0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /*
-        * Single Write. (Offset 18 in UPMA RAM)
-        */
-       0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /*
-        * Burst Write. (Offset 20 in UPMA RAM)
-        */
-       0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-       0xf0affc00, 0xe1bbbc04, 0x1ff77c47,     /* last */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /*
-        * Refresh  (Offset 30 in UPMA RAM)
-        */
-       0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       0xfffffc84, 0xfffffc07,         /* last */
-       _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       /*
-        * Exception. (Offset 3c in UPMA RAM)
-        */
-       0x7ffffc07,                                     /* last */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-};
-
-
-/* ------------------------------------------------------------------------- */
-int board_early_init_f(void)
-{
-    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
-    volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
-    memctl->memc_or4 = CONFIG_SYS_OR4;
-    memctl->memc_br4 = CONFIG_SYS_BR4;
-
-    return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- *
- * Test ID string (IP860...)
- */
-
-int checkboard (void)
-{
-       unsigned char *s, *e;
-       unsigned char buf[64];
-       int i;
-
-       puts ("Board: ");
-
-       i = getenv_f("serial#", (char *)buf, sizeof (buf));
-       s = (i > 0) ? buf : NULL;
-
-       if (!s || strncmp ((char *)s, "IP860", 5)) {
-               puts ("### No HW ID - assuming IP860");
-       } else {
-               for (e = s; *e; ++e) {
-                       if (*e == ' ')
-                               break;
-               }
-
-               for (; s < e; ++s) {
-                       putc (*s);
-               }
-       }
-
-       putc ('\n');
-
-       return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size;
-       ulong refresh_val;
-
-       upmconfig (UPMA, (uint *) sdram_table,
-                          sizeof (sdram_table) / sizeof (uint));
-
-       /*
-        * Preliminary prescaler for refresh
-        */
-       if (ip860_get_clk_freq() == 50000000)
-       {
-               memctl->memc_mptpr = 0x0400;
-               refresh_val = 0xC3000000;
-       }
-       else
-       {
-               memctl->memc_mptpr = 0x0200;
-               refresh_val = 0x9C000000;
-       }
-
-
-       memctl->memc_mar = 0x00000088;
-
-       /*
-        * Map controller banks 2 to the SDRAM address
-        */
-       memctl->memc_or2 = CONFIG_SYS_OR2;
-       memctl->memc_br2 = CONFIG_SYS_BR2;
-
-       /* IP860 boards have only one bank SDRAM */
-
-
-       udelay (200);
-
-       /* perform SDRAM initializsation sequence */
-
-       memctl->memc_mamr = 0x00804114 | refresh_val;
-       memctl->memc_mcr  = 0x80004105; /* run precharge pattern from loc 5 */
-       udelay(1);
-       memctl->memc_mamr = 0x00804118 | refresh_val;
-       memctl->memc_mcr  = 0x80004130; /* run refresh pattern 8 times */
-
-
-       udelay (1000);
-
-       /*
-        * Check SDRAM Memory Size
-        */
-       if (ip860_get_dram_size() == 16)
-               size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
-       else
-               size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
-
-       udelay (1000);
-
-       memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
-       memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
-
-       udelay (10000);
-
-       /*
-        * Also, map other memory to correct position
-        */
-
-#if (defined(CONFIG_SYS_OR1) && defined(CONFIG_SYS_BR1_PRELIM))
-       memctl->memc_or1 = CONFIG_SYS_OR1;
-       memctl->memc_br1 = CONFIG_SYS_BR1;
-#endif
-
-#if defined(CONFIG_SYS_OR3) && defined(CONFIG_SYS_BR3)
-       memctl->memc_or3 = CONFIG_SYS_OR3;
-       memctl->memc_br3 = CONFIG_SYS_BR3;
-#endif
-
-#if defined(CONFIG_SYS_OR4) && defined(CONFIG_SYS_BR4)
-       memctl->memc_or4 = CONFIG_SYS_OR4;
-       memctl->memc_br4 = CONFIG_SYS_BR4;
-#endif
-
-#if defined(CONFIG_SYS_OR5) && defined(CONFIG_SYS_BR5)
-       memctl->memc_or5 = CONFIG_SYS_OR5;
-       memctl->memc_br5 = CONFIG_SYS_BR5;
-#endif
-
-#if defined(CONFIG_SYS_OR6) && defined(CONFIG_SYS_BR6)
-       memctl->memc_or6 = CONFIG_SYS_OR6;
-       memctl->memc_br6 = CONFIG_SYS_BR6;
-#endif
-
-#if defined(CONFIG_SYS_OR7) && defined(CONFIG_SYS_BR7)
-       memctl->memc_or7 = CONFIG_SYS_OR7;
-       memctl->memc_br7 = CONFIG_SYS_BR7;
-#endif
-
-       return (size);
-}
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-
-static long int dram_size (long int mamr_value, long int *base,
-                                                  long int maxsize)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-       memctl->memc_mamr = mamr_value;
-
-       return (get_ram_size(base, maxsize));
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phy (void)
-{
-       volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-       ulong mask = PB_ENET_RESET | PB_ENET_JABD;
-       ulong reg;
-
-       /* Make sure PHY is not in low-power mode */
-       immr->im_cpm.cp_pbpar &= ~(mask);       /* GPIO */
-       immr->im_cpm.cp_pbodr &= ~(mask);       /* active output */
-
-       /* Set  JABD low  (no JABber Disable),
-        * and RESET high (Reset PHY)
-        */
-       reg = immr->im_cpm.cp_pbdat;
-       reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET;
-       immr->im_cpm.cp_pbdat = reg;
-
-       /* now drive outputs */
-       immr->im_cpm.cp_pbdir |= mask;  /* output */
-       udelay (1000);
-       /*
-          * Release RESET signal
-        */
-       immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET);
-       udelay (1000);
-}
-
-/* ------------------------------------------------------------------------- */
-
-unsigned long ip860_get_clk_freq(void)
-{
-       volatile ip860_bcsr_t   *bcsr   = (ip860_bcsr_t *)BCSR_BASE;
-       ulong temp;
-       uchar sysclk;
-
-       if ((bcsr->bd_status & 0x80) == 0x80)   /* bd_rev valid ? */
-               sysclk = (bcsr->bd_rev & 0x18) >> 3;
-       else
-               sysclk = 0x00;
-
-       switch (sysclk)
-       {
-               case 0x00:
-                       temp = 50000000;
-                       break;
-
-               case 0x01:
-                       temp = 80000000;
-                       break;
-
-               default:
-                       temp = 50000000;
-                       break;
-       }
-
-       return (temp);
-
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-unsigned long ip860_get_dram_size(void)
-{
-       volatile ip860_bcsr_t   *bcsr   = (ip860_bcsr_t *)BCSR_BASE;
-       ulong temp;
-       uchar dram_size;
-
-       if ((bcsr->bd_status & 0x80) == 0x80)   /* bd_rev valid ? */
-               dram_size = (bcsr->bd_rev & 0xE0) >> 5;
-       else
-               dram_size = 0x00;       /* default is 16 MB */
-
-       switch (dram_size)
-       {
-               case 0x00:
-                       temp = 16;
-                       break;
-
-               case 0x01:
-                       temp = 32;
-                       break;
-
-               default:
-                       temp = 16;
-                       break;
-       }
-
-       return (temp);
-
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug
deleted file mode 100644 (file)
index e561bb4..0000000
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)          }
-  .dynsym        : { *(.dynsym)                }
-  .dynstr        : { *(.dynstr)                }
-  .rel.text      : { *(.rel.text)              }
-  .rela.text     : { *(.rela.text)     }
-  .rel.data      : { *(.rel.data)              }
-  .rela.data     : { *(.rela.data)     }
-  .rel.rodata    : { *(.rel.rodata)    }
-  .rela.rodata   : { *(.rela.rodata)   }
-  .rel.got       : { *(.rel.got)               }
-  .rela.got      : { *(.rela.got)              }
-  .rel.ctors     : { *(.rel.ctors)     }
-  .rela.ctors    : { *(.rela.ctors)    }
-  .rel.dtors     : { *(.rel.dtors)     }
-  .rela.dtors    : { *(.rela.dtors)    }
-  .rel.bss       : { *(.rel.bss)               }
-  .rela.bss      : { *(.rela.bss)              }
-  .rel.plt       : { *(.rel.plt)               }
-  .rela.plt      : { *(.rela.plt)              }
-  .init          : { *(.init)  }
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within */
-    /* the sector layout of our flash chips!   XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc8xx/start.o    (.text)
-    arch/powerpc/lib/ppcstring.o       (.text)
-    arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
-    arch/powerpc/lib/time.o            (.text)
-    arch/powerpc/lib/ticks.o           (.text)
-/**
-    . = env_offset;
-    common/env_embedded.o(.text)
-**/
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/configs/IP860_defconfig b/configs/IP860_defconfig
deleted file mode 100644 (file)
index feb243d..0000000
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_8xx=y
-CONFIG_TARGET_IP860=y
index 252b607127a6a27585c02d8673cdbc69f7fadacb..0e39857a2a9d321a4ac06d3f020276d88cb6e7e8 100644 (file)
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+IP860            powerpc     mpc8xx         -           -           Wolfgang Denk <wd@denx.de>
 IVML24           powerpc     mpc8xx         -           -           Wolfgang Denk <wd@denx.de>
 IVMS8            powerpc     mpc8xx         -           -           Wolfgang Denk <wd@denx.de>
 lwmon            powerpc     mpc8xx         -           -           Wolfgang Denk <wd@denx.de>
index 6e0a233e7a73c16a262d7d889b032c3b4b0df0b2..c53482ccce1c2ce1a7714c56bebece8396e9dfb9 100644 (file)
@@ -484,34 +484,6 @@ typedef struct scc_enet {
 
 #endif
 
-/***  IP860  **********************************************************/
-
-#if defined(CONFIG_IP860)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define        PROFF_ENET      PROFF_SCC1
-#define        CPM_CR_ENET     CPM_CR_CH_SCC1
-#define        SCC_ENET        0
-#define PA_ENET_RXD    ((ushort)0x0001)        /* PA 15 */
-#define PA_ENET_TXD    ((ushort)0x0002)        /* PA 14 */
-#define PA_ENET_RCLK   ((ushort)0x0200)        /* PA  6 */
-#define PA_ENET_TCLK   ((ushort)0x0100)        /* PA  7 */
-
-#define PC_ENET_TENA   ((ushort)0x0001)        /* PC 15 */
-#define PC_ENET_CLSN   ((ushort)0x0010)        /* PC 11 */
-#define PC_ENET_RENA   ((ushort)0x0020)        /* PC 10 */
-
-#define PB_ENET_RESET  (uint)0x00000008        /* PB 28 */
-#define PB_ENET_JABD   (uint)0x00000004        /* PB 29 */
-
-/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT        ((uint)0x0000002C)
-#endif /* CONFIG_IP860 */
-
 /***  KM8XX  *********************************************************/
 
 /* The KM8XX Service Module uses SCC3 for Ethernet */
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
deleted file mode 100644 (file)
index 97eda58..0000000
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC860          1       /* This is a MPC860 CPU         */
-#define CONFIG_IP860           1       /* ...on a IP860 board          */
-
-#define        CONFIG_SYS_TEXT_BASE    0x10000000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_early_init_f      */
-#define CONFIG_RESET_PHY_R     1       /* Call reset_phy()             */
-
-#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
-#define CONFIG_BAUDRATE                9600
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
-"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                                     \
-       "bootp; "                                                               \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
-       "bootm"
-
-#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
-
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-
-
-/* enable I2C and select the hardware/software driver */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT            /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED      50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE      0xFE
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define PB_SCL         0x00000020      /* PB 26 */
-#define PB_SDA         0x00000010      /* PB 27 */
-
-#define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
-#define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
-#define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
-#define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
-#define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
-                       else    immr->im_cpm.cp_pbdat &= ~PB_SDA
-#define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
-                       else    immr->im_cpm.cp_pbdat &= ~PB_SCL
-#define I2C_DELAY      udelay(5)       /* 1/4 I2C clock duration */
-
-# define CONFIG_SYS_I2C_EEPROM_ADDR    0x50    /* EEPROM X24C16                */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1      /* bytes of address             */
-/* mask of address bits that overflow into the "EEPROM chip address"    */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10      /* takes up to 10 msec */
-
-#define        CONFIG_TIMESTAMP                /* Print image info with timestamp */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-/*
- * Miscellaneous configurable options
- */
-#define        CONFIG_SYS_LONGHELP                     /* undef to save memory         */
-#if defined(CONFIG_CMD_KGDB)
-#define        CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
-#else
-#define        CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
-#endif
-#define        CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define        CONFIG_SYS_MAXARGS      16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x00100000      /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
-
-#define        CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
-
-#define        CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR                0xF1000000      /* Non-standard value!! */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define        CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define        CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define        CONFIG_SYS_SDRAM_BASE           0x00000000
-#define CONFIG_SYS_FLASH_BASE          0x10000000
-#ifdef DEBUG
-#define        CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 512 kB for Monitor   */
-#else
-#if 0 /* need more space for I2C tests */
-#define        CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
-#else
-#define        CONFIG_SYS_MONITOR_LEN          (256 << 10)
-#endif
-#endif
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define        CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define        CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT      124     /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
-
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef  CONFIG_ENV_IS_IN_NVRAM
-#undef DEBUG_I2C
-#define        CONFIG_ENV_IS_IN_EEPROM
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_ADDR                0x20000000      /* use SRAM     */
-#define CONFIG_ENV_SIZE                (16<<10)        /* use 16 kB    */
-#endif /* CONFIG_ENV_IS_IN_NVRAM */
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_OFFSET               512    /* Leave 512 bytes free for other data  */
-#define CONFIG_ENV_SIZE                1536    /* Use remaining space                  */
-#endif /* CONFIG_ENV_IS_IN_EEPROM */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
-#endif
-#define CONFIG_SYS_DELAYED_ICACHE      1       /* enable ICache not before
-                                                * running in RAM.
-                                                */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                           11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- * +0x0004
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                        SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                           11-6
- *-----------------------------------------------------------------------
- * +0x0000 => 0x80600800
- */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_EARB   | SIUMCR_EARP0 | \
-                        SIUMCR_DBGC11 | SIUMCR_MLRC10)
-
-/*-----------------------------------------------------------------------
- * Clock Setting - get clock frequency from Board Revision Register
- *-----------------------------------------------------------------------
- */
-#ifndef __ASSEMBLY__
-extern  unsigned long           ip860_get_clk_freq (void);
-#endif
-#define        CONFIG_8xx_GCLK_FREQ    ip860_get_clk_freq()
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control                                11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- * +0x0200 => 0x00C2
- */
-#define CONFIG_SYS_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control               11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- * +0x0240 => 0x0082
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit, set PLL multiplication factor !
- */
-/* +0x0286 => was: 0x0000D000 */
-#define CONFIG_SYS_PLPRCR                                                      \
-               (       PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
-                       /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
-                       PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
-               )
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register              15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#define SCCR_MASK      SCCR_EBDF11
-#define CONFIG_SYS_SCCR        (SCCR_COM00     |   SCCR_TBS      |     \
-                        SCCR_RTDIV     |   SCCR_RTSEL    |     \
-                        /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
-                        SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
-                        SCCR_DFBRG00   |   SCCR_DFNL000  |     \
-                        SCCR_DFNH000)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register         11-27
- *-----------------------------------------------------------------------
- */
-/* +0x0220 => 0x00C3 */
-#define CONFIG_SYS_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration Register               19-4
- *-----------------------------------------------------------------------
- */
-/* +0x09C4 => TIMEP=1 */
-#define CONFIG_SYS_RCCR 0x0100
-
-/*-----------------------------------------------------------------------
- * RMDS - RISC Microcode Development Support Control Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMDS 0
-
-/*-----------------------------------------------------------------------
- * DER - Debug Event Register
- *-----------------------------------------------------------------------
- *
- */
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- */
-
-/*
- * MAMR settings for SDRAM     - 16-14
- * => 0xC3804114
- */
-
-/* periodic timer for refresh */
-#define CONFIG_SYS_MAMR_PTA    0xC3
-
-#define CONFIG_SYS_MAMR        ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-/*
- * BR1 and OR1 (FLASH)
- */
-#define FLASH_BASE             0x10000000      /* FLASH bank #0        */
-
-/* used to re-map FLASH
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-/* allow for max 8 MB of Flash */
-#define CONFIG_SYS_REMAP_OR_AM         0xFF800000      /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
-
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
-
-#define CONFIG_SYS_OR0_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-/* 16 bit, bank valid */
-#define CONFIG_SYS_BR0_PRELIM  ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
-
-#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_OR0_PRELIM
-#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_BR0_PRELIM
-
-/*
- * BR2/OR2 - SDRAM
- */
-#define SDRAM_BASE             0x00000000      /* SDRAM bank */
-#define SDRAM_PRELIM_OR_AM     0xF8000000      /* map max. 128 MB */
-#define SDRAM_TIMING           0x00000A00      /* SDRAM-Timing */
-
-#define SDRAM_MAX_SIZE         0x04000000      /* max 64 MB SDRAM */
-
-#define CONFIG_SYS_OR2         (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
-#define CONFIG_SYS_BR2         ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
-
-/*
- * BR3/OR3 - SRAM (16 bit)
- */
-#define        SRAM_BASE       0x20000000
-#define CONFIG_SYS_OR3         0xFFF00130              /* BI/SCY = 5/TRLX (internal) */
-#define CONFIG_SYS_BR3         ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-#define SRAM_SIZE      (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
-#define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_OR3                  /* Make sure to map early */
-#define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_BR3                  /* in case it's used for ENV */
-#define        CONFIG_SYS_SRAM_BASE    SRAM_BASE
-#define        CONFIG_SYS_SRAM_SIZE    SRAM_SIZE
-
-/*
- * BR4/OR4 - Board Control & Status (8 bit)
- */
-#define        BCSR_BASE       0xFC000000
-#define CONFIG_SYS_OR4         0xFFFF0120              /* BI (internal) */
-#define CONFIG_SYS_BR4         ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
-
-/*
- * BR5/OR5 - IP Slot A/B (16 bit)
- */
-#define        IP_SLOT_BASE    0x40000000
-#define CONFIG_SYS_OR5         0xFE00010C              /* SETA/TRLX/BI/ SCY=0 (external) */
-#define CONFIG_SYS_BR5         ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*
- * BR6/OR6 - VME STD  (16 bit)
- */
-#define        VME_STD_BASE    0xFE000000
-#define CONFIG_SYS_OR6         0xFF00010C              /* SETA/TRLX/BI/SCY=0  (external) */
-#define CONFIG_SYS_BR6         ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*
- * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
- */
-#define VME_SHORT_BASE 0xFF000000
-#define CONFIG_SYS_OR7         0xFF00010C              /* SETA/TRLX/BI/ SCY=0 (external) */
-#define CONFIG_SYS_BR7         ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
-
-/*-----------------------------------------------------------------------
- * Board Control and Status Region:
- *-----------------------------------------------------------------------
- */
-#ifndef __ASSEMBLY__
-typedef        struct ip860_bcsr_s {
-       unsigned char   shmem_addr;     /* +00 shared memory address register   */
-       unsigned char   reserved0;
-       unsigned char   mbox_addr;      /* +02 mailbox address register         */
-       unsigned char   reserved1;
-       unsigned char   vme_int_mask;   /* +04 VME Bus interrupt mask register  */
-       unsigned char   reserved2;
-       unsigned char   vme_int_pend;   /* +06 VME interrupt pending register   */
-       unsigned char   reserved3;
-       unsigned char   bd_int_mask;    /* +08 board interrupt mask register    */
-       unsigned char   reserved4;
-       unsigned char   bd_int_pend;    /* +0A board interrupt pending register */
-       unsigned char   reserved5;
-       unsigned char   bd_ctrl;        /* +0C board control register           */
-       unsigned char   reserved6;
-       unsigned char   bd_status;      /* +0E board status  register           */
-       unsigned char   reserved7;
-       unsigned char   vme_irq;        /* +10 VME interrupt request register   */
-       unsigned char   reserved8;
-       unsigned char   vme_ivec;       /* +12 VME interrupt vector register    */
-       unsigned char   reserved9;
-       unsigned char   cli_mbox;       /* +14 clear mailbox irq                */
-       unsigned char   reservedA;
-       unsigned char   rtc;            /* +16 RTC control register             */
-       unsigned char   reservedB;
-       unsigned char   mbox_data;      /* +18 mailbox read/write register      */
-       unsigned char   reservedC;
-       unsigned char   wd_trigger;     /* +1A Watchdog trigger register        */
-       unsigned char   reservedD;
-       unsigned char   rmw_req;        /* +1C RMW request register             */
-       unsigned char   reservedE;
-       unsigned char   bd_rev;         /* +1E Board Revision register          */
-} ip860_bcsr_t;
-#endif /* __ASSEMBLY__ */
-
-/*-----------------------------------------------------------------------
- * Board Control Register: bd_ctrl (Offset 0x0C)
- *-----------------------------------------------------------------------
- */
-#define BD_CTRL_IPLSE  0x80    /* IP Slot Long Select Enable           */
-#define BD_CTRL_WDOGE  0x40    /* Watchdog Enable                      */
-#define BD_CTRL_FLWE   0x20    /* Flash Write Enable                   */
-#define BD_CTRL_RWDN   0x10    /* VMEBus Requester Release When Done Enable */
-
-#endif /* __CONFIG_H */