#include <div64.h>
#include <netdev.h>
#include <asm/io.h>
+#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
bool
config MX6SX
+ select ROM_UNIFIED_SECTIONS
bool
config MX6UL
select SYS_L2CACHE_OFF
+ select ROM_UNIFIED_SECTIONS
bool
choice
obj-y := soc.o clock.o
obj-$(CONFIG_SPL_BUILD) += ddr.o
-obj-$(CONFIG_SECURE_BOOT) += hab.o
obj-$(CONFIG_MP) += mp.o
+++ /dev/null
-/*
- * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/system.h>
-#include <asm/arch/hab.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-
-/* -------- start of HAB API updates ------------*/
-
-#define hab_rvt_report_event_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
- ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
-)
-
-#define hab_rvt_report_status_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
- ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
-)
-
-#define hab_rvt_authenticate_image_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
-)
-
-#define hab_rvt_entry_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
- ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
-)
-
-#define hab_rvt_exit_p \
-( \
- ((is_cpu_type(MXC_CPU_MX6Q) || \
- is_cpu_type(MXC_CPU_MX6D)) && \
- (soc_rev() >= CHIP_REV_1_5)) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- (is_cpu_type(MXC_CPU_MX6DL) && \
- (soc_rev() >= CHIP_REV_1_2)) ? \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
- ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
-)
-
-#define IVT_SIZE 0x20
-#define ALIGN_SIZE 0x1000
-#define CSF_PAD_SIZE 0x2000
-#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
-#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
-#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
-
-/*
- * +------------+ 0x0 (DDR_UIMAGE_START) -
- * | Header | |
- * +------------+ 0x40 |
- * | | |
- * | | |
- * | | |
- * | | |
- * | Image Data | |
- * . | |
- * . | > Stuff to be authenticated ----+
- * . | | |
- * | | | |
- * | | | |
- * +------------+ | |
- * | | | |
- * | Fill Data | | |
- * | | | |
- * +------------+ Align to ALIGN_SIZE | |
- * | IVT | | |
- * +------------+ + IVT_SIZE - |
- * | | |
- * | CSF DATA | <---------------------------------------------------------+
- * | |
- * +------------+
- * | |
- * | Fill Data |
- * | |
- * +------------+ + CSF_PAD_SIZE
- */
-
-#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
-
-struct record {
- uint8_t tag; /* Tag */
- uint8_t len[2]; /* Length */
- uint8_t par; /* Version */
- uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
- bool any_rec_flag;
-};
-
-char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
- "RSN = HAB_ENG_FAIL (0x30)\n",
- "RSN = HAB_INV_ADDRESS (0x22)\n",
- "RSN = HAB_INV_ASSERTION (0x0C)\n",
- "RSN = HAB_INV_CALL (0x28)\n",
- "RSN = HAB_INV_CERTIFICATE (0x21)\n",
- "RSN = HAB_INV_COMMAND (0x06)\n",
- "RSN = HAB_INV_CSF (0x11)\n",
- "RSN = HAB_INV_DCD (0x27)\n",
- "RSN = HAB_INV_INDEX (0x0F)\n",
- "RSN = HAB_INV_IVT (0x05)\n",
- "RSN = HAB_INV_KEY (0x1D)\n",
- "RSN = HAB_INV_RETURN (0x1E)\n",
- "RSN = HAB_INV_SIGNATURE (0x18)\n",
- "RSN = HAB_INV_SIZE (0x17)\n",
- "RSN = HAB_MEM_FAIL (0x2E)\n",
- "RSN = HAB_OVR_COUNT (0x2B)\n",
- "RSN = HAB_OVR_STORAGE (0x2D)\n",
- "RSN = HAB_UNS_ALGORITHM (0x12)\n",
- "RSN = HAB_UNS_COMMAND (0x03)\n",
- "RSN = HAB_UNS_ENGINE (0x0A)\n",
- "RSN = HAB_UNS_ITEM (0x24)\n",
- "RSN = HAB_UNS_KEY (0x1B)\n",
- "RSN = HAB_UNS_PROTOCOL (0x14)\n",
- "RSN = HAB_UNS_STATE (0x09)\n",
- "RSN = INVALID\n",
- NULL};
-
-char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
- "STS = HAB_FAILURE (0x33)\n",
- "STS = HAB_WARNING (0x69)\n",
- "STS = INVALID\n",
- NULL};
-
-char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
- "ENG = HAB_ENG_SCC (0x03)\n",
- "ENG = HAB_ENG_RTIC (0x05)\n",
- "ENG = HAB_ENG_SAHARA (0x06)\n",
- "ENG = HAB_ENG_CSU (0x0A)\n",
- "ENG = HAB_ENG_SRTC (0x0C)\n",
- "ENG = HAB_ENG_DCP (0x1B)\n",
- "ENG = HAB_ENG_CAAM (0x1D)\n",
- "ENG = HAB_ENG_SNVS (0x1E)\n",
- "ENG = HAB_ENG_OCOTP (0x21)\n",
- "ENG = HAB_ENG_DTCP (0x22)\n",
- "ENG = HAB_ENG_ROM (0x36)\n",
- "ENG = HAB_ENG_HDCP (0x24)\n",
- "ENG = HAB_ENG_RTL (0x77)\n",
- "ENG = HAB_ENG_SW (0xFF)\n",
- "ENG = INVALID\n",
- NULL};
-
-char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
- "CTX = HAB_CTX_FAB (0xFF)\n",
- "CTX = HAB_CTX_ENTRY (0xE1)\n",
- "CTX = HAB_CTX_TARGET (0x33)\n",
- "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
- "CTX = HAB_CTX_DCD (0xDD)\n",
- "CTX = HAB_CTX_CSF (0xCF)\n",
- "CTX = HAB_CTX_COMMAND (0xC0)\n",
- "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
- "CTX = HAB_CTX_ASSERT (0xA0)\n",
- "CTX = HAB_CTX_EXIT (0xEE)\n",
- "CTX = INVALID\n",
- NULL};
-
-uint8_t hab_statuses[5] = {
- HAB_STS_ANY,
- HAB_FAILURE,
- HAB_WARNING,
- HAB_SUCCESS,
- -1
-};
-
-uint8_t hab_reasons[26] = {
- HAB_RSN_ANY,
- HAB_ENG_FAIL,
- HAB_INV_ADDRESS,
- HAB_INV_ASSERTION,
- HAB_INV_CALL,
- HAB_INV_CERTIFICATE,
- HAB_INV_COMMAND,
- HAB_INV_CSF,
- HAB_INV_DCD,
- HAB_INV_INDEX,
- HAB_INV_IVT,
- HAB_INV_KEY,
- HAB_INV_RETURN,
- HAB_INV_SIGNATURE,
- HAB_INV_SIZE,
- HAB_MEM_FAIL,
- HAB_OVR_COUNT,
- HAB_OVR_STORAGE,
- HAB_UNS_ALGORITHM,
- HAB_UNS_COMMAND,
- HAB_UNS_ENGINE,
- HAB_UNS_ITEM,
- HAB_UNS_KEY,
- HAB_UNS_PROTOCOL,
- HAB_UNS_STATE,
- -1
-};
-
-uint8_t hab_contexts[12] = {
- HAB_CTX_ANY,
- HAB_CTX_FAB,
- HAB_CTX_ENTRY,
- HAB_CTX_TARGET,
- HAB_CTX_AUTHENTICATE,
- HAB_CTX_DCD,
- HAB_CTX_CSF,
- HAB_CTX_COMMAND,
- HAB_CTX_AUT_DAT,
- HAB_CTX_ASSERT,
- HAB_CTX_EXIT,
- -1
-};
-
-uint8_t hab_engines[16] = {
- HAB_ENG_ANY,
- HAB_ENG_SCC,
- HAB_ENG_RTIC,
- HAB_ENG_SAHARA,
- HAB_ENG_CSU,
- HAB_ENG_SRTC,
- HAB_ENG_DCP,
- HAB_ENG_CAAM,
- HAB_ENG_SNVS,
- HAB_ENG_OCOTP,
- HAB_ENG_DTCP,
- HAB_ENG_ROM,
- HAB_ENG_HDCP,
- HAB_ENG_RTL,
- HAB_ENG_SW,
- -1
-};
-
-bool is_hab_enabled(void)
-{
- struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- struct fuse_bank *bank = &ocotp->bank[0];
- struct fuse_bank0_regs *fuse =
- (struct fuse_bank0_regs *)bank->fuse_regs;
- uint32_t reg = readl(&fuse->cfg5);
-
- return (reg & 0x2) == 0x2;
-}
-
-static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
-{
- uint8_t idx = 0;
- uint8_t element = list[idx];
- while (element != -1) {
- if (element == tgt)
- return idx;
- element = list[++idx];
- }
- return -1;
-}
-
-void process_event_record(uint8_t *event_data, size_t bytes)
-{
- struct record *rec = (struct record *)event_data;
-
- printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
- printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
- printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
- printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
-}
-
-void display_event(uint8_t *event_data, size_t bytes)
-{
- uint32_t i;
-
- if (!(event_data && bytes > 0))
- return;
-
- for (i = 0; i < bytes; i++) {
- if (i == 0)
- printf("\t0x%02x", event_data[i]);
- else if ((i % 8) == 0)
- printf("\n\t0x%02x", event_data[i]);
- else
- printf(" 0x%02x", event_data[i]);
- }
-
- process_event_record(event_data, bytes);
-}
-
-int get_hab_status(void)
-{
- uint32_t index = 0; /* Loop index */
- uint8_t event_data[128]; /* Event data buffer */
- size_t bytes = sizeof(event_data); /* Event size in bytes */
- enum hab_config config = 0;
- enum hab_state state = 0;
- hab_rvt_report_event_t *hab_rvt_report_event;
- hab_rvt_report_status_t *hab_rvt_report_status;
-
- hab_rvt_report_event = hab_rvt_report_event_p;
- hab_rvt_report_status = hab_rvt_report_status_p;
-
- if (is_hab_enabled())
- puts("\nSecure boot enabled\n");
- else
- puts("\nSecure boot disabled\n");
-
- /* Check HAB status */
- if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
- printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
- config, state);
-
- /* Display HAB Error events */
- while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
- &bytes) == HAB_SUCCESS) {
- puts("\n");
- printf("--------- HAB Event %d -----------------\n",
- index + 1);
- puts("event data:\n");
- display_event(event_data, bytes);
- puts("\n");
- bytes = sizeof(event_data);
- index++;
- }
- }
- /* Display message if no HAB events are found */
- else {
- printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
- config, state);
- puts("No HAB Events Found!\n\n");
- }
- return 0;
-}
-
-uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
-{
- uint32_t load_addr = 0;
- size_t bytes;
- ptrdiff_t ivt_offset = 0;
- int result = 0;
- ulong start;
- hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
- hab_rvt_entry_t *hab_rvt_entry;
- hab_rvt_exit_t *hab_rvt_exit;
-
- hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
- hab_rvt_entry = hab_rvt_entry_p;
- hab_rvt_exit = hab_rvt_exit_p;
-
- if (is_hab_enabled()) {
- printf("\nAuthenticate image from DDR location 0x%x...\n",
- ddr_start);
-
- hab_caam_clock_enable(1);
-
- if (hab_rvt_entry() == HAB_SUCCESS) {
- /* If not already aligned, Align to ALIGN_SIZE */
- ivt_offset = (image_size + ALIGN_SIZE - 1) &
- ~(ALIGN_SIZE - 1);
-
- start = ddr_start;
- bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
-#ifdef DEBUG
- printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
- ivt_offset, ddr_start + ivt_offset);
- puts("Dumping IVT\n");
- print_buffer(ddr_start + ivt_offset,
- (void *)(ddr_start + ivt_offset),
- 4, 0x8, 0);
-
- puts("Dumping CSF Header\n");
- print_buffer(ddr_start + ivt_offset+IVT_SIZE,
- (void *)(ddr_start + ivt_offset+IVT_SIZE),
- 4, 0x10, 0);
-
- get_hab_status();
-
- puts("\nCalling authenticate_image in ROM\n");
- printf("\tivt_offset = 0x%x\n", ivt_offset);
- printf("\tstart = 0x%08lx\n", start);
- printf("\tbytes = 0x%x\n", bytes);
-#endif
- /*
- * If the MMU is enabled, we have to notify the ROM
- * code, or it won't flush the caches when needed.
- * This is done, by setting the "pu_irom_mmu_enabled"
- * word to 1. You can find its address by looking in
- * the ROM map. This is critical for
- * authenticate_image(). If MMU is enabled, without
- * setting this bit, authentication will fail and may
- * crash.
- */
- /* Check MMU enabled */
- if (get_cr() & CR_M) {
- if (is_cpu_type(MXC_CPU_MX6Q) ||
- is_cpu_type(MXC_CPU_MX6D)) {
- /*
- * This won't work on Rev 1.0.0 of
- * i.MX6Q/D, since their ROM doesn't
- * do cache flushes. don't think any
- * exist, so we ignore them.
- */
- if (!is_mx6dqp())
- writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6DL) ||
- is_cpu_type(MXC_CPU_MX6SOLO)) {
- writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
- } else if (is_cpu_type(MXC_CPU_MX6SL)) {
- writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
- }
- }
-
- load_addr = (uint32_t)hab_rvt_authenticate_image(
- HAB_CID_UBOOT,
- ivt_offset, (void **)&start,
- (size_t *)&bytes, NULL);
- if (hab_rvt_exit() != HAB_SUCCESS) {
- puts("hab exit function fail\n");
- load_addr = 0;
- }
- } else {
- puts("hab entry function fail\n");
- }
-
- hab_caam_clock_enable(0);
-
- get_hab_status();
- } else {
- puts("hab fuse not enabled\n");
- }
-
- if ((!is_hab_enabled()) || (load_addr != 0))
- result = 1;
-
- return result;
-}
-
-int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if ((argc != 1)) {
- cmd_usage(cmdtp);
- return 1;
- }
-
- get_hab_status();
-
- return 0;
-}
-
-static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- ulong addr, ivt_offset;
- int rcode = 0;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[1], NULL, 16);
- ivt_offset = simple_strtoul(argv[2], NULL, 16);
-
- rcode = authenticate_image(addr, ivt_offset);
-
- return rcode;
-}
-
-U_BOOT_CMD(
- hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
- "display HAB status",
- ""
- );
-
-U_BOOT_CMD(
- hab_auth_img, 3, 0, do_authenticate_image,
- "authenticate image via HAB",
- "addr ivt_offset\n"
- "addr - image hex address\n"
- "ivt_offset - hex offset of IVT in the image"
- );
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
+#include <asm/imx-common/hab.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
};
#endif
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 0,
+ .word = 6,
+};
+#endif
+
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
config MX7
bool
+ select ROM_UNIFIED_SECTIONS
default y
config MX7D
+ select ROM_UNIFIED_SECTIONS
bool
choice
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
+#include <asm/imx-common/hab.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>
};
#endif
+#if defined(CONFIG_SECURE_BOOT)
+struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
+ .bank = 1,
+ .word = 3,
+};
+#endif
+
/*
* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
* defines a 2-bit SPEED_GRADING
config IMX_CONFIG
string
+
+config ROM_UNIFIED_SECTIONS
+ bool
obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
+obj-$(CONFIG_SECURE_BOOT) += hab.o
endif
ifeq ($(SOC),$(filter $(SOC),vf610))
obj-y += ddrmc-vf610.o
--- /dev/null
+/*
+ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <fuse.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/hab.h>
+
+/* -------- start of HAB API updates ------------*/
+
+#define hab_rvt_report_event_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
+)
+
+#define hab_rvt_report_status_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
+)
+
+#define hab_rvt_authenticate_image_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
+)
+
+#define hab_rvt_entry_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
+)
+
+#define hab_rvt_exit_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
+)
+
+#define IVT_SIZE 0x20
+#define ALIGN_SIZE 0x1000
+#define CSF_PAD_SIZE 0x2000
+#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
+#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
+#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
+#define IS_HAB_ENABLED_BIT \
+ (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
+
+/*
+ * +------------+ 0x0 (DDR_UIMAGE_START) -
+ * | Header | |
+ * +------------+ 0x40 |
+ * | | |
+ * | | |
+ * | | |
+ * | | |
+ * | Image Data | |
+ * . | |
+ * . | > Stuff to be authenticated ----+
+ * . | | |
+ * | | | |
+ * | | | |
+ * +------------+ | |
+ * | | | |
+ * | Fill Data | | |
+ * | | | |
+ * +------------+ Align to ALIGN_SIZE | |
+ * | IVT | | |
+ * +------------+ + IVT_SIZE - |
+ * | | |
+ * | CSF DATA | <---------------------------------------------------------+
+ * | |
+ * +------------+
+ * | |
+ * | Fill Data |
+ * | |
+ * +------------+ + CSF_PAD_SIZE
+ */
+
+#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
+
+struct record {
+ uint8_t tag; /* Tag */
+ uint8_t len[2]; /* Length */
+ uint8_t par; /* Version */
+ uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
+ bool any_rec_flag;
+};
+
+char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
+ "RSN = HAB_ENG_FAIL (0x30)\n",
+ "RSN = HAB_INV_ADDRESS (0x22)\n",
+ "RSN = HAB_INV_ASSERTION (0x0C)\n",
+ "RSN = HAB_INV_CALL (0x28)\n",
+ "RSN = HAB_INV_CERTIFICATE (0x21)\n",
+ "RSN = HAB_INV_COMMAND (0x06)\n",
+ "RSN = HAB_INV_CSF (0x11)\n",
+ "RSN = HAB_INV_DCD (0x27)\n",
+ "RSN = HAB_INV_INDEX (0x0F)\n",
+ "RSN = HAB_INV_IVT (0x05)\n",
+ "RSN = HAB_INV_KEY (0x1D)\n",
+ "RSN = HAB_INV_RETURN (0x1E)\n",
+ "RSN = HAB_INV_SIGNATURE (0x18)\n",
+ "RSN = HAB_INV_SIZE (0x17)\n",
+ "RSN = HAB_MEM_FAIL (0x2E)\n",
+ "RSN = HAB_OVR_COUNT (0x2B)\n",
+ "RSN = HAB_OVR_STORAGE (0x2D)\n",
+ "RSN = HAB_UNS_ALGORITHM (0x12)\n",
+ "RSN = HAB_UNS_COMMAND (0x03)\n",
+ "RSN = HAB_UNS_ENGINE (0x0A)\n",
+ "RSN = HAB_UNS_ITEM (0x24)\n",
+ "RSN = HAB_UNS_KEY (0x1B)\n",
+ "RSN = HAB_UNS_PROTOCOL (0x14)\n",
+ "RSN = HAB_UNS_STATE (0x09)\n",
+ "RSN = INVALID\n",
+ NULL};
+
+char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
+ "STS = HAB_FAILURE (0x33)\n",
+ "STS = HAB_WARNING (0x69)\n",
+ "STS = INVALID\n",
+ NULL};
+
+char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
+ "ENG = HAB_ENG_SCC (0x03)\n",
+ "ENG = HAB_ENG_RTIC (0x05)\n",
+ "ENG = HAB_ENG_SAHARA (0x06)\n",
+ "ENG = HAB_ENG_CSU (0x0A)\n",
+ "ENG = HAB_ENG_SRTC (0x0C)\n",
+ "ENG = HAB_ENG_DCP (0x1B)\n",
+ "ENG = HAB_ENG_CAAM (0x1D)\n",
+ "ENG = HAB_ENG_SNVS (0x1E)\n",
+ "ENG = HAB_ENG_OCOTP (0x21)\n",
+ "ENG = HAB_ENG_DTCP (0x22)\n",
+ "ENG = HAB_ENG_ROM (0x36)\n",
+ "ENG = HAB_ENG_HDCP (0x24)\n",
+ "ENG = HAB_ENG_RTL (0x77)\n",
+ "ENG = HAB_ENG_SW (0xFF)\n",
+ "ENG = INVALID\n",
+ NULL};
+
+char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
+ "CTX = HAB_CTX_FAB (0xFF)\n",
+ "CTX = HAB_CTX_ENTRY (0xE1)\n",
+ "CTX = HAB_CTX_TARGET (0x33)\n",
+ "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
+ "CTX = HAB_CTX_DCD (0xDD)\n",
+ "CTX = HAB_CTX_CSF (0xCF)\n",
+ "CTX = HAB_CTX_COMMAND (0xC0)\n",
+ "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
+ "CTX = HAB_CTX_ASSERT (0xA0)\n",
+ "CTX = HAB_CTX_EXIT (0xEE)\n",
+ "CTX = INVALID\n",
+ NULL};
+
+uint8_t hab_statuses[5] = {
+ HAB_STS_ANY,
+ HAB_FAILURE,
+ HAB_WARNING,
+ HAB_SUCCESS,
+ -1
+};
+
+uint8_t hab_reasons[26] = {
+ HAB_RSN_ANY,
+ HAB_ENG_FAIL,
+ HAB_INV_ADDRESS,
+ HAB_INV_ASSERTION,
+ HAB_INV_CALL,
+ HAB_INV_CERTIFICATE,
+ HAB_INV_COMMAND,
+ HAB_INV_CSF,
+ HAB_INV_DCD,
+ HAB_INV_INDEX,
+ HAB_INV_IVT,
+ HAB_INV_KEY,
+ HAB_INV_RETURN,
+ HAB_INV_SIGNATURE,
+ HAB_INV_SIZE,
+ HAB_MEM_FAIL,
+ HAB_OVR_COUNT,
+ HAB_OVR_STORAGE,
+ HAB_UNS_ALGORITHM,
+ HAB_UNS_COMMAND,
+ HAB_UNS_ENGINE,
+ HAB_UNS_ITEM,
+ HAB_UNS_KEY,
+ HAB_UNS_PROTOCOL,
+ HAB_UNS_STATE,
+ -1
+};
+
+uint8_t hab_contexts[12] = {
+ HAB_CTX_ANY,
+ HAB_CTX_FAB,
+ HAB_CTX_ENTRY,
+ HAB_CTX_TARGET,
+ HAB_CTX_AUTHENTICATE,
+ HAB_CTX_DCD,
+ HAB_CTX_CSF,
+ HAB_CTX_COMMAND,
+ HAB_CTX_AUT_DAT,
+ HAB_CTX_ASSERT,
+ HAB_CTX_EXIT,
+ -1
+};
+
+uint8_t hab_engines[16] = {
+ HAB_ENG_ANY,
+ HAB_ENG_SCC,
+ HAB_ENG_RTIC,
+ HAB_ENG_SAHARA,
+ HAB_ENG_CSU,
+ HAB_ENG_SRTC,
+ HAB_ENG_DCP,
+ HAB_ENG_CAAM,
+ HAB_ENG_SNVS,
+ HAB_ENG_OCOTP,
+ HAB_ENG_DTCP,
+ HAB_ENG_ROM,
+ HAB_ENG_HDCP,
+ HAB_ENG_RTL,
+ HAB_ENG_SW,
+ -1
+};
+
+bool is_hab_enabled(void)
+{
+ struct imx_sec_config_fuse_t *fuse =
+ (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+ uint32_t reg;
+ int ret;
+
+ ret = fuse_read(fuse->bank, fuse->word, ®);
+ if (ret) {
+ puts("\nSecure boot fuse read error\n");
+ return ret;
+ }
+
+ return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
+}
+
+static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+{
+ uint8_t idx = 0;
+ uint8_t element = list[idx];
+ while (element != -1) {
+ if (element == tgt)
+ return idx;
+ element = list[++idx];
+ }
+ return -1;
+}
+
+void process_event_record(uint8_t *event_data, size_t bytes)
+{
+ struct record *rec = (struct record *)event_data;
+
+ printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
+ printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
+ printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
+ printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+}
+
+void display_event(uint8_t *event_data, size_t bytes)
+{
+ uint32_t i;
+
+ if (!(event_data && bytes > 0))
+ return;
+
+ for (i = 0; i < bytes; i++) {
+ if (i == 0)
+ printf("\t0x%02x", event_data[i]);
+ else if ((i % 8) == 0)
+ printf("\n\t0x%02x", event_data[i]);
+ else
+ printf(" 0x%02x", event_data[i]);
+ }
+
+ process_event_record(event_data, bytes);
+}
+
+int get_hab_status(void)
+{
+ uint32_t index = 0; /* Loop index */
+ uint8_t event_data[128]; /* Event data buffer */
+ size_t bytes = sizeof(event_data); /* Event size in bytes */
+ enum hab_config config = 0;
+ enum hab_state state = 0;
+ hab_rvt_report_event_t *hab_rvt_report_event;
+ hab_rvt_report_status_t *hab_rvt_report_status;
+
+ hab_rvt_report_event = hab_rvt_report_event_p;
+ hab_rvt_report_status = hab_rvt_report_status_p;
+
+ if (is_hab_enabled())
+ puts("\nSecure boot enabled\n");
+ else
+ puts("\nSecure boot disabled\n");
+
+ /* Check HAB status */
+ if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
+ printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+ config, state);
+
+ /* Display HAB Error events */
+ while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
+ &bytes) == HAB_SUCCESS) {
+ puts("\n");
+ printf("--------- HAB Event %d -----------------\n",
+ index + 1);
+ puts("event data:\n");
+ display_event(event_data, bytes);
+ puts("\n");
+ bytes = sizeof(event_data);
+ index++;
+ }
+ }
+ /* Display message if no HAB events are found */
+ else {
+ printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
+ config, state);
+ puts("No HAB Events Found!\n\n");
+ }
+ return 0;
+}
+
+uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
+{
+ uint32_t load_addr = 0;
+ size_t bytes;
+ ptrdiff_t ivt_offset = 0;
+ int result = 0;
+ ulong start;
+ hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
+ hab_rvt_entry_t *hab_rvt_entry;
+ hab_rvt_exit_t *hab_rvt_exit;
+
+ hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
+ hab_rvt_entry = hab_rvt_entry_p;
+ hab_rvt_exit = hab_rvt_exit_p;
+
+ if (is_hab_enabled()) {
+ printf("\nAuthenticate image from DDR location 0x%x...\n",
+ ddr_start);
+
+ hab_caam_clock_enable(1);
+
+ if (hab_rvt_entry() == HAB_SUCCESS) {
+ /* If not already aligned, Align to ALIGN_SIZE */
+ ivt_offset = (image_size + ALIGN_SIZE - 1) &
+ ~(ALIGN_SIZE - 1);
+
+ start = ddr_start;
+ bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
+#ifdef DEBUG
+ printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
+ ivt_offset, ddr_start + ivt_offset);
+ puts("Dumping IVT\n");
+ print_buffer(ddr_start + ivt_offset,
+ (void *)(ddr_start + ivt_offset),
+ 4, 0x8, 0);
+
+ puts("Dumping CSF Header\n");
+ print_buffer(ddr_start + ivt_offset+IVT_SIZE,
+ (void *)(ddr_start + ivt_offset+IVT_SIZE),
+ 4, 0x10, 0);
+
+ get_hab_status();
+
+ puts("\nCalling authenticate_image in ROM\n");
+ printf("\tivt_offset = 0x%x\n", ivt_offset);
+ printf("\tstart = 0x%08lx\n", start);
+ printf("\tbytes = 0x%x\n", bytes);
+#endif
+ /*
+ * If the MMU is enabled, we have to notify the ROM
+ * code, or it won't flush the caches when needed.
+ * This is done, by setting the "pu_irom_mmu_enabled"
+ * word to 1. You can find its address by looking in
+ * the ROM map. This is critical for
+ * authenticate_image(). If MMU is enabled, without
+ * setting this bit, authentication will fail and may
+ * crash.
+ */
+ /* Check MMU enabled */
+ if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
+ if (is_cpu_type(MXC_CPU_MX6Q) ||
+ is_cpu_type(MXC_CPU_MX6D)) {
+ /*
+ * This won't work on Rev 1.0.0 of
+ * i.MX6Q/D, since their ROM doesn't
+ * do cache flushes. don't think any
+ * exist, so we ignore them.
+ */
+ if (!is_mx6dqp())
+ writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+ } else if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO)) {
+ writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
+ } else if (is_cpu_type(MXC_CPU_MX6SL)) {
+ writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
+ }
+ }
+
+ load_addr = (uint32_t)hab_rvt_authenticate_image(
+ HAB_CID_UBOOT,
+ ivt_offset, (void **)&start,
+ (size_t *)&bytes, NULL);
+ if (hab_rvt_exit() != HAB_SUCCESS) {
+ puts("hab exit function fail\n");
+ load_addr = 0;
+ }
+ } else {
+ puts("hab entry function fail\n");
+ }
+
+ hab_caam_clock_enable(0);
+
+ get_hab_status();
+ } else {
+ puts("hab fuse not enabled\n");
+ }
+
+ if ((!is_hab_enabled()) || (load_addr != 0))
+ result = 1;
+
+ return result;
+}
+
+int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if ((argc != 1)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ get_hab_status();
+
+ return 0;
+}
+
+static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong addr, ivt_offset;
+ int rcode = 0;
+
+ if (argc < 3)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ ivt_offset = simple_strtoul(argv[2], NULL, 16);
+
+ rcode = authenticate_image(addr, ivt_offset);
+
+ return rcode;
+}
+
+U_BOOT_CMD(
+ hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
+ "display HAB status",
+ ""
+ );
+
+U_BOOT_CMD(
+ hab_auth_img, 3, 0, do_authenticate_image,
+ "authenticate image via HAB",
+ "addr ivt_offset\n"
+ "addr - image hex address\n"
+ "ivt_offset - hex offset of IVT in the image"
+ );
return MXC_CLK32;
#endif
}
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- ulong gpt_clk = gpt_get_clk();
-
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gpt_clk);
-
- return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long usec)
-{
- ulong gpt_clk = gpt_get_clk();
-
- usec = usec * gpt_clk + 999999;
- do_div(usec, 1000000);
-
- return usec;
-}
int timer_init(void)
{
return 0;
}
-unsigned long long get_ticks(void)
+unsigned long timer_read_counter(void)
{
- ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
- /*
- * get_ticks() returns a long long (64 bit), it wraps in
- * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
- * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
- * 5 * 10^6 days - long enough.
- */
- return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = us_to_tick(usec);
- tmp = get_ticks() + tmo; /* get current timestamp */
-
- while (get_ticks() < tmp) /* loop till event */
- /*NOP*/;
+ return __raw_readl(&cur_gpt->counter); /* current tick value */
}
/*
{
return gpt_get_clk();
}
-
-/*
- * This function is intended for SHORT delays only.
- * It will overflow at around 10 seconds @ 400MHz,
- * or 20 seconds @ 200MHz.
- */
-unsigned long usec2ticks(unsigned long usec)
-{
- ulong ticks;
-
- if (usec < 1000)
- ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
- else
- ticks = ((usec / 10) * (get_tbclk() / 100000));
-
- return ticks;
-}
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x25
+#define CHIP_REV_3_0 0x30
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+#define BOARD_VER_OFFSET 0x8
+
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
IMX_CSPI2_BASE, \
IMX_CSPI3_BASE
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_1_2 0x12
-
#endif /* _IMX_REGS_H */
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_5 0x25
-#define CHIP_REV_3_0 0x30
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#define BOARD_VER_OFFSET 0x8
-
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+++ /dev/null
-/*
- * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
-*/
-
-#ifndef __SECURE_MX6Q_H__
-#define __SECURE_MX6Q_H__
-
-#include <linux/types.h>
-
-/* -------- start of HAB API updates ------------*/
-/* The following are taken from HAB4 SIS */
-
-/* Status definitions */
-enum hab_status {
- HAB_STS_ANY = 0x00,
- HAB_FAILURE = 0x33,
- HAB_WARNING = 0x69,
- HAB_SUCCESS = 0xf0
-};
-
-/* Security Configuration definitions */
-enum hab_config {
- HAB_CFG_RETURN = 0x33, /* < Field Return IC */
- HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */
- HAB_CFG_CLOSED = 0xcc /* < Secure IC */
-};
-
-/* State definitions */
-enum hab_state {
- HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */
- HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */
- HAB_STATE_NONSECURE = 0x66, /* Non-secure state */
- HAB_STATE_TRUSTED = 0x99, /* Trusted state */
- HAB_STATE_SECURE = 0xaa, /* Secure state */
- HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
- HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
- HAB_STATE_NONE = 0xf0, /* No security state machine */
- HAB_STATE_MAX
-};
-
-enum hab_reason {
- HAB_RSN_ANY = 0x00, /* Match any reason */
- HAB_ENG_FAIL = 0x30, /* Engine failure */
- HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */
- HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */
- HAB_INV_CALL = 0x28, /* Function called out of sequence */
- HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
- HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */
- HAB_INV_CSF = 0x11, /* Invalid csf */
- HAB_INV_DCD = 0x27, /* Invalid dcd */
- HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */
- HAB_INV_IVT = 0x05, /* Invalid ivt */
- HAB_INV_KEY = 0x1d, /* Invalid key */
- HAB_INV_RETURN = 0x1e, /* Failed callback function */
- HAB_INV_SIGNATURE = 0x18, /* Invalid signature */
- HAB_INV_SIZE = 0x17, /* Invalid data size */
- HAB_MEM_FAIL = 0x2e, /* Memory failure */
- HAB_OVR_COUNT = 0x2b, /* Expired poll count */
- HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */
- HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
- HAB_UNS_COMMAND = 0x03, /* Unsupported command */
- HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */
- HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */
- HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
- HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
- HAB_UNS_STATE = 0x09, /* Unsuitable state */
- HAB_RSN_MAX
-};
-
-enum hab_context {
- HAB_CTX_ANY = 0x00, /* Match any context */
- HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */
- HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
- HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
- HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
- HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
- HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
- HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
- HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */
- HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
- HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
- HAB_CTX_MAX
-};
-
-/*Function prototype description*/
-typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
- uint8_t* , size_t*);
-typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
- enum hab_state *);
-typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
-typedef enum hab_status hab_rvt_entry_t(void);
-typedef enum hab_status hab_rvt_exit_t(void);
-typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
- void **, size_t *, hab_loader_callback_f_t);
-typedef void hapi_clock_init_t(void);
-
-#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
-#define HAB_ENG_SCC 0x03 /* Security controller */
-#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */
-#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */
-#define HAB_ENG_CSU 0x0a /* Central Security Unit */
-#define HAB_ENG_SRTC 0x0c /* Secure clock */
-#define HAB_ENG_DCP 0x1b /* Data Co-Processor */
-#define HAB_ENG_CAAM 0x1d /* CAAM */
-#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */
-#define HAB_ENG_OCOTP 0x21 /* Fuse controller */
-#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */
-#define HAB_ENG_ROM 0x36 /* Protected ROM area */
-#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */
-#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
-#define HAB_ENG_SW 0xff /* Software engine */
-
-#ifdef CONFIG_MX6SX
-#define HAB_RVT_BASE 0x00000100
-#else
-#define HAB_RVT_BASE 0x00000094
-#endif
-
-#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
-#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
-#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
-#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
-
-#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
-#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
-#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
-#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
-#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
-
-#define HAB_CID_ROM 0 /**< ROM Caller ID */
-#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
-
-/* ----------- end of HAB API updates ------------*/
-
-#endif
#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_2 0x12
-#define CHIP_REV_1_5 0x15
-#define CHIP_REV_2_0 0x20
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else
};
/* GPR1 bitfields */
+#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
+#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
+#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
+#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
+#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
+#define IOMUXC_GPR1_DPI_OFF BIT(24)
+#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
+#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
+#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
+#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
+#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
+#define IOMUXC_GPR1_PCIE_INT BIT(14)
#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+#define IOMUXC_GPR1_GINT BIT(12)
+#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
+#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
+#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
+#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
+#define IOMUXC_GPR1_ACT_CS3 BIT(9)
+#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
+#define IOMUXC_GPR1_ACT_CS2 BIT(6)
+#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
+#define IOMUXC_GPR1_ACT_CS1 BIT(3)
+#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
+#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
+#define IOMUXC_GPR1_ACT_CS0 BIT(0)
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+/* gpr12 bitfields */
+#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
+#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
+#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
+#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
+#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
+#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
struct iomuxc {
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
--- /dev/null
+/*
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+*/
+
+#ifndef __SECURE_MX6Q_H__
+#define __SECURE_MX6Q_H__
+
+#include <linux/types.h>
+
+/* -------- start of HAB API updates ------------*/
+/* The following are taken from HAB4 SIS */
+
+/* Status definitions */
+enum hab_status {
+ HAB_STS_ANY = 0x00,
+ HAB_FAILURE = 0x33,
+ HAB_WARNING = 0x69,
+ HAB_SUCCESS = 0xf0
+};
+
+/* Security Configuration definitions */
+enum hab_config {
+ HAB_CFG_RETURN = 0x33, /* < Field Return IC */
+ HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */
+ HAB_CFG_CLOSED = 0xcc /* < Secure IC */
+};
+
+/* State definitions */
+enum hab_state {
+ HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */
+ HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */
+ HAB_STATE_NONSECURE = 0x66, /* Non-secure state */
+ HAB_STATE_TRUSTED = 0x99, /* Trusted state */
+ HAB_STATE_SECURE = 0xaa, /* Secure state */
+ HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */
+ HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */
+ HAB_STATE_NONE = 0xf0, /* No security state machine */
+ HAB_STATE_MAX
+};
+
+enum hab_reason {
+ HAB_RSN_ANY = 0x00, /* Match any reason */
+ HAB_ENG_FAIL = 0x30, /* Engine failure */
+ HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */
+ HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */
+ HAB_INV_CALL = 0x28, /* Function called out of sequence */
+ HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */
+ HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */
+ HAB_INV_CSF = 0x11, /* Invalid csf */
+ HAB_INV_DCD = 0x27, /* Invalid dcd */
+ HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */
+ HAB_INV_IVT = 0x05, /* Invalid ivt */
+ HAB_INV_KEY = 0x1d, /* Invalid key */
+ HAB_INV_RETURN = 0x1e, /* Failed callback function */
+ HAB_INV_SIGNATURE = 0x18, /* Invalid signature */
+ HAB_INV_SIZE = 0x17, /* Invalid data size */
+ HAB_MEM_FAIL = 0x2e, /* Memory failure */
+ HAB_OVR_COUNT = 0x2b, /* Expired poll count */
+ HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */
+ HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */
+ HAB_UNS_COMMAND = 0x03, /* Unsupported command */
+ HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */
+ HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */
+ HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */
+ HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */
+ HAB_UNS_STATE = 0x09, /* Unsuitable state */
+ HAB_RSN_MAX
+};
+
+enum hab_context {
+ HAB_CTX_ANY = 0x00, /* Match any context */
+ HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */
+ HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */
+ HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */
+ HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */
+ HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */
+ HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */
+ HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */
+ HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */
+ HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */
+ HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */
+ HAB_CTX_MAX
+};
+
+struct imx_sec_config_fuse_t {
+ int bank;
+ int word;
+};
+
+#if defined(CONFIG_SECURE_BOOT)
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#endif
+
+/*Function prototype description*/
+typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
+ uint8_t* , size_t*);
+typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
+ enum hab_state *);
+typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
+typedef enum hab_status hab_rvt_entry_t(void);
+typedef enum hab_status hab_rvt_exit_t(void);
+typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
+ void **, size_t *, hab_loader_callback_f_t);
+typedef void hapi_clock_init_t(void);
+
+#define HAB_ENG_ANY 0x00 /* Select first compatible engine */
+#define HAB_ENG_SCC 0x03 /* Security controller */
+#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */
+#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */
+#define HAB_ENG_CSU 0x0a /* Central Security Unit */
+#define HAB_ENG_SRTC 0x0c /* Secure clock */
+#define HAB_ENG_DCP 0x1b /* Data Co-Processor */
+#define HAB_ENG_CAAM 0x1d /* CAAM */
+#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */
+#define HAB_ENG_OCOTP 0x21 /* Fuse controller */
+#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */
+#define HAB_ENG_ROM 0x36 /* Protected ROM area */
+#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */
+#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
+#define HAB_ENG_SW 0xff /* Software engine */
+
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define HAB_RVT_BASE 0x00000100
+#else
+#define HAB_RVT_BASE 0x00000094
+#endif
+
+#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
+
+#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
+#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
+#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
+#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
+
+#define HAB_CID_ROM 0 /**< ROM Caller ID */
+#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
+
+/* ----------- end of HAB API updates ------------*/
+
+#endif
imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
}
+static void set_gpr_register(void)
+{
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
+ IOMUXC_GPR1_EXC_MON_SLVE |
+ (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
+ IOMUXC_GPR1_ACT_CS0,
+ &iomuxc_regs->gpr[1]);
+ writel(0x0, &iomuxc_regs->gpr[8]);
+ writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
+ IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
+ &iomuxc_regs->gpr[12]);
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
gpio_direction_output(SOFT_RESET_GPIO, 1);
gpio_direction_output(SD2_DRIVER_ENABLE, 1);
setup_display();
+ set_gpr_register();
return 0;
}
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
setenv("board_name", "SABRESD");
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ if (is_mx6dqp())
+ setenv("board_rev", "MX6QP");
+ else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
setenv("board_rev", "MX6Q");
else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
setenv("board_rev", "MX6DL");
.dram_dqm7 = 0x00020030,
};
+const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00000030,
+ .dram_sdclk_1 = 0x00000030,
+ .dram_cas = 0x00000030,
+ .dram_ras = 0x00000030,
+ .dram_reset = 0x00000030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+ .dram_dqm0 = 0x00000030,
+ .dram_dqm1 = 0x00000030,
+ .dram_dqm2 = 0x00000030,
+ .dram_dqm3 = 0x00000030,
+ .dram_dqm4 = 0x00000030,
+ .dram_dqm5 = 0x00000030,
+ .dram_dqm6 = 0x00000030,
+ .dram_dqm7 = 0x00000030,
+};
+
const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
.grp_ddr_type = 0x000C0000,
.grp_ddrmode_ctl = 0x00020000,
.p1_mpwrdlctl = 0x48254A36,
};
+const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x001B001E,
+ .p0_mpwldectrl1 = 0x002E0029,
+ .p1_mpwldectrl0 = 0x001B002A,
+ .p1_mpwldectrl1 = 0x0019002C,
+ .p0_mpdgctrl0 = 0x43240334,
+ .p0_mpdgctrl1 = 0x0324031A,
+ .p1_mpdgctrl0 = 0x43340344,
+ .p1_mpdgctrl1 = 0x03280276,
+ .p0_mprddlctl = 0x44383A3E,
+ .p1_mprddlctl = 0x3C3C3846,
+ .p0_mpwrdlctl = 0x2E303230,
+ .p1_mpwrdlctl = 0x38283E34,
+};
+
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
- /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
- writel(0x007F007F, &iomux->gpr[6]);
- writel(0x007F007F, &iomux->gpr[7]);
+ if (is_mx6dqp()) {
+ /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ } else {
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ }
}
/*
.ddr_type = DDR_TYPE_DDR3,
};
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ if (is_mx6dqp()) {
+ mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
+ } else {
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ }
}
void board_init_f(ulong dummy)
BOOT_FROM sd
+/*
+ * Secure boot support
+ */
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
/*
* Device Configuration Data (DCD)
*
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
+config MXC_OCOTP
+ bool "Enable MXC OCOTP Driver"
+ help
+ If you say Y here, you will get support for the One Time
+ Programmable memory pages that are stored on the some
+ Freescale i.MX processors.
+
config PCA9551_LED
bool "Enable PCA9551 LED driver"
help
"else echo U-Boot not downloaded..exiting;fi\0" \
"bootcmd=run net_nfs\0"
+/* Enable FIT images support */
+#define CONFIG_CMD_FDT
+#define CONFIG_FIT
+
#endif /* __CONFIG_H */
"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
+ "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+ "setenv fdt_file imx6qp-sabresd.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
"setenv fdt_file imx6q-sabresd.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
-#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_ROM_UNIFIED_SECTIONS
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DBG_MONITOR
#define PHYS_SDRAM_SIZE SZ_1G
+/* Uncomment to enable secure boot support */
+/* #define CONFIG_SECURE_BOOT */
+#define CONFIG_CSF_SIZE 0x4000
+
/* Network */
#define CONFIG_CMD_MII
#define CONFIG_FEC_MXC
#define CONFIG_HW_WATCHDOG
+#define CONFIG_OF_LIBFDT
+
#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
/* text base address used when linking */
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