/* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE3_IO_BASE,
+                              CONFIG_SYS_PCIE3_IO_BUS,
                               CONFIG_SYS_PCIE3_IO_PHYS,
                               CONFIG_SYS_PCIE3_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_BUS,
                               CONFIG_SYS_PCIE1_IO_PHYS,
                               CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE2_IO_BASE,
+                              CONFIG_SYS_PCIE2_IO_BUS,
                               CONFIG_SYS_PCIE2_IO_PHYS,
                               CONFIG_SYS_PCIE2_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
 
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE3_IO_BASE,
+                              CONFIG_SYS_PCIE3_IO_BUS,
                               CONFIG_SYS_PCIE3_IO_PHYS,
                               CONFIG_SYS_PCIE3_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_BUS,
                               CONFIG_SYS_PCIE1_IO_PHYS,
                               CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE2_IO_BASE,
+                              CONFIG_SYS_PCIE2_IO_BUS,
                               CONFIG_SYS_PCIE2_IO_PHYS,
                               CONFIG_SYS_PCIE2_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
 
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_BUS,
                               CONFIG_SYS_PCIE1_IO_PHYS,
                               CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
 
 
                /* outbound io */
                pci_set_region(r++,
-                               CONFIG_SYS_PCI1_IO_BASE,
+                               CONFIG_SYS_PCI1_IO_BUS,
                                CONFIG_SYS_PCI1_IO_PHYS,
                                CONFIG_SYS_PCI1_IO_SIZE,
                                PCI_REGION_IO);
 
                /* outbound io */
                pci_set_region(r++,
-                               CONFIG_SYS_PCIE1_IO_BASE,
+                               CONFIG_SYS_PCIE1_IO_BUS,
                                CONFIG_SYS_PCIE1_IO_PHYS,
                                CONFIG_SYS_PCIE1_IO_SIZE,
                                PCI_REGION_IO);
 
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE3_IO_BASE,
+                                       CONFIG_SYS_PCIE3_IO_BUS,
                                        CONFIG_SYS_PCIE3_IO_PHYS,
                                        CONFIG_SYS_PCIE3_IO_SIZE,
                                        PCI_REGION_IO);
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE2_IO_BASE,
+                                       CONFIG_SYS_PCIE2_IO_BUS,
                                        CONFIG_SYS_PCIE2_IO_PHYS,
                                        CONFIG_SYS_PCIE2_IO_SIZE,
                                        PCI_REGION_IO);
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE1_IO_BASE,
+                                       CONFIG_SYS_PCIE1_IO_BUS,
                                        CONFIG_SYS_PCIE1_IO_PHYS,
                                        CONFIG_SYS_PCIE1_IO_SIZE,
                                        PCI_REGION_IO);
 
 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
 #endif
 
+#ifndef CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
+#endif
+
 #ifndef CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
 #endif
 
+#ifndef CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
+#endif
+
 static struct pci_controller *pci_hose;
 
 void
        pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
                        POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
 
-       pcix->potar2  = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
+       pcix->potar2  = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
        pcix->potear2  = 0x00000000;
        pcix->powbar2  = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
        pcix->powbear2 = 0x00000000;
                       PCI_REGION_MEM);
 
        pci_set_region(hose->regions + 1,
-                      CONFIG_SYS_PCI1_IO_BASE,
+                      CONFIG_SYS_PCI1_IO_BUS,
                       CONFIG_SYS_PCI1_IO_PHYS,
                       CONFIG_SYS_PCI1_IO_SIZE,
                       PCI_REGION_IO);
        pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
                        POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
 
-       pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
+       pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
        pcix2->potear2  = 0x00000000;
        pcix2->powbar2  = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
        pcix2->powbear2 = 0x00000000;
                       PCI_REGION_MEM);
 
        pci_set_region(hose->regions + 1,
-                      CONFIG_SYS_PCI2_IO_BASE,
+                      CONFIG_SYS_PCI2_IO_BUS,
                       CONFIG_SYS_PCI2_IO_PHYS,
                       CONFIG_SYS_PCI2_IO_SIZE,
                       PCI_REGION_IO);
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xffc00000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE1_MEM_BUS       0x90000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x08000000      /* 128M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x98000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x08000000      /* 128M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc20000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc30000
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif
 
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x100000        /* 1M */
 
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0xc0000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x00100000      /* 1M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00100000      /* 1M */
 #define CONFIG_SYS_PCIE3_MEM_BUS2      0xb0200000
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif
 
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2800000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
 #endif
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /*   1M */
 #endif
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
 
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
 
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00800000      /* 8M */
 
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
 
 
 #define CONFIG_SYS_PCIE3_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif