]> git.sur5r.net Git - u-boot/commitdiff
85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards
authorKumar Gala <galak@kernel.crashing.org>
Tue, 2 Dec 2008 22:08:37 +0000 (16:08 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Fri, 23 Jan 2009 23:03:13 +0000 (17:03 -0600)
Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
15 files changed:
board/freescale/mpc8536ds/mpc8536ds.c
board/freescale/mpc8544ds/mpc8544ds.c
board/freescale/mpc8548cds/mpc8548cds.c
board/freescale/mpc8568mds/mpc8568mds.c
board/freescale/mpc8572ds/mpc8572ds.c
cpu/mpc85xx/pci.c
include/configs/MPC8536DS.h
include/configs/MPC8540ADS.h
include/configs/MPC8541CDS.h
include/configs/MPC8544DS.h
include/configs/MPC8548CDS.h
include/configs/MPC8555CDS.h
include/configs/MPC8560ADS.h
include/configs/MPC8568MDS.h
include/configs/MPC8572DS.h

index 280ae1a317b3d59ef9f508d3ba6b609286f7f337..1e2e2dc13af661f0e46febd1a6eaf6fdb5276173 100644 (file)
@@ -199,7 +199,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE3_IO_BASE,
+                              CONFIG_SYS_PCIE3_IO_BUS,
                               CONFIG_SYS_PCIE3_IO_PHYS,
                               CONFIG_SYS_PCIE3_IO_SIZE,
                               PCI_REGION_IO);
@@ -254,7 +254,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_BUS,
                               CONFIG_SYS_PCIE1_IO_PHYS,
                               CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
@@ -317,7 +317,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE2_IO_BASE,
+                              CONFIG_SYS_PCIE2_IO_BUS,
                               CONFIG_SYS_PCIE2_IO_PHYS,
                               CONFIG_SYS_PCIE2_IO_SIZE,
                               PCI_REGION_IO);
@@ -385,7 +385,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
index c3bf60a46db2fed7beaf0d3844bf21805dcb4bfe..7ff5a9bb8327de09dd41f3ca47c942f8ec92c02e 100644 (file)
@@ -146,7 +146,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE3_IO_BASE,
+                              CONFIG_SYS_PCIE3_IO_BUS,
                               CONFIG_SYS_PCIE3_IO_PHYS,
                               CONFIG_SYS_PCIE3_IO_SIZE,
                               PCI_REGION_IO);
@@ -213,7 +213,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_BUS,
                               CONFIG_SYS_PCIE1_IO_PHYS,
                               CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
@@ -276,7 +276,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE2_IO_BASE,
+                              CONFIG_SYS_PCIE2_IO_BUS,
                               CONFIG_SYS_PCIE2_IO_PHYS,
                               CONFIG_SYS_PCIE2_IO_SIZE,
                               PCI_REGION_IO);
@@ -344,7 +344,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
index ff8d26fb9c60f9cea10ae9085a65b7aeaf9361d7..70320ea1a74d909e62dc765678e41ceecf3db74a 100644 (file)
@@ -313,7 +313,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCI1_IO_BASE,
+                              CONFIG_SYS_PCI1_IO_BUS,
                               CONFIG_SYS_PCI1_IO_PHYS,
                               CONFIG_SYS_PCI1_IO_SIZE,
                               PCI_REGION_IO);
@@ -397,7 +397,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                              CONFIG_SYS_PCIE1_IO_BASE,
+                              CONFIG_SYS_PCIE1_IO_BUS,
                               CONFIG_SYS_PCIE1_IO_PHYS,
                               CONFIG_SYS_PCIE1_IO_SIZE,
                               PCI_REGION_IO);
index 20f70fb520b8d219ed8867d800f7e1e13d532e05..915fae7fa401377b36142c06c10abd685c45765e 100644 (file)
@@ -404,7 +404,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                               CONFIG_SYS_PCI1_IO_BASE,
+                               CONFIG_SYS_PCI1_IO_BUS,
                                CONFIG_SYS_PCI1_IO_PHYS,
                                CONFIG_SYS_PCI1_IO_SIZE,
                                PCI_REGION_IO);
@@ -457,7 +457,7 @@ pci_init_board(void)
 
                /* outbound io */
                pci_set_region(r++,
-                               CONFIG_SYS_PCIE1_IO_BASE,
+                               CONFIG_SYS_PCIE1_IO_BUS,
                                CONFIG_SYS_PCIE1_IO_PHYS,
                                CONFIG_SYS_PCIE1_IO_SIZE,
                                PCI_REGION_IO);
index 01143ec89f854520548ec3ae76c48777506d67cb..5148d337da41ef37a319a59424cb8f7d67fa0f61 100644 (file)
@@ -192,7 +192,7 @@ void pci_init_board(void)
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE3_IO_BASE,
+                                       CONFIG_SYS_PCIE3_IO_BUS,
                                        CONFIG_SYS_PCIE3_IO_PHYS,
                                        CONFIG_SYS_PCIE3_IO_SIZE,
                                        PCI_REGION_IO);
@@ -259,7 +259,7 @@ void pci_init_board(void)
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE2_IO_BASE,
+                                       CONFIG_SYS_PCIE2_IO_BUS,
                                        CONFIG_SYS_PCIE2_IO_PHYS,
                                        CONFIG_SYS_PCIE2_IO_SIZE,
                                        PCI_REGION_IO);
@@ -314,7 +314,7 @@ void pci_init_board(void)
 
                        /* outbound io */
                        pci_set_region(r++,
-                                       CONFIG_SYS_PCIE1_IO_BASE,
+                                       CONFIG_SYS_PCIE1_IO_BUS,
                                        CONFIG_SYS_PCIE1_IO_PHYS,
                                        CONFIG_SYS_PCIE1_IO_SIZE,
                                        PCI_REGION_IO);
index 7a8184a50123f982722570081fdc58f40c19ca35..fedf1a54df69cbb6b77df5cd17105fac0d62c343 100644 (file)
 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
 #endif
 
+#ifndef CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
+#endif
+
 #ifndef CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
 #endif
 
+#ifndef CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
+#endif
+
 static struct pci_controller *pci_hose;
 
 void
@@ -95,7 +103,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
        pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
                        POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
 
-       pcix->potar2  = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
+       pcix->potar2  = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
        pcix->potear2  = 0x00000000;
        pcix->powbar2  = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
        pcix->powbear2 = 0x00000000;
@@ -119,7 +127,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
                       PCI_REGION_MEM);
 
        pci_set_region(hose->regions + 1,
-                      CONFIG_SYS_PCI1_IO_BASE,
+                      CONFIG_SYS_PCI1_IO_BUS,
                       CONFIG_SYS_PCI1_IO_PHYS,
                       CONFIG_SYS_PCI1_IO_SIZE,
                       PCI_REGION_IO);
@@ -180,7 +188,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
        pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
                        POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
 
-       pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
+       pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
        pcix2->potear2  = 0x00000000;
        pcix2->powbar2  = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
        pcix2->powbear2 = 0x00000000;
@@ -204,7 +212,7 @@ pci_mpc85xx_init(struct pci_controller *board_hose)
                       PCI_REGION_MEM);
 
        pci_set_region(hose->regions + 1,
-                      CONFIG_SYS_PCI2_IO_BASE,
+                      CONFIG_SYS_PCI2_IO_BUS,
                       CONFIG_SYS_PCI2_IO_PHYS,
                       CONFIG_SYS_PCI2_IO_SIZE,
                       PCI_REGION_IO);
index e280311a0f619d4ed32cab419bf3fec75506255a..b2a7d9ef03eb151c474a4f93111f58370b74d519 100644 (file)
@@ -360,7 +360,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xffc00000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
 
@@ -368,7 +368,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0x90000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x08000000      /* 128M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
@@ -376,7 +376,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x98000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x08000000      /* 128M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc20000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
@@ -384,7 +384,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc30000
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
@@ -424,8 +424,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif
 
index 2483d507e35902dc254273b76b68ae85b608680f..18e4105aea10098a97fd1cafc34123cc042ab042 100644 (file)
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
index 850384a9e6ff946271d9de39e4902bad9ccedf0b..03f6a6993c535387ae6d76b685513d0e62897ba7 100644 (file)
@@ -344,14 +344,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x100000        /* 1M */
 
index e31c65b0cc5f889906bea22b10a75f09c8030718..8d0d7848d189dc951695c9a9084c92b6f9d433ff 100644 (file)
@@ -269,7 +269,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCI1_MEM_BUS        0xc0000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64k */
 
@@ -277,7 +277,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe1010000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
@@ -285,7 +285,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe1020000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
@@ -293,7 +293,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x00100000      /* 1M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xb0100000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00100000      /* 1M */
 #define CONFIG_SYS_PCIE3_MEM_BUS2      0xb0200000
@@ -336,8 +336,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif
 
index 2477c48395d5edc63cb957fdfaf00297089a7592..d76e38cca4fa25de8412f9a6de80ce452506b82e 100644 (file)
@@ -370,7 +370,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
@@ -378,7 +378,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2800000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
 #endif
@@ -387,7 +387,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /*   1M */
 #endif
index 7c6e68a9b337ee9ba8b74e35e85f27290bc7af80..738fe52a5407cd0f016639c78156622fbe55f5c5 100644 (file)
@@ -342,14 +342,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 #define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2100000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
 
index 91512056d17844baa13311ee6f7974ffbf009450..0ef5acdf1c89f12637f652b4c63c63b7f9ec3516 100644 (file)
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x100000        /* 1M */
 
index 6cc0685ad42e9cb92eef089893a11137b565ea4d..8b067394e8362661ff2afb846968703f3c73f044 100644 (file)
@@ -325,14 +325,14 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
 #define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00800000      /* 8M */
 
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe2800000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000      /* 8M */
 
index 58b92acffedcde2a5fb4b1fe2429016d99ce3ad5..f665fecc725e0a85d0590b4dc5d6ad11ecc191dd 100644 (file)
@@ -383,7 +383,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE3_MEM_BUS       0x80000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      CONFIG_SYS_PCIE3_MEM_BUS
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE3_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE3_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
@@ -391,7 +391,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
@@ -399,7 +399,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
@@ -436,8 +436,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 
 #ifndef CONFIG_PCI_PNP
-       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BASE
-       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BASE
+       #define PCI_ENET0_IOADDR        CONFIG_SYS_PCIE3_IO_BUS
+       #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCIE3_IO_BUS
        #define PCI_IDSEL_NUMBER        0x11    /* IDSEL = AD11 */
 #endif