T: git git://git.denx.de/u-boot-atmel.git
F: arch/arm/mach-at91/
+ARM BROADCOM BCM283X
+M: Stephen Warren <swarren@wwwdotorg.org>
+S: Maintained
+F: arch/arm/mach-bcm283x/
+F: drivers/gpio/bcm2835_gpio.c
+F: drivers/mmc/bcm2835_sdhci.c
+F: drivers/serial/serial_bcm283x_mu.c
+F: drivers/video/bcm2835.c
+F: include/dm/platform_data/serial_bcm283x_mu.h
+
ARM FREESCALE IMX
M: Stefano Babic <sbabic@denx.de>
S: Maintained
The DIU driver will look for the 'video-mode' environment
variable, and if defined, enable the DIU as a console during
- boot. See the documentation file README.video for a
+ boot. See the documentation file doc/README.video for a
description of this variable.
- LCD Support: CONFIG_LCD
extra-y := start.o
-obj-y += cache_v7.o
+obj-y += cache_v7.o cache_v7_asm.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
#include <asm/armv7.h>
#include <asm/utils.h>
-#define ARMV7_DCACHE_INVAL_ALL 1
-#define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
-#define ARMV7_DCACHE_INVAL_RANGE 3
-#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
+#define ARMV7_DCACHE_INVAL_RANGE 1
+#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
#ifndef CONFIG_SYS_DCACHE_OFF
+
+/* Asm functions from cache_v7_asm.S */
+void v7_flush_dcache_all(void);
+void v7_invalidate_dcache_all(void);
+
static int check_cache_range(unsigned long start, unsigned long stop)
{
int ok = 1;
return ok;
}
-/*
- * Write the level and type you want to Cache Size Selection Register(CSSELR)
- * to get size details from Current Cache Size ID Register(CCSIDR)
- */
-static void set_csselr(u32 level, u32 type)
-{
- u32 csselr = level << 1 | type;
-
- /* Write to Cache Size Selection Register(CSSELR) */
- asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
-}
-
static u32 get_ccsidr(void)
{
u32 ccsidr;
return ccsidr;
}
-static u32 get_clidr(void)
-{
- u32 clidr;
-
- /* Read current CP15 Cache Level ID Register */
- asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
- return clidr;
-}
-
-static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /* Invalidate data/unified cache line by set/way */
- asm volatile (" mcr p15, 0, %0, c7, c6, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- DSB;
-}
-
-static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
- u32 num_ways, u32 way_shift,
- u32 log2_line_len)
-{
- int way, set;
- u32 setway;
-
- /*
- * For optimal assembly code:
- * a. count down
- * b. have bigger loop inside
- */
- for (way = num_ways - 1; way >= 0 ; way--) {
- for (set = num_sets - 1; set >= 0; set--) {
- setway = (level << 1) | (set << log2_line_len) |
- (way << way_shift);
- /*
- * Clean & Invalidate data/unified
- * cache line by set/way
- */
- asm volatile (" mcr p15, 0, %0, c7, c14, 2"
- : : "r" (setway));
- }
- }
- /* DSB to make sure the operation is complete */
- DSB;
-}
-
-static void v7_maint_dcache_level_setway(u32 level, u32 operation)
-{
- u32 ccsidr;
- u32 num_sets, num_ways, log2_line_len, log2_num_ways;
- u32 way_shift;
-
- set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
-
- ccsidr = get_ccsidr();
-
- log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
- CCSIDR_LINE_SIZE_OFFSET) + 2;
- /* Converting from words to bytes */
- log2_line_len += 2;
-
- num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
- CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
- num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
- CCSIDR_NUM_SETS_OFFSET) + 1;
- /*
- * According to ARMv7 ARM number of sets and number of ways need
- * not be a power of 2
- */
- log2_num_ways = log_2_n_round_up(num_ways);
-
- way_shift = (32 - log2_num_ways);
- if (operation == ARMV7_DCACHE_INVAL_ALL) {
- v7_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
- v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
- way_shift, log2_line_len);
- }
-}
-
-static void v7_maint_dcache_all(u32 operation)
-{
- u32 level, cache_type, level_start_bit = 0;
- u32 clidr = get_clidr();
-
- for (level = 0; level < 7; level++) {
- cache_type = (clidr >> level_start_bit) & 0x7;
- if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
- (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
- (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
- v7_maint_dcache_level_setway(level, operation);
- level_start_bit += 3;
- }
-}
-
static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
{
u32 mva;
void invalidate_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
+ v7_invalidate_dcache_all();
v7_outer_cache_inval_all();
}
*/
void flush_dcache_all(void)
{
- v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
+ v7_flush_dcache_all();
v7_outer_cache_flush_all();
}
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <linux/sizes.h>
+#include <asm/system.h>
+
+#ifdef CONFIG_SYS_THUMB_BUILD
+#define ARM(x...)
+#define THUMB(x...) x
+#else
+#define ARM(x...) x
+#define THUMB(x...)
+#endif
+
+/*
+ * v7_flush_dcache_all()
+ *
+ * Flush the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(__v7_flush_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq finished @ if loc is 0, then no need to clean
+start_flush_levels:
+ mov r10, #0 @ start clean at cache level 0
+flush_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+loop1:
+ mov r9, r7 @ create working copy of max index
+loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge loop2
+ subs r4, r4, #1 @ decrement the way
+ bge loop1
+skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt flush_levels
+finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_flush_dcache_all)
+
+ENTRY(v7_flush_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_flush_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_flush_dcache_all)
+
+/*
+ * v7_invalidate_dcache_all()
+ *
+ * Invalidate the whole D-cache.
+ *
+ * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ * Note: copied from __v7_flush_dcache_all above with
+ * mcr p15, 0, r11, c7, c14, 2
+ * Replaced with:
+ * mcr p15, 0, r11, c7, c6, 2
+ */
+ENTRY(__v7_invalidate_dcache_all)
+ dmb @ ensure ordering with previous memory accesses
+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
+ mov r3, r0, lsr #23 @ move LoC into position
+ ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
+ beq inval_finished @ if loc is 0, then no need to clean
+ mov r10, #0 @ start clean at cache level 0
+inval_levels:
+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
+ and r1, r1, #7 @ mask of the bits for current cache only
+ cmp r1, #2 @ see what cache we have at this level
+ blt inval_skip @ skip if no cache, or just i-cache
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ isb @ isb to sych the new cssr&csidr
+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
+ and r2, r1, #7 @ extract the length of the cache lines
+ add r2, r2, #4 @ add 4 (line length offset)
+ movw r4, #0x3ff
+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
+ clz r5, r4 @ find bit position of way size increment
+ movw r7, #0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+inval_loop1:
+ mov r9, r7 @ create working copy of max index
+inval_loop2:
+ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
+ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
+ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way
+ subs r9, r9, #1 @ decrement the index
+ bge inval_loop2
+ subs r4, r4, #1 @ decrement the way
+ bge inval_loop1
+inval_skip:
+ add r10, r10, #2 @ increment cache number
+ cmp r3, r10
+ bgt inval_levels
+inval_finished:
+ mov r10, #0 @ swith back to cache level 0
+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
+ dsb st
+ isb
+ bx lr
+ENDPROC(__v7_invalidate_dcache_all)
+
+ENTRY(v7_invalidate_dcache_all)
+ ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
+ bl __v7_invalidate_dcache_all
+ ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
+ THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
+ bx lr
+ENDPROC(v7_invalidate_dcache_all)
mov x29, lr /* Save LR */
#ifndef CONFIG_ARMV8_MULTIENTRY
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
/*
* For single-entry systems the lowlevel init is very simple.
*/
ldr x0, =GICD_BASE
bl gic_init_secure
-
+#endif
#else /* CONFIG_ARMV8_MULTIENTRY is set */
-
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
ldr x0, =GICD_BASE
#define BOOT_DEVICE_NAND_I2C 0x06
#define BOOT_DEVICE_MMC1 0x08
#define BOOT_DEVICE_MMC2 0x09
-#define BOOT_DEVICE_SPI 0x15
+#define BOOT_DEVICE_SPI 0x0B
#define BOOT_DEVICE_UART 0x41
#define BOOT_DEVICE_USBETH 0x44
#define BOOT_DEVICE_CPGMAC 0x46
config BCM2835
bool "Broadcom BCM2835 SoC support"
depends on ARCH_BCM283X
+ select CPU_ARM1176
config BCM2836
bool "Broadcom BCM2836 SoC support"
depends on ARCH_BCM283X
+ select ARMV7_LPAE
+ select CPU_V7
config BCM2837
bool "Broadcom BCM2837 SoC support"
depends on ARCH_BCM283X
+config BCM2837_32B
+ bool "Broadcom BCM2837 SoC 32-bit support"
+ depends on ARCH_BCM283X
+ select BCM2837
+ select ARMV7_LPAE
+ select CPU_V7
+
+config BCM2837_64B
+ bool "Broadcom BCM2837 SoC 64-bit support"
+ depends on ARCH_BCM283X
+ select BCM2837
+ select ARM64
+
menu "Broadcom BCM283X family"
depends on ARCH_BCM283X
This option creates a build targetting the ARM1176 ISA.
select BCM2835
- select CPU_ARM1176
config TARGET_RPI_2
bool "Raspberry Pi 2"
https://github.com/raspberrypi/firmware/issues/572".
This option creates a build targetting the ARMv7/AArch32 ISA.
- select ARMV7_LPAE
select BCM2836
- select CPU_V7
config TARGET_RPI_3_32B
bool "Raspberry Pi 3 32-bit build"
This option assumes the VideoCore firmware is configured to use the
mini UART (rather than PL011) for the serial console. This is the
default on the RPi 3. To enable the UART console, the following non-
- default option must be present in config.txt: enable_uart=1.
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
This option creates a build targetting the ARMv7/AArch32 ISA.
- select ARMV7_LPAE
- select BCM2837
- select CPU_V7
+ select BCM2837_32B
+
+config TARGET_RPI_3
+ bool "Raspberry Pi 3 64-bit build"
+ help
+ Support for all BCM2837-based Raspberry Pi variants, such as
+ the RPi 3 model B, in AArch64 (64-bit) mode.
+
+ This option assumes the VideoCore firmware is configured to use the
+ mini UART (rather than PL011) for the serial console. This is the
+ default on the RPi 3. To enable the UART console, the following non-
+ default option must be present in config.txt: enable_uart=1. This is
+ required for U-Boot to operate correctly, even if you only care
+ about the HDMI/usbkbd console.
+
+ At the time of writing, the VC FW requires a non-default option in
+ config.txt to request the ARM CPU boot in 64-bit mode:
+ arm_control=0x200
+
+ The VC FW typically provides ARM "stub" code to set up the CPU and
+ quiesce secondary SMP CPUs. This is not currently true in 64-bit
+ mode. In order to boot U-Boot before the VC FW is enhanced, please
+ see the commit description for the commit which added RPi3 support
+ for a workaround. Since the instructions are temporary, they are not
+ duplicated here. The VC FW enhancement is tracked in
+ https://github.com/raspberrypi/firmware/issues/579.
+
+ This option creates a build targetting the ARMv8/AArch64 ISA.
+ select BCM2837_64B
endchoice
config SYS_BOARD
- default "rpi" if TARGET_RPI
- default "rpi_2" if TARGET_RPI_2
- default "rpi_3_32b" if TARGET_RPI_3_32B
+ default "rpi"
config SYS_VENDOR
default "raspberrypi"
default "bcm283x"
config SYS_CONFIG_NAME
- default "rpi" if TARGET_RPI
- default "rpi_2" if TARGET_RPI_2
- default "rpi_3_32b" if TARGET_RPI_3_32B
+ default "rpi"
endmenu
# SPDX-License-Identifier: GPL-2.0
#
-obj-$(CONFIG_TARGET_RPI) += lowlevel_init.o
+obj-$(CONFIG_BCM2835) += lowlevel_init.o
obj-y += init.o reset.o mbox.o phys2bus.o
* to do next is to create a page table and switch over to it.
*/
bl create_page_table
- bl v7_flush_dcache_all
+ bl __v7_flush_dcache_all
/* Disable MMU and Dcache before switching Page Table */
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
str r0, [r12, #4] @ mark the second section as Normal
mov pc, lr
ENDPROC(create_page_table)
-
-/* We don't use Thumb instructions for now */
-#define ARM(x...) x
-#define THUMB(x...)
-
-/*
- * v7_flush_dcache_all()
- *
- * Flush the whole D-cache.
- *
- * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
- *
- * - mm - mm_struct describing address space
- *
- * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
- */
-ENTRY(v7_flush_dcache_all)
- dmb @ ensure ordering with previous memory accesses
- mrc p15, 1, r0, c0, c0, 1 @ read clidr
- mov r3, r0, lsr #23 @ move LoC into position
- ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
- beq finished @ if loc is 0, then no need to clean
-start_flush_levels:
- mov r10, #0 @ start clean at cache level 0
-flush_levels:
- add r2, r10, r10, lsr #1 @ work out 3x current cache level
- mov r1, r0, lsr r2 @ extract cache type bits from clidr
- and r1, r1, #7 @ mask of the bits for current cache only
- cmp r1, #2 @ see what cache we have at this level
- blt skip @ skip if no cache, or just i-cache
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- isb @ isb to sych the new cssr&csidr
- mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
- and r2, r1, #7 @ extract the length of the cache lines
- add r2, r2, #4 @ add 4 (line length offset)
- movw r4, #0x3ff
- ands r4, r4, r1, lsr #3 @ find maximum number on the way size
- clz r5, r4 @ find bit position of way size increment
- movw r7, #0x7fff
- ands r7, r7, r1, lsr #13 @ extract max number of the index size
-loop1:
- mov r9, r7 @ create working copy of max index
-loop2:
- ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
- THUMB( lsl r6, r4, r5 )
- THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
- ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
- THUMB( lsl r6, r9, r2 )
- THUMB( orr r11, r11, r6 ) @ factor index number into r11
- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
- subs r9, r9, #1 @ decrement the index
- bge loop2
- subs r4, r4, #1 @ decrement the way
- bge loop1
-skip:
- add r10, r10, #2 @ increment cache number
- cmp r3, r10
- bgt flush_levels
-finished:
- mov r10, #0 @ swith back to cache level 0
- mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
- dsb st
- isb
- mov pc, lr
-ENDPROC(v7_flush_dcache_all)
S: Maintained
F: board/raspberrypi/rpi/
F: include/configs/rpi.h
-F: configs/rpi_defconfig
+F: configs/rpi_*defconfig
#include <asm/global_data.h>
#include <dm/platform_data/serial_pl01x.h>
#include <dm/platform_data/serial_bcm283x_mu.h>
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
static uint32_t rev_type;
static const struct rpi_model *model;
+#ifdef CONFIG_ARM64
+static struct mm_region bcm2837_mem_map[] = {
+ {
+ .base = 0x00000000UL,
+ .size = 0x3f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x3f000000UL,
+ .size = 0x01000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm2837_mem_map;
+#endif
+
int dram_init(void)
{
ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1);
+++ /dev/null
-RPI_2 BOARD
-M: Stephen Warren <swarren@wwwdotorg.org>
-S: Maintained
-F: board/raspberrypi/rpi_2/
-F: include/configs/rpi_2.h
-F: configs/rpi_2_defconfig
+++ /dev/null
-#
-# (C) Copyright 2012,2015 Stephen Warren
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := ../rpi/rpi.o
+++ /dev/null
-RPI_3_32B BOARD
-M: Stephen Warren <swarren@wwwdotorg.org>
-S: Maintained
-F: board/raspberrypi/rpi_3_32b/
-F: include/configs/rpi_3_32b.h
-F: configs/rpi_3_32b_defconfig
+++ /dev/null
-#
-# (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
-#
-# SPDX-License-Identifier: GPL-2.0
-#
-
-obj-y := ../rpi/rpi.o
int board_late_init(void)
{
- init_sata(0);
setup_board_eeprom_env();
/*
struct block_cache_stats stats;
blkcache_stats(&stats);
- printf(" hits: %u\n"
- " misses: %u\n"
- " entries: %u\n"
- " max blocks/entry: %u\n"
- " max cache entries: %u\n",
+ printf("hits: %u\n"
+ "misses: %u\n"
+ "entries: %u\n"
+ "max blocks/entry: %u\n"
+ "max cache entries: %u\n",
stats.hits, stats.misses, stats.entries,
stats.max_blocks_per_entry, stats.max_entries);
return 0;
c = find_cmd_tbl(argv[0], &cmd_blkc_sub[0], ARRAY_SIZE(cmd_blkc_sub));
- if (c)
- return c->cmd(cmdtp, flag, argc, argv);
- else
+ if (!c)
return CMD_RET_USAGE;
- return 0;
+ return c->cmd(cmdtp, flag, argc, argv);
}
U_BOOT_CMD(
gd->env_valid = 1;
}
- if (gd->env_valid == 2)
- gd->env_addr = off_env[1] + offsetof(env_t, data);
- else if (gd->env_valid == 1)
- gd->env_addr = off_env[0] + offsetof(env_t, data);
-
#else /* CONFIG_ENV_OFFSET_REDUND */
ulong crc, len, new;
uchar rdbuf[64];
}
if (crc == new) {
- gd->env_addr = offsetof(env_t, data);
gd->env_valid = 1;
} else {
- gd->env_addr = 0;
gd->env_valid = 0;
}
#endif /* CONFIG_ENV_OFFSET_REDUND */
sparse_storage_t *storage,
sparse_header_t *sparse)
{
- return size * sparse->blk_sz / storage->block_sz;
+ return (unsigned int)lldiv((uint64_t)size * sparse->blk_sz,
+ storage->block_sz);
}
static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
static int mmc_load_image_raw_os(struct mmc *mmc)
{
unsigned long count;
+ int ret;
count = mmc->block_dev.block_read(&mmc->block_dev,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
return -1;
}
- return mmc_load_image_raw_sector(mmc,
+ ret = mmc_load_image_raw_sector(mmc,
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR);
+ if (ret)
+ return ret;
+
+ if (spl_image.os != IH_OS_LINUX) {
+ puts("Expected Linux image is not found. Trying to start U-boot\n");
+ return -ENOENT;
+ }
+
+ return 0;
}
#else
int spl_start_uboot(void)
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_BCM283X=y
+CONFIG_TARGET_RPI_3=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_PROMPT="U-Boot> "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_PHYS_TO_BUS=y
+CONFIG_OF_LIBFDT=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_GADGET=y
writel(patterns[i % NBR_OF_PATTERNS],
&save_addr[i + OFFS_PATTERN]);
+ /* Make sure the data is written to RAM */
+ flush_dcache_range((ulong)&save_addr[0],
+ (ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN]);
}
ulong bootcount_load(void)
/* To make things simple use byte writes only */
for (i = 0; i < cnt; i++) {
*(uchar *)(addr + i) = src[i];
+ /* avoid re-ordering flash data write and busy status
+ * check as flash memory space attributes are generally Normal
+ */
+ mb();
while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
;
}
};
struct sandbox_emul_gpio {
- struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END]; /* Fake registers */
+ /* Fake registers - need one more entry as REG_END is valid address. */
+ struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END + 1];
};
struct sandbox_spmi_priv {
rsk.struct_version = 2;
rsk.uid = ROLLBACK_SPACE_KERNEL_UID;
rsk.kernel_versions = 0;
- rsk.crc8 = crc8((unsigned char *)&rsk,
+ rsk.crc8 = crc8(0, (unsigned char *)&rsk,
offsetof(struct rollback_space_kernel,
crc8));
memcpy(data, &rsk, sizeof(rsk));
*
* @return - '1' if block returned from cache, '0' otherwise.
*/
-int blkcache_read
- (int iftype, int dev,
- lbaint_t start, lbaint_t blkcnt,
- unsigned long blksz, void *buffer);
+int blkcache_read(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void *buffer);
/**
* blkcache_fill() - make data read from a block device available
* @param buf - buffer containing data to cache
*
*/
-void blkcache_fill
- (int iftype, int dev,
- lbaint_t start, lbaint_t blkcnt,
- unsigned long blksz, void const *buffer);
+void blkcache_fill(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void const *buffer);
/**
* blkcache_invalidate() - discard the cache for a set of blocks
* @param iftype - IF_TYPE_x for type of device
* @param dev - device index of particular type
*/
-void blkcache_invalidate
- (int iftype, int dev);
+void blkcache_invalidate(int iftype, int dev);
/**
* blkcache_configure() - configure block cache
#else
-static inline int blkcache_read
- (int iftype, int dev,
- lbaint_t start, lbaint_t blkcnt,
- unsigned long blksz, void *buffer)
+static inline int blkcache_read(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void *buffer)
{
return 0;
}
-static inline void blkcache_fill
- (int iftype, int dev,
- lbaint_t start, lbaint_t blkcnt,
- unsigned long blksz, void const *buffer) {}
+static inline void blkcache_fill(int iftype, int dev,
+ lbaint_t start, lbaint_t blkcnt,
+ unsigned long blksz, void const *buffer) {}
-static inline void blkcache_invalidate
- (int iftype, int dev) {}
+static inline void blkcache_invalidate(int iftype, int dev) {}
#endif
+++ /dev/null
-/*
- * (C) Copyright 2012-2016 Stephen Warren
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _RPI_COMMON_H_
-#define _RPI_COMMON_H_
-
-#include <linux/sizes.h>
-#include <asm/arch/timer.h>
-
-/* Architecture, CPU, etc.*/
-#define CONFIG_ARCH_CPU_INIT
-
-#define CONFIG_SYS_TIMER_RATE 1000000
-#define CONFIG_SYS_TIMER_COUNTER \
- (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
-
-/*
- * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
- * so 2708 has historically been used rather than a dedicated 2835 ID.
- *
- * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
- * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
- * rather than obtaining a valid ID:-/
- *
- * For the bcm2837, hopefully a machine type is not needed, since everything
- * is DT.
- */
-#ifdef CONFIG_BCM2835
-#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
-#endif
-
-/* Memory layout */
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_TEXT_BASE 0x00008000
-#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
-/*
- * The board really has 256M. However, the VC (VideoCore co-processor) shares
- * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
- * smaller amount of RAM is present in order to avoid stomping on the area
- * the VC uses.
- */
-#define CONFIG_SYS_SDRAM_SIZE SZ_128M
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
- CONFIG_SYS_SDRAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MALLOC_LEN SZ_4M
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x00200000
-#define CONFIG_LOADADDR 0x00200000
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH
-
-/* Devices */
-/* GPIO */
-#define CONFIG_BCM2835_GPIO
-/* LCD */
-#define CONFIG_LCD
-#define CONFIG_LCD_DT_SIMPLEFB
-#define LCD_BPP LCD_COLOR16
-/*
- * Prevent allocation of RAM for FB; the real FB address is queried
- * dynamically from the VideoCore co-processor, and comes from RAM
- * not owned by the ARM CPU.
- */
-#define CONFIG_FB_ADDR 0
-#define CONFIG_VIDEO_BCM2835
-#define CONFIG_SYS_WHITE_ON_BLACK
-#define CONFIG_CONSOLE_SCROLL_LINES 10
-
-/* SD/MMC configuration */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_SDHCI
-#define CONFIG_MMC_SDHCI_IO_ACCESSORS
-#define CONFIG_BCM2835_SDHCI
-
-#define CONFIG_CMD_USB
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_DWC2
-#ifndef CONFIG_BCM2835
-#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
-#else
-#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
-#endif
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_MISC_INIT_R
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-#define CONFIG_SYS_STDIO_DEREGISTER
-#endif
-
-/* Console UART */
-#ifdef CONFIG_BCM2837
-#define CONFIG_BCM283X_MU_SERIAL
-#else
-#define CONFIG_PL01X_SERIAL
-#endif
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200
-
-/* Console configuration */
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Environment */
-#define CONFIG_ENV_SIZE SZ_16K
-#define CONFIG_ENV_IS_IN_FAT
-#define FAT_ENV_INTERFACE "mmc"
-#define FAT_ENV_DEVICE_AND_PART "0:1"
-#define FAT_ENV_FILE "uboot.env"
-#define CONFIG_FAT_WRITE
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_SYS_LOAD_ADDR 0x1000000
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_PREBOOT "usb start"
-
-/* Shell */
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_COMMAND_HISTORY
-
-/* Commands */
-#define CONFIG_CMD_MMC
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
-/* ATAGs support for bootm/bootz */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-#include <config_distro_defaults.h>
-
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define ENV_DEVICE_SETTINGS \
- "stdin=serial,usbkbd\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0"
-
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
- *
- * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
- * binary firmware loads a DT to address 0x100, so we choose this address to
- * match it. This allows custom boot scripts to pass this DT on to Linux
- * simply by not over-writing the data at this address. When using U-Boot,
- * U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
- * and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
- *
- * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
- * something else. Put it low in memory to avoid conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- * should not overlap that area, or the kernel will have to copy itself
- * somewhere else before decompression. Similarly, the address of any other
- * data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
- * compressed load address.
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- * else. Choosing 32M allows for the compressed kernel to be up to 16M.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- * for any boot script to be up to 1M, which is hopefully plenty.
- */
-#define ENV_MEM_LAYOUT_SETTINGS \
- "fdt_high=ffffffff\0" \
- "initrd_high=ffffffff\0" \
- "fdt_addr_r=0x00000100\0" \
- "pxefile_addr_r=0x00100000\0" \
- "kernel_addr_r=0x01000000\0" \
- "scriptaddr=0x02000000\0" \
- "ramdisk_addr_r=0x02100000\0" \
-
-#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- func(USB, usb, 0) \
- func(PXE, pxe, na) \
- func(DHCP, dhcp, na)
-#include <config_distro_bootcmd.h>
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- ENV_DEVICE_SETTINGS \
- ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV
-
-#define CONFIG_BOOTDELAY 2
-
-#endif
/*
- * (C) Copyright 2012,2015 Stephen Warren
+ * (C) Copyright 2012-2016 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
+#include <asm/arch/timer.h>
+
+#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifdef CONFIG_BCM2835
#define CONFIG_SYS_CACHELINE_SIZE 32
+#else
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#endif
+
+/* Architecture, CPU, etc.*/
+#define CONFIG_ARCH_CPU_INIT
+
+/* Use SoC timer for AArch32, but architected timer for AArch64 */
+#ifndef CONFIG_ARM64
+#define CONFIG_SYS_TIMER_RATE 1000000
+#define CONFIG_SYS_TIMER_COUNTER \
+ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo)
+#endif
+
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ *
+ * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation
+ * chose to use someone else's previously registered machine ID (3139, MX51_GGC)
+ * rather than obtaining a valid ID:-/
+ *
+ * For the bcm2837, hopefully a machine type is not needed, since everything
+ * is DT.
+ */
+#ifdef CONFIG_BCM2835
+#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708
+#endif
+
+/* Memory layout */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_TEXT_BASE 0x00008000
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+#define CONFIG_LOADADDR 0x00200000
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_LCD_DT_SIMPLEFB
+#define LCD_BPP LCD_COLOR16
+/*
+ * Prevent allocation of RAM for FB; the real FB address is queried
+ * dynamically from the VideoCore co-processor, and comes from RAM
+ * not owned by the ARM CPU.
+ */
+#define CONFIG_FB_ADDR 0
+#define CONFIG_VIDEO_BCM2835
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_BCM2835_SDHCI
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#ifndef CONFIG_BCM2835
+#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000
+#else
+#define CONFIG_USB_DWC2_REG_ADDR 0x20980000
+#endif
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MISC_INIT_R
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_STDIO_DEREGISTER
+#endif
+
+/* Console UART */
+#ifdef CONFIG_BCM2837
+#define CONFIG_BCM283X_MU_SERIAL
+#else
+#define CONFIG_PL01X_SERIAL
+#endif
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Environment */
+#define CONFIG_ENV_SIZE SZ_16K
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE "mmc"
+#define FAT_ENV_DEVICE_AND_PART "0:1"
+#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_FAT_WRITE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_SYS_LOAD_ADDR 0x1000000
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT "usb start"
+
+/* Shell */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_COMMAND_HISTORY
+
+/* Commands */
+#define CONFIG_CMD_MMC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#include <config_distro_defaults.h>
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define ENV_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,lcd\0" \
+ "stderr=serial,lcd\0"
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. However, the RPi's
+ * binary firmware loads a DT to address 0x100, so we choose this address to
+ * match it. This allows custom boot scripts to pass this DT on to Linux
+ * simply by not over-writing the data at this address. When using U-Boot,
+ * U-Boot (and scripts it executes) typicaly ignore the DT loaded by the FW
+ * and loads its own DT from disk (triggered by boot.scr or extlinux.conf).
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ * something else. Put it low in memory to avoid conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Choosing 32M allows for the compressed kernel to be up to 16M.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for any boot script to be up to 1M, which is hopefully plenty.
+ */
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "fdt_high=ffffffff\0" \
+ "initrd_high=ffffffff\0" \
+ "fdt_addr_r=0x00000100\0" \
+ "pxefile_addr_r=0x00100000\0" \
+ "kernel_addr_r=0x01000000\0" \
+ "scriptaddr=0x02000000\0" \
+ "ramdisk_addr_r=0x02100000\0" \
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(USB, usb, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
+ ENV_DEVICE_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
-#include "rpi-common.h"
+#define CONFIG_BOOTDELAY 2
#endif
+++ /dev/null
-/*
- * (C) Copyright 2012,2015 Stephen Warren
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#include "rpi-common.h"
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012-2016 Stephen Warren <swarren@wwwdotorg.org>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#include "rpi-common.h"
-
-#endif
* This uses an x^8 + x^2 + x + 1 polynomial. A table-based algorithm would
* be faster, but for only a few bytes it isn't worth the code size
*
+ * @crc_start: CRC8 start value
* @vptr: Buffer to checksum
* @len: Length of buffer in bytes
* @return CRC8 checksum
*/
-unsigned int crc8(const unsigned char *vptr, int len);
+unsigned int crc8(unsigned int crc_start, const unsigned char *vptr, int len);
#endif
*/
#ifdef CONFIG_SPL_BUILD
# define part_print_ptr(x) NULL
-# if defined(CONFIG_SPL_EXT_SUPPORT) || \
+# if defined(CONFIG_SPL_EXT_SUPPORT) || defined(CONFIG_SPL_FAT_SUPPORT) || \
defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
# define part_get_info_ptr(x) x
# else
#include "linux/crc8.h"
-unsigned int crc8(const unsigned char *vptr, int len)
+#define POLY (0x1070U << 3)
+
+static unsigned char _crc8(unsigned short data)
{
- const unsigned char *data = vptr;
- unsigned int crc = 0;
- int i, j;
-
- for (j = len; j; j--, data++) {
- crc ^= (*data << 8);
- for (i = 8; i; i--) {
- if (crc & 0x8000)
- crc ^= (0x1070 << 3);
- crc <<= 1;
- }
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (data & 0x8000)
+ data = data ^ POLY;
+ data = data << 1;
}
- return (crc >> 8) & 0xff;
+ return (unsigned char)(data >> 8);
+}
+
+unsigned int crc8(unsigned int crc, const unsigned char *vptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ crc = _crc8((crc ^ vptr[i]) << 8);
+
+ return crc;
}
avoid the need for `u-boot-test-flash` to actually write U-Boot to flash, thus
saving wear on the flash chip(s).
+#### Examples
+
+https://github.com/swarren/uboot-test-hooks contains some working example hook
+scripts, and may be useful as a reference when implementing hook scripts for
+your platform. These scripts are not considered part of U-Boot itself.
+
### Board-type-specific configuration
Each board has a different configuration and behaviour. Many of these
# may be omitted or set to None if TFTP testing is not possible or desired.
env__net_tftp_readable_file = {
"fn": "ubtest-readable.bin",
+ "addr": 0x10000000,
"size": 5058624,
"crc32": "c2244b26",
}
if not f:
pytest.skip('No TFTP readable file to read')
- addr = u_boot_utils.find_ram_base(u_boot_console)
+ addr = f.get('addr', None)
+ if not addr:
+ addr = u_boot_utils.find_ram_base(u_boot_console)
+
fn = f['fn']
output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn))
expected_text = 'Bytes transferred = '
cmd += ['gdbserver', self.config.gdbserver]
cmd += [
self.config.build_dir + '/u-boot',
+ '-v',
'-d',
self.config.build_dir + '/arch/sandbox/dts/test.dtb'
]
projects / u-boot / commitdiff